From b7751460e04a233589393fd4faccef5bc6e8e88b Mon Sep 17 00:00:00 2001 From: Jonathan Hui Date: Fri, 2 Apr 2021 18:50:37 -0700 Subject: [PATCH] [cc2650] remove example platform (#6398) --- configure.ac | 11 +- .../porting/set-up-the-build-environment.md | 5 +- examples/Makefile-cc2650 | 269 - examples/platforms/Makefile.am | 5 - examples/platforms/Makefile.platform.am | 4 - examples/platforms/cc2650/CMakeLists.txt | 96 - examples/platforms/cc2650/Makefile.am | 80 - .../platforms/cc2650/Makefile.platform.am | 44 - examples/platforms/cc2650/README.md | 119 - examples/platforms/cc2650/alarm.c | 122 - examples/platforms/cc2650/arm-none-eabi.cmake | 42 - examples/platforms/cc2650/cc2650_ccfg.c | 52 - examples/platforms/cc2650/cc2650_radio.h | 195 - examples/platforms/cc2650/cc2650_startup.c | 39 - examples/platforms/cc2650/crypto/aes_alt.c | 197 - examples/platforms/cc2650/crypto/aes_alt.h | 104 - .../cc2650/crypto/cc2650-mbedtls-config.h | 37 - examples/platforms/cc2650/crypto/sha256_alt.c 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third_party/ti/ti-openthread_1.01.0_manifest.html diff --git a/configure.ac b/configure.ac index 168579c6f..b94519f29 100644 --- a/configure.ac +++ b/configure.ac @@ -780,7 +780,7 @@ AC_MSG_CHECKING([whether to build examples]) AC_ARG_WITH(examples, [AS_HELP_STRING([--with-examples=TARGET], - [Build example applications for one of: simulation, cc2538, cc2650, efr32mg1, efr32mg12, efr32mg13, efr32mg21, + [Build example applications for one of: simulation, cc2538, efr32mg1, efr32mg12, efr32mg13, efr32mg21, jn5189, k32w061, nrf52811, nrf52833, nrf52840 @<:@default=no@:>@. Note that building example applications also builds the associated OpenThread platform libraries and any third_party libraries needed to support the examples.])], @@ -788,7 +788,7 @@ AC_ARG_WITH(examples, case "${with_examples}" in no) ;; - simulation|cc2538|cc2650|efr32mg1|efr32mg12|efr32mg13|efr32mg21|jn5189|k32w061|nrf52811|nrf52833|nrf52840) + simulation|cc2538|efr32mg1|efr32mg12|efr32mg13|efr32mg21|jn5189|k32w061|nrf52811|nrf52833|nrf52840) ;; *) AC_MSG_RESULT(ERROR) @@ -802,7 +802,6 @@ AM_CONDITIONAL([OPENTHREAD_ENABLE_EXAMPLES], [test ${with_examples} != "no"]) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_SIMULATION],[test "${with_examples}" = "simulation"]) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_CC2538], [test "${with_examples}" = "cc2538"]) -AM_CONDITIONAL([OPENTHREAD_EXAMPLES_CC2650], [test "${with_examples}" = "cc2650"]) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG1], [test "${with_examples}" = "efr32mg1"]) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG12], [test "${with_examples}" = "efr32mg12"]) AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG13], [test "${with_examples}" = "efr32mg13"]) @@ -835,12 +834,12 @@ AC_MSG_CHECKING([whether to build platform libraries]) AC_ARG_WITH(platform, [AS_HELP_STRING([--with-platform=TARGET], - [Build OpenThread platform libraries for one of: cc2538, cc2650, + [Build OpenThread platform libraries for one of: cc2538, efr32mg1, efr32mg12, efr32mg13, efr32mg21, jn5189, nrf52811, nrf52833, nrf52840, posix, simulation @<:@default=simulation@:>@.])], [ # Make sure the given target is valid. case "${with_platform}" in - no|cc2538|cc2650|efr32mg1|efr32mg12|efr32mg13|efr32mg21|jn5189|nrf52811|nrf52833|nrf52840|posix|simulation) + no|cc2538|efr32mg1|efr32mg12|efr32mg13|efr32mg21|jn5189|nrf52811|nrf52833|nrf52840|posix|simulation) ;; *) AC_MSG_RESULT(ERROR) @@ -872,7 +871,6 @@ AM_CONDITIONAL([OPENTHREAD_ENABLE_PLATFORM], [test ${with_platform} != "no"]) OPENTHREAD_ENABLE_PLATFORM=${with_platform} AM_CONDITIONAL([OPENTHREAD_PLATFORM_CC2538], [test "${with_platform}" = "cc2538"]) -AM_CONDITIONAL([OPENTHREAD_PLATFORM_CC2650], [test "${with_platform}" = "cc2650"]) AM_CONDITIONAL([OPENTHREAD_PLATFORM_EFR32MG1], [test "${with_platform}" = "efr32mg1"]) AM_CONDITIONAL([OPENTHREAD_PLATFORM_EFR32MG12], [test "${with_platform}" = "efr32mg12"]) AM_CONDITIONAL([OPENTHREAD_PLATFORM_EFR32MG13], [test "${with_platform}" = "efr32mg13"]) @@ -1026,7 +1024,6 @@ examples/apps/cli/Makefile examples/apps/ncp/Makefile examples/platforms/Makefile examples/platforms/cc2538/Makefile -examples/platforms/cc2650/Makefile examples/platforms/efr32/Makefile examples/platforms/efr32/sleepy-demo/Makefile examples/platforms/efr32/sleepy-demo/sleepy-demo-mtd/Makefile diff --git a/doc/site/en/guides/porting/set-up-the-build-environment.md b/doc/site/en/guides/porting/set-up-the-build-environment.md index f7a318ba3..6be7be33b 100644 --- a/doc/site/en/guides/porting/set-up-the-build-environment.md +++ b/doc/site/en/guides/porting/set-up-the-build-environment.md @@ -32,12 +32,12 @@ Example: ``` AC_ARG_WITH(examples, [AS_HELP_STRING([--with-examples=TARGET], - [Specify the examples from one of: none, simulation, cc2538, cc2650, efr32, nrf52840 @<:@default=none@:>@.])], + [Specify the examples from one of: none, simulation, cc2538, efr32, nrf52840 @<:@default=none@:>@.])], [ case "${with_examples}" in none) ;; - simulation|cc2538|cc2650|efr32|nrf52840) + simulation|cc2538|efr32|nrf52840) if test ${enable_posix_app} = "yes"; then AC_MSG_ERROR([--with-examples must be none when POSIX apps are enabled by --enable-posix-app]) fi @@ -167,7 +167,6 @@ order: DIST_SUBDIRS = \ cc2538 \ - cc2650 \ efr32 \ nrf52840 \ simulation \ diff --git a/examples/Makefile-cc2650 b/examples/Makefile-cc2650 deleted file mode 100644 index 34ecac69a..000000000 --- a/examples/Makefile-cc2650 +++ /dev/null @@ -1,269 +0,0 @@ -# -# Copyright (c) 2017, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -.NOTPARALLEL: - -AR = arm-none-eabi-ar -AS = arm-none-eabi-as -CPP = arm-none-eabi-cpp -CC = arm-none-eabi-gcc -CXX = arm-none-eabi-g++ -LD = arm-none-eabi-ld -STRIP = arm-none-eabi-strip -NM = arm-none-eabi-nm -RANLIB = arm-none-eabi-ranlib -OBJCOPY = arm-none-eabi-objcopy - -BuildJobs ?= 10 - -configure_OPTIONS = \ - --enable-cli \ - --enable-mtd \ - --enable-ncp \ - --enable-radio-only \ - --enable-linker-map \ - --with-examples=cc2650 \ - MBEDTLS_CPPFLAGS="$(CC2650_MBEDTLS_CPPFLAGS)" \ - $(NULL) - -CC2650_MBEDTLS_CPPFLAGS = -DMBEDTLS_CONFIG_FILE='\"mbedtls-config.h\"' -CC2650_MBEDTLS_CPPFLAGS += -DMBEDTLS_USER_CONFIG_FILE='\"cc2650-mbedtls-config.h\"' -CC2650_MBEDTLS_CPPFLAGS += -I$(PWD)/examples/platforms/cc2650/crypto -CC2650_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/ti/devices/cc26x0 -CC2650_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/mbedtls -CC2650_MBEDTLS_CPPFLAGS += -I$(PWD)/third_party/mbedtls/repo/include - -CC2650_CONFIG_FILE_CPPFLAGS = -DOPENTHREAD_PROJECT_CORE_CONFIG_FILE='\"openthread-core-cc2650-config.h\"' -CC2650_CONFIG_FILE_CPPFLAGS += -DOPENTHREAD_CORE_CONFIG_PLATFORM_CHECK_FILE='\"openthread-core-cc2650-config-check.h\"' -CC2650_CONFIG_FILE_CPPFLAGS += -I$(PWD)/examples/platforms/cc2650/ - -COMMONCFLAGS := \ - -fdata-sections \ - -ffunction-sections \ - -Os \ - -g \ - $(CC2650_CONFIG_FILE_CPPFLAGS)\ - $(NULL) - -include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/common-switches.mk - -CPPFLAGS += \ - $(COMMONCFLAGS) \ - $(target_CPPFLAGS) \ - $(NULL) - -CFLAGS += \ - $(COMMONCFLAGS) \ - $(target_CFLAGS) \ - $(NULL) - -CXXFLAGS += \ - $(COMMONCFLAGS) \ - $(target_CXXFLAGS) \ - -fno-exceptions \ - -fno-rtti \ - $(NULL) - -LDFLAGS += \ - $(COMMONCFLAGS) \ - $(target_LDFLAGS) \ - -nostartfiles \ - -specs=nano.specs \ - -specs=nosys.specs \ - -Wl,--gc-sections \ - $(NULL) - -ECHO := @echo -MAKE := make -MKDIR_P := mkdir -p -LN_S := ln -s -RM_F := rm -f - -INSTALL := /usr/bin/install -INSTALLFLAGS := -p - -TopSourceDir := $(dir $(shell readlink $(firstword $(MAKEFILE_LIST)))).. -AbsTopSourceDir := $(dir $(realpath $(firstword $(MAKEFILE_LIST)))).. - -BuildPath = build -TopBuildDir = $(BuildPath) -AbsTopBuildDir = $(PWD)/$(TopBuildDir) - -ResultPath = output -TopResultDir = $(ResultPath) -AbsTopResultDir = $(PWD)/$(TopResultDir) - -TargetTuple = cc2650 - -ARCHS = cortex-m3 - -TopTargetLibDir = $(TopResultDir)/$(TargetTuple)/lib - -ifndef BuildJobs -BuildJobs := $(shell getconf _NPROCESSORS_ONLN) -endif -JOBSFLAG := -j$(BuildJobs) - -# -# configure-arch -# -# Configure OpenThread for the specified architecture. -# -# arch - The architecture to configure. -# -define configure-arch -$(ECHO) " CONFIG $(TargetTuple)..." -(cd $(BuildPath)/$(TargetTuple) && $(AbsTopSourceDir)/configure \ -INSTALL="$(INSTALL) $(INSTALLFLAGS)" \ -CPP="$(CPP)" CC="$(CC)" CXX="$(CXX)" OBJC="$(OBJC)" OBJCXX="$(OBJCXX)" AR="$(AR)" RANLIB="$(RANLIB)" NM="$(NM)" STRIP="$(STRIP)" CPPFLAGS="$(CPPFLAGS)" CFLAGS="$(CFLAGS)" CXXFLAGS="$(CXXFLAGS)" LDFLAGS="$(LDFLAGS)" \ ---host=arm-none-eabi \ ---prefix=/ \ ---exec-prefix=/$(TargetTuple) \ -$(configure_OPTIONS)) -endef # configure-arch - -# -# build-arch -# -# Build the OpenThread intermediate build products for the specified -# architecture. -# -# arch - The architecture to build. -# -define build-arch -$(ECHO) " BUILD $(TargetTuple)" -$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \ -all -endef # build-arch - -# -# stage-arch -# -# Stage (install) the OpenThread final build products for the specified -# architecture. -# -# arch - The architecture to stage. -# -define stage-arch -$(ECHO) " STAGE $(TargetTuple)" -$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \ -DESTDIR=$(AbsTopResultDir) \ -install -endef # stage-arch - -# -# ARCH_template -# -# Define macros, targets and rules to configure, build, and stage the -# OpenThread for a single architecture. -# -# arch - The architecture to instantiate the template for. -# -define ARCH_template -CONFIGURE_TARGETS += configure-$(1) -BUILD_TARGETS += do-build-$(1) -STAGE_TARGETS += stage-$(1) -BUILD_DIRS += $(BuildPath)/$(TargetTuple) -DIRECTORIES += $(BuildPath)/$(TargetTuple) - -configure-$(1): target_CPPFLAGS=$($(1)_target_CPPFLAGS) -configure-$(1): target_CFLAGS=$($(1)_target_CFLAGS) -configure-$(1): target_CXXFLAGS=$($(1)_target_CXXFLAGS) -configure-$(1): target_LDFLAGS=$($(1)_target_LDFLAGS) - -configure-$(1): $(BuildPath)/$(TargetTuple)/config.status - -$(BuildPath)/$(TargetTuple)/config.status: | $(BuildPath)/$(TargetTuple) - $$(call configure-arch,$(1)) - -do-build-$(1): configure-$(1) - -do-build-$(1): - +$$(call build-arch,$(1)) - -stage-$(1): do-build-$(1) - -stage-$(1): | $(TopResultDir) - $$(call stage-arch,$(1)) - -$(1): stage-$(1) -endef # ARCH_template - -.DEFAULT_GOAL := all - -all: stage - -# -# cortex-m3 -# - -cortex-m3_target_ABI = cortex-m3 -cortex-m3_target_CPPFLAGS = -mcpu=cortex-m3 -mfloat-abi=soft -mthumb -cortex-m3_target_CFLAGS = -mcpu=cortex-m3 -mfloat-abi=soft -mthumb -cortex-m3_target_CXXFLAGS = -mcpu=cortex-m3 -mfloat-abi=soft -mthumb -cortex-m3_target_LDFLAGS = -mcpu=cortex-m3 -mfloat-abi=soft -mthumb - -# Instantiate an architecture-specific build template for each target -# architecture. - -$(foreach arch,$(ARCHS),$(eval $(call ARCH_template,$(arch)))) - -# -# Common / Finalization -# - -configure: $(CONFIGURE_TARGETS) - -build: $(BUILD_TARGETS) - -stage: $(STAGE_TARGETS) - -DIRECTORIES = $(TopResultDir) $(TopResultDir)/$(TargetTuple)/lib $(BUILD_DIRS) - -CLEAN_DIRS = $(TopResultDir) $(BUILD_DIRS) - -all: stage - -$(DIRECTORIES): - $(ECHO) " MKDIR $@" - @$(MKDIR_P) "$@" - -clean: - $(ECHO) " CLEAN" - @$(RM_F) -r $(CLEAN_DIRS) - -help: - $(ECHO) "Simply type 'make -f $(firstword $(MAKEFILE_LIST))' to build OpenThread for the following " - $(ECHO) "architectures: " - $(ECHO) "" - $(ECHO) " $(ARCHS)" - $(ECHO) "" - $(ECHO) "To build only a particular architecture, specify: " - $(ECHO) "" - $(ECHO) " make -f $(firstword $(MAKEFILE_LIST)) " - $(ECHO) "" diff --git a/examples/platforms/Makefile.am b/examples/platforms/Makefile.am index 9ac9c2492..8ecd602a0 100644 --- a/examples/platforms/Makefile.am +++ b/examples/platforms/Makefile.am @@ -43,7 +43,6 @@ EXTRA_DIST = \ DIST_SUBDIRS = \ cc2538 \ - cc2650 \ efr32 \ k32w \ nrf528xx \ @@ -61,10 +60,6 @@ if OPENTHREAD_PLATFORM_CC2538 SUBDIRS += cc2538 endif -if OPENTHREAD_PLATFORM_CC2650 -SUBDIRS += cc2650 -endif - if OPENTHREAD_PLATFORM_EFR32 SUBDIRS += efr32 endif diff --git a/examples/platforms/Makefile.platform.am b/examples/platforms/Makefile.platform.am index f0734dbf7..8ef465ffb 100644 --- a/examples/platforms/Makefile.platform.am +++ b/examples/platforms/Makefile.platform.am @@ -45,10 +45,6 @@ if OPENTHREAD_EXAMPLES_CC2538 include $(top_srcdir)/examples/platforms/cc2538/Makefile.platform.am endif -if OPENTHREAD_EXAMPLES_CC2650 -include $(top_srcdir)/examples/platforms/cc2650/Makefile.platform.am -endif - if OPENTHREAD_EXAMPLES_EFR32 include $(top_srcdir)/examples/platforms/efr32/Makefile.platform.am endif diff --git a/examples/platforms/cc2650/CMakeLists.txt b/examples/platforms/cc2650/CMakeLists.txt deleted file mode 100644 index 685e5b0ae..000000000 --- a/examples/platforms/cc2650/CMakeLists.txt +++ /dev/null @@ -1,96 +0,0 @@ -# -# Copyright (c) 2020, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -set(OT_PLATFORM_LIB "openthread-cc2650" PARENT_SCOPE) - -if(NOT OT_CONFIG) - set(OT_CONFIG "openthread-core-cc2650-config.h") - set(OT_CONFIG ${OT_CONFIG} PARENT_SCOPE) -endif() - -list(APPEND OT_PLATFORM_DEFINES - "OPENTHREAD_CORE_CONFIG_PLATFORM_CHECK_FILE=\"openthread-core-cc2650-config-check.h\"" -) -set(OT_PLATFORM_DEFINES ${OT_PLATFORM_DEFINES} PARENT_SCOPE) - -target_compile_definitions(ot-config INTERFACE "MBEDTLS_USER_CONFIG_FILE=\"cc2650-mbedtls-config.h\"") -list(APPEND OT_PUBLIC_INCLUDES - "${CMAKE_CURRENT_SOURCE_DIR}/crypto" - "${PROJECT_SOURCE_DIR}/third_party/ti/devices/cc26x0" -) -set(OT_PUBLIC_INCLUDES ${OT_PUBLIC_INCLUDES} PARENT_SCOPE) - -list(APPEND OT_PLATFORM_DEFINES "OPENTHREAD_PROJECT_CORE_CONFIG_FILE=\"${OT_CONFIG}\"") - -add_library(openthread-cc2650 - alarm.c - cc2650_ccfg.c - cc2650_startup.c - crypto/aes_alt.c - crypto/sha256_alt.c - cxx_helpers.c - diag.c - entropy.c - logging.c - misc.c - radio.c - system.c - uart.c - $ -) - -set_target_properties( - openthread-cc2650 - PROPERTIES - C_STANDARD 99 - CXX_STANDARD 11 -) - -target_link_libraries(openthread-cc2650 - PUBLIC - cc26x0-driver - -Wl,--gc-sections - -Wl,-Map=$.map - PRIVATE - ${OT_MBEDTLS} - ot-config -) - -target_compile_definitions(openthread-cc2650 - PUBLIC - ${OT_PLATFORM_DEFINES} -) - -target_compile_options(openthread-cc2650 PRIVATE ${OT_CFLAGS}) - -target_include_directories(openthread-cc2650 - PRIVATE - ${OT_PUBLIC_INCLUDES} - ${PROJECT_SOURCE_DIR}/src/core - ${PROJECT_SOURCE_DIR}/examples/platforms -) diff --git a/examples/platforms/cc2650/Makefile.am b/examples/platforms/cc2650/Makefile.am deleted file mode 100644 index db1e8b61e..000000000 --- a/examples/platforms/cc2650/Makefile.am +++ /dev/null @@ -1,80 +0,0 @@ -# -# Copyright (c) 2017, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -include $(abs_top_nlbuild_autotools_dir)/automake/pre.am - -# Do not enable -Wcast-align for this platform -override CFLAGS := $(filter-out -Wcast-align,$(CFLAGS)) -override CXXFLAGS := $(filter-out -Wcast-align,$(CXXFLAGS)) - -lib_LIBRARIES = libopenthread-cc2650.a - -libopenthread_cc2650_a_CPPFLAGS = \ - -I$(top_srcdir)/include \ - -I$(top_srcdir)/src \ - -I$(top_srcdir)/src/core \ - -I$(top_srcdir)/examples/platforms \ - -I$(top_srcdir)/examples/platforms/cc2650 \ - -I$(top_srcdir)/third_party/ti/devices/cc26x0 \ - -I$(top_srcdir)/third_party/mbedtls/repo/include \ - $(MBEDTLS_CPPFLAGS) \ - $(NULL) - -PLATFORM_SOURCES = \ - alarm.c \ - cc2650_radio.h \ - diag.c \ - entropy.c \ - misc.c \ - logging.c \ - openthread-core-cc2650-config.h \ - openthread-core-cc2650-config-check.h \ - platform-cc2650.h \ - radio.c \ - system.c \ - uart.c \ - crypto/sha256_alt.c \ - crypto/aes_alt.c \ - cxx_helpers.c \ - cc2650_ccfg.c \ - cc2650_startup.c \ - $(NULL) - -libopenthread_cc2650_a_SOURCES = \ - $(PLATFORM_SOURCES) \ - $(NULL) - -libopenthread_cc2650_a_DEPENDENCIES = \ - $(top_srcdir)/third_party/ti/devices/cc26x0/driverlib/bin/gcc/driverlib.a \ - $(NULL) - -Dash = - -libopenthread_cc2650_a_LIBADD = \ - $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o") - -include $(abs_top_nlbuild_autotools_dir)/automake/post.am diff --git a/examples/platforms/cc2650/Makefile.platform.am b/examples/platforms/cc2650/Makefile.platform.am deleted file mode 100644 index de7b9e7da..000000000 --- a/examples/platforms/cc2650/Makefile.platform.am +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright (c) 2017, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -# -# cc2650 platform-specific Makefile -# - -CPPFLAGS_COMMON += \ - -I$(top_srcdir)/third_party/ti/devices/cc26x0 \ - $(NULL) - -LDADD_COMMON += \ - $(top_builddir)/examples/platforms/cc2650/libopenthread-cc2650.a \ - $(top_srcdir)/third_party/ti/devices/cc26x0/driverlib/bin/gcc/driverlib.a \ - $(NULL) - -LDFLAGS_COMMON += \ - -T $(top_srcdir)/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.lds \ - $(NULL) diff --git a/examples/platforms/cc2650/README.md b/examples/platforms/cc2650/README.md deleted file mode 100644 index 48141a150..000000000 --- a/examples/platforms/cc2650/README.md +++ /dev/null @@ -1,119 +0,0 @@ -# OpenThread on CC2650 Example - -This directory contains example platform drivers for the [Texas Instruments CC2650][cc2650]. - -The example platform drivers are intended to present the minimal code necessary to support OpenThread. As a result, the example platform drivers do not necessarily highlight the platform's full capabilities. The platform abstraction layer was build for the [CC2650 LAUNCHXL][cc2650-launchxl], usage on other boards with a CC2650 will require changes to the peripheral drivers. - -Due to flash size limitations, some features of OpenThread are not supported on the [Texas Instruments CC2650][cc2650]. This platform is intended for exprimentation and exploration of OpenThread, not a production ready environment. Texas Instruments recommends future TI SoCs for production. - -Building with gcc 5.4 is recommended due to generated code size concerns. - -All three configurations were tested with `arm-none-eabi-gcc 5.4.1 20160609 (release)` on [this commit][tested-commit]. The automatic integration builds have since been limited to only the `cli-mtd` configuration to limit the impact on pull requests. - -[cc2650]: http://www.ti.com/product/CC2650 -[cc2650-launchxl]: http://www.ti.com/tool/Launchxl-cc2650 -[tested-commit]: https://github.com/openthread/openthread/commit/e8611291d65e8ad28d77a7645695c5352504c3dd - -## Build Environment - -Building the examples for the cc2650 requires [GNU AutoConf][gnu-autoconf], [GNU AutoMake][gnu-automake], [Python][python], and the [ARM gcc toolchain][arm-toolchain]. - -With the exception of the arm toolchain, most of these tools are installed by default on modern Posix systems. Windows does not have these tools installed by default, and the bootstrap script requires a Posix or MSYS environment to run. It is possible to setup an MSYS environment inside of Windows using tools such as [Cygwin][cygwin] or [MinGW][mingw] but it is recommended to setup a Linux VM for building on a Windows system. For help setting up VirtualBox with Ubuntu, consult this [community help wiki article][ubuntu-wiki-virtualbox]. - -[gnu-autoconf]: https://www.gnu.org/software/autoconf -[gnu-automake]: https://www.gnu.org/software/automake -[python]: https://www.python.org -[arm-toolchain]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm -[cygwin]: https://www.cygwin.com -[mingw]: http://www.mingw.org -[ubuntu-wiki-virtualbox]: https://help.ubuntu.com/community/VirtualBox - -In a Bash terminal, follow these instructions to install the GNU toolchain and other dependencies. - -```bash -$ cd -$ ./script/bootstrap -``` - -## Building - -In a Bash terminal, follow these instructions to build the cc2650 examples. - -```bash -$ cd -$ ./bootstrap -$ make -f examples/Makefile-cc2650 -``` - -## Flash Binaries - -If the build completed successfully, the `elf` files may be found in `/output/cc2650/bin`. - -To flash the images with [Flash Programmer 2][ti-flash-programmer-2], the files must have the `*.elf` extension. - -```bash -$ cd /output/cc2650/bin -$ cp ot-cli ot-cli.elf -``` - -To load the images with the [serial bootloader][ti-cc2650-bootloader], the images must be converted to `bin`. This is done using `arm-none-eabi-objcopy` - -```bash -$ cd /output/cc2650/bin -$ arm-none-eabi-objcopy -O binary ot-cli ot-cli.bin -``` - -The [cc2538-bsl.py script][cc2538-bsl-tool] provides a convenient method for flashing a CC2650 via the UART. To enter the bootloader backdoor for flashing, hold down BTN-1 on CC2650 LauchPad or SELECT for CC2650DK (corresponds to logic '0') while you press the Reset button. - -[ti-flash-programmer-2]: http://www.ti.com/tool/flash-programmer -[ti-cc2650-bootloader]: http://www.ti.com/lit/an/swra466a/swra466a.pdf -[cc2538-bsl-tool]: https://github.com/JelmerT/cc2538-bsl - -## Interact - -### CLI example - -1. With a terminal client (putty, minicom, etc.) open the com port associated with the cc2650 UART. The serial port settings are: - - 115200 baud - - 8 data bits - - no parity bit - - 1 stop bit -2. Type `help` for a list of commands -3. follow the instructions in the [CLI README][cli-readme] for instructions on setting up a network - -[cli-readme]: ../../../src/cli/README.md - -```bash -> help -help -channel -childtimeout -contextreusedelay -extaddr -extpanid -ipaddr -keysequence -leaderweight -masterkey -mode -netdata register -networkidtimeout -networkname -panid -ping -prefix -releaserouterid -rloc16 -route -routerupgradethreshold -scan -start -state -stop -``` - -### NCP example - -Refer to the documentation in the [wpantund][wpantund] project for build instructions and usage information. - -[wpantund]: https://github.com/openthread/wpantund diff --git a/examples/platforms/cc2650/alarm.c b/examples/platforms/cc2650/alarm.c deleted file mode 100644 index 919787aa6..000000000 --- a/examples/platforms/cc2650/alarm.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "openthread-core-config.h" - -#include -#include -#include - -#include -#include - -/** - * /NOTE: we could use systick, but that would sacrifice atleast a few ops - * every ms, and not run when the processor is sleeping. - */ - -static uint32_t sTime0 = 0; -static uint32_t sAlarmTime = 0; -static bool sIsRunning = false; - -/** - * Function documented in platform-cc2650.h - */ -void cc2650AlarmInit(void) -{ - /* - * NOTE: this will not enable the individual rtc alarm channels - */ - AONRTCEnable(); - sIsRunning = true; -} - -/** - * Function documented in platform/alarm-milli.h - */ -uint32_t otPlatAlarmMilliGetNow(void) -{ - /* - * This is current value of RTC as it appears in the register. - * With seconds as the upper 32 bytes and fractions of a second as the - * lower 32 bytes <32.32>. - */ - uint64_t rtcVal = AONRTCCurrent64BitValueGet(); - return ((rtcVal * 1000) >> 32); -} - -/** - * Function documented in platform/alarm-milli.h - */ -void otPlatAlarmMilliStartAt(otInstance *aInstance, uint32_t aT0, uint32_t aDt) -{ - OT_UNUSED_VARIABLE(aInstance); - - sTime0 = aT0; - sAlarmTime = aDt; - sIsRunning = true; -} - -/** - * Function documented in platform/alarm-milli.h - */ -void otPlatAlarmMilliStop(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - sIsRunning = false; -} - -/** - * Function documented in platform-cc2650.h - */ -void cc2650AlarmProcess(otInstance *aInstance) -{ - uint32_t offsetTime; - - if (sIsRunning) - { - /* unsinged subtraction will result in the absolute offset */ - offsetTime = otPlatAlarmMilliGetNow() - sTime0; - - if (sAlarmTime <= offsetTime) - { - sIsRunning = false; -#if OPENTHREAD_CONFIG_DIAG_ENABLE - - if (otPlatDiagModeGet()) - { - otPlatDiagAlarmFired(aInstance); - } - else -#endif /* OPENTHREAD_CONFIG_DIAG_ENABLE */ - { - otPlatAlarmMilliFired(aInstance); - } - } - } -} diff --git a/examples/platforms/cc2650/arm-none-eabi.cmake b/examples/platforms/cc2650/arm-none-eabi.cmake deleted file mode 100644 index 6dba6fdb1..000000000 --- a/examples/platforms/cc2650/arm-none-eabi.cmake +++ /dev/null @@ -1,42 +0,0 @@ -# -# Copyright (c) 2020, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_SYSTEM_PROCESSOR ARM) - -set(CMAKE_C_COMPILER arm-none-eabi-gcc) -set(CMAKE_CXX_COMPILER arm-none-eabi-g++) -set(CMAKE_ASM_COMPILER arm-none-eabi-as) -set(CMAKE_RANLIB arm-none-eabi-ranlib) - -set(COMMON_C_FLAGS "-mthumb -fdata-sections -ffunction-sections -mcpu=cortex-m3 -mfloat-abi=soft") - -set(CMAKE_C_FLAGS_INIT "${COMMON_C_FLAGS} -std=gnu99") -set(CMAKE_CXX_FLAGS_INIT "${COMMON_C_FLAGS} -fno-exceptions -fno-rtti") -set(CMAKE_ASM_FLAGS_INIT "${COMMON_C_FLAGS}") -set(CMAKE_EXE_LINKER_FLAGS_INIT "${COMMON_C_FLAGS} -specs=nano.specs -specs=nosys.specs -nostartfiles") diff --git a/examples/platforms/cc2650/cc2650_ccfg.c b/examples/platforms/cc2650/cc2650_ccfg.c deleted file mode 100644 index 1470ba6ff..000000000 --- a/examples/platforms/cc2650/cc2650_ccfg.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Configure the Customer Configuration Area. - */ - -// clang-format off - -// enable bootloader backdoor -#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader - -#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor - -#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0x0D // DIO13 (BTN-1 button) on CC2650 LaunchPad Board for boot loader backdoor -// #define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0x0B // DIO11 (SELECT button) on CC2650DK (QFN48/7*7) for boot loader backdoor - -#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor - -#define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image is valid - -/* - * Include the default ccfg struct and configuration code. - */ -#include - -// clang-format on diff --git a/examples/platforms/cc2650/cc2650_radio.h b/examples/platforms/cc2650/cc2650_radio.h deleted file mode 100644 index 8a8749ee9..000000000 --- a/examples/platforms/cc2650/cc2650_radio.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef CC2650_RADIO_H_ -#define CC2650_RADIO_H_ - -#include - -enum -{ - IEEE802154_FRAME_TYPE_MASK = 0x7, ///< (IEEE 802.15.4-2006) PSDU.FCF.frameType - IEEE802154_FRAME_TYPE_ACK = 0x2, ///< (IEEE 802.15.4-2006) frame type: ACK - IEEE802154_ACK_REQUEST = (1 << 5), ///< (IEEE 802.15.4-2006) PSDU.FCF.bAR - IEEE802154_DSN_OFFSET = 2, ///< (IEEE 802.15.4-2006) PSDU.sequenceNumber - IEEE802154_MAC_MIN_BE = 1, ///< (IEEE 802.15.4-2006) macMinBE - IEEE802154_MAC_MAX_BE = 5, ///< (IEEE 802.15.4-2006) macMaxBE - IEEE802154_MAC_MAX_CSMA_BACKOFFS = 4, ///< (IEEE 802.15.4-2006) macMaxCSMABackoffs - IEEE802154_MAC_MAX_FRAMES_RETRIES = 3, ///< (IEEE 802.15.4-2006) macMaxFrameRetries - IEEE802154_A_UINT_BACKOFF_PERIOD = 20, ///< (IEEE 802.15.4-2006 7.4.1) MAC constants - IEEE802154_A_TURNAROUND_TIME = 12, ///< (IEEE 802.15.4-2006 6.4.1) PHY constants - IEEE802154_PHY_SHR_DURATION = 10, - ///< (IEEE 802.15.4-2006 6.4.2) PHY PIB attribute, specifically the O-QPSK PHY - IEEE802154_PHY_SYMBOLS_PER_OCTET = 2, - ///< (IEEE 802.15.4-2006 6.4.2) PHY PIB attribute, specifically the O-QPSK PHY - IEEE802154_MAC_ACK_WAIT_DURATION = (IEEE802154_A_UINT_BACKOFF_PERIOD + // - IEEE802154_A_TURNAROUND_TIME + // - IEEE802154_PHY_SHR_DURATION + // - (6 * IEEE802154_PHY_SYMBOLS_PER_OCTET)), - ///< (IEEE 802.15.4-2006 7.4.2) macAckWaitDuration PIB attribute - IEEE802154_SYMBOLS_PER_SEC = 62500 ///< (IEEE 802.15.4-2006 6.5.3.2) O-QPSK symbol rate -}; - -enum -{ - CC2650_RAT_TICKS_PER_SEC = 4000000, ///< 4MHz clock - CC2650_INVALID_RSSI = 127, - CC2650_UNKNOWN_EUI64 = 0xFF, - ///< If the EUI64 read from the ccfg is all ones then the customer did not set the address -}; - -/** - * TX Power dBm lookup table - values from SmartRF Studio - */ -typedef struct output_config -{ - int dbm; - uint16_t value; -} output_config_t; - -static const output_config_t rgOutputPower[] = { - {5, 0x9330}, // - {4, 0x9324}, // - {3, 0x5a1c}, // - {2, 0x4e18}, // - {1, 0x4214}, // - {0, 0x3161}, // - {-3, 0x2558}, // - {-6, 0x1d52}, // - {-9, 0x194e}, // - {-12, 0x144b}, // - {-15, 0x0ccb}, // - {-18, 0x0cc9}, // - {-21, 0x0cc7}, // -}; - -#define OUTPUT_CONFIG_COUNT (sizeof(rgOutputPower) / sizeof(rgOutputPower[0])) - -/* Max and Min Output Power in dBm */ -#define OUTPUT_POWER_MIN (rgOutputPower[OUTPUT_CONFIG_COUNT - 1].dbm) -#define OUTPUT_POWER_MAX (rgOutputPower[0].dbm) -#define OUTPUT_POWER_UNKNOWN 0xFFFF - -/** - * return value used when searching the source match array - */ -#define CC2650_SRC_MATCH_NONE 0xFF - -/** - * number of extended addresses used for source matching - */ -#define CC2650_EXTADD_SRC_MATCH_NUM 10 - -/** - * structure for source matching extended addresses - */ -typedef struct __attribute__((aligned(4))) ext_src_match_data -{ - uint32_t srcMatchEn[((CC2650_EXTADD_SRC_MATCH_NUM + 31) / 32)]; - uint32_t srcPendEn[((CC2650_EXTADD_SRC_MATCH_NUM + 31) / 32)]; - uint64_t extAddrEnt[CC2650_EXTADD_SRC_MATCH_NUM]; -} ext_src_match_data_t; - -/** - * number of short addresses used for source matching - */ -#define CC2650_SHORTADD_SRC_MATCH_NUM 10 - -/** - * structure for source matching short addresses - */ -typedef struct __attribute__((aligned(4))) short_src_match_data -{ - uint32_t srcMatchEn[((CC2650_SHORTADD_SRC_MATCH_NUM + 31) / 32)]; - uint32_t srcPendEn[((CC2650_SHORTADD_SRC_MATCH_NUM + 31) / 32)]; - rfc_shortAddrEntry_t extAddrEnt[CC2650_SHORTADD_SRC_MATCH_NUM]; -} short_src_match_data_t; - -/** - * size of length field in receive struct - * - * defined in Table 23-10 of the cc26xx TRM - */ -#define DATA_ENTRY_LENSZ_BYTE 1 - -/** - * address type for @ref rfCoreModifySourceMatchEntry() - */ -typedef enum cc2650_address -{ - SHORT_ADDRESS = 1, - EXT_ADDRESS = 0, -} cc2650_address_t; - -/** - * This enum represents the state of a radio. - * Initially, a radio is in the Disabled state. - * - * The following are valid radio state transitions for the cc2650: - * - * (Radio ON) - * +----------+ Enable() +-------+ Receive() +---------+ Transmit() +----------+ - * | |----------->| |------------->| |--------------->| | - * | Disabled | | Sleep | | Receive | | Transmit | - * | |<-----------| |<-------------| |<---------------| | - * +----------+ Disable() | | Sleep() | | AckFrame RX or +----------+ - * | | (Radio OFF) +---------+ sTxCmdChainDone == true - * | | - * | | EnergyScan() +--------+ - * | |------------->| | - * | | | EdScan | - * | |<-------------| | - * | | signal ED | | - * +-------+ scan done +--------+ - * - * These states slightly differ from the states in \ref include/platform/radio.h. - * The additional states the phy can be in are due to the asynchronous nature - * of the CM0 radio core. - * - * | state | description | - * |------------------|----------------------------------------------------| - * | Disabled | The rfcore powerdomain is off and the RFCPE is off | - * | Sleep | The RFCORE PD is on, and the RFCPE is in IEEE mode | - * | Receive | The RFCPE is running a CMD_IEEE_RX | - * | Transmit | The RFCPE is running a transmit command string | - * | TransmitComplete | The transmit command string has completed | - * | EdScan | The RFCPE is running a CMD_IEEE_ED_SCAN | - * - * \note The RAT start and Radio Setup commands may be moved to the Receive() - * and EnergyScan() transitions in the future. - */ -typedef enum cc2650_PhyState -{ - cc2650_stateDisabled = 0, - cc2650_stateSleep, - cc2650_stateReceive, - cc2650_stateEdScan, - cc2650_stateTransmit, -} cc2650_PhyState; - -#endif /* CC2650_RADIO_H_ */ diff --git a/examples/platforms/cc2650/cc2650_startup.c b/examples/platforms/cc2650/cc2650_startup.c deleted file mode 100644 index 17ac72965..000000000 --- a/examples/platforms/cc2650/cc2650_startup.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Include the standard startup files for the specified toolchain - * startup code is in 'third_party/ti' - */ -#if defined(__GNUC__) -#include -#elif defined(__TI_ARM__) -#include -#else -#error "Unknown compiler" -#endif diff --git a/examples/platforms/cc2650/crypto/aes_alt.c b/examples/platforms/cc2650/crypto/aes_alt.c deleted file mode 100644 index 9d88b0836..000000000 --- a/examples/platforms/cc2650/crypto/aes_alt.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "aes_alt.h" -#include "mbedtls/aes.h" - -#ifdef MBEDTLS_AES_ALT - -#include -#include -#include -#include - -#define CC2650_AES_KEY_UNUSED (-1) -#define CC2650_AES_CTX_MAGIC (0x7E) - -/** - * bitmap of which key stores are currently used - */ -static uint8_t sUsedKeys = 0; - -/** - * number of active contexts, used for power on/off of the crypto core - */ -static unsigned int sRefNum = 0; - -void mbedtls_aes_init(mbedtls_aes_context *ctx) -{ - if (sRefNum++ == 0) - { - /* enable the crypto core */ - /* The TRNG should already be running before we ever ask the AES core - * to do anything, if there is any scenario that the TRNG powers off - * the peripheral power domain use this code to repower it - - PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH); - while (PRCMPowerDomainStatus(PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_ON); - */ - PRCMPeripheralRunEnable(PRCM_PERIPH_CRYPTO); - PRCMPeripheralSleepEnable(PRCM_PERIPH_CRYPTO); - PRCMPeripheralDeepSleepEnable(PRCM_PERIPH_CRYPTO); - PRCMLoadSet(); - - while (!PRCMLoadGet()) - ; - } - - ctx->magic = CC2650_AES_CTX_MAGIC; - ctx->key_idx = CC2650_AES_KEY_UNUSED; -} - -void mbedtls_aes_free(mbedtls_aes_context *ctx) -{ - otEXPECT(ctx->magic == CC2650_AES_CTX_MAGIC); - - if (ctx->key_idx != CC2650_AES_KEY_UNUSED) - { - sUsedKeys &= ~(1 << ctx->key_idx); - } - - if (--sRefNum == 0) - { - /* disable the crypto core */ - /* The TRNG core needs the peripheral power domain powered on to - * function. if there is a situation where the power domain must be - * powered off, use this code to do so. - - PRCMPowerDomainOff(PRCM_DOMAIN_PERIPH); - while (PRCMPowerDomainStatus(PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_OFF); - */ - PRCMPeripheralRunDisable(PRCM_PERIPH_CRYPTO); - PRCMPeripheralSleepDisable(PRCM_PERIPH_CRYPTO); - PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_CRYPTO); - PRCMLoadSet(); - - while (!PRCMLoadGet()) - ; - } - - memset((void *)ctx, 0x00, sizeof(ctx)); - -exit: - return; -} - -int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits) -{ - unsigned char key_idx; - int retval = 0; - - otEXPECT_ACTION(ctx->magic == CC2650_AES_CTX_MAGIC, retval = -1); - - if (ctx->key_idx != CC2650_AES_KEY_UNUSED) - { - sUsedKeys &= ~(1 << ctx->key_idx); - } - - /* our hardware only supports 128 bit keys */ - otEXPECT_ACTION(keybits == 128u, retval = MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); - - for (key_idx = 0; ((sUsedKeys >> key_idx) & 0x01) != 0 && key_idx < 8; key_idx++) - ; - - /* we have no more room for this key */ - otEXPECT_ACTION(key_idx < 8, retval = -2); - - otEXPECT_ACTION(CRYPTOAesLoadKey((uint32_t *)key, key_idx) == AES_SUCCESS, - retval = MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); - - sUsedKeys |= (1 << key_idx); - ctx->key_idx = key_idx; -exit: - return retval; -} - -int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits) -{ - unsigned char key_idx; - int retval = 0; - - otEXPECT_ACTION(ctx->magic == CC2650_AES_CTX_MAGIC, retval = -1); - - if (ctx->key_idx != CC2650_AES_KEY_UNUSED) - { - sUsedKeys &= ~(1 << ctx->key_idx); - } - - /* our hardware only supports 128 bit keys */ - otEXPECT_ACTION(keybits == 128u, retval = MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); - - for (key_idx = 0; ((sUsedKeys >> key_idx) & 0x01) != 0 && key_idx < 8; key_idx++) - ; - - /* we have no more room for this key */ - otEXPECT_ACTION(key_idx < 8, retval = -2); - - otEXPECT_ACTION(CRYPTOAesLoadKey((uint32_t *)key, key_idx) == AES_SUCCESS, - retval = MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); - - sUsedKeys |= (1 << key_idx); - ctx->key_idx = key_idx; -exit: - return retval; -} - -/** - * \brief AES-ECB block encryption/decryption - * - * \param ctx AES context - * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT - * \param input 16-byte input block - * \param output 16-byte output block - * - * \return 0 if successful - */ -int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16]) -{ - int retval = -1; - - retval = CRYPTOAesEcb((uint32_t *)input, (uint32_t *)output, ctx->key_idx, mode == MBEDTLS_AES_ENCRYPT, false); - otEXPECT(retval == AES_SUCCESS); - - while ((retval = CRYPTOAesEcbStatus()) == AES_DMA_BSY) - ; - - CRYPTOAesEcbFinish(); - -exit: - return retval; -} - -#endif /* MBEDTLS_AES_ALT */ diff --git a/examples/platforms/cc2650/crypto/aes_alt.h b/examples/platforms/cc2650/crypto/aes_alt.h deleted file mode 100644 index 299c85b88..000000000 --- a/examples/platforms/cc2650/crypto/aes_alt.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef MBEDTLS_AES_ALT_H -#define MBEDTLS_AES_ALT_H - -#ifndef MBEDTLS_CONFIG_FILE -#include "cc2650-mbedtls-config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#ifdef MBEDTLS_AES_ALT - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct -{ - uint8_t magic; - signed char key_idx; -} mbedtls_aes_context; - -/** - * @brief Initialize AES context - * - * @param [in,out] ctx AES context to be initialized - */ -void mbedtls_aes_init(mbedtls_aes_context *ctx); - -/** - * @brief Clear AES context - * - * \param ctx AES context to be cleared - */ -void mbedtls_aes_free(mbedtls_aes_context *ctx); - -/** - * \brief AES key schedule (encryption) - * - * \param ctx AES context to be initialized - * \param key encryption key - * \param keybits must be 128, 192 or 256 - * - * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH - */ -int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits); - -/** - * \brief AES key schedule (decryption) - * - * \param ctx AES context to be initialized - * \param key decryption key - * \param keybits must be 128, 192 or 256 - * - * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH - */ -int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits); - -/** - * \brief AES-ECB block encryption/decryption - * - * \param ctx AES context - * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT - * \param input 16-byte input block - * \param output 16-byte output block - * - * \return 0 if successful - */ -int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16]); - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_AES_ALT */ - -#endif /* MBEDTLS_AES_ALT_H */ diff --git a/examples/platforms/cc2650/crypto/cc2650-mbedtls-config.h b/examples/platforms/cc2650/crypto/cc2650-mbedtls-config.h deleted file mode 100644 index db4605814..000000000 --- a/examples/platforms/cc2650/crypto/cc2650-mbedtls-config.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2018, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef CC2650_MBEDTLS_CONFIG_H -#define CC2650_MBEDTLS_CONFIG_H - -#define MBEDTLS_AES_ALT -#define MBEDTLS_SHA256_ALT - -#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY - -#endif // CC2650_MBEDTLS_CONFIG_H diff --git a/examples/platforms/cc2650/crypto/sha256_alt.c b/examples/platforms/cc2650/crypto/sha256_alt.c deleted file mode 100644 index 537cea853..000000000 --- a/examples/platforms/cc2650/crypto/sha256_alt.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "sha256_alt.h" - -#ifdef MBEDTLS_SHA256_ALT - -#include - -/** - * documented in sha256_alt.h - */ -void mbedtls_sha256_init(mbedtls_sha256_context *ctx) -{ - memset((void *)ctx, 0x00, sizeof(ctx)); -} - -/** - * documented in sha256_alt.h - */ -void mbedtls_sha256_free(mbedtls_sha256_context *ctx) -{ - memset((void *)ctx, 0x00, sizeof(ctx)); -} - -/** - * documented in sha256_alt.h - */ -void mbedtls_sha256_clone(mbedtls_sha256_context *dst, const mbedtls_sha256_context *src) -{ - *dst = *src; -} - -/** - * documented in sha256_alt.h - */ -int mbedtls_sha256_starts_ret(mbedtls_sha256_context *ctx, int is224) -{ - SHA256_initialize(ctx); - - if (is224 != 0) - { - /* SHA-224 */ - ctx->state[0] = 0xC1059ED8; - ctx->state[1] = 0x367CD507; - ctx->state[2] = 0x3070DD17; - ctx->state[3] = 0xF70E5939; - ctx->state[4] = 0xFFC00B31; - ctx->state[5] = 0x68581511; - ctx->state[6] = 0x64F98FA7; - ctx->state[7] = 0xBEFA4FA4; - } - - return 0; -} - -/** - * documented in sha256_alt.h - */ -int mbedtls_sha256_update_ret(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen) -{ - SHA256_execute(ctx, (uint8_t *)input, (uint32_t)ilen); - return 0; -} - -char *workaround_cc2650_rom; - -/** - * documented in sha256_alt.h - */ -int mbedtls_sha256_finish_ret(mbedtls_sha256_context *ctx, unsigned char output[32]) -{ - /* workaround for error in copy subroutine of SHA256 ROM implementation. - * Allocate an extra 64 bytes on the stack to make sure we have buffer - * room. This could be optomized out if you never call this function with - * a call stack shorter than 16 words, approx. 8 stack frames. - * - * The simple description is this: - * If the stack pointer is within 64bytes of the end of RAM - * the bug exposes it self. - * If the stack pointer is more then 64bytes from end of RAM - * There is no bug... - * Solution: - * Make a 64byte buffer on the stack.. - * And force the compiler to think it requires this buffer. - */ - char buffer[64]; - workaround_cc2650_rom = &buffer[0]; - SHA256_output(ctx, (uint8_t *)output); - return 0; -} - -/** - * documented in sha256_alt.h - */ -int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64]) -{ - return SHA256_execute(ctx, (uint8_t *)data, sizeof(unsigned char) * 64); -} - -#endif /* MBEDTLS_SHA256_ALT */ diff --git a/examples/platforms/cc2650/crypto/sha256_alt.h b/examples/platforms/cc2650/crypto/sha256_alt.h deleted file mode 100644 index 8e0aec875..000000000 --- a/examples/platforms/cc2650/crypto/sha256_alt.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef MBEDTLS_SHA256_ALT_H -#define MBEDTLS_SHA256_ALT_H - -#ifndef MBEDTLS_CONFIG_FILE -#include "cc2650-mbedtls-config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#ifdef MBEDTLS_SHA256_ALT - -#include "driverlib/rom_crypto.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief translating the mbedtls SHA256 workspace to the cc2650 SHA256 workspace. - */ -typedef SHA256_memory_t mbedtls_sha256_context; - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_SHA256_ALT */ - -#endif /* MBEDTLS_SHA256_ALT_H */ diff --git a/examples/platforms/cc2650/cxx_helpers.c b/examples/platforms/cc2650/cxx_helpers.c deleted file mode 100644 index d4b003662..000000000 --- a/examples/platforms/cc2650/cxx_helpers.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Helper functions for running c++ without the standard library - */ - -__extension__ typedef int __guard __attribute__((mode(__DI__))); - -int __cxa_guard_acquire(__guard *g) -{ - return !*(char *)(g); -} - -void __cxa_guard_release(__guard *g) -{ - *(char *)g = 1; -} - -void __cxa_guard_abort(__guard *g) -{ - (void)g; -} - -void __cxa_pure_virtual(void) -{ - while (1) - ; -} diff --git a/examples/platforms/cc2650/diag.c b/examples/platforms/cc2650/diag.c deleted file mode 100644 index 50d20d984..000000000 --- a/examples/platforms/cc2650/diag.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "openthread-core-config.h" -#include - -#include -#include -#include - -#include - -#if OPENTHREAD_CONFIG_DIAG_ENABLE - -#include "platform-cc2650.h" -/** - * Diagnostics mode variables. - * - */ -static bool sDiagMode = false; - -void otPlatDiagModeSet(bool aMode) -{ - sDiagMode = aMode; -} - -bool otPlatDiagModeGet() -{ - return sDiagMode; -} - -void otPlatDiagChannelSet(uint8_t aChannel) -{ - OT_UNUSED_VARIABLE(aChannel); -} - -void otPlatDiagTxPowerSet(int8_t aTxPower) -{ - OT_UNUSED_VARIABLE(aTxPower); -} - -void otPlatDiagRadioReceived(otInstance *aInstance, otRadioFrame *aFrame, otError aError) -{ - OT_UNUSED_VARIABLE(aInstance); - OT_UNUSED_VARIABLE(aFrame); - OT_UNUSED_VARIABLE(aError); -} - -void otPlatDiagAlarmCallback(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); -} - -#endif // OPENTHREAD_CONFIG_DIAG_ENABLE diff --git a/examples/platforms/cc2650/entropy.c b/examples/platforms/cc2650/entropy.c deleted file mode 100644 index 864a46371..000000000 --- a/examples/platforms/cc2650/entropy.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2019, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file implements an entropy source based on TRNG. - * - */ - -#include - -#include - -#include -#include - -#include - -enum -{ - CC2650_TRNG_MIN_SAMPLES_PER_CYCLE = (1 << 6), - CC2650_TRNG_MAX_SAMPLES_PER_CYCLE = (1 << 24), - CC2650_TRNG_CLOCKS_PER_SAMPLE = 0, -}; - -/** - * \note if more than 32 bits of entropy are needed, the TRNG core produces - * 64 bytes of random data, we just ignore the upper 32 bytes - */ - -/** - * Function documented in platform-cc2650.h - */ -void cc2650RandomInit(void) -{ - PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH); - - while (PRCMPowerDomainStatus(PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_ON) - ; - - PRCMPeripheralRunEnable(PRCM_PERIPH_TRNG); - PRCMPeripheralSleepEnable(PRCM_DOMAIN_PERIPH); - PRCMPeripheralDeepSleepEnable(PRCM_DOMAIN_PERIPH); - PRCMLoadSet(); - TRNGConfigure(CC2650_TRNG_MIN_SAMPLES_PER_CYCLE, CC2650_TRNG_MAX_SAMPLES_PER_CYCLE, CC2650_TRNG_CLOCKS_PER_SAMPLE); - TRNGEnable(); -} - -/** - * Fill an arbitrary area with random data - * - * @param [out] aOutput area to place the random data - * @param [in] aLen size of the area to place random data - * @param [out] oLen how much of the output was written to - * - * @return indication of error - * @retval 0 no error occured - */ -static int TRNGPoll(unsigned char *aOutput, size_t aLen) -{ - size_t length = 0; - union - { - uint32_t u32[2]; - uint8_t u8[8]; - } buffer; - - while (length < aLen) - { - if (length % 8 == 0) - { - /* we've run to the end of the buffer */ - while (!(TRNGStatusGet() & TRNG_NUMBER_READY)) - ; - - /* - * don't use TRNGNumberGet here because it will tell the TRNG to - * refil the entropy pool, instad we do it ourself. - */ - buffer.u32[0] = HWREG(TRNG_BASE + TRNG_O_OUT0); - buffer.u32[1] = HWREG(TRNG_BASE + TRNG_O_OUT1); - HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; - } - - aOutput[length] = buffer.u8[length % 8]; - - length++; - } - - return 0; -} - -/** - * Function documented in platform/entropy.h - */ -otError otPlatEntropyGet(uint8_t *aOutput, uint16_t aOutputLength) -{ - otError error = OT_ERROR_NONE; - size_t length = aOutputLength; - - otEXPECT_ACTION(aOutput, error = OT_ERROR_INVALID_ARGS); - - otEXPECT_ACTION(TRNGPoll((unsigned char *)aOutput, length) != 0, error = OT_ERROR_FAILED); - -exit: - return error; -} diff --git a/examples/platforms/cc2650/logging.c b/examples/platforms/cc2650/logging.c deleted file mode 100644 index c9a9a3bc7..000000000 --- a/examples/platforms/cc2650/logging.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2016, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file logging.c - * Platform abstraction for the logging - * - */ -#include -#include -#include -#include - -#if (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED) -OT_TOOL_WEAK void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const char *aFormat, ...) -{ - OT_UNUSED_VARIABLE(aLogLevel); - OT_UNUSED_VARIABLE(aLogRegion); - OT_UNUSED_VARIABLE(aFormat); -} -#endif diff --git a/examples/platforms/cc2650/misc.c b/examples/platforms/cc2650/misc.c deleted file mode 100644 index a6dc34f8b..000000000 --- a/examples/platforms/cc2650/misc.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -/** - * Function documented in platform/misc.h - */ -void otPlatReset(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - SysCtrlSystemReset(); -} - -/** - * Function documented in platform/misc.h - */ -otPlatResetReason otPlatGetResetReason(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - switch (SysCtrlResetSourceGet()) - { - case RSTSRC_PWR_ON: - return OT_PLAT_RESET_REASON_POWER_ON; - - case RSTSRC_PIN_RESET: - return OT_PLAT_RESET_REASON_EXTERNAL; - - case RSTSRC_VDDS_LOSS: - case RSTSRC_VDDR_LOSS: - case RSTSRC_CLK_LOSS: - return OT_PLAT_RESET_REASON_CRASH; - - case RSTSRC_WARMRESET: - case RSTSRC_SYSRESET: - case RSTSRC_WAKEUP_FROM_SHUTDOWN: - return OT_PLAT_RESET_REASON_SOFTWARE; - - default: - return OT_PLAT_RESET_REASON_UNKNOWN; - } -} - -void otPlatWakeHost(void) -{ - // TODO: implement an operation to wake the host from sleep state. -} diff --git a/examples/platforms/cc2650/openthread-core-cc2650-config-check.h b/examples/platforms/cc2650/openthread-core-cc2650-config-check.h deleted file mode 100644 index bf7393a6d..000000000 --- a/examples/platforms/cc2650/openthread-core-cc2650-config-check.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2019, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef OPENTHREAD_CORE_CC2650_CONFIG_CHECK_H_ -#define OPENTHREAD_CORE_CC2650_CONFIG_CHECK_H_ - -#if OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT -#error "Platform cc2650 doesn't support configuration option: OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT" -#endif - -#endif /* OPENTHREAD_CORE_CC2650_CONFIG_CHECK_H_ */ diff --git a/examples/platforms/cc2650/openthread-core-cc2650-config.h b/examples/platforms/cc2650/openthread-core-cc2650-config.h deleted file mode 100644 index 94de3b5a6..000000000 --- a/examples/platforms/cc2650/openthread-core-cc2650-config.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef OPENTHREAD_CORE_CC2650_CONFIG_H_ -#define OPENTHREAD_CORE_CC2650_CONFIG_H_ - -/** - * @def OPENTHREAD_CONFIG_PLATFORM_INFO - * - * The platform-specific string to insert into the OpenThread version string. - * - */ -#define OPENTHREAD_CONFIG_PLATFORM_INFO "CC2650" - -/** - * @def OPENTHREAD_CONFIG_NUM_MESSAGE_BUFFERS - * - * The number of message buffers in buffer pool - */ -#define OPENTHREAD_CONFIG_NUM_MESSAGE_BUFFERS 32 - -/** - * @def OPENTHREAD_CONFIG_NCP_HDLC_ENABLE - * - * Define to 1 to enable NCP HDLC support. - * - */ -#define OPENTHREAD_CONFIG_NCP_HDLC_ENABLE 1 - -/** - * @def OPENTHREAD_SETTINGS_RAM - * - * Define as 1 to enable saving the settings in RAM instead of flash. - * - */ -#define OPENTHREAD_SETTINGS_RAM 1 - -#endif /* OPENTHREAD_CORE_CC2650_CONFIG_H_ */ diff --git a/examples/platforms/cc2650/platform-cc2650.h b/examples/platforms/cc2650/platform-cc2650.h deleted file mode 100644 index 33e1c3dbd..000000000 --- a/examples/platforms/cc2650/platform-cc2650.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef PLATFORM_H_ -#define PLATFORM_H_ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// Global OpenThread instance structure -extern otInstance *sInstance; - -/** - * This method initializes the alarm service used by OpenThread. - * - */ -void cc2650AlarmInit(void); - -/** - * This method performs alarm driver processing. - * - */ -void cc2650AlarmProcess(otInstance *aInstance); - -/** - * This method initializes the radio service used by OpenThread. - * - */ -void cc2650RadioInit(void); - -/** - * This method performs radio driver processing. - * - */ -void cc2650RadioProcess(otInstance *aInstance); - -/** - * This method initializes the random number service used by OpenThread. - * - */ -void cc2650RandomInit(void); - -/** - * This method performs radio driver processing. - * - */ -void cc2650UartProcess(void); - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif // PLATFORM_H_ diff --git a/examples/platforms/cc2650/radio.c b/examples/platforms/cc2650/radio.c deleted file mode 100644 index 09d45d6fa..000000000 --- a/examples/platforms/cc2650/radio.c +++ /dev/null @@ -1,1963 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "openthread-core-config.h" -#include - -#include "cc2650_radio.h" -#include -#include -#include -#include /* to seed the CSMA-CA funciton */ -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -enum -{ - CC2650_RECEIVE_SENSITIVITY = -100, // dBm -}; - -enum -{ - CC2650_CHANNEL_MIN = OT_RADIO_2P4GHZ_OQPSK_CHANNEL_MIN, -}; - -/* phy state as defined by openthread */ -static volatile cc2650_PhyState sState; - -static output_config_t const *sCurrentOutputPower = &(rgOutputPower[OUTPUT_CONFIG_COUNT - 1]); - -/* Overrides for IEEE 802.15.4, differential mode */ -static uint32_t sIEEEOverrides[] = { - 0x00354038, /* Synth: Set RTRIM (POTAILRESTRIM) to 5 */ - 0x4001402D, /* Synth: Correct CKVD latency setting (address) */ - 0x00608402, /* Synth: Correct CKVD latency setting (value) */ - 0x000784A3, /* Synth: Set FREF = 3.43 MHz (24 MHz / 7) */ - 0xA47E0583, /* Synth: Set loop bandwidth after lock to 80 kHz (K2) */ - 0xEAE00603, /* Synth: Set loop bandwidth after lock to 80 kHz (K3, LSB) */ - 0x00010623, /* Synth: Set loop bandwidth after lock to 80 kHz (K3, MSB) */ - 0x002B50DC, /* Adjust AGC DC filter */ - 0x05000243, /* Increase synth programming timeout */ - 0x002082C3, /* Increase synth programming timeout */ - 0xFFFFFFFF, /* End of override list */ -}; - -/* - * Number of retry counts left to the currently transmitting frame. - * - * Initialized when a frame is passed to be sent over the air, and decremented - * by the radio ISR every time the transmit command string fails to receive a - * corresponding ack. - */ -static volatile unsigned int sTransmitRetryCount = 0; - -/* - * Offset of the radio timer from the rtc. - * - * Used when we start and stop the RAT on enabling and disabling of the rf - * core. - */ -static uint32_t sRatOffset = 0; - -/* - * Radio command structures that run on the CM0. - */ -// clang-format off -static volatile __attribute__((aligned(4))) rfc_CMD_SYNC_START_RAT_t sStartRatCmd; -static volatile __attribute__((aligned(4))) rfc_CMD_RADIO_SETUP_t sRadioSetupCmd; - -static volatile __attribute__((aligned(4))) rfc_CMD_FS_POWERDOWN_t sFsPowerdownCmd; -static volatile __attribute__((aligned(4))) rfc_CMD_SYNC_STOP_RAT_t sStopRatCmd; - -static volatile __attribute__((aligned(4))) rfc_CMD_CLEAR_RX_t sClearReceiveQueueCmd; -static volatile __attribute__((aligned(4))) rfc_CMD_IEEE_MOD_FILT_t sModifyReceiveFilterCmd; -static volatile __attribute__((aligned(4))) rfc_CMD_IEEE_MOD_SRC_MATCH_t sModifyReceiveSrcMatchCmd; - -static volatile __attribute__((aligned(4))) rfc_CMD_IEEE_ED_SCAN_t sEdScanCmd; - -static volatile __attribute__((aligned(4))) rfc_CMD_IEEE_RX_t sReceiveCmd; - -static volatile __attribute__((aligned(4))) rfc_CMD_IEEE_CSMA_t sCsmacaBackoffCmd; -static volatile __attribute__((aligned(4))) rfc_CMD_IEEE_TX_t sTransmitCmd; -static volatile __attribute__((aligned(4))) rfc_CMD_IEEE_RX_ACK_t sTransmitRxAckCmd; - -static volatile __attribute__((aligned(4))) ext_src_match_data_t sSrcMatchExtData; -static volatile __attribute__((aligned(4))) short_src_match_data_t sSrcMatchShortData; -// clang-format on - -/* - * Structure containing radio statistics. - */ -static __attribute__((aligned(4))) rfc_ieeeRxOutput_t sRfStats; - -#define RX_BUF_SIZE 144 -/* two receive buffers entries with room for 1 max IEEE802.15.4 frame in each */ -static uint8_t sRxBuf0[RX_BUF_SIZE] __attribute__((aligned(4))); -static uint8_t sRxBuf1[RX_BUF_SIZE] __attribute__((aligned(4))); - -/* The RX Data Queue */ -static dataQueue_t sRxDataQueue = {0}; - -/* openthread data primatives */ -static otRadioFrame sTransmitFrame; -static otError sTransmitError; - -static __attribute__((aligned(4))) uint8_t sTransmitPsdu[OT_RADIO_FRAME_MAX_SIZE]; - -static volatile bool sTxCmdChainDone = false; - -/* - * Interrupt handlers forward declared for register functions. - */ -void RFCCPE0IntHandler(void); -void RFCCPE1IntHandler(void); - -/** - * Initialize the RX/TX buffers. - * - * Zeros out the receive and transmit buffers and sets up the data structures - * of the receive queue. - */ -static void rfCoreInitBufs(void) -{ - rfc_dataEntry_t *entry; - memset(sRxBuf0, 0x00, RX_BUF_SIZE); - memset(sRxBuf1, 0x00, RX_BUF_SIZE); - - entry = (rfc_dataEntry_t *)sRxBuf0; - entry->pNextEntry = sRxBuf1; - entry->config.lenSz = DATA_ENTRY_LENSZ_BYTE; - entry->length = sizeof(sRxBuf0) - sizeof(rfc_dataEntry_t); - - entry = (rfc_dataEntry_t *)sRxBuf1; - entry->pNextEntry = sRxBuf0; - entry->config.lenSz = DATA_ENTRY_LENSZ_BYTE; - entry->length = sizeof(sRxBuf1) - sizeof(rfc_dataEntry_t); - - sTransmitFrame.mPsdu = sTransmitPsdu; - sTransmitFrame.mLength = 0; -} - -/** - * Initialize the RX command structure. - * - * Sets the default values for the receive command structure. - */ -static void rfCoreInitReceiveParams(void) -{ - // clang-format off - static const rfc_CMD_IEEE_RX_t cReceiveCmd = - { - .commandNo = CMD_IEEE_RX, - .status = IDLE, - .pNextOp = NULL, - .startTime = 0u, - .startTrigger = - { - .triggerType = TRIG_NOW, - }, - .condition = { - .rule = COND_NEVER, - }, - .channel = CC2650_CHANNEL_MIN, - .rxConfig = - { - .bAutoFlushCrc = 1, - .bAutoFlushIgn = 0, - .bIncludePhyHdr = 0, - .bIncludeCrc = 0, - .bAppendRssi = 1, - .bAppendCorrCrc = 1, - .bAppendSrcInd = 0, - .bAppendTimestamp = 0, - }, - .frameFiltOpt = - { - .frameFiltEn = 1, - .frameFiltStop = 1, - .autoAckEn = 1, - .slottedAckEn = 0, - .autoPendEn = 0, - .defaultPend = 0, - .bPendDataReqOnly = 0, - .bPanCoord = 0, - .maxFrameVersion = 3, - .bStrictLenFilter = 1, - }, - .frameTypes = - { - .bAcceptFt0Beacon = 1, - .bAcceptFt1Data = 1, - .bAcceptFt2Ack = 1, - .bAcceptFt3MacCmd = 1, - .bAcceptFt4Reserved = 1, - .bAcceptFt5Reserved = 1, - .bAcceptFt6Reserved = 1, - .bAcceptFt7Reserved = 1, - }, - .ccaOpt = - { - .ccaEnEnergy = 1, - .ccaEnCorr = 1, - .ccaEnSync = 1, - .ccaCorrOp = 1, - .ccaSyncOp = 0, - .ccaCorrThr = 3, - }, - .ccaRssiThr = -90, - .endTrigger = - { - .triggerType = TRIG_NEVER, - }, - .endTime = 0u, - }; - // clang-format on - sReceiveCmd = cReceiveCmd; - - sReceiveCmd.pRxQ = &sRxDataQueue; - sReceiveCmd.pOutput = &sRfStats; - - sReceiveCmd.numShortEntries = CC2650_SHORTADD_SRC_MATCH_NUM; - sReceiveCmd.pShortEntryList = (void *)&sSrcMatchShortData; - - sReceiveCmd.numExtEntries = CC2650_EXTADD_SRC_MATCH_NUM; - sReceiveCmd.pExtEntryList = (uint32_t *)&sSrcMatchExtData; -} - -/** - * Sends the direct abort command to the radio core. - * - * @return The value from the command status register. - * @retval CMDSTA_Done The command completed correctly. - */ -static uint_fast8_t rfCoreExecuteAbortCmd(void) -{ - return (RFCDoorbellSendTo(CMDR_DIR_CMD(CMD_ABORT)) & 0xFF); -} - -/** - * Sends the direct ping command to the radio core. - * - * Check that the Radio core is alive and able to respond to commands. - * - * @return The value from the command status register. - * @retval CMDSTA_Done The command completed correctly. - */ -static uint_fast8_t rfCoreExecutePingCmd(void) -{ - return (RFCDoorbellSendTo(CMDR_DIR_CMD(CMD_PING)) & 0xFF); -} - -/** - * Sends the immediate clear rx queue command to the radio core. - * - * Uses the radio core to mark all of the entries in the receive queue as - * pending. This is used instead of clearing the entries manually to avoid race - * conditions between the main processor and the radio core. - * - * @param [in] aQueue A pointer to the receive queue to be cleared. - * - * @return The value from the command status register. - * @retval CMDSTA_Done The command completed correctly. - */ -static uint_fast8_t rfCoreClearReceiveQueue(dataQueue_t *aQueue) -{ - /* memset skipped because sClearReceiveQueueCmd has only 2 members and padding */ - sClearReceiveQueueCmd.commandNo = CMD_CLEAR_RX; - sClearReceiveQueueCmd.pQueue = aQueue; - - return (RFCDoorbellSendTo((uint32_t)&sClearReceiveQueueCmd) & 0xFF); -} - -/** - * Enable/disable frame filtering. - * - * Uses the radio core to alter the current running RX command filtering - * options. This ensures there is no access fault between the CM3 and CM0 for - * the RX command. - * - * This function leaves the type of frames to be filtered the same as the - * receive command. - * - * @note An IEEE RX command *must* be running while this command executes. - * - * @param [in] aEnable TRUE: enable frame filtering, - * FALSE: disable frame filtering. - * - * @return The value from the command status register. - * @retval CMDSTA_Done The command completed correctly. - */ -static uint_fast8_t rfCoreModifyRxFrameFilter(bool aEnable) -{ - /* memset skipped because sModifyReceiveFilterCmd has only 3 members */ - sModifyReceiveFilterCmd.commandNo = CMD_IEEE_MOD_FILT; - /* copy current frame filtering and frame types from running RX command */ - memcpy((void *)&sModifyReceiveFilterCmd.newFrameFiltOpt, (void *)&sReceiveCmd.frameFiltOpt, - sizeof(sModifyReceiveFilterCmd.newFrameFiltOpt)); - memcpy((void *)&sModifyReceiveFilterCmd.newFrameTypes, (void *)&sReceiveCmd.frameTypes, - sizeof(sModifyReceiveFilterCmd.newFrameTypes)); - - sModifyReceiveFilterCmd.newFrameFiltOpt.frameFiltEn = aEnable ? 1 : 0; - - return (RFCDoorbellSendTo((uint32_t)&sModifyReceiveFilterCmd) & 0xFF); -} - -/** - * Enable/disable autoPend feature. - * - * Uses the radio core to alter the current running RX command filtering - * options. This ensures there is no access fault between the CM3 and CM0 for - * the RX command. - * - * This function leaves the type of frames to be filtered the same as the - * receive command. - * - * @note An IEEE RX command *must* be running while this command executes. - * - * @param [in] aEnable TRUE: enable autoPend, - * FALSE: disable autoPend. - * - * @return The value from the command status register. - * @retval CMDSTA_Done The command completed correctly. - */ -static uint_fast8_t rfCoreModifyRxAutoPend(bool aEnable) -{ - /* memset skipped because sModifyReceiveFilterCmd has only 3 members */ - sModifyReceiveFilterCmd.commandNo = CMD_IEEE_MOD_FILT; - /* copy current frame filtering and frame types from running RX command */ - memcpy((void *)&sModifyReceiveFilterCmd.newFrameFiltOpt, (void *)&sReceiveCmd.frameFiltOpt, - sizeof(sModifyReceiveFilterCmd.newFrameFiltOpt)); - memcpy((void *)&sModifyReceiveFilterCmd.newFrameTypes, (void *)&sReceiveCmd.frameTypes, - sizeof(sModifyReceiveFilterCmd.newFrameTypes)); - - sModifyReceiveFilterCmd.newFrameFiltOpt.autoPendEn = aEnable ? 1 : 0; - - return (RFCDoorbellSendTo((uint32_t)&sModifyReceiveFilterCmd) & 0xFF); -} - -/** - * Sends the immediate modify source matching command to the radio core. - * - * Uses the radio core to alter the current source matching parameters used by - * the running RX command. This ensures there is no access fault between the - * CM3 and CM0, and ensures that the RX command has cohesive view of the data. - * The CM3 may make alterations to the source matching entries if the entry is - * marked as disabled. - * - * @note An IEEE RX command *must* be running while this command executes. - * - * @param [in] aEntryNo The index of the entry to alter. - * @param [in] aType TRUE: the entry is a short address, - * FALSE: the entry is an extended address. - * @param [in] aEnable Whether the given entry is to be enabled or disabled. - * - * @return The value from the command status register. - * @retval CMDSTA_Done The command completed correctly. - */ -static uint_fast8_t rfCoreModifySourceMatchEntry(uint8_t aEntryNo, cc2650_address_t aType, bool aEnable) -{ - /* memset kept to save 60 bytes of text space, gcc can't optimize the - * following bitfield operation if it doesn't know the fields are zero - * already. - */ - memset((void *)&sModifyReceiveSrcMatchCmd, 0, sizeof(sModifyReceiveSrcMatchCmd)); - - sModifyReceiveSrcMatchCmd.commandNo = CMD_IEEE_MOD_SRC_MATCH; - - /* we only use source matching for pending data bit, so enabling and - * pending are the same to us. - */ - if (aEnable) - { - sModifyReceiveSrcMatchCmd.options.bEnable = 1; - sModifyReceiveSrcMatchCmd.options.srcPend = 1; - } - else - { - sModifyReceiveSrcMatchCmd.options.bEnable = 0; - sModifyReceiveSrcMatchCmd.options.srcPend = 0; - } - - sModifyReceiveSrcMatchCmd.options.entryType = aType; - sModifyReceiveSrcMatchCmd.entryNo = aEntryNo; - - return (RFCDoorbellSendTo((uint32_t)&sModifyReceiveSrcMatchCmd) & 0xFF); -} - -/** - * Walks the short address source match list to find an address. - * - * @param [in] aAddress The short address to search for. - * - * @return The index where the address was found. - * @retval CC2650_SRC_MATCH_NONE The address was not found. - */ -static uint8_t rfCoreFindShortSrcMatchIdx(uint16_t aAddress) -{ - uint8_t i; - uint8_t ret = CC2650_SRC_MATCH_NONE; - - for (i = 0; i < CC2650_SHORTADD_SRC_MATCH_NUM; i++) - { - if (sSrcMatchShortData.extAddrEnt[i].shortAddr == aAddress) - { - ret = i; - break; - } - } - - return ret; -} - -/** - * Walks the short address source match list to find an empty slot. - * - * @return The index of an unused address slot. - * @retval CC2650_SRC_MATCH_NONE No unused slots available. - */ -static uint8_t rfCoreFindEmptyShortSrcMatchIdx(void) -{ - uint8_t i; - uint8_t ret = CC2650_SRC_MATCH_NONE; - - for (i = 0; i < CC2650_SHORTADD_SRC_MATCH_NUM; i++) - { - if ((sSrcMatchShortData.srcMatchEn[i / 32] & (1 << (i % 32))) == 0u) - { - ret = i; - break; - } - } - - return ret; -} - -/** - * Walks the extended address source match list to find an address. - * - * @param [in] aAddress The extended address to search for. - * - * @return The index where the address was found. - * @retval CC2650_SRC_MATCH_NONE The address was not found. - */ -static uint8_t rfCoreFindExtSrcMatchIdx(const uint64_t *aAddress) -{ - uint8_t i; - uint8_t ret = CC2650_SRC_MATCH_NONE; - - for (i = 0; i < CC2650_EXTADD_SRC_MATCH_NUM; i++) - { - if (sSrcMatchExtData.extAddrEnt[i] == *aAddress) - { - ret = i; - break; - } - } - - return ret; -} - -/** - * Walks the extended address source match list to find an empty slot. - * - * @return The index of an unused address slot. - * @retval CC2650_SRC_MATCH_NONE No unused slots available. - */ -static uint8_t rfCoreFindEmptyExtSrcMatchIdx(void) -{ - uint8_t i; - uint8_t ret = CC2650_SRC_MATCH_NONE; - - for (i = 0; i < CC2650_EXTADD_SRC_MATCH_NUM; i++) - { - if ((sSrcMatchExtData.srcMatchEn[i / 32] & (1 << (i % 32))) != 0u) - { - ret = i; - break; - } - } - - return ret; -} - -/** - * Sends the tx command to the radio core. - * - * Sends the packet to the radio core to be sent asynchronously. - * - * @note @ref aPsdu *must* be 4 byte aligned and not include the FCS. - * - * @param [in] aPsdu A pointer to the data to be sent. - * @param [in] aLen The length in bytes of data pointed to by PSDU. - * - * @return The value from the command status register. - * @retval CMDSTA_Done The command completed correctly. - */ -static uint_fast8_t rfCoreSendTransmitCmd(uint8_t *aPsdu, uint8_t aLen) -{ - // clang-format off - static const rfc_CMD_IEEE_CSMA_t cCsmacaBackoffCmd = - { - .commandNo = CMD_IEEE_CSMA, - .status = IDLE, - .startTrigger = - { - .triggerType = TRIG_NOW, - }, - .condition = { - .rule = COND_ALWAYS, - }, - .macMaxBE = IEEE802154_MAC_MAX_BE, - .macMaxCSMABackoffs = IEEE802154_MAC_MAX_CSMA_BACKOFFS, - .csmaConfig = - { - .initCW = 1, - .bSlotted = 0, - .rxOffMode = 0, - }, - .NB = 0, - .BE = IEEE802154_MAC_MIN_BE, - .remainingPeriods = 0, - .endTrigger = - { - .triggerType = TRIG_NEVER, - }, - .endTime = 0x00000000, - }; - static const rfc_CMD_IEEE_TX_t cTransmitCmd = - { - .commandNo = CMD_IEEE_TX, - .status = IDLE, - .startTrigger = - { - .triggerType = TRIG_NOW, - }, - .condition = { - .rule = COND_NEVER, - }, - .pNextOp = NULL, - }; - static const rfc_CMD_IEEE_RX_ACK_t cTransmitRxAckCmd = - { - .commandNo = CMD_IEEE_RX_ACK, - .status = IDLE, - .startTrigger = - { - .triggerType = TRIG_NOW, - }, - .endTrigger = - { - .triggerType = TRIG_REL_START, - .pastTrig = 1, - }, - .condition = { - .rule = COND_NEVER, - }, - .pNextOp = NULL, - /* number of RAT ticks to wait before claiming we haven't received an ack */ - .endTime = ((IEEE802154_MAC_ACK_WAIT_DURATION * CC2650_RAT_TICKS_PER_SEC) / IEEE802154_SYMBOLS_PER_SEC), - }; - // clang-format on - - /* reset retry count */ - sTransmitRetryCount = 0; - - sCsmacaBackoffCmd = cCsmacaBackoffCmd; - /* initialize the random state with a true random seed for the radio core's - * psudo rng */ - sCsmacaBackoffCmd.randomState = otRandomNonCryptoGetUint16(); - sCsmacaBackoffCmd.pNextOp = (rfc_radioOp_t *)&sTransmitCmd; - - sTransmitCmd = cTransmitCmd; - /* no need to look for an ack if the tx operation was stopped */ - sTransmitCmd.payloadLen = aLen; - sTransmitCmd.pPayload = aPsdu; - - if (aPsdu[0] & IEEE802154_ACK_REQUEST) - { - /* setup the receive ack command to follow the tx command */ - sTransmitCmd.condition.rule = COND_STOP_ON_FALSE; - sTransmitCmd.pNextOp = (rfc_radioOp_t *)&sTransmitRxAckCmd; - - sTransmitRxAckCmd = cTransmitRxAckCmd; - sTransmitRxAckCmd.seqNo = aPsdu[IEEE802154_DSN_OFFSET]; - } - - return (RFCDoorbellSendTo((uint32_t)&sCsmacaBackoffCmd) & 0xFF); -} - -/** - * Sends the rx command to the radio core. - * - * Sends the pre-built receive command to the radio core. This sets up the - * radio to receive packets according to the settings in the global rx command. - * - * @note This function does not alter any of the parameters of the rx command. - * It is only concerned with sending the command to the radio core. See @ref - * otPlatRadioSetPanId for an example of how the rx settings are set changed. - * - * @return The value from the command status register. - * @retval CMDSTA_Done The command completed correctly. - */ -static uint_fast8_t rfCoreSendReceiveCmd(void) -{ - sReceiveCmd.status = IDLE; - return (RFCDoorbellSendTo((uint32_t)&sReceiveCmd) & 0xFF); -} - -static uint_fast8_t rfCoreSendEdScanCmd(uint8_t aChannel, uint16_t aDurration) -{ - // clang-format off - static const rfc_CMD_IEEE_ED_SCAN_t cEdScanCmd = - { - .commandNo = CMD_IEEE_ED_SCAN, - .startTrigger = - { - .triggerType = TRIG_NOW, - }, - .condition = { - .rule = COND_NEVER, - }, - .ccaOpt = - { - .ccaEnEnergy = 1, - .ccaEnCorr = 1, - .ccaEnSync = 1, - .ccaCorrOp = 1, - .ccaSyncOp = 0, - .ccaCorrThr = 3, - }, - .ccaRssiThr = -90, - .endTrigger = - { - .triggerType = TRIG_REL_START, - .pastTrig = 1, - }, - }; - // clang-format on - sEdScanCmd = cEdScanCmd; - - sEdScanCmd.channel = aChannel; - - /* durration is in ms */ - sEdScanCmd.endTime = aDurration * (CC2650_RAT_TICKS_PER_SEC / 1000); - - return (RFCDoorbellSendTo((uint32_t)&sEdScanCmd) & 0xFF); -} - -/** - * Enables the cpe0 and cpe1 radio interrupts. - * - * Enables the @ref IRQ_LAST_COMMAND_DONE and @ref IRQ_LAST_FG_COMMAND_DONE to - * be handled by the @ref RFCCPE0IntHandler interrupt handler. - */ -static void rfCoreSetupInt(void) -{ - bool interruptsWereDisabled; - - otEXPECT(PRCMRfReady()); - - interruptsWereDisabled = IntMasterDisable(); - - /* Set all interrupt channels to CPE0 channel, error to CPE1 */ - HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEISL) = IRQ_INTERNAL_ERROR; - HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIEN) = IRQ_LAST_COMMAND_DONE | IRQ_LAST_FG_COMMAND_DONE; - - IntRegister(INT_RFC_CPE_0, RFCCPE0IntHandler); - IntRegister(INT_RFC_CPE_1, RFCCPE1IntHandler); - IntPendClear(INT_RFC_CPE_0); - IntPendClear(INT_RFC_CPE_1); - IntEnable(INT_RFC_CPE_0); - IntEnable(INT_RFC_CPE_1); - - if (!interruptsWereDisabled) - { - IntMasterEnable(); - } - -exit: - return; -} - -/** - * Disables and clears the cpe0 and cpe1 radio interrupts. - */ -static void rfCoreStopInt(void) -{ - bool interruptsWereDisabled; - - interruptsWereDisabled = IntMasterDisable(); - - /* clear and disable interrupts */ - HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0; - HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIEN) = 0x0; - - IntUnregister(INT_RFC_CPE_0); - IntUnregister(INT_RFC_CPE_1); - IntPendClear(INT_RFC_CPE_0); - IntPendClear(INT_RFC_CPE_1); - IntDisable(INT_RFC_CPE_0); - IntDisable(INT_RFC_CPE_1); - - if (!interruptsWereDisabled) - { - IntMasterEnable(); - } -} - -/** - * Sets the mode for the radio core to IEEE 802.15.4 - */ -static void rfCoreSetModeSelect(void) -{ - switch (ChipInfo_GetChipType()) - { - case CHIP_TYPE_CC2650: - HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = PRCM_RFCMODESEL_CURR_MODE5; - break; - - case CHIP_TYPE_CC2630: - HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = PRCM_RFCMODESEL_CURR_MODE2; - break; - - default: - /* This code must be run on a valid cc26xx chip */ - assert(false); - break; - } -} - -/** - * Turns on the radio core. - * - * Sets up the power and resources for the radio core. - * - switches the high frequency clock to the xosc crystal - * - sets the mode for the radio core to IEEE 802.15.4 - * - initializes the rx buffers and command - * - powers on the radio core power domain - * - enables the radio core power domain - * - sets up the interrupts - * - sends the ping command to the radio core to make sure it is running - * - * @return The value from the command status register. - * @retval CMDSTA_Done The command was received. - */ -static uint_fast8_t rfCorePowerOn(void) -{ - bool interruptsWereDisabled; - - /* Request the HF XOSC as the source for the HF clock. Needed before we can - * use the FS. This will only request, it will _not_ perform the switch. - */ - if (OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_XOSC_HF) - { - /* Request to switch to the crystal to enable radio operation. It takes a - * while for the XTAL to be ready so instead of performing the actual - * switch, we do other stuff while the XOSC is getting ready. - */ - OSCClockSourceSet(OSC_SRC_CLK_MF | OSC_SRC_CLK_HF, OSC_XOSC_HF); - } - - rfCoreSetModeSelect(); - - /* Set of RF Core data queue. Circular buffer, no last entry */ - sRxDataQueue.pCurrEntry = sRxBuf0; - sRxDataQueue.pLastEntry = NULL; - - rfCoreInitBufs(); - - /* - * Trigger a switch to the XOSC, so that we can subsequently use the RF FS - * This will block until the XOSC is actually ready, but give how we - * requested it early on, this won't be too long a wait. - * This should be done before starting the RAT. - */ - if (OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_XOSC_HF) - { - /* Switch the HF clock source (cc26xxware executes this from ROM) */ - OSCHfSourceSwitch(); - } - - interruptsWereDisabled = IntMasterDisable(); - - /* Enable RF Core power domain */ - PRCMPowerDomainOn(PRCM_DOMAIN_RFCORE); - - while (PRCMPowerDomainStatus(PRCM_DOMAIN_RFCORE) != PRCM_DOMAIN_POWER_ON) - ; - - PRCMDomainEnable(PRCM_DOMAIN_RFCORE); - PRCMLoadSet(); - - while (!PRCMLoadGet()) - ; - - rfCoreSetupInt(); - - if (!interruptsWereDisabled) - { - IntMasterEnable(); - } - - /* Let CPE boot */ - HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = - (RFC_PWR_PWMCLKEN_RFC_M | RFC_PWR_PWMCLKEN_CPE_M | RFC_PWR_PWMCLKEN_CPERAM_M); - - /* Send ping (to verify RFCore is ready and alive) */ - return rfCoreExecutePingCmd(); -} - -/** - * Turns off the radio core. - * - * Switches off the power and resources for the radio core. - * - disables the interrupts - * - disables the radio core power domain - * - powers off the radio core power domain - * - switches the high frequency clock to the rcosc to save power - */ -static void rfCorePowerOff(void) -{ - rfCoreStopInt(); - - PRCMDomainDisable(PRCM_DOMAIN_RFCORE); - PRCMLoadSet(); - - while (!PRCMLoadGet()) - ; - - PRCMPowerDomainOff(PRCM_DOMAIN_RFCORE); - - while (PRCMPowerDomainStatus(PRCM_DOMAIN_RFCORE) != PRCM_DOMAIN_POWER_OFF) - ; - - if (OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_RCOSC_HF) - { - /* Request to switch to the RC osc for low power mode. */ - OSCClockSourceSet(OSC_SRC_CLK_MF | OSC_SRC_CLK_HF, OSC_RCOSC_HF); - /* Switch the HF clock source (cc26xxware executes this from ROM) */ - OSCHfSourceSwitch(); - } -} - -/** - * Sends the setup command string to the radio core. - * - * Enables the clock line from the RTC to the RF core RAT. Enables the RAT - * timer and sets up the radio in IEEE mode. - * - * @return The value from the command status register. - * @retval CMDSTA_Done The command was received. - */ -static uint_fast16_t rfCoreSendEnableCmd(void) -{ - uint8_t doorbellRet; - bool interruptsWereDisabled; - uint_fast16_t ret; - - // clang-format off - static const rfc_CMD_SYNC_START_RAT_t cStartRatCmd = - { - .commandNo = CMD_SYNC_START_RAT, - .startTrigger = - { - .triggerType = TRIG_NOW, - }, - .condition = { - .rule = COND_STOP_ON_FALSE, - }, - }; - static const rfc_CMD_RADIO_SETUP_t cRadioSetupCmd = - { - .commandNo = CMD_RADIO_SETUP, - .startTrigger = - { - .triggerType = TRIG_NOW, - }, - .condition = { - .rule = COND_NEVER, - }, - .mode = 1, // IEEE 802.15.4 mode - }; - // clang-format on - /* turn on the clock line to the radio core */ - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RTC_UPD_EN_BITN) = 1; - - /* initialize the rat start command */ - sStartRatCmd = cStartRatCmd; - sStartRatCmd.pNextOp = (rfc_radioOp_t *)&sRadioSetupCmd; - sStartRatCmd.rat0 = sRatOffset; - - /* initialize radio setup command */ - sRadioSetupCmd = cRadioSetupCmd; - /* initally set the radio tx power to the max */ - sRadioSetupCmd.txPower = sCurrentOutputPower->value; - sRadioSetupCmd.pRegOverride = sIEEEOverrides; - - interruptsWereDisabled = IntMasterDisable(); - - doorbellRet = (RFCDoorbellSendTo((uint32_t)&sStartRatCmd) & 0xFF); - otEXPECT_ACTION(CMDSTA_Done == doorbellRet, ret = doorbellRet); - - /* synchronously wait for the CM0 to stop executing */ - while ((HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) & IRQ_LAST_COMMAND_DONE) == 0x00) - ; - - ret = sRadioSetupCmd.status; - -exit: - - if (!interruptsWereDisabled) - { - IntMasterEnable(); - } - - return ret; -} - -/** - * Sends the shutdown command string to the radio core. - * - * Powers down the frequency synthesizer and stops the RAT. - * - * @note synchronously waits until the command string completes. - * - * @return The status of the RAT stop command. - * @retval DONE_OK The command string executed properly. - */ -static uint_fast16_t rfCoreSendDisableCmd(void) -{ - uint8_t doorbellRet; - bool interruptsWereDisabled; - uint_fast16_t ret; - - // clang-format off - static const rfc_CMD_FS_POWERDOWN_t cFsPowerdownCmd = - { - .commandNo = CMD_FS_POWERDOWN, - .startTrigger = - { - .triggerType = TRIG_NOW, - }, - .condition = { - .rule = COND_ALWAYS, - }, - }; - static const rfc_CMD_SYNC_STOP_RAT_t cStopRatCmd = - { - .commandNo = CMD_SYNC_STOP_RAT, - .startTrigger = - { - .triggerType = TRIG_NOW, - }, - .condition = { - .rule = COND_NEVER, - }, - }; - // clang-format on - - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RTC_UPD_EN_BITN) = 1; - - /* initialize the command to power down the frequency synth */ - sFsPowerdownCmd = cFsPowerdownCmd; - sFsPowerdownCmd.pNextOp = (rfc_radioOp_t *)&sStopRatCmd; - - sStopRatCmd = cStopRatCmd; - - interruptsWereDisabled = IntMasterDisable(); - - HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = ~IRQ_LAST_COMMAND_DONE; - - doorbellRet = (RFCDoorbellSendTo((uint32_t)&sFsPowerdownCmd) & 0xFF); - otEXPECT_ACTION(CMDSTA_Done == doorbellRet, ret = doorbellRet); - - /* synchronously wait for the CM0 to stop */ - while ((HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) & IRQ_LAST_COMMAND_DONE) == 0x00) - ; - - ret = sStopRatCmd.status; - - if (sStopRatCmd.status == DONE_OK) - { - sRatOffset = sStopRatCmd.rat0; - } - -exit: - - if (!interruptsWereDisabled) - { - IntMasterEnable(); - } - - return ret; -} - -/** - * Error interrupt handler. - */ -void RFCCPE1IntHandler(void) -{ - /* Clear INTERNAL_ERROR interrupt flag */ - HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x7FFFFFFF; -} - -/** - * Command done handler. - */ -void RFCCPE0IntHandler(void) -{ - if (HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) & IRQ_LAST_COMMAND_DONE) - { - HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = ~IRQ_LAST_COMMAND_DONE; - - if (sState == cc2650_stateReceive && sReceiveCmd.status != ACTIVE && sReceiveCmd.status != IEEE_SUSPENDED) - { - /* the rx command was probably aborted to change the channel */ - sState = cc2650_stateSleep; - } - else if (sState == cc2650_stateEdScan) - { - sState = cc2650_stateSleep; - } - } - - if (HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) & IRQ_LAST_FG_COMMAND_DONE) - { - HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = ~IRQ_LAST_FG_COMMAND_DONE; - - if (sState == cc2650_stateTransmit) - { - if (sTransmitCmd.pPayload[0] & IEEE802154_ACK_REQUEST) - { - /* we are looking for an ack */ - switch (sTransmitRxAckCmd.status) - { - case IEEE_DONE_TIMEOUT: - if (sTransmitRetryCount < IEEE802154_MAC_MAX_FRAMES_RETRIES) - { - /* re-submit the tx command chain */ - sTransmitRetryCount++; - RFCDoorbellSendTo((uint32_t)&sCsmacaBackoffCmd); - } - else - { - sTransmitError = OT_ERROR_NO_ACK; - /* signal polling function we are done transmitting, we failed to send the packet */ - sTxCmdChainDone = true; - } - - break; - - case IEEE_DONE_ACK: - sTransmitError = OT_ERROR_NONE; - /* signal polling function we are done transmitting */ - sTxCmdChainDone = true; - break; - - case IEEE_DONE_ACKPEND: - sTransmitError = OT_ERROR_NONE; - /* signal polling function we are done transmitting */ - sTxCmdChainDone = true; - break; - - default: - sTransmitError = OT_ERROR_FAILED; - /* signal polling function we are done transmitting */ - sTxCmdChainDone = true; - break; - } - } - else - { - /* The TX command was either stopped or we are not looking for - * an ack */ - switch (sTransmitCmd.status) - { - case IEEE_DONE_OK: - sTransmitError = OT_ERROR_NONE; - break; - - case IEEE_DONE_TIMEOUT: - sTransmitError = OT_ERROR_CHANNEL_ACCESS_FAILURE; - break; - - case IEEE_ERROR_NO_SETUP: - case IEEE_ERROR_NO_FS: - case IEEE_ERROR_SYNTH_PROG: - sTransmitError = OT_ERROR_INVALID_STATE; - break; - - case IEEE_ERROR_TXUNF: - sTransmitError = OT_ERROR_NO_BUFS; - break; - - default: - sTransmitError = OT_ERROR_FAILED; - break; - } - - /* signal polling function we are done transmitting */ - sTxCmdChainDone = true; - } - } - } -} - -/** - * Function documented in platform-cc2650.h - */ -void cc2650RadioInit(void) -{ - /* Populate the RX parameters data structure with default values */ - rfCoreInitReceiveParams(); - - sState = cc2650_stateDisabled; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioEnable(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_BUSY; - - if (sState == cc2650_stateSleep) - { - error = OT_ERROR_NONE; - } - else if (sState == cc2650_stateDisabled) - { - otEXPECT_ACTION(rfCorePowerOn() == CMDSTA_Done, error = OT_ERROR_FAILED); - otEXPECT_ACTION(rfCoreSendEnableCmd() == DONE_OK, error = OT_ERROR_FAILED); - sState = cc2650_stateSleep; - error = OT_ERROR_NONE; - } - -exit: - - if (error == OT_ERROR_FAILED) - { - rfCorePowerOff(); - sState = cc2650_stateDisabled; - } - - return error; -} - -/** - * Function documented in platform/radio.h - */ -bool otPlatRadioIsEnabled(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - return (sState != cc2650_stateDisabled); -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioDisable(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_BUSY; - - if (sState == cc2650_stateDisabled) - { - error = OT_ERROR_NONE; - } - else if (sState == cc2650_stateSleep) - { - rfCoreSendDisableCmd(); - /* we don't want to fail if this command string doesn't work, just turn - * off the whole core - */ - rfCorePowerOff(); - sState = cc2650_stateDisabled; - error = OT_ERROR_NONE; - } - - return error; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioEnergyScan(otInstance *aInstance, uint8_t aScanChannel, uint16_t aScanDuration) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_BUSY; - - if (sState == cc2650_stateSleep) - { - sState = cc2650_stateEdScan; - otEXPECT_ACTION(rfCoreSendEdScanCmd(aScanChannel, aScanDuration) == CMDSTA_Done, error = OT_ERROR_FAILED); - error = OT_ERROR_NONE; - } - -exit: - return error; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioGetTransmitPower(otInstance *aInstance, int8_t *aPower) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_NONE; - - otEXPECT_ACTION(aPower != NULL, error = OT_ERROR_INVALID_ARGS); - *aPower = sCurrentOutputPower->dbm; - -exit: - return error; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioSetTransmitPower(otInstance *aInstance, int8_t aPower) -{ - OT_UNUSED_VARIABLE(aInstance); - - unsigned int i; - output_config_t const *powerCfg = &(rgOutputPower[0]); - - for (i = 1; i < OUTPUT_CONFIG_COUNT; i++) - { - if (rgOutputPower[i].dbm >= aPower) - { - powerCfg = &(rgOutputPower[i]); - } - else - { - break; - } - } - - sCurrentOutputPower = powerCfg; - - return OT_ERROR_NONE; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioGetCcaEnergyDetectThreshold(otInstance *aInstance, int8_t *aThreshold) -{ - OT_UNUSED_VARIABLE(aInstance); - OT_UNUSED_VARIABLE(aThreshold); - - return OT_ERROR_NOT_IMPLEMENTED; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioSetCcaEnergyDetectThreshold(otInstance *aInstance, int8_t aThreshold) -{ - OT_UNUSED_VARIABLE(aInstance); - OT_UNUSED_VARIABLE(aThreshold); - - return OT_ERROR_NOT_IMPLEMENTED; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioReceive(otInstance *aInstance, uint8_t aChannel) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_BUSY; - - if (sState == cc2650_stateSleep) - { - sState = cc2650_stateReceive; - - /* initialize the receive command - * XXX: no memset here because we assume init has been called and we - * may have changed some values in the rx command - */ - sReceiveCmd.channel = aChannel; - otEXPECT_ACTION(rfCoreSendReceiveCmd() == CMDSTA_Done, error = OT_ERROR_FAILED); - error = OT_ERROR_NONE; - } - else if (sState == cc2650_stateReceive) - { - if (sReceiveCmd.status == ACTIVE && sReceiveCmd.channel == aChannel) - { - /* we are already running on the right channel */ - sState = cc2650_stateReceive; - error = OT_ERROR_NONE; - } - else - { - /* we have either not fallen back into our receive command or - * we are running on the wrong channel. Either way assume the - * caller correctly called us and abort all running commands. - */ - otEXPECT_ACTION(rfCoreExecuteAbortCmd() == CMDSTA_Done, error = OT_ERROR_FAILED); - - /* any frames in the queue will be for the old channel */ - otEXPECT_ACTION(rfCoreClearReceiveQueue(&sRxDataQueue) == CMDSTA_Done, error = OT_ERROR_FAILED); - - sReceiveCmd.channel = aChannel; - otEXPECT_ACTION(rfCoreSendReceiveCmd() == CMDSTA_Done, error = OT_ERROR_FAILED); - - sState = cc2650_stateReceive; - error = OT_ERROR_NONE; - } - } - -exit: - return error; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioSleep(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_BUSY; - - if (sState == cc2650_stateSleep) - { - error = OT_ERROR_NONE; - } - else if (sState == cc2650_stateReceive) - { - if (rfCoreExecuteAbortCmd() != CMDSTA_Done) - { - error = OT_ERROR_BUSY; - } - else - { - sState = cc2650_stateSleep; - } - } - - return error; -} - -/** - * Function documented in platform/radio.h - */ -otRadioFrame *otPlatRadioGetTransmitBuffer(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - return &sTransmitFrame; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame) -{ - otError error = OT_ERROR_BUSY; - - if (sState == cc2650_stateReceive) - { - sState = cc2650_stateTransmit; - - /* removing 2 bytes of CRC placeholder because we generate that in hardware */ - otEXPECT_ACTION(rfCoreSendTransmitCmd(aFrame->mPsdu, aFrame->mLength - 2) == CMDSTA_Done, - error = OT_ERROR_FAILED); - error = OT_ERROR_NONE; - sTransmitError = OT_ERROR_NONE; - sTxCmdChainDone = false; - otPlatRadioTxStarted(aInstance, aFrame); - } - -exit: - return error; -} - -/** - * Function documented in platform/radio.h - */ -int8_t otPlatRadioGetRssi(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - return sRfStats.maxRssi; -} - -/** - * Function documented in platform/radio.h - */ -otRadioCaps otPlatRadioGetCaps(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - return OT_RADIO_CAPS_ACK_TIMEOUT | OT_RADIO_CAPS_ENERGY_SCAN | OT_RADIO_CAPS_TRANSMIT_RETRIES; -} - -/** - * Function documented in platform/radio.h - */ -void otPlatRadioEnableSrcMatch(otInstance *aInstance, bool aEnable) -{ - OT_UNUSED_VARIABLE(aInstance); - - if (sReceiveCmd.status == ACTIVE || sReceiveCmd.status == IEEE_SUSPENDED) - { - /* we have a running or backgrounded rx command */ - rfCoreModifyRxAutoPend(aEnable); - } - else - { - /* if we are promiscuous, then frame filtering should be disabled */ - sReceiveCmd.frameFiltOpt.autoPendEn = aEnable ? 1 : 0; - } -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, uint16_t aShortAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_NONE; - uint8_t idx = rfCoreFindShortSrcMatchIdx(aShortAddress); - - if (idx == CC2650_SRC_MATCH_NONE) - { - /* the entry does not exist already, add it */ - otEXPECT_ACTION((idx = rfCoreFindEmptyShortSrcMatchIdx()) != CC2650_SRC_MATCH_NONE, error = OT_ERROR_NO_BUFS); - sSrcMatchShortData.extAddrEnt[idx].shortAddr = aShortAddress; - sSrcMatchShortData.extAddrEnt[idx].panId = sReceiveCmd.localPanID; - } - - if (sReceiveCmd.status == ACTIVE || sReceiveCmd.status == IEEE_SUSPENDED) - { - /* we have a running or backgrounded rx command */ - otEXPECT_ACTION(rfCoreModifySourceMatchEntry(idx, SHORT_ADDRESS, true) == CMDSTA_Done, error = OT_ERROR_FAILED); - } - else - { - /* we are not running, so we must update the values ourselves */ - sSrcMatchShortData.srcPendEn[idx / 32] |= (1 << (idx % 32)); - sSrcMatchShortData.srcMatchEn[idx / 32] |= (1 << (idx % 32)); - } - -exit: - return error; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, uint16_t aShortAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_NONE; - uint8_t idx; - - otEXPECT_ACTION((idx = rfCoreFindShortSrcMatchIdx(aShortAddress)) != CC2650_SRC_MATCH_NONE, - error = OT_ERROR_NO_ADDRESS); - - if (sReceiveCmd.status == ACTIVE || sReceiveCmd.status == IEEE_SUSPENDED) - { - /* we have a running or backgrounded rx command */ - otEXPECT_ACTION(rfCoreModifySourceMatchEntry(idx, SHORT_ADDRESS, false) == CMDSTA_Done, - error = OT_ERROR_FAILED); - } - else - { - /* we are not running, so we must update the values ourselves */ - sSrcMatchShortData.srcPendEn[idx / 32] &= ~(1 << (idx % 32)); - sSrcMatchShortData.srcMatchEn[idx / 32] &= ~(1 << (idx % 32)); - } - -exit: - return error; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const otExtAddress *aExtAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_NONE; - uint64_t extAddress = otEncodingReadUint64Le(aExtAddress->m8); - uint8_t idx = rfCoreFindExtSrcMatchIdx(&extAddress); - - if (idx == CC2650_SRC_MATCH_NONE) - { - /* the entry does not exist already, add it */ - otEXPECT_ACTION((idx = rfCoreFindEmptyExtSrcMatchIdx()) != CC2650_SRC_MATCH_NONE, error = OT_ERROR_NO_BUFS); - sSrcMatchExtData.extAddrEnt[idx] = extAddress; - } - - if (sReceiveCmd.status == ACTIVE || sReceiveCmd.status == IEEE_SUSPENDED) - { - /* we have a running or backgrounded rx command */ - otEXPECT_ACTION(rfCoreModifySourceMatchEntry(idx, EXT_ADDRESS, true) == CMDSTA_Done, error = OT_ERROR_FAILED); - } - else - { - /* we are not running, so we must update the values ourselves */ - sSrcMatchExtData.srcPendEn[idx / 32] |= (1 << (idx % 32)); - sSrcMatchExtData.srcMatchEn[idx / 32] |= (1 << (idx % 32)); - } - -exit: - return error; -} - -/** - * Function documented in platform/radio.h - */ -otError otPlatRadioClearSrcMatchExtEntry(otInstance *aInstance, const otExtAddress *aExtAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - otError error = OT_ERROR_NONE; - uint64_t extAddress = otEncodingReadUint64Le(aExtAddress->m8); - uint8_t idx; - - otEXPECT_ACTION((idx = rfCoreFindExtSrcMatchIdx(&extAddress)) != CC2650_SRC_MATCH_NONE, - error = OT_ERROR_NO_ADDRESS); - - if (sReceiveCmd.status == ACTIVE || sReceiveCmd.status == IEEE_SUSPENDED) - { - /* we have a running or backgrounded rx command */ - otEXPECT_ACTION(rfCoreModifySourceMatchEntry(idx, EXT_ADDRESS, false) == CMDSTA_Done, error = OT_ERROR_FAILED); - } - else - { - /* we are not running, so we must update the values ourselves */ - sSrcMatchExtData.srcPendEn[idx / 32] &= ~(1 << (idx % 32)); - sSrcMatchExtData.srcMatchEn[idx / 32] &= ~(1 << (idx % 32)); - } - -exit: - return error; -} - -/** - * Function documented in platform/radio.h - */ -void otPlatRadioClearSrcMatchShortEntries(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - if (sReceiveCmd.status == ACTIVE || sReceiveCmd.status == IEEE_SUSPENDED) - { - unsigned int i; - - for (i = 0; i < CC2650_SHORTADD_SRC_MATCH_NUM; i++) - { - /* we have a running or backgrounded rx command */ - otEXPECT(rfCoreModifySourceMatchEntry(i, SHORT_ADDRESS, false) == CMDSTA_Done); - } - } - else - { - /* we are not running, so we can erase them ourselves */ - memset((void *)&sSrcMatchShortData, 0, sizeof(sSrcMatchShortData)); - } - -exit: - return; -} - -/** - * Function documented in platform/radio.h - */ -void otPlatRadioClearSrcMatchExtEntries(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - - if (sReceiveCmd.status == ACTIVE || sReceiveCmd.status == IEEE_SUSPENDED) - { - unsigned int i; - - for (i = 0; i < CC2650_EXTADD_SRC_MATCH_NUM; i++) - { - /* we have a running or backgrounded rx command */ - otEXPECT(rfCoreModifySourceMatchEntry(i, EXT_ADDRESS, false) == CMDSTA_Done); - } - } - else - { - /* we are not running, so we can erase them ourselves */ - memset((void *)&sSrcMatchExtData, 0, sizeof(sSrcMatchExtData)); - } - -exit: - return; -} - -/** - * Function documented in platform/radio.h - */ -bool otPlatRadioGetPromiscuous(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - /* we are promiscuous if we are not filtering */ - return sReceiveCmd.frameFiltOpt.frameFiltEn == 0; -} - -/** - * Function documented in platform/radio.h - */ -void otPlatRadioSetPromiscuous(otInstance *aInstance, bool aEnable) -{ - OT_UNUSED_VARIABLE(aInstance); - - if (sReceiveCmd.status == ACTIVE || sReceiveCmd.status == IEEE_SUSPENDED) - { - /* we have a running or backgrounded rx command */ - /* if we are promiscuous, then frame filtering should be disabled */ - rfCoreModifyRxFrameFilter(!aEnable); - /* XXX should we dump any queued messages ? */ - } - else - { - /* if we are promiscuous, then frame filtering should be disabled */ - sReceiveCmd.frameFiltOpt.frameFiltEn = aEnable ? 0 : 1; - } -} - -/** - * Function documented in platform/radio.h - */ -void otPlatRadioGetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64) -{ - uint8_t * eui64; - unsigned int i; - - OT_UNUSED_VARIABLE(aInstance); - - /* The IEEE MAC address can be stored two places. We check the Customer - * Configuration was not set before defaulting to the Factory - * Configuration. - */ - eui64 = (uint8_t *)(CCFG_BASE + CCFG_O_IEEE_MAC_0); - - for (i = 0; i < OT_EXT_ADDRESS_SIZE; i++) - { - if (eui64[i] != CC2650_UNKNOWN_EUI64) - { - break; - } - } - - if (i >= OT_EXT_ADDRESS_SIZE) - { - /* The ccfg address was all 0xFF, switch to the fcfg */ - eui64 = (uint8_t *)(FCFG1_BASE + FCFG1_O_MAC_15_4_0); - } - - /* The IEEE MAC address is stored in network byte order (big endian). - * The caller seems to want the address stored in little endian format, - * which is backwards of the conventions setup by @ref - * otPlatRadioSetExtendedAddress. otPlatRadioSetExtendedAddress assumes - * that the address being passed to it is in network byte order (big - * endian), so the caller of otPlatRadioSetExtendedAddress must swap the - * endianness before calling. - * - * It may be easier to have the caller of this function store the IEEE - * address in network byte order (big endian). - */ - for (i = 0; i < OT_EXT_ADDRESS_SIZE; i++) - { - aIeeeEui64[i] = eui64[(OT_EXT_ADDRESS_SIZE - 1) - i]; - } -} - -/** - * Function documented in platform/radio.h - * - * @note it is entirely possible for this function to fail, but there is no - * valid way to return that error since the function prototype was changed. - */ -void otPlatRadioSetPanId(otInstance *aInstance, uint16_t aPanid) -{ - OT_UNUSED_VARIABLE(aInstance); - - /* XXX: if the pan id is the broadcast pan id (0xFFFF) the auto ack will - * not work. This is due to the design of the CM0 and follows IEEE 802.15.4 - */ - if (sState == cc2650_stateReceive) - { - otEXPECT(rfCoreExecuteAbortCmd() == CMDSTA_Done); - sReceiveCmd.localPanID = aPanid; - otEXPECT(rfCoreClearReceiveQueue(&sRxDataQueue) == CMDSTA_Done); - otEXPECT(rfCoreSendReceiveCmd() == CMDSTA_Done); - /* the interrupt from abort changed our state to sleep */ - sState = cc2650_stateReceive; - } - else if (sState != cc2650_stateTransmit) - { - sReceiveCmd.localPanID = aPanid; - } - -exit: - return; -} - -/** - * Function documented in platform/radio.h - * - * @note it is entirely possible for this function to fail, but there is no - * valid way to return that error since the function prototype was changed. - */ -void otPlatRadioSetExtendedAddress(otInstance *aInstance, const otExtAddress *aAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - /* XXX: assuming little endian format */ - if (sState == cc2650_stateReceive) - { - otEXPECT(rfCoreExecuteAbortCmd() == CMDSTA_Done); - sReceiveCmd.localExtAddr = otEncodingReadUint64Le(aAddress->m8); - otEXPECT(rfCoreClearReceiveQueue(&sRxDataQueue) == CMDSTA_Done); - otEXPECT(rfCoreSendReceiveCmd() == CMDSTA_Done); - /* the interrupt from abort changed our state to sleep */ - sState = cc2650_stateReceive; - } - else if (sState != cc2650_stateTransmit) - { - sReceiveCmd.localExtAddr = otEncodingReadUint64Le(aAddress->m8); - } - -exit: - return; -} - -/** - * Function documented in platform/radio.h - * - * @note it is entirely possible for this function to fail, but there is no - * valid way to return that error since the function prototype was changed. - */ -void otPlatRadioSetShortAddress(otInstance *aInstance, uint16_t aAddress) -{ - OT_UNUSED_VARIABLE(aInstance); - - if (sState == cc2650_stateReceive) - { - otEXPECT(rfCoreExecuteAbortCmd() == CMDSTA_Done); - sReceiveCmd.localShortAddr = aAddress; - otEXPECT(rfCoreClearReceiveQueue(&sRxDataQueue) == CMDSTA_Done); - otEXPECT(rfCoreSendReceiveCmd() == CMDSTA_Done); - /* the interrupt from abort changed our state to sleep */ - sState = cc2650_stateReceive; - } - else if (sState != cc2650_stateTransmit) - { - sReceiveCmd.localShortAddr = aAddress; - } - -exit: - return; -} - -static void cc2650RadioProcessTransmitDone(otInstance * aInstance, - otRadioFrame *aTransmitFrame, - otRadioFrame *aAckFrame, - otError aTransmitError) -{ -#if OPENTHREAD_CONFIG_DIAG_ENABLE - - if (otPlatDiagModeGet()) - { - otPlatDiagRadioTransmitDone(aInstance, aTransmitFrame, aTransmitError); - } - else -#endif /* OPENTHREAD_CONFIG_DIAG_ENABLE */ - { - otPlatRadioTxDone(aInstance, aTransmitFrame, aAckFrame, aTransmitError); - } -} - -static void cc2650RadioProcessReceiveDone(otInstance *aInstance, otRadioFrame *aReceiveFrame, otError aReceiveError) -{ - // TODO Set this flag only when the packet is really acknowledged with frame pending set. - // See https://github.com/openthread/openthread/pull/3785 - aReceiveFrame->mInfo.mRxInfo.mAckedWithFramePending = true; -#if OPENTHREAD_CONFIG_DIAG_ENABLE - - if (otPlatDiagModeGet()) - { - otPlatDiagRadioReceiveDone(aInstance, aReceiveFrame, aReceiveError); - } - else -#endif /* OPENTHREAD_CONFIG_DIAG_ENABLE */ - { - otPlatRadioReceiveDone(aInstance, aReceiveFrame, aReceiveError); - } -} - -static void cc2650RadioProcessReceiveQueue(otInstance *aInstance) -{ - rfc_ieeeRxCorrCrc_t * crcCorr; - rfc_dataEntryGeneral_t *curEntry, *startEntry; - uint8_t rssi; - - startEntry = (rfc_dataEntryGeneral_t *)sRxDataQueue.pCurrEntry; - curEntry = startEntry; - - /* loop through receive queue */ - do - { - uint8_t *payload = &(curEntry->data); - - if (curEntry->status == DATA_ENTRY_FINISHED) - { - uint8_t len; - otError receiveError; - otRadioFrame receiveFrame; - - /* get the information appended to the end of the frame. - * This array access looks like it is a fencepost error, but the - * first byte is the number of bytes that follow. - */ - len = payload[0]; - crcCorr = (rfc_ieeeRxCorrCrc_t *)&payload[len]; - rssi = payload[len - 1]; - - if (crcCorr->status.bCrcErr == 0 && (len - 2) < OT_RADIO_FRAME_MAX_SIZE) - { -#if OPENTHREAD_CONFIG_TIME_SYNC_ENABLE -#error Time sync requires the timestamp of SFD rather than that of rx done! -#else - if (otPlatRadioGetPromiscuous(aInstance)) -#endif - { - // TODO: Propagate CM0 timestamp - // The current driver only supports milliseconds resolution. - receiveFrame.mInfo.mRxInfo.mTimestamp = otPlatAlarmMilliGetNow() * 1000; - } - - receiveFrame.mLength = len; - receiveFrame.mPsdu = &(payload[1]); - receiveFrame.mChannel = sReceiveCmd.channel; - receiveFrame.mInfo.mRxInfo.mRssi = rssi; - receiveFrame.mInfo.mRxInfo.mLqi = crcCorr->status.corr; - - receiveError = OT_ERROR_NONE; - } - else - { - receiveError = OT_ERROR_FCS; - } - - if ((receiveFrame.mPsdu[0] & IEEE802154_FRAME_TYPE_MASK) == IEEE802154_FRAME_TYPE_ACK) - { - if (receiveFrame.mPsdu[IEEE802154_DSN_OFFSET] == sTransmitFrame.mPsdu[IEEE802154_DSN_OFFSET]) - { - sState = cc2650_stateReceive; - cc2650RadioProcessTransmitDone(aInstance, &sTransmitFrame, &receiveFrame, receiveError); - } - } - else - { - cc2650RadioProcessReceiveDone(aInstance, &receiveFrame, receiveError); - } - - curEntry->status = DATA_ENTRY_PENDING; - break; - } - else if (curEntry->status == DATA_ENTRY_UNFINISHED) - { - curEntry->status = DATA_ENTRY_PENDING; - } - - curEntry = (rfc_dataEntryGeneral_t *)(curEntry->pNextEntry); - } while (curEntry != startEntry); -} - -/** - * Function documented in platform-cc2650.h - */ -void cc2650RadioProcess(otInstance *aInstance) -{ - if (sState == cc2650_stateEdScan) - { - if (sEdScanCmd.status == IEEE_DONE_OK) - { - otPlatRadioEnergyScanDone(aInstance, sEdScanCmd.maxRssi); - } - else if (sEdScanCmd.status == ACTIVE) - { - otPlatRadioEnergyScanDone(aInstance, CC2650_INVALID_RSSI); - } - } - - if (sState == cc2650_stateReceive || sState == cc2650_stateTransmit) - { - cc2650RadioProcessReceiveQueue(aInstance); - } - - if (sTxCmdChainDone) - { - if (sState == cc2650_stateTransmit) - { - /* we are not looking for an ACK packet, or failed */ - sState = cc2650_stateReceive; - cc2650RadioProcessTransmitDone(aInstance, &sTransmitFrame, NULL, sTransmitError); - } - - sTransmitError = OT_ERROR_NONE; - sTxCmdChainDone = false; - } -} - -int8_t otPlatRadioGetReceiveSensitivity(otInstance *aInstance) -{ - OT_UNUSED_VARIABLE(aInstance); - return CC2650_RECEIVE_SENSITIVITY; -} diff --git a/examples/platforms/cc2650/system.c b/examples/platforms/cc2650/system.c deleted file mode 100644 index 90cac5e76..000000000 --- a/examples/platforms/cc2650/system.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "platform-cc2650.h" -#include -#include "inc/hw_ccfg_simple_struct.h" - -extern const ccfg_t __ccfg; - -void *dummy_ccfg_ref = ((void *)(&(__ccfg))); - -/** - * Function documented in platform-cc2650.h - */ -void otSysInit(int argc, char *argv[]) -{ - OT_UNUSED_VARIABLE(argc); - OT_UNUSED_VARIABLE(argv); - - while (dummy_ccfg_ref == NULL) - { - /* - * This provides a code reference to the customer configuration - * area of the flash, otherwise the data is skipped by the - * linker and not put into the final flash image. - */ - } - - cc2650AlarmInit(); - cc2650RandomInit(); - cc2650RadioInit(); -} - -bool otSysPseudoResetWasRequested(void) -{ - return false; -} - -/** - * Function documented in platform-cc2650.h - */ -void otSysProcessDrivers(otInstance *aInstance) -{ - // should sleep and wait for interrupts here - - cc2650UartProcess(); - cc2650RadioProcess(aInstance); - cc2650AlarmProcess(aInstance); -} diff --git a/examples/platforms/cc2650/uart.c b/examples/platforms/cc2650/uart.c deleted file mode 100644 index 44515fa44..000000000 --- a/examples/platforms/cc2650/uart.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2017, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include - -#include - -#include "utils/uart.h" - -/** - * \note this will configure the uart for 115200 baud 8-N-1, no HW flow control - * RX pin IOID_2 TX pin IOID_3 - * - * \note make sure that data being sent is not in a volatile area - */ - -enum -{ - CC2650_RECV_CIRC_BUFF_SIZE = 256, -}; - -static uint8_t const *sSendBuffer = NULL; -static uint16_t sSendLen = 0; - -static uint8_t sReceiveBuffer[CC2650_RECV_CIRC_BUFF_SIZE]; -static uint16_t sReceiveHeadIdx = 0; -static uint16_t sReceiveTailIdx = 0; - -void UART0_intHandler(void); - -/** - * Function documented in utils/uart.h - */ -otError otPlatUartEnable(void) -{ - PRCMPowerDomainOn(PRCM_DOMAIN_SERIAL); - - while (PRCMPowerDomainStatus(PRCM_DOMAIN_SERIAL) != PRCM_DOMAIN_POWER_ON) - ; - - PRCMPeripheralRunEnable(PRCM_PERIPH_UART0); - PRCMPeripheralSleepEnable(PRCM_PERIPH_UART0); - PRCMPeripheralDeepSleepEnable(PRCM_PERIPH_UART0); - PRCMLoadSet(); - - while (!PRCMLoadGet()) - ; - - IOCPinTypeUart(UART0_BASE, IOID_2, IOID_3, IOID_UNUSED, IOID_UNUSED); - - UARTConfigSetExpClk(UART0_BASE, SysCtrlClockGet(), 115200, - UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE); - UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT); - UARTIntRegister(UART0_BASE, UART0_intHandler); - UARTEnable(UART0_BASE); - return OT_ERROR_NONE; -} - -/** - * Function documented in utils/uart.h - */ -otError otPlatUartDisable(void) -{ - UARTDisable(UART0_BASE); - UARTIntUnregister(UART0_BASE); - UARTIntDisable(UART0_BASE, UART_INT_RX | UART_INT_RT); - IOCPortConfigureSet(IOID_2, IOC_PORT_GPIO, IOC_STD_INPUT); - IOCPortConfigureSet(IOID_3, IOC_PORT_GPIO, IOC_STD_INPUT); - - PRCMPeripheralRunDisable(PRCM_PERIPH_UART0); - PRCMPeripheralSleepDisable(PRCM_PERIPH_UART0); - PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_UART0); - PRCMLoadSet(); - /** - * \warn this assumes that there are no other devices being used in the - * serial power domain - */ - PRCMPowerDomainOff(PRCM_DOMAIN_SERIAL); - return OT_ERROR_NONE; -} - -/** - * Function documented in utils/uart.h - */ -otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength) -{ - otError error = OT_ERROR_NONE; - otEXPECT_ACTION(sSendBuffer == NULL, error = OT_ERROR_BUSY); - - sSendBuffer = aBuf; - sSendLen = aBufLength; - -exit: - return error; -} - -/** - * @brief process the receive side of the buffers - */ -static void processReceive(void) -{ - while (sReceiveHeadIdx != sReceiveTailIdx) - { - uint16_t tailIdx; - - if (sReceiveHeadIdx < sReceiveTailIdx) - { - tailIdx = sReceiveTailIdx; - otPlatUartReceived(&(sReceiveBuffer[sReceiveHeadIdx]), tailIdx - sReceiveHeadIdx); - sReceiveHeadIdx = tailIdx; - } - else - { - tailIdx = CC2650_RECV_CIRC_BUFF_SIZE; - otPlatUartReceived(&(sReceiveBuffer[sReceiveHeadIdx]), tailIdx - sReceiveHeadIdx); - sReceiveHeadIdx = 0; - } - } -} - -otError otPlatUartFlush(void) -{ - otEXPECT(sSendBuffer != NULL); - - for (; sSendLen > 0; sSendLen--) - { - UARTCharPut(UART0_BASE, *sSendBuffer); - sSendBuffer++; - } - - sSendBuffer = NULL; - sSendLen = 0; - - return OT_ERROR_NONE; - -exit: - return OT_ERROR_INVALID_STATE; -} - -/** - * @brief process the transmit side of the buffers - */ -static void processTransmit(void) -{ - otPlatUartFlush(); - otPlatUartSendDone(); -} - -/** - * Function documented in platform-cc2650.h - */ -void cc2650UartProcess(void) -{ - processReceive(); - processTransmit(); -} - -/** - * @brief the interrupt handler for the uart interrupt vector - */ -void UART0_intHandler(void) -{ - while (UARTCharsAvail(UART0_BASE)) - { - uint32_t c = UARTCharGet(UART0_BASE); - /* XXX process error flags for this character ?? */ - sReceiveBuffer[sReceiveTailIdx] = (uint8_t)c; - sReceiveTailIdx++; - - if (sReceiveTailIdx >= CC2650_RECV_CIRC_BUFF_SIZE) - { - sReceiveTailIdx = 0; - } - } -} diff --git a/script/check-arm-build-autotools b/script/check-arm-build-autotools index d45b5da1b..ebccd4e7a 100755 --- a/script/check-arm-build-autotools +++ b/script/check-arm-build-autotools @@ -51,12 +51,6 @@ build_cc2538() make -f examples/Makefile-cc2538 "${options[@]}" } -build_cc2650() -{ - reset_source - make -f examples/Makefile-cc2650 -} - build_jn5189() { local options=( @@ -213,7 +207,6 @@ main() if [[ $# == 0 ]]; then build_cc2538 - build_cc2650 build_jn5189 build_k32w061 build_nrf52811 diff --git a/script/check-arm-build-cmake b/script/check-arm-build-cmake index 7f18c0947..5ff52f6d9 100755 --- a/script/check-arm-build-cmake +++ b/script/check-arm-build-cmake @@ -59,12 +59,6 @@ build_cc2538() "$(dirname "$0")"/cmake-build cc2538 "${OT_COMMON_OPTIONS[@]}" "${OT_BASIC_CHECK_OPTIONS[@]}" "${options[@]}" } -build_cc2650() -{ - reset_source - "$(dirname "$0")"/cmake-build cc2650 "${OT_COMMON_OPTIONS[@]}" -} - build_nrf52811() { reset_source @@ -89,7 +83,6 @@ main() if [[ $# == 0 ]]; then build_cc2538 - build_cc2650 # UART transport build_nrf52840 UART_trans # USB transport with bootloader e.g. to support PCA10059 dongle diff --git a/script/cmake-build b/script/cmake-build index 27e54bed9..813304e84 100755 --- a/script/cmake-build +++ b/script/cmake-build @@ -79,7 +79,7 @@ set -euxo pipefail OT_CMAKE_NINJA_TARGET=${OT_CMAKE_NINJA_TARGET:-} readonly OT_SRCDIR="$(pwd)" -readonly OT_PLATFORMS=(cc2538 cc2650 efr32mg1 efr32mg12 efr32mg13 efr32mg21 nrf52811 nrf52833 nrf52840 simulation posix) +readonly OT_PLATFORMS=(cc2538 efr32mg1 efr32mg12 efr32mg13 efr32mg21 nrf52811 nrf52833 nrf52840 simulation posix) readonly OT_NRF528XX_BUILD_TYPES=(UART_trans USB_trans_bl SPI_trans_NCP soft_crypto soft_crypto_threading) readonly OT_POSIX_SIM_COMMON_OPTIONS=( "-DOT_BORDER_AGENT=ON" @@ -228,10 +228,6 @@ main() local_options=("-DOT_LINK_RAW=ON") options+=("${OT_POSIX_SIM_COMMON_OPTIONS[@]}" "${local_options[@]}") ;; - cc2650) - OT_CMAKE_NINJA_TARGET=("ot-cli-mtd" "ot-ncp-mtd") - options+=("-DCMAKE_TOOLCHAIN_FILE=examples/platforms/${platform}/arm-none-eabi.cmake" "-DCMAKE_BUILD_TYPE=MinSizeRel") - ;; cc2538) options+=("-DCMAKE_TOOLCHAIN_FILE=examples/platforms/${platform}/arm-none-eabi.cmake" "-DCMAKE_BUILD_TYPE=MinSizeRel") ;; diff --git a/third_party/CMakeLists.txt b/third_party/CMakeLists.txt index 1a0a71a60..6dfc47e3a 100644 --- a/third_party/CMakeLists.txt +++ b/third_party/CMakeLists.txt @@ -30,9 +30,7 @@ if(NOT OT_EXTERNAL_MBEDTLS) add_subdirectory(mbedtls) endif() -if(OT_PLATFORM MATCHES "cc*") - add_subdirectory(ti) -elseif(OT_PLATFORM MATCHES "^nrf*") +if(OT_PLATFORM MATCHES "^nrf*") add_subdirectory(jlink) add_subdirectory(NordicSemiconductor) elseif(OT_PLATFORM MATCHES "^efr*") diff --git a/third_party/ti/CMakeLists.txt b/third_party/ti/CMakeLists.txt deleted file mode 100644 index dd5cfae7b..000000000 --- a/third_party/ti/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# -# Copyright (c) 2020, The OpenThread Authors. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of the copyright holder nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if(OT_PLATFORM STREQUAL "cc2650") - add_library(cc26x0-driver INTERFACE) - - target_link_libraries(cc26x0-driver - INTERFACE - ${CMAKE_CURRENT_SOURCE_DIR}/devices/cc26x0/driverlib/bin/gcc/driverlib.a - -T${CMAKE_CURRENT_SOURCE_DIR}/devices/cc26x0/linker_files/cc26x0f128.lds - ) -endif() diff --git a/third_party/ti/README.md b/third_party/ti/README.md deleted file mode 100644 index 68f392a6a..000000000 --- a/third_party/ti/README.md +++ /dev/null @@ -1,40 +0,0 @@ -#CC26XXware - -## URL -http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk - -## Version -`driverlib_cc13xx_cc26xx_3_05_06_18894` - -## License - -BSD-3-Clause - -## License File - -[Export Manifest] manifest_driverlib_cc13xx_cc26xx_3_xx_xx.html - -## Documentation - -This version of cc26xxware is copied from the [SimpleLink CC26x2 Software -Development Kit](http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk). Modifications -were made to enable the OpenThread build. - -Also see: release_notes_driverlib_cc13xx_cc26xx.html - -| file | change | -|------------------------------------------------------|-------------------------------------------------------------------------| -| `devices/cc26x0/driverlib/bin/gcc/driverlib.a` | Renamed from `driverlib.lib` to allow Automake to recognize the library | -| `devices/cc26x0/linker_files/cc26x0f128.lds` | `end` symbol added for GCC stdlib and C++ init array placement | -| `devices/cc26x0/startup_files/startup_gcc.c` | C++ constructor calls added to `ResetHandler` | - -Documentation can be found within the [SimpleLink CC26x2 Software Development -Kit](http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk). - -## Description - -CC26XXware is the board support library for Texas Instruments' CC26XX line of -connected MCUs for developers to easily leverage the hardware capabilities of -those platforms. Texas Instruments Incorporated recommends TI-RTOS and its -associated drivers for future development. - diff --git a/third_party/ti/devices/DeviceFamily.h b/third_party/ti/devices/DeviceFamily.h deleted file mode 100644 index 8566650a7..000000000 --- a/third_party/ti/devices/DeviceFamily.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file DeviceFamily.h - * - * @brief Infrastructure to select correct driverlib path and identify devices - * - * This module enables the selection of the correct driverlib path for the current - * device. It also facilitates the use of per-device conditional compilation - * to enable minor variations in drivers between devices. - * - * In order to use this functionality, DeviceFamily_XYZ must be defined as one of - * the supported values. The DeviceFamily_ID and DeviceFamily_DIRECTORY defines - * are set based on DeviceFamily_XYZ. - */ - -#ifndef ti_devices_DeviceFamily__include -#define ti_devices_DeviceFamily__include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * DeviceFamily_ID_XYZ values. - * - * DeviceFamily_ID may be used in the preprocessor for conditional compilation. - * DeviceFamily_ID is set to one of these values based on the top level - * DeviceFamily_XYZ define. - */ -#define DeviceFamily_ID_CC13X0 1 -#define DeviceFamily_ID_CC26X0 2 -#define DeviceFamily_ID_CC26X0R2 3 -#define DeviceFamily_ID_CC13X2_V1 4 -#define DeviceFamily_ID_CC13X2_V2 5 -#define DeviceFamily_ID_CC13X2 DeviceFamily_ID_CC13X2_V1 -#define DeviceFamily_ID_CC26X2_V1 6 -#define DeviceFamily_ID_CC26X2_V2 7 -#define DeviceFamily_ID_CC26X2 DeviceFamily_ID_CC26X2_V1 -#define DeviceFamily_ID_CC3200 8 -#define DeviceFamily_ID_CC3220 9 -#define DeviceFamily_ID_MSP432P401x 10 -#define DeviceFamily_ID_MSP432P4x1xI 11 -#define DeviceFamily_ID_MSP432P4x1xT 12 -#define DeviceFamily_ID_MSP432E401Y 13 -#define DeviceFamily_ID_MSP432E411Y 14 - -/* - * DeviceFamily_PARENT_XYZ values. - * - * DeviceFamily_PARENT may be used in the preprocessor for conditional - * compilation. DeviceFamily_PARENT is set to one of these values based - * on the top-level DeviceFamily_XYZ define. - */ -#define DeviceFamily_PARENT_CC13X0_CC26X0 1 -#define DeviceFamily_PARENT_CC13X2_CC26X2 2 -#define DeviceFamily_PARENT_MSP432P401R 3 -#define DeviceFamily_PARENT_MSP432P4111 4 - -/* - * Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and - * DeviceFamily_PARENT based on the DeviceFamily_XYZ define. - * If DeviceFamily_XYZ is undefined, a compiler error is thrown. If - * multiple DeviceFamily_XYZ are defined, the first one encountered is used. - */ -#if defined(DeviceFamily_CC13X0) - #define DeviceFamily_ID DeviceFamily_ID_CC13X0 - #define DeviceFamily_DIRECTORY cc13x0 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 - -#elif defined(DeviceFamily_CC13X2) - #define DeviceFamily_ID DeviceFamily_ID_CC13X2 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC13X2_V1) - #define DeviceFamily_ID DeviceFamily_ID_CC13X2_V1 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC13X2_V2) - #define DeviceFamily_ID DeviceFamily_ID_CC13X2_V2 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v2 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC26X0) - #define DeviceFamily_ID DeviceFamily_ID_CC26X0 - #define DeviceFamily_DIRECTORY cc26x0 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 - -#elif defined(DeviceFamily_CC26X0R2) - #define DeviceFamily_ID DeviceFamily_ID_CC26X0R2 - #define DeviceFamily_DIRECTORY cc26x0r2 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 - -#elif defined(DeviceFamily_CC26X2) - #define DeviceFamily_ID DeviceFamily_ID_CC26X2 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC26X2_V1) - #define DeviceFamily_ID DeviceFamily_ID_CC26X2_V1 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC26X2_V2) - #define DeviceFamily_ID DeviceFamily_ID_CC26X2_V2 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2_v2 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC3200) - #define DeviceFamily_ID DeviceFamily_ID_CC3200 - #define DeviceFamily_DIRECTORY cc32xx - -#elif defined(DeviceFamily_CC3220) - #define DeviceFamily_ID DeviceFamily_ID_CC3220 - #define DeviceFamily_DIRECTORY cc32xx - -#elif defined(DeviceFamily_MSP432P401x) || defined(__MSP432P401R__) - #define DeviceFamily_ID DeviceFamily_ID_MSP432P401x - #define DeviceFamily_DIRECTORY msp432p4xx - #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P401R - #if !defined(__MSP432P401R__) - #define __MSP432P401R__ - #endif - -#elif defined(DeviceFamily_MSP432P4x1xI) - #define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xI - #define DeviceFamily_DIRECTORY msp432p4xx - #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 - #if !defined(__MSP432P4111__) - #define __MSP432P4111__ - #endif - -#elif defined(DeviceFamily_MSP432P4x1xT) - #define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xT - #define DeviceFamily_DIRECTORY msp432p4xx - #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 - #if !defined(__MSP432P4111__) - #define __MSP432P4111__ - #endif - -#elif defined(DeviceFamily_MSP432E401Y) - #define DeviceFamily_ID DeviceFamily_ID_MSP432E401Y - #define DeviceFamily_DIRECTORY msp432e4 - #if !defined(__MSP432E401Y__) - #define __MSP432E401Y__ - #endif - -#elif defined(DeviceFamily_MSP432E411Y) - #define DeviceFamily_ID DeviceFamily_ID_MSP432E411Y - #define DeviceFamily_DIRECTORY msp432e4 - #if !defined(__MSP432E411Y__) - #define __MSP432E411Y__ - #endif -#else - #error "DeviceFamily_XYZ undefined. You must defined DeviceFamily_XYZ!" -#endif - -/*! - * @brief Macro to include correct driverlib path. - * - * @pre DeviceFamily_XYZ which sets DeviceFamily_DIRECTORY must be defined - * first. - * - * @param x A token containing the path of the file to include based on - * the root device folder. The preceding forward slash must be - * omitted. For example: - * - #include DeviceFamily_constructPath(inc/hw_memmap.h) - * - #include DeviceFamily_constructPath(driverlib/ssi.h) - * - * @return Returns an include path. - * - */ -#define DeviceFamily_constructPath(x) - -#ifdef __cplusplus -} -#endif - -#endif /* ti_devices_DeviceFamily__include */ diff --git a/third_party/ti/devices/cc26x0/driverlib/adi.c b/third_party/ti/devices/cc26x0/driverlib/adi.c deleted file mode 100644 index f3893d3e0..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/adi.c +++ /dev/null @@ -1,73 +0,0 @@ -/****************************************************************************** -* Filename: adi.c -* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) -* Revision: 47706 -* -* Description: Driver for the ADI interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aux_smph.h" -#include "adi.h" -#include "cpu.h" - - -//***************************************************************************** -// -// SafeHapiVoid() and SafeHapiAuxAdiSelect() -// Common wrapper functions for the Hapi functions needing workaround for the -// "bus arbitration" issue. -// -//***************************************************************************** -void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ) -{ - bool bIrqEnabled = ( ! CPUcpsid() ); - while ( ! HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 )); - fPtr(); - HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 ) = 1; - if ( bIrqEnabled ) { - CPUcpsie(); - } -} - -void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ) -{ - bool bIrqEnabled = ( ! CPUcpsid() ); - while ( ! HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 )); - fPtr( ut8Signal ); - HWREG( AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 ) = 1; - if ( bIrqEnabled ) { - CPUcpsie(); - } -} diff --git a/third_party/ti/devices/cc26x0/driverlib/adi.h b/third_party/ti/devices/cc26x0/driverlib/adi.h deleted file mode 100644 index ca5a0bbd5..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/adi.h +++ /dev/null @@ -1,861 +0,0 @@ -/****************************************************************************** -* Filename: adi.h -* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) -* Revision: 47706 -* -* Description: Defines and prototypes for the ADI master interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup analog_group -//! @{ -//! \addtogroup adi_api -//! @{ -// -//***************************************************************************** - -#ifndef __ADI_H__ -#define __ADI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_uart.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_adi.h" -#include "debug.h" -#include "ddi.h" - -//***************************************************************************** -// -// Number of registers in the ADI slave -// -//***************************************************************************** -#define ADI_SLAVE_REGS 16 - - -//***************************************************************************** -// -// Defines that is used to control the ADI slave and master -// -//***************************************************************************** -#define ADI_PROTECT 0x00000080 -#define ADI_ACK 0x00000001 -#define ADI_SYNC 0x00000000 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! \brief Checks an ADI base address. -//! -//! This function determines if an ADI port base address is valid. -//! -//! \param ui32Base is the base address of the ADI port. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise -// -//***************************************************************************** -static bool -ADIBaseValid(uint32_t ui32Base) -{ - return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE || - ui32Base == AUX_ADI4_BASE); -} -#endif - - - - - -//***************************************************************************** -// -//! \brief Write an 8 bit value to a register in an ADI slave. -//! -//! This function will write a value to a single register in the analog domain. -//! The access to the registers in the analog domain is either 8, 16, or 32 bit -//! aligned. You can only do 16 bit access on registers 0-1 / 2-3, etc. Similarly -//! 32 bit accesses are always performed on register 0-3 / 4-7, etc. Addresses -//! for the registers and values being written to the registers will be -//! truncated according to this access scheme. -//! -//! \note This operation is write only for the specified register. No -//! previous value of the register will be kept (i.e. this is NOT -//! read-modify-write on the register). -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the register to write. -//! \param ui8Val is the 8 bit value to write to the register. -//! -//! \return None -//! -//! \sa ADI16RegWrite(), ADI32RegWrite() -// -//***************************************************************************** -__STATIC_INLINE void -ADI8RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Write the value to the register. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + ui32Reg, ui8Val, 1); - } else { - HWREGB(ui32Base + ui32Reg) = ui8Val; - } -} - -//***************************************************************************** -// -//! \brief Write a 16 bit value to 2 registers in the ADI slave. -//! -//! This function will write a value to 2 consecutive registers in the analog -//! domain. The access to the registers in the analog domain is either 8, 16 -//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, -//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, -//! etc. Addresses for the registers and values being written -//! to the registers will be truncated according to this access scheme. -//! -//! \note The byte addressing bit will be ignored, to ensure 16 bit access -//! to the ADI slave. -//! -//! \note This operation is write only for the specified register. No -//! previous value of the register will be kept (i.e. this is NOT -//! read-modify-write on the register). -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the register to write. -//! \param ui16Val is the 16 bit value to write to the register. -//! -//! \return None -//! -//! \sa ADI8RegWrite(), ADI32RegWrite() -// -//***************************************************************************** -__STATIC_INLINE void -ADI16RegWrite(uint32_t ui32Base, uint32_t ui32Reg, - uint16_t ui16Val) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Write the value to the register. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + (ui32Reg & 0xFE), ui16Val, 2); - } else { - HWREGH(ui32Base + (ui32Reg & 0xFE)) = ui16Val; - } -} - -//***************************************************************************** -// -//! \brief Write a 32 bit value to 4 registers in the ADI slave. -//! -//! This function will write a value to 4 consecutive registers in the analog -//! domain. The access to the registers in the analog domain is either 8, 16 -//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, -//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, -//! etc. Addresses for the registers and values being written -//! to the registers will be truncated according to this access scheme. -//! -//! \note The byte and half word addressing bits will be ignored, to ensure -//! 32 bit access to the ADI slave. -//! -//! \note This operation is write only for the specified register. No -//! previous value of the register will be kept (i.e. this is NOT -//! read-modify-write on the register). -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the register to write. -//! \param ui32Val is the 32 bit value to write to the register. -//! -//! \return None -//! -//! \sa ADI8RegWrite(), ADI16RegWrite() -// -//***************************************************************************** -__STATIC_INLINE void -ADI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Write the value to the register. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + (ui32Reg & 0xFC), ui32Val, 4); - } else { - HWREG(ui32Base + (ui32Reg & 0xFC)) = ui32Val; - } -} - -//***************************************************************************** -// -//! \brief Read the value of an 8 bit register in the ADI slave. -//! -//! This function will read an 8 bit register in the analog domain and return -//! the value as the lower 8 bits of an \c uint32_t. The access to the -//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can -//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses -//! are always performed on register 0-3 / 4-7, etc. Addresses for the -//! registers and values being written to the registers will be truncated -//! according to this access scheme. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the 8 bit register to read. -//! -//! \return Returns the 8 bit value of the analog register in the least -//! significant byte of the \c uint32_t. -//! -//! \sa ADI16RegRead(), ADI32RegRead() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -ADI8RegRead(uint32_t ui32Base, uint32_t ui32Reg) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Read the register and return the value. - if (ui32Base==AUX_ADI4_BASE) { - return AuxAdiDdiSafeRead(ui32Base + ui32Reg, 1); - } else { - return(HWREGB(ui32Base + ui32Reg)); - } -} - -//***************************************************************************** -// -//! \brief Read the value in a 16 bit register. -//! -//! This function will read 2 x 8 bit registers in the analog domain and return -//! the value as the lower 16 bits of an \c uint32_t. The access to the -//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can -//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses -//! are always performed on register 0-3 / 4-7, etc. Addresses for the -//! registers and values being written to the registers will be truncated -//! according to this access scheme. -//! -//! \note The byte addressing bit will be ignored, to ensure 16 bit access -//! to the ADI slave. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the 16 bit register to read. -//! -//! \return Returns the 16 bit value of the 2 analog register in the 2 least -//! significant bytes of the \c uint32_t. -//! -//! \sa ADI8RegRead(), ADI32RegRead() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -ADI16RegRead(uint32_t ui32Base, uint32_t ui32Reg) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Read the registers and return the value. - if (ui32Base==AUX_ADI4_BASE) { - return AuxAdiDdiSafeRead(ui32Base + (ui32Reg & 0xFE), 2); - } else { - return(HWREGH(ui32Base + (ui32Reg & 0xFE))); - } -} - -//***************************************************************************** -// -//! \brief Read the value in a 32 bit register. -//! -//! This function will read 4 x 8 bit registers in the analog domain and return -//! the value as an \c uint32_t. The access to the registers in the analog -//! domain is either 8, 16 or 32 bit aligned. You can only do 16 bit access on -//! registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always performed on -//! register 0-3 / 4-7, etc. Addresses for the registers and values being -//! written to the registers will be truncated according to this access scheme. -//! -//! \note The byte and half word addressing bits will be ignored, to ensure -//! 32 bit access to the ADI slave. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the 32 bit register to read. -//! -//! \return Returns the 32 bit value of the 4 analog registers. -//! -//! \sa ADI8RegRead(), ADI16RegRead() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -ADI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Read the registers and return the value. - if (ui32Base==AUX_ADI4_BASE) { - return AuxAdiDdiSafeRead(ui32Base + (ui32Reg & 0xFC), 4); - } else { - return(HWREG(ui32Base + (ui32Reg & 0xFC))); - } -} - -//***************************************************************************** -// -//! \brief Set specific bits in a single 8 bit ADI register. -//! -//! This function will set bits in a single register in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to set bits in a specific 8 bit register in the -//! ADI slave. Only bits in the selected register are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base register to assert the bits in. -//! \param ui8Val is the 8 bit one-hot encoded value specifying which -//! bits to set in the register. -//! -//! \return None -//! -//! \sa ADI16BitsSet(), ADI32BitsSet() -// -//***************************************************************************** -__STATIC_INLINE void -ADI8BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_SET; - - // Set the selected bits. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + ui32Reg, ui8Val, 1); - } else { - HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; - } -} - -//***************************************************************************** -// -//! \brief Set specific bits in 2 x 8 bit ADI slave registers. -//! -//! This function will set bits in 2 registers in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to set bits in 2 consecutive 8 bit registers in the -//! ADI slave. Only bits in the selected registers are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base register to assert the bits in. -//! \param ui16Val is the 16 bit one-hot encoded value specifying which -//! bits to set in the registers. -//! -//! \return None -//! -//! \sa ADI8BitsSet(), ADI32BitsSet() -// -//***************************************************************************** -__STATIC_INLINE void -ADI16BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_SET; - - // Set the selected bits. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFE), ui16Val, 2); - } else { - HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; - } -} - -//***************************************************************************** -// -//! \brief Set specific bits in 4 x 8 bit ADI slave registers. -//! -//! This function will set bits in 4 registers in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to set bits in 4 consecutive 8 bit registers in the -//! ADI slave. Only bits in the selected registers are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base register to assert the bits in. -//! \param ui32Val is the 32 bit one-hot encoded value specifying which -//! bits to set in the registers. -//! -//! \return None -//! -//! \sa ADI8BitsSet(), ADI16BitsSet() -// -//***************************************************************************** -__STATIC_INLINE void -ADI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_SET; - - // Set the selected bits. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFC), ui32Val, 4); - } else { - HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; - } -} - -//***************************************************************************** -// -//! \brief Clear specific bits in an 8 bit ADI register. -//! -//! This function will clear bits in a register in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to clear bits in a specific 8 bit register in -//! the ADI slave. Only bits in the selected register are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base registers to clear the bits in. -//! \param ui8Val is the 8 bit one-hot encoded value specifying which -//! bits to clear in the register. -//! -//! \return None -//! -//! \sa ADI16BitsClear(), ADI32BitsClear() -// -//***************************************************************************** -__STATIC_INLINE void -ADI8BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_CLR; - - // Set the selected bits. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + ui32Reg, ui8Val, 1); - } else { - HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; - } -} - -//***************************************************************************** -// -//! \brief Clear specific bits in two 8 bit ADI register. -//! -//! This function will clear bits in 2 registers in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to clear bits in 2 consecutive 8 bit registers in -//! the ADI slave. Only bits in the selected registers are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base registers to clear the bits in. -//! \param ui16Val is the 16 bit one-hot encoded value specifying which -//! bits to clear in the registers. -//! -//! \return None -//! -//! \sa ADI8BitsClear(), ADI32BitsClear() -// -//***************************************************************************** -__STATIC_INLINE void -ADI16BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_CLR; - - // Set the selected bits. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFE), ui16Val, 2); - } else { - HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; - } -} - -//***************************************************************************** -// -//! \brief Clear specific bits in four 8 bit ADI register. -//! -//! This function will clear bits in 4 registers in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to clear bits in 4 consecutive 8 bit registers in -//! the ADI slave. Only bits in the selected registers are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base registers to clear the bits in. -//! \param ui32Val is the 32 bit one-hot encoded value specifying which -//! bits to clear in the registers. -//! -//! \return None -//! -//! \sa ADI8BitsClear(), ADI16BitsClear() -// -//***************************************************************************** -__STATIC_INLINE void -ADI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_CLR; - - // Set the selected bits. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset + (ui32Reg & 0xFC), ui32Val, 4); - } else { - HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; - } -} - -//***************************************************************************** -// -//! \brief Set a value on any 4 bits inside an 8 bit register in the ADI slave. -//! -//! This function allows halfbyte (4 bit) access to the ADI slave registers. -//! The parameter \c bWriteHigh determines whether to write to the lower -//! or higher part of the 8 bit register. -//! -//! Use this function to write any value in the range 0-3 bits aligned on a -//! half byte boundary. Fx. for writing the value 0b101 to bits 1 to 3 the -//! \c ui8Val = 0xA and the \c ui8Mask = 0xE. Bit 0 will not be affected by -//! the operation, as the corresponding bit is not set in the \c ui8Mask. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is the base address of the ADI port. -//! \param ui32Reg is the Least Significant Register in the ADI slave that -//! will be affected by the write operation. -//! \param bWriteHigh defines which part of the register to write in. -//! - \c true: Write upper half byte of register. -//! - \c false: Write lower half byte of register. -//! \param ui8Mask is the mask defining which of the 4 bits that should be -//! overwritten. The mask must be defined in the lower half of the 8 bits of -//! the parameter. -//! \param ui8Val is the value to write. The value must be defined in the lower -//! half of the 8 bits of the parameter. -//! -//! \return None -//! -//! \sa ADI8SetValBit(), ADI16SetValBit -// -//***************************************************************************** -__STATIC_INLINE void -ADI4SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, - uint8_t ui8Mask, uint8_t ui8Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - ASSERT(!(ui8Val & 0xF0)); - ASSERT(!(ui8Mask & 0xF0)); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_MASK4B + (ui32Reg << 1) + (bWriteHigh ? 1 : 0); - - // Set the selected bits. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui8Mask << 4) | ui8Val, 1); - } else { - HWREGB(ui32Base + ui32RegOffset) = (ui8Mask << 4) | ui8Val; - } -} - -//***************************************************************************** -// -//! \brief Set a value on any bits inside an 8 bit register in the ADI slave. -//! -//! This function allows byte (8 bit) access to the ADI slave registers. -//! -//! Use this function to write any value in the range 0-7 bits aligned on a -//! byte boundary. Fx. for writing the value 0b101 to bits 1 and 3 the -//! \c ui16Val = 0x0A and the \c ui16Mask = 0x0E. Bits 0 and 5-7 will not be affected -//! by the operation, as the corresponding bits are not set in the -//! \c ui16Mask. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is the base address of the ADI port. -//! \param ui32Reg is the Least Significant Register in the ADI slave that -//! will be affected by the write operation. -//! \param ui16Mask is the mask defining which of the 8 bit that should be -//! overwritten. The mask must be defined in the lower half of the 16 bits. -//! \param ui16Val is the value to write. The value must be defined in the lower -//! half of the 16 bits. -//! -//! \return None -//! -//! \sa ADI4SetValBit(), ADI16SetValBit() -// -//***************************************************************************** -__STATIC_INLINE void -ADI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Mask, - uint16_t ui16Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - ASSERT(!(ui16Val & 0xFF00)); - ASSERT(!(ui16Mask & 0xFF00)); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_MASK8B + (ui32Reg << 1); - - // Set the selected bits. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui16Mask << 8) | ui16Val, 2); - } else { - HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val; - } -} - -//***************************************************************************** -// -//! \brief Set a value on any bits inside an 2 x 8 bit register aligned on a -//! half-word (byte) boundary in the ADI slave. -//! -//! This function allows 2 byte (16 bit) access to the ADI slave registers. -//! -//! Use this function to write any value in the range 0-15 bits aligned on a -//! half-word (byte) boundary. Fx. for writing the value 0b101 to bits 1 and 3 the -//! \c ui32Val = 0x000A and the \c ui32Mask = 0x000E. Bits 0 and 5-15 will not -//! be affected by the operation, as the corresponding bits are not set -//! in the \c ui32Mask. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is the base address of the ADI port. -//! \param ui32Reg is the Least Significant Register in the ADI slave that -//! will be affected by the write operation. -//! \param ui32Mask is the mask defining which of the 16 bit that should be -//! overwritten. The mask must be defined in the lower half of the 32 bits. -//! \param ui32Val is the value to write. The value must be defined in the lower -//! half of the 32 bits. -//! -//! \return None -//! -//! \sa ADI4SetValBit(), ADI8SetValBit() -// -//***************************************************************************** -__STATIC_INLINE void -ADI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, - uint32_t ui32Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - ASSERT(!(ui32Val & 0xFFFF0000)); - ASSERT(!(ui32Mask & 0xFFFF0000)); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_MASK16B + ((ui32Reg << 1) & 0xFC); - - // Set the selected bits. - if (ui32Base==AUX_ADI4_BASE) { - AuxAdiDdiSafeWrite(ui32Base + ui32RegOffset, (ui32Mask << 16) | ui32Val, 4); - } else { - HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val; - } -} - -//***************************************************************************** -// -// SafeHapiVoid() and SafeHapiAuxAdiSelect() -// Common wrapper functions for the Hapi functions needing workaround for the -// "bus arbitration" issue. -// -//***************************************************************************** -void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ); -void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __ADI_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/adi_doc.h b/third_party/ti/devices/cc26x0/driverlib/adi_doc.h deleted file mode 100644 index e7eadcaf1..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/adi_doc.h +++ /dev/null @@ -1,68 +0,0 @@ -/****************************************************************************** -* Filename: adi_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup adi_api -//! @{ -//! \section sec_adi Introduction -//! \n -//! -//! \section sec_adi_api API -//! -//! The API functions can be grouped like this: -//! -//! Write: -//! - Direct (all bits): -//! - \ref ADI8RegWrite() -//! - \ref ADI16RegWrite() -//! - \ref ADI32RegWrite() -//! - Set individual bits: -//! - \ref ADI8BitsSet() -//! - \ref ADI16BitsSet() -//! - \ref ADI32BitsSet() -//! - Clear individual bits: -//! - \ref ADI8BitsClear() -//! - \ref ADI16BitsClear() -//! - \ref ADI32BitsClear() -//! - Masked: -//! - \ref ADI4SetValBit() -//! - \ref ADI8SetValBit() -//! - \ref ADI16SetValBit() -//! -//! Read: -//! - \ref ADI8RegRead() -//! - \ref ADI16RegRead() -//! - \ref ADI32RegRead() -//! -//! @} diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_batmon.c b/third_party/ti/devices/cc26x0/driverlib/aon_batmon.c deleted file mode 100644 index de80801e0..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_batmon.c +++ /dev/null @@ -1,80 +0,0 @@ -/****************************************************************************** -* Filename: aon_batmon.c -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Driver for the AON Battery and Temperature Monitor -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aon_batmon.h" -#include "../inc/hw_fcfg1.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AONBatMonTemperatureGetDegC - #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC -#endif - -//***************************************************************************** -// -// AONBatMonTemperatureGetDegC() -// Returns sign extended temperature in Deg C (-256 .. +255) -// -//***************************************************************************** -int32_t -AONBatMonTemperatureGetDegC( void ) -{ - int32_t signedTemp ; // Signed extended temperature with 8 fractional bits - int32_t tempCorrection ; // Voltage dependent temp correction with 8 fractional bits - int8_t voltageSlope ; // Signed byte value representing the TEMP slope with battery voltage, in degrees C/V, with 4 fractional bits. - - // Shift left then right to sign extend the BATMON_TEMP field - signedTemp = ((((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_TEMP )) - << ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )) - >> ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )); - - // Typecasting voltageSlope to int8_t prior to assignment in order to make sure sign extension works properly - // Using byte read (HWREGB) in order to make more efficient code since voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM - voltageSlope = ((int8_t)HWREGB( FCFG1_BASE + FCFG1_O_MISC_TRIM )); - tempCorrection = (( voltageSlope * (((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT )) - 0x300 )) >> 4 ); - - return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 ); -} - - -// See aon_batmon.h for implementation of remaining functions diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_batmon.h b/third_party/ti/devices/cc26x0/driverlib/aon_batmon.h deleted file mode 100644 index 3a9b1adb1..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_batmon.h +++ /dev/null @@ -1,306 +0,0 @@ -/****************************************************************************** -* Filename: aon_batmon.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AON Battery and Temperature -* Monitor -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aon_group -//! @{ -//! \addtogroup aonbatmon_api -//! @{ -// -//***************************************************************************** - -#ifndef __AON_BATMON_H__ -#define __AON_BATMON_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_batmon.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC -#endif - - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Enable the temperature and battery monitoring. -//! -//! This function will enable the measurements of the temperature and the -//! battery voltage. -//! -//! To speed up the measurement of the levels the measurement can be enabled -//! before configuring the battery and temperature settings. When all of the -//! AON_BATMON registers are configured, the calculation of the voltage and -//! temperature values can be enabled (the measurement will now take -//! effect/propagate to other blocks). -//! -//! It is possible to enable both at the same time, after the AON_BATMON -//! registers are configured, but then the first values will be ready at a -//! later point compared to the scenario above. -//! -//! \note Temperature and battery voltage measurements are not done in -//! parallel. The measurement cycle is controlled by a hardware Finite State -//! Machine. First the temperature and then the battery voltage each taking -//! one cycle to complete. However, if the comparator measuring the battery -//! voltage detects a change on the reference value, a new measurement of the -//! battery voltage only is performed immediately after. This has no impact on -//! the cycle count. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONBatMonEnable(void) -{ - // Enable the measurements. - HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = - AON_BATMON_CTL_CALC_EN | - AON_BATMON_CTL_MEAS_EN; -} - -//***************************************************************************** -// -//! \brief Disable the temperature and battery monitoring. -//! -//! This function will disable the measurements of the temperature and the -//! battery voltage. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONBatMonDisable(void) -{ - // Disable the measurements. - HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0; -} - - -//***************************************************************************** -// -//! \brief Get the current temperature measurement as a signed value in Deg Celsius. -//! -//! This function returns an calibrated and rounded value in degree Celsius. -//! The temperature measurements are updated every cycle. -//! -//! \note The temperature drifts slightly depending on the battery voltage. -//! This function compensates for this drift and returns a calibrated temperature. -//! -//! \note Use the function AONBatMonNewTempMeasureReady() to test for a new measurement. -//! -//! \return Returns signed integer part of temperature in Deg C (-256 .. +255) -//! -//! \sa AONBatMonNewTempMeasureReady() -// -//***************************************************************************** -extern int32_t AONBatMonTemperatureGetDegC( void ); - -//***************************************************************************** -// -//! \brief Get the battery monitor measurement. -//! -//! This function will return the current battery monitor measurement. -//! The battery voltage measurements are updated every cycle. -//! -//! \note The returned value is NOT sign-extended! -//! -//! \note Use the function \ref AONBatMonNewBatteryMeasureReady() to test for -//! a change in measurement. -//! -//! \return Returns the current battery monitor value of the battery voltage -//! measurement in a format size <3.8> in units of volt. -//! -//! \sa AONBatMonNewBatteryMeasureReady() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONBatMonBatteryVoltageGet(void) -{ - uint32_t ui32CurrentBattery; - - ui32CurrentBattery = HWREG(AON_BATMON_BASE + AON_BATMON_O_BAT); - - // Return the current battery voltage measurement. - return (ui32CurrentBattery >> AON_BATMON_BAT_FRAC_S); -} - -//***************************************************************************** -// -//! \brief Check if battery monitor measurement has changed. -//! -//! This function checks if a new battery monitor value is available. If the -//! measurement value has \b changed since last clear the function returns \c true. -//! -//! If the measurement has changed the function will automatically clear the -//! status bit. -//! -//! \note It is always possible to read out the current value of the -//! battery level using AONBatMonBatteryVoltageGet() but this function can be -//! used to check if the measurement has changed. -//! -//! \return Returns \c true if the measurement value has changed and \c false -//! otherwise. -//! -//! \sa AONBatMonNewTempMeasureReady(), AONBatMonBatteryVoltageGet() -// -//***************************************************************************** -__STATIC_INLINE bool -AONBatMonNewBatteryMeasureReady(void) -{ - bool bStatus; - - // Check the status bit. - bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) & - AON_BATMON_BATUPD_STAT ? true : false; - - // Clear status bit if set. - if(bStatus) - { - HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) = 1; - } - - // Return status. - return (bStatus); -} - -//***************************************************************************** -// -//! \brief Check if temperature monitor measurement has changed. -//! -//! This function checks if a new temperature value is available. If the -//! measurement value has \b changed since last clear the function returns \c true. -//! -//! If the measurement has changed the function will automatically clear the -//! status bit. -//! -//! \note It is always possible to read out the current value of the -//! temperature using \ref AONBatMonTemperatureGetDegC() -//! but this function can be used to check if the measurement has changed. -//! -//! \return Returns \c true if the measurement value has changed and \c false -//! otherwise. -//! -//! \sa AONBatMonNewBatteryMeasureReady(), AONBatMonTemperatureGetDegC() -// -//***************************************************************************** -__STATIC_INLINE bool -AONBatMonNewTempMeasureReady(void) -{ - bool bStatus; - - // Check the status bit. - bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) & - AON_BATMON_TEMPUPD_STAT ? true : false; - - // Clear status bit if set. - if(bStatus) - { - HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) = 1; - } - - // Return status. - return (bStatus); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AONBatMonTemperatureGetDegC - #undef AONBatMonTemperatureGetDegC - #define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AON_BATMON_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_event.c b/third_party/ti/devices/cc26x0/driverlib/aon_event.c deleted file mode 100644 index 4fcad6978..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_event.c +++ /dev/null @@ -1,299 +0,0 @@ -/****************************************************************************** -* Filename: aon_event.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the AON Event fabric. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aon_event.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AONEventMcuWakeUpSet - #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet - #undef AONEventMcuWakeUpGet - #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet - #undef AONEventAuxWakeUpSet - #define AONEventAuxWakeUpSet NOROM_AONEventAuxWakeUpSet - #undef AONEventAuxWakeUpGet - #define AONEventAuxWakeUpGet NOROM_AONEventAuxWakeUpGet - #undef AONEventMcuSet - #define AONEventMcuSet NOROM_AONEventMcuSet - #undef AONEventMcuGet - #define AONEventMcuGet NOROM_AONEventMcuGet -#endif - -//***************************************************************************** -// -// Select event source for the specified MCU wakeup programmable event -// -//***************************************************************************** -void -AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) -{ - uint32_t ui32Ctrl; - - // Check the arguments. - ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); - ASSERT(ui32EventSrc <= AON_EVENT_NONE); - - ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); - - if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) - { - ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU0_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU0_EV_S; - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) - { - ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU1_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU1_EV_S; - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) - { - ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU2_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU2_EV_S; - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) - { - ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU3_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU3_EV_S; - } - - HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = ui32Ctrl; -} - -//***************************************************************************** -// -// Get event source for the specified MCU wakeup programmable event -// -//***************************************************************************** -uint32_t -AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) -{ - uint32_t ui32EventSrc; - - // Check the arguments. - ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); - - ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); - - if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) - { - return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU0_EV_M) >> - AON_EVENT_MCUWUSEL_WU0_EV_S); - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) - { - return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU1_EV_M) >> - AON_EVENT_MCUWUSEL_WU1_EV_S); - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) - { - return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU2_EV_M) >> - AON_EVENT_MCUWUSEL_WU2_EV_S); - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) - { - return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU3_EV_M) >> - AON_EVENT_MCUWUSEL_WU3_EV_S); - } - - // Should never get to this statement, but suppress warning. - ASSERT(0); - return(0); -} - -//***************************************************************************** -// -// Select event source for the specified AUX wakeup programmable event -// -//***************************************************************************** -void -AONEventAuxWakeUpSet(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc) -{ - uint32_t ui32Ctrl; - - // Check the arguments. - ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || - (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || - (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); - ASSERT(ui32EventSrc <= AON_EVENT_NONE); - - ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); - - if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) - { - ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU0_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU0_EV_S; - } - else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) - { - ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU1_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU1_EV_S; - } - else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) - { - ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU2_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU2_EV_S; - } - - HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL) = ui32Ctrl; -} - -//***************************************************************************** -// -// Get event source for the specified AUX wakeup programmable event -// -//***************************************************************************** -uint32_t -AONEventAuxWakeUpGet(uint32_t ui32AUXWUEvent) -{ - uint32_t ui32EventSrc; - - // Check the arguments. - ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || - (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || - (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); - - ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); - - if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) - { - return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU0_EV_M) >> - AON_EVENT_AUXWUSEL_WU0_EV_S); - } - else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) - { - return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU1_EV_M) >> - AON_EVENT_AUXWUSEL_WU1_EV_S); - } - else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) - { - return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU2_EV_M) >> - AON_EVENT_AUXWUSEL_WU2_EV_S); - } - - // Should never get to this statement, but suppress warning. - ASSERT(0); - return(0); -} - -//***************************************************************************** -// -// Select event source for the specified programmable event forwarded to the -// MCU event fabric -// -//***************************************************************************** -void -AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) -{ - uint32_t ui32Ctrl; - - // Check the arguments. - ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); - ASSERT(ui32EventSrc <= AON_EVENT_NONE); - - ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); - - if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) - { - ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) - { - ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) - { - ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; - } - - HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; -} - -//***************************************************************************** -// -// Get source for the specified programmable event forwarded to the MCU event -// fabric. -// -//***************************************************************************** -uint32_t -AONEventMcuGet(uint32_t ui32MCUEvent) -{ - uint32_t ui32EventSrc; - - // Check the arguments. - ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); - - ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); - - if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) - { - return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> - AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) - { - return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> - AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) - { - return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> - AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); - } - - // Should never get to this statement, but suppress warning. - ASSERT(0); - return(0); -} diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_event.h b/third_party/ti/devices/cc26x0/driverlib/aon_event.h deleted file mode 100644 index dd6865268..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_event.h +++ /dev/null @@ -1,623 +0,0 @@ -/****************************************************************************** -* Filename: aon_event.h -* Revised: 2017-06-21 11:05:14 +0200 (Wed, 21 Jun 2017) -* Revision: 49178 -* -* Description: Defines and prototypes for the AON Event fabric. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aon_group -//! @{ -//! \addtogroup aonevent_api -//! @{ -// -//***************************************************************************** - -#ifndef __AON_EVENT_H__ -#define __AON_EVENT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_device.h" -#include "../inc/hw_aon_event.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet - #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet - #define AONEventAuxWakeUpSet NOROM_AONEventAuxWakeUpSet - #define AONEventAuxWakeUpGet NOROM_AONEventAuxWakeUpGet - #define AONEventMcuSet NOROM_AONEventMcuSet - #define AONEventMcuGet NOROM_AONEventMcuGet -#endif - -//***************************************************************************** -// -// Event sources for the event AON fabric. -// Note: Events are level-triggered active high -// -//***************************************************************************** -// AON_EVENT_DIO0 // Edge detect on DIO0. See hw_device.h -// ... // ... -// AON_EVENT_DIO31 // Edge detect on DIO31. See hw_device.h -#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. - // Event ID 33 is reserved for future use - // Event ID 34 is reserved for future use -#define AON_EVENT_RTC_CH0 35 // RTC channel 0 -#define AON_EVENT_RTC_CH1 36 // RTC channel 1 -#define AON_EVENT_RTC_CH2 37 // RTC channel 2 -#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event -#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event -#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event -#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event -#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -#define AON_EVENT_JTAG 43 // JTAG generated event -#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 -#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 -#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 -#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) -#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) -#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed -#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out -#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event -#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event -#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event -#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event -#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -#define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B - // Event ID 57-62 is reserved for future use -#define AON_EVENT_NONE 63 // No event, always low - -// Keeping backward compatibility until major revision number is incremented -#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 ) - -//***************************************************************************** -// -// Values that can be passed to AONEventMCUWakeUpSet() and returned -// by AONEventMCUWakeUpGet(). -// -//***************************************************************************** -#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 -#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 -#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 -#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 - -//***************************************************************************** -// -// Values that can be passed to AONEventAuxWakeUpSet() and AONEventAuxWakeUpGet() -// -//***************************************************************************** -#define AON_EVENT_AUX_WU0 0 // Programmable AUX wake-up event 0 -#define AON_EVENT_AUX_WU1 1 // Programmable AUX wake-up event 1 -#define AON_EVENT_AUX_WU2 2 // Programmable AUX wake-up event 2 - -//***************************************************************************** -// -// Values that can be passed to AONEventMcuSet() and AONEventMcuGet() -// -//***************************************************************************** -#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) -#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) -#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Select event source for the specified MCU wake-up programmable event. -//! -//! The AON event fabric has several programmable events that can -//! wake up the MCU. The events are forwarded to the wake-up controller (WUC). -//! -//! \note The programmable event sources are effectively OR'ed together -//! to form a single wake-up event forwarded to the WUC. -//! -//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. -//! - \ref AON_EVENT_MCU_WU0 -//! - \ref AON_EVENT_MCU_WU1 -//! - \ref AON_EVENT_MCU_WU2 -//! - \ref AON_EVENT_MCU_WU3 -//! \param ui32EventSrc is an event source for the event AON fabric. -//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h -//! - ... -//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \return None -//! -//! \sa AONEventMcuWakeUpGet() -// -//***************************************************************************** -extern void AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, - uint32_t ui32EventSrc); - -//***************************************************************************** -// -//! \brief Get event source for the specified MCU wake-up programmable event. -//! -//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. -//! - \ref AON_EVENT_MCU_WU0 -//! - \ref AON_EVENT_MCU_WU1 -//! - \ref AON_EVENT_MCU_WU2 -//! - \ref AON_EVENT_MCU_WU3 -//! -//! \return Returns the event source for the event AON fabric. -//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h -//! - ... -//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \sa AONEventMcuWakeUpSet() -// -//***************************************************************************** -extern uint32_t AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent); - -//***************************************************************************** -// -//! \brief Select event source for the specified AUX wake-up programmable event. -//! -//! The AON event fabric has a total of three programmable events that can -//! wake-up the AUX domain. The events are forwarded to the wake-up -//! controller (WUC). -//! -//! \note The three programmable event sources are effectively OR'ed together -//! to form a single wake-up event forwarded to the WUC. -//! -//! \param ui32AUXWUEvent is one of three programmable AUX wake-up event sources. -//! - \ref AON_EVENT_AUX_WU0 -//! - \ref AON_EVENT_AUX_WU1 -//! - \ref AON_EVENT_AUX_WU2 -//! \param ui32EventSrc is an event sources for the event AON fabric. -//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h -//! - ... -//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \return None -//! -//! \sa AONEventAuxWakeUpGet() -// -//***************************************************************************** -extern void AONEventAuxWakeUpSet(uint32_t ui32AUXWUEvent, - uint32_t ui32EventSrc); - -//***************************************************************************** -// -//! \brief Get event source for the specified AUX wake-up programmable event. -//! -//! The AON event fabric has a total of three programmable events that can -//! wake-up the AUX domain. The events are forwarded to the wake-up -//! controller (WUC). -//! -//! \param ui32AUXWUEvent is one of three programmable AUX wake-up event sources. -//! - \ref AON_EVENT_AUX_WU0 -//! - \ref AON_EVENT_AUX_WU1 -//! - \ref AON_EVENT_AUX_WU2 -//! -//! \return Returns the event source for the event AON fabric. -//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h -//! - ... -//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \sa AONEventAuxWakeUpSet() -// -//***************************************************************************** -extern uint32_t AONEventAuxWakeUpGet(uint32_t ui32AUXWUEvent); - -//***************************************************************************** -// -//! \brief Select event source for the specified programmable event forwarded to the -//! MCU event fabric. -//! -//! The AON event fabric has a total of three programmable events that can -//! be forwarded to the MCU event fabric. -//! -//! \note The three programmable event sources are forwarded to the MCU Event -//! Fabric as: -//! - AON_PROG0 -//! - AON_PROG1 -//! - AON_PROG2 -//! -//! \param ui32MCUEvent is one of three programmable events forwarded to the -//! MCU event fabric. -//! - \ref AON_EVENT_MCU_EVENT0 -//! - \ref AON_EVENT_MCU_EVENT1 -//! - \ref AON_EVENT_MCU_EVENT2 -//! \param ui32EventSrc is an event source for the event AON fabric. -//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h -//! - ... -//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \return None -//! -//! \sa AONEventMcuGet() -// -//***************************************************************************** -extern void AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc); - -//***************************************************************************** -// -//! \brief Get source for the specified programmable event forwarded to the MCU event -//! fabric. -//! -//! The AON event fabric has a total of three programmable events that can -//! be forwarded to the MCU event fabric. -//! -//! \param ui32MCUEvent is one of three programmable events forwarded to the -//! MCU event fabric. -//! - \ref AON_EVENT_MCU_EVENT0 -//! - \ref AON_EVENT_MCU_EVENT1 -//! - \ref AON_EVENT_MCU_EVENT2 -//! -//! \return Returns the event source for the event AON fabric. -//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h -//! - ... -//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \sa AONEventMcuSet() -// -//***************************************************************************** -extern uint32_t AONEventMcuGet(uint32_t ui32MCUEvent); - -//***************************************************************************** -// -//! \brief Select event source forwarded to AON Real Time Clock (RTC). -//! -//! A programmable event can be forwarded to the AON real time clock -//! for triggering a capture event on RTC channel 1. -//! -//! \param ui32EventSrc is an event source for the event AON fabric. -//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h -//! - ... -//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \return None -//! -//! \sa AONEventRtcGet() -// -//***************************************************************************** -__STATIC_INLINE void -AONEventRtcSet(uint32_t ui32EventSrc) -{ - uint32_t ui32Ctrl; - - // Check the arguments. - ASSERT(ui32EventSrc <= AON_EVENT_NONE); - - ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); - ui32Ctrl &= ~(AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S; - - HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL) = ui32Ctrl; -} - -//***************************************************************************** -// -//! \brief Get event source forwarded to AON Real Time Clock (RTC). -//! -//! A programmable event can be forwarded to the AON real time clock -//! for triggering a capture event on RTC channel 1. -//! -//! \return Returns the event source to the event AON fabric. -//! - AON_EVENT_DIO0 : Edge detect on DIO0. See hw_device.h -//! - ... -//! - AON_EVENT_DIO31 : Edge detect on DIO31. See hw_device.h -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \sa AONEventRtcSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONEventRtcGet(void) -{ - uint32_t ui32EventSrc; - - // Return the active event. - ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); - - return ((ui32EventSrc & AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M) >> - AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AONEventMcuWakeUpSet - #undef AONEventMcuWakeUpSet - #define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet - #endif - #ifdef ROM_AONEventMcuWakeUpGet - #undef AONEventMcuWakeUpGet - #define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet - #endif - #ifdef ROM_AONEventAuxWakeUpSet - #undef AONEventAuxWakeUpSet - #define AONEventAuxWakeUpSet ROM_AONEventAuxWakeUpSet - #endif - #ifdef ROM_AONEventAuxWakeUpGet - #undef AONEventAuxWakeUpGet - #define AONEventAuxWakeUpGet ROM_AONEventAuxWakeUpGet - #endif - #ifdef ROM_AONEventMcuSet - #undef AONEventMcuSet - #define AONEventMcuSet ROM_AONEventMcuSet - #endif - #ifdef ROM_AONEventMcuGet - #undef AONEventMcuGet - #define AONEventMcuGet ROM_AONEventMcuGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AON_EVENT_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_event_doc.h b/third_party/ti/devices/cc26x0/driverlib/aon_event_doc.h deleted file mode 100644 index c02a5f109..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_event_doc.h +++ /dev/null @@ -1,62 +0,0 @@ -/****************************************************************************** -* Filename: aon_event_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup aonevent_api -//! @{ -//! \section sec_aonevent Introduction -//! -//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and -//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers -//! to the AON event fabric. For more information on MCU event fabric, see [MCU event API](@ref event_api). -//! -//! The AON event fabric is a configurable combinatorial router between AON event sources and event -//! subscribers in both AON and MCU domains. The AON event fabric has three main event subscribers: AON WUC, -//! AON RTC, and MCU event fabric. The API to control the AON event fabric configuration can be grouped based -//! on the event subscriber to configure: -//! -//! - AON WUC receives two programmable event lines from AON event fabric. One for MCU wake-up events and one for AUX wake-up events. For more information, see [AON WUC API](@ref aonwuc_api). -//! - MCU wake-up event -//! - @ref AONEventMcuWakeUpSet() -//! - @ref AONEventMcuWakeUpGet() -//! - AUX wake-up event -//! - @ref AONEventAuxWakeUpSet() -//! - @ref AONEventAuxWakeUpGet() -//! - AON RTC receives a single programmable event line from the AON event fabric. For more information, see [AON RTC API](@ref aonrtc_api). -//! - @ref AONEventRtcSet() -//! - @ref AONEventRtcGet() -//! - MCU event fabric receives a number of programmable event lines from the AON event fabric. For more information, see [MCU event API](@ref event_api). -//! - @ref AONEventMcuSet() -//! - @ref AONEventMcuGet() -//! @} diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_ioc.c b/third_party/ti/devices/cc26x0/driverlib/aon_ioc.c deleted file mode 100644 index c0c9b3c4a..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_ioc.c +++ /dev/null @@ -1,39 +0,0 @@ -/****************************************************************************** -* Filename: aon_ioc.c -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Driver for the AON IO Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aon_ioc.h" diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_ioc.h b/third_party/ti/devices/cc26x0/driverlib/aon_ioc.h deleted file mode 100644 index 13ab44960..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_ioc.h +++ /dev/null @@ -1,292 +0,0 @@ -/****************************************************************************** -* Filename: aon_ioc.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AON IO Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aon_group -//! @{ -//! \addtogroup aonioc_api -//! @{ -// -//***************************************************************************** - -#ifndef __AON_IOC_H__ -#define __AON_IOC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_ioc.h" -#include "debug.h" - -//***************************************************************************** -// -// Defines for the drive strength -// -//***************************************************************************** -#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength -#define AONIOC_DRV_STR_2 0x00000001 -#define AONIOC_DRV_STR_3 0x00000003 -#define AONIOC_DRV_STR_4 0x00000002 -#define AONIOC_DRV_STR_5 0x00000006 -#define AONIOC_DRV_STR_6 0x00000007 -#define AONIOC_DRV_STR_7 0x00000005 -#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength - -#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) -#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) -#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Configure drive strength values for the manual drive strength options. -//! -//! This function defines the general drive strength settings for the non-AUTO -//! drive strength options in the MCU IOC. Consequently, if all IOs are using the -//! automatic drive strength option this function has no effect. -//! -//! Changing the drive strength values affects all current modes (Low-Current, -//! High-Current, and Extended-Current). Current mode for individual IOs is set in -//! MCU IOC by \ref IOCIODrvStrengthSet(). -//! -//! \note Values are Gray encoded. Simply incrementing values to increase drive -//! strength will not work. -//! -//! \param ui32DriveLevel -//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. Default value is selected -//! to give minimum 2/4/8 mA @3.3V for Low-Current mode, High-Current mode, -//! and Extended-Current mode respectively. -//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. Default value is selected -//! to give minimum 2/4/8 mA @2.5V for Low-Current mode, High-Current mode, -//! and Extended-Current mode respectively. -//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. Default value is selected -//! to give minimum 2/4/8 mA @1.8V for Low-Current mode, High-Current mode, -//! and Extended-Current mode respectively. -//! \param ui32DriveStrength sets the value used by IOs configured as non-AUTO drive strength in MCU IOC. -//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength -//! - \ref AONIOC_DRV_STR_2 -//! - \ref AONIOC_DRV_STR_3 -//! - \ref AONIOC_DRV_STR_4 -//! - \ref AONIOC_DRV_STR_5 -//! - \ref AONIOC_DRV_STR_6 -//! - \ref AONIOC_DRV_STR_7 -//! - \ref AONIOC_DRV_STR_8 : Highest drive strength -//! -//! \return None -//! -//! \sa \ref AONIOCDriveStrengthGet(), \ref IOCIODrvStrengthSet() -// -//***************************************************************************** -__STATIC_INLINE void -AONIOCDriveStrengthSet(uint32_t ui32DriveLevel, uint32_t ui32DriveStrength) -{ - ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || - (ui32DriveLevel == AONIOC_DRV_LVL_MED) || - (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); - ASSERT((ui32DriveStrength == AONIOC_DRV_STR_1) || - (ui32DriveStrength == AONIOC_DRV_STR_2) || - (ui32DriveStrength == AONIOC_DRV_STR_3) || - (ui32DriveStrength == AONIOC_DRV_STR_4) || - (ui32DriveStrength == AONIOC_DRV_STR_5) || - (ui32DriveStrength == AONIOC_DRV_STR_6) || - (ui32DriveStrength == AONIOC_DRV_STR_7) || - (ui32DriveStrength == AONIOC_DRV_STR_8)); - - // Set the drive strength. - HWREG(AON_IOC_BASE + ui32DriveLevel) = ui32DriveStrength; -} - -//***************************************************************************** -// -//! \brief Get a specific drive level setting for all IOs. -//! -//! Use this function to read the drive strength setting for a specific -//! IO drive level. -//! -//! \note Values are Gray encoded. -//! -//! \param ui32DriveLevel is the specific drive level to get the setting for. -//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. -//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. -//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. -//! -//! \return Returns the requested drive strength level setting for all IOs. -//! Possible values are: -//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength -//! - \ref AONIOC_DRV_STR_2 -//! - \ref AONIOC_DRV_STR_3 -//! - \ref AONIOC_DRV_STR_4 -//! - \ref AONIOC_DRV_STR_5 -//! - \ref AONIOC_DRV_STR_6 -//! - \ref AONIOC_DRV_STR_7 -//! - \ref AONIOC_DRV_STR_8 : Highest drive strength -//! -//! \sa AONIOCDriveStrengthSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) -{ - // Check the arguments. - ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || - (ui32DriveLevel == AONIOC_DRV_LVL_MED) || - (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); - - // Return the drive strength value. - return( HWREG(AON_IOC_BASE + ui32DriveLevel) ); -} - -//***************************************************************************** -// -//! \brief Freeze the IOs. -//! -//! To retain the values of the output IOs during a powerdown/shutdown of the -//! device all IO latches in the AON domain should be frozen in their current -//! state. This ensures that software can regain control of the IOs after a -//! reboot without the IOs first falling back to the default values (i.e. input -//! and no pull). -//! -//! \return None -//! -//! \sa AONIOCFreezeDisable() -// -//***************************************************************************** -__STATIC_INLINE void -AONIOCFreezeEnable(void) -{ - // Set the AON IO latches as static. - HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = 0x0; -} - -//***************************************************************************** -// -//! \brief Un-freeze the IOs. -//! -//! When rebooting the chip after it has entered powerdown/shutdown mode, the -//! software can regain control of the IOs by setting the IO latches as -//! transparent. The IOs should not be unfrozen before software has restored -//! the functionality of the IO. -//! -//! \return None -//! -//! \sa AONIOCFreezeEnable() -// -//***************************************************************************** -__STATIC_INLINE void -AONIOCFreezeDisable(void) -{ - // Set the AON IOC latches as transparent. - HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = AON_IOC_IOCLATCH_EN; -} - -//***************************************************************************** -// -//! \brief Disable the 32kHz clock output. -//! -//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality -//! in the IOC is bypassed. Therefore, the programmer needs to call this -//! function to disable the clock output. -//! -//! \return None -//! -//! \sa AONIOC32kHzOutputEnable() -// -//***************************************************************************** -__STATIC_INLINE void -AONIOC32kHzOutputDisable(void) -{ - // Disable the LF clock output. - HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = AON_IOC_CLK32KCTL_OE_N; -} - -//***************************************************************************** -// -//! \brief Enable the 32kHz clock output. -//! -//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality -//! in the IOC is bypassed. Therefore, the programmer needs to call this -//! function to enable the clock output. -//! -//! \return None -//! -//! \sa AONIOC32kHzOutputDisable() -// -//***************************************************************************** -__STATIC_INLINE void -AONIOC32kHzOutputEnable(void) -{ - // Enable the LF clock output. - HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = 0x0; -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AON_IOC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_ioc_doc.h b/third_party/ti/devices/cc26x0/driverlib/aon_ioc_doc.h deleted file mode 100644 index 3d379780c..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_ioc_doc.h +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** -* Filename: aon_ioc_doc.h -* Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) -* Revision: 45969 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup aonioc_api -//! @{ -//! \section sec_aonioc Introduction -//! -//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). -//! The IOC consists of two APIs: -//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. -//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. -//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is -//! routed to a DIO for external use. -//! -//! For more information on the MCU IOC see the [IOC API](\ref ioc_api). -//! -//! \section sec_aonioc_api API -//! -//! The API functions can be grouped like this: -//! -//! Freeze IOs while MCU domain is powered down: -//! - \ref AONIOCFreezeEnable() -//! - \ref AONIOCFreezeDisable() -//! -//! Output LF clock to a DIO: -//! - \ref AONIOC32kHzOutputEnable() -//! - \ref AONIOC32kHzOutputDisable() -//! -//! Configure the value of drive strength for the three manual MCU IOC settings (MIN, MED, MAX): -//! - \ref AONIOCDriveStrengthSet() -//! - \ref AONIOCDriveStrengthGet() -//! -//! @} diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_rtc.c b/third_party/ti/devices/cc26x0/driverlib/aon_rtc.c deleted file mode 100644 index 625f0bb6d..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_rtc.c +++ /dev/null @@ -1,102 +0,0 @@ -/****************************************************************************** -* Filename: aon_rtc.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the AON RTC. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aon_rtc.h" -#include "cpu.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AONRTCCurrentCompareValueGet - #define AONRTCCurrentCompareValueGet NOROM_AONRTCCurrentCompareValueGet - #undef AONRTCCurrent64BitValueGet - #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet -#endif - - -//***************************************************************************** -// -// Get the current value of the RTC counter in a format compatible to the compare registers. -// -//***************************************************************************** -uint32_t -AONRTCCurrentCompareValueGet( void ) -{ - uint32_t ui32CurrentSec ; - uint32_t ui32CurrentSubSec ; - uint32_t ui32SecondSecRead ; - - // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC - // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. - do { - ui32CurrentSec = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); - ui32CurrentSubSec = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC ); - ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); - } while ( ui32CurrentSec != ui32SecondSecRead ); - - return (( ui32CurrentSec << 16 ) | ( ui32CurrentSubSec >> 16 )); -} - -//***************************************************************************** -// -// Get the current 64-bit value of the RTC counter. -// -//***************************************************************************** -uint64_t -AONRTCCurrent64BitValueGet( void ) -{ - union { - uint64_t returnValue ; - uint32_t secAndSubSec[ 2 ] ; - } currentRtc ; - uint32_t ui32SecondSecRead ; - - // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC - // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. - do { - currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); - currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC ); - ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); - } while ( currentRtc.secAndSubSec[ 1 ] != ui32SecondSecRead ); - - return ( currentRtc.returnValue ); -} diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_rtc.h b/third_party/ti/devices/cc26x0/driverlib/aon_rtc.h deleted file mode 100644 index 9efaccd64..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_rtc.h +++ /dev/null @@ -1,936 +0,0 @@ -/****************************************************************************** -* Filename: aon_rtc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AON RTC -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aon_group -//! @{ -//! \addtogroup aonrtc_api -//! @{ -// -//***************************************************************************** - -#ifndef __AON_RTC_H__ -#define __AON_RTC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_rtc.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AONRTCCurrentCompareValueGet NOROM_AONRTCCurrentCompareValueGet - #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet -#endif - -//***************************************************************************** -// -// Values that can be passed to most of the AON_RTC APIs as the ui32Channel -// parameter. -// -//***************************************************************************** -#define AON_RTC_CH_NONE 0x0 // RTC No channel -#define AON_RTC_CH0 0x1 // RTC Channel 0 -#define AON_RTC_CH1 0x2 // RTC Channel 1 -#define AON_RTC_CH2 0x4 // RTC Channel 2 -#define AON_RTC_ACTIVE 0x8 // RTC Active - -//***************************************************************************** -// -// Values that can be passed to AONRTCConfigDelay as the ui32Delay parameter. -// -//***************************************************************************** -#define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY -#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle -#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles -#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles -#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles -#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles -#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles -#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles -#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles -#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles -#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles -#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles -#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles -#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles - -//***************************************************************************** -// -// Values that can be passed to AONRTCSetModeCH1 as the ui32Mode -// parameter. -// -//***************************************************************************** -#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode -#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode - -//***************************************************************************** -// -// Values that can be passed to AONRTCSetModeCH2 as the ui32Mode -// parameter. -// -//***************************************************************************** -#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode -#define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode - -//***************************************************************************** -// -// Mutliplication factor for converting from seconds to corresponding time in -// the "CompareValue" format. -// The factor correspond to the compare value format described in the registers -// \ref AON_RTC_O_CH0CMP, \ref AON_RTC_O_CH1CMP and \ref AON_RTC_O_CH2CMP. -// Example1: -// 4 milliseconds in CompareValue format can be written like this: -// ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT )) -// Example2: -// 4 seconds in CompareValue format can be written like this: -// ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT ) -// -//***************************************************************************** -#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Enable the RTC. -//! -//! Enable the AON Real Time Clock. -//! -//! \note Event generation for each of the three channels must also be enabled -//! using the function AONRTCChannelEnable(). -//! -//! \return None -//! -//! \sa AONRTCChannelEnable() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCEnable(void) -{ - // Enable RTC. - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disable the RTC. -//! -//! Disable the AON Real Time Clock. -//! -//! \note Event generation for each of the three channels can also be disabled -//! using the function AONRTCChannelDisable(). -//! -//! \return None -//! -//! \sa AONRTCChannelDisable() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCDisable(void) -{ - // Disable RTC - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Reset the RTC. -//! -//! Reset the AON Real Time Clock. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCReset(void) -{ - // Reset RTC. - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RESET_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Check if the RTC is active (enabled). -//! -//! \return Returns the status of the RTC. -//! - false : RTC is disabled -//! - true : RTC is enabled -// -//***************************************************************************** -__STATIC_INLINE bool -AONRTCActive(void) -{ - // Read if RTC is enabled - return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN)); -} - -//***************************************************************************** -// -//! \brief Check if an RTC channel is active (enabled). -//! -//! \param ui32Channel specifies the RTC channel to check status of. -//! Parameter must be one (and only one) of the following: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return Returns the status of the requested channel: -//! - false : Channel is disabled -//! - true : Channel is enabled -// -//***************************************************************************** -__STATIC_INLINE bool -AONRTCChannelActive(uint32_t ui32Channel) -{ - uint32_t uint32Status = 0; - - if(ui32Channel & AON_RTC_CH0) - { - uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN); - } - - if(ui32Channel & AON_RTC_CH1) - { - uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN); - } - - if(ui32Channel & AON_RTC_CH2) - { - uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN); - } - - return(uint32Status); -} - -//***************************************************************************** -// -//! \brief Configure Event Delay for the RTC. -//! -//! Each event from the three individual channels can generate a delayed -//! event. The delay time for these events is set using this function. -//! The delay is measured in clock cycles. -//! -//! \note There is only one delay setting shared for all three channels. -//! -//! \param ui32Delay specifies the delay time for delayed events. -//! Parameter must be one of the following: -//! - \ref AON_RTC_CONFIG_DELAY_NODELAY -//! - \ref AON_RTC_CONFIG_DELAY_1 -//! - \ref AON_RTC_CONFIG_DELAY_2 -//! - \ref AON_RTC_CONFIG_DELAY_4 -//! - \ref AON_RTC_CONFIG_DELAY_8 -//! - \ref AON_RTC_CONFIG_DELAY_16 -//! - \ref AON_RTC_CONFIG_DELAY_32 -//! - \ref AON_RTC_CONFIG_DELAY_48 -//! - \ref AON_RTC_CONFIG_DELAY_64 -//! - \ref AON_RTC_CONFIG_DELAY_80 -//! - \ref AON_RTC_CONFIG_DELAY_96 -//! - \ref AON_RTC_CONFIG_DELAY_112 -//! - \ref AON_RTC_CONFIG_DELAY_128 -//! - \ref AON_RTC_CONFIG_DELAY_144 -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCDelayConfig(uint32_t ui32Delay) -{ - uint32_t ui32Cfg; - - // Check the arguments. - ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144); - - - ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); - ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M); - ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S); - - HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; -} - -//***************************************************************************** -// -//! \brief Configure the source of the combined event. -//! -//! A combined delayed event can be generated from a combination of the three -//! delayed events. Delayed events form the specified channels are OR'ed -//! together to generate the combined event. -//! -//! \param ui32Channels specifies the channels that are to be used for -//! generating the combined event. -//! The parameter must be the bitwise OR of any of the following: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! - \ref AON_RTC_CH_NONE -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCCombinedEventConfig(uint32_t ui32Channels) -{ - uint32_t ui32Cfg; - - // Check the arguments. - ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || - (ui32Channels == AON_RTC_CH_NONE) ); - - ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); - ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M); - ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S); - - HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; -} - -//***************************************************************************** -// -//! \brief Clear event from a specified channel. -//! -//! In case of an active event from the specified channel, the event -//! will be cleared (de-asserted). -//! -//! \param ui32Channel clears the event from one or more RTC channels: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCEventClear(uint32_t ui32Channel) -{ - // Check the arguments. - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0; - } - - if(ui32Channel & AON_RTC_CH1) - { - HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1; - } - - if(ui32Channel & AON_RTC_CH2) - { - HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH2; - } -} - -//***************************************************************************** -// -//! \brief Get event status for a specified channel. -//! -//! In case of an active event from the specified channel, -//! this call will return \c true otherwise \c false. -//! -//! \param ui32Channel specifies the channel from which to query the event state. -//! The parameter must be one (and only one) of the following: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return Returns \c true if an event has occurred for the given channel, -//! otherwise \c false. -// -//***************************************************************************** -__STATIC_INLINE bool -AONRTCEventGet(uint32_t ui32Channel) -{ - uint32_t uint32Event = 0; - - // Check the arguments. - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH0_BITN); - } - - if(ui32Channel & AON_RTC_CH1) - { - uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH1_BITN); - } - - if(ui32Channel & AON_RTC_CH2) - { - uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH2_BITN); - } - - return(uint32Event); -} - -//***************************************************************************** -// -//! \brief Get integer part (seconds) of RTC free-running timer. -//! -//! Get the value in seconds of RTC free-running timer, i.e. the integer part. -//! The fractional part is returned from a call to AONRTCFractionGet(). -//! -//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead -//! of this function if the <16.16> format is sufficient. -//! -//! \note To read a consistent pair of integer and fractional parts, -//! \ref AONRTCSecGet() must be called first to trigger latching of the -//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts -//! must be disabled to ensure that these operations are performed atomically. -//! -//! \return Returns the integer part of RTC free running timer. -//! -//! \sa \ref AONRTCFractionGet() \ref AONRTCCurrentCompareValueGet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCSecGet(void) -{ - // The following read gets the seconds, but also latches the fractional - // part. - return(HWREG(AON_RTC_BASE + AON_RTC_O_SEC)); -} - -//***************************************************************************** -// -//! \brief Get fractional part (sub-seconds) of RTC free-running timer. -//! -//! Get the value of the fractional part of RTC free-running timer, i.e. the -//! sub-second part. -//! -//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead -//! of this function if the <16.16> format is sufficient. -//! -//! \note To read a consistent pair of integer and fractional parts, -//! \ref AONRTCSecGet() must be called first to trigger latching of the -//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts -//! must be disabled to ensure that these operations are performed atomically. -//! -//! \return Returns the fractional part of RTC free running timer. -//! -//! \sa \ref AONRTCSecGet() \ref AONRTCCurrentCompareValueGet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCFractionGet(void) -{ - // Note1: It is recommended to use AON RTCCurrentCompareValueGet() instead - // of this function if the <16.16> format is sufficient. - // Note2: AONRTCSecGet() must be called before this function to get a - // consistent reading. - // Note3: Interrupts must be disabled between the call to AONRTCSecGet() and this - // call since there are interrupt functions that reads AON_RTC_O_SEC - return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC)); -} - -//***************************************************************************** -// -//! \brief Get the sub second increment of the RTC. -//! -//! Get the value of the sub-second increment which is added to the RTC -//! absolute time on every clock tick. -//! -//! \note For a precise and temperature independent LF clock (e.g. an LF XTAL) -//! this value would stay the same across temperature. For temperatue -//! dependent clock sources like an RC oscillator, this value will change -//! over time if the application includes functionality for doing temperature -//! compensation of the RTC clock source. The default value corresponds to a -//! LF clock frequency of exactly 32.768 kHz. -//! -//! \return Returns the sub-second increment of the RTC added to the overall -//! value on every RTC clock tick. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCSubSecIncrGet(void) -{ - return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC)); -} - -//***************************************************************************** -// -//! \brief Set operational mode of channel 1. -//! -//! Set the operational mode of channel 1. It can be capture or compare mode. -//! In capture mode, an external event causes the value of the free running -//! counter to be stored, to remember the time of the event. -//! -//! \note The default mode is compare. -//! -//! \param ui32Mode specifies the mode for channel 1. -//! The parameter must be one of the following: -//! - \ref AON_RTC_MODE_CH1_CAPTURE -//! - \ref AON_RTC_MODE_CH1_COMPARE -//! -//! \return None -//! -//! \sa AONRTCModeCh1Get() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCModeCh1Set(uint32_t ui32Mode) -{ - // Check the arguments. - ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) || - (ui32Mode == AON_RTC_MODE_CH1_COMPARE)); - - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN) = ui32Mode; -} - -//***************************************************************************** -// -//! \brief Get operational mode of channel 1. -//! -//! Get the operational mode of channel 1. It can be capture or compare mode. -//! In capture mode, an external event causes the value of the free running -//! counter to be stored, to remember the time of the event. -//! -//! \return Returns the operational mode of channel 1, one of: -//! - \ref AON_RTC_MODE_CH1_CAPTURE -//! - \ref AON_RTC_MODE_CH1_COMPARE -//! -//! \sa AONRTCModeCh1Set() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCModeCh1Get(void) -{ - return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN)); -} - -//***************************************************************************** -// -//! \brief Set operational mode of channel 2. -//! -//! Set the operational mode of channel 2. It can be in continuous compare -//! mode or normal compare mode. -//! In continuous mode, a value is automatically incremented to the channel 2 -//! compare register, upon a channel 2 compare event. This allows channel 2 to -//! generate a series of completely equidistant events. -//! The increment value is set by the AONRTCIncValueCh2Set() call. -//! -//! \note The default mode is normal compare. -//! -//! \param ui32Mode specifies the mode for channel 2. -//! The parameter must be one of the following: -//! - \ref AON_RTC_MODE_CH2_CONTINUOUS -//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE -//! -//! \return None -//! -//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCModeCh2Set(uint32_t ui32Mode) -{ - // Check the arguments. - ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) || - (ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE)); - - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN) = ui32Mode; -} - -//***************************************************************************** -// -//! \brief Get operational mode of channel 2. -//! -//! Get the operational mode of channel 2. It can be in continuous compare -//! mode or normal compare mode. -//! In continuous mode, a value is automatically incremented to the channel 2 -//! compare register, upon a channel 2 compare event. This allows channel 2 to -//! generate a series of completely equidistant events. -//! The increment value is set by the AONRTCIncValueCh2Set() call. -//! -//! \return Returns the operational mode of channel 2, i.e. one of: -//! - \ref AON_RTC_MODE_CH2_CONTINUOUS -//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE -//! -//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCModeCh2Get(void) -{ - return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN)); -} - -//***************************************************************************** -// -//! \brief Enable event operation for the specified channel. -//! -//! Enable the event generation for the specified channel. -//! -//! \note The RTC free running clock must also be enabled globally using the -//! AONRTCEnable() call. -//! -//! \param ui32Channel specifies one or more channels to enable: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return None -//! -//! \sa AONRTCEnable() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCChannelEnable(uint32_t ui32Channel) -{ - // Check the arguments. - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 1; - } - - if(ui32Channel & AON_RTC_CH1) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 1; - } - - if(ui32Channel & AON_RTC_CH2) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 1; - } -} - -//***************************************************************************** -// -//! \brief Disable event operation for the specified channel. -//! -//! Disable the event generation for the specified channel. -//! -//! \note The RTC free running clock can also be disabled globally using the -//! AONRTCDisable() call. -//! -//! \param ui32Channel specifies one or more channels to disable: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return None -//! -//! \sa AONRTCDisable() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCChannelDisable(uint32_t ui32Channel) -{ - // Check the arguments. - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 0; - } - - if(ui32Channel & AON_RTC_CH1) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 0; - } - - if(ui32Channel & AON_RTC_CH2) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 0; - } -} - -//***************************************************************************** -// -//! \brief Set the compare value for the given channel. -//! -//! Set compare value for the specified channel. -//! -//! The format of the compare value is a 16 bit integer and 16 bit fractional -//! format <16 sec.16 subsec>. The current value of the RTC counter -//! can be retrieved in a format compatible to the compare register using -//! \ref AONRTCCurrentCompareValueGet() -//! -//! \param ui32Channel specifies one or more channels to set compare value for: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! \param ui32CompValue is the compare value to set for the specified channel. -//! - Format: <16 sec.16 subsec> -//! -//! \return None -//! -//! \sa AONRTCCurrentCompareValueGet() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue) -{ - // Check the arguments. - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP) = ui32CompValue; - } - - if(ui32Channel & AON_RTC_CH1) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP) = ui32CompValue; - } - - if(ui32Channel & AON_RTC_CH2) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP) = ui32CompValue; - } -} - -//***************************************************************************** -// -//! \brief Get the compare value for the given channel. -//! -//! Get compare value for the specified channel. -//! -//! \param ui32Channel specifies a channel. -//! The parameter must be one (and only one) of the following: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return Returns the stored compare value for the given channel. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCCompareValueGet(uint32_t ui32Channel) -{ - uint32_t ui32Value = 0; - - // Check the arguments - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP); - } - - if(ui32Channel & AON_RTC_CH1) - { - ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP); - } - - if(ui32Channel & AON_RTC_CH2) - { - ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP); - } - - return(ui32Value); -} - -//***************************************************************************** -// -//! \brief Get the current value of the RTC counter in a format that matches -//! RTC compare values. -//! -//! The compare value registers contains 16 integer and 16 fractional bits. -//! This function will return the current value of the RTC counter in an -//! identical format. -//! -//! \note Reading SEC both before and after SUBSEC in order to detect if SEC -//! incremented while reading SUBSEC. If SEC incremented, we can't be sure -//! which SEC the SUBSEC belongs to, so repeating the sequence then. -//! -//! \return Returns the current value of the RTC counter in a <16.16> format -//! (SEC[15:0].SUBSEC[31:16]). -//! -//! \sa \ref AONRTCCompareValueSet() -// -//***************************************************************************** -extern uint32_t AONRTCCurrentCompareValueGet(void); - -//***************************************************************************** -// -//! \brief Get the current 64-bit value of the RTC counter. -//! -//! \note Reading SEC both before and after SUBSEC in order to detect if SEC -//! incremented while reading SUBSEC. If SEC incremented, we can't be sure -//! which SEC the SUBSEC belongs to, so repeating the sequence then. -//! -//! \return Returns the current value of the RTC counter in a 64-bits format -//! (SEC[31:0].SUBSEC[31:0]). -// -//***************************************************************************** -extern uint64_t AONRTCCurrent64BitValueGet(void); - -//***************************************************************************** -// -//! \brief Set the channel 2 increment value when operating in continuous mode. -//! -//! Set the channel 2 increment value when operating in continuous mode. -//! The specified value is automatically incremented to the channel 2 compare -//! register, upon a channel 2 compare event. This allows channel 2 to generate -//! a series of completely equidistant events. -//! -//! \param ui32IncValue is the increment value when operating in continuous mode. -//! -//! \return None -//! -//! \sa AONRTCIncValueCh2Get() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCIncValueCh2Set(uint32_t ui32IncValue) -{ - HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC) = ui32IncValue; -} - -//***************************************************************************** -// -//! \brief Get the channel2 increment value when operating in continuous mode. -//! -//! Get the channel 2 increment value, when channel 2 is operating in -//! continuous mode. -//! This value is automatically incremented to the channel 2 compare -//! register, upon a channel 2 compare event. This allows channel 2 to -//! generate a series of completely equidistant events. -//! -//! \return Returns the channel 2 increment value when operating in continuous -//! mode. -//! -//! \sa AONRTCIncValueCh2Set() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCIncValueCh2Get(void) -{ - return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC)); -} - -//***************************************************************************** -// -//! \brief Get the channel 1 capture value. -//! -//! Get the channel 1 capture value. -//! The upper 16 bits of the returned value is the lower 16 bits of the -//! integer part of the RTC timer. The lower 16 bits of the returned part -//! is the upper 16 bits of the fractional part. -//! -//! \return Returns the channel 1 capture value. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCCaptureValueCh1Get(void) -{ - return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CAPT)); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AONRTCCurrentCompareValueGet - #undef AONRTCCurrentCompareValueGet - #define AONRTCCurrentCompareValueGet ROM_AONRTCCurrentCompareValueGet - #endif - #ifdef ROM_AONRTCCurrent64BitValueGet - #undef AONRTCCurrent64BitValueGet - #define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AON_RTC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_rtc_doc.h b/third_party/ti/devices/cc26x0/driverlib/aon_rtc_doc.h deleted file mode 100644 index e5be29f02..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_rtc_doc.h +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: aon_rtc_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup aonrtc_api -//! @{ -//! \section sec_aonrtc Introduction -//! -//! \note If using TI-RTOS then only TI-RTOS is allowed to configure the RTC timer! -//! @} diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_wuc.c b/third_party/ti/devices/cc26x0/driverlib/aon_wuc.c deleted file mode 100644 index 4f3d54724..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_wuc.c +++ /dev/null @@ -1,224 +0,0 @@ -/****************************************************************************** -* Filename: aon_wuc.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the AON Wake-Up Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aon_wuc.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AONWUCAuxReset - #define AONWUCAuxReset NOROM_AONWUCAuxReset - #undef AONWUCRechargeCtrlConfigSet - #define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet - #undef AONWUCOscConfig - #define AONWUCOscConfig NOROM_AONWUCOscConfig -#endif - - -//***************************************************************************** -// -//! Reset the AUX domain -// -//***************************************************************************** -void -AONWUCAuxReset(void) -{ - // Reset the AUX domain. -// HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) |= AON_WUC_AUXCTL_RESET_REQ; // ROM version - HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_RESET_REQ_BITN) = 1; - - // Wait for AON interface to be in sync. - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); - - // De-assert reset on the AUX domain. -// HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) &= ~AON_WUC_AUXCTL_RESET_REQ; // ROM version - HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_RESET_REQ_BITN) = 0; - - // Wait for AON interface to be in sync. - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); -} - -//***************************************************************************** -// -//! Configure the recharge controller -// -//***************************************************************************** -void -AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, uint32_t ui32AdaptRate, - uint32_t ui32Period, uint32_t ui32MaxPeriod) -{ - uint32_t ui32Shift; - uint32_t ui32C1; - uint32_t ui32C2; - uint32_t ui32Reg; - uint32_t ui32Exponent; - uint32_t ui32MaxExponent; - uint32_t ui32Mantissa; - uint32_t ui32MaxMantissa; - - // Check the arguments. - ASSERT((ui32AdaptRate >= RC_RATE_MIN) || - (ui32AdaptRate <= RC_RATE_MAX)); - - ui32C1 = 0; - ui32C2 = 0; - ui32Shift = 9; - - // Clear the previous values. - ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); - ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M | - AON_WUC_RECHARGECFG_ADAPTIVE_EN_M | AON_WUC_RECHARGECFG_PER_M_M | - AON_WUC_RECHARGECFG_PER_E_M | AON_WUC_RECHARGECFG_C1_M | - AON_WUC_RECHARGECFG_C2_M); - - // Check if the recharge controller adaptation algorithm should be active. - if(bAdaptEnable) - { - // Calculate adaptation parameters. - while(ui32AdaptRate) - { - if(ui32AdaptRate & (1 << ui32Shift)) - { - if(!ui32C1) - { - ui32C1 = ui32Shift; - } - else if(!ui32C2) - { - if((2 * ui32AdaptRate) > ((uint32_t)(3 << ui32Shift))) - { - ui32C2 = ui32Shift + 1; - } - else - { - ui32C2 = ui32Shift; - } - } - else - { - break; - } - ui32AdaptRate &= ~(1 << ui32Shift); - } - ui32Shift--; - } - if(!ui32C2) - { - ui32C2 = ui32C1 = ui32C1 - 1; - } - - ui32C1 = 10 - ui32C1; - ui32C2 = 10 - ui32C2; - - // Update the recharge rate parameters. - ui32Reg &= ~(AON_WUC_RECHARGECFG_C1_M | AON_WUC_RECHARGECFG_C2_M); - ui32Reg |= (ui32C1 << AON_WUC_RECHARGECFG_C1_S) | - (ui32C2 << AON_WUC_RECHARGECFG_C2_S) | - AON_WUC_RECHARGECFG_ADAPTIVE_EN_M; - } - - // Resolve the period into an exponent and mantissa. - ui32Period = (ui32Period >> 4); - ui32Exponent = 0; - while(ui32Period > (AON_WUC_RECHARGECFG_PER_M_M >> AON_WUC_RECHARGECFG_PER_M_S)) - { - ui32Period >>= 1; - ui32Exponent++; - } - ui32Mantissa = ui32Period; - - // Resolve the max period into an exponent and mantissa. - ui32MaxPeriod = (ui32MaxPeriod >> 4); - ui32MaxExponent = 0; - while(ui32MaxPeriod > (AON_WUC_RECHARGECFG_MAX_PER_M_M >> AON_WUC_RECHARGECFG_MAX_PER_M_S)) - { - ui32MaxPeriod >>= 1; - ui32MaxExponent++; - } - ui32MaxMantissa = ui32MaxPeriod; - - // Configure the controller. - ui32Reg |= ((ui32MaxMantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | - (ui32MaxExponent << AON_WUC_RECHARGECFG_MAX_PER_E_S) | - (ui32Mantissa << AON_WUC_RECHARGECFG_PER_M_S) | - (ui32Exponent << AON_WUC_RECHARGECFG_PER_E_S)); - HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; - -} - -//***************************************************************************** -// -//! Configure the interval for oscillator amplitude calibration -// -//***************************************************************************** -void -AONWUCOscConfig(uint32_t ui32Period) -{ - uint32_t ui32Mantissa; - uint32_t ui32Exponent; - uint32_t ui32Reg; - - // Resolve the period into a exponent and mantissa. - ui32Period = (ui32Period >> 4); - ui32Exponent = 0; - while(ui32Period > (AON_WUC_OSCCFG_PER_M_M >> AON_WUC_OSCCFG_PER_M_S)) - { - ui32Period >>= 1; - ui32Exponent++; - } - ui32Mantissa = ui32Period; - - // Update the period for the oscillator amplitude calibration. - HWREG(AON_WUC_BASE + AON_WUC_O_OSCCFG) = - (ui32Mantissa << AON_WUC_OSCCFG_PER_M_S) | - (ui32Exponent << AON_WUC_OSCCFG_PER_E_S); - - // Set the maximum recharge period equal to the oscillator amplitude - // calibration period. - ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); - ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M); - ui32Reg |= ((ui32Mantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | - (ui32Exponent << AON_WUC_RECHARGECFG_MAX_PER_E_S)); - - // Write the configuration. - HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; -} diff --git a/third_party/ti/devices/cc26x0/driverlib/aon_wuc.h b/third_party/ti/devices/cc26x0/driverlib/aon_wuc.h deleted file mode 100644 index b871c5b4e..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aon_wuc.h +++ /dev/null @@ -1,838 +0,0 @@ -/****************************************************************************** -* Filename: aon_wuc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AON Wake-Up Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aon_group -//! @{ -//! \addtogroup aonwuc_api -//! @{ -// -//***************************************************************************** - -#ifndef __AON_WUC_H__ -#define __AON_WUC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aon_wuc.h" -#include "../inc/hw_aon_rtc.h" -#include "interrupt.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AONWUCAuxReset NOROM_AONWUCAuxReset - #define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet - #define AONWUCOscConfig NOROM_AONWUCOscConfig -#endif - -//***************************************************************************** -// -// Defines the possible clock source for the MCU and AUX domain. -// -//***************************************************************************** -#define AONWUC_CLOCK_SRC_HF 0x00000003 // System clock high frequency - - // 48 MHz. -#define AONWUC_CLOCK_SRC_LF 0x00000001 // System clock low frequency - - // 32 kHz. -#define AONWUC_NO_CLOCK 0x00000000 // System clock low frequency - - // 32 kHz. - -//***************************************************************************** -// -// Defines the possible clock division factors for the AUX domain. -// -//***************************************************************************** -#define AUX_CLOCK_DIV_2 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 ) -#define AUX_CLOCK_DIV_4 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 ) -#define AUX_CLOCK_DIV_8 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 ) -#define AUX_CLOCK_DIV_16 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 ) -#define AUX_CLOCK_DIV_32 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 ) -#define AUX_CLOCK_DIV_64 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 ) -#define AUX_CLOCK_DIV_128 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 ) -#define AUX_CLOCK_DIV_256 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 ) -#define AUX_CLOCK_DIV_UNUSED ( AON_WUC_AUXCLK_SCLK_HF_DIV_M + ( 1 << AON_WUC_AUXCLK_SCLK_HF_DIV_S )) -#define AUX_CLOCK_DIV_M ( AON_WUC_AUXCLK_SCLK_HF_DIV_M ) - -//***************************************************************************** -// -// Defines used for configuring the power-off and wake up procedure. -// -//***************************************************************************** -#define MCU_VIRT_PWOFF_DISABLE 0x00000000 -#define MCU_VIRT_PWOFF_ENABLE 0x00020000 -#define MCU_IMM_WAKE_UP 0x00000000 -#define MCU_FIXED_WAKE_UP 0x00010000 -#define AUX_VIRT_PWOFF_DISABLE 0x00000000 -#define AUX_VIRT_PWOFF_ENABLE 0x00020000 -#define AUX_IMM_WAKE_UP 0x00000000 -#define AUX_FIXED_WAKE_UP 0x00010000 - -//***************************************************************************** -// -// Defines that can be be used to enable/disable the entire SRAM and the -// retention on the SRAM in both the MCU and the AUX domain. -// -//***************************************************************************** -#define MCU_RAM0_RETENTION 0x00000001 -#define MCU_RAM1_RETENTION 0x00000002 -#define MCU_RAM2_RETENTION 0x00000004 -#define MCU_RAM3_RETENTION 0x00000008 -#define MCU_RAM_BLOCK_RETENTION 0x0000000F -#define MCU_AUX_RET_ENABLE 0x00000001 - -//***************************************************************************** -// -// Defines for different wake up modes for AUX domain which can be set using -// AONWUCAuxWakeUpEvent() . -// -//***************************************************************************** -#define AONWUC_AUX_WAKEUP 0x00000001 -#define AONWUC_AUX_ALLOW_SLEEP 0x00000000 - -//***************************************************************************** -// -// Defines for all the different power modes available through -// AONWUCPowerStatusGet() . -// -//***************************************************************************** -#define AONWUC_OSC_GBIAS_REQ 0x00400000 // OSC is requesting GBias -#define AONWUC_AUX_GBIAS_REQ 0x00200000 // AUX is requesting GBias -#define AONWUC_MCU_GBIAS_REQ 0x00100000 // MCU is requesting GBias -#define AONWUC_OSC_BGAP_REQ 0x00040000 // OSC is requesting BGap -#define AONWUC_AUX_BGAP_REQ 0x00020000 // AUX is requesting BGap -#define AONWUC_MCU_BGAP_REQ 0x00010000 // MCU is requesting BGap -#define AONWUC_GBIAS_ON 0x00002000 // Global Bias is on -#define AONWUC_BGAP_ON 0x00001000 // Band Gap is on -#define AONWUC_AUX_POWER_DOWN 0x00000200 // AUX is in powerdown mode -#define AONWUC_MCU_POWER_DOWN 0x00000100 // MCU is in powerdown mode -#define AONWUC_JTAG_POWER_ON 0x00000040 // JTAG is powered on -#define AONWUC_AUX_POWER_ON 0x00000020 // AUX is powered on -#define AONWUC_MCU_POWER_ON 0x00000010 // MCU is powered on -#define AONWUC_SPLY_POWER_DOWN 0x00000001 // Power supply is in power down - - -//***************************************************************************** -// -// RAM repair status bits. Values are returned by AOXWUCRamRepairStatusGet() . -// -//***************************************************************************** -#define MCU_RAMREPAIR_DONE 0x00000001 -#define AUX_RAMREPAIR_DONE 0x00000002 - -//***************************************************************************** - -//***************************************************************************** -#define RC_RATE_MAX 768 // Maximum recharge rate for the - // recharge controller. -#define RC_RATE_MIN 2 // Minimum recharge rate for the - // recharge controller. - -//***************************************************************************** -#define AONWUC_MCU_RESET_SRC 0x00000002 // MCU reset source can be SW or - // JTAG -#define AONWUC_MCU_WARM_RESET 0x00000001 // MCU reset type and can be warm - // or not warm. - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Configure the power down clock for the MCU domain. -//! -//! Use this function to control which one of the clock sources that -//! is fed into the MCU domain when the system is in standby mode. When the -//! power is back in Active mode the clock source will automatically switch to -//! \ref AONWUC_CLOCK_SRC_HF. -//! -//! Each clock is fed 'as is' into the MCU domain, since the MCU domain -//! contains internal clock dividers controllable through the PRCM. -//! -//! \param ui32ClkSrc is the clock source for the MCU domain when in power -//! down. Values available as clock source: -//! - \ref AONWUC_NO_CLOCK -//! - \ref AONWUC_CLOCK_SRC_LF -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCMcuPowerDownConfig(uint32_t ui32ClkSrc) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT((ui32ClkSrc == AONWUC_NO_CLOCK) || - (ui32ClkSrc == AONWUC_CLOCK_SRC_LF)); - - // Set the clock source for the MCU domain when in power down. - ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK); - ui32Reg &= ~AON_WUC_MCUCLK_PWR_DWN_SRC_M; - HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK) = ui32Reg | - (ui32ClkSrc << - AON_WUC_MCUCLK_PWR_DWN_SRC_S); -} - -//***************************************************************************** -// -//! \brief Configure the power down mode for the MCU domain. -//! -//! The parameter \c ui32Mode determines the power down mode of the MCU Voltage -//! Domain. When the AON WUC receives a request to power off the MCU domain it -//! can choose to power off completely or use a virtual power-off. In a virtual -//! power-off, reset is asserted and the clock is stopped but the power to the -//! domain is kept on. -//! -//! \param ui32Mode defines the power down mode of the MCU domain. -//! Allowed values for setting the virtual power-off are: -//! - \ref MCU_VIRT_PWOFF_DISABLE -//! - \ref MCU_VIRT_PWOFF_ENABLE -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCMcuPowerOffConfig(uint32_t ui32Mode) -{ - // Check the arguments. - ASSERT((ui32Mode == MCU_VIRT_PWOFF_ENABLE) || - (ui32Mode == MCU_VIRT_PWOFF_DISABLE)); - - // Set the powerdown mode. - HWREGBITW(AON_WUC_BASE + AON_WUC_O_MCUCFG, AON_WUC_MCUCFG_VIRT_OFF_BITN) = (ui32Mode != 0); -} - -//***************************************************************************** -// -//! \brief Configure the wake-up procedure for the MCU domain. -//! -//! The MCU domain can wake up using two different procedures. Either it wakes -//! up immediately following the triggering event or wake-up is forced to -//! happen a fixed number of 32 KHz clocks following the triggering -//! event. The last can be used to compensate for any variable delays caused -//! by other activities going on at the time of wakeup (such as a recharge -//! event, etc.). -//! -//! \param ui32WakeUp determines the timing of the MCU wake up procedure. -//! - \ref MCU_IMM_WAKE_UP -//! - \ref MCU_FIXED_WAKE_UP -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCMcuWakeUpConfig(uint32_t ui32WakeUp) -{ - // Check the arguments. - ASSERT((ui32WakeUp == MCU_IMM_WAKE_UP) || - (ui32WakeUp == MCU_FIXED_WAKE_UP)); - - // Configure the wake up procedure. - HWREGBITW(AON_WUC_BASE + AON_WUC_O_MCUCFG, AON_WUC_MCUCFG_FIXED_WU_EN_BITN) = (ui32WakeUp != 0); -} - -//***************************************************************************** -// -//! \brief Configure the retention on the block RAM in the MCU domain. -//! -//! MCU SRAM is partitioned into 4 banks of 1k x 32 each. The SRAM supports -//! retention on all 4 blocks. The retention on the SRAM can be turned on and -//! off. Use this function to enable the retention on the individual blocks. -//! -//! If a block is not represented in the parameter \c ui32Retention then the -//! the retention will be disabled for that block. -//! -//! \note Retention on the SRAM is not enabled by default. If retention is -//! turned off on all RAM blocks then the SRAM is powered off when it would -//! otherwise be put in retention mode. -//! -//! \param ui32Retention defines which RAM blocks to enable/disable retention on. -//! To enable retention on individual parts of the RAM use a bitwise OR'ed -//! combination of: -//! - \ref MCU_RAM0_RETENTION -//! - \ref MCU_RAM1_RETENTION -//! - \ref MCU_RAM2_RETENTION -//! - \ref MCU_RAM3_RETENTION -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCMcuSRamConfig(uint32_t ui32Retention) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT(ui32Retention & MCU_RAM_BLOCK_RETENTION); - ASSERT(!(ui32Retention & ~MCU_RAM_BLOCK_RETENTION)); - - // Configure the retention. - ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_MCUCFG) & ~MCU_RAM_BLOCK_RETENTION; - ui32Reg |= ui32Retention; - HWREG(AON_WUC_BASE + AON_WUC_O_MCUCFG) = ui32Reg; -} - - -//***************************************************************************** -// -//! \brief Return the clock configuration for the AUX domain. -//! -//! The AUX domain does not have a local clock divider, so the AON WUC contains -//! a dedicated clock divider for AUX domain. Use this function to -//! get the setting of the clock divider. -//! -//! \return Return the clock configuration. Enumerated return values are: -//! - \ref AUX_CLOCK_DIV_2 -//! - \ref AUX_CLOCK_DIV_4 -//! - \ref AUX_CLOCK_DIV_8 -//! - \ref AUX_CLOCK_DIV_16 -//! - \ref AUX_CLOCK_DIV_32 -//! - \ref AUX_CLOCK_DIV_64 -//! - \ref AUX_CLOCK_DIV_128 -//! - \ref AUX_CLOCK_DIV_256 -//! -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONWUCAuxClockConfigGet(void) -{ - // Return the clock divider value. - return ((HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) & - AON_WUC_AUXCLK_SCLK_HF_DIV_M) >> - AON_WUC_AUXCLK_SCLK_HF_DIV_S); -} - -//***************************************************************************** -// -//! \brief Configure the power down mode for the AUX domain. -//! -//! Use this function to control which one of the clock sources that -//! is fed into the MCU domain when it is in Power Down mode. When the Power -//! is back in active mode the clock source will automatically switch to -//! \ref AONWUC_CLOCK_SRC_HF. -//! -//! Each clock is fed 'as is' into the AUX domain, since the AUX domain -//! contains internal clock dividers controllable through the PRCM. -//! -//! \param ui32ClkSrc is the clock source for the AUX domain when in power down. -//! - \ref AONWUC_NO_CLOCK -//! - \ref AONWUC_CLOCK_SRC_LF -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCAuxPowerDownConfig(uint32_t ui32ClkSrc) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT((ui32ClkSrc == AONWUC_NO_CLOCK) || - (ui32ClkSrc == AONWUC_CLOCK_SRC_LF)); - - // Set the clock source for the AUX domain when in power down. - ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK); - ui32Reg &= ~AON_WUC_AUXCLK_PWR_DWN_SRC_M; - HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg | - (ui32ClkSrc << - AON_WUC_AUXCLK_PWR_DWN_SRC_S); -} - - -//***************************************************************************** -// -//! \brief Configure the retention on the AUX SRAM. -//! -//! The AUX SRAM contains only one block which supports retention. The retention -//! on the SRAM can be turned on and off. Use this function to enable/disable -//! the retention on the entire RAM. -//! -//! \param ui32Retention either enables or disables AUX SRAM retention. -//! - 0 : Disable retention. -//! - 1 : Enable retention. -//! -//! \note Retention on the SRAM is not enabled by default. If retention is -//! turned off then the SRAM is powered off when it would otherwise be put in -//! retention mode. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCAuxSRamConfig(uint32_t ui32Retention) -{ - // Enable/disable the retention. - HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCFG, AON_WUC_AUXCFG_RAM_RET_EN_BITN) = ui32Retention; -} - -//***************************************************************************** -// -//! \brief Control the wake up procedure of the AUX domain. -//! -//! The AUX domain can be woken in two different modes. In both modes power -//! is turned on. In one mode a software event is generated for the -//! Sensor Controller and it is allowed to start processing. The second mode will -//! just force power on the Sensor Controller. If System CPU requires exclusive access -//! to the AUX domain resources, it is advised to ensure that the image in -//! the Sensor Controller memory is declared invalid. This can be achieved by -//! calling AONWUCAuxImageInvalid(). -//! -//! \note Any writes to the AON interface must pass a 32 kHz clock boundary, -//! and is therefore relatively slow. To ensure that a given write is -//! complete the value of the register can be read back after write. -// -//! \note When accessing the AUX domain from the System CPU, it is advised always to -//! have set the AUX in at least \ref AONWUC_AUX_WAKEUP. This overwrites any -//! instruction from the Sensor Controller and ensures that the AUX domain -//! is on so it won't leave the System CPU hanging. -//! -//! \param ui32Mode is the wake up mode for the AUX domain. -//! - \ref AONWUC_AUX_WAKEUP -//! - \ref AONWUC_AUX_ALLOW_SLEEP -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCAuxWakeupEvent(uint32_t ui32Mode) -{ - // Check the arguments. - ASSERT((ui32Mode == AONWUC_AUX_WAKEUP) || - (ui32Mode == AONWUC_AUX_ALLOW_SLEEP)); - - // Wake up the AUX domain. - HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_AUX_FORCE_ON_BITN) = ui32Mode; -} - -//***************************************************************************** -// -//! \brief Reset the AUX domain. -//! -//! Use this function to reset the entire AUX domain. The write to the AON_WUC -//! module must pass an 32 kHz clock boundary. By reading the -//! AON_RTC_O_SYNC register after each write, it is guaranteed that the AON -//! interface will be in sync and that both the assert and the de-assert of the -//! reset signal to AUX will propagate. -//! -//! \note This requires two writes and two reads on a 32 kHz clock boundary. -//! -//! \return None -// -//***************************************************************************** -extern void AONWUCAuxReset(void); - -//***************************************************************************** -// -//! \brief Tells the Sensor Controller that the image in memory is valid. -//! -//! Use this function to tell the sensor controller that the image in memory is -//! valid, and it is allowed to start executing the program. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCAuxImageValid(void) -{ - // Tell the Sensor Controller that the image in memory is valid. - HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_SCE_RUN_EN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Tells the Sensor Controller that the image in memory is invalid. -//! -//! Use this function to tell the sensor controller that the image in memory is -//! invalid. Sensor Controller might wake up, but it will stay idle. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCAuxImageInvalid(void) -{ - // Tell the Sensor Controller that the image in memory is invalid. - HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_SCE_RUN_EN_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Get the power status of the device. -//! -//! The Always On (AON) domain is the only part of the device which is truly -//! "ALWAYS ON". The power status for the other device can always be read from -//! this status register. -//! -//! Possible power modes for the different parts of the device are: -//! -//! \return Returns the current power status of the device as a bitwise OR'ed -//! combination of these values: -//! - \ref AONWUC_AUX_POWER_DOWN -//! - \ref AONWUC_AUX_POWER_ON -//! - \ref AONWUC_JTAG_POWER_ON -//! - \ref AONWUC_MCU_POWER_ON -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONWUCPowerStatusGet(void) -{ - // Return the power status. - return (HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT)); -} - -//***************************************************************************** -// -//! \brief Enable shut-down of the device. -//! -//! Use this function to enable shut-down of the device. This will force all I/O values to -//! be latched - possibly enabling I/O wakeup - then all internal power -//! supplies are turned off, effectively putting the device into shut-down mode. -//! -//! \note No action will take place before the System CPU is put to deep sleep. -//! -//! \note The shut-down command is ignored if the JTAG interface has been -//! activated. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCShutDownEnable(void) -{ - // Ensure the JTAG domain is turned off; - // otherwise MCU domain can't be turned off. - HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; - - // Enable shutdown of the device. - HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 0; - HWREG(AON_WUC_BASE + AON_WUC_O_SHUTDOWN) = AON_WUC_SHUTDOWN_EN; -} - -//***************************************************************************** -// -//! \brief Enable power down mode on AUX and MCU domain. -//! -//! Use this function to enable powerdown on the AUX and MCU domain. -//! -//! \note The powerdown command is ignored if the JTAG interface has been -//! activated. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCDomainPowerDownEnable(void) -{ - // Ensure the JTAG domain is turned off; - // otherwise MCU domain can't be turned off. - HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; - - // Enable power down mode. - HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Use this function to disable power down mode of the MCU and AUX domain. -//! -//! Disabling powerdown on the MCU and/or AUX will put the domains in a -//! virtual power down when requesting to be powered down. Logic is the same -//! but power is kept on. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCDomainPowerDownDisable(void) -{ - // Disable power down mode. - HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Use this function to clear specific status bits. -//! -//! Use this function to clear the bits that are set in the AON WUC status -//! register. This register requires a write 1 to clear. -//! -//! AON Wake Up Controller TAP can request a total/full Flash erase. If so, -//! the corresponding status bits will be set in the status register and can -//! be read using \ref AONWUCMcuResetStatusGet() or cleared using this function. The reset -//! source and type give information about what and how the latest reset -//! was performed. Access to these bits are identical to the flash erase -//! bits. -//! -//! \param ui32Status defines in a one-hot encoding which bits to clear in the -//! status register. Use OR'ed combinations of the following: -//! - \ref AONWUC_MCU_RESET_SRC -//! - \ref AONWUC_MCU_WARM_RESET -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCMcuResetClear(uint32_t ui32Status) -{ - // Check the arguments. - ASSERT((ui32Status & AONWUC_MCU_RESET_SRC) || - (ui32Status & AONWUC_MCU_WARM_RESET)); - - // Clear the status bits. - HWREG(AON_WUC_BASE + AON_WUC_O_CTL1) = ui32Status; -} - -//***************************************************************************** -// -//! \brief Return the reset status. -//! -//! This function returns the value of the AON_WUC_O_CTL1 register. -//! -//! \return Returns the status from the AON WUC. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONWUCMcuResetStatusGet(void) -{ - // Return the current status. - return (HWREG(AON_WUC_BASE + AON_WUC_O_CTL1)); -} - -//***************************************************************************** -// -//! \brief Configure the recharge controller. -//! -//! The parameter \c bAdaptEnable is used to enable or disable the adaptive -//! algorithm for the recharge controller. -//! The adaptive algorithm for the recharge controller is defined as -//! -/*! -\verbatim - - New_Period = Period * (1 + (AdaptRate / 1024) ) - - AdaptRate - ----------- = ( 2^(-C1) + 2^(-C2) ) - 1024 - -\endverbatim -*/ -//! -//! Where C1 is between 1 and 10 and C2 is between 2 and 10. The \c ui32AdaptRate -//! must be a number between 2 and 768 (\ref RC_RATE_MIN and \ref RC_RATE_MAX) -//! resulting in an adaptive rate between 0.2% and 75%. -//! -//! The \c ui32Period is the number of 32 KHz clocks between two recharges. The -//! length of the interval is defined by the formula: -//! -/*! -\verbatim - - Period = ({ulMantissa,5'b1111} << ui32Exponent) - -\endverbatim -*/ -//! -//! \note The maximum number of recharge cycles is required when enabling the -//! adaptive recharge algorithm. -//! -//! \note The maximum period between two recharges should never exceed the -//! period between two oscillator amplitude calibrations which is configured -//! using AONWUCOscConfig(). -//! -//! \param bAdaptEnable enables the adaptation algorithm for the controller. -//! \param ui32AdaptRate determines the adjustment value for the adoption -//! algorithm. -//! \param ui32Period determines the number of clock cycles between each -//! activation of the recharge controller. -//! \param ui32MaxPeriod determines the maximum number of clock cycles between -//! each activation of the recharge controller. -//! -//! \return None -// -//***************************************************************************** -extern void AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, - uint32_t ui32AdaptRate, - uint32_t ui32Period, - uint32_t ui32MaxPeriod); - -//***************************************************************************** -// -//! \brief Get the current configuration of the recharge controller. -//! -//! This function returns the value of the register AON_WUC_O_RECHARGECFG. -//! -//! \return Returns the current configuration of the recharge controller. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONWUCRechargeCtrlConfigGet(void) -{ - // Return the current configuration. - return(HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG)); -} - -//***************************************************************************** -// -//! \brief Configure the interval for oscillator amplitude calibration. -//! -//! Use this function to set the number of 32 kHz clocks between oscillator -//! amplitude calibrations. -//! -//! The value of the interval is defined by the formula: -//! -/*! -\verbatim - - Period = ({ulMantissa,5'b1111} << ui32Exponent) - -\endverbatim -*/ -//! -//! \note When this counter expires an oscillator amplitude calibration is -//! triggered immediately in Active mode. When this counter expires in -//! Powerdown mode an internal flag is set that causes GBIAS to turn on -//! together with BGAP when the next recharge occurs, at the same time -//! triggering the oscillator amplitude calibration as well as a recharge of -//! the uLDO reference voltage. -//! -//! \note The oscillator amplitude calibration is performed at the same time -//! as the recharge for the uLDO reference voltage. So the maximum period -//! between each recharge operation should not exceed the number of clock -//! cycles for the amplitude calibration. -//! -//! \param ui32Period is the number of 32 kHz clock cycles in each interval. -//! -//! \return None -// -//***************************************************************************** -extern void AONWUCOscConfig(uint32_t ui32Period); - -//***************************************************************************** -// -//! \brief Request power off of the JTAG domain. -//! -//! The JTAG domain is automatically powered up on if a debugger is connected. -//! If a debugger is not connected this function can be used to power off the -//! JTAG domain. -//! -//! \note Achieving the lowest power modes (shutdown/powerdown) requires the -//! JTAG domain to be turned off. In general the JTAG domain should never be -//! powered in production code. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONWUCJtagPowerOff(void) -{ - // Request the power off of the Jtag domain - HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; -} - - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AONWUCAuxReset - #undef AONWUCAuxReset - #define AONWUCAuxReset ROM_AONWUCAuxReset - #endif - #ifdef ROM_AONWUCRechargeCtrlConfigSet - #undef AONWUCRechargeCtrlConfigSet - #define AONWUCRechargeCtrlConfigSet ROM_AONWUCRechargeCtrlConfigSet - #endif - #ifdef ROM_AONWUCOscConfig - #undef AONWUCOscConfig - #define AONWUCOscConfig ROM_AONWUCOscConfig - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AON_WUC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/aux_adc.c b/third_party/ti/devices/cc26x0/driverlib/aux_adc.c deleted file mode 100644 index 72b3d7823..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aux_adc.c +++ /dev/null @@ -1,333 +0,0 @@ -/****************************************************************************** -* Filename: aux_adc.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the AUX Time to Digital Converter interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aux_adc.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aux_wuc.h" -#include "../inc/hw_fcfg1.h" -#include "adi.h" -#include "event.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AUXADCDisable - #define AUXADCDisable NOROM_AUXADCDisable - #undef AUXADCEnableAsync - #define AUXADCEnableAsync NOROM_AUXADCEnableAsync - #undef AUXADCEnableSync - #define AUXADCEnableSync NOROM_AUXADCEnableSync - #undef AUXADCDisableInputScaling - #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling - #undef AUXADCFlushFifo - #define AUXADCFlushFifo NOROM_AUXADCFlushFifo - #undef AUXADCReadFifo - #define AUXADCReadFifo NOROM_AUXADCReadFifo - #undef AUXADCPopFifo - #define AUXADCPopFifo NOROM_AUXADCPopFifo - #undef AUXADCGetAdjustmentGain - #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain - #undef AUXADCGetAdjustmentOffset - #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset - #undef AUXADCValueToMicrovolts - #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts - #undef AUXADCMicrovoltsToValue - #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue - #undef AUXADCAdjustValueForGainAndOffset - #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset - #undef AUXADCUnadjustValueForGainAndOffset - #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset -#endif - -//***************************************************************************** -// -// Disables the ADC -// -//***************************************************************************** -void -AUXADCDisable(void) -{ - // Disable the ADC reference - ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M); - - // Assert reset and disable the ADC - ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M); - - // Ensure that scaling is enabled by default before next use of the ADC - ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); - - // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately) - HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = 0; - - // Disable the ADC data interface - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0; -} - -//***************************************************************************** -// -// Enables the ADC for asynchronous operation -// -//***************************************************************************** -void -AUXADCEnableAsync(uint32_t refSource, uint32_t trigger) -{ - // Enable the ADC reference, with the following options: - // - SRC: Set when using relative reference - // - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M); - - // Enable the ADC clock - HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = AUX_WUC_ADCCLKCTL_REQ_M; - while (!(HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) & AUX_WUC_ADCCLKCTL_ACK_M)); - - // Enable the ADC data interface - if (trigger == AUXADC_TRIGGER_MANUAL) { - // Manual trigger: No need to configure event routing from GPT - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 | AUX_ANAIF_ADCCTL_CMD_EN; - } else { - // GPT trigger: Configure event routing via MCU_EV to the AUX domain - HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; - } - - // Configure the ADC - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_SMPL_MODE_M); - - // Release reset and enable the ADC - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); -} - -//***************************************************************************** -// -// Enables the ADC for synchronous operation -// -//***************************************************************************** -void -AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger) -{ - // Enable the ADC reference, with the following options: - // - SRC: Set when using relative reference - // - REF_ON_IDLE: Set when using fixed reference and sample time < 21.3 us - uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M; - if (!refSource && (sampleTime < AUXADC_SAMPLE_TIME_21P3_US)) { - adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M; - } - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0); - - // Enable the ADC clock - HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = AUX_WUC_ADCCLKCTL_REQ_M; - while (!(HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) & AUX_WUC_ADCCLKCTL_ACK_M)); - - // Enable the ADC data interface - if (trigger == AUXADC_TRIGGER_MANUAL) { - // Manual trigger: No need to configure event routing from GPT - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 | AUX_ANAIF_ADCCTL_CMD_EN; - } else { - // GPT trigger: Configure event routing via MCU_EV to the AUX domain - HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; - } - - // Configure the ADC - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, sampleTime << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S); - - // Release reset and enable the ADC - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); -} - -//***************************************************************************** -// -// Disables scaling of the ADC input -// -//***************************************************************************** -void -AUXADCDisableInputScaling(void) -{ - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); -} - -//***************************************************************************** -// -// Flushes the ADC FIFO -// -//***************************************************************************** -void -AUXADCFlushFifo(void) -{ - HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) - HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) -} - -//***************************************************************************** -// -// Waits for and returns the first sample in the ADC FIFO -// -//***************************************************************************** -uint32_t -AUXADCReadFifo(void) { - - // Wait until there is at least one sample in the FIFO - while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M); - - // Return the first sample from the FIFO - return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); -} - -//***************************************************************************** -// -// Returns the first sample in the ADC FIFO, without waiting -// -//***************************************************************************** -uint32_t -AUXADCPopFifo(void) { - - // Return the first sample from the FIFO. If the FIFO is empty, this - // generates ADC FIFO underflow - return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); -} - -//***************************************************************************** -// -// Returns the gain value used when adjusting for ADC gain/offset -// -//***************************************************************************** -int32_t -AUXADCGetAdjustmentGain(uint32_t refSource) -{ - int32_t gain; - if (refSource == AUXADC_REF_FIXED) { - // AUXADC_REF_FIXED ==> ABS_GAIN - gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_ABS_GAIN) & FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S; - } else { - // AUXADC_REF_VDDS_REL ==> REL_GAIN - gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_REL_GAIN) & FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S; - } - return gain; -} - -//***************************************************************************** -// -// Returns the offset value used when adjusting for ADC gain/offset -// -//***************************************************************************** -int32_t -AUXADCGetAdjustmentOffset(uint32_t refSource) -{ - int8_t offset; - if ( refSource == AUXADC_REF_FIXED ) { - // AUXADC_REF_FIXED ==> ABS_OFFSET - offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S; - } else { - // AUXADC_REF_VDDS_REL ==> REL_OFFSET - offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S; - } - return offset; -} - -//***************************************************************************** -// -// Converts an "ideal" ADC value to microvolts -// -//***************************************************************************** -int32_t -AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue) -{ - // Chop off 4 bits during calculations to avoid 32-bit overflow - fixedRefVoltage >>= 4; - return (((adcValue * fixedRefVoltage) + 2047) / 4095) << 4; -} - -//***************************************************************************** -// -// Converts a number of microvolts to corresponding "ideal" ADC value -// -//***************************************************************************** -int32_t -AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts) -{ - // Chop off 4 bits during calculations to avoid 32-bit overflow - fixedRefVoltage >>= 4; - microvolts >>= 4; - return ((microvolts * 4095) + (fixedRefVoltage / 2)) / fixedRefVoltage; -} - -//***************************************************************************** -// -// Performs ADC value gain and offset adjustment -// -//***************************************************************************** -int32_t -AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) -{ - // Apply gain and offset adjustment - adcValue = (((adcValue + offset) * gain) + 16384) / 32768; - - // Saturate - if (adcValue < 0) { - return 0; - } else if (adcValue > 4095) { - return 4095; - } else { - return adcValue; - } -} - -//***************************************************************************** -// -// Performs the inverse of the ADC value gain and offset adjustment -// -//***************************************************************************** -int32_t -AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) -{ - // Apply inverse gain and offset adjustment - adcValue = (((adcValue * 32768) + (gain / 2)) / gain) - offset; - - // Saturate - if (adcValue < 0) { - return 0; - } else if (adcValue > 4095) { - return 4095; - } else { - return adcValue; - } -} diff --git a/third_party/ti/devices/cc26x0/driverlib/aux_adc.h b/third_party/ti/devices/cc26x0/driverlib/aux_adc.h deleted file mode 100644 index 69d271403..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aux_adc.h +++ /dev/null @@ -1,590 +0,0 @@ -/****************************************************************************** -* Filename: aux_adc.h -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Defines and prototypes for the AUX Analog-to-Digital -* Converter -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aux_group -//! @{ -//! \addtogroup auxadc_api -//! @{ -// -//***************************************************************************** - -#ifndef __AUX_ADC_H__ -#define __AUX_ADC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_event.h" -#include "../inc/hw_adi.h" -#include "../inc/hw_adi_4_aux.h" -#include "../inc/hw_aux_anaif.h" -#include "rom.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AUXADCDisable NOROM_AUXADCDisable - #define AUXADCEnableAsync NOROM_AUXADCEnableAsync - #define AUXADCEnableSync NOROM_AUXADCEnableSync - #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling - #define AUXADCFlushFifo NOROM_AUXADCFlushFifo - #define AUXADCReadFifo NOROM_AUXADCReadFifo - #define AUXADCPopFifo NOROM_AUXADCPopFifo - #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain - #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset - #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts - #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue - #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset - #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset -#endif - -//***************************************************************************** -// -// Defines for ADC reference sources. -// -//***************************************************************************** -#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) -#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) - -//***************************************************************************** -// -// Defines for the ADC FIFO status bits. -// -//***************************************************************************** -#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) -#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) -#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) -#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) -#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) - -//***************************************************************************** -// -// Defines for supported ADC triggers. -// -//***************************************************************************** -#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) -#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) -#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) -#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) -#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) -#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) -#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) -#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) -#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) - -//***************************************************************************** -// -// Defines for ADC sampling type for synchronous operation. -// -//***************************************************************************** -#define AUXADC_SAMPLE_TIME_2P7_US 3 -#define AUXADC_SAMPLE_TIME_5P3_US 4 -#define AUXADC_SAMPLE_TIME_10P6_US 5 -#define AUXADC_SAMPLE_TIME_21P3_US 6 -#define AUXADC_SAMPLE_TIME_42P6_US 7 -#define AUXADC_SAMPLE_TIME_85P3_US 8 -#define AUXADC_SAMPLE_TIME_170_US 9 -#define AUXADC_SAMPLE_TIME_341_US 10 -#define AUXADC_SAMPLE_TIME_682_US 11 -#define AUXADC_SAMPLE_TIME_1P37_MS 12 -#define AUXADC_SAMPLE_TIME_2P73_MS 13 -#define AUXADC_SAMPLE_TIME_5P46_MS 14 -#define AUXADC_SAMPLE_TIME_10P9_MS 15 - -//***************************************************************************** -// -// Equivalent voltages for fixed ADC reference, in microvolts. -// -//***************************************************************************** -#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 -#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 - - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - - -//***************************************************************************** -// -//! \brief Disables the ADC. -//! -//! This function must be called: -//! - Before re-enabling the ADC using \ref AUXADCEnableAsync() or -//! \ref AUXADCEnableSync() -//! - Before entering system standby -// -//***************************************************************************** -extern void AUXADCDisable(void); - -//***************************************************************************** -// -//! \brief Enables the ADC for asynchronous operation. -//! -//! In asynchronous operation, the ADC samples continuously between -//! conversions. -//! -//! The ADC trigger starts the conversion. Note that the first conversion may -//! be invalid if the sampling period is too short. -//! -//! ADC input scaling is enabled by default after device reset, and is also re- -//! enabled by \ref AUXADCDisable(). To disable input scaling, call -//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableAsync(). -//! -//! \param refSource -//! ADC reference source: -//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) -//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) -//! \param trigger -//! ADC conversion trigger: -//! - \ref AUXADC_TRIGGER_MANUAL -//! - \ref AUXADC_TRIGGER_GPT0A -//! - \ref AUXADC_TRIGGER_GPT0B -//! - \ref AUXADC_TRIGGER_GPT1A -//! - \ref AUXADC_TRIGGER_GPT1B -//! - \ref AUXADC_TRIGGER_GPT2A -//! - \ref AUXADC_TRIGGER_GPT2B -//! - \ref AUXADC_TRIGGER_GPT3A -//! - \ref AUXADC_TRIGGER_GPT3B -// -//***************************************************************************** -extern void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger); - -//***************************************************************************** -// -//! \brief Enables the ADC for synchronous operation. -//! -//! In synchronous operation, the ADC is idle between a conversion and -//! subsequent samplings. -//! -//! The ADC trigger starts sampling with specified duration, followed by the -//! conversion. Note that the first conversion may be invalid if the initial -//! sampling period is too short. -//! -//! ADC input scaling is enabled by default after device reset, and is also re- -//! enabled by \ref AUXADCDisable(). To disable input scaling, call -//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableSync(). -//! -//! \param refSource -//! ADC reference source: -//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) -//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) -//! \param sampleTime -//! ADC sampling time: -//! - \ref AUXADC_SAMPLE_TIME_2P7_US -//! - \ref AUXADC_SAMPLE_TIME_5P3_US -//! - \ref AUXADC_SAMPLE_TIME_10P6_US -//! - \ref AUXADC_SAMPLE_TIME_21P3_US -//! - \ref AUXADC_SAMPLE_TIME_42P6_US -//! - \ref AUXADC_SAMPLE_TIME_85P3_US -//! - \ref AUXADC_SAMPLE_TIME_170_US -//! - \ref AUXADC_SAMPLE_TIME_341_US -//! - \ref AUXADC_SAMPLE_TIME_682_US -//! - \ref AUXADC_SAMPLE_TIME_1P37_MS -//! - \ref AUXADC_SAMPLE_TIME_2P73_MS -//! - \ref AUXADC_SAMPLE_TIME_5P46_MS -//! - \ref AUXADC_SAMPLE_TIME_10P9_MS -//! \param trigger -//! ADC conversion trigger: -//! - \ref AUXADC_TRIGGER_MANUAL -//! - \ref AUXADC_TRIGGER_GPT0A -//! - \ref AUXADC_TRIGGER_GPT0B -//! - \ref AUXADC_TRIGGER_GPT1A -//! - \ref AUXADC_TRIGGER_GPT1B -//! - \ref AUXADC_TRIGGER_GPT2A -//! - \ref AUXADC_TRIGGER_GPT2B -//! - \ref AUXADC_TRIGGER_GPT3A -//! - \ref AUXADC_TRIGGER_GPT3B -// -//***************************************************************************** -extern void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger); - -//***************************************************************************** -// -//! \brief Disables scaling of the ADC input. -//! -//! By default, the ADC operates internally on a version of the input signal -//! that has been scaled down by a factor 1408 / 4095. This function -//! disables that scaling, allowing for a trade-off between dynamic range and -//! and resolution. -//! -//! \note This function must only be called while the ADC is disabled, before -//! calling \ref AUXADCEnableSync() or \ref AUXADCEnableAsync(). -//! \note Different input maximum ratings apply when input scaling is disabled. -//! Violating these may damage the device. -// -//***************************************************************************** -extern void AUXADCDisableInputScaling(void); - -//***************************************************************************** -// -//! \brief Flushes the ADC FIFO. -//! -//! This empties the FIFO and clears the underflow/overflow flags. -//! -//! Note: This function must only be called while the ADC is enabled. -// -//***************************************************************************** -extern void AUXADCFlushFifo(void); - -//***************************************************************************** -// -//! \brief Generates a single manual ADC trigger. -//! -//! For synchronous mode, the trigger starts sampling followed by conversion. -//! For asynchronous mode, the trigger starts conversion. -// -//***************************************************************************** -__STATIC_INLINE void -AUXADCGenManualTrigger(void) -{ - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCTRIG) = 0; -} - -//***************************************************************************** -// -//! \brief Returns flags indicating the status of the ADC FIFO. -//! -//! The flags indicate FIFO empty, full and almost full, and whether -//! overflow/underflow has occurred. -//! -//! \return -//! A combination (bitwise OR) of the following flags: -//! - \ref AUXADC_FIFO_EMPTY_M -//! - \ref AUXADC_FIFO_ALMOST_FULL_M -//! - \ref AUXADC_FIFO_FULL_M -//! - \ref AUXADC_FIFO_UNDERFLOW_M -//! - \ref AUXADC_FIFO_OVERFLOW_M -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXADCGetFifoStatus(void) -{ - return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT); -} - -//***************************************************************************** -// -//! \brief Waits for and returns the first sample in the ADC FIFO. -//! -//! This function waits until there is at least one sample in the ADC FIFO. It -//! then pops and returns the first sample from the FIFO. -//! -//! \note This procedure will deadlock if called without setting up ADC trigger -//! generation in advance. The trigger can either be manual or periodical -//! (using a GPT). -//! -//! \return The first (12-bit) sample from the ADC FIFO -// -//***************************************************************************** -extern uint32_t AUXADCReadFifo(void); - -//***************************************************************************** -// -//! \brief Returns the first sample in the ADC FIFO, without waiting. -//! -//! This function does not wait, and must only be called when there is at least -//! one sample in the ADC FIFO. Otherwise the call will generate FIFO underflow -//! (\ref AUXADC_FIFO_UNDERFLOW_M). -//! -//! \return The first (12-bit) sample from the ADC FIFO, or an undefined value -//! if the FIFO is empty -// -//***************************************************************************** -extern uint32_t AUXADCPopFifo(void); - -//***************************************************************************** -// -//! \brief Selects internal or external input for the ADC. -//! -//! Note that calling this function also selects the same input for AUX_COMPB. -//! -//! \param input -//! Internal/external input selection: -//! - \ref ADC_COMPB_IN_DCOUPL -//! - \ref ADC_COMPB_IN_VSS -//! - \ref ADC_COMPB_IN_VDDS -//! - \ref ADC_COMPB_IN_AUXIO7 -//! - \ref ADC_COMPB_IN_AUXIO6 -//! - \ref ADC_COMPB_IN_AUXIO5 -//! - \ref ADC_COMPB_IN_AUXIO4 -//! - \ref ADC_COMPB_IN_AUXIO3 -//! - \ref ADC_COMPB_IN_AUXIO2 -//! - \ref ADC_COMPB_IN_AUXIO1 -//! - \ref ADC_COMPB_IN_AUXIO0 -// -//***************************************************************************** -__STATIC_INLINE void -AUXADCSelectInput(uint32_t input) -{ - HapiSelectADCCompBInput(input); -} - -//***************************************************************************** -// -//! \brief Returns the gain value used when adjusting for ADC gain/offset. -//! -//! The function returns the gain value to be used with -//! \ref AUXADCAdjustValueForGainAndOffset() or -//! \ref AUXADCUnadjustValueForGainAndOffset(). The gain value is found during -//! chip manufacturing and is stored in the factory configuration, FCFG1. -//! -//! \param refSource -//! ADC reference source: -//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) -//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) -//! -//! \return -//! The gain value to be used in adjustments -// -//***************************************************************************** -extern int32_t AUXADCGetAdjustmentGain(uint32_t refSource); - -//***************************************************************************** -// -//! \brief Returns the offset value used when adjusting for ADC gain/offset. -//! -//! The function returns the offset value to be used with -//! \ref AUXADCAdjustValueForGainAndOffset() or -//! \ref AUXADCUnadjustValueForGainAndOffset(). The offset value is found -//! during chip manufacturing and is stored in the factory configuration, -//! FCFG1. -//! -//! \param refSource -//! ADC reference source: -//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) -//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) -//! -//! \return -//! The offset value to be used in adjustments -// -//***************************************************************************** -extern int32_t AUXADCGetAdjustmentOffset(uint32_t refSource); - -//***************************************************************************** -// -//! \brief Converts an "adjusted" ADC value to microvolts. -//! -//! This function can only be used when measuring with fixed ADC reference -//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for -//! whether the sampled ADC input is scaled down before conversion or not. -//! -//! \param fixedRefVoltage -//! Fixed reference voltage, in microvolts -//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) -//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input -//! \param adcValue -//! The ADC value -//! -//! \return -//! The corresponding number of microvolts -// -//***************************************************************************** -extern int32_t AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue); - -//***************************************************************************** -// -//! \brief Converts a number of microvolts to corresponding "adjusted" ADC value. -//! -//! This function can only be used when measuring with fixed ADC reference -//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for -//! whether the sampled ADC input is scaled down before conversion or not. -//! -//! \param fixedRefVoltage -//! Fixed reference voltage, in microvolts -//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) -//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input -//! \param microvolts -//! The number of microvolts -//! -//! \return -//! The corresponding expected ADC value (adjusted for ADC gain/offset) -// -//***************************************************************************** -extern int32_t AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts); - -//***************************************************************************** -// -//! \brief Performs ADC value gain and offset adjustment. -//! -//! This function takes a measured ADC value compensates for the internal gain -//! and offset in the ADC. -//! -//! \param adcValue -//! 12-bit ADC unadjusted value -//! \param gain -//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() -//! \param offset -//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() -//! -//! \return -//! 12-bit ADC adjusted value -// -//***************************************************************************** -extern int32_t AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); - -//***************************************************************************** -// -//! \brief Performs the inverse of the ADC value gain and offset adjustment. -//! -//! This function finds the expected measured ADC value, without gain and -//! offset compensation, for a given "ideal" ADC value. The function can for -//! example be used to find ADC value thresholds to be used in Sensor -//! Controller task configurations. -//! -//! \param adcValue -//! 12-bit ADC adjusted value -//! \param gain -//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() -//! \param offset -//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() -//! -//! \return -//! 12-bit ADC unadjusted value -// -//***************************************************************************** -extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AUXADCDisable - #undef AUXADCDisable - #define AUXADCDisable ROM_AUXADCDisable - #endif - #ifdef ROM_AUXADCEnableAsync - #undef AUXADCEnableAsync - #define AUXADCEnableAsync ROM_AUXADCEnableAsync - #endif - #ifdef ROM_AUXADCEnableSync - #undef AUXADCEnableSync - #define AUXADCEnableSync ROM_AUXADCEnableSync - #endif - #ifdef ROM_AUXADCDisableInputScaling - #undef AUXADCDisableInputScaling - #define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling - #endif - #ifdef ROM_AUXADCFlushFifo - #undef AUXADCFlushFifo - #define AUXADCFlushFifo ROM_AUXADCFlushFifo - #endif - #ifdef ROM_AUXADCReadFifo - #undef AUXADCReadFifo - #define AUXADCReadFifo ROM_AUXADCReadFifo - #endif - #ifdef ROM_AUXADCPopFifo - #undef AUXADCPopFifo - #define AUXADCPopFifo ROM_AUXADCPopFifo - #endif - #ifdef ROM_AUXADCGetAdjustmentGain - #undef AUXADCGetAdjustmentGain - #define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain - #endif - #ifdef ROM_AUXADCGetAdjustmentOffset - #undef AUXADCGetAdjustmentOffset - #define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset - #endif - #ifdef ROM_AUXADCValueToMicrovolts - #undef AUXADCValueToMicrovolts - #define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts - #endif - #ifdef ROM_AUXADCMicrovoltsToValue - #undef AUXADCMicrovoltsToValue - #define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue - #endif - #ifdef ROM_AUXADCAdjustValueForGainAndOffset - #undef AUXADCAdjustValueForGainAndOffset - #define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset - #endif - #ifdef ROM_AUXADCUnadjustValueForGainAndOffset - #undef AUXADCUnadjustValueForGainAndOffset - #define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AUX_ADC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/aux_smph.c b/third_party/ti/devices/cc26x0/driverlib/aux_smph.c deleted file mode 100644 index a5d3f0864..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aux_smph.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: aux_smph.c -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Driver for the AUX Semaphore. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aux_smph.h" - -// See aux_smph.h for implementation diff --git a/third_party/ti/devices/cc26x0/driverlib/aux_smph.h b/third_party/ti/devices/cc26x0/driverlib/aux_smph.h deleted file mode 100644 index d2d6d4d32..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aux_smph.h +++ /dev/null @@ -1,258 +0,0 @@ -/****************************************************************************** -* Filename: aux_smph.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AUX Semaphore -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aux_group -//! @{ -//! \addtogroup auxsmph_api -//! @{ -// -//***************************************************************************** - -#ifndef __AUX_SMPH_H__ -#define __AUX_SMPH_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_aux_smph.h" -#include "../inc/hw_memmap.h" -#include "debug.h" - -//***************************************************************************** -// -// General constants and defines -// -//***************************************************************************** -#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed -#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed - -//***************************************************************************** -// -// Values that can be passed to AUXSMPHAcquire and AUXSMPHRelease -// as the ui32Semaphore parameter. -// -//***************************************************************************** -#define AUX_SMPH_0 0 // AUX Semaphore 0 -#define AUX_SMPH_1 1 // AUX Semaphore 1 -#define AUX_SMPH_2 2 // AUX Semaphore 2 -#define AUX_SMPH_3 3 // AUX Semaphore 3 -#define AUX_SMPH_4 4 // AUX Semaphore 4 -#define AUX_SMPH_5 5 // AUX Semaphore 5 -#define AUX_SMPH_6 6 // AUX Semaphore 6 -#define AUX_SMPH_7 7 // AUX Semaphore 7 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Acquire an AUX semaphore. -//! -//! This function acquires the given AUX semaphore, blocking the call until -//! the semaphore is available. -//! -//! \note The semaphore can also be acquired by the dedicated Sensor Controller. -//! The System CPU master can thus be competing for the shared resource, i.e. -//! the specified semaphore. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref AUX_SMPH_0 -//! - \ref AUX_SMPH_1 -//! - \ref AUX_SMPH_2 -//! - \ref AUX_SMPH_3 -//! - \ref AUX_SMPH_4 -//! - \ref AUX_SMPH_5 -//! - \ref AUX_SMPH_6 -//! - \ref AUX_SMPH_7 -//! -//! \return None -//! -//! \sa AUXSMPHTryAcquire(), AUXSMPHRelease() -// -//***************************************************************************** -__STATIC_INLINE void -AUXSMPHAcquire(uint32_t ui32Semaphore) -{ - // Check the arguments. - ASSERT((ui32Semaphore == AUX_SMPH_0) || - (ui32Semaphore == AUX_SMPH_1) || - (ui32Semaphore == AUX_SMPH_2) || - (ui32Semaphore == AUX_SMPH_3) || - (ui32Semaphore == AUX_SMPH_4) || - (ui32Semaphore == AUX_SMPH_5) || - (ui32Semaphore == AUX_SMPH_6) || - (ui32Semaphore == AUX_SMPH_7)); - - // Wait for semaphore to be released such that it can be claimed - // Semaphore register reads 1 when lock was acquired otherwise 0 - // (i.e. AUX_SMPH_CLAIMED). - while(HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) == - AUX_SMPH_CLAIMED) - { - } -} - -//***************************************************************************** -// -//! \brief Try to acquire an AUX semaphore. -//! -//! This function tries to acquire the given AUX semaphore, if the semaphore -//! could not be claimed the function returns false. -//! -//! \note The semaphore can also be acquired by the dedicated Sensor Controller. -//! The System CPU master can thus be competing for the shared resource, i.e. -//! the specified semaphore. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref AUX_SMPH_0 -//! - \ref AUX_SMPH_1 -//! - \ref AUX_SMPH_2 -//! - \ref AUX_SMPH_3 -//! - \ref AUX_SMPH_4 -//! - \ref AUX_SMPH_5 -//! - \ref AUX_SMPH_6 -//! - \ref AUX_SMPH_7 -//! -//! \return Returns true if semaphore was acquired, false otherwise -//! -//! \sa AUXSMPHAcquire(), AUXSMPHRelease() -// -//***************************************************************************** -__STATIC_INLINE bool -AUXSMPHTryAcquire(uint32_t ui32Semaphore) -{ - uint32_t ui32SemaReg; - - // Check the arguments. - ASSERT((ui32Semaphore == AUX_SMPH_0) || - (ui32Semaphore == AUX_SMPH_1) || - (ui32Semaphore == AUX_SMPH_2) || - (ui32Semaphore == AUX_SMPH_3) || - (ui32Semaphore == AUX_SMPH_4) || - (ui32Semaphore == AUX_SMPH_5) || - (ui32Semaphore == AUX_SMPH_6) || - (ui32Semaphore == AUX_SMPH_7)); - - // AUX Semaphore register reads 1 if lock was acquired - // (i.e. SMPH_FREE when read) but subsequent reads will read 0. - ui32SemaReg = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore); - - return (ui32SemaReg == AUX_SMPH_FREE); -} - -//***************************************************************************** -// -//! \brief Release an AUX semaphore by System CPU master. -//! -//! This function releases the given AUX semaphore. -//! -//! \note It is up to the application to provide the convention for clearing -//! semaphore. -//! -//! \note The semaphore can also be acquired by the dedicated Sensor Controller. -//! The System CPU master can thus be competing for the shared resource, i.e. -//! the specified semaphore. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref AUX_SMPH_0 -//! - \ref AUX_SMPH_1 -//! - \ref AUX_SMPH_2 -//! - \ref AUX_SMPH_3 -//! - \ref AUX_SMPH_4 -//! - \ref AUX_SMPH_5 -//! - \ref AUX_SMPH_6 -//! - \ref AUX_SMPH_7 -//! -//! \return None -//! -//! \sa AUXSMPHAcquire(), AUXSMPHTryAcquire() -// -//***************************************************************************** -__STATIC_INLINE void -AUXSMPHRelease(uint32_t ui32Semaphore) -{ - // Check the arguments. - ASSERT((ui32Semaphore == AUX_SMPH_0) || - (ui32Semaphore == AUX_SMPH_1) || - (ui32Semaphore == AUX_SMPH_2) || - (ui32Semaphore == AUX_SMPH_3) || - (ui32Semaphore == AUX_SMPH_4) || - (ui32Semaphore == AUX_SMPH_5) || - (ui32Semaphore == AUX_SMPH_6) || - (ui32Semaphore == AUX_SMPH_7)); - - // No check before release. It is up to the application to provide the - // conventions for who and when a semaphore can be released. - HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) = - AUX_SMPH_FREE; -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AUX_SMPH_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/aux_tdc.c b/third_party/ti/devices/cc26x0/driverlib/aux_tdc.c deleted file mode 100644 index 6bbcf55a5..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aux_tdc.c +++ /dev/null @@ -1,111 +0,0 @@ -/****************************************************************************** -* Filename: aux_tdc.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the AUX Time to Digital Converter interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aux_tdc.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AUXTDCConfigSet - #define AUXTDCConfigSet NOROM_AUXTDCConfigSet - #undef AUXTDCMeasurementDone - #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone -#endif - -//***************************************************************************** -// -// Configure the operation of the AUX TDC -// -//***************************************************************************** -void -AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, - uint32_t ui32StopCondition) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Make sure the AUX TDC is in the idle state before changing the - // configuration. - while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) - { - } - - // Clear previous results. - HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; - - // Change the configuration. - HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; -} - -//***************************************************************************** -// -// Check if the AUX TDC is done measuring -// -//***************************************************************************** -uint32_t -AUXTDCMeasurementDone(uint32_t ui32Base) -{ - uint32_t ui32Reg; - uint32_t ui32Status; - - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Check if the AUX TDC is done measuring. - ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); - if(ui32Reg & AUX_TDC_STAT_DONE) - { - ui32Status = AUX_TDC_DONE; - } - else if(ui32Reg & AUX_TDC_STAT_SAT) - { - ui32Status = AUX_TDC_TIMEOUT; - } - else - { - ui32Status = AUX_TDC_BUSY; - } - - // Return the status. - return (ui32Status); -} diff --git a/third_party/ti/devices/cc26x0/driverlib/aux_tdc.h b/third_party/ti/devices/cc26x0/driverlib/aux_tdc.h deleted file mode 100644 index c66bced5c..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aux_tdc.h +++ /dev/null @@ -1,776 +0,0 @@ -/****************************************************************************** -* Filename: aux_tdc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Time-to-Digital Converter -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aux_group -//! @{ -//! \addtogroup auxtdc_api -//! @{ -// -//***************************************************************************** - -#ifndef __AUX_TDC_H__ -#define __AUX_TDC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aux_tdc.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AUXTDCConfigSet NOROM_AUXTDCConfigSet - #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone -#endif - -//***************************************************************************** -// -// Defines for the status of a AUX TDC measurement. -// -//***************************************************************************** -#define AUX_TDC_BUSY 0x00000001 -#define AUX_TDC_TIMEOUT 0x00000002 -#define AUX_TDC_DONE 0x00000004 - -//***************************************************************************** -// -// Defines for the control of a AUX TDC. -// -//***************************************************************************** -#define AUX_TDC_RUNSYNC 0x00000001 -#define AUX_TDC_RUN 0x00000002 -#define AUX_TDC_ABORT 0x00000003 - -//***************************************************************************** -// -// Defines for possible states of the TDC internal state machine. -// -//***************************************************************************** -#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) -#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) -#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) -#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) -#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) -#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) -#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) -#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) -#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) -#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) -#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) - -//***************************************************************************** -// -// Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet(). -// -//***************************************************************************** -#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event -#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event - -#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) -#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) -#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) -#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) -#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) -#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) -#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) -#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) -#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) -#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) -#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) -#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) -#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) -#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) -#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) -#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) -#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE) -#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL) -#define AUXTDC_STOP_AON_PROG_WU (AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU) -#define AUXTDC_STOP_AON_SW (AUX_TDC_TRIGSRC_STOP_SRC_AON_SW) -#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET) -#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0) -#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1) -#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE) -#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE) -#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV) -#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV) -#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) -#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) -#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) -#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) -#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) - -#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event -#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event - -#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) -#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) -#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) -#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) -#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) -#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) -#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) -#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) -#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) -#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) -#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) -#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) -#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) -#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) -#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) -#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) -#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_ADC_DONE) -#define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL) -#define AUXTDC_START_AON_PROG_WU (AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU) -#define AUXTDC_START_AON_SW (AUX_TDC_TRIGSRC_START_SRC_AON_SW) -#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET) -#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX0) -#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX1) -#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE) -#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_TDC_PRE) -#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV) -#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV) -#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) -#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) -#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) -#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) -#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) - -//***************************************************************************** -// -// Defines for the possible saturation values set using AUXTDCLimitSet(). -// -//***************************************************************************** -#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) -#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) -#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) -#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) -#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) -#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) -#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) -#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) -#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) -#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) -#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) -#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) -#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) -#define AUXTDC_NUM_SAT_VALS 16 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! \brief Checks an AUX TDC base address. -//! -//! This function determines if a AUX TDC port base address is valid. -//! -//! \param ui32Base is the base address of the AUX TDC port. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -AUXTDCBaseValid(uint32_t ui32Base) -{ - return(ui32Base == AUX_TDC_BASE); -} -#endif - -//***************************************************************************** -// -//! \brief Get the status of the AUX TDC internal state machine. -//! -//! This function will return the current state of the AUX TDC internal state -//! machine. -//! \param ui32Base is base address of the AUX TDC -//! -//! \return Returns the current state of the state machine. -//! Possible states for the state machine are: -//! - \ref AUXTDC_WAIT_START -//! - \ref AUXTDC_WAIT_START_CNTEN -//! - \ref AUXTDC_IDLE -//! - \ref AUXTDC_CLRCNT -//! - \ref AUXTDC_WAIT_STOP -//! - \ref AUXTDC_WAIT_STOP_CNTDOWN -//! - \ref AUXTDC_GETRESULTS -//! - \ref AUXTDC_POR -//! - \ref AUXTDC_WAIT_CLRCNT_DONE -//! - \ref AUXTDC_START_FALL -//! - \ref AUXTDC_FORCE_STOP. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXTDCStatusGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Return the status value for the correct ADI Slave. - return((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) >> - AUX_TDC_STAT_STATE_S); -} - -//***************************************************************************** -// -//! \brief Configure the operation of the AUX TDC. -//! -//! Use this function to configure the start and stop event for the AUX TDC. -//! -//! The \c ui32StartCondition must be a bitwise OR of the start event and the -//! polarity of the start event. The start events are: -//! - \ref AUXTDC_START_AUXIO0 -//! - \ref AUXTDC_START_AUXIO1 -//! - \ref AUXTDC_START_AUXIO2 -//! - \ref AUXTDC_START_AUXIO3 -//! - \ref AUXTDC_START_AUXIO4 -//! - \ref AUXTDC_START_AUXIO5 -//! - \ref AUXTDC_START_AUXIO6 -//! - \ref AUXTDC_START_AUXIO7 -//! - \ref AUXTDC_START_AUXIO8 -//! - \ref AUXTDC_START_AUXIO9 -//! - \ref AUXTDC_START_AUXIO10 -//! - \ref AUXTDC_START_AUXIO11 -//! - \ref AUXTDC_START_AUXIO12 -//! - \ref AUXTDC_START_AUXIO13 -//! - \ref AUXTDC_START_AUXIO14 -//! - \ref AUXTDC_START_AUXIO15 -//! - \ref AUXTDC_START_ADC_DONE -//! - \ref AUXTDC_START_ADC_FIFO_ALMOST_FULL -//! - \ref AUXTDC_START_AON_PROG_WU -//! - \ref AUXTDC_START_AON_SW -//! - \ref AUXTDC_START_ISRC_RESET -//! - \ref AUXTDC_START_OBSMUX0 -//! - \ref AUXTDC_START_OBSMUX1 -//! - \ref AUXTDC_START_SMPH_AUTOTAKE_DONE -//! - \ref AUXTDC_START_TDC_PRE -//! - \ref AUXTDC_START_TIMER0_EV -//! - \ref AUXTDC_START_TIMER1_EV -//! - \ref AUXTDC_START_AON_RTC_CH2 -//! - \ref AUXTDC_START_AUX_COMPA -//! - \ref AUXTDC_START_AUX_COMPB -//! - \ref AUXTDC_START_ACLK_REF -//! - \ref AUXTDC_START_MCU_EV -//! -//! The polarity of the start event is either rising \ref AUXTDC_STARTPOL_RIS -//! or falling \ref AUXTDC_STARTPOL_FALL. -//! -//! The \c ui32StopCondition must be a bitwise OR of the stop event and the -//! polarity of the stop event. The stop events are: -//! - \ref AUXTDC_STOP_AUXIO0 -//! - \ref AUXTDC_STOP_AUXIO1 -//! - \ref AUXTDC_STOP_AUXIO2 -//! - \ref AUXTDC_STOP_AUXIO3 -//! - \ref AUXTDC_STOP_AUXIO4 -//! - \ref AUXTDC_STOP_AUXIO5 -//! - \ref AUXTDC_STOP_AUXIO6 -//! - \ref AUXTDC_STOP_AUXIO7 -//! - \ref AUXTDC_STOP_AUXIO8 -//! - \ref AUXTDC_STOP_AUXIO9 -//! - \ref AUXTDC_STOP_AUXIO10 -//! - \ref AUXTDC_STOP_AUXIO11 -//! - \ref AUXTDC_STOP_AUXIO12 -//! - \ref AUXTDC_STOP_AUXIO13 -//! - \ref AUXTDC_STOP_AUXIO14 -//! - \ref AUXTDC_STOP_AUXIO15 -//! - \ref AUXTDC_STOP_ADC_DONE -//! - \ref AUXTDC_STOP_ADC_FIFO_ALMOST_FULL -//! - \ref AUXTDC_STOP_AON_PROG_WU -//! - \ref AUXTDC_STOP_AON_SW -//! - \ref AUXTDC_STOP_ISRC_RESET -//! - \ref AUXTDC_STOP_OBSMUX0 -//! - \ref AUXTDC_STOP_OBSMUX1 -//! - \ref AUXTDC_STOP_SMPH_AUTOTAKE_DONE -//! - \ref AUXTDC_STOP_TDC_PRE -//! - \ref AUXTDC_STOP_TIMER0_EV -//! - \ref AUXTDC_STOP_TIMER1_EV -//! - \ref AUXTDC_STOP_AON_RTC_CH2 -//! - \ref AUXTDC_STOP_AUX_COMPA -//! - \ref AUXTDC_STOP_AUX_COMPB -//! - \ref AUXTDC_STOP_ACLK_REF -//! - \ref AUXTDC_STOP_MCU_EV -//! -//! The polarity of the stop event is either rising \ref AUXTDC_STOPPOL_RIS -//! or falling \ref AUXTDC_STOPPOL_FALL. -//! -//! \note The AUX TDC should only be configured when the AUX TDC is in the Idle -//! state. To ensure that software does not lock up, it is recommended to -//! ensure that the AUX TDC is actually in idle when calling \ref AUXTDCConfigSet(). -//! This can be tested using \ref AUXTDCIdle(). -//! -//! \param ui32Base is base address of the AUX TDC. -//! \param ui32StartCondition is AUX TDC a bitwise OR of a start event and polarity. -//! \param ui32StopCondition is AUX TDC a bitwise OR of a stop event and polarity. -//! -//! \return None -//! -//! \sa \ref AUXTDCConfigSet(), \ref AUXTDCIdle() -// -//***************************************************************************** -extern void AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, - uint32_t ui32StopCondition); - -//***************************************************************************** -// -//! \brief Check if the AUX TDC is in idle mode. -//! -//! This function can be used to check whether the AUX TDC internal state -//! machine is in idle mode. This is required before setting the polarity -//! of the start and stop event. -//! -//! \param ui32Base is the base address of the AUX TDC. -//! -//! \return Returns \c true if state machine is in idle and returns \c false -//! if the state machine is in any other state. -// -//***************************************************************************** -__STATIC_INLINE bool -AUXTDCIdle(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Check if the AUX TDC is in the Idle state. - return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE) ? true : false); -} - -//***************************************************************************** -// -//! \brief Enable the AUX TDC for a measurement. -//! -//! This function is used for arming the AUX TDC to begin a measurement as -//! soon as the start condition is met. There are two run modes: -//! - \ref AUX_TDC_RUNSYNC will wait for a falling event of the start pulse before -//! starting measurement on next rising edge of start. This guarantees an edge -//! triggered start and is recommended for frequency measurements. If the -//! first falling edge is close to the start command it may be missed, but -//! the TDC shall catch later falling edges and in any case guarantee a -//! measurement start synchronous to the rising edge of the start event. -//! - The \ref AUX_TDC_RUN is asynchronous start and asynchronous stop mode. Using -//! this a TDC measurement may start immediately if start is high and hence it -//! may not give precise edge to edge measurements. This mode is only -//! recommended when start pulse is guaranteed to arrive at least 7 clock -//! periods after command. -//! -//! \note The AUX TDC should be configured and in Idle mode before calling this -//! function. -//! -//! \param ui32Base is the base address of the AUX TDC. -//! \param ui32RunMode is the run mode for the AUX TDC. -//! - \ref AUX_TDC_RUNSYNC : Synchronous run mode. -//! - \ref AUX_TDC_RUN : Asynchronous run mode. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AUXTDCEnable(uint32_t ui32Base, uint32_t ui32RunMode) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - ASSERT((ui32RunMode == AUX_TDC_RUN) || - (ui32RunMode == AUX_TDC_RUNSYNC)); - - // Enable the AUX TDC. - HWREG(ui32Base + AUX_TDC_O_CTL) = ui32RunMode; -} - -//***************************************************************************** -// -//! \brief Force the AUX TDC back to Idle mode. -//! -//! This function will force the AUX TDC in Idle mode. The internal state -//! machine will not go directly to Idle mode, so it is left to the programmer to -//! ensure that the state machine is in Idle mode before doing any new -//! configuration. This can be checked using \ref AUXTDCIdle(). -//! -//! \param ui32Base is the base address of the AUX TDC. -//! -//! \return None -//! -//! \sa \ref AUXTDCIdle() -// -//***************************************************************************** -__STATIC_INLINE void -AUXTDCIdleForce(uint32_t ui32Base) -{ - // Check the arguments - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Abort operation of AUX TDC and force into Idle mode. - HWREG(ui32Base + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT; -} - -//***************************************************************************** -// -//! \brief Check if the AUX TDC is done measuring. -//! -//! This function can be used to check whether the AUX TDC has finished a -//! measurement. The AUX TDC may have completed a measurement for two reasons. -//! Either it finish successfully \ref AUX_TDC_DONE or it failed due to a timeout -//! \ref AUX_TDC_TIMEOUT. If the AUX TDC is still measuring it this function -//! will return \ref AUX_TDC_BUSY. -//! -//! \param ui32Base is the base address of the AUX TDC. -//! -//! \return Returns the current status of a measurement: -//! - \ref AUX_TDC_DONE : An AUX TDC measurement finished successfully. -//! - \ref AUX_TDC_TIMEOUT : An AUX TDC measurement failed due to timeout. -//! - \ref AUX_TDC_BUSY : An AUX TDC measurement is being performed. -// -//***************************************************************************** -extern uint32_t AUXTDCMeasurementDone(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Get the value of the latest measurement. -//! -//! This function is used for retrieving the value of the latest measurement -//! performed by the AUX TDC. -//! -//! \param ui32Base is the base address of the AUX TDC. -//! -//! \return Returns the result of the latest measurement. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXTDCMeasurementGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Return the measurement. - return (HWREG(ui32Base + AUX_TDC_O_RESULT)); -} - -//***************************************************************************** -// -//! \brief Set the saturation limit of the measurement. -//! -//! This function is used to set a saturation limit for the event accumulation -//! register. The saturation limit is defined as a bit width of the -//! accumulation register and therefore increases in power of 2. -//! -//! \param ui32Base is base address of the AUX TDC. -//! \param ui32Limit is the saturation limit. -//! - \ref AUXTDC_SAT_4096 -//! - \ref AUXTDC_SAT_8192 -//! - \ref AUXTDC_SAT_16384 -//! - \ref AUXTDC_SAT_32768 -//! - \ref AUXTDC_SAT_65536 -//! - \ref AUXTDC_SAT_131072 -//! - \ref AUXTDC_SAT_262144 -//! - \ref AUXTDC_SAT_524288 -//! - \ref AUXTDC_SAT_1048576 -//! - \ref AUXTDC_SAT_2097152 -//! - \ref AUXTDC_SAT_4194304 -//! - \ref AUXTDC_SAT_8388608 -//! - \ref AUXTDC_SAT_16777216 (default) -//! -//! \return None -//! -//! \note The actual value of the accumulation register might increase slightly beyond -//! the saturation value before the saturation takes effect. -//! -//! \sa \ref AUXTDCLimitGet() -// -//***************************************************************************** -__STATIC_INLINE void -AUXTDCLimitSet(uint32_t ui32Base, uint32_t ui32Limit) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - ASSERT(ui32Limit < AUXTDC_NUM_SAT_VALS); - - // Set the saturation limit. - HWREG(ui32Base + AUX_TDC_O_SATCFG) = ui32Limit; -} - -//***************************************************************************** -// -//! \brief Get the saturation limit of the measurement. -//! -//! This function is used to retrieve the current saturation for the -//! accumulator register. -//! -//! \param ui32Base is base address of the AUX TDC. -//! -//! \return Returns the saturation limit. -//! - \ref AUXTDC_SAT_4096 -//! - \ref AUXTDC_SAT_8192 -//! - \ref AUXTDC_SAT_16384 -//! - \ref AUXTDC_SAT_32768 -//! - \ref AUXTDC_SAT_65536 -//! - \ref AUXTDC_SAT_131072 -//! - \ref AUXTDC_SAT_262144 -//! - \ref AUXTDC_SAT_524288 -//! - \ref AUXTDC_SAT_1048576 -//! - \ref AUXTDC_SAT_2097152 -//! - \ref AUXTDC_SAT_4194304 -//! - \ref AUXTDC_SAT_8388608 -//! - \ref AUXTDC_SAT_16777216 -//! -//! \sa \ref AUXTDCLimitSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXTDCLimitGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Return the saturation limit. - return (HWREG(ui32Base + AUX_TDC_O_SATCFG)); -} - -//***************************************************************************** -// -//! \brief Enables the counter if possible. -//! -//! This function can be used to enable the AUX TDC stop/compare event counter. -//! The counter can be used to measure multiple periods of a clock signal. -//! For each stop/compare event the counter will be decremented by one and -//! the measurement will continue running until the value of the counter -//! reaches 0. The current value of the counter can be read using -//! \ref AUXTDCCounterGet(). The reset value of the counter can be set using -//! \ref AUXTDCCounterSet(). -//! -//! \param ui32Base is base address of the AUX TDC. -//! -//! \return Returns \c true if the counter was successfully enabled. If the -//! AUX TDC is not in Idle mode, the counter can not be enabled, and the -//! return value will be \c false. -//! -//! \sa \ref AUXTDCCounterGet(), \ref AUXTDCCounterSet() -// -//***************************************************************************** -__STATIC_INLINE bool -AUXTDCCounterEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Check if the AUX TDC is in idle mode. If not in Idle mode, the counter - // will not be enabled. - if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) - { - return false; - } - - // Enable the counter. - HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN; - - // Counter successfully enabled. - return true; -} - -//***************************************************************************** -// -//! \brief Disables the counter if possible. -//! -//! This function can be used to disable the AUX TDC stop/compare event counter. -//! -//! \param ui32Base is base address of the AUX TDC. -//! -//! \return Returns \c true if the counter was successfully disabled. If the -//! AUX TDC is not in Idle mode, the counter can not be disabled, and the -//! return value will be \c false. -//! -//! \sa \ref AUXTDCCounterEnable() for more information on how to use the counter. -// -//***************************************************************************** -__STATIC_INLINE bool -AUXTDCCounterDisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter - // will not be disabled. - if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) - { - return false; - } - - // Disable the counter. - HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = 0; - - // Counter successfully disabled. - return true; -} - -//***************************************************************************** -// -//! \brief Set the reset number of counter compare/stop event to ignore before taking -//! a measurement. -//! -//! This function loads the reset value of the counter with the specified -//! number of events to ignore. A reset in this context means the counter -//! has been disabled and then enabled. -//! -//! \param ui32Base is base address of the AUX TDC. -//! \param ui32Events is the number of compare/stop events to load into the -//! counter. -//! -//! \return Returns \c true if the counter was successfully updated. If the -//! AUX TDC is not in Idle mode, the counter can not be updated, and the -//! return value will be \c false. -//! -//! \sa \ref AUXTDCCounterEnable() -// -//***************************************************************************** -__STATIC_INLINE bool -AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Check if the AUX TDC is in idle mode. If not in idle mode, the counter - // will not be disabled. - if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) - { - return false; - } - - // Update the reset counter value. - HWREG(ui32Base + AUX_TDC_O_TRIGCNTLOAD) = ui32Events; - - // Counter successfully updated. - return true; -} - -//***************************************************************************** -// -//! \brief Get the current number of counter compare/stop event to ignore before -//! taking a measurement. -//! -//! This function returns the current value of compare/stop events before -//! a measurement is registered. This value is decremented by one for each -//! registered compare/stop event and will always be less than or equal the -//! reset value of the counter set using \ref AUXTDCCounterSet(). -//! -//! \param ui32Base is base address of the AUX TDC. -//! -//! \return Returns the current value of compare/stop events ignored before a -//! measurement is performed. -//! -//! \sa \ref AUXTDCCounterEnable(). -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXTDCCounterGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Return the current counter value. - return (HWREG(ui32Base + AUX_TDC_O_TRIGCNT)); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AUXTDCConfigSet - #undef AUXTDCConfigSet - #define AUXTDCConfigSet ROM_AUXTDCConfigSet - #endif - #ifdef ROM_AUXTDCMeasurementDone - #undef AUXTDCMeasurementDone - #define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AUX_TDC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/aux_timer.c b/third_party/ti/devices/cc26x0/driverlib/aux_timer.c deleted file mode 100644 index 686009bab..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aux_timer.c +++ /dev/null @@ -1,251 +0,0 @@ -/****************************************************************************** -* Filename: aux_timer.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the AUX Timer Module -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aux_timer.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AUXTimerConfigure - #define AUXTimerConfigure NOROM_AUXTimerConfigure - #undef AUXTimerStart - #define AUXTimerStart NOROM_AUXTimerStart - #undef AUXTimerStop - #define AUXTimerStop NOROM_AUXTimerStop - #undef AUXTimerPrescaleSet - #define AUXTimerPrescaleSet NOROM_AUXTimerPrescaleSet - #undef AUXTimerPrescaleGet - #define AUXTimerPrescaleGet NOROM_AUXTimerPrescaleGet -#endif - -//***************************************************************************** -// -// Configure AUX timer -// -//***************************************************************************** -void -AUXTimerConfigure(uint32_t ui32Timer, uint32_t ui32Config) -{ - uint32_t ui32Val; - - // Check the arguments. - ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || - (ui32Timer == AUX_TIMER_BOTH)); - - // Configure Timer 0. - if(ui32Timer & AUX_TIMER_0) - { - // Stop timer 0. - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; - - // Set mode. - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); - ui32Val &= ~(AUX_TIMER_T0CFG_MODE_M | AUX_TIMER_T0CFG_RELOAD_M); - ui32Val |= (ui32Config & (AUX_TIMER_T0CFG_MODE_M | - AUX_TIMER_T0CFG_RELOAD_M)); - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; - - // If edge counter, set rising/falling edge and tick source. - if(ui32Config & AUX_TIMER_T0CFG_MODE_M) - { - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); - ui32Val &= ~(AUX_TIMER_T0CFG_TICK_SRC_POL_M | - AUX_TIMER_T0CFG_TICK_SRC_M); - - // Set edge polarity. - if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) - { - ui32Val |= AUX_TIMER_T0CFG_TICK_SRC_POL; - } - - // Set tick source. - ui32Val |= (ui32Config & AUX_TIMER_T0CFG_TICK_SRC_M); - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; - } - } - - // Configure Timer 1. - if(ui32Timer & AUX_TIMER_1) - { - // Stop timer 1. - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; - - // Set mode. - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); - ui32Val &= ~(AUX_TIMER_T1CFG_MODE_M | AUX_TIMER_T1CFG_RELOAD_M); - ui32Val |= ((ui32Config) & (AUX_TIMER_T1CFG_MODE_M | - AUX_TIMER_T1CFG_RELOAD_M)); - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; - - // If edge counter, set rising/falling edge and tick source. - if(ui32Config & AUX_TIMER_T1CFG_MODE) - { - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); - ui32Val &= ~(AUX_TIMER_T1CFG_TICK_SRC_POL_M | - AUX_TIMER_T1CFG_TICK_SRC_M); - - // Set edge polarity. - if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) - { - ui32Val |= AUX_TIMER_T1CFG_TICK_SRC_POL; - } - - // Set tick source. - ui32Val |= (ui32Config & AUX_TIMER_T1CFG_TICK_SRC_M); - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; - } - } -} - -//***************************************************************************** -// -// Start AUX timer -// -//***************************************************************************** -void -AUXTimerStart(uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT((ui32Timer == AUX_TIMER_0) || - (ui32Timer == AUX_TIMER_1) || - (ui32Timer == AUX_TIMER_BOTH)); - - if(ui32Timer & AUX_TIMER_0) - { - // Start timer 0. - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = AUX_TIMER_T0CTL_EN; - } - if(ui32Timer & AUX_TIMER_1) - { - // Start timer 1. - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = AUX_TIMER_T1CTL_EN; - } -} - -//***************************************************************************** -// -// Stop AUX timer -// -//***************************************************************************** -void -AUXTimerStop(uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT((ui32Timer == AUX_TIMER_0) || - (ui32Timer == AUX_TIMER_1) || - (ui32Timer == AUX_TIMER_BOTH)); - - if(ui32Timer & AUX_TIMER_0) - { - // Stop timer 0. - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; - } - if(ui32Timer & AUX_TIMER_1) - { - // Stop timer 1. - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; - } -} - -//***************************************************************************** -// -// Set AUX timer prescale value -// -//***************************************************************************** -void -AUXTimerPrescaleSet(uint32_t ui32Timer, uint32_t ui32PrescaleDiv) -{ - uint32_t ui32Val; - - // Check the arguments. - ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || - (ui32Timer == AUX_TIMER_BOTH)); - ASSERT(ui32PrescaleDiv <= AUX_TIMER_PRESCALE_DIV_32768); - - if(ui32Timer & AUX_TIMER_0) - { - // Set timer 0 prescale value. - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); - ui32Val &= ~AUX_TIMER_T0CFG_PRE_M; - ui32Val |= ui32PrescaleDiv << AUX_TIMER_T0CFG_PRE_S; - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; - } - if(ui32Timer & AUX_TIMER_1) - { - // Set timer 1 prescale value. - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); - ui32Val &= ~AUX_TIMER_T1CFG_PRE_M; - ui32Val |= ui32PrescaleDiv << AUX_TIMER_T1CFG_PRE_S; - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; - } -} - -//***************************************************************************** -// -// Get AUX timer prescale value -// -//***************************************************************************** -uint32_t -AUXTimerPrescaleGet(uint32_t ui32Timer) -{ - uint32_t ui32Val; - uint32_t ui32PrescaleDiv; - - // Check the arguments. - ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); - - ui32Val = (HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG)); - if(ui32Timer & AUX_TIMER_0) - { - // Get timer 0 prescale value. - ui32PrescaleDiv = - (ui32Val & AUX_TIMER_T0CFG_PRE_M) >> AUX_TIMER_T0CFG_PRE_S; - } - else - { - // Get timer 1 prescale value. - ui32PrescaleDiv = - (ui32Val & AUX_TIMER_T1CFG_PRE_M) >> AUX_TIMER_T1CFG_PRE_S; - } - - return(ui32PrescaleDiv); -} diff --git a/third_party/ti/devices/cc26x0/driverlib/aux_timer.h b/third_party/ti/devices/cc26x0/driverlib/aux_timer.h deleted file mode 100644 index 6c0105a5c..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aux_timer.h +++ /dev/null @@ -1,482 +0,0 @@ -/****************************************************************************** -* Filename: aux_timer.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Timer -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aux_group -//! @{ -//! \addtogroup auxtimer_api -//! @{ -// -//***************************************************************************** - -#ifndef __AUX_TIMER_H__ -#define __AUX_TIMER_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aux_timer.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AUXTimerConfigure NOROM_AUXTimerConfigure - #define AUXTimerStart NOROM_AUXTimerStart - #define AUXTimerStop NOROM_AUXTimerStop - #define AUXTimerPrescaleSet NOROM_AUXTimerPrescaleSet - #define AUXTimerPrescaleGet NOROM_AUXTimerPrescaleGet -#endif - -//***************************************************************************** -// -// Values that can be passed to AUXTimerConfigure(). -// -//***************************************************************************** -#define AUX_TIMER_CFG_ONE_SHOT (AUX_TIMER_T0CFG_RELOAD_MAN) // One-shot timer mode -#define AUX_TIMER_CFG_PERIODIC (AUX_TIMER_T0CFG_RELOAD_CONT) // Period timer mode -#define AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_MAN) | (AUX_TIMER_T0CFG_MODE_TICK)) // One-shot timer with edge count -#define AUX_TIMER_CFG_PERIODIC_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_CONT) | (AUX_TIMER_T0CFG_MODE_TICK)) // Periodic timer with edge count -#define AUX_TIMER_CFG_RISING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_RISE) // Count rising edges (used with edge count mode) -#define AUX_TIMER_CFG_FALLING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_FALL) // Count falling edges (used with edge count mode) - -#define AUX_TIMER_CFG_TICK_SRC_RTC_EVENT (AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV) // AON wake-up event -#define AUX_TIMER_CFG_TICK_SRC_CMP_A (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA) // Comparator A -#define AUX_TIMER_CFG_TICK_SRC_CMP_B (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB) // Comparator B -#define AUX_TIMER_CFG_TICK_SRC_TDCDONE (AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE) // TDC Done -#define AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT (AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV) // Timer 0 event -#define AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT (AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV) // Timer 1 event -#define AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE (AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE) // Semaphore release -#define AUX_TIMER_CFG_TICK_SRC_ADC_DONE (AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE) // ADC done -#define AUX_TIMER_CFG_TICK_SRC_RTC_4KHZ (AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ) -#define AUX_TIMER_CFG_TICK_SRC_OBSMUX0 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0) -#define AUX_TIMER_CFG_TICK_SRC_OBSMUX1 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1) -#define AUX_TIMER_CFG_TICK_SRC_AON_SW (AUX_TIMER_T0CFG_TICK_SRC_AON_SW) -#define AUX_TIMER_CFG_TICK_SRC_AON_PROG_WU (AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU) -#define AUX_TIMER_CFG_TICK_SRC_AIO0 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO0) // AIO_DAT[ 0] -#define AUX_TIMER_CFG_TICK_SRC_AIO1 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO1) // AIO_DAT[ 1] -#define AUX_TIMER_CFG_TICK_SRC_AIO2 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO2) // AIO_DAT[ 2] -#define AUX_TIMER_CFG_TICK_SRC_AIO3 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO3) // AIO_DAT[ 3] -#define AUX_TIMER_CFG_TICK_SRC_AIO4 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO4) // AIO_DAT[ 4] -#define AUX_TIMER_CFG_TICK_SRC_AIO5 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO5) // AIO_DAT[ 5] -#define AUX_TIMER_CFG_TICK_SRC_AIO6 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO6) // AIO_DAT[ 6] -#define AUX_TIMER_CFG_TICK_SRC_AIO7 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO7) // AIO_DAT[ 7] -#define AUX_TIMER_CFG_TICK_SRC_AIO8 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO8) // AIO_DAT[ 8] -#define AUX_TIMER_CFG_TICK_SRC_AIO9 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO9) // AIO_DAT[ 9] -#define AUX_TIMER_CFG_TICK_SRC_AIO10 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO10) // AIO_DAT[10] -#define AUX_TIMER_CFG_TICK_SRC_AIO11 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO11) // AIO_DAT[11] -#define AUX_TIMER_CFG_TICK_SRC_AIO12 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO12) // AIO_DAT[12] -#define AUX_TIMER_CFG_TICK_SRC_AIO13 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO13) // AIO_DAT[13] -#define AUX_TIMER_CFG_TICK_SRC_AIO14 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO14) // AIO_DAT[14] -#define AUX_TIMER_CFG_TICK_SRC_AIO15 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO15) // AIO_DAT[15] -#define AUX_TIMER_CFG_TICK_SRC_ACLK_REF (AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF) // ACLK_REF_i -#define AUX_TIMER_CFG_TICK_SRC_MCU_EVENT (AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT) // MCU event -#define AUX_TIMER_CFG_TICK_SRC_ADC_IRQ (AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ) // DMA done - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ui32Timer -// parameter. -// -//***************************************************************************** -#define AUX_TIMER_0 0x0000FFFF // AUX Timer 0 -#define AUX_TIMER_1 0x00FF0000 // AUX Timer 1 -#define AUX_TIMER_BOTH 0x00FFFFFF // AUX Timer Both 0 and 1 - -//***************************************************************************** -// -// Values that can be passed to AUXTimerPrescaleSet and returned from -// AUXTimerPrescaleGet. -// -//***************************************************************************** -#define AUX_TIMER_PRESCALE_DIV_1 0x00000000 // Prescale division ratio 1 -#define AUX_TIMER_PRESCALE_DIV_2 0x00000001 // Prescale division ratio 2 -#define AUX_TIMER_PRESCALE_DIV_4 0x00000002 // Prescale division ratio 4 -#define AUX_TIMER_PRESCALE_DIV_8 0x00000003 // Prescale division ratio 8 -#define AUX_TIMER_PRESCALE_DIV_16 0x00000004 // Prescale division ratio 16 -#define AUX_TIMER_PRESCALE_DIV_32 0x00000005 // Prescale division ratio 32 -#define AUX_TIMER_PRESCALE_DIV_64 0x00000006 // Prescale division ratio 64 -#define AUX_TIMER_PRESCALE_DIV_128 0x00000007 // Prescale division ratio 128 -#define AUX_TIMER_PRESCALE_DIV_256 0x00000008 // Prescale division ratio 256 -#define AUX_TIMER_PRESCALE_DIV_512 0x00000009 // Prescale division ratio 512 -#define AUX_TIMER_PRESCALE_DIV_1028 0x0000000A // Prescale div. ratio 1028 -#define AUX_TIMER_PRESCALE_DIV_2048 0x0000000B // Prescale div. ratio 2048 -#define AUX_TIMER_PRESCALE_DIV_4096 0x0000000C // Prescale div. ratio 4096 -#define AUX_TIMER_PRESCALE_DIV_8192 0x0000000D // Prescale div. ratio 8192 -#define AUX_TIMER_PRESCALE_DIV_16384 0x0000000E // Prescale div. ratio 16384 -#define AUX_TIMER_PRESCALE_DIV_32768 0x0000000F // Prescale div. ratio 32768 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Configure AUX timer. -//! -//! This call configures the AUX timer selected by the \c ui32Timer. -//! The timer module is disabled before being configured and is left in the -//! disabled state. -//! -//! The configuration is specified in \c ui32Config as one of the following -//! values: -//! - \ref AUX_TIMER_CFG_ONE_SHOT : One-shot timer. -//! - \ref AUX_TIMER_CFG_PERIODIC : Periodic timer. -//! - \ref AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT : One-shot edge counter. -//! - \ref AUX_TIMER_CFG_PERIODIC_EDGE_COUNT : Periodic edge counter. -//! -//! When configured as timer, the counter is incremented based on the AUX clock -//! after the prescaler. The prescale division ratio is set -//! using \ref AUXTimerPrescaleSet(). -//! -//! When configured as an edge counter the counter is incremented only on edges -//! of the selected event. -//! The polarity of the event is selected by: -//! - \ref AUX_TIMER_CFG_RISING_EDGE : rising edge trigger -//! - \ref AUX_TIMER_CFG_FALLING_EDGE : falling edge trigger -//! -//! The event source is selected as one of the following defines: -//! - \ref AUX_TIMER_CFG_TICK_SRC_RTC_EVENT -//! - \ref AUX_TIMER_CFG_TICK_SRC_CMP_A -//! - \ref AUX_TIMER_CFG_TICK_SRC_CMP_B -//! - \ref AUX_TIMER_CFG_TICK_SRC_TDCDONE -//! - \ref AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT -//! - \ref AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT -//! - \ref AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE -//! - \ref AUX_TIMER_CFG_TICK_SRC_ADC_DONE -//! - \ref AUX_TIMER_CFG_TICK_SRC_RTC_4KHZ -//! - \ref AUX_TIMER_CFG_TICK_SRC_OBSMUX0 -//! - \ref AUX_TIMER_CFG_TICK_SRC_OBSMUX1 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AON_SW -//! - \ref AUX_TIMER_CFG_TICK_SRC_AON_PROG_WU -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO0 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO1 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO2 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO3 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO4 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO5 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO6 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO7 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO8 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO9 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO10 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO11 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO12 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO13 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO14 -//! - \ref AUX_TIMER_CFG_TICK_SRC_AIO15 -//! - \ref AUX_TIMER_CFG_TICK_SRC_ACLK_REF -//! - \ref AUX_TIMER_CFG_TICK_SRC_MCU_EVENT -//! - \ref AUX_TIMER_CFG_TICK_SRC_ADC_IRQ -//! -//! The mode, event polarity and event source are configured by setting the -//! \c ui32Config parameter as the bitwise OR of the various settings. -//! Example: (\ref AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT | -//! \ref AUX_TIMER_CFG_RISING_EDGE | -//! \ref AUX_TIMER_CFG_TICK_SRC_RTC_EVENT). -//! -//! \note When used as an edge counter the prescaler should be set to -//! \ref AUX_TIMER_PRESCALE_DIV_1. -//! -//! \note A timer can not trigger itself thus timer 0 can \b not use -//! \ref AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT and timer 1 can \b not use -//! \ref AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT. -//! -//! \param ui32Timer is the timer to configure. -//! - \ref AUX_TIMER_0 -//! - \ref AUX_TIMER_1 -//! - \ref AUX_TIMER_BOTH -//! \param ui32Config is the timer configuration. -//! -//! \return None -//! -//! \sa \ref AUXTimerPrescaleSet() -// -//***************************************************************************** -extern void AUXTimerConfigure(uint32_t ui32Timer, uint32_t ui32Config); - -//***************************************************************************** -// -//! \brief Start AUX timer(s). -//! -//! This call starts the selected AUX timer(s). -//! -//! \note The counter will start counting up from zero. -//! -//! \param ui32Timer is the timer to start. -//! - \ref AUX_TIMER_0 -//! - \ref AUX_TIMER_1 -//! - \ref AUX_TIMER_BOTH -//! -//! \return None -//! -//! \sa \ref AUXTimerStop() -// -//***************************************************************************** -extern void AUXTimerStart(uint32_t ui32Timer); - -//***************************************************************************** -// -//! \brief Stop AUX timer(s). -//! -//! This call stops the selected AUX timer(s). -//! -//! \param ui32Timer is the timer to stop. -//! - \ref AUX_TIMER_0 -//! - \ref AUX_TIMER_1 -//! - \ref AUX_TIMER_BOTH -//! -//! \return None -//! -//! \sa \ref AUXTimerStart() -// -//***************************************************************************** -extern void AUXTimerStop(uint32_t ui32Timer); - -//***************************************************************************** -// -//! \brief Set AUX timer target value. -//! -//! The timer counts from zero to the target value. When target value is -//! reached an event is generated. -//! -//! \param ui32Timer is the timer to set the target value for. -//! - \ref AUX_TIMER_0 -//! - \ref AUX_TIMER_1 -//! \param ui32Target is the timer target value. -//! - For \ref AUX_TIMER_0 the target value must be an integer in the range 0..65535 (16 bit). -//! - For \ref AUX_TIMER_1 the target value must be an integer in the range 0..255 (8 bit). -//! -//! \return None -//! -//! \sa \ref AUXTimerTargetValGet() -// -//***************************************************************************** -__STATIC_INLINE void -AUXTimerTargetValSet(uint32_t ui32Timer, uint32_t ui32Target) -{ - uint32_t ui32Addr; - - // Check the arguments. - ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); - ASSERT(((ui32Timer & AUX_TIMER_0) && (ui32Target <= 65535)) || - ((ui32Timer & AUX_TIMER_1) && (ui32Target <= 255))); - - ui32Addr = (ui32Timer & AUX_TIMER_0) ? - (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : - (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET); - - HWREG(ui32Addr) = ui32Target; -} - -//***************************************************************************** -// -//! \brief Get AUX timer target value. -//! -//! The timer counts from zero to the target value. When target value is -//! reached an event is generated. This function returns the programmed target -//! value for the specified timer. -//! -//! \param ui32Timer is the timer to get the target value from. -//! - \ref AUX_TIMER_0 -//! - \ref AUX_TIMER_1 -//! -//! \return Returns target value for the specified timer -//! -//! \sa \ref AUXTimerTargetValSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXTimerTargetValGet(uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); - - return(HWREG((ui32Timer & AUX_TIMER_0) ? - (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : - (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET))); -} - -//***************************************************************************** -// -//! \brief Set AUX timer prescale value. -//! -//! When configured as timer, the counter is incremented based on the AUX clock -//! after the prescaler. -//! -//! \note Setting prescale value is \b not advised when the timer is running. -//! -//! \note When timer is used as an edge counter the prescaler should be -//! set to \ref AUX_TIMER_PRESCALE_DIV_1. -//! -//! \param ui32Timer is the timer to set the prescale on. -//! - \ref AUX_TIMER_0 -//! - \ref AUX_TIMER_1 -//! - \ref AUX_TIMER_BOTH -//! \param ui32PrescaleDiv is the prescaler division ratio. -//! - \ref AUX_TIMER_PRESCALE_DIV_1 : Prescale division ratio 1 -//! - \ref AUX_TIMER_PRESCALE_DIV_2 : Prescale division ratio 2 -//! - \ref AUX_TIMER_PRESCALE_DIV_4 : Prescale division ratio 4 -//! - \ref AUX_TIMER_PRESCALE_DIV_16 : Prescale division ratio 16 -//! - \ref AUX_TIMER_PRESCALE_DIV_32 : Prescale division ratio 32 -//! - \ref AUX_TIMER_PRESCALE_DIV_64 : Prescale division ratio 64 -//! - \ref AUX_TIMER_PRESCALE_DIV_128 : Prescale division ratio 128 -//! - \ref AUX_TIMER_PRESCALE_DIV_256 : Prescale division ratio 256 -//! - \ref AUX_TIMER_PRESCALE_DIV_1028 : Prescale division ratio 1028 -//! - \ref AUX_TIMER_PRESCALE_DIV_2048 : Prescale division ratio 2048 -//! - \ref AUX_TIMER_PRESCALE_DIV_4096 : Prescale division ratio 4096 -//! - \ref AUX_TIMER_PRESCALE_DIV_8192 : Prescale division ratio 8192 -//! - \ref AUX_TIMER_PRESCALE_DIV_16384 : Prescale division ratio 16384 -//! - \ref AUX_TIMER_PRESCALE_DIV_32768 : Prescale division ratio 32768 -//! -//! \return None -//! -//! \sa \ref AUXTimerPrescaleGet() -// -//***************************************************************************** -extern void AUXTimerPrescaleSet(uint32_t ui32Timer, uint32_t ui32PrescaleDiv); - -//***************************************************************************** -// -//! \brief Get AUX timer prescale value. -//! -//! When configured as timer, the counter is incremented based on the AUX clock -//! after the prescaler. This call returns the setting of the prescale divide -//! ratio for the specified timer. -//! -//! \param ui32Timer is the timer to get the prescale value from. -//! - \ref AUX_TIMER_0 -//! - \ref AUX_TIMER_1 -//! -//! \return Returns the prescaler division ratio as one of the following values: -//! - \ref AUX_TIMER_PRESCALE_DIV_1 : Prescale division ratio 1 -//! - \ref AUX_TIMER_PRESCALE_DIV_2 : Prescale division ratio 2 -//! - \ref AUX_TIMER_PRESCALE_DIV_4 : Prescale division ratio 4 -//! - \ref AUX_TIMER_PRESCALE_DIV_16 : Prescale division ratio 16 -//! - \ref AUX_TIMER_PRESCALE_DIV_32 : Prescale division ratio 32 -//! - \ref AUX_TIMER_PRESCALE_DIV_64 : Prescale division ratio 64 -//! - \ref AUX_TIMER_PRESCALE_DIV_128 : Prescale division ratio 128 -//! - \ref AUX_TIMER_PRESCALE_DIV_256 : Prescale division ratio 256 -//! - \ref AUX_TIMER_PRESCALE_DIV_1028 : Prescale division ratio 1028 -//! - \ref AUX_TIMER_PRESCALE_DIV_2048 : Prescale division ratio 2048 -//! - \ref AUX_TIMER_PRESCALE_DIV_4096 : Prescale division ratio 4096 -//! - \ref AUX_TIMER_PRESCALE_DIV_8192 : Prescale division ratio 8192 -//! - \ref AUX_TIMER_PRESCALE_DIV_16384 : Prescale division ratio 16384 -//! - \ref AUX_TIMER_PRESCALE_DIV_32768 : Prescale division ratio 32768 -//! -//! \sa \ref AUXTimerPrescaleSet() -// -//***************************************************************************** -extern uint32_t AUXTimerPrescaleGet(uint32_t ui32Timer); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AUXTimerConfigure - #undef AUXTimerConfigure - #define AUXTimerConfigure ROM_AUXTimerConfigure - #endif - #ifdef ROM_AUXTimerStart - #undef AUXTimerStart - #define AUXTimerStart ROM_AUXTimerStart - #endif - #ifdef ROM_AUXTimerStop - #undef AUXTimerStop - #define AUXTimerStop ROM_AUXTimerStop - #endif - #ifdef ROM_AUXTimerPrescaleSet - #undef AUXTimerPrescaleSet - #define AUXTimerPrescaleSet ROM_AUXTimerPrescaleSet - #endif - #ifdef ROM_AUXTimerPrescaleGet - #undef AUXTimerPrescaleGet - #define AUXTimerPrescaleGet ROM_AUXTimerPrescaleGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AUX_TIMER_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/aux_wuc.c b/third_party/ti/devices/cc26x0/driverlib/aux_wuc.c deleted file mode 100644 index f86e12202..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aux_wuc.c +++ /dev/null @@ -1,283 +0,0 @@ -/****************************************************************************** -* Filename: aux_wuc.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the AUX Wakeup Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aux_wuc.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AUXWUCClockEnable - #define AUXWUCClockEnable NOROM_AUXWUCClockEnable - #undef AUXWUCClockDisable - #define AUXWUCClockDisable NOROM_AUXWUCClockDisable - #undef AUXWUCClockStatus - #define AUXWUCClockStatus NOROM_AUXWUCClockStatus - #undef AUXWUCPowerCtrl - #define AUXWUCPowerCtrl NOROM_AUXWUCPowerCtrl -#endif - -//**************************************************************************** -// -//! Enable clocks for peripherals in the AUX domain -// -//**************************************************************************** -void -AUXWUCClockEnable(uint32_t ui32Clocks) -{ - // Check the arguments. - ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || - (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || - (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || - (ui32Clocks & AUX_WUC_ANAIF_CLOCK) || - (ui32Clocks & AUX_WUC_TIMER_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || - (ui32Clocks & AUX_WUC_SMPH_CLOCK) || - (ui32Clocks & AUX_WUC_TDC_CLOCK) || - (ui32Clocks & AUX_WUC_ADC_CLOCK) || - (ui32Clocks & AUX_WUC_REF_CLOCK)); - - // Enable some of the clocks in the clock register. - HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) |= (ui32Clocks & - AUX_WUC_MODCLK_MASK); - - // Check the rest. - if(ui32Clocks & AUX_WUC_ADC_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = - AUX_WUC_ADCCLKCTL_REQ; - } - if(ui32Clocks & AUX_WUC_TDC_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) = - AUX_WUC_TDCCLKCTL_REQ; - } - if(ui32Clocks & AUX_WUC_REF_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = - AUX_WUC_REFCLKCTL_REQ; - } -} - -//**************************************************************************** -// -//! Disable clocks for peripherals in the AUX domain -// -//**************************************************************************** -void -AUXWUCClockDisable(uint32_t ui32Clocks) -{ - // Check the arguments. - ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || - (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || - (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || - (ui32Clocks & AUX_WUC_ANAIF_CLOCK) || - (ui32Clocks & AUX_WUC_TIMER_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || - (ui32Clocks & AUX_WUC_SMPH_CLOCK) || - (ui32Clocks & AUX_WUC_TDC_CLOCK) || - (ui32Clocks & AUX_WUC_ADC_CLOCK) || - (ui32Clocks & AUX_WUC_REF_CLOCK)); - - // Disable some of the clocks in the clock register. - HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) &= ~(ui32Clocks & - AUX_WUC_MODCLK_MASK); - - // Check the rest. - if(ui32Clocks & AUX_WUC_ADC_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) &= - ~AUX_WUC_ADCCLKCTL_REQ; - } - if(ui32Clocks & AUX_WUC_TDC_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) &= - ~AUX_WUC_TDCCLKCTL_REQ; - } - if(ui32Clocks & AUX_WUC_REF_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) &= - ~AUX_WUC_REFCLKCTL_REQ; - } -} - -//**************************************************************************** -// -//! Get the status of a clock -// -//**************************************************************************** -uint32_t -AUXWUCClockStatus(uint32_t ui32Clocks) -{ - bool bClockStatus; - uint32_t ui32ClockRegister; - - // Check the arguments. - ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || - (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || - (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || - (ui32Clocks & AUX_WUC_ANAIF_CLOCK) || - (ui32Clocks & AUX_WUC_TIMER_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || - (ui32Clocks & AUX_WUC_SMPH_CLOCK) || - (ui32Clocks & AUX_WUC_TDC_CLOCK) || - (ui32Clocks & AUX_WUC_ADC_CLOCK) || - (ui32Clocks & AUX_WUC_REF_CLOCK)); - - bClockStatus = true; - - // Read the status registers. - ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0); - - // Check all requested clocks - if(ui32Clocks & AUX_WUC_ADI_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_AUX_ADI4 ? - true : false); - } - if(ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_AUX_DDI0_OSC ? - true : false); - } - if(ui32Clocks & AUX_WUC_TDCIF_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_TDC ? - true : false); - } - if(ui32Clocks & AUX_WUC_ANAIF_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_ANAIF ? - true : false); - } - if(ui32Clocks & AUX_WUC_TIMER_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_TIMER ? - true : false); - } - if(ui32Clocks & AUX_WUC_AIODIO0_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_AIODIO0 ? - true : false); - } - if(ui32Clocks & AUX_WUC_AIODIO1_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_AIODIO1 ? - true : false); - } - if(ui32Clocks & AUX_WUC_SMPH_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_SMPH ? - true : false); - } - if(ui32Clocks & AUX_WUC_ADC_CLOCK) - { - ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL); - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_ADCCLKCTL_ACK ? - true : false); - } - if(ui32Clocks & AUX_WUC_TDC_CLOCK) - { - ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL); - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_TDCCLKCTL_ACK ? - true : false); - } - if(ui32Clocks & AUX_WUC_REF_CLOCK) - { - ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL); - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_REFCLKCTL_ACK ? - true : false); - } - - // Return the clock status. - return bClockStatus ? AUX_WUC_CLOCK_READY : AUX_WUC_CLOCK_OFF; -} - -//**************************************************************************** -// -//! Control the power to the AUX domain -// -//**************************************************************************** -void -AUXWUCPowerCtrl(uint32_t ui32PowerMode) -{ - // Check the arguments. - ASSERT((ui32PowerMode == AUX_WUC_POWER_OFF) || - (ui32PowerMode == AUX_WUC_POWER_DOWN) || - (ui32PowerMode == AUX_WUC_POWER_ACTIVE)); - - // Power on/off. - if(ui32PowerMode == AUX_WUC_POWER_OFF) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = AUX_WUC_PWROFFREQ_REQ; - HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; - return; - } - else - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = 0x0; - } - - // Power down/active. - if(ui32PowerMode == AUX_WUC_POWER_DOWN) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = AUX_WUC_PWRDWNREQ_REQ; - HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; - } - else - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = 0x0; - } -} diff --git a/third_party/ti/devices/cc26x0/driverlib/aux_wuc.h b/third_party/ti/devices/cc26x0/driverlib/aux_wuc.h deleted file mode 100644 index 58ae1d152..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/aux_wuc.h +++ /dev/null @@ -1,347 +0,0 @@ -/****************************************************************************** -* Filename: aon_wuc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Wakeup Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//**************************************************************************** -// -//! \addtogroup aux_group -//! @{ -//! \addtogroup auxwuc_api -//! @{ -// -//**************************************************************************** - -#ifndef __AUX_WUC_H__ -#define __AUX_WUC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aux_wuc.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AUXWUCClockEnable NOROM_AUXWUCClockEnable - #define AUXWUCClockDisable NOROM_AUXWUCClockDisable - #define AUXWUCClockStatus NOROM_AUXWUCClockStatus - #define AUXWUCPowerCtrl NOROM_AUXWUCPowerCtrl -#endif - -//***************************************************************************** -// -// Defines for the AUX power control. -// -//***************************************************************************** -#define AUX_WUC_POWER_OFF 0x00000001 -#define AUX_WUC_POWER_DOWN 0x00000002 -#define AUX_WUC_POWER_ACTIVE 0x00000004 - -//***************************************************************************** -// -// Defines for the AUX peripherals clock control. -// -//***************************************************************************** -#define AUX_WUC_SMPH_CLOCK (AUX_WUC_MODCLKEN0_SMPH_EN) -#define AUX_WUC_AIODIO0_CLOCK (AUX_WUC_MODCLKEN0_AIODIO0_EN) -#define AUX_WUC_AIODIO1_CLOCK (AUX_WUC_MODCLKEN0_AIODIO1_EN) -#define AUX_WUC_TIMER_CLOCK (AUX_WUC_MODCLKEN0_TIMER_EN) -#define AUX_WUC_ANAIF_CLOCK (AUX_WUC_MODCLKEN0_ANAIF_EN) -#define AUX_WUC_TDCIF_CLOCK (AUX_WUC_MODCLKEN0_TDC_EN) -#define AUX_WUC_OSCCTRL_CLOCK (AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN) -#define AUX_WUC_ADI_CLOCK (AUX_WUC_MODCLKEN0_AUX_ADI4_EN) -#define AUX_WUC_MODCLK_MASK 0x000000FF - -#define AUX_WUC_TDC_CLOCK 0x00000100 -#define AUX_WUC_ADC_CLOCK 0x00000200 -#define AUX_WUC_REF_CLOCK 0x00000400 - -#define AUX_WUC_CLOCK_OFF 0x00000000 -#define AUX_WUC_CLOCK_UNSTABLE 0x00000001 -#define AUX_WUC_CLOCK_READY 0x00000011 - -#define AUX_WUC_CLOCK_HIFREQ 0x00000000 -#define AUX_WUC_CLOCK_LOFREQ 0x00000001 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//**************************************************************************** -// -//! \brief Enable clocks for peripherals in the AUX domain. -//! -//! Use this function to enable specific clocks in the AUX domain. -//! -//! \param ui32Clocks is a bitmap of clocks to enable. -//! Use a bitwise OR combination of the following values: -//! - \ref AUX_WUC_ADI_CLOCK -//! - \ref AUX_WUC_OSCCTRL_CLOCK -//! - \ref AUX_WUC_TDCIF_CLOCK -//! - \ref AUX_WUC_ANAIF_CLOCK -//! - \ref AUX_WUC_TIMER_CLOCK -//! - \ref AUX_WUC_AIODIO0_CLOCK -//! - \ref AUX_WUC_AIODIO1_CLOCK -//! - \ref AUX_WUC_SMPH_CLOCK -//! - \ref AUX_WUC_TDC_CLOCK -//! - \ref AUX_WUC_ADC_CLOCK -//! - \ref AUX_WUC_REF_CLOCK -//! -//! \return None -//! -//! \sa \ref AUXWUCClockDisable() -// -//**************************************************************************** -extern void AUXWUCClockEnable(uint32_t ui32Clocks); - -//**************************************************************************** -// -//! \brief Disable clocks for peripherals in the AUX domain. -//! -//! Use this function to enable specific clocks in the AUX domain. -//! -//! \param ui32Clocks a bitmap of clocks to disable. -//! Use a bitwise OR combination of the following values: -//! - \ref AUX_WUC_ADI_CLOCK -//! - \ref AUX_WUC_OSCCTRL_CLOCK -//! - \ref AUX_WUC_TDCIF_CLOCK -//! - \ref AUX_WUC_ANAIF_CLOCK -//! - \ref AUX_WUC_TIMER_CLOCK -//! - \ref AUX_WUC_AIODIO0_CLOCK -//! - \ref AUX_WUC_AIODIO1_CLOCK -//! - \ref AUX_WUC_SMPH_CLOCK -//! - \ref AUX_WUC_TDC_CLOCK -//! - \ref AUX_WUC_ADC_CLOCK -//! - \ref AUX_WUC_REF_CLOCK -//! -//! \return None -//! -//! \sa \ref AUXWUCClockEnable() -// -//**************************************************************************** -extern void AUXWUCClockDisable(uint32_t ui32Clocks); - -//**************************************************************************** -// -//! \brief Get the status of a clock. -//! -//! Use this function to poll the status of a specific clock in the AUX -//! domain. -//! -//! \param ui32Clocks is the clock for which to return status. -//! - \ref AUX_WUC_ADI_CLOCK -//! - \ref AUX_WUC_OSCCTRL_CLOCK -//! - \ref AUX_WUC_TDCIF_CLOCK -//! - \ref AUX_WUC_ANAIF_CLOCK -//! - \ref AUX_WUC_TIMER_CLOCK -//! - \ref AUX_WUC_AIODIO0_CLOCK -//! - \ref AUX_WUC_AIODIO1_CLOCK -//! - \ref AUX_WUC_SMPH_CLOCK -//! - \ref AUX_WUC_TDC_CLOCK -//! - \ref AUX_WUC_ADC_CLOCK -//! - \ref AUX_WUC_REF_CLOCK -//! -//! \return Returns the status of the clock as one of two states: -//! - \ref AUX_WUC_CLOCK_OFF -//! - \ref AUX_WUC_CLOCK_READY -// -//**************************************************************************** -extern uint32_t AUXWUCClockStatus(uint32_t ui32Clocks); - -//**************************************************************************** -// -//! \brief Request a high or low frequency clock source. -//! -//! Using this function it is possible to make a request to the System -//! Control to use a high or low frequency clock as clock source for the AUX -//! domain. -//! -//! \note A low frequency clock is always 32 kHz, while a high frequency clock -//! is really a large span of frequencies determined by the clock source (High -//! Frequency or Medium Frequency) and the setting for the clock divider for -//! the AUX domain in the System Control. -//! -//! \param ui32ClockFreq determines the clock source frequency. -//! - \ref AUX_WUC_CLOCK_LOFREQ : Request low frequency clock source for AUX domain. -//! - \ref AUX_WUC_CLOCK_HIFREQ : Request high frequency clock source for AUX domain. -//! -//! \return -// -//**************************************************************************** -__STATIC_INLINE void -AUXWUCClockFreqReq(uint32_t ui32ClockFreq) -{ - // Check the arguments. - ASSERT((ui32ClockFreq == AUX_WUC_CLOCK_HIFREQ) || - (ui32ClockFreq == AUX_WUC_CLOCK_LOFREQ)); - - // Set the request - HWREG(AUX_WUC_BASE + AUX_WUC_O_CLKLFREQ) = ui32ClockFreq; -} - -//**************************************************************************** -// -//! \brief Control the power to the AUX domain. -//! -//! Use this function to set the power mode of the entire AUX domain. -//! -//! \param ui32PowerMode control the desired power mode for the AUX domain. -//! The domain has three different power modes: -//! - \ref AUX_WUC_POWER_OFF -//! - \ref AUX_WUC_POWER_DOWN -//! - \ref AUX_WUC_POWER_ACTIVE -//! -//! \return None -// -//**************************************************************************** -extern void AUXWUCPowerCtrl(uint32_t ui32PowerMode); - -//***************************************************************************** -// -//! \brief Freeze the AUX IOs. -//! -//! To retain the values of the output IOs during a powerdown of the AUX domain -//! all IO latches in the AUX domain should be frozen in their current state. -//! This ensures that software can regain control of the IOs after a powerdown -//! without the IOs first falling back to the default values (i.e. input and -//! pull-up). -//! -//! \return None -//! -//! \sa AUXWUCFreezeDisable() -// -//***************************************************************************** -__STATIC_INLINE void -AUXWUCFreezeEnable(void) -{ - // Set the AUX WUC latches as static. - HWREG(AUX_WUC_BASE + AUX_WUC_O_AUXIOLATCH) = 0x0; -} - -//***************************************************************************** -// -//! \brief Unfreeze the AUX IOs. -//! -//! When restarting the AUX domain after it has entered powerdown mode, the -//! software can regain control of the IOs by setting the IO latches as -//! transparent. -//! -//! \note The IOs should not be unfrozen before software has restored -//! the functionality of the IO. -//! -//! \return None -//! -//! \sa AUXWUCFreezeEnable() -// -//***************************************************************************** -__STATIC_INLINE void -AUXWUCFreezeDisable(void) -{ - // Set the AUX WUC latches as transparent. - HWREG(AUX_WUC_BASE + AUX_WUC_O_AUXIOLATCH) = AUX_WUC_AUXIOLATCH_EN; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AUXWUCClockEnable - #undef AUXWUCClockEnable - #define AUXWUCClockEnable ROM_AUXWUCClockEnable - #endif - #ifdef ROM_AUXWUCClockDisable - #undef AUXWUCClockDisable - #define AUXWUCClockDisable ROM_AUXWUCClockDisable - #endif - #ifdef ROM_AUXWUCClockStatus - #undef AUXWUCClockStatus - #define AUXWUCClockStatus ROM_AUXWUCClockStatus - #endif - #ifdef ROM_AUXWUCPowerCtrl - #undef AUXWUCPowerCtrl - #define AUXWUCPowerCtrl ROM_AUXWUCPowerCtrl - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AUX_WUC_H__ - -//**************************************************************************** -// -//! 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zGl_dI0kJ2o8=gwL-51h8|B~p|iPq+}&6`_00!LR@`9N+vyQ8fuV4VYwmX?qcKk7G~ zfXY`E^8P!+`VCAaMSFRVonh$;f14g;sBbd4eM{HIGq$v?uiA(uZmGP~+O1p9#7sQD za61^k9juchXU++Un5xS?@>ezFk1sbms9pTIxzbNT-Mq(ArhkNZA2Ub~;? zKar}!(f%a7A-#5UYQca7K%}b{9DMc7gQ=RoK6dfE^2hv|gD2(xI5{!%SaO6)nc42u zyz%4O1&SJQgQ5@IUhK8AyU+5eB)*dpl?f03YmokS+|TenvjKn7;N>^hg>qA5p`7cJ)G%%Uufhs zRPzZFehy}Fol&B+q9R?;H=Q0Jzwm!hmY|~~PV&-b{+>EYdS_uUmEttQj_;2qvT z!rP4B;B!8n3e1+_T2AHkprLa3L2i^XHZJr;ttf>)k?V^QxEm_!{(7{Po^m$0odjM8dym5LQ%) zyz}0^8@QUU0L7Tw>*x(Ka9WLTV74V z%g3zlM+W(QCWz(zQ1z4p2VYv47_kW+VJ3B9L2> - // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); - TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); - TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); - } - else - { - // Consider adding a check for soft reset to allow debugging to skip - // this section!!! - // - // NB. This should be calling a ROM implementation of required trim and - // compensation - // e.g. TrimAfterColdReset() --> - // TrimAfterColdResetWakeupFromShutDown() --> - // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() - TrimAfterColdReset(); - TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); - TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); - - } - - // Set VIMS power domain control. - // PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered - HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; - - // Configure optimal wait time for flash FSM in cases where flash pump - // wakes up from sleep - HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) & - ~FLASH_FPAC1_PSLEEPTDIS_M) | - (0x139<> - AON_SYSCTL_RESETCTL_BOOT_DET_0_S ) == 1 ) - { - ui32AonSysResetctl = ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & - ~( AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M | - AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M )); - HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M; - HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) = ui32AonSysResetctl; - } - - // Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice() - // (There should typically be no wait time here, but need to be sure) - while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { - // Do nothing - wait for an eventual ongoing mode change to complete. - } -} - -//***************************************************************************** -// -//! \brief Trims to be applied when coming from POWER_DOWN (also called when -//! coming from SHUTDOWN and PIN_RESET). -//! -//! \return None -// -//***************************************************************************** -static void -TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ) -{ - // Currently no specific trim for Powerdown -} - -//***************************************************************************** -// -//! \brief Trims to be applied when coming from SHUTDOWN (also called when -//! coming from PIN_RESET). -//! -//! \param ui32Fcfg1Revision -//! -//! \return None -// -//***************************************************************************** -static void -TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision) -{ - uint32_t ccfg_ModeConfReg ; - uint32_t mp1rev ; - - // Force AUX on and enable clocks - // - // No need to save the current status of the power/clock registers. - // At this point both AUX and AON should have been reset to 0x0. - HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) = AON_WUC_AUXCTL_AUX_FORCE_ON; - - // Wait for power on on the AUX domain - while( ! ( HWREGBITW( AON_WUC_BASE + AON_WUC_O_PWRSTAT, AON_WUC_PWRSTAT_AUX_PD_ON_BITN ))); - - // Enable the clocks for AUX_DDI0_OSC and AUX_ADI4 - HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) = AUX_WUC_MODCLKEN0_AUX_DDI0_OSC | - AUX_WUC_MODCLKEN0_AUX_ADI4; - - // It's found to be optimal to override the FCFG1..DCDC_IPEAK setting as follows: - // if ( alternative DCDC setting in CCFG is enabled ) ADI3..IPEAK = CCFG..DCDC_IPEAK - // else ADI3..IPEAK = 2 - if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) { - // ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=ALT_DCDC_DITHER_EN) - // ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) - // Using a single 4-bit masked write since layout is equal for both source and destination - HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 | - ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S )); - - } else { - HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = 0x72; - } - - // - // Enable for JTAG to be powered down (will still be powered on if debugger is connected) - AONWUCJtagPowerOff(); - - // read the MODE_CONF register in CCFG - ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); - - // First part of trim done after cold reset and wakeup from shutdown: - // -Adjust the VDDR_TRIM_SLEEP value. - // -Configure DCDC. - SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg ); - - // Second part of trim done after cold reset and wakeup from shutdown: - // -Configure XOSC. -#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) - SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); -#else - NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); -#endif - - // Increased margin between digital supply voltage and VDD BOD during standby. - // VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7) - // VTRIM_BOD: unsigned 4 bits value to be decremented by 1 (min = 0) - // This applies to chips with mp1rev < 542 for cc13x0 and for mp1rev < 527 for cc26x0 - mp1rev = (( HWREG( FCFG1_BASE + FCFG1_O_TRIM_CAL_REVISION ) & FCFG1_TRIM_CAL_REVISION_MP1_M ) >> - FCFG1_TRIM_CAL_REVISION_MP1_S ) ; - if ( mp1rev < 527 ) { - uint32_t ldoTrimReg = HWREG( FCFG1_BASE + FCFG1_O_BAT_RC_LDO_TRIM ); - uint32_t vtrim_bod = (( ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M ) >> - FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S ); // bit[27:24] unsigned - uint32_t vtrim_udig = (( ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M ) >> - FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S ); // bit[19:16] signed but treated as unsigned - if ( vtrim_bod > 0 ) { - vtrim_bod -= 1; - } - if ( vtrim_udig != 7 ) { - if ( vtrim_udig == 6 ) { - vtrim_udig = 7; - } else { - vtrim_udig = (( vtrim_udig + 2 ) & 0xF ); - } - } - HWREGB( ADI2_BASE + ADI_2_REFSYS_O_SOCLDOCTL0 ) = - ( vtrim_udig << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S ) | - ( vtrim_bod << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S ) ; - } - - // Third part of trim done after cold reset and wakeup from shutdown: - // -Configure HPOSC. - // -Setup the LF clock. -#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) - SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); -#else - NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); -#endif - - // Allow AUX to power down - AUXWUCPowerCtrl( AUX_WUC_POWER_DOWN ); - - // Leaving on AUX and clock for AUX_DDI0_OSC on but turn off clock for AUX_ADI4 - HWREG( AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0 ) = AUX_WUC_MODCLKEN0_AUX_DDI0_OSC; - - // Disable EFUSE clock - HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1; -} - - -//***************************************************************************** -// -//! \brief Trims to be applied when coming from PIN_RESET. -//! -//! \return None -// -//***************************************************************************** -static void -TrimAfterColdReset( void ) -{ - // Currently no specific trim for Cold Reset -} diff --git a/third_party/ti/devices/cc26x0/driverlib/setup.h b/third_party/ti/devices/cc26x0/driverlib/setup.h deleted file mode 100644 index d032d71d7..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/setup.h +++ /dev/null @@ -1,128 +0,0 @@ -/****************************************************************************** -* Filename: setup.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 -* -* Description: Prototypes and defines for the setup API. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup setup_api -//! @{ -// -//***************************************************************************** - -#ifndef __SETUP_H__ -#define __SETUP_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -// Hardware headers -#include "../inc/hw_types.h" -// Driverlib headers -// - None needed - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SetupTrimDevice NOROM_SetupTrimDevice -#endif - -//***************************************************************************** -// -//! \brief Performs the necessary trim of the device which is not done in boot code. -//! -//! This function should only execute coming from ROM boot. The current -//! implementation does not take soft reset into account. However, it does no -//! damage to execute it again. It only consumes time. -//! -//! \return None -// -//***************************************************************************** -extern void SetupTrimDevice( void ); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SetupTrimDevice - #undef SetupTrimDevice - #define SetupTrimDevice ROM_SetupTrimDevice - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SETUP_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/setup_rom.c b/third_party/ti/devices/cc26x0/driverlib/setup_rom.c deleted file mode 100644 index 250379731..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/setup_rom.c +++ /dev/null @@ -1,908 +0,0 @@ -/****************************************************************************** -* Filename: setup_rom.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Setup file for CC13xx/CC26xx devices. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -// Hardware headers -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_adi.h" -#include "../inc/hw_adi_2_refsys.h" -#include "../inc/hw_adi_3_refsys.h" -#include "../inc/hw_adi_4_aux.h" -#include "../inc/hw_aon_batmon.h" -#include "../inc/hw_aon_sysctl.h" -#include "../inc/hw_ccfg.h" -#include "../inc/hw_ddi_0_osc.h" -#include "../inc/hw_fcfg1.h" -// Driverlib headers -#include "ddi.h" -#include "ioc.h" -#include "osc.h" -#include "sys_ctrl.h" -#include "setup_rom.h" -// ##### INCLUDE IN ROM BEGIN ##### -// We need intrinsic functions for IAR (if used in source code) -#ifdef __IAR_SYSTEMS_ICC__ -#include -#endif -// ##### INCLUDE IN ROM END ##### - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef SetupAfterColdResetWakeupFromShutDownCfg1 - #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 - #undef SetupAfterColdResetWakeupFromShutDownCfg2 - #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 - #undef SetupAfterColdResetWakeupFromShutDownCfg3 - #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 - #undef SetupGetTrimForAdcShModeEn - #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn - #undef SetupGetTrimForAdcShVbufEn - #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn - #undef SetupGetTrimForAmpcompCtrl - #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl - #undef SetupGetTrimForAmpcompTh1 - #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 - #undef SetupGetTrimForAmpcompTh2 - #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 - #undef SetupGetTrimForAnabypassValue1 - #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 - #undef SetupGetTrimForDblrLoopFilterResetVoltage - #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage - #undef SetupGetTrimForRadcExtCfg - #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg - #undef SetupGetTrimForRcOscLfIBiasTrim - #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim - #undef SetupGetTrimForRcOscLfRtuneCtuneTrim - #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim - #undef SetupGetTrimForXoscHfCtl - #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl - #undef SetupGetTrimForXoscHfFastStart - #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart - #undef SetupGetTrimForXoscHfIbiastherm - #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm - #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #undef SetupSetCacheModeAccordingToCcfgSetting - #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting - #undef SetupSetAonRtcSubSecInc - #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc -#endif - -//***************************************************************************** -// -// Function declarations -// -//***************************************************************************** - -//***************************************************************************** -// -// SetupAfterColdResetWakeupFromShutDownCfg1 -// -//***************************************************************************** -void -SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ) -{ - int32_t i32VddrSleepTrim; - int32_t i32VddrSleepDelta; - - { - i32VddrSleepTrim = SetupSignExtendVddrTrimValue(( - HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) & - FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M ) >> - FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S ) ; - } - - // Adjust the VDDR_TRIM_SLEEP value with value adjustable by customer (CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA) - // Read and sign extend VddrSleepDelta (in range -8 to +7) - i32VddrSleepDelta = - (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ))) - >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )); - // Calculate new VDDR sleep trim - i32VddrSleepTrim = ( i32VddrSleepTrim + i32VddrSleepDelta + 1 ); - if ( i32VddrSleepTrim > 21 ) i32VddrSleepTrim = 21; - if ( i32VddrSleepTrim < -10 ) i32VddrSleepTrim = -10; - // Write adjusted value using MASKED write (MASK8) - HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL1 * 2 )) = (( ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M << 8 ) | - (( i32VddrSleepTrim << ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S ) & ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M )); - - // 1. - // Do not allow DCDC to be enabled if in external regulator mode. - // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg). - // - // 2. - // Adjusted battery monitor low limit in internal regulator mode. - // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode. - if ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) { - ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M ); - } else { - HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0; - } - - // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE - // Note: Inverse polarity - HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL, AON_SYSCTL_PWRCTL_DCDC_EN_BITN ) = - ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 ); - - // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE - // Note: Inverse polarity - HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL, AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN ) = - ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 ); -} - -//***************************************************************************** -// -// SetupAfterColdResetWakeupFromShutDownCfg2 -// -//***************************************************************************** -void -SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ) -{ - uint32_t ui32Trim; - - // Following sequence is required for using XOSCHF, if not included - // devices crashes when trying to switch to XOSCHF. - // - // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1 - // register - ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ); - DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim); - - // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and - // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. - ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim(); - DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL, - (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M | - DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M), - DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S, - ui32Trim); - - // Trim XOSCHF IBIAS THERM. Get and set trim value for the - // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other - // register bit fields are set to 0. - ui32Trim = SetupGetTrimForXoscHfIbiastherm(); - DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2, - ui32Trim< writing to bits[7:4] - ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision ); - HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = - ( 0x20 | ( ui32Trim << 1 )); - - // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting - // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register - // Using MASK4 write + 1 => writing to bits[7:4] - ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision ); - HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = - ( 0x10 | ( ui32Trim )); - - // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields - // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting. - // Remaining register bit fields are set to their reset values of 0. - ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision); - DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim); - - // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting - // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL) - // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4)) - // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and - // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000) - ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision ); - HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) = - ( 0x60 | ( ui32Trim << 1 )); - - // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from - // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM - // This is DDI_0_OSC_O_ATESTCTL bit[7] - // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020)) - // Using MASK4 write + 1 => writing to bits[7:4] - ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision ); - HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) = - ( 0x80 | ( ui32Trim << 3 )); - - // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and - // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write - // This can be simplified since the registers are packed together in the same - // order both in FCFG1 and in the HW register. - // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18] - // Using MASK8 write + 4 => writing to bits[23:16] - ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision ); - HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) = - ( 0xFC00 | ( ui32Trim << 2 )); - - // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit - // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting. - // Remaining register bit fields are set to their reset values of 0. - ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision); - DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim); - - // Setting FORCE_KICKSTART_EN (ref. CC26_V1_BUG00261). Should also be done for PG2 - // (This is bit 22 in DDI_0_OSC_O_CTL0) - HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_FORCE_KICKSTART_EN; -} - -//***************************************************************************** -// -// SetupAfterColdResetWakeupFromShutDownCfg3 -// -//***************************************************************************** -void -SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) -{ - uint32_t fcfg1OscConf; - uint32_t ui32Trim; - uint32_t currentHfClock; - uint32_t ccfgExtLfClk; - - // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC - switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) { - case 2 : - // XOSC source is a 48 MHz crystal - // Do nothing (since this is the reset setting) - break; - case 1 : - // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC) - - fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ); - - if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) { - // This is a HPOSC chip, apply HPOSC settings - // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0) - HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN; - - // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit) - // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits) - // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits) - // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit) - // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits) - // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits) - // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) - - HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) & - ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) ); - HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) ); - HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) & - ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) ); - break; - } - // Not a HPOSC chip - fall through to default - default : - // XOSC source is a 24 MHz crystal (default) - // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0) - HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M; - break; - } - - // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO - // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used. - if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) { - HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS; - } - - // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0. - // This is typically already 0 except on Lizard where it is set in ROM-boot - HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN; - - // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1 - ui32Trim = SetupGetTrimForXoscHfFastStart(); - HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim ); - - // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION - switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) { - case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz) - OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF ); - SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency - break; - case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) - // Set SCLK_LF to use the same source as SCLK_HF - // Can be simplified a bit since possible return values for HF matches LF settings - currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF ); - OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock ); - while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) { - // Wait until switched - } - ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ); - SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S ); - IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S, - IOC_PORT_AON_CLK32K, - IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis - // Set XOSC_LF in bypass mode to allow external 32 kHz clock - HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS; - // Fall through to set XOSC_LF as SCLK_LF source - case 2 : // XOSC_LF -> SLCK_LF (32768 Hz) - OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF ); - break; - default : // (=3) RCOSC_LF - OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF ); - break; - } - - // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1 - HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) = - ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >> - FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) << - ADI_4_AUX_ADCREF1_VTRIM_S ) & - ADI_4_AUX_ADCREF1_VTRIM_M ); - - // Set ADI_4_AUX:ADC0.SMPL_CYCLE_EXP to it's default minimum value (=3) - // (Note: Using MASK8B requires that the bits to be modified must be within the same - // byte boundary which is the case for the ADI_4_AUX_ADC0_SMPL_CYCLE_EXP field) - HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_ADC0 * 2 )) = - ( ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M << 8 ) | ( 3 << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S ); - - // Sync with AON - SysCtrlAonSync(); -} - -//***************************************************************************** -// -// SetupGetTrimForAnabypassValue1 -// -//***************************************************************************** -uint32_t -SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ) -{ - uint32_t ui32Fcfg1Value ; - uint32_t ui32XoscHfRow ; - uint32_t ui32XoscHfCol ; - uint32_t ui32TrimValue ; - - // Use device specific trim values located in factory configuration - // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in - // the ANABYPASS_VALUE1 register. Value for the other bit fields - // are set to 0. - - ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP); - ui32XoscHfRow = (( ui32Fcfg1Value & - FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >> - FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S ); - ui32XoscHfCol = (( ui32Fcfg1Value & - FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >> - FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S ); - - if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) { - // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation - // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg - // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by - // a define and sign extension must therefore be hard coded. - // ( A small test program is created verifying the code lines below: - // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) - int32_t i32CustomerDeltaAdjust = - (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ))) - >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W )); - - while ( i32CustomerDeltaAdjust < 0 ) { - ui32XoscHfCol >>= 1; // COL 1 step down - if ( ui32XoscHfCol == 0 ) { // if COL below minimum - ui32XoscHfCol = 0xFFFF; // Set COL to maximum - ui32XoscHfRow >>= 1; // ROW 1 step down - if ( ui32XoscHfRow == 0 ) { // if ROW below minimum - ui32XoscHfRow = 1; // Set both ROW and COL - ui32XoscHfCol = 1; // to minimum - } - } - i32CustomerDeltaAdjust++; - } - while ( i32CustomerDeltaAdjust > 0 ) { - ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up - if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum - ui32XoscHfCol = 1; // Set COL to minimum - ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up - if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum - ui32XoscHfRow = 0xF; // Set both ROW and COL - ui32XoscHfCol = 0xFFFF; // to maximum - } - } - i32CustomerDeltaAdjust--; - } - } - - ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) | - ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) ); - - return (ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForRcOscLfRtuneCtuneTrim -// -//***************************************************************************** -uint32_t -SetupGetTrimForRcOscLfRtuneCtuneTrim( void ) -{ - uint32_t ui32TrimValue; - - // Use device specific trim values located in factory configuration - // area - ui32TrimValue = - ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & - FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>> - FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<< - DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S; - - ui32TrimValue |= - ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & - FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>> - FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<< - DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S; - - return(ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForXoscHfIbiastherm -// -//***************************************************************************** -uint32_t -SetupGetTrimForXoscHfIbiastherm( void ) -{ - uint32_t ui32TrimValue; - - // Use device specific trim value located in factory configuration - // area - ui32TrimValue = - (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) & - FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>> - FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S; - - return(ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForAmpcompTh2 -// -//***************************************************************************** -uint32_t -SetupGetTrimForAmpcompTh2( void ) -{ - uint32_t ui32TrimValue; - uint32_t ui32Fcfg1Value; - - // Use device specific trim value located in factory configuration - // area. All defined register bit fields have corresponding trim - // value in the factory configuration area - ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2); - ui32TrimValue = ((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>> - FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<< - DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S; - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>> - FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<< - DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>> - FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<< - DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>> - FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<< - DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S); - - return(ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForAmpcompTh1 -// -//***************************************************************************** -uint32_t -SetupGetTrimForAmpcompTh1( void ) -{ - uint32_t ui32TrimValue; - uint32_t ui32Fcfg1Value; - - // Use device specific trim values located in factory configuration - // area. All defined register bit fields have a corresponding trim - // value in the factory configuration area - ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1); - ui32TrimValue = (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>> - FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<< - DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>> - FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<< - DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>> - FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<< - DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>> - FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<< - DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S); - - return(ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForAmpcompCtrl -// -//***************************************************************************** -uint32_t -SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ) -{ - uint32_t ui32TrimValue ; - uint32_t ui32Fcfg1Value ; - uint32_t ibiasOffset ; - uint32_t ibiasInit ; - uint32_t modeConf1 ; - int32_t deltaAdjust ; - - // Use device specific trim values located in factory configuration - // area. Register bit fields without trim values in the factory - // configuration area will be set to the value of 0. - ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 ); - - ibiasOffset = ( ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >> - FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ; - ibiasInit = ( ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >> - FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ; - - if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { - // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG - modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ); - - // Both fields are signed 4-bit values. This is an assumption when doing the sign extension. - deltaAdjust = - (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ))) - >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W )); - deltaAdjust += (int32_t)ibiasOffset; - if ( deltaAdjust < 0 ) { - deltaAdjust = 0; - } - if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) { - deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ); - } - ibiasOffset = (uint32_t)deltaAdjust; - - deltaAdjust = - (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ))) - >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W )); - deltaAdjust += (int32_t)ibiasInit; - if ( deltaAdjust < 0 ) { - deltaAdjust = 0; - } - if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) { - deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ); - } - ibiasInit = (uint32_t)deltaAdjust; - } - ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) | - ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ; - - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>> - FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<< - DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>> - FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<< - DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>> - FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<< - DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S); - - if ( ui32Fcfg1Revision >= 0x00000022 ) { - ui32TrimValue |= ((( ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >> - FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) << - DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S ); - } - - return(ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForDblrLoopFilterResetVoltage -// -//***************************************************************************** -uint32_t -SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ) -{ - uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value - - if ( ui32Fcfg1Revision >= 0x00000020 ) { - dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) & - FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >> - FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S; - } - - return ( dblrLoopFilterResetVoltageValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForAdcShModeEn -// -//***************************************************************************** -uint32_t -SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ) -{ - uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting - - if ( ui32Fcfg1Revision >= 0x00000022 ) { - getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & - FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >> - FCFG1_OSC_CONF_ADC_SH_MODE_EN_S; - } - - return ( getTrimForAdcShModeEnValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForAdcShVbufEn -// -//***************************************************************************** -uint32_t -SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ) -{ - uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting - - if ( ui32Fcfg1Revision >= 0x00000022 ) { - getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & - FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >> - FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S; - } - - return ( getTrimForAdcShVbufEnValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForXoscHfCtl -// -//***************************************************************************** -uint32_t -SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ) -{ - uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting - uint32_t fcfg1Data; - - if ( ui32Fcfg1Revision >= 0x00000020 ) { - fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); - getTrimForXoschfCtlValue = - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >> - FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) << - DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S); - - getTrimForXoschfCtlValue |= - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >> - FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) << - DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S); - - getTrimForXoschfCtlValue |= - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >> - FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) << - DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S); - } - - return ( getTrimForXoschfCtlValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForXoscHfFastStart -// -//***************************************************************************** -uint32_t -SetupGetTrimForXoscHfFastStart( void ) -{ - uint32_t ui32XoscHfFastStartValue ; - - // Get value from FCFG1 - ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & - FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >> - FCFG1_OSC_CONF_XOSC_HF_FAST_START_S; - - return ( ui32XoscHfFastStartValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForRadcExtCfg -// -//***************************************************************************** -uint32_t -SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ) -{ - uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting - uint32_t fcfg1Data; - - if ( ui32Fcfg1Revision >= 0x00000020 ) { - fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); - getTrimForRadcExtCfgValue = - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >> - FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) << - DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S); - - getTrimForRadcExtCfgValue |= - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >> - FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) << - DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S); - - getTrimForRadcExtCfgValue |= - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >> - FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) << - DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S); - } - - return ( getTrimForRadcExtCfgValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForRcOscLfIBiasTrim -// -//***************************************************************************** -uint32_t -SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ) -{ - uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value - - if ( ui32Fcfg1Revision >= 0x00000022 ) { - trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & - FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >> - FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ; - } - - return ( trimForRcOscLfIBiasTrimValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio -// -//***************************************************************************** -uint32_t -SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ) -{ - uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields - - if ( ui32Fcfg1Revision >= 0x00000022 ) { - trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & - ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M | - FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >> - FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ; - } - - return ( trimForXoscLfRegulatorAndCmirrwrRatioValue ); -} - -//***************************************************************************** -// -// SetupSetCacheModeAccordingToCcfgSetting -// -//***************************************************************************** -void -SetupSetCacheModeAccordingToCcfgSetting( void ) -{ - // - Make sure to enable aggressive VIMS clock gating for power optimization - // Only for PG2 devices. - // - Enable cache prefetch enable as default setting - // (Slightly higher power consumption, but higher CPU performance) - // - IF ( CCFG_..._DIS_GPRAM == 1 ) - // then: Enable cache (set cache mode = 1), even if set by ROM boot code - // (This is done because it's not set by boot code when running inside - // a debugger supporting the Halt In Boot (HIB) functionality). - // else: Set MODE_GPRAM if not already set (see inline comments as well) - uint32_t vimsCtlMode0 ; - - while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { - // Do nothing - wait for an eventual ongoing mode change to complete. - // (There should typically be no wait time here, but need to be sure) - } - - // Note that Mode=0 is equal to MODE_GPRAM - vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M ); - - - if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) { - // Enable cache (and hence disable GPRAM) - HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); - } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) { - // GPRAM is enabled in CCFG but not selected - // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM - HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF ); - while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) { - // Do nothing - wait for an eventual mode change to complete (This goes fast). - } - HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; - } else { - // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set - HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; - } -} - -//***************************************************************************** -// -// SetupSetAonRtcSubSecInc -// -//***************************************************************************** -void -SetupSetAonRtcSubSecInc( uint32_t subSecInc ) -{ - // Loading a new RTCSUBSECINC value is done in 5 steps: - // 1. Write bit[15:0] of new SUBSECINC value to AUX_WUC_O_RTCSUBSECINC0 - // 2. Write bit[23:16] of new SUBSECINC value to AUX_WUC_O_RTCSUBSECINC1 - // 3. Set AUX_WUC_RTCSUBSECINCCTL_UPD_REQ - // 4. Wait for AUX_WUC_RTCSUBSECINCCTL_UPD_ACK - // 5. Clear AUX_WUC_RTCSUBSECINCCTL_UPD_REQ - HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_WUC_RTCSUBSECINC0_INC15_0_M ); - HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_WUC_RTCSUBSECINC1_INC23_16_M ); - - HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL ) = AUX_WUC_RTCSUBSECINCCTL_UPD_REQ; - while( ! ( HWREGBITW( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL, AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN ))); - HWREG( AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL ) = 0; -} diff --git a/third_party/ti/devices/cc26x0/driverlib/setup_rom.h b/third_party/ti/devices/cc26x0/driverlib/setup_rom.h deleted file mode 100644 index 2f62dedac..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/setup_rom.h +++ /dev/null @@ -1,427 +0,0 @@ -/****************************************************************************** -* Filename: setup_rom.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Prototypes and defines for the setup API. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup setup_api -//! @{ -// -//***************************************************************************** - -#ifndef __SETUP_ROM_H__ -#define __SETUP_ROM_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -// Hardware headers -#include "../inc/hw_types.h" -// Driverlib headers -// - None needed - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 - #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 - #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 - #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn - #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn - #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl - #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 - #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 - #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 - #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage - #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg - #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim - #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim - #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl - #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart - #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm - #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting - #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc -#endif - -//***************************************************************************** -// -//! \brief First part of configuration required when waking up from shutdown. -//! -//! \param ccfg_ModeConfReg -//! -//! \return None -// -//***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ); - -//***************************************************************************** -// -//! \brief Second part of configuration required when waking up from shutdown. -//! -//! \param ui32Fcfg1Revision -//! \param ccfg_ModeConfReg -//! -//! \return None -// -//***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ); - -//***************************************************************************** -// -//! \brief Third part of configuration required when waking up from shutdown. -//! -//! \param ccfg_ModeConfReg -//! -//! \return None -// -//***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ); - -//***************************************************************************** -// -//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting. -//! -//! \param ui32Fcfg1Revision -//! -//! \return Returns the trim value from FCFG1. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting. -//! -//! \param ui32Fcfg1Revision -//! -//! \return Returns the trim value from FCFG1. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG. -//! -//! \param ui32Fcfg1Revision -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG. -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompTh1( void ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG. -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompTh2( void ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG. -//! -//! \param ccfg_ModeConfReg -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); - -//***************************************************************************** -// -//! \brief Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting. -//! -//! \param ui32Fcfg1Revision -//! -//! \return Returns the trim value from FCFG1. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG. -//! -//! \param ui32Fcfg1Revision -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM. -//! -//! \param ui32Fcfg1Revision -//! -//! \return Returns the trim value from FCFG1. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the -//! RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG. -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG. -//! -//! \param ui32Fcfg1Revision -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START. -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfFastStart( void ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in -//! the ANABYPASS_VALUE2 register in OSC_DIG. -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); - -//***************************************************************************** -// -//! \brief Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet -//! spanning bits [5:0] in the returned value. -//! -//! \param ui32Fcfg1Revision -//! -//! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) -//! -//! \param ui32VddrTrimVal -//! -//! \return Returns Sign extended VDDR_TRIM setting. -// -//***************************************************************************** -__STATIC_INLINE int32_t -SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) -{ - // The VDDR trim value is 5 bits representing the range from -10 to +21 - // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) - int32_t i32SignedVddrVal = ui32VddrTrimVal; - if ( i32SignedVddrVal > 0x15 ) { - i32SignedVddrVal -= 0x20; - } - return ( i32SignedVddrVal ); -} - -//***************************************************************************** -// -//! \brief Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM) -//! -//! \return None -// -//***************************************************************************** -extern void SetupSetCacheModeAccordingToCcfgSetting( void ); - -//***************************************************************************** -// -//! \brief Doing the tricky stuff needed to enter new RTCSUBSECINC value -//! -//! \param subSecInc -//! -//! \return None -// -//***************************************************************************** -extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg1 - #undef SetupAfterColdResetWakeupFromShutDownCfg1 - #define SetupAfterColdResetWakeupFromShutDownCfg1 ROM_SetupAfterColdResetWakeupFromShutDownCfg1 - #endif - #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg2 - #undef SetupAfterColdResetWakeupFromShutDownCfg2 - #define SetupAfterColdResetWakeupFromShutDownCfg2 ROM_SetupAfterColdResetWakeupFromShutDownCfg2 - #endif - #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg3 - #undef SetupAfterColdResetWakeupFromShutDownCfg3 - #define SetupAfterColdResetWakeupFromShutDownCfg3 ROM_SetupAfterColdResetWakeupFromShutDownCfg3 - #endif - #ifdef ROM_SetupGetTrimForAdcShModeEn - #undef SetupGetTrimForAdcShModeEn - #define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn - #endif - #ifdef ROM_SetupGetTrimForAdcShVbufEn - #undef SetupGetTrimForAdcShVbufEn - #define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn - #endif - #ifdef ROM_SetupGetTrimForAmpcompCtrl - #undef SetupGetTrimForAmpcompCtrl - #define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl - #endif - #ifdef ROM_SetupGetTrimForAmpcompTh1 - #undef SetupGetTrimForAmpcompTh1 - #define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 - #endif - #ifdef ROM_SetupGetTrimForAmpcompTh2 - #undef SetupGetTrimForAmpcompTh2 - #define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 - #endif - #ifdef ROM_SetupGetTrimForAnabypassValue1 - #undef SetupGetTrimForAnabypassValue1 - #define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 - #endif - #ifdef ROM_SetupGetTrimForDblrLoopFilterResetVoltage - #undef SetupGetTrimForDblrLoopFilterResetVoltage - #define SetupGetTrimForDblrLoopFilterResetVoltage ROM_SetupGetTrimForDblrLoopFilterResetVoltage - #endif - #ifdef ROM_SetupGetTrimForRadcExtCfg - #undef SetupGetTrimForRadcExtCfg - #define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg - #endif - #ifdef ROM_SetupGetTrimForRcOscLfIBiasTrim - #undef SetupGetTrimForRcOscLfIBiasTrim - #define SetupGetTrimForRcOscLfIBiasTrim ROM_SetupGetTrimForRcOscLfIBiasTrim - #endif - #ifdef ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim - #undef SetupGetTrimForRcOscLfRtuneCtuneTrim - #define SetupGetTrimForRcOscLfRtuneCtuneTrim ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim - #endif - #ifdef ROM_SetupGetTrimForXoscHfCtl - #undef SetupGetTrimForXoscHfCtl - #define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl - #endif - #ifdef ROM_SetupGetTrimForXoscHfFastStart - #undef SetupGetTrimForXoscHfFastStart - #define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart - #endif - #ifdef ROM_SetupGetTrimForXoscHfIbiastherm - #undef SetupGetTrimForXoscHfIbiastherm - #define SetupGetTrimForXoscHfIbiastherm ROM_SetupGetTrimForXoscHfIbiastherm - #endif - #ifdef ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #endif - #ifdef ROM_SetupSetCacheModeAccordingToCcfgSetting - #undef SetupSetCacheModeAccordingToCcfgSetting - #define SetupSetCacheModeAccordingToCcfgSetting ROM_SetupSetCacheModeAccordingToCcfgSetting - #endif - #ifdef ROM_SetupSetAonRtcSubSecInc - #undef SetupSetAonRtcSubSecInc - #define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SETUP_ROM_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/smph.c b/third_party/ti/devices/cc26x0/driverlib/smph.c deleted file mode 100644 index e6f47e6bb..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/smph.c +++ /dev/null @@ -1,101 +0,0 @@ -/****************************************************************************** -* Filename: smph.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the MCU Semaphore. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "smph.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef SMPHAcquire - #define SMPHAcquire NOROM_SMPHAcquire -#endif - -//***************************************************************************** -// -// Acquire a semaphore -// -//***************************************************************************** -void -SMPHAcquire(uint32_t ui32Semaphore) -{ - // Check the arguments. - ASSERT((ui32Semaphore == SMPH_0) || - (ui32Semaphore == SMPH_1) || - (ui32Semaphore == SMPH_2) || - (ui32Semaphore == SMPH_3) || - (ui32Semaphore == SMPH_4) || - (ui32Semaphore == SMPH_5) || - (ui32Semaphore == SMPH_6) || - (ui32Semaphore == SMPH_7) || - (ui32Semaphore == SMPH_8) || - (ui32Semaphore == SMPH_9) || - (ui32Semaphore == SMPH_10) || - (ui32Semaphore == SMPH_11) || - (ui32Semaphore == SMPH_12) || - (ui32Semaphore == SMPH_13) || - (ui32Semaphore == SMPH_14) || - (ui32Semaphore == SMPH_15) || - (ui32Semaphore == SMPH_16) || - (ui32Semaphore == SMPH_17) || - (ui32Semaphore == SMPH_18) || - (ui32Semaphore == SMPH_19) || - (ui32Semaphore == SMPH_20) || - (ui32Semaphore == SMPH_21) || - (ui32Semaphore == SMPH_22) || - (ui32Semaphore == SMPH_23) || - (ui32Semaphore == SMPH_24) || - (ui32Semaphore == SMPH_25) || - (ui32Semaphore == SMPH_26) || - (ui32Semaphore == SMPH_27) || - (ui32Semaphore == SMPH_28) || - (ui32Semaphore == SMPH_29) || - (ui32Semaphore == SMPH_30) || - (ui32Semaphore == SMPH_31)); - - // Wait for semaphore to be release such that it can be claimed - // Semaphore register reads 1 when lock was acquired otherwise 0 - // (i.e. SMPH_CLAIMED). - while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == - SMPH_CLAIMED) - { - } -} diff --git a/third_party/ti/devices/cc26x0/driverlib/smph.h b/third_party/ti/devices/cc26x0/driverlib/smph.h deleted file mode 100644 index 0ed7387fa..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/smph.h +++ /dev/null @@ -1,312 +0,0 @@ -/****************************************************************************** -* Filename: smph.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the MCU Semaphore. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup mcusemaphore_api -//! @{ -// -//***************************************************************************** - -#ifndef __SMPH_H__ -#define __SMPH_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_smph.h" -#include "../inc/hw_memmap.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SMPHAcquire NOROM_SMPHAcquire -#endif - -//***************************************************************************** -// -// General constants and defines -// -//***************************************************************************** -#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed -#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed - -//***************************************************************************** -// -// Values that can be passed to SMPHAcquire, SMPHTryAcquire and SMPHRelease -// as the ui32Semaphore parameter. -// -//***************************************************************************** -#define SMPH_0 0 // MCU Semaphore 0 -#define SMPH_1 1 // MCU Semaphore 1 -#define SMPH_2 2 // MCU Semaphore 2 -#define SMPH_3 3 // MCU Semaphore 3 -#define SMPH_4 4 // MCU Semaphore 4 -#define SMPH_5 5 // MCU Semaphore 5 -#define SMPH_6 6 // MCU Semaphore 6 -#define SMPH_7 7 // MCU Semaphore 7 -#define SMPH_8 8 // MCU Semaphore 8 -#define SMPH_9 9 // MCU Semaphore 9 -#define SMPH_10 10 // MCU Semaphore 10 -#define SMPH_11 11 // MCU Semaphore 11 -#define SMPH_12 12 // MCU Semaphore 12 -#define SMPH_13 13 // MCU Semaphore 13 -#define SMPH_14 14 // MCU Semaphore 14 -#define SMPH_15 15 // MCU Semaphore 15 -#define SMPH_16 16 // MCU Semaphore 16 -#define SMPH_17 17 // MCU Semaphore 17 -#define SMPH_18 18 // MCU Semaphore 18 -#define SMPH_19 19 // MCU Semaphore 19 -#define SMPH_20 20 // MCU Semaphore 20 -#define SMPH_21 21 // MCU Semaphore 21 -#define SMPH_22 22 // MCU Semaphore 22 -#define SMPH_23 23 // MCU Semaphore 23 -#define SMPH_24 24 // MCU Semaphore 24 -#define SMPH_25 25 // MCU Semaphore 25 -#define SMPH_26 26 // MCU Semaphore 26 -#define SMPH_27 27 // MCU Semaphore 27 -#define SMPH_28 28 // MCU Semaphore 28 -#define SMPH_29 29 // MCU Semaphore 29 -#define SMPH_30 30 // MCU Semaphore 30 -#define SMPH_31 31 // MCU Semaphore 31 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Acquire a semaphore. -//! -//! This function acquires the given semaphore, blocking the call until -//! the semaphore is available. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref SMPH_0 -//! - \ref SMPH_1 -//! - ... -//! - \ref SMPH_31 -//! -//! \return None -// -//***************************************************************************** -extern void SMPHAcquire(uint32_t ui32Semaphore); - -//***************************************************************************** -// -//! \brief Try to Acquire a semaphore. -//! -//! This function tries to acquire the given semaphore, if the semaphore -//! could not be claimed the function returns false. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref SMPH_0 -//! - \ref SMPH_1 -//! - ... -//! - \ref SMPH_31 -//! -//! \return Returns if a semaphore was acquired -//! - \c true : Semaphore acquired. -//! - \c false : Semaphore \b not acquired. -// -//***************************************************************************** -__STATIC_INLINE bool -SMPHTryAcquire(uint32_t ui32Semaphore) -{ - uint32_t ui32SemaReg; - - // Check the arguments. - ASSERT((ui32Semaphore == SMPH_0) || - (ui32Semaphore == SMPH_1) || - (ui32Semaphore == SMPH_2) || - (ui32Semaphore == SMPH_3) || - (ui32Semaphore == SMPH_4) || - (ui32Semaphore == SMPH_5) || - (ui32Semaphore == SMPH_6) || - (ui32Semaphore == SMPH_7) || - (ui32Semaphore == SMPH_8) || - (ui32Semaphore == SMPH_9) || - (ui32Semaphore == SMPH_10) || - (ui32Semaphore == SMPH_11) || - (ui32Semaphore == SMPH_12) || - (ui32Semaphore == SMPH_13) || - (ui32Semaphore == SMPH_14) || - (ui32Semaphore == SMPH_15) || - (ui32Semaphore == SMPH_16) || - (ui32Semaphore == SMPH_17) || - (ui32Semaphore == SMPH_18) || - (ui32Semaphore == SMPH_19) || - (ui32Semaphore == SMPH_20) || - (ui32Semaphore == SMPH_21) || - (ui32Semaphore == SMPH_22) || - (ui32Semaphore == SMPH_23) || - (ui32Semaphore == SMPH_24) || - (ui32Semaphore == SMPH_25) || - (ui32Semaphore == SMPH_26) || - (ui32Semaphore == SMPH_27) || - (ui32Semaphore == SMPH_28) || - (ui32Semaphore == SMPH_29) || - (ui32Semaphore == SMPH_30) || - (ui32Semaphore == SMPH_31)); - - // Semaphore register reads 1 if lock was acquired - // (i.e. SMPH_FREE). - ui32SemaReg = HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore); - - return (ui32SemaReg == SMPH_FREE); -} - -//***************************************************************************** -// -//! \brief Release a semaphore. -//! -//! This function releases the given semaphore. -//! -//! \note It is up to the application to provide the convention for clearing -//! semaphore. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref SMPH_0 -//! - \ref SMPH_1 -//! - ... -//! - \ref SMPH_31 -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SMPHRelease(uint32_t ui32Semaphore) -{ - // Check the arguments. - ASSERT((ui32Semaphore == SMPH_0) || - (ui32Semaphore == SMPH_1) || - (ui32Semaphore == SMPH_2) || - (ui32Semaphore == SMPH_3) || - (ui32Semaphore == SMPH_4) || - (ui32Semaphore == SMPH_5) || - (ui32Semaphore == SMPH_6) || - (ui32Semaphore == SMPH_7) || - (ui32Semaphore == SMPH_8) || - (ui32Semaphore == SMPH_9) || - (ui32Semaphore == SMPH_10) || - (ui32Semaphore == SMPH_11) || - (ui32Semaphore == SMPH_12) || - (ui32Semaphore == SMPH_13) || - (ui32Semaphore == SMPH_14) || - (ui32Semaphore == SMPH_15) || - (ui32Semaphore == SMPH_16) || - (ui32Semaphore == SMPH_17) || - (ui32Semaphore == SMPH_18) || - (ui32Semaphore == SMPH_19) || - (ui32Semaphore == SMPH_20) || - (ui32Semaphore == SMPH_21) || - (ui32Semaphore == SMPH_22) || - (ui32Semaphore == SMPH_23) || - (ui32Semaphore == SMPH_24) || - (ui32Semaphore == SMPH_25) || - (ui32Semaphore == SMPH_26) || - (ui32Semaphore == SMPH_27) || - (ui32Semaphore == SMPH_28) || - (ui32Semaphore == SMPH_29) || - (ui32Semaphore == SMPH_30) || - (ui32Semaphore == SMPH_31)); - - // No check before release, it is up to the application to provide the - // conventions for who and when a semaphore can be released. - HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) = SMPH_FREE; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SMPHAcquire - #undef SMPHAcquire - #define SMPHAcquire ROM_SMPHAcquire - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SMPH_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/smph_doc.h b/third_party/ti/devices/cc26x0/driverlib/smph_doc.h deleted file mode 100644 index 3c6f4b3e4..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/smph_doc.h +++ /dev/null @@ -1,57 +0,0 @@ -/****************************************************************************** -* Filename: smph_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup mcusemaphore_api -//! @{ -//! \section sec_mcusemaphore Introduction -//! -//! The MCU Semaphore offers 32 semaphores that each can be claimed and released in an atomic operation. -//! One and only one semaphore can be handled during a transaction. -//! -//! Claiming a semaphore causes subsequent claims/reads to return '0' (i.e. "not available"). -//! How the semaphores are used and respected is decided by software. -//! -//! \section sec_mcusemaphore_api API -//! -//! The API functions can be grouped like this: -//! -//! Semaphore acquire: -//! - \ref SMPHAcquire() -//! - \ref SMPHTryAcquire() -//! -//! Semaphore release: -//! - \ref SMPHRelease() -//! -//! @} diff --git a/third_party/ti/devices/cc26x0/driverlib/ssi.c b/third_party/ti/devices/cc26x0/driverlib/ssi.c deleted file mode 100644 index eb66b6b66..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/ssi.c +++ /dev/null @@ -1,253 +0,0 @@ -/****************************************************************************** -* Filename: ssi.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for Synchronous Serial Interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "ssi.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef SSIConfigSetExpClk - #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk - #undef SSIDataPut - #define SSIDataPut NOROM_SSIDataPut - #undef SSIDataPutNonBlocking - #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking - #undef SSIDataGet - #define SSIDataGet NOROM_SSIDataGet - #undef SSIDataGetNonBlocking - #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking - #undef SSIIntRegister - #define SSIIntRegister NOROM_SSIIntRegister - #undef SSIIntUnregister - #define SSIIntUnregister NOROM_SSIIntUnregister -#endif - -//***************************************************************************** -// -// Configures the synchronous serial port -// -//***************************************************************************** -void -SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, - uint32_t ui32Protocol, uint32_t ui32Mode, - uint32_t ui32BitRate, uint32_t ui32DataWidth) -{ - uint32_t ui32MaxBitRate; - uint32_t ui32RegVal; - uint32_t ui32PreDiv; - uint32_t ui32SCR; - uint32_t ui32SPH_SPO; - - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || - (ui32Protocol == SSI_FRF_MOTO_MODE_1) || - (ui32Protocol == SSI_FRF_MOTO_MODE_2) || - (ui32Protocol == SSI_FRF_MOTO_MODE_3) || - (ui32Protocol == SSI_FRF_TI) || - (ui32Protocol == SSI_FRF_NMW)); - ASSERT((ui32Mode == SSI_MODE_MASTER) || - (ui32Mode == SSI_MODE_SLAVE) || - (ui32Mode == SSI_MODE_SLAVE_OD)); - ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || - ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); - ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); - ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); - - // Set the mode. - ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; - ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; - HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; - - // Set the clock predivider. - ui32MaxBitRate = ui32SSIClk / ui32BitRate; - ui32PreDiv = 0; - do - { - ui32PreDiv += 2; - ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; - } - while(ui32SCR > 255); - HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; - - // Set protocol and clock rate. - ui32SPH_SPO = (ui32Protocol & 3) << 6; - ui32Protocol &= SSI_CR0_FRF_M; - ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); - HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; -} - -//***************************************************************************** -// -// Puts a data element into the SSI transmit FIFO -// -//***************************************************************************** -int32_t -SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & - SSI_CR0_DSS_M))) == 0); - - // Check for space to write. - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) - { - HWREG(ui32Base + SSI_O_DR) = ui32Data; - return(1); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -// Puts a data element into the SSI transmit FIFO -// -//***************************************************************************** -void -SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & - SSI_CR0_DSS_M))) == 0); - - // Wait until there is space. - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) - { - } - - // Write the data to the SSI. - HWREG(ui32Base + SSI_O_DR) = ui32Data; -} - -//***************************************************************************** -// -// Gets a data element from the SSI receive FIFO -// -//***************************************************************************** -void -SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Wait until there is data to be read. - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) - { - } - - // Read data from SSI. - *pui32Data = HWREG(ui32Base + SSI_O_DR); -} - -//***************************************************************************** -// -// Gets a data element from the SSI receive FIFO -// -//***************************************************************************** -int32_t -SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Check for data to read. - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) - { - *pui32Data = HWREG(ui32Base + SSI_O_DR); - return(1); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -// Registers an interrupt handler for the synchronous serial port -// -//***************************************************************************** -void -SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Determine the interrupt number based on the SSI port. - ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; - - // Register the interrupt handler. - IntRegister(ui32Int, pfnHandler); - - // Enable the synchronous serial port interrupt. - IntEnable(ui32Int); -} - -//***************************************************************************** -// -// Unregisters an interrupt handler for the synchronous serial port -// -//***************************************************************************** -void -SSIIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Determine the interrupt number based on the SSI port. - ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; - - // Disable the interrupt. - IntDisable(ui32Int); - - // Unregister the interrupt handler. - IntUnregister(ui32Int); -} diff --git a/third_party/ti/devices/cc26x0/driverlib/ssi.h b/third_party/ti/devices/cc26x0/driverlib/ssi.h deleted file mode 100644 index 21eacf8a6..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/ssi.h +++ /dev/null @@ -1,700 +0,0 @@ -/****************************************************************************** -* Filename: ssi.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and macros for the SSI. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup ssi_api -//! @{ -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_ints.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_types.h" -#include "../inc/hw_ssi.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk - #define SSIDataPut NOROM_SSIDataPut - #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking - #define SSIDataGet NOROM_SSIDataGet - #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking - #define SSIIntRegister NOROM_SSIIntRegister - #define SSIIntUnregister NOROM_SSIIntUnregister -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ui32IntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half full or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or more -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that are returned from SSIStatus -// -//***************************************************************************** -#define SSI_RX_FULL 0x00000008 // Receive FIFO full -#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty -#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full -#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty -#define SSI_STATUS_MASK 0x0000000F - -//***************************************************************************** -// -// Values that can be passed to SSIConfigSetExpClk. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). -// -//***************************************************************************** -#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit -#define SSI_DMA_RX 0x00000001 // Enable DMA for receive - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Checks an SSI base address. -//! -//! This function determines if an SSI module base address is valid. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -SSIBaseValid(uint32_t ui32Base) -{ - return(ui32Base == SSI0_BASE || ui32Base == SSI1_BASE); -} -#endif - -//***************************************************************************** -// -//! \brief Configures the synchronous serial port. -//! -//! This function configures the synchronous serial port. It sets -//! the SSI protocol, mode of operation, bit rate, and data width. -//! -//! The \c ui32Protocol parameter defines the data frame format. The Motorola -//! frame formats imply the following polarity and phase configurations: -//! -//! 

    -//! Polarity Phase       Mode
-//!   0       0   SSI_FRF_MOTO_MODE_0
-//!   0       1   SSI_FRF_MOTO_MODE_1
-//!   1       0   SSI_FRF_MOTO_MODE_2
-//!   1       1   SSI_FRF_MOTO_MODE_3
-//!
    -//! -//! The \c ui32Mode parameter defines the operating mode of the SSI module. -//! The SSI module can operate as a master or slave; if a slave, the SSI can be -//! configured to disable output on its serial output line. -//! -//! The \c ui32BitRate parameter defines the bit rate for the SSI. This bit -//! rate must satisfy the following clock ratio criteria: -//! - Master mode : FSSI >= 2 * bit rate -//! - Slave mode : FSSI >= 12 * bit rate -//! -//! where FSSI is the frequency of the clock supplied to the SSI module. -//! -//! The \c ui32DataWidth parameter defines the width of the data transfers, and -//! can be a value between 4 and 16, inclusive. -//! -//! \note The peripheral clock is not necessarily the same as the processor clock. -//! The frequency of the peripheral clock is set by the system control. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32SSIClk is the rate of the clock supplied to the SSI module. -//! \param ui32Protocol specifies the data transfer protocol. -//! The parameter can be one of the following values: -//! - \ref SSI_FRF_MOTO_MODE_0 -//! - \ref SSI_FRF_MOTO_MODE_1 -//! - \ref SSI_FRF_MOTO_MODE_2 -//! - \ref SSI_FRF_MOTO_MODE_3 -//! - \ref SSI_FRF_TI -//! - \ref SSI_FRF_NMW. -//! \param ui32Mode specifies the mode of operation. -//! The parameter can be one of the following values: -//! - \ref SSI_MODE_MASTER -//! - \ref SSI_MODE_SLAVE -//! - \ref SSI_MODE_SLAVE_OD -//! \param ui32BitRate specifies the clock rate. -//! \param ui32DataWidth specifies number of bits transferred per frame. -//! Must be a value between 4 and 16, both included. -//! -//! \return None -// -//***************************************************************************** -extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, - uint32_t ui32Protocol, uint32_t ui32Mode, - uint32_t ui32BitRate, uint32_t ui32DataWidth); - -//***************************************************************************** -// -//! \brief Enables the synchronous serial port. -//! -//! This function enables operation of the synchronous serial port. The -//! synchronous serial port must be configured before it is enabled. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Read-modify-write the enable bit. - HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; -} - -//***************************************************************************** -// -//! \brief Disables the synchronous serial port. -//! -//! This function disables operation of the synchronous serial port. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIDisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Read-modify-write the enable bit. - HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); -} - -//***************************************************************************** -// -//! \brief Puts a data element into the SSI transmit FIFO. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module. -//! -//! \note The upper 32 - N bits of the \c ui32Data are discarded by the -//! hardware, where N is the data width as configured by \ref SSIConfigSetExpClk(). -//! For example, if the interface is configured for 8-bit data width, the upper -//! 24 bits of \c ui32Data are discarded. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! \return None -// -//***************************************************************************** -extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); - -//***************************************************************************** -// -//! \brief Puts a data element into the SSI transmit FIFO. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module. If there is no space in the FIFO, then this function -//! returns a zero. -//! -//! \note The upper 32 - N bits of the \c ui32Data are discarded by the hardware, -//! where N is the data width as configured by \ref SSIConfigSetExpClk(). For -//! example, if the interface is configured for 8-bit data width, the upper 24 -//! bits of \c ui32Data are discarded. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! \return Returns the number of elements written to the SSI transmit FIFO. -// -//***************************************************************************** -extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); - -//***************************************************************************** -// -//! \brief Gets a data element from the SSI receive FIFO. -//! -//! This function gets received data from the receive FIFO of the specified -//! SSI module and places that data into the location specified by the -//! \c pui32Data parameter. -//! -//! \note Only the lower N bits of the value written to \c pui32Data contain -//! valid data, where N is the data width as configured by -//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for -//! 8-bit data width, only the lower 8 bits of the value written to -//! \c pui32Data contain valid data. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pui32Data is a pointer to a storage location for data that was -//! received over the SSI interface. -//! -//! \return None -// -//***************************************************************************** -extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); - -//***************************************************************************** -// -//! \brief Gets a data element from the SSI receive FIFO. -//! -//! This function gets received data from the receive FIFO of the specified SSI -//! module and places that data into the location specified by the \c ui32Data -//! parameter. If there is no data in the FIFO, then this function returns a -//! zero. -//! -//! \note Only the lower N bits of the value written to \c pui32Data contain -//! valid data, where N is the data width as configured by -//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for -//! 8-bit data width, only the lower 8 bits of the value written to \c pui32Data -//! contain valid data. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pui32Data is a pointer to a storage location for data that was -//! received over the SSI interface. -//! -//! \return Returns the number of elements read from the SSI receive FIFO. -// -//***************************************************************************** -extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data); - -//***************************************************************************** -// -//! \brief Determines whether the SSI transmitter is busy or not. -//! -//! Allows the caller to determine whether all transmitted bytes have cleared -//! the transmitter hardware. If \c false is returned, then the transmit FIFO -//! is empty and all bits of the last transmitted word have left the hardware -//! shift register. -//! -//! \param ui32Base is the base address of the SSI port. -//! -//! \return Returns status of the SSI transmit buffer. -//! - \c true : SSI is transmitting. -//! - \c false : SSI transmissions are complete. -// -//***************************************************************************** -__STATIC_INLINE bool -SSIBusy(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Determine if the SSI is busy. - return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false); -} - -//***************************************************************************** -// -//! \brief Get the status of the SSI data buffers. -//! -//! This function is used to poll the status of the internal FIFOs in the SSI -//! module. The status of both TX and RX FIFO is returned. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! \return Returns the current status of the internal SSI data buffers. -//! The status is a bitwise OR'ed combination of: -//! - \ref SSI_RX_FULL : Receive FIFO full. -//! - \ref SSI_RX_NOT_EMPTY : Receive FIFO not empty. -//! - \ref SSI_TX_NOT_FULL : Transmit FIFO not full. -//! - \ref SSI_TX_EMPTY : Transmit FIFO empty. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -SSIStatus(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Return the status - return (HWREG(ui32Base + SSI_O_SR) & SSI_STATUS_MASK); -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific SSI interrupts must be enabled via \ref SSIIntEnable(). If necessary, -//! it is the interrupt handler's responsibility to clear the interrupt source -//! via \ref SSIIntClear(). -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pfnHandler is a pointer to the function to be called when the -//! synchronous serial port interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. -//! -//! This function will clear the handler to be called when a SSI -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void SSIIntUnregister(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Enables individual SSI interrupt sources. -//! -//! Enables the indicated SSI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! - \ref SSI_TXFF -//! - \ref SSI_RXFF -//! - \ref SSI_RXTO -//! - \ref SSI_RXOR -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Enable the specified interrupts. - HWREG(ui32Base + SSI_O_IMSC) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Disables individual SSI interrupt sources. -//! -//! Disables the indicated SSI interrupt sources. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! - \ref SSI_TXFF -//! - \ref SSI_RXFF -//! - \ref SSI_RXTO -//! - \ref SSI_RXOR -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Disable the specified interrupts. - HWREG(ui32Base + SSI_O_IMSC) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! \brief Clears SSI interrupt sources. -//! -//! The specified SSI interrupt sources are cleared so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupts from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! The parameter can consist of either or both of: -//! - \ref SSI_RXTO : Timeout interrupt. -//! - \ref SSI_RXOR : Overrun interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Clear the requested interrupt sources. - HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status. -//! -//! This function returns the interrupt status for the SSI module. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param bMasked selects either raw or masked interrupt. -//! \c false : Raw interrupt status is required. -//! \c true : Masked interrupt status is required. -//! -//! \return Returns the current interrupt status as an OR'ed combination of: -//! - \ref SSI_TXFF -//! - \ref SSI_RXFF -//! - \ref SSI_RXTO -//! - \ref SSI_RXOR -// -//***************************************************************************** -__STATIC_INLINE uint32_t -SSIIntStatus(uint32_t ui32Base, bool bMasked) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Return either the interrupt status or the raw interrupt status as - // requested. - if(bMasked) - { - return(HWREG(ui32Base + SSI_O_MIS)); - } - else - { - return(HWREG(ui32Base + SSI_O_RIS)); - } -} - -//***************************************************************************** -// -//! \brief Enable SSI DMA operation. -//! -//! The specified SSI DMA features are enabled. The SSI can be -//! configured to use DMA for transmit and/or receive data transfers. -//! -//! \note The uDMA controller must also be set up before DMA can be used -//! with the SSI. -//! -//! \param ui32Base is the base address of the SSI port. -//! \param ui32DMAFlags is a bit mask of the DMA features to enable. -//! The parameter is the bitwise OR of any of the following values: -//! - \ref SSI_DMA_RX : Enable DMA for receive. -//! - \ref SSI_DMA_TX : Enable DMA for transmit. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Set the requested bits in the SSI DMA control register. - HWREG(ui32Base + SSI_O_DMACR) |= ui32DMAFlags; -} - -//***************************************************************************** -// -//! \brief Disable SSI DMA operation. -//! -//! This function is used to disable SSI DMA features that were enabled -//! by \ref SSIDMAEnable(). The specified SSI DMA features are disabled. -//! -//! \param ui32Base is the base address of the SSI port. -//! \param ui32DMAFlags is a bit mask of the DMA features to disable. -//! The parameter is the bitwise OR of any of the following values: -//! - \ref SSI_DMA_RX : Disable DMA for receive. -//! - \ref SSI_DMA_TX : Disable DMA for transmit. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Clear the requested bits in the SSI DMA control register. - HWREG(ui32Base + SSI_O_DMACR) &= ~ui32DMAFlags; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SSIConfigSetExpClk - #undef SSIConfigSetExpClk - #define SSIConfigSetExpClk ROM_SSIConfigSetExpClk - #endif - #ifdef ROM_SSIDataPut - #undef SSIDataPut - #define SSIDataPut ROM_SSIDataPut - #endif - #ifdef ROM_SSIDataPutNonBlocking - #undef SSIDataPutNonBlocking - #define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking - #endif - #ifdef ROM_SSIDataGet - #undef SSIDataGet - #define SSIDataGet ROM_SSIDataGet - #endif - #ifdef ROM_SSIDataGetNonBlocking - #undef SSIDataGetNonBlocking - #define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking - #endif - #ifdef ROM_SSIIntRegister - #undef SSIIntRegister - #define SSIIntRegister ROM_SSIIntRegister - #endif - #ifdef ROM_SSIIntUnregister - #undef SSIIntUnregister - #define SSIIntUnregister ROM_SSIIntUnregister - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/sw_chacha.c b/third_party/ti/devices/cc26x0/driverlib/sw_chacha.c deleted file mode 100644 index 781f48fda..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/sw_chacha.c +++ /dev/null @@ -1,121 +0,0 @@ -/****************************************************************************** -* Filename: sw_chacha.c -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* -chacha-ref.c version 20080118 -D. J. Bernstein -Public domain. -*/ - -#define ECRYPT_LITTLE_ENDIAN - -#include "sw_ecrypt-sync.h" - -#define ROTATE(v,c) (ROTL32(v,c)) -#define XOR(v,w) ((v) ^ (w)) -#define PLUS(v,w) (U32V((v) + (w))) -#define PLUSONE(v) (PLUS((v),1)) - -#define QUARTERROUND(a,b,c,d) \ - x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]),16); \ - x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]),12); \ - x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]), 8); \ - x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]), 7); - -static void salsa20_wordtobyte(u8 output[64],const u32 input[16]) -{ - u32 x[16]; - int i; - - for (i = 0;i < 16;++i) x[i] = input[i]; - for (i = 8;i > 0;i -= 2) { - QUARTERROUND( 0, 4, 8,12) - QUARTERROUND( 1, 5, 9,13) - QUARTERROUND( 2, 6,10,14) - QUARTERROUND( 3, 7,11,15) - QUARTERROUND( 0, 5,10,15) - QUARTERROUND( 1, 6,11,12) - QUARTERROUND( 2, 7, 8,13) - QUARTERROUND( 3, 4, 9,14) - } - for (i = 0;i < 16;++i) x[i] = PLUS(x[i],input[i]); - for (i = 0;i < 16;++i) U32TO8_LITTLE(output + 4 * i,x[i]); -} - -void ECRYPT_init(void) -{ - return; -} - -static const char sigma[16] = "expand 32-byte k"; -static const char tau[16] = "expand 16-byte k"; - -void ECRYPT_keysetup(ECRYPT_ctx *x,const u8 *k,u32 kbits,u32 ivbits) -{ - const char *constants; - - x->input[4] = U8TO32_LITTLE(k + 0); - x->input[5] = U8TO32_LITTLE(k + 4); - x->input[6] = U8TO32_LITTLE(k + 8); - x->input[7] = U8TO32_LITTLE(k + 12); - if (kbits == 256) { /* recommended */ - k += 16; - constants = sigma; - } else { /* kbits == 128 */ - constants = tau; - } - x->input[8] = U8TO32_LITTLE(k + 0); - x->input[9] = U8TO32_LITTLE(k + 4); - x->input[10] = U8TO32_LITTLE(k + 8); - x->input[11] = U8TO32_LITTLE(k + 12); - x->input[0] = U8TO32_LITTLE(constants + 0); - x->input[1] = U8TO32_LITTLE(constants + 4); - x->input[2] = U8TO32_LITTLE(constants + 8); - x->input[3] = U8TO32_LITTLE(constants + 12); -} - -void ECRYPT_ivsetup(ECRYPT_ctx *x,const u8 *iv) -{ - x->input[12] = 0; - x->input[13] = 0; - x->input[14] = U8TO32_LITTLE(iv + 0); - x->input[15] = U8TO32_LITTLE(iv + 4); -} - -void ECRYPT_encrypt_bytes(ECRYPT_ctx *x,const u8 *m,u8 *c,u32 bytes) -{ - u8 output[64]; - int i; - - if (!bytes) return; - for (;;) { - salsa20_wordtobyte(output,x->input); - x->input[12] = PLUSONE(x->input[12]); - if (!x->input[12]) { - x->input[13] = PLUSONE(x->input[13]); - /* stopping at 2^70 bytes per nonce is user's responsibility */ - } - if (bytes <= 64) { - for (i = 0;i < bytes;++i) c[i] = m[i] ^ output[i]; - return; - } - for (i = 0;i < 64;++i) c[i] = m[i] ^ output[i]; - bytes -= 64; - c += 64; - m += 64; - } -} - -void ECRYPT_decrypt_bytes(ECRYPT_ctx *x,const u8 *c,u8 *m,u32 bytes) -{ - ECRYPT_encrypt_bytes(x,c,m,bytes); -} - -void ECRYPT_keystream_bytes(ECRYPT_ctx *x,u8 *stream,u32 bytes) -{ - u32 i; - for (i = 0;i < bytes;++i) stream[i] = 0; - ECRYPT_encrypt_bytes(x,stream,stream,bytes); -} diff --git a/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-config.h b/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-config.h deleted file mode 100644 index 6ec233d3b..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-config.h +++ /dev/null @@ -1,279 +0,0 @@ -/****************************************************************************** -* Filename: sw_ecrypt-config.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* ecrypt-config.h */ - -/* *** Normally, it should not be necessary to edit this file. *** */ - -#ifndef ECRYPT_CONFIG -#define ECRYPT_CONFIG - -/* ------------------------------------------------------------------------- */ - -/* Guess the endianness of the target architecture. */ - -/* - * The LITTLE endian machines: - */ -#if ( ! defined(ECRYPT_LITTLE_ENDIAN)) -#if defined(__ultrix) /* Older MIPS */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(__alpha) /* Alpha */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(i386) /* x86 (gcc) */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(__i386) /* x86 (gcc) */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(_M_IX86) /* x86 (MSC, Borland) */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(_MSC_VER) /* x86 (surely MSC) */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ -#define ECRYPT_LITTLE_ENDIAN - -/* - * The BIG endian machines: - */ -#elif defined(sun) /* Newer Sparc's */ -#define ECRYPT_BIG_ENDIAN -#elif defined(__ppc__) /* PowerPC */ -#define ECRYPT_BIG_ENDIAN - -/* - * Finally machines with UNKNOWN endianness: - */ -#elif defined (_AIX) /* RS6000 */ -#define ECRYPT_UNKNOWN -#elif defined(__hpux) /* HP-PA */ -#define ECRYPT_UNKNOWN -#elif defined(__aux) /* 68K */ -#define ECRYPT_UNKNOWN -#elif defined(__dgux) /* 88K (but P6 in latest boxes) */ -#define ECRYPT_UNKNOWN -#elif defined(__sgi) /* Newer MIPS */ -#define ECRYPT_UNKNOWN -#else /* Any other processor */ -#define ECRYPT_UNKNOWN -#endif -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * Find minimal-width types to store 8-bit, 16-bit, 32-bit, and 64-bit - * integers. - * - * Note: to enable 64-bit types on 32-bit compilers, it might be - * necessary to switch from ISO C90 mode to ISO C99 mode (e.g., gcc - * -std=c99). - */ - -#include - -/* --- check char --- */ - -#if (UCHAR_MAX / 0xFU > 0xFU) -#ifndef I8T -#define I8T char -#define U8C(v) (v##U) - -#if (UCHAR_MAX == 0xFFU) -#define ECRYPT_I8T_IS_BYTE -#endif - -#endif - -#if (UCHAR_MAX / 0xFFU > 0xFFU) -#ifndef I16T -#define I16T char -#define U16C(v) (v##U) -#endif - -#if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) -#ifndef I32T -#define I32T char -#define U32C(v) (v##U) -#endif - -#if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) -#ifndef I64T -#define I64T char -#define U64C(v) (v##U) -#define ECRYPT_NATIVE64 -#endif - -#endif -#endif -#endif -#endif - -/* --- check short --- */ - -#if (USHRT_MAX / 0xFU > 0xFU) -#ifndef I8T -#define I8T short -#define U8C(v) (v##U) - -#if (USHRT_MAX == 0xFFU) -#define ECRYPT_I8T_IS_BYTE -#endif - -#endif - -#if (USHRT_MAX / 0xFFU > 0xFFU) -#ifndef I16T -#define I16T short -#define U16C(v) (v##U) -#endif - -#if (USHRT_MAX / 0xFFFFU > 0xFFFFU) -#ifndef I32T -#define I32T short -#define U32C(v) (v##U) -#endif - -#if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) -#ifndef I64T -#define I64T short -#define U64C(v) (v##U) -#define ECRYPT_NATIVE64 -#endif - -#endif -#endif -#endif -#endif - -/* --- check int --- */ - -#if (UINT_MAX / 0xFU > 0xFU) -#ifndef I8T -#define I8T int -#define U8C(v) (v##U) - -#if (ULONG_MAX == 0xFFU) -#define ECRYPT_I8T_IS_BYTE -#endif - -#endif - -#if (UINT_MAX / 0xFFU > 0xFFU) -#ifndef I16T -#define I16T int -#define U16C(v) (v##U) -#endif - -#if (UINT_MAX / 0xFFFFU > 0xFFFFU) -#ifndef I32T -#define I32T int -#define U32C(v) (v##U) -#endif - -#if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) -#ifndef I64T -#define I64T int -#define U64C(v) (v##U) -#define ECRYPT_NATIVE64 -#endif - -#endif -#endif -#endif -#endif - -/* --- check long --- */ - -#if (ULONG_MAX / 0xFUL > 0xFUL) -#ifndef I8T -#define I8T long -#define U8C(v) (v##UL) - -#if (ULONG_MAX == 0xFFUL) -#define ECRYPT_I8T_IS_BYTE -#endif - -#endif - -#if (ULONG_MAX / 0xFFUL > 0xFFUL) -#ifndef I16T -#define I16T long -#define U16C(v) (v##UL) -#endif - -#if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) -#ifndef I32T -#define I32T long -#define U32C(v) (v##UL) -#endif - -#if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) -#ifndef I64T -#define I64T long -#define U64C(v) (v##UL) -#define ECRYPT_NATIVE64 -#endif - -#endif -#endif -#endif -#endif - -/* --- check long long --- */ - -#ifdef ULLONG_MAX - -#if (ULLONG_MAX / 0xFULL > 0xFULL) -#ifndef I8T -#define I8T long long -#define U8C(v) (v##ULL) - -#if (ULLONG_MAX == 0xFFULL) -#define ECRYPT_I8T_IS_BYTE -#endif - -#endif - -#if (ULLONG_MAX / 0xFFULL > 0xFFULL) -#ifndef I16T -#define I16T long long -#define U16C(v) (v##ULL) -#endif - -#if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) -#ifndef I32T -#define I32T long long -#define U32C(v) (v##ULL) -#endif - -#if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) -#ifndef I64T -#define I64T long long -#define U64C(v) (v##ULL) -#endif - -#endif -#endif -#endif -#endif - -#endif - -/* --- check __int64 --- */ - -#ifdef _UI64_MAX - -#if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) -#ifndef I64T -#define I64T __int64 -#define U64C(v) (v##ui64) -#endif - -#endif - -#endif - -/* ------------------------------------------------------------------------- */ - -#endif diff --git a/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-machine.h b/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-machine.h deleted file mode 100644 index 7194dcb6c..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-machine.h +++ /dev/null @@ -1,51 +0,0 @@ -/****************************************************************************** -* Filename: sw_ecrypt-machine.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* ecrypt-machine.h */ - -/* - * This file is included by 'ecrypt-portable.h'. It allows to override - * the default macros for specific platforms. Please carefully check - * the machine code generated by your compiler (with optimisations - * turned on) before deciding to edit this file. - */ - -/* ------------------------------------------------------------------------- */ - -#if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT)) - -#define ECRYPT_MACHINE_ROT - -#if (defined(WIN32) && defined(_MSC_VER)) - -#undef ROTL32 -#undef ROTR32 -#undef ROTL64 -#undef ROTR64 - -#include - -#define ROTL32(v, n) _lrotl(v, n) -#define ROTR32(v, n) _lrotr(v, n) -#define ROTL64(v, n) _rotl64(v, n) -#define ROTR64(v, n) _rotr64(v, n) - -#endif - -#endif - -/* ------------------------------------------------------------------------- */ - -#if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP)) - -#define ECRYPT_MACHINE_SWAP - -/* - * If you want to overwrite the default swap macros, put it here. And so on. - */ - -#endif - -/* ------------------------------------------------------------------------- */ diff --git a/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-portable.h b/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-portable.h deleted file mode 100644 index dd81b8316..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-portable.h +++ /dev/null @@ -1,308 +0,0 @@ -/****************************************************************************** -* Filename: sw_ecrypt-portable.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* ecrypt-portable.h */ - -/* - * WARNING: the conversions defined below are implemented as macros, - * and should be used carefully. They should NOT be used with - * parameters which perform some action. E.g., the following two lines - * are not equivalent: - * - * 1) ++x; y = ROTL32(x, n); - * 2) y = ROTL32(++x, n); - */ - -/* - * *** Please do not edit this file. *** - * - * The default macros can be overridden for specific architectures by - * editing 'ecrypt-machine.h'. - */ - -#ifndef ECRYPT_PORTABLE -#define ECRYPT_PORTABLE - -#include "sw_ecrypt-config.h" - -/* ------------------------------------------------------------------------- */ - -/* - * The following types are defined (if available): - * - * u8: unsigned integer type, at least 8 bits - * u16: unsigned integer type, at least 16 bits - * u32: unsigned integer type, at least 32 bits - * u64: unsigned integer type, at least 64 bits - * - * s8, s16, s32, s64 -> signed counterparts of u8, u16, u32, u64 - * - * The selection of minimum-width integer types is taken care of by - * 'ecrypt-config.h'. Note: to enable 64-bit types on 32-bit - * compilers, it might be necessary to switch from ISO C90 mode to ISO - * C99 mode (e.g., gcc -std=c99). - */ - -#ifdef I8T -typedef signed I8T s8; -typedef unsigned I8T u8; -#endif - -#ifdef I16T -typedef signed I16T s16; -typedef unsigned I16T u16; -#endif - -#ifdef I32T -typedef signed I32T s32; -typedef unsigned I32T u32; -#endif - -#ifdef I64T -typedef signed I64T s64; -typedef unsigned I64T u64; -#endif - -/* - * The following macros are used to obtain exact-width results. - */ - -#define U8V(v) ((u8)(v) & U8C(0xFF)) -#define U16V(v) ((u16)(v) & U16C(0xFFFF)) -#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF)) -#define U64V(v) ((u64)(v) & U64C(0xFFFFFFFFFFFFFFFF)) - -/* ------------------------------------------------------------------------- */ - -/* - * The following macros return words with their bits rotated over n - * positions to the left/right. - */ - -#define ECRYPT_DEFAULT_ROT - -#define ROTL8(v, n) \ - (U8V((v) << (n)) | ((v) >> (8 - (n)))) - -#define ROTL16(v, n) \ - (U16V((v) << (n)) | ((v) >> (16 - (n)))) - -#define ROTL32(v, n) \ - (U32V((v) << (n)) | ((v) >> (32 - (n)))) - -#define ROTL64(v, n) \ - (U64V((v) << (n)) | ((v) >> (64 - (n)))) - -#define ROTR8(v, n) ROTL8(v, 8 - (n)) -#define ROTR16(v, n) ROTL16(v, 16 - (n)) -#define ROTR32(v, n) ROTL32(v, 32 - (n)) -#define ROTR64(v, n) ROTL64(v, 64 - (n)) - -#include "sw_ecrypt-machine.h" - -/* ------------------------------------------------------------------------- */ - -/* - * The following macros return a word with bytes in reverse order. - */ - -#define ECRYPT_DEFAULT_SWAP - -#define SWAP16(v) \ - ROTL16(v, 8) - -#define SWAP32(v) \ - ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ - (ROTL32(v, 24) & U32C(0xFF00FF00))) - -#ifdef ECRYPT_NATIVE64 -#define SWAP64(v) \ - ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ - (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \ - (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | \ - (ROTL64(v, 56) & U64C(0xFF000000FF000000))) -#else -#define SWAP64(v) \ - (((u64)SWAP32(U32V(v)) << 32) | (u64)SWAP32(U32V(v >> 32))) -#endif - -#include "sw_ecrypt-machine.h" - -#define ECRYPT_DEFAULT_WTOW - -#ifdef ECRYPT_LITTLE_ENDIAN -#define U16TO16_LITTLE(v) (v) -#define U32TO32_LITTLE(v) (v) -#define U64TO64_LITTLE(v) (v) - -#define U16TO16_BIG(v) SWAP16(v) -#define U32TO32_BIG(v) SWAP32(v) -#define U64TO64_BIG(v) SWAP64(v) -#endif - -#ifdef ECRYPT_BIG_ENDIAN -#define U16TO16_LITTLE(v) SWAP16(v) -#define U32TO32_LITTLE(v) SWAP32(v) -#define U64TO64_LITTLE(v) SWAP64(v) - -#define U16TO16_BIG(v) (v) -#define U32TO32_BIG(v) (v) -#define U64TO64_BIG(v) (v) -#endif - -#include "sw_ecrypt-machine.h" - -/* - * The following macros load words from an array of bytes with - * different types of endianness, and vice versa. - */ - -#define ECRYPT_DEFAULT_BTOW - -#if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE)) - -#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16*)(p))[0]) -#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32*)(p))[0]) -#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64*)(p))[0]) - -#define U8TO16_BIG(p) U16TO16_BIG(((u16*)(p))[0]) -#define U8TO32_BIG(p) U32TO32_BIG(((u32*)(p))[0]) -#define U8TO64_BIG(p) U64TO64_BIG(((u64*)(p))[0]) - -#define U16TO8_LITTLE(p, v) (((u16*)(p))[0] = U16TO16_LITTLE(v)) -#define U32TO8_LITTLE(p, v) (((u32*)(p))[0] = U32TO32_LITTLE(v)) -#define U64TO8_LITTLE(p, v) (((u64*)(p))[0] = U64TO64_LITTLE(v)) - -#define U16TO8_BIG(p, v) (((u16*)(p))[0] = U16TO16_BIG(v)) -#define U32TO8_BIG(p, v) (((u32*)(p))[0] = U32TO32_BIG(v)) -#define U64TO8_BIG(p, v) (((u64*)(p))[0] = U64TO64_BIG(v)) - -#else - -#define U8TO16_LITTLE(p) \ - (((u16)((p)[0]) ) | \ - ((u16)((p)[1]) << 8)) - -#define U8TO32_LITTLE(p) \ - (((u32)((p)[0]) ) | \ - ((u32)((p)[1]) << 8) | \ - ((u32)((p)[2]) << 16) | \ - ((u32)((p)[3]) << 24)) - -#ifdef ECRYPT_NATIVE64 -#define U8TO64_LITTLE(p) \ - (((u64)((p)[0]) ) | \ - ((u64)((p)[1]) << 8) | \ - ((u64)((p)[2]) << 16) | \ - ((u64)((p)[3]) << 24) | \ - ((u64)((p)[4]) << 32) | \ - ((u64)((p)[5]) << 40) | \ - ((u64)((p)[6]) << 48) | \ - ((u64)((p)[7]) << 56)) -#else -#define U8TO64_LITTLE(p) \ - ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32)) -#endif - -#define U8TO16_BIG(p) \ - (((u16)((p)[0]) << 8) | \ - ((u16)((p)[1]) )) - -#define U8TO32_BIG(p) \ - (((u32)((p)[0]) << 24) | \ - ((u32)((p)[1]) << 16) | \ - ((u32)((p)[2]) << 8) | \ - ((u32)((p)[3]) )) - -#ifdef ECRYPT_NATIVE64 -#define U8TO64_BIG(p) \ - (((u64)((p)[0]) << 56) | \ - ((u64)((p)[1]) << 48) | \ - ((u64)((p)[2]) << 40) | \ - ((u64)((p)[3]) << 32) | \ - ((u64)((p)[4]) << 24) | \ - ((u64)((p)[5]) << 16) | \ - ((u64)((p)[6]) << 8) | \ - ((u64)((p)[7]) )) -#else -#define U8TO64_BIG(p) \ - (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4)) -#endif - -#define U16TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ - } while (0) - -#define U32TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ - (p)[2] = U8V((v) >> 16); \ - (p)[3] = U8V((v) >> 24); \ - } while (0) - -#ifdef ECRYPT_NATIVE64 -#define U64TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ - (p)[2] = U8V((v) >> 16); \ - (p)[3] = U8V((v) >> 24); \ - (p)[4] = U8V((v) >> 32); \ - (p)[5] = U8V((v) >> 40); \ - (p)[6] = U8V((v) >> 48); \ - (p)[7] = U8V((v) >> 56); \ - } while (0) -#else -#define U64TO8_LITTLE(p, v) \ - do { \ - U32TO8_LITTLE((p), U32V((v) )); \ - U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \ - } while (0) -#endif - -#define U16TO8_BIG(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ - } while (0) - -#define U32TO8_BIG(p, v) \ - do { \ - (p)[0] = U8V((v) >> 24); \ - (p)[1] = U8V((v) >> 16); \ - (p)[2] = U8V((v) >> 8); \ - (p)[3] = U8V((v) ); \ - } while (0) - -#ifdef ECRYPT_NATIVE64 -#define U64TO8_BIG(p, v) \ - do { \ - (p)[0] = U8V((v) >> 56); \ - (p)[1] = U8V((v) >> 48); \ - (p)[2] = U8V((v) >> 40); \ - (p)[3] = U8V((v) >> 32); \ - (p)[4] = U8V((v) >> 24); \ - (p)[5] = U8V((v) >> 16); \ - (p)[6] = U8V((v) >> 8); \ - (p)[7] = U8V((v) ); \ - } while (0) -#else -#define U64TO8_BIG(p, v) \ - do { \ - U32TO8_BIG((p), U32V((v) >> 32)); \ - U32TO8_BIG((p) + 4, U32V((v) )); \ - } while (0) -#endif - -#endif - -#include "sw_ecrypt-machine.h" - -/* ------------------------------------------------------------------------- */ - -#endif diff --git a/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-sync.h b/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-sync.h deleted file mode 100644 index 436d10887..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/sw_ecrypt-sync.h +++ /dev/null @@ -1,284 +0,0 @@ -/****************************************************************************** -* Filename: sw_ecrypt-sync.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* ecrypt-sync.h */ - -/* - * Header file for synchronous stream ciphers without authentication - * mechanism. - * - * *** Please only edit parts marked with "[edit]". *** - */ - -#ifndef ECRYPT_SYNC -#define ECRYPT_SYNC - -#include "sw_ecrypt-portable.h" - -/* ------------------------------------------------------------------------- */ - -/* Cipher parameters */ - -/* - * The name of your cipher. - */ -#define ECRYPT_NAME "ChaCha8" -#define ECRYPT_PROFILE "_____" - -/* - * Specify which key and IV sizes are supported by your cipher. A user - * should be able to enumerate the supported sizes by running the - * following code: - * - * for (i = 0; ECRYPT_KEYSIZE(i) <= ECRYPT_MAXKEYSIZE; ++i) - * { - * keysize = ECRYPT_KEYSIZE(i); - * - * ... - * } - * - * All sizes are in bits. - */ - -#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ -#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */ - -#define ECRYPT_MAXIVSIZE 64 /* [edit] */ -#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */ - -/* ------------------------------------------------------------------------- */ - -/* Data structures */ - -/* - * ECRYPT_ctx is the structure containing the representation of the - * internal state of your cipher. - */ - -typedef struct -{ - u32 input[16]; /* could be compressed */ - /* - * [edit] - * - * Put here all state variable needed during the encryption process. - */ -} ECRYPT_ctx; - -/* ------------------------------------------------------------------------- */ - -/* Mandatory functions */ - -/* - * Key and message independent initialization. This function will be - * called once when the program starts (e.g., to build expanded S-box - * tables). - */ -void ECRYPT_init(void); - -/* - * Key setup. It is the user's responsibility to select the values of - * keysize and ivsize from the set of supported values specified - * above. - */ -void ECRYPT_keysetup( - ECRYPT_ctx* ctx, - const u8* key, - u32 keysize, /* Key size in bits. */ - u32 ivsize); /* IV size in bits. */ - -/* - * IV setup. After having called ECRYPT_keysetup(), the user is - * allowed to call ECRYPT_ivsetup() different times in order to - * encrypt/decrypt different messages with the same key but different - * IV's. - */ -void ECRYPT_ivsetup( - ECRYPT_ctx* ctx, - const u8* iv); - -/* - * Encryption/decryption of arbitrary length messages. - * - * For efficiency reasons, the API provides two types of - * encrypt/decrypt functions. The ECRYPT_encrypt_bytes() function - * (declared here) encrypts byte strings of arbitrary length, while - * the ECRYPT_encrypt_blocks() function (defined later) only accepts - * lengths which are multiples of ECRYPT_BLOCKLENGTH. - * - * The user is allowed to make multiple calls to - * ECRYPT_encrypt_blocks() to incrementally encrypt a long message, - * but he is NOT allowed to make additional encryption calls once he - * has called ECRYPT_encrypt_bytes() (unless he starts a new message - * of course). For example, this sequence of calls is acceptable: - * - * ECRYPT_keysetup(); - * - * ECRYPT_ivsetup(); - * ECRYPT_encrypt_blocks(); - * ECRYPT_encrypt_blocks(); - * ECRYPT_encrypt_bytes(); - * - * ECRYPT_ivsetup(); - * ECRYPT_encrypt_blocks(); - * ECRYPT_encrypt_blocks(); - * - * ECRYPT_ivsetup(); - * ECRYPT_encrypt_bytes(); - * - * The following sequence is not: - * - * ECRYPT_keysetup(); - * ECRYPT_ivsetup(); - * ECRYPT_encrypt_blocks(); - * ECRYPT_encrypt_bytes(); - * ECRYPT_encrypt_blocks(); - */ - -void ECRYPT_encrypt_bytes( - ECRYPT_ctx* ctx, - const u8* plaintext, - u8* ciphertext, - u32 msglen); /* Message length in bytes. */ - -void ECRYPT_decrypt_bytes( - ECRYPT_ctx* ctx, - const u8* ciphertext, - u8* plaintext, - u32 msglen); /* Message length in bytes. */ - -/* ------------------------------------------------------------------------- */ - -/* Optional features */ - -/* - * For testing purposes it can sometimes be useful to have a function - * which immediately generates keystream without having to provide it - * with a zero plaintext. If your cipher cannot provide this function - * (e.g., because it is not strictly a synchronous cipher), please - * reset the ECRYPT_GENERATES_KEYSTREAM flag. - */ - -#define ECRYPT_GENERATES_KEYSTREAM -#ifdef ECRYPT_GENERATES_KEYSTREAM - -void ECRYPT_keystream_bytes( - ECRYPT_ctx* ctx, - u8* keystream, - u32 length); /* Length of keystream in bytes. */ - -#endif - -/* ------------------------------------------------------------------------- */ - -/* Optional optimizations */ - -/* - * By default, the functions in this section are implemented using - * calls to functions declared above. However, you might want to - * implement them differently for performance reasons. - */ - -/* - * All-in-one encryption/decryption of (short) packets. - * - * The default definitions of these functions can be found in - * "ecrypt-sync.c". If you want to implement them differently, please - * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag. - */ -#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ - -void ECRYPT_encrypt_packet( - ECRYPT_ctx* ctx, - const u8* iv, - const u8* plaintext, - u8* ciphertext, - u32 msglen); - -void ECRYPT_decrypt_packet( - ECRYPT_ctx* ctx, - const u8* iv, - const u8* ciphertext, - u8* plaintext, - u32 msglen); - -/* - * Encryption/decryption of blocks. - * - * By default, these functions are defined as macros. If you want to - * provide a different implementation, please undef the - * ECRYPT_USES_DEFAULT_BLOCK_MACROS flag and implement the functions - * declared below. - */ - -#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ - -#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ -#ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS - -#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ - ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ - (blocks) * ECRYPT_BLOCKLENGTH) - -#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ - ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ - (blocks) * ECRYPT_BLOCKLENGTH) - -#ifdef ECRYPT_GENERATES_KEYSTREAM - -#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ - ECRYPT_keystream_bytes(ctx, keystream, \ - (blocks) * ECRYPT_BLOCKLENGTH) - -#endif - -#else - -void ECRYPT_encrypt_blocks( - ECRYPT_ctx* ctx, - const u8* plaintext, - u8* ciphertext, - u32 blocks); /* Message length in blocks. */ - -void ECRYPT_decrypt_blocks( - ECRYPT_ctx* ctx, - const u8* ciphertext, - u8* plaintext, - u32 blocks); /* Message length in blocks. */ - -#ifdef ECRYPT_GENERATES_KEYSTREAM - -void ECRYPT_keystream_blocks( - ECRYPT_ctx* ctx, - const u8* keystream, - u32 blocks); /* Keystream length in blocks. */ - -#endif - -#endif - -/* - * If your cipher can be implemented in different ways, you can use - * the ECRYPT_VARIANT parameter to allow the user to choose between - * them at compile time (e.g., gcc -DECRYPT_VARIANT=3 ...). Please - * only use this possibility if you really think it could make a - * significant difference and keep the number of variants - * (ECRYPT_MAXVARIANT) as small as possible (definitely not more than - * 10). Note also that all variants should have exactly the same - * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.). - */ -#define ECRYPT_MAXVARIANT 1 /* [edit] */ - -#ifndef ECRYPT_VARIANT -#define ECRYPT_VARIANT 1 -#endif - -#if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT) -#error this variant does not exist -#endif - -/* ------------------------------------------------------------------------- */ - -#endif diff --git a/third_party/ti/devices/cc26x0/driverlib/sw_poly1305-donna-32.h b/third_party/ti/devices/cc26x0/driverlib/sw_poly1305-donna-32.h deleted file mode 100644 index b25d40a3f..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/sw_poly1305-donna-32.h +++ /dev/null @@ -1,223 +0,0 @@ -/****************************************************************************** -* Filename: sw_poly1305-donna-32.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* - poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition -*/ - -#if defined(_MSC_VER) - #define POLY1305_NOINLINE __declspec(noinline) -#elif defined(__GNUC__) - #define POLY1305_NOINLINE __attribute__((noinline)) -#else - #define POLY1305_NOINLINE -#endif - -#define poly1305_block_size 16 - -/* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */ -typedef struct { - unsigned long r[5]; - unsigned long h[5]; - unsigned long pad[4]; - size_t leftover; - unsigned char buffer[poly1305_block_size]; - unsigned char final; -} poly1305_state_internal_t; - -/* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */ -static unsigned long -U8TO32(const unsigned char *p) { - return - (((unsigned long)(p[0] & 0xff) ) | - ((unsigned long)(p[1] & 0xff) << 8) | - ((unsigned long)(p[2] & 0xff) << 16) | - ((unsigned long)(p[3] & 0xff) << 24)); -} - -/* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */ -static void -U32TO8(unsigned char *p, unsigned long v) { - p[0] = (v ) & 0xff; - p[1] = (v >> 8) & 0xff; - p[2] = (v >> 16) & 0xff; - p[3] = (v >> 24) & 0xff; -} - -void -poly1305_init(poly1305_context *ctx, const unsigned char key[32]) { - poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; - - /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */ - st->r[0] = (U8TO32(&key[ 0]) ) & 0x3ffffff; - st->r[1] = (U8TO32(&key[ 3]) >> 2) & 0x3ffff03; - st->r[2] = (U8TO32(&key[ 6]) >> 4) & 0x3ffc0ff; - st->r[3] = (U8TO32(&key[ 9]) >> 6) & 0x3f03fff; - st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff; - - /* h = 0 */ - st->h[0] = 0; - st->h[1] = 0; - st->h[2] = 0; - st->h[3] = 0; - st->h[4] = 0; - - /* save pad for later */ - st->pad[0] = U8TO32(&key[16]); - st->pad[1] = U8TO32(&key[20]); - st->pad[2] = U8TO32(&key[24]); - st->pad[3] = U8TO32(&key[28]); - - st->leftover = 0; - st->final = 0; -} - -static void -poly1305_blocks(poly1305_state_internal_t *st, const unsigned char *m, size_t bytes) { - const unsigned long hibit = (st->final) ? 0 : (1UL << 24); /* 1 << 128 */ - unsigned long r0,r1,r2,r3,r4; - unsigned long s1,s2,s3,s4; - unsigned long h0,h1,h2,h3,h4; - unsigned long long d0,d1,d2,d3,d4; - unsigned long c; - - r0 = st->r[0]; - r1 = st->r[1]; - r2 = st->r[2]; - r3 = st->r[3]; - r4 = st->r[4]; - - s1 = r1 * 5; - s2 = r2 * 5; - s3 = r3 * 5; - s4 = r4 * 5; - - h0 = st->h[0]; - h1 = st->h[1]; - h2 = st->h[2]; - h3 = st->h[3]; - h4 = st->h[4]; - - while (bytes >= poly1305_block_size) { - /* h += m[i] */ - h0 += (U8TO32(m+ 0) ) & 0x3ffffff; - h1 += (U8TO32(m+ 3) >> 2) & 0x3ffffff; - h2 += (U8TO32(m+ 6) >> 4) & 0x3ffffff; - h3 += (U8TO32(m+ 9) >> 6) & 0x3ffffff; - h4 += (U8TO32(m+12) >> 8) | hibit; - - /* h *= r */ - d0 = ((unsigned long long)h0 * r0) + ((unsigned long long)h1 * s4) + ((unsigned long long)h2 * s3) + ((unsigned long long)h3 * s2) + ((unsigned long long)h4 * s1); - d1 = ((unsigned long long)h0 * r1) + ((unsigned long long)h1 * r0) + ((unsigned long long)h2 * s4) + ((unsigned long long)h3 * s3) + ((unsigned long long)h4 * s2); - d2 = ((unsigned long long)h0 * r2) + ((unsigned long long)h1 * r1) + ((unsigned long long)h2 * r0) + ((unsigned long long)h3 * s4) + ((unsigned long long)h4 * s3); - d3 = ((unsigned long long)h0 * r3) + ((unsigned long long)h1 * r2) + ((unsigned long long)h2 * r1) + ((unsigned long long)h3 * r0) + ((unsigned long long)h4 * s4); - d4 = ((unsigned long long)h0 * r4) + ((unsigned long long)h1 * r3) + ((unsigned long long)h2 * r2) + ((unsigned long long)h3 * r1) + ((unsigned long long)h4 * r0); - - /* (partial) h %= p */ - c = (unsigned long)(d0 >> 26); h0 = (unsigned long)d0 & 0x3ffffff; - d1 += c; c = (unsigned long)(d1 >> 26); h1 = (unsigned long)d1 & 0x3ffffff; - d2 += c; c = (unsigned long)(d2 >> 26); h2 = (unsigned long)d2 & 0x3ffffff; - d3 += c; c = (unsigned long)(d3 >> 26); h3 = (unsigned long)d3 & 0x3ffffff; - d4 += c; c = (unsigned long)(d4 >> 26); h4 = (unsigned long)d4 & 0x3ffffff; - h0 += c * 5; c = (h0 >> 26); h0 = h0 & 0x3ffffff; - h1 += c; - - m += poly1305_block_size; - bytes -= poly1305_block_size; - } - - st->h[0] = h0; - st->h[1] = h1; - st->h[2] = h2; - st->h[3] = h3; - st->h[4] = h4; -} - -POLY1305_NOINLINE void -poly1305_finish(poly1305_context *ctx, unsigned char mac[16]) { - poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; - unsigned long h0,h1,h2,h3,h4,c; - unsigned long g0,g1,g2,g3,g4; - unsigned long long f; - unsigned long mask; - - /* process the remaining block */ - if (st->leftover) { - size_t i = st->leftover; - st->buffer[i++] = 1; - for (; i < poly1305_block_size; i++) - st->buffer[i] = 0; - st->final = 1; - poly1305_blocks(st, st->buffer, poly1305_block_size); - } - - /* fully carry h */ - h0 = st->h[0]; - h1 = st->h[1]; - h2 = st->h[2]; - h3 = st->h[3]; - h4 = st->h[4]; - - c = h1 >> 26; h1 = h1 & 0x3ffffff; - h2 += c; c = h2 >> 26; h2 = h2 & 0x3ffffff; - h3 += c; c = h3 >> 26; h3 = h3 & 0x3ffffff; - h4 += c; c = h4 >> 26; h4 = h4 & 0x3ffffff; - h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff; - h1 += c; - - /* compute h + -p */ - g0 = h0 + 5; c = g0 >> 26; g0 &= 0x3ffffff; - g1 = h1 + c; c = g1 >> 26; g1 &= 0x3ffffff; - g2 = h2 + c; c = g2 >> 26; g2 &= 0x3ffffff; - g3 = h3 + c; c = g3 >> 26; g3 &= 0x3ffffff; - g4 = h4 + c - (1UL << 26); - - /* select h if h < p, or h + -p if h >= p */ - mask = (g4 >> ((sizeof(unsigned long) * 8) - 1)) - 1; - g0 &= mask; - g1 &= mask; - g2 &= mask; - g3 &= mask; - g4 &= mask; - mask = ~mask; - h0 = (h0 & mask) | g0; - h1 = (h1 & mask) | g1; - h2 = (h2 & mask) | g2; - h3 = (h3 & mask) | g3; - h4 = (h4 & mask) | g4; - - /* h = h % (2^128) */ - h0 = ((h0 ) | (h1 << 26)) & 0xffffffff; - h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; - h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff; - h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; - - /* mac = (h + pad) % (2^128) */ - f = (unsigned long long)h0 + st->pad[0] ; h0 = (unsigned long)f; - f = (unsigned long long)h1 + st->pad[1] + (f >> 32); h1 = (unsigned long)f; - f = (unsigned long long)h2 + st->pad[2] + (f >> 32); h2 = (unsigned long)f; - f = (unsigned long long)h3 + st->pad[3] + (f >> 32); h3 = (unsigned long)f; - - U32TO8(mac + 0, h0); - U32TO8(mac + 4, h1); - U32TO8(mac + 8, h2); - U32TO8(mac + 12, h3); - - /* zero out the state */ - st->h[0] = 0; - st->h[1] = 0; - st->h[2] = 0; - st->h[3] = 0; - st->h[4] = 0; - st->r[0] = 0; - st->r[1] = 0; - st->r[2] = 0; - st->r[3] = 0; - st->r[4] = 0; - st->pad[0] = 0; - st->pad[1] = 0; - st->pad[2] = 0; - st->pad[3] = 0; -} diff --git a/third_party/ti/devices/cc26x0/driverlib/sw_poly1305-donna.c b/third_party/ti/devices/cc26x0/driverlib/sw_poly1305-donna.c deleted file mode 100644 index 63234fe68..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/sw_poly1305-donna.c +++ /dev/null @@ -1,186 +0,0 @@ -/****************************************************************************** -* Filename: sw_poly1305-donna.c -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ - -#include "sw_poly1305-donna.h" - -#include "sw_poly1305-donna-32.h" - -void -poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes) { - poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; - size_t i; - - /* handle leftover */ - if (st->leftover) { - size_t want = (poly1305_block_size - st->leftover); - if (want > bytes) - want = bytes; - for (i = 0; i < want; i++) - st->buffer[st->leftover + i] = m[i]; - bytes -= want; - m += want; - st->leftover += want; - if (st->leftover < poly1305_block_size) - return; - poly1305_blocks(st, st->buffer, poly1305_block_size); - st->leftover = 0; - } - - /* process full blocks */ - if (bytes >= poly1305_block_size) { - size_t want = (bytes & ~(poly1305_block_size - 1)); - poly1305_blocks(st, m, want); - m += want; - bytes -= want; - } - - /* store leftover */ - if (bytes) { - for (i = 0; i < bytes; i++) - st->buffer[st->leftover + i] = m[i]; - st->leftover += bytes; - } -} - -void -poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]) { - poly1305_context ctx; - poly1305_init(&ctx, key); - poly1305_update(&ctx, m, bytes); - poly1305_finish(&ctx, mac); -} - -int -poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]) { - size_t i; - unsigned int dif = 0; - for (i = 0; i < 16; i++) - dif |= (mac1[i] ^ mac2[i]); - dif = (dif - 1) >> ((sizeof(unsigned int) * 8) - 1); - return (dif & 1); -} - - -/* test a few basic operations */ -int -poly1305_power_on_self_test(void) { - /* example from nacl */ - static const unsigned char nacl_key[32] = { - 0xee,0xa6,0xa7,0x25,0x1c,0x1e,0x72,0x91, - 0x6d,0x11,0xc2,0xcb,0x21,0x4d,0x3c,0x25, - 0x25,0x39,0x12,0x1d,0x8e,0x23,0x4e,0x65, - 0x2d,0x65,0x1f,0xa4,0xc8,0xcf,0xf8,0x80 - }; - - static const unsigned char nacl_msg[131] = { - 0x8e,0x99,0x3b,0x9f,0x48,0x68,0x12,0x73, - 0xc2,0x96,0x50,0xba,0x32,0xfc,0x76,0xce, - 0x48,0x33,0x2e,0xa7,0x16,0x4d,0x96,0xa4, - 0x47,0x6f,0xb8,0xc5,0x31,0xa1,0x18,0x6a, - 0xc0,0xdf,0xc1,0x7c,0x98,0xdc,0xe8,0x7b, - 0x4d,0xa7,0xf0,0x11,0xec,0x48,0xc9,0x72, - 0x71,0xd2,0xc2,0x0f,0x9b,0x92,0x8f,0xe2, - 0x27,0x0d,0x6f,0xb8,0x63,0xd5,0x17,0x38, - 0xb4,0x8e,0xee,0xe3,0x14,0xa7,0xcc,0x8a, - 0xb9,0x32,0x16,0x45,0x48,0xe5,0x26,0xae, - 0x90,0x22,0x43,0x68,0x51,0x7a,0xcf,0xea, - 0xbd,0x6b,0xb3,0x73,0x2b,0xc0,0xe9,0xda, - 0x99,0x83,0x2b,0x61,0xca,0x01,0xb6,0xde, - 0x56,0x24,0x4a,0x9e,0x88,0xd5,0xf9,0xb3, - 0x79,0x73,0xf6,0x22,0xa4,0x3d,0x14,0xa6, - 0x59,0x9b,0x1f,0x65,0x4c,0xb4,0x5a,0x74, - 0xe3,0x55,0xa5 - }; - - static const unsigned char nacl_mac[16] = { - 0xf3,0xff,0xc7,0x70,0x3f,0x94,0x00,0xe5, - 0x2a,0x7d,0xfb,0x4b,0x3d,0x33,0x05,0xd9 - }; - - /* generates a final value of (2^130 - 2) == 3 */ - static const unsigned char wrap_key[32] = { - 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - }; - - static const unsigned char wrap_msg[16] = { - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff - }; - - static const unsigned char wrap_mac[16] = { - 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - }; - - /* - mac of the macs of messages of length 0 to 256, where the key and messages - have all their values set to the length - */ - static const unsigned char total_key[32] = { - 0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0xff,0xfe,0xfd,0xfc,0xfb,0xfa,0xf9, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff - }; - - static const unsigned char total_mac[16] = { - 0x64,0xaf,0xe2,0xe8,0xd6,0xad,0x7b,0xbd, - 0xd2,0x87,0xf9,0x7c,0x44,0x62,0x3d,0x39 - }; - - poly1305_context ctx; - poly1305_context total_ctx; - unsigned char all_key[32]; - unsigned char all_msg[256]; - unsigned char mac[16]; - size_t i, j; - int result = 1; - - for (i = 0; i < sizeof(mac); i++) - mac[i] = 0; - poly1305_auth(mac, nacl_msg, sizeof(nacl_msg), nacl_key); - result &= poly1305_verify(nacl_mac, mac); - - for (i = 0; i < sizeof(mac); i++) - mac[i] = 0; - poly1305_init(&ctx, nacl_key); - poly1305_update(&ctx, nacl_msg + 0, 32); - poly1305_update(&ctx, nacl_msg + 32, 64); - poly1305_update(&ctx, nacl_msg + 96, 16); - poly1305_update(&ctx, nacl_msg + 112, 8); - poly1305_update(&ctx, nacl_msg + 120, 4); - poly1305_update(&ctx, nacl_msg + 124, 2); - poly1305_update(&ctx, nacl_msg + 126, 1); - poly1305_update(&ctx, nacl_msg + 127, 1); - poly1305_update(&ctx, nacl_msg + 128, 1); - poly1305_update(&ctx, nacl_msg + 129, 1); - poly1305_update(&ctx, nacl_msg + 130, 1); - poly1305_finish(&ctx, mac); - result &= poly1305_verify(nacl_mac, mac); - - for (i = 0; i < sizeof(mac); i++) - mac[i] = 0; - poly1305_auth(mac, wrap_msg, sizeof(wrap_msg), wrap_key); - result &= poly1305_verify(wrap_mac, mac); - - poly1305_init(&total_ctx, total_key); - for (i = 0; i < 256; i++) { - /* set key and message to 'i,i,i..' */ - for (j = 0; j < sizeof(all_key); j++) - all_key[j] = i; - for (j = 0; j < i; j++) - all_msg[j] = i; - poly1305_auth(mac, all_msg, i, all_key); - poly1305_update(&total_ctx, mac, 16); - } - poly1305_finish(&total_ctx, mac); - result &= poly1305_verify(total_mac, mac); - - return result; -} diff --git a/third_party/ti/devices/cc26x0/driverlib/sw_poly1305-donna.h b/third_party/ti/devices/cc26x0/driverlib/sw_poly1305-donna.h deleted file mode 100644 index 2c91e4a47..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/sw_poly1305-donna.h +++ /dev/null @@ -1,25 +0,0 @@ -/****************************************************************************** -* Filename: sw_poly1305-donna.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ - -#ifndef POLY1305_DONNA_H -#define POLY1305_DONNA_H - -#include - -typedef struct { - size_t aligner; - unsigned char opaque[136]; -} poly1305_context; - -void poly1305_init(poly1305_context *ctx, const unsigned char key[32]); -void poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes); -void poly1305_finish(poly1305_context *ctx, unsigned char mac[16]); -void poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]); - -int poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]); -int poly1305_power_on_self_test(void); - -#endif /* POLY1305_DONNA_H */ diff --git a/third_party/ti/devices/cc26x0/driverlib/sys_ctrl.c b/third_party/ti/devices/cc26x0/driverlib/sys_ctrl.c deleted file mode 100644 index c2cc93629..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/sys_ctrl.c +++ /dev/null @@ -1,422 +0,0 @@ -/****************************************************************************** -* Filename: sys_ctrl.c -* Revised: 2017-08-02 14:52:20 +0200 (Wed, 02 Aug 2017) -* Revision: 49471 -* -* Description: Driver for the System Control. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -// Hardware headers -#include "../inc/hw_types.h" -#include "../inc/hw_ccfg.h" -// Driverlib headers -#include "aon_batmon.h" -#include "sys_ctrl.h" -#include "setup_rom.h" - - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef SysCtrlSetRechargeBeforePowerDown - #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown - #undef SysCtrlAdjustRechargeAfterPowerDown - #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown - #undef SysCtrl_DCDC_VoltageConditionalControl - #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl - #undef SysCtrlResetSourceGet - #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet -#endif - -//***************************************************************************** -// -// Recharge calculator defines and globals -// -//***************************************************************************** - -#define PD_STATE_CACHE_RET 1 -#define PD_STATE_RFMEM_RET 2 -#define PD_STATE_XOSC_LPM 4 -#define PD_STATE_EXT_REG_MODE 8 - -typedef struct { - uint32_t pdTime ; - uint16_t pdRechargePeriod ; - uint8_t pdState ; - int8_t pdTemp ; -} PowerQualGlobals_t; - -static PowerQualGlobals_t powerQualGlobals; - - -//***************************************************************************** -// -// SysCtrlSetRechargeBeforePowerDown( xoscPowerMode ) -// -//***************************************************************************** -void -SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ) -{ - int32_t curTemp ; - int32_t shiftedTemp ; - int32_t deltaVddrSleepTrim ; - int32_t vddrTrimSleep ; - int32_t vddrTrimActve ; - int32_t diffVddrActiveSleep ; - uint32_t ccfg_ModeConfReg ; - uint32_t curState ; - uint32_t prcmRamRetention ; - uint32_t di ; - uint32_t dii ; - uint32_t ti ; - uint32_t cd ; - uint32_t cl ; - uint32_t load ; - uint32_t k ; - uint32_t vddrCap ; - uint32_t newRechargePeriod ; - uint32_t perE ; - uint32_t perM ; - const uint32_t * pLookupTable ; - - // If external regulator mode we shall: - // - Disable adaptive recharge (bit[31]=0) in AON_WUC_O_RECHARGECFG - // - Set recharge period to approximately 500 mS (perM=31, perE=5 => 0xFD) - // - Make sure you get a recalculation if leaving external regulator mode by setting powerQualGlobals.pdState accordingly - if ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) { - powerQualGlobals.pdState = PD_STATE_EXT_REG_MODE; - HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG ) = 0x00A4FDFD; - return; - } - - //--- Spec. point 1 --- - curTemp = AONBatMonTemperatureGetDegC(); - curState = 0; - - // read the MODE_CONF register in CCFG - ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); - // Get VDDR_TRIM_SLEEP_DELTA + 1 (sign extended) - deltaVddrSleepTrim = ((((int32_t) ccfg_ModeConfReg ) - << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S )) - >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )) + 1; - // Do temperature compensation if enabled - if (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC ) == 0 ) { - int32_t tcDelta = ( 62 - curTemp ) >> 3; - if ( tcDelta > 8 ) tcDelta = 8; - if ( tcDelta > deltaVddrSleepTrim ) deltaVddrSleepTrim = tcDelta; - } - { - vddrTrimSleep = SetupSignExtendVddrTrimValue(( - HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) & - FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M ) >> - FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S ) ; - vddrTrimActve = SetupSignExtendVddrTrimValue(( - HWREG( FCFG1_BASE + FCFG1_O_SHDW_ANA_TRIM ) & - FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M ) >> - FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S ) ; - } - vddrTrimSleep += deltaVddrSleepTrim; - if ( vddrTrimSleep > 21 ) vddrTrimSleep = 21; - if ( vddrTrimSleep < -10 ) vddrTrimSleep = -10; - // Write adjusted value using MASKED write (MASK8) - HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL1 * 2 )) = (( ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M << 8 ) | - (( vddrTrimSleep << ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S ) & ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M )); - - prcmRamRetention = HWREG( PRCM_BASE + PRCM_O_RAMRETEN ); - if ( prcmRamRetention & PRCM_RAMRETEN_VIMS_M ) { - curState |= PD_STATE_CACHE_RET; - } - if ( prcmRamRetention & PRCM_RAMRETEN_RFC ) { - curState |= PD_STATE_RFMEM_RET; - } - if ( xoscPowerMode != XOSC_IN_HIGH_POWER_MODE ) { - curState |= PD_STATE_XOSC_LPM; - } - - //--- Spec. point 2 --- - if ((( curTemp - powerQualGlobals.pdTemp ) >= 5 ) || ( curState != powerQualGlobals.pdState )) { - //--- Spec. point 3 --- - shiftedTemp = curTemp - 15; - - //--- Spec point 4 --- - //4. Check for external VDDR load option (may not be supported): ext_load = (VDDR_EXT_LOAD=0 in CCFG) - // Currently not implementing external load handling - // if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) { - // } - - pLookupTable = (uint32_t *)( FCFG1_BASE + FCFG1_O_PWD_CURR_20C ); - - //--- Spec point 5 --- - di = 0; - ti = 0; - if ( shiftedTemp >= 0 ) { - //--- Spec point 5.a --- - shiftedTemp += ( shiftedTemp << 4 ); - - //--- Spec point 5.b --- - ti = ( shiftedTemp >> 8 ); - if ( ti > 7 ) { - ti = 7; - } - dii = ti; - if ( dii > 6 ) { - dii = 6; - } - - //--- Spec point 5.c --- - cd = pLookupTable[ dii + 1 ] - pLookupTable[ dii ]; - - //--- Spec point 5.d --- - di = cd & 0xFF; - - //--- Spec point 5.e --- - if ( curState & PD_STATE_XOSC_LPM ) { - di += (( cd >> 8 ) & 0xFF ); - } - if ( curState & PD_STATE_RFMEM_RET ) { - di += (( cd >> 16 ) & 0xFF ); - } - if ( curState & PD_STATE_CACHE_RET ) { - di += (( cd >> 24 ) & 0xFF ); - } - - //--- Spec point 5.f --- - // Currently not implementing external load handling - } - - //--- Spec. point 6 --- - cl = pLookupTable[ ti ]; - - //--- Spec. point 7 --- - load = cl & 0xFF; - - //--- Spec. point 8 --- - if ( curState & PD_STATE_XOSC_LPM ) { - load += (( cl >> 8 ) & 0xFF ); - } - if ( curState & PD_STATE_RFMEM_RET ) { - load += (( cl >> 16 ) & 0xFF ); - } - if ( curState & PD_STATE_CACHE_RET ) { - load += (( cl >> 24 ) & 0xFF ); - } - - //--- Spec. point 9 --- - load += ((( di * ( shiftedTemp - ( ti << 8 ))) + 128 ) >> 8 ); - - // Currently not implementing external load handling - // if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) { - //--- Spec. point 10 --- - // } else { - //--- Spec. point 11 --- - diffVddrActiveSleep = ( vddrTrimActve - vddrTrimSleep ); - if ( diffVddrActiveSleep < 1 ) diffVddrActiveSleep = 1; - k = ( diffVddrActiveSleep * 52 ); - // } - - //--- Spec. point 12 --- - - vddrCap = ( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_CAP_M ) >> CCFG_MODE_CONF_VDDR_CAP_S; - newRechargePeriod = ( vddrCap * k ) / load; - if ( newRechargePeriod > 0xFFFF ) { - newRechargePeriod = 0xFFFF; - } - powerQualGlobals.pdRechargePeriod = newRechargePeriod; - - //--- Spec. point 13 --- - if ( curTemp > 127 ) curTemp = 127; - if ( curTemp < -128 ) curTemp = -128; - powerQualGlobals.pdTemp = curTemp; - powerQualGlobals.pdState = curState; - } - - powerQualGlobals.pdTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); - - // Calculate PER_E and PER_M (based on powerQualGlobals.pdRechargePeriod) - // Round downwards but make sure PER_E=0 and PER_M=1 is the minimum possible setting. - // (assuming that powerQualGlobals.pdRechargePeriod always are <= 0xFFFF) - perE = 0; - perM = powerQualGlobals.pdRechargePeriod; - if ( perM < 31 ) { - perM = 31; - powerQualGlobals.pdRechargePeriod = 31; - } - while ( perM > 511 ) { - perM >>= 1; - perE += 1; - } - perM = ( perM - 15 ) >> 4; - - HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG ) = - ( 0x80A4E700 ) | - ( perM << AON_WUC_RECHARGECFG_PER_M_S ) | - ( perE << AON_WUC_RECHARGECFG_PER_E_S ) ; - HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) = 0; -} - - -//***************************************************************************** -// -// SysCtrlAdjustRechargeAfterPowerDown() -// -//***************************************************************************** -void -SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ) -{ - int32_t curTemp ; - uint32_t longestRechargePeriod ; - uint32_t deltaTime ; - uint32_t newRechargePeriod ; - - //--- Spec. point 2 --- - longestRechargePeriod = ( HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) & - AON_WUC_RECHARGESTAT_MAX_USED_PER_M ) >> - AON_WUC_RECHARGESTAT_MAX_USED_PER_S ; - - if ( longestRechargePeriod != 0 ) { - //--- Spec. changed (originaly point 1) --- - curTemp = AONBatMonTemperatureGetDegC(); - if ( curTemp < powerQualGlobals.pdTemp ) { - if ( curTemp < -128 ) { - curTemp = -128; - } - powerQualGlobals.pdTemp = curTemp; - } - - // Add some margin between the longest previous recharge period and the - // next initial recharge period. Since it is a fixed margin, it will have a - // higher impact as a fraction of the converged recharge period at higher temperatures - // where it is needed more due to higher leakage. - if (longestRechargePeriod > vddrRechargeMargin) { - longestRechargePeriod -= vddrRechargeMargin; - } - else { - longestRechargePeriod = 1; - } - - //--- Spec. point 4 --- - if ( longestRechargePeriod < powerQualGlobals.pdRechargePeriod ) { - powerQualGlobals.pdRechargePeriod = longestRechargePeriod; - } else { - //--- Spec. point 5 --- - deltaTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ) - powerQualGlobals.pdTime + 2; - if ( deltaTime > 31 ) { - deltaTime = 31; - } - newRechargePeriod = powerQualGlobals.pdRechargePeriod + (( longestRechargePeriod - powerQualGlobals.pdRechargePeriod ) >> (deltaTime>>1)); - if ( newRechargePeriod > 0xFFFF ) { - newRechargePeriod = 0xFFFF; - } - powerQualGlobals.pdRechargePeriod = newRechargePeriod; - } - } -} - - -//***************************************************************************** -// -// SysCtrl_DCDC_VoltageConditionalControl() -// -//***************************************************************************** -void -SysCtrl_DCDC_VoltageConditionalControl( void ) -{ - uint32_t batThreshold ; // Fractional format with 8 fractional bits. - uint32_t aonBatmonBat ; // Fractional format with 8 fractional bits. - uint32_t ccfg_ModeConfReg ; // Holds a copy of the CCFG_O_MODE_CONF register. - uint32_t aonSysctlPwrctl ; // Reflect whats read/written to the AON_SYSCTL_O_PWRCTL register. - - // We could potentially call this function before any battery voltage measurement - // is made/available. In that case we must make sure that we do not turn off the DCDC. - // This can be done by doing nothing as long as the battery voltage is 0 (Since the - // reset value of the battery voltage register is 0). - aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT ); - if ( aonBatmonBat != 0 ) { - // Check if Voltage Conditional Control is enabled - // It is enabled if all the following are true: - // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero). - // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 ) - // - Not in external regulator mode ( EXT_REG_MODE == 0 ) - ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); - - if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) || - (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) && - (( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) & AON_SYSCTL_PWRCTL_EXT_REG_MODE ) == 0 ) && - (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) ) - { - aonSysctlPwrctl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ); - batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & - CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >> - CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 ); - - if ( aonSysctlPwrctl & ( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M )) { - // DCDC is ON, check if it should be switched off - if ( aonBatmonBat < batThreshold ) { - aonSysctlPwrctl &= ~( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M ); - - HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl; - } - } else { - // DCDC is OFF, check if it should be switched on - if ( aonBatmonBat > batThreshold ) { - if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_EN_M ; - if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M ; - - HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl; - } - } - } - } -} - - -//***************************************************************************** -// -// SysCtrlResetSourceGet() -// -//***************************************************************************** -uint32_t -SysCtrlResetSourceGet( void ) -{ - if ( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & AON_SYSCTL_RESETCTL_WU_FROM_SD_M ) { - return ( RSTSRC_WAKEUP_FROM_SHUTDOWN ); - } else { - return (( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & - AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> - AON_SYSCTL_RESETCTL_RESET_SRC_S ) ; - } -} diff --git a/third_party/ti/devices/cc26x0/driverlib/sys_ctrl.h b/third_party/ti/devices/cc26x0/driverlib/sys_ctrl.h deleted file mode 100644 index 1898e4229..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/sys_ctrl.h +++ /dev/null @@ -1,410 +0,0 @@ -/****************************************************************************** -* Filename: sys_ctrl.h -* Revised: 2017-08-02 14:52:20 +0200 (Wed, 02 Aug 2017) -* Revision: 49471 -* -* Description: Defines and prototypes for the System Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup sysctrl_api -//! @{ -// -//***************************************************************************** - -#ifndef __SYSCTRL_H__ -#define __SYSCTRL_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_sysctl.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_nvic.h" -#include "../inc/hw_aon_wuc.h" -#include "../inc/hw_aux_wuc.h" -#include "../inc/hw_aon_ioc.h" -#include "../inc/hw_ddi_0_osc.h" -#include "../inc/hw_rfc_pwr.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_adi_3_refsys.h" -#include "../inc/hw_aon_sysctl.h" -#include "../inc/hw_aon_rtc.h" -#include "../inc/hw_fcfg1.h" -#include "interrupt.h" -#include "debug.h" -#include "pwr_ctrl.h" -#include "osc.h" -#include "prcm.h" -#include "aux_wuc.h" -#include "aon_wuc.h" -#include "adi.h" -#include "ddi.h" -#include "cpu.h" -#include "vims.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown - #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown - #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl - #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet -#endif - -//***************************************************************************** -// -// Defines for the settings of the main XOSC -// -//***************************************************************************** -#define SYSCTRL_SYSBUS_ON 0x00000001 -#define SYSCTRL_SYSBUS_OFF 0x00000000 - -//***************************************************************************** -// -// Defines for the different power modes of the System CPU -// -//***************************************************************************** -#define CPU_RUN 0x00000000 -#define CPU_SLEEP 0x00000001 -#define CPU_DEEP_SLEEP 0x00000002 - -//***************************************************************************** -// -// Defines for SysCtrlSetRechargeBeforePowerDown -// -//***************************************************************************** -#define XOSC_IN_HIGH_POWER_MODE 0 // When xosc_hf is in HIGH_POWER_XOSC -#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Get the CPU core clock frequency. -//! -//! Use this function to get the current clock frequency for the CPU. -//! -//! The CPU can run from 48 MHz and down to 750kHz. The frequency is defined -//! by the combined division factor of the SYSBUS and the CPU clock divider. -//! -//! \return Returns the current CPU core clock frequency. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -SysCtrlClockGet( void ) -{ - // Return fixed clock speed - return( GET_MCU_CLOCK ); -} - -//***************************************************************************** -// -//! \brief Sync all accesses to the AON register interface. -//! -//! When this function returns, all writes to the AON register interface are -//! guaranteed to have propagated to hardware. The function will return -//! immediately if no AON writes are pending; otherwise, it will wait for the next -//! AON clock before returning. -//! -//! \return None -//! -//! \sa \ref SysCtrlAonUpdate() -// -//***************************************************************************** -__STATIC_INLINE void -SysCtrlAonSync(void) -{ - // Sync the AON interface - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); -} - -//***************************************************************************** -// -//! \brief Update all interfaces to AON. -//! -//! When this function returns, at least 1 clock cycle has progressed on the -//! AON domain, so that any outstanding updates to and from the AON interface -//! is guaranteed to be in sync. -//! -//! \note This function should primarily be used after wakeup from sleep modes, -//! as it will guarantee that all shadow registers on the AON interface are updated -//! before reading any AON registers from the MCU domain. If a write has been -//! done to the AON interface it is sufficient to call the \ref SysCtrlAonSync(). -//! -//! \return None -//! -//! \sa \ref SysCtrlAonSync() -// -//***************************************************************************** -__STATIC_INLINE void -SysCtrlAonUpdate(void) -{ - // Force a clock cycle on the AON interface to guarantee all registers are - // in sync. - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1; - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); -} - - -//***************************************************************************** -// -//! \brief Set Recharge values before entering Power Down. -//! -//! This function shall be called just before entering Power Down. -//! It calculates an optimal and safe recharge setting of the adaptive recharge -//! controller. The results of previous setting are also taken into account. -//! -//! \note In order to make sure that the register writes are completed, \ref SysCtrlAonSync() -//! must be called before entering standby/power down. This is not done internally -//! in this function due to two reasons: -//! - 1) There might be other register writes that must be synchronized as well. -//! - 2) It is possible to save some time by doing other things before calling -//! \ref SysCtrlAonSync() since this call will not return before there are no -//! outstanding write requests between MCU and AON. -//! -//! \param xoscPowerMode (typically running in XOSC_IN_HIGH_POWER_MODE all the time). -//! - \ref XOSC_IN_HIGH_POWER_MODE : When xosc_hf is in HIGH_POWER_XOSC. -//! - \ref XOSC_IN_LOW_POWER_MODE : When xosc_hf is in LOW_POWER_XOSC. -//! -//! \return None -// -//***************************************************************************** -extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); - - -///***************************************************************************** -// -//! \brief Adjust Recharge calculations to be used next. -//! -//! This function shall be called just after returning from Power Down. -//! -//! Reads the results from the adaptive recharge controller and current chip -//! temperature. This is used as additional information when calculating -//! optimal recharge controller settings next time (When -//! \ref SysCtrlSetRechargeBeforePowerDown() is called next time). -//! -//! \param vddrRechargeMargin margin in SCLK_LF periods to subtract from -//! previous longest recharge period experienced while in standby. -//! -//! \note -//! Special care must be taken to make sure that the AON registers read are -//! updated after the wakeup. Writing to an AON register and then calling -//! \ref SysCtrlAonSync() will handle this. -//! -//! \return None -// -//***************************************************************************** -extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); - - -//***************************************************************************** -// -//! \brief Turns DCDC on or off depending of what is considered to be optimal usage. -//! -//! This function controls the DCDC only if both the following CCFG settings are \c true: -//! - DCDC is configured to be used. -//! - Alternative DCDC settings are defined and enabled. -//! -//! The DCDC is configured in accordance to the CCFG settings when turned on. -//! -//! This function should be called periodically. -//! -//! \return None -// -//***************************************************************************** -extern void SysCtrl_DCDC_VoltageConditionalControl( void ); - - -//***************************************************************************** -// \name Return values from calling SysCtrlResetSourceGet() -//@{ -//***************************************************************************** -#define RSTSRC_PWR_ON (( AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_PIN_RESET (( AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_VDDS_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_VDDR_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_CLK_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_SYSRESET (( AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_WARMRESET (( AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_WAKEUP_FROM_SHUTDOWN ((( AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) + 1 ) -//@} - -//***************************************************************************** -// -//! \brief Returns last reset source (including "wakeup from shutdown"). -//! -//! \return Returns one of the RSTSRC_ defines. -// -//***************************************************************************** -extern uint32_t SysCtrlResetSourceGet( void ); - -//***************************************************************************** -// -//! \brief Perform a full system reset. -//! -//! \return The chip will reset and hence never return from this call. -// -//***************************************************************************** -__STATIC_INLINE void -SysCtrlSystemReset( void ) -{ - // Disable CPU interrupts - CPUcpsid(); - // Write reset register - HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_SYSRESET_BITN ) = 1; - // Finally, wait until the above write propagates - while ( 1 ) { - // Do nothing, just wait for the reset (and never return from here) - } -} - -//***************************************************************************** -// -//! \brief Enables reset if OSC clock loss event is asserted. -//! -//! Clock loss circuit in analog domain must be enabled as well in order to -//! actually enable for a clock loss reset to occur -//! \ref OSCClockLossEventEnable(). -//! -//! \note This function shall typically not be called because the clock loss -//! reset functionality is controlled by the boot code (a factory configuration -//! defines whether it is set or not). -//! -//! \return None -//! -//! \sa \ref SysCtrlClockLossResetDisable(), \ref OSCClockLossEventEnable() -// -//***************************************************************************** -__STATIC_INLINE void -SysCtrlClockLossResetEnable(void) -{ - // Set clock loss enable bit in AON_SYSCTRL using bit banding - HWREGBITW(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disables reset due to OSC clock loss event. -//! -//! \note This function shall typically not be called because the clock loss -//! reset functionality is controlled by the boot code (a factory configuration -//! defines whether it is set or not). -//! -//! \return None -//! -//! \sa \ref SysCtrlClockLossResetEnable() -// -//***************************************************************************** -__STATIC_INLINE void -SysCtrlClockLossResetDisable(void) -{ - // Clear clock loss enable bit in AON_SYSCTRL using bit banding - HWREGBITW(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SysCtrlSetRechargeBeforePowerDown - #undef SysCtrlSetRechargeBeforePowerDown - #define SysCtrlSetRechargeBeforePowerDown ROM_SysCtrlSetRechargeBeforePowerDown - #endif - #ifdef ROM_SysCtrlAdjustRechargeAfterPowerDown - #undef SysCtrlAdjustRechargeAfterPowerDown - #define SysCtrlAdjustRechargeAfterPowerDown ROM_SysCtrlAdjustRechargeAfterPowerDown - #endif - #ifdef ROM_SysCtrl_DCDC_VoltageConditionalControl - #undef SysCtrl_DCDC_VoltageConditionalControl - #define SysCtrl_DCDC_VoltageConditionalControl ROM_SysCtrl_DCDC_VoltageConditionalControl - #endif - #ifdef ROM_SysCtrlResetSourceGet - #undef SysCtrlResetSourceGet - #define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTRL_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/systick.c b/third_party/ti/devices/cc26x0/driverlib/systick.c deleted file mode 100644 index 6a64e2d63..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/systick.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: systick.c -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Driver for the SysTick timer in NVIC -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "systick.h" - -// See systick.h for implementation diff --git a/third_party/ti/devices/cc26x0/driverlib/systick.h b/third_party/ti/devices/cc26x0/driverlib/systick.h deleted file mode 100644 index a70702c31..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/systick.h +++ /dev/null @@ -1,287 +0,0 @@ -/****************************************************************************** -* Filename: systick.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Prototypes for the SysTick driver. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_cpu_group -//! @{ -//! \addtogroup systick_api -//! @{ -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_ints.h" -#include "../inc/hw_nvic.h" -#include "../inc/hw_types.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// API Functions and Prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Enables the SysTick counter. -//! -//! This will start the SysTick counter. If an interrupt handler has been -//! registered, it will be called when the SysTick counter rolls over. -//! -//! \note Calling this function will cause the SysTick counter to (re)commence -//! counting from its current value. The counter is not automatically reloaded -//! with the period as specified in a previous call to \ref SysTickPeriodSet(). If -//! an immediate reload is required, the NVIC_ST_CURRENT register must be -//! written to force this. Any write to this register clears the SysTick -//! counter to 0 and will cause a reload with the supplied period on the next -//! clock. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SysTickEnable(void) -{ - // Enable SysTick. - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; -} - -//***************************************************************************** -// -//! \brief Disables the SysTick counter. -//! -//! This will stop the SysTick counter. If an interrupt handler has been -//! registered, it will no longer be called until SysTick is restarted. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SysTickDisable(void) -{ - // Disable SysTick. - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the SysTick interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! SysTick interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -SysTickIntRegister(void (*pfnHandler)(void)) -{ - // Register the interrupt handler, returning an error if an error occurs. - IntRegister(INT_SYSTICK, pfnHandler); - - // Enable the SysTick interrupt. - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} - -//***************************************************************************** -// -//! \brief Unregisters the interrupt handler for the SysTick interrupt in the dynamic interrupt table. -//! -//! This function will clear the handler to be called when a SysTick interrupt -//! occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -SysTickIntUnregister(void) -{ - // Disable the SysTick interrupt. - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - - // Unregister the interrupt handler. - IntUnregister(INT_SYSTICK); -} - -//***************************************************************************** -// -//! \brief Enables the SysTick interrupt. -//! -//! This function will enable the SysTick interrupt, allowing it to be -//! reflected to the processor. -//! -//! \note The SysTick interrupt handler does not need to clear the SysTick -//! interrupt source as this is done automatically by NVIC when the interrupt -//! handler is called. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SysTickIntEnable(void) -{ - // Enable the SysTick interrupt. - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} - -//***************************************************************************** -// -//! \brief Disables the SysTick interrupt. -//! -//! This function will disable the SysTick interrupt, preventing it from being -//! reflected to the processor. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SysTickIntDisable(void) -{ - // Disable the SysTick interrupt. - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); -} - -//***************************************************************************** -// -//! \brief Sets the period of the SysTick counter. -//! -//! This function sets the rate at which the SysTick counter wraps; this -//! equals to the number of processor clocks between interrupts. -//! -//! \note Calling this function does not cause the SysTick counter to reload -//! immediately. If an immediate reload is required, the NVIC_ST_CURRENT -//! register must be written. Any write to this register clears the SysTick -//! counter to 0 and will cause a reload with the \c ui32Period supplied here -//! on the next clock after the SysTick is enabled. -//! -//! \param ui32Period is the number of clock ticks in each period of the -//! SysTick counter; must be between 1 and 16,777,216 (0x1000000), both included. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SysTickPeriodSet(uint32_t ui32Period) -{ - // Check the arguments. - ASSERT((ui32Period > 0) && (ui32Period <= 16777216)); - - // Set the period of the SysTick counter. - HWREG(NVIC_ST_RELOAD) = ui32Period - 1; -} - -//***************************************************************************** -// -//! \brief Gets the period of the SysTick counter. -//! -//! This function returns the rate at which the SysTick counter wraps; this -//! equals to the number of processor clocks between interrupts. -//! -//! \return Returns the period of the SysTick counter. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -SysTickPeriodGet(void) -{ - // Return the period of the SysTick counter. - return(HWREG(NVIC_ST_RELOAD) + 1); -} - -//***************************************************************************** -// -//! \brief Gets the current value of the SysTick counter. -//! -//! This function returns the current value of the SysTick counter; this will -//! be a value between the (period - 1) and zero, both included. -//! -//! \return Returns the current value of the SysTick counter -// -//***************************************************************************** -__STATIC_INLINE uint32_t -SysTickValueGet(void) -{ - // Return the current value of the SysTick counter. - return(HWREG(NVIC_ST_CURRENT)); -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ - -//***************************************************************************** -// -//! Close the Doxygen group -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/systick_doc.h b/third_party/ti/devices/cc26x0/driverlib/systick_doc.h deleted file mode 100644 index 47a37de3d..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/systick_doc.h +++ /dev/null @@ -1,68 +0,0 @@ -/****************************************************************************** -* Filename: systick_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup systick_api -//! @{ -//! \section sec_systick Introduction -//! -//! The system CPU includes a system timer, SysTick, integrated in the NVIC which provides a simple, 24-bit, -//! clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. -//! When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) on -//! the next clock edge, then decrements on subsequent clocks. -//! -//! The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the -//! SysTick counter stops. -//! -//! When the processor is halted for debugging, the counter does not decrement. -//! -//! \section sec_systick_api API -//! -//! The API functions can be grouped like this: -//! -//! Configuration and status: -//! - \ref SysTickPeriodSet() -//! - \ref SysTickPeriodGet() -//! - \ref SysTickValueGet() -//! -//! Enable and disable: -//! - \ref SysTickEnable() -//! - \ref SysTickDisable() -//! -//! Interrupt configuration: -//! - \ref SysTickIntRegister() -//! - \ref SysTickIntUnregister() -//! - \ref SysTickIntEnable() -//! - \ref SysTickIntDisable() -//! @} diff --git a/third_party/ti/devices/cc26x0/driverlib/timer.c b/third_party/ti/devices/cc26x0/driverlib/timer.c deleted file mode 100644 index 5acc1a632..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/timer.c +++ /dev/null @@ -1,392 +0,0 @@ -/****************************************************************************** -* Filename: timer.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the General Purpose Timer -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "timer.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef TimerConfigure - #define TimerConfigure NOROM_TimerConfigure - #undef TimerLevelControl - #define TimerLevelControl NOROM_TimerLevelControl - #undef TimerStallControl - #define TimerStallControl NOROM_TimerStallControl - #undef TimerWaitOnTriggerControl - #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl - #undef TimerIntRegister - #define TimerIntRegister NOROM_TimerIntRegister - #undef TimerIntUnregister - #define TimerIntUnregister NOROM_TimerIntUnregister - #undef TimerMatchUpdateMode - #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode - #undef TimerIntervalLoadMode - #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode -#endif - -//***************************************************************************** -// -//! \brief Gets the timer interrupt number. -//! -//! Given a timer base address, this function returns the corresponding -//! interrupt number. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! \return Returns a timer interrupt number, or -1 if \c ui32Base is invalid. -// -//***************************************************************************** -static uint32_t -TimerIntNumberGet(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // Loop through the table that maps timer base addresses to interrupt - // numbers. - switch(ui32Base) - { - case GPT0_BASE : - ui32Int = INT_GPT0A; - break; - case GPT1_BASE : - ui32Int = INT_GPT1A; - break; - case GPT2_BASE : - ui32Int = INT_GPT2A; - break; - case GPT3_BASE : - ui32Int = INT_GPT3A; - break; - default : - ui32Int = 0x0; - } - - // Return the interrupt number or (-1) if not base address is not matched. - return (ui32Int); -} - -//***************************************************************************** -// -// Configures the timer(s) -// -//***************************************************************************** -void -TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || - (ui32Config == TIMER_CFG_ONE_SHOT_UP) || - (ui32Config == TIMER_CFG_PERIODIC) || - (ui32Config == TIMER_CFG_PERIODIC_UP) || - ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); - ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || - ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && - (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); - - // Disable the timers. - HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); - - // Set the global timer configuration. - HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; - - // Set the configuration of the A and B timers. Note that the B timer - // configuration is ignored by the hardware in 32-bit modes. - HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; - HWREG(ui32Base + GPT_O_TBMR) = - ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; -} - -//***************************************************************************** -// -// Controls the output level -// -//***************************************************************************** -void -TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the output levels as requested. - ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; - HWREG(ui32Base + GPT_O_CTL) = (bInvert ? - (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : - (HWREG(ui32Base + GPT_O_CTL) & - ~(ui32Timer))); -} - -//***************************************************************************** -// -// Controls the stall handling -// -//***************************************************************************** -void -TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the stall mode. - ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; - HWREG(ui32Base + GPT_O_CTL) = (bStall ? - (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : - (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); -} - -//***************************************************************************** -// -// Controls the wait on trigger handling -// -//***************************************************************************** -void -TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the wait on trigger mode for timer A. - if(ui32Timer & TIMER_A) - { - if(bWait) - { - HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; - } - else - { - HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); - } - } - - // Set the wait on trigger mode for timer B. - if(ui32Timer & TIMER_B) - { - if(bWait) - { - HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; - } - else - { - HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); - } - } -} - -//***************************************************************************** -// -// Registers an interrupt handler for the timer interrupt -// -//***************************************************************************** -void -TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Get the interrupt number for this timer module. - ui32Int = TimerIntNumberGet(ui32Base); - - // Register an interrupt handler for timer A if requested. - if(ui32Timer & TIMER_A) - { - // Register the interrupt handler. - IntRegister(ui32Int, pfnHandler); - - // Enable the interrupt. - IntEnable(ui32Int); - } - - // Register an interrupt handler for timer B if requested. - if(ui32Timer & TIMER_B) - { - // Register the interrupt handler. - IntRegister(ui32Int + 1, pfnHandler); - - // Enable the interrupt. - IntEnable(ui32Int + 1); - } -} - -//***************************************************************************** -// -// Unregisters an interrupt handler for the timer interrupt -// -//***************************************************************************** -void -TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer) -{ - uint32_t ui32Int; - - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Get the interrupt number for this timer module. - ui32Int = TimerIntNumberGet(ui32Base); - - // Unregister the interrupt handler for timer A if requested. - if(ui32Timer & TIMER_A) - { - // Disable the interrupt. - IntDisable(ui32Int); - - // Unregister the interrupt handler. - IntUnregister(ui32Int); - } - - // Unregister the interrupt handler for timer B if requested. - if(ui32Timer & TIMER_B) - { - // Disable the interrupt. - IntDisable(ui32Int + 1); - - // Unregister the interrupt handler. - IntUnregister(ui32Int + 1); - } -} - -//***************************************************************************** -// -// Sets the Match Register Update mode -// -//***************************************************************************** -void -TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) -{ - // Check the arguments - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); - ASSERT((ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) || (ui32Mode == TIMER_MATCHUPDATE_TIMEOUT)); - - // Set mode for timer A - if(ui32Timer & TIMER_A) - { - if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) - { - HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAMRSU); - } - else - { - HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAMRSU; - } - } - - // Set mode for timer B - if(ui32Timer & TIMER_B) - { - if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) - { - HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBMRSU); - } - else - { - HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBMRSU; - } - } -} - -//***************************************************************************** -// -// Sets the Interval Load mode -// -//***************************************************************************** -void -TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) -{ - // Check the arguments - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); - ASSERT((ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) || (ui32Mode == TIMER_INTERVALLOAD_TIMEOUT)); - - // Set mode for timer A - if(ui32Timer & TIMER_A) - { - if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) - { - HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAILD); - } - else - { - HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAILD; - } - } - - // Set mode for timer B - if(ui32Timer & TIMER_B) - { - if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) - { - HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBILD); - } - else - { - HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBILD; - } - } -} diff --git a/third_party/ti/devices/cc26x0/driverlib/timer.h b/third_party/ti/devices/cc26x0/driverlib/timer.h deleted file mode 100644 index d34e6ce32..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/timer.h +++ /dev/null @@ -1,1176 +0,0 @@ -/****************************************************************************** -* Filename: timer.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//**************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup timer_api -//! @{ -// -//**************************************************************************** - -#ifndef __GPT_H__ -#define __GPT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_ints.h" -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_gpt.h" -#include "interrupt.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define TimerConfigure NOROM_TimerConfigure - #define TimerLevelControl NOROM_TimerLevelControl - #define TimerStallControl NOROM_TimerStallControl - #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl - #define TimerIntRegister NOROM_TimerIntRegister - #define TimerIntUnregister NOROM_TimerIntUnregister - #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode - #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ui32Config parameter. -// -//***************************************************************************** -#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer -#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer -#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer -#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer -#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers -#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer -#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer -#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer -#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer -#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer -#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer -#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ui32IntFlags parameter, and returned from -// TimerIntStatus. -// -//***************************************************************************** -#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt -#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt -#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ui32Event parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ui32Timer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000FF // Timer A -#define TIMER_B 0x0000FF00 // Timer B -#define TIMER_BOTH 0x0000FFFF // Timer Both - -//***************************************************************************** -// -// Values that can be passed to GPTSynchronize as the ui32Timers parameter -// -//***************************************************************************** -#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A -#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B -#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A -#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B -#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A -#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B -#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A -#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B - -//***************************************************************************** -// -// Values that can be passed to TimerMatchUpdateMode -// -//***************************************************************************** -#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle -#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout - -//***************************************************************************** -// -// Values that can be passed to TimerIntervalLoad -// -//***************************************************************************** -#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle -#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Checks a timer base address. -//! -//! This function determines if a timer module base address is valid. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -TimerBaseValid(uint32_t ui32Base) -{ - return((ui32Base == GPT0_BASE) || (ui32Base == GPT1_BASE) || - (ui32Base == GPT2_BASE) || (ui32Base == GPT3_BASE)); -} -#endif - -//***************************************************************************** -// -//! \brief Enables the timer(s). -//! -//! This function enables operation of the timer module. The timer must be -//! configured before it is enabled. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to enable. Must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Enable the timer(s) module. - HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN); -} - -//***************************************************************************** -// -//! \brief Disables the timer(s). -//! -//! This function disables operation of the timer module. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to disable. Must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Disable the timer module. - HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer & - (GPT_CTL_TAEN | GPT_CTL_TBEN)); -} - -//***************************************************************************** -// -//! \brief Configures the timer(s). -//! -//! This function configures the operating mode of the timer(s). The timer -//! module is disabled before being configured and is left in the disabled -//! state. -//! -//! The timers are comprised of two 16-bit timers that can -//! operate independently or be concatenated to form a 32-bit timer. -//! -//! \note If the timers are used independently the length of timer can be -//! extended to 24 bit by use of an 8 bit prescale register set using -//! \ref TimerPrescaleSet(). -//! -//! When configuring for full-width timer \c ui32Config is set -//! as one of the following values: -//! - \ref TIMER_CFG_ONE_SHOT : Full-width one-shot timer. -//! - \ref TIMER_CFG_ONE_SHOT_UP : Full-width one-shot timer that counts up -//! instead of down. -//! - \ref TIMER_CFG_PERIODIC : Full-width periodic timer. -//! - \ref TIMER_CFG_PERIODIC_UP : Full-width periodic timer that counts up -//! instead of down. -//! -//! When configuring for a pair of half-width timers, each timer is separately -//! configured. The timers are configured by setting \c ui32Config to -//! the bitwise OR of one of each of the following three: -//! - Use half-width timers: -//! - \ref TIMER_CFG_SPLIT_PAIR -//! - Timer A: -//! - \ref TIMER_CFG_A_ONE_SHOT : Half-width one-shot timer -//! - \ref TIMER_CFG_A_ONE_SHOT_UP : Half-width one-shot timer that counts up -//! instead of down. -//! - \ref TIMER_CFG_A_PERIODIC : Half-width periodic timer -//! - \ref TIMER_CFG_A_PERIODIC_UP : Half-width periodic timer that counts up -//! instead of down. -//! - \ref TIMER_CFG_A_CAP_COUNT : Half-width edge count capture -//! - \ref TIMER_CFG_A_CAP_COUNT_UP : Half-width edge count capture that counts -//! up instead of down. -//! - \ref TIMER_CFG_A_CAP_TIME : Half-width edge time capture -//! - \ref TIMER_CFG_A_CAP_TIME_UP : Half-width edge time capture that counts up -//! instead of down. -//! - \ref TIMER_CFG_A_PWM : Half-width PWM output -//! - Timer B: -//! - Same as Timer A but using TIMER_CFG_B_* instead. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Config is the configuration for the timer. -//! -//! \return None -// -//***************************************************************************** -extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); - -//***************************************************************************** -// -//! \brief Controls the output level. -//! -//! This function configures the PWM output level for the specified timer. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust. Must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param bInvert specifies the output level. -//! - \c true : Timer's output is active low. -//! - \c false : Timer's output is active high. -//! -//! \return None -// -//***************************************************************************** -extern void TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, - bool bInvert); - -//***************************************************************************** -// -//! \brief Controls the event type. -//! -//! This function configures the signal edge(s) that triggers the timer when -//! in capture mode. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Event specifies the type of event; must be one of: -//! - \ref TIMER_EVENT_POS_EDGE -//! - \ref TIMER_EVENT_NEG_EDGE -//! - \ref TIMER_EVENT_BOTH_EDGES -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerEventControl(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Event) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the event type. - ui32Timer &= GPT_CTL_TAEVENT_M | GPT_CTL_TBEVENT_M; - HWREG(ui32Base + GPT_O_CTL) = ((HWREG(ui32Base + GPT_O_CTL) & ~ui32Timer) | - (ui32Event & ui32Timer)); -} - -//***************************************************************************** -// -//! \brief Controls the stall handling. -//! -//! This function controls the stall response for the specified timer. If the -//! \e bStall parameter is \b true, then the timer stops counting if the -//! processor enters debug mode; otherwise the timer keeps running while in -//! debug mode. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param bStall specifies the response to a stall signal. -//! - \c true : Timer stops counting if the processor enters debug mode. -//! - \c false : Timer keeps running if the processor enters debug mode. -//! -//! \return None -// -//***************************************************************************** -extern void TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, - bool bStall); - -//***************************************************************************** -// -//! \brief Controls the wait on trigger handling. -//! -//! This function controls whether or not a timer waits for a trigger input to -//! start counting. When enabled, the previous timer in the trigger chain must -//! count to its timeout in order for this timer to start counting. Refer to -//! the part's data sheet for a description of the trigger chain. -//! -//! \note This function should not be used for Timer 0A or Wide Timer 0A. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param bWait specifies if the timer should wait for a trigger input. -//! - \c true : Wait for trigger. -//! - \c false : Do not wait for trigger. -//! -//! \return None -// -//***************************************************************************** -extern void TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, - bool bWait); - -//***************************************************************************** -// -//! \brief Set the timer prescale value. -//! -//! This function configures the value of the timer clock prescaler. The -//! prescaler is only operational when in half-width mode and is used to extend -//! the range of the half-width timer modes. -//! -//! When in one-shot or periodic down count modes, \b ui32Value defines the -//! prescaler for the timer counter. When acting as a true prescaler, the -//! prescaler counts down to 0 before the value in timer registers are incremented. -//! -//! In all other individual/split modes, \b ui32Value is a linear extension of -//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes -//! of the 16/32-bit timer. -//! -//! \note Because the prescaler counts down to 0 the timer division ratio equals -//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Value is the timer prescale value which must be between 0 and 255 -//! (both included). -//! - 0 : Timer division ratio = 1 (disable prescaling). -//! - 1 : Timer division ratio = 2. -//! - ... -//! - 255 : Timer division ratio = 256. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - ASSERT(ui32Value < 256); - - // Set the timer A prescaler if requested. - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + GPT_O_TAPR) = ui32Value; - } - - // Set the timer B prescaler if requested. - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + GPT_O_TBPR) = ui32Value; - } -} - -//***************************************************************************** -// -//! \brief Get the timer prescale value. -//! -//! This function gets the value of the timer clock prescaler. The -//! prescaler is only operational when in half-width mode and is used to extend -//! the range of the half-width timer modes. -//! -//! When in one-shot or periodic down count modes, \b ui32Value defines the -//! prescaler for the timer counter. When acting as a true prescaler, the -//! prescaler counts down to 0 before the value in timer registers are incremented. -//! -//! In all other individual/split modes, \b ui32Value is a linear extension of -//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes -//! of the 16/32-bit timer. -//! -//! \note Because the prescaler counts down to 0 the timer division ratio equals -//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! -//! \return Returns the value of the timer prescaler. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Return the appropriate prescale value. - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : - HWREG(ui32Base + GPT_O_TBPR)); -} - -//***************************************************************************** -// -//! \brief Set the timer prescale match value. -//! -//! This function configures the value of the input clock prescaler match -//! value. When in a half-width mode that uses the counter match and the -//! prescaler, the prescale match effectively extends the range of the match. -//! The prescaler provides the least significant bits when counting down in -//! periodic and one-shot modes; in all other modes, the prescaler provides the -//! most significant bits. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Value is the timer prescale match value which must be between 0 -//! and 255 (both included). -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - ASSERT(ui32Value < 256); - - // Set the timer A prescale match if requested. - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + GPT_O_TAPMR) = ui32Value; - } - - // Set the timer B prescale match if requested. - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + GPT_O_TBPMR) = ui32Value; - } -} - -//***************************************************************************** -// -//! \brief Get the timer prescale match value. -//! -//! This function gets the value of the input clock prescaler match value. -//! When in a half-width mode that uses the counter match and prescaler, the -//! prescale match effectively extends the range of the match. The prescaler -//! provides the least significant bits when counting down in periodic and -//! one-shot modes; in all other modes, the prescaler provides the most -//! significant bits. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! -//! \return Returns the value of the timer prescale match. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // Return the appropriate prescale match value. - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : - HWREG(ui32Base + GPT_O_TBPMR)); -} - -//***************************************************************************** -// -//! \brief Sets the timer load value. -//! -//! This function configures the timer load value; if the timer is running then -//! the value is immediately loaded into the timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \note Only \ref TIMER_A should be used when the timer is configured for -//! full-width operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Value is the load value. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the timer A load value if requested. - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + GPT_O_TAILR) = ui32Value; - } - - // Set the timer B load value if requested. - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + GPT_O_TBILR) = ui32Value; - } -} - -//***************************************************************************** -// -//! \brief Gets the timer load value. -//! -//! This function gets the currently programmed interval load value for the -//! specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \note Only \ref TIMER_A should be used when the timer is configured for -//! full-width operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! -//! \return Returns the load value for the timer -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // Return the appropriate load value. - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : - HWREG(ui32Base + GPT_O_TBILR)); -} - -//***************************************************************************** -// -//! \brief Gets the current timer value. -//! -//! This function reads the current value of the specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \note Only \ref TIMER_A should be used when the timer is configured for -//! full-width operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! -//! \return Returns the current value of the timer. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // Return the appropriate timer value. - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : - HWREG(ui32Base + GPT_O_TBR)); -} - -//***************************************************************************** -// -//! \brief Sets the timer match value. -//! -//! This function configures the match value for a timer. This value is used -//! in capture count mode to determine when to interrupt the processor and in -//! PWM mode to determine the duty cycle of the output signal. Match interrupts -//! can also be generated in periodic and one-shot modes when the value of the -//! counter matches this register. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \note Only \ref TIMER_A should be used when the timer is configured for -//! full-width operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Value is the match value. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the timer A match value if requested. - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + GPT_O_TAMATCHR) = ui32Value; - } - - // Set the timer B match value if requested. - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + GPT_O_TBMATCHR) = ui32Value; - } -} - -//***************************************************************************** -// -//! \brief Gets the timer match value. -//! -//! This function gets the match value for the specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \note Only \ref TIMER_A should be used when the timer is configured for -//! full-width operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! -//! \return Returns the match value for the timer -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // Return the appropriate match value. - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : - HWREG(ui32Base + GPT_O_TBMATCHR)); -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the timer interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific timer interrupts must be enabled via \ref TimerIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! \ref TimerIntClear(). -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s); must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param pfnHandler is a pointer to the function to be called when the timer -//! interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, - void (*pfnHandler)(void)); - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for the timer interrupt in the dynamic interrupt table. -//! -//! This function unregisters the handler to be called when a timer interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler is no longer called. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s); must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); - -//***************************************************************************** -// -//! \brief Enables individual timer interrupt sources. -//! -//! This function enables the indicated timer interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! The parameter must be the bitwise OR of any combination of -//! the following: -//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. -//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. -//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. -//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. -//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. -//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - - // Enable the specified interrupts. - HWREG(ui32Base + GPT_O_IMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Disables individual timer interrupt sources. -//! -//! This function disables the indicated timer interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! The parameter must be the bitwise OR of any combination of -//! the following: -//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. -//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. -//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. -//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. -//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. -//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - - // Disable the specified interrupts. - HWREG(ui32Base + GPT_O_IMR) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status. -//! -//! This function returns the interrupt status for the timer module. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param ui32Base is the base address of the timer module. -//! \param bMasked selects either raw or masked interrupt status: -//! - \c true : Masked interrupt. -//! - \c false : Raw interrupt. -//! -//! \return The current interrupt status, enumerated as a bit field of values: -//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. -//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. -//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. -//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. -//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. -//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerIntStatus(uint32_t ui32Base, bool bMasked) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - - // Return either the interrupt status or the raw interrupt status as - // requested. - return(bMasked ? HWREG(ui32Base + GPT_O_MIS) : - HWREG(ui32Base + GPT_O_RIS)); -} - -//***************************************************************************** -// -//! \brief Clears timer interrupt sources. -//! -//! The specified timer interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! The parameter must be the bitwise OR of any combination of -//! the following: -//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. -//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. -//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. -//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. -//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. -//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - - // Clear the requested interrupt sources. - HWREG(ui32Base + GPT_O_ICLR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Synchronizes the counters in a set of timers. -//! -//! This function synchronizes the counters in a specified set of timers. -//! When a timer is running in half-width mode, each half can be included or -//! excluded in the synchronization event. When a timer is running in -//! full-width mode, only the A timer can be synchronized (specifying the B -//! timer has no effect). -//! -//! \param ui32Base is the base address of the timer module. This parameter must -//! be the base address of Timer0 (in other words, \b GPT0_BASE). -//! \param ui32Timers is the set of timers to synchronize. -//! The parameter is the bitwise OR of any of the following: -//! - \ref TIMER_0A_SYNC -//! - \ref TIMER_0B_SYNC -//! - \ref TIMER_1A_SYNC -//! - \ref TIMER_1B_SYNC -//! - \ref TIMER_2A_SYNC -//! - \ref TIMER_2B_SYNC -//! - \ref TIMER_3A_SYNC -//! - \ref TIMER_3B_SYNC -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers) -{ - // Check the arguments. - ASSERT(ui32Base == GPT0_BASE); - - // Synchronize the specified timers. - HWREG(ui32Base + GPT_O_SYNC) = ui32Timers; -} - -//***************************************************************************** -// -//! \brief Enables AND'ing of the CCP outputs from Timer A and Timer B. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerCcpCombineEnable(uint32_t ui32Base) -{ - // Check the arguments - ASSERT(TimerBaseValid(ui32Base)); - - // Set the bit - HWREG(ui32Base + GPT_O_ANDCCP) |= GPT_ANDCCP_CCP_AND_EN; -} - -//***************************************************************************** -// -//! \brief Disables AND'ing of the CCP outputs from Timer A and Timer B. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerCcpCombineDisable(uint32_t ui32Base) -{ - // Check the arguments - ASSERT(TimerBaseValid(ui32Base)); - - // Clear the bit - HWREG(ui32Base + GPT_O_ANDCCP) &= ~(GPT_ANDCCP_CCP_AND_EN); -} - -//***************************************************************************** -// -//! \brief Sets the Match Register Update mode. -//! -//! This function controls when the Match Register value and Prescale Register value -//! are applied after writing these registers while a timer is enabled. -//! -//! \note If the timer is disabled when setting the update mode the Match Register -//! and Prescale Register values are applied immediately when enabling the timer. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to configure; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Mode sets the mode: -//! - \ref TIMER_MATCHUPDATE_NEXTCYCLE : Apply Match Register and Prescale Register on next clock -//! cycle after writing any of these registers. -//! - \ref TIMER_MATCHUPDATE_TIMEOUT : Apply Match Register and Prescale Register on next timeout -//! after writing any of these registers. -//! -//! \return None -// -//***************************************************************************** -extern void TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); - -//***************************************************************************** -// -//! \brief Sets the Interval Load mode. -//! -//! This function controls when the Timer Register and Prescale Snap-shot (if used) -//! are updated. -//! -//! Timer Register (TAR/TBR) is updated when Interval Load Register (TAILR/TBILR) is written -//! and the Prescale Snap-shot (TAPS/TBPS) is updated when Prescale Register (TAPR/TBPR) is -//! written depending on the mode of operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to configure; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Mode sets the mode: -//! - \ref TIMER_INTERVALLOAD_NEXTCYCLE : Update Timer Register and Prescale Snap-shot on next clock -//! cycle after writing Interval Load Register or Prescale Register, respectively. -//! - \ref TIMER_INTERVALLOAD_TIMEOUT : Update Timer Register and Prescale Snap-shot on next timeout -//! after writing Interval Load Register or Prescale Register, respectively. -//! -//! \return None -// -//***************************************************************************** -extern void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_TimerConfigure - #undef TimerConfigure - #define TimerConfigure ROM_TimerConfigure - #endif - #ifdef ROM_TimerLevelControl - #undef TimerLevelControl - #define TimerLevelControl ROM_TimerLevelControl - #endif - #ifdef ROM_TimerStallControl - #undef TimerStallControl - #define TimerStallControl ROM_TimerStallControl - #endif - #ifdef ROM_TimerWaitOnTriggerControl - #undef TimerWaitOnTriggerControl - #define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl - #endif - #ifdef ROM_TimerIntRegister - #undef TimerIntRegister - #define TimerIntRegister ROM_TimerIntRegister - #endif - #ifdef ROM_TimerIntUnregister - #undef TimerIntUnregister - #define TimerIntUnregister ROM_TimerIntUnregister - #endif - #ifdef ROM_TimerMatchUpdateMode - #undef TimerMatchUpdateMode - #define TimerMatchUpdateMode ROM_TimerMatchUpdateMode - #endif - #ifdef ROM_TimerIntervalLoadMode - #undef TimerIntervalLoadMode - #define TimerIntervalLoadMode ROM_TimerIntervalLoadMode - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __GPT_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/timer_doc.h b/third_party/ti/devices/cc26x0/driverlib/timer_doc.h deleted file mode 100644 index f30779f4b..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/timer_doc.h +++ /dev/null @@ -1,121 +0,0 @@ -/****************************************************************************** -* Filename: timer_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup timer_api -//! @{ -//! \section sec_timer Introduction -//! -//! The timer API provides a set of functions for using the general-purpose timer module. -//! -//! The timer module contains four timer blocks with the following functional options: -//! - Operating modes: -//! - 16-bit with 8-bit prescaler or 32-bit programmable one-shot timer. -//! - 16-bit with 8-bit prescaler or 32-bit programmable periodic timer. -//! - Two capture compare PWM pins (CCP) for each 32-bit timer. -//! - 24-bit input-edge count or 24-bit time-capture modes. -//! - 24-bit PWM mode with software-programmable output inversion of the PWM signal. -//! - Count up or down. -//! - Daisy chaining of timer modules allows a single timer to initiate multiple timing events. -//! - Timer synchronization allows selected timers to start counting on the same clock cycle. -//! - User-enabled stalling when the System CPU asserts a CPU Halt flag during debug. -//! - Ability to determine the elapsed time between the assertion of the timer interrupt and -//! entry into the interrupt service routine. -//! -//! Each timer block provides two half-width timers/counters that can be configured -//! to operate independently as timers or event counters or to operate as a combined -//! full-width timer. -//! The timers provide 16-bit half-width timers and a 32-bit full-width timer. -//! For the purposes of this API, the two -//! half-width timers provided by a timer block are referred to as TimerA and -//! TimerB, and the full-width timer is referred to as TimerA. -//! -//! When in half-width mode, the timer can also be configured for event capture or -//! as a pulse width modulation (PWM) generator. When configured for event -//! capture, the timer acts as a counter. It can be configured to count either the -//! time between events or the events themselves. The type of event -//! being counted can be configured as a positive edge, a negative edge, or both -//! edges. When a timer is configured as a PWM generator, the input signal used to -//! capture events becomes an output signal, and the timer drives an -//! edge-aligned pulse onto that signal. -//! -//! Control is also provided over interrupt sources and events. Interrupts can be -//! generated to indicate that an event has been captured, or that a certain number -//! of events have been captured. Interrupts can also be generated when the timer -//! has counted down to 0 or when the timer matches a certain value. -//! -//! Timer configuration is handled by \ref TimerConfigure(), which performs the high -//! level setup of the timer module; that is, it is used to set up full- or -//! half-width modes, and to select between PWM, capture, and timer operations. -//! -//! \section sec_timer_api API -//! -//! The API functions can be grouped like this: -//! -//! Functions to perform timer control: -//! - \ref TimerConfigure() -//! - \ref TimerEnable() -//! - \ref TimerDisable() -//! - \ref TimerLevelControl() -//! - \ref TimerWaitOnTriggerControl() -//! - \ref TimerEventControl() -//! - \ref TimerStallControl() -//! - \ref TimerIntervalLoadMode() -//! - \ref TimerMatchUpdateMode() -//! - \ref TimerCcpCombineDisable() -//! - \ref TimerCcpCombineEnable() -//! -//! Functions to manage timer content: -//! - \ref TimerLoadSet() -//! - \ref TimerLoadGet() -//! - \ref TimerPrescaleSet() -//! - \ref TimerPrescaleGet() -//! - \ref TimerMatchSet() -//! - \ref TimerMatchGet() -//! - \ref TimerPrescaleMatchSet() -//! - \ref TimerPrescaleMatchGet() -//! - \ref TimerValueGet() -//! - \ref TimerSynchronize() -//! -//! Functions to manage the interrupt handler for the timer interrupt: -//! - \ref TimerIntRegister() -//! - \ref TimerIntUnregister() -//! -//! The individual interrupt sources within the timer module are managed with: -//! - \ref TimerIntEnable() -//! - \ref TimerIntDisable() -//! - \ref TimerIntStatus() -//! - \ref TimerIntClear() -//! -//! @} diff --git a/third_party/ti/devices/cc26x0/driverlib/trng.c b/third_party/ti/devices/cc26x0/driverlib/trng.c deleted file mode 100644 index 751c5cbaa..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/trng.c +++ /dev/null @@ -1,112 +0,0 @@ -/****************************************************************************** -* Filename: trng.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the TRNG module -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "trng.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef TRNGConfigure - #define TRNGConfigure NOROM_TRNGConfigure - #undef TRNGNumberGet - #define TRNGNumberGet NOROM_TRNGNumberGet -#endif - -//***************************************************************************** -// -// Configure the true random number generator -// -//***************************************************************************** -void -TRNGConfigure(uint32_t ui32MinSamplesPerCycle, - uint32_t ui32MaxSamplesPerCycle, - uint32_t ui32ClocksPerSample) -{ - uint32_t ui32Val; - - // Make sure the TRNG is disabled. - ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; - HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; - - // Configure the startup number of samples. - ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; - ui32Val |= ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CTL_STARTUP_CYCLES_S ) & TRNG_CTL_STARTUP_CYCLES_M ); - HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; - - // Configure the minimum and maximum number of samples pr generated number - // and the number of clocks per sample. - HWREG(TRNG_BASE + TRNG_O_CFG0) = ( - ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CFG0_MAX_REFILL_CYCLES_S ) & TRNG_CFG0_MAX_REFILL_CYCLES_M ) | - ((( ui32ClocksPerSample ) << TRNG_CFG0_SMPL_DIV_S ) & TRNG_CFG0_SMPL_DIV_M ) | - ((( ui32MinSamplesPerCycle >> 6 ) << TRNG_CFG0_MIN_REFILL_CYCLES_S ) & TRNG_CFG0_MIN_REFILL_CYCLES_M ) ); -} - -//***************************************************************************** -// -// Get a random number from the generator -// -//***************************************************************************** -uint32_t -TRNGNumberGet(uint32_t ui32Word) -{ - uint32_t ui32RandomNumber; - - // Check the arguments. - ASSERT((ui32Word == TRNG_HI_WORD) || - (ui32Word == TRNG_LOW_WORD)); - - // Return the right requested part of the generated number. - if(ui32Word == TRNG_HI_WORD) - { - ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); - } - else - { - ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); - } - - // Initiate generation of new number. - HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; - - // Return the random number. - return ui32RandomNumber; -} diff --git a/third_party/ti/devices/cc26x0/driverlib/trng.h b/third_party/ti/devices/cc26x0/driverlib/trng.h deleted file mode 100644 index 2a2f047cd..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/trng.h +++ /dev/null @@ -1,451 +0,0 @@ -/****************************************************************************** -* Filename: trng.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the true random number gen. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup trng_api -//! @{ -// -//***************************************************************************** - -#ifndef __TRNG_H__ -#define __TRNG_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_trng.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "debug.h" -#include "interrupt.h" -#include "cpu.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define TRNGConfigure NOROM_TRNGConfigure - #define TRNGNumberGet NOROM_TRNGNumberGet -#endif - -//***************************************************************************** -// -// -// -//***************************************************************************** -#define TRNG_NUMBER_READY 0x00000001 // -#define TRNG_FRO_SHUTDOWN 0x00000002 // -#define TRNG_NEED_CLOCK 0x80000000 // - -#define TRNG_HI_WORD 0x00000001 -#define TRNG_LOW_WORD 0x00000002 - -//***************************************************************************** -// -// API Function and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Configure the true random number generator. -//! -//! Use this function to set the minimum and maximum number of samples required -//! in each generation of a new random number. -//! -//! \param ui32MinSamplesPerCycle is the minimum number of samples per each -//! generated random number. Constraints: -//! - Value must be bigger than or equal to 2^6 and less than 2^14. -//! - The 6 LSBs of the argument are truncated. -//! - If the value is zero, the number of samples is fixed to the value determined -//! by ui32MaxSamplesPerCycle. To ensure same entropy in all generated random -//! numbers the value 0 should be used. -//! \param ui32MaxSamplesPerCycle is the maximum number of samples per each -//! generated random number. Constraints: -//! - Value must be between 2^8 and 2^24 (both included). -//! - The 8 LSBs of the argument are truncated. -//! - Value 0 and 2^24 both give the highest possible value. -//! \param ui32ClocksPerSample is the number of clock cycles for each time -//! a new sample is generated from the FROs. -//! - 0 : Every sample. -//! - 1 : Every second sample. -//! - ... -//! - 15 : Every 16. sample. -//! -//! \return None -// -//***************************************************************************** -extern void TRNGConfigure(uint32_t ui32MinSamplesPerCycle, - uint32_t ui32MaxSamplesPerCycle, - uint32_t ui32ClocksPerSample); - -//***************************************************************************** -// -//! \brief Enable the TRNG. -//! -//! Enable the TRNG to start preparing a random number. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGEnable(void) -{ - // Enable the TRNG. - HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disable the TRNG module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGDisable(void) -{ - // Enable the TRNG - HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Get a random number from the generator. -//! -//! Use this function to get either the high or low part of the 64 bit -//! generated number. -//! -//! \note Data from this register is only valid if the TRNG has produced a -//! number. Use \ref TRNGStatusGet() to poll the for status. After calling this -//! function a new random number will be generated. -//! -//! \param ui32Word determines if whether to return the high or low 32 bits. -//! - \ref TRNG_HI_WORD -//! - \ref TRNG_LOW_WORD -//! -//! \return Return either the high or low part of the 64 bit generated random -//! number. -// -//***************************************************************************** -extern uint32_t TRNGNumberGet(uint32_t ui32Word); - -//***************************************************************************** -// -//! \brief Get the status of the TRNG. -//! -//! Use this function to retrieve the status of the TRNG. -//! -//! \return Returns the current status of the TRNG module. -//! The returned status is a bitwise OR'ed combination of: -//! - \ref TRNG_NUMBER_READY -//! - \ref TRNG_FRO_SHUTDOWN -//! - \ref TRNG_NEED_CLOCK -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TRNGStatusGet(void) -{ - // Return the status. - return (HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); -} - -//***************************************************************************** -// -//! \brief Reset the TRNG. -//! -//! Use this function to reset the TRNG module. Reset will be low for -//! approximately 5 clock cycles. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGReset(void) -{ - // Reset the TRNG. - HWREG(TRNG_BASE + TRNG_O_SWRESET) = 1; -} - -//***************************************************************************** -// -//! \brief Enables individual TRNG interrupt sources. -//! -//! This function enables the indicated TRNG interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref TRNG_NUMBER_READY -//! - \ref TRNG_FRO_SHUTDOWN -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGIntEnable(uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || - (ui32IntFlags & TRNG_FRO_SHUTDOWN)); - - // Enable the specified interrupts. - HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Disables individual TRNG interrupt sources. -//! -//! This function disables the indicated TRNG interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref TRNG_NUMBER_READY -//! - \ref TRNG_FRO_SHUTDOWN -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGIntDisable(uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || - (ui32IntFlags & TRNG_FRO_SHUTDOWN)); - - // Disable the specified interrupts. - HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status of the TRNG module. -//! -//! This function returns the interrupt status for the specified TRNG. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param bMasked selects either raw or masked interrupt status. -//! - \c true : Masked interrupt. -//! - \c false : Raw interrupt. -//! -//! \return Returns the current interrupt status, enumerated as: -//! - \ref TRNG_NUMBER_READY -//! - \ref TRNG_FRO_SHUTDOWN -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TRNGIntStatus(bool bMasked) -{ - uint32_t ui32Mask; - - // Return either the interrupt status or the raw interrupt status as - // requested. - if(bMasked) - { - ui32Mask = HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK); - return(ui32Mask & HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); - } - else - { - return(HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT) & 0x00000003); - } -} - -//***************************************************************************** -// -//! \brief Clears TRNG interrupt sources. -//! -//! The specified TRNG interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! The parameter is the bitwise OR of any of the following: -//! - \ref TRNG_NUMBER_READY -//! - \ref TRNG_FRO_SHUTDOWN -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGIntClear(uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || - (ui32IntFlags & TRNG_FRO_SHUTDOWN)); - - // Clear the requested interrupt sources. - HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for a TRNG interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific TRNG interrupts must be enabled via \ref TRNGIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! TRNG interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -TRNGIntRegister(void (*pfnHandler)(void)) -{ - // Register the interrupt handler. - IntRegister(INT_TRNG_IRQ, pfnHandler); - - // Enable the TRNG interrupt. - IntEnable(INT_TRNG_IRQ); -} - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for a TRNG interrupt in the dynamic interrupt table. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a Crypto interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -TRNGIntUnregister(void) -{ - // Disable the interrupt. - IntDisable(INT_TRNG_IRQ); - - // Unregister the interrupt handler. - IntUnregister(INT_TRNG_IRQ); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_TRNGConfigure - #undef TRNGConfigure - #define TRNGConfigure ROM_TRNGConfigure - #endif - #ifdef ROM_TRNGNumberGet - #undef TRNGNumberGet - #define TRNGNumberGet ROM_TRNGNumberGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __TRNG_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/uart.c b/third_party/ti/devices/cc26x0/driverlib/uart.c deleted file mode 100644 index 10e41c5f0..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/uart.c +++ /dev/null @@ -1,296 +0,0 @@ -/****************************************************************************** -* Filename: uart.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the UART. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "uart.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef UARTFIFOLevelGet - #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet - #undef UARTConfigSetExpClk - #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk - #undef UARTConfigGetExpClk - #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk - #undef UARTDisable - #define UARTDisable NOROM_UARTDisable - #undef UARTCharGetNonBlocking - #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking - #undef UARTCharGet - #define UARTCharGet NOROM_UARTCharGet - #undef UARTCharPutNonBlocking - #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking - #undef UARTCharPut - #define UARTCharPut NOROM_UARTCharPut - #undef UARTIntRegister - #define UARTIntRegister NOROM_UARTIntRegister - #undef UARTIntUnregister - #define UARTIntUnregister NOROM_UARTIntUnregister -#endif - -//***************************************************************************** -// -// Gets the FIFO level at which interrupts are generated -// -//***************************************************************************** -void -UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, - uint32_t *pui32RxLevel) -{ - uint32_t ui32Temp; - - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Read the FIFO level register. - ui32Temp = HWREG(ui32Base + UART_O_IFLS); - - // Extract the transmit and receive FIFO levels. - *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; - *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; -} - -//***************************************************************************** -// -// Sets the configuration of a UART -// -//***************************************************************************** -void -UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t ui32Baud, uint32_t ui32Config) -{ - uint32_t ui32Div; - - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - ASSERT(ui32Baud != 0); - - // Stop the UART. - UARTDisable(ui32Base); - - // Compute the fractional baud rate divider. - ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; - - // Set the baud rate. - HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; - HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; - - // Set parity, data length, and number of stop bits. - HWREG(ui32Base + UART_O_LCRH) = ui32Config; -} - -//***************************************************************************** -// -// Gets the current configuration of a UART -// -//***************************************************************************** -void -UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t *pui32Baud, uint32_t *pui32Config) -{ - uint32_t ui32Int, ui32Frac; - - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Compute the baud rate. - ui32Int = HWREG(ui32Base + UART_O_IBRD); - ui32Frac = HWREG(ui32Base + UART_O_FBRD); - *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); - - // Get the parity, data length, and number of stop bits. - *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | - UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -// Disables transmitting and receiving -// -//***************************************************************************** -void -UARTDisable(uint32_t ui32Base) -{ - - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Wait for end of TX. - while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) - { - } - - // Disable the FIFO. - HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); - - // Disable the UART. - HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -// Receives a character from the specified port -// -//***************************************************************************** -int32_t -UARTCharGetNonBlocking(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // See if there are any characters in the receive FIFO. - if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) - { - // Read and return the next character. - return(HWREG(ui32Base + UART_O_DR)); - } - else - { - // There are no characters, so return a failure. - return(-1); - } -} - -//***************************************************************************** -// -// Waits for a character from the specified port -// -//***************************************************************************** -int32_t -UARTCharGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Wait until a char is available. - while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) - { - } - - // Now get the character. - return(HWREG(ui32Base + UART_O_DR)); -} - -//***************************************************************************** -// -// Sends a character to the specified port -// -//***************************************************************************** -bool -UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // See if there is space in the transmit FIFO. - if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) - { - // Write this character to the transmit FIFO. - HWREG(ui32Base + UART_O_DR) = ui8Data; - - // Success. - return(true); - } - else - { - // There is no space in the transmit FIFO, so return a failure. - return(false); - } -} - -//***************************************************************************** -// -// Waits to send a character from the specified port -// -//***************************************************************************** -void -UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Wait until space is available. - while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) - { - } - - // Send the char. - HWREG(ui32Base + UART_O_DR) = ui8Data; -} - -//***************************************************************************** -// -// Registers an interrupt handler for a UART interrupt -// -//***************************************************************************** -void -UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Register the interrupt handler. - IntRegister(INT_UART0_COMB, pfnHandler); - - // Enable the UART interrupt. - IntEnable(INT_UART0_COMB); -} - -//***************************************************************************** -// -// Unregisters an interrupt handler for a UART interrupt -// -//***************************************************************************** -void -UARTIntUnregister(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Disable the interrupt. - IntDisable(INT_UART0_COMB); - - // Unregister the interrupt handler. - IntUnregister(INT_UART0_COMB); -} diff --git a/third_party/ti/devices/cc26x0/driverlib/uart.h b/third_party/ti/devices/cc26x0/driverlib/uart.h deleted file mode 100644 index 769374302..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/uart.h +++ /dev/null @@ -1,1091 +0,0 @@ -/****************************************************************************** -* Filename: uart.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the UART. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup uart_api -//! @{ -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_uart.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "interrupt.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet - #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk - #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk - #define UARTDisable NOROM_UARTDisable - #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking - #define UARTCharGet NOROM_UARTCharGet - #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking - #define UARTCharPut NOROM_UARTCharPut - #define UARTIntRegister NOROM_UARTIntRegister - #define UARTIntUnregister NOROM_UARTIntUnregister -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ui32IntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE ( UART_IMSC_OEIM ) // Overrun Error Interrupt Mask -#define UART_INT_BE ( UART_IMSC_BEIM ) // Break Error Interrupt Mask -#define UART_INT_PE ( UART_IMSC_PEIM ) // Parity Error Interrupt Mask -#define UART_INT_FE ( UART_IMSC_FEIM ) // Framing Error Interrupt Mask -#define UART_INT_RT ( UART_IMSC_RTIM ) // Receive Timeout Interrupt Mask -#define UART_INT_TX ( UART_IMSC_TXIM ) // Transmit Interrupt Mask -#define UART_INT_RX ( UART_IMSC_RXIM ) // Receive Interrupt Mask -#define UART_INT_CTS ( UART_IMSC_CTSMIM ) // CTS Modem Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter -// and returned by UARTConfigGetExpClk in the pui32Config parameter. -// Additionally, the UART_CONFIG_PAR_* subset can be passed to -// UARTParityModeSet as the ui32Parity parameter, and are returned by -// UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero - -//***************************************************************************** -// -// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter -// and returned by UARTFIFOLevelGet in the pui32TxLevel. -// -//***************************************************************************** -#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full -#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full -#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full -#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full -#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full - -//***************************************************************************** -// -// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter -// and returned by UARTFIFOLevelGet in the pui32RxLevel. -// -//***************************************************************************** -#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full -#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full -#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full -#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full -#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full - -//***************************************************************************** -// -// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). -// -//***************************************************************************** -#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error -#define UART_DMA_TX 0x00000002 // Enable DMA for transmit -#define UART_DMA_RX 0x00000001 // Enable DMA for receive - -//***************************************************************************** -// -// Values returned from UARTRxErrorGet(). -// -//***************************************************************************** -#define UART_RXERROR_OVERRUN 0x00000008 -#define UART_RXERROR_BREAK 0x00000004 -#define UART_RXERROR_PARITY 0x00000002 -#define UART_RXERROR_FRAMING 0x00000001 - -//***************************************************************************** -// -// Values returned from the UARTBusy(). -// -//***************************************************************************** -#define UART_BUSY 0x00000001 -#define UART_IDLE 0x00000000 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Checks a UART base address. -//! -//! This function determines if a UART port base address is valid. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -UARTBaseValid(uint32_t ui32Base) -{ - return(( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE )); -} -#endif - -//***************************************************************************** -// -//! \brief Sets the type of parity. -//! -//! This function sets the type of parity to use for transmitting and expect -//! when receiving. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Parity specifies the type of parity to use. The last two allow -//! direct control of the parity bit; it is always either one or zero based on -//! the mode. -//! - \ref UART_CONFIG_PAR_NONE -//! - \ref UART_CONFIG_PAR_EVEN -//! - \ref UART_CONFIG_PAR_ODD -//! - \ref UART_CONFIG_PAR_ONE -//! - \ref UART_CONFIG_PAR_ZERO -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || - (ui32Parity == UART_CONFIG_PAR_EVEN) || - (ui32Parity == UART_CONFIG_PAR_ODD) || - (ui32Parity == UART_CONFIG_PAR_ONE) || - (ui32Parity == UART_CONFIG_PAR_ZERO)); - - // Set the parity mode. - HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & - ~(UART_LCRH_SPS | UART_LCRH_EPS | - UART_LCRH_PEN)) | ui32Parity); -} - -//***************************************************************************** -// -//! \brief Gets the type of parity currently being used. -//! -//! This function gets the type of parity used for transmitting data and -//! expected when receiving data. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns the current parity settings, specified as one of: -//! - \ref UART_CONFIG_PAR_NONE -//! - \ref UART_CONFIG_PAR_EVEN -//! - \ref UART_CONFIG_PAR_ODD -//! - \ref UART_CONFIG_PAR_ONE -//! - \ref UART_CONFIG_PAR_ZERO -// -//***************************************************************************** -__STATIC_INLINE uint32_t -UARTParityModeGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Return the current parity setting - return(HWREG(ui32Base + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -//! \brief Sets the FIFO level at which interrupts are generated. -//! -//! This function sets the FIFO level at which transmit and receive interrupts -//! are generated. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one of: -//! - \ref UART_FIFO_TX1_8 -//! - \ref UART_FIFO_TX2_8 -//! - \ref UART_FIFO_TX4_8 -//! - \ref UART_FIFO_TX6_8 -//! - \ref UART_FIFO_TX7_8 -//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of: -//! - \ref UART_FIFO_RX1_8 -//! - \ref UART_FIFO_RX2_8 -//! - \ref UART_FIFO_RX4_8 -//! - \ref UART_FIFO_RX6_8 -//! - \ref UART_FIFO_RX7_8 -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, - uint32_t ui32RxLevel) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || - (ui32TxLevel == UART_FIFO_TX2_8) || - (ui32TxLevel == UART_FIFO_TX4_8) || - (ui32TxLevel == UART_FIFO_TX6_8) || - (ui32TxLevel == UART_FIFO_TX7_8)); - ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || - (ui32RxLevel == UART_FIFO_RX2_8) || - (ui32RxLevel == UART_FIFO_RX4_8) || - (ui32RxLevel == UART_FIFO_RX6_8) || - (ui32RxLevel == UART_FIFO_RX7_8)); - - // Set the FIFO interrupt levels. - HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel; -} - -//***************************************************************************** -// -//! \brief Gets the FIFO level at which interrupts are generated. -//! -//! This function gets the FIFO level at which transmit and receive interrupts -//! are generated. -//! -//! \param ui32Base is the base address of the UART port. -//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, -//! returned as one of: -//! - \ref UART_FIFO_TX1_8 -//! - \ref UART_FIFO_TX2_8 -//! - \ref UART_FIFO_TX4_8 -//! - \ref UART_FIFO_TX6_8 -//! - \ref UART_FIFO_TX7_8 -//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, -//! returned as one of: -//! - \ref UART_FIFO_RX1_8 -//! - \ref UART_FIFO_RX2_8 -//! - \ref UART_FIFO_RX4_8 -//! - \ref UART_FIFO_RX6_8 -//! - \ref UART_FIFO_RX7_8 -//! -//! \return None -// -//***************************************************************************** -extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, - uint32_t *pui32RxLevel); - -//***************************************************************************** -// -//! \brief Sets the configuration of a UART. -//! -//! This function configures the UART for operation in the specified data -//! format. -//! -//! \note The peripheral clock is not necessarily the same as the processor -//! clock. The frequency of the peripheral clock is set by the system control. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32UARTClk is the rate of the clock supplied to the UART module. -//! \param ui32Baud is the desired baud rate. -//! - Minimum baud rate: ui32Baud >= ceil(ui32UARTClk / 1,048,559.875) -//! - Maximum baud rate: ui32Baud <= floor(ui32UARTClk / 15.875) -//! \param ui32Config is the data format for the port. -//! The parameter is the bitwise OR of three values: -//! - Number of data bits -//! - \ref UART_CONFIG_WLEN_8 : 8 data bits per byte. -//! - \ref UART_CONFIG_WLEN_7 : 7 data bits per byte. -//! - \ref UART_CONFIG_WLEN_6 : 6 data bits per byte. -//! - \ref UART_CONFIG_WLEN_5 : 5 data bits per byte. -//! - Number of stop bits -//! - \ref UART_CONFIG_STOP_ONE : One stop bit. -//! - \ref UART_CONFIG_STOP_TWO : Two stop bits. -//! - Parity -//! - \ref UART_CONFIG_PAR_NONE -//! - \ref UART_CONFIG_PAR_EVEN -//! - \ref UART_CONFIG_PAR_ODD -//! - \ref UART_CONFIG_PAR_ONE -//! - \ref UART_CONFIG_PAR_ZERO -//! -//! \return None -// -//***************************************************************************** -extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t ui32Baud, uint32_t ui32Config); - -//***************************************************************************** -// -//! \brief Gets the current configuration of a UART. -//! -//! The baud rate and data format for the UART is determined, given an -//! explicitly provided peripheral clock (hence the ExpClk suffix). The -//! returned baud rate is the actual baud rate; it may not be the exact baud -//! rate requested or an "official" baud rate. The data format returned in -//! \c pui32Config is enumerated the same as the \c ui32Config parameter of -//! \ref UARTConfigSetExpClk(). -//! -//! \note The peripheral clock is not necessarily the same as the processor -//! clock. The frequency of the peripheral clock is set by the system control. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32UARTClk is the rate of the clock supplied to the UART module. -//! \param pui32Baud is a pointer to storage for the baud rate. -//! \param pui32Config is a pointer to storage for the data format. -//! -//! \return None -// -//***************************************************************************** -extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t *pui32Baud, uint32_t *pui32Config); - -//***************************************************************************** -// -//! \brief Enables transmitting and receiving. -//! -//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit -//! and receive FIFOs. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Enable the FIFO. - HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; - - // Enable RX, TX, and the UART. - HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -//! \brief Disables transmitting and receiving. -//! -//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of -//! transmission of the current character, and flushes the transmit FIFO. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -extern void UARTDisable(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Enables the transmit and receive FIFOs. -//! -//! This functions enables the transmit and receive FIFOs in the UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTFIFOEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Enable the FIFO. - HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; -} - -//***************************************************************************** -// -//! \brief Disables the transmit and receive FIFOs. -//! -//! This functions disables the transmit and receive FIFOs in the UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTFIFODisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Disable the FIFO. - HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); -} - -//***************************************************************************** -// -//! \brief Determines if there are any characters in the receive FIFO. -//! -//! This function returns a flag indicating whether or not there is data -//! available in the receive FIFO. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns status of the receive FIFO. -//! - \c true : There is data in the receive FIFO. -//! - \c false : There is no data in the receive FIFO. -// -//***************************************************************************** -__STATIC_INLINE bool -UARTCharsAvail(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Return the availability of characters. - return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true); -} - -//***************************************************************************** -// -//! \brief Determines if there is any space in the transmit FIFO. -//! -//! This function returns a flag indicating whether or not there is space -//! available in the transmit FIFO. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns status of the transmit FIFO. -//! - \c true : There is space available in the transmit FIFO. -//! - \c false : There is no space available in the transmit FIFO. -// -//***************************************************************************** -__STATIC_INLINE bool -UARTSpaceAvail(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Return the availability of space. - return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true); -} - -//***************************************************************************** -// -//! \brief Receives a character from the specified port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. -//! -//! \note The \ref UARTCharsAvail() function should be called before -//! attempting to call this function. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns the character read from the specified port, cast as an -//! \c int32_t. A \c -1 is returned if there are no characters present in the -//! receive FIFO. -//! -//! \sa \ref UARTCharsAvail() -// -//***************************************************************************** -extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Waits for a character from the specified port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. If there are no characters available, this function waits until a -//! character is received before returning. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns the character read from the specified port, cast as an -//! \c int32_t. -// -//***************************************************************************** -extern int32_t UARTCharGet(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Sends a character to the specified port. -//! -//! This function writes the character \c ui8Data to the transmit FIFO for the -//! specified port. This function does not block, so if there is no space -//! available, then a \c false is returned, and the application must retry the -//! function later. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui8Data is the character to be transmitted. -//! -//! \return Returns status of the character transmit. -//! - \c true : The character was successfully placed in the transmit FIFO. -//! - \c false : There was no space available in the transmit FIFO. Try again later. -// -//***************************************************************************** -extern bool UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data); - -//***************************************************************************** -// -//! \brief Waits to send a character from the specified port. -//! -//! This function sends the character \c ui8Data to the transmit FIFO for the -//! specified port. If there is no space available in the transmit FIFO, this -//! function waits until there is space available before returning. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui8Data is the character to be transmitted. -//! -//! \return None -// -//***************************************************************************** -extern void UARTCharPut(uint32_t ui32Base, uint8_t ui8Data); - -//***************************************************************************** -// -//! \brief Determines whether the UART transmitter is busy or not. -//! -//! Allows the caller to determine whether all transmitted bytes have cleared -//! the transmitter hardware. If \c false is returned, the transmit FIFO is -//! empty and all bits of the last transmitted character, including all stop -//! bits, have left the hardware shift register. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns status of UART transmitter. -//! - \c true : UART is transmitting. -//! - \c false : All transmissions are complete. -// -//***************************************************************************** -__STATIC_INLINE bool -UARTBusy(uint32_t ui32Base) -{ - // Check the argument. - ASSERT(UARTBaseValid(ui32Base)); - - // Determine if the UART is busy. - return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? - UART_BUSY : UART_IDLE); -} - -//***************************************************************************** -// -//! \brief Causes a BREAK to be sent. -//! -//! \note For proper transmission of a break -//! command, the break must be asserted for at least two complete frames. -//! -//! \param ui32Base is the base address of the UART port. -//! \param bBreakState controls the output level. -//! - \c true : Asserts a break condition on the UART. -//! - \c false : Removes the break condition. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTBreakCtl(uint32_t ui32Base, bool bBreakState) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Set the break condition as requested. - HWREG(ui32Base + UART_O_LCRH) = - (bBreakState ? - (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : - (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for a UART interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific UART interrupts must be enabled via \ref UARTIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source. -//! -//! \param ui32Base is the base address of the UART module. -//! \param pfnHandler is a pointer to the function to be called when the -//! UART interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for a UART interrupt in the dynamic interrupt table. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a UART interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \param ui32Base is the base address of the UART module. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void UARTIntUnregister(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Enables individual UART interrupt sources. -//! -//! This function enables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref UART_INT_OE : Overrun Error interrupt. -//! - \ref UART_INT_BE : Break Error interrupt. -//! - \ref UART_INT_PE : Parity Error interrupt. -//! - \ref UART_INT_FE : Framing Error interrupt. -//! - \ref UART_INT_RT : Receive Timeout interrupt. -//! - \ref UART_INT_TX : Transmit interrupt. -//! - \ref UART_INT_RX : Receive interrupt. -//! - \ref UART_INT_CTS : CTS interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Enable the specified interrupts. - HWREG(ui32Base + UART_O_IMSC) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Disables individual UART interrupt sources. -//! -//! This function disables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! - \ref UART_INT_OE : Overrun Error interrupt. -//! - \ref UART_INT_BE : Break Error interrupt. -//! - \ref UART_INT_PE : Parity Error interrupt. -//! - \ref UART_INT_FE : Framing Error interrupt. -//! - \ref UART_INT_RT : Receive Timeout interrupt. -//! - \ref UART_INT_TX : Transmit interrupt. -//! - \ref UART_INT_RX : Receive interrupt. -//! - \ref UART_INT_CTS : CTS interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Disable the specified interrupts. - HWREG(ui32Base + UART_O_IMSC) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status. -//! -//! This function returns the interrupt status for the specified UART. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param ui32Base is the base address of the UART port. -//! \param bMasked selects either raw or masked interrupt. -//! - \c true : Masked interrupt status is required. -//! - \c false : Raw interrupt status is required. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of: -//! - \ref UART_INT_OE : Overrun Error interrupt. -//! - \ref UART_INT_BE : Break Error interrupt. -//! - \ref UART_INT_PE : Parity Error interrupt. -//! - \ref UART_INT_FE : Framing Error interrupt. -//! - \ref UART_INT_RT : Receive Timeout interrupt. -//! - \ref UART_INT_TX : Transmit interrupt. -//! - \ref UART_INT_RX : Receive interrupt. -//! - \ref UART_INT_CTS : CTS interrupt. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -UARTIntStatus(uint32_t ui32Base, bool bMasked) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Return either the interrupt status or the raw interrupt status as - // requested. - if(bMasked) - { - return(HWREG(ui32Base + UART_O_MIS)); - } - else - { - return(HWREG(ui32Base + UART_O_RIS)); - } -} - -//***************************************************************************** -// -//! \brief Clears UART interrupt sources. -//! -//! The specified UART interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! - \ref UART_INT_OE : Overrun Error interrupt. -//! - \ref UART_INT_BE : Break Error interrupt. -//! - \ref UART_INT_PE : Parity Error interrupt. -//! - \ref UART_INT_FE : Framing Error interrupt. -//! - \ref UART_INT_RT : Receive Timeout interrupt. -//! - \ref UART_INT_TX : Transmit interrupt. -//! - \ref UART_INT_RX : Receive interrupt. -//! - \ref UART_INT_CTS : CTS interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments - ASSERT(UARTBaseValid(ui32Base)); - - // Clear the requested interrupt sources - HWREG(ui32Base + UART_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Enable UART DMA operation. -//! -//! The specified UART DMA features are enabled. The UART can be -//! configured to use DMA for transmit or receive, and to disable -//! receive if an error occurs. -//! -//! \note The uDMA controller must also be set up before DMA can be used -//! with the UART. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32DMAFlags is a bit mask of the DMA features to enable. -//! The parameter is the bitwise OR of any of the following values: -//! - UART_DMA_RX : Enable DMA for receive. -//! - UART_DMA_TX : Enable DMA for transmit. -//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Set the requested bits in the UART DMA control register. - HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags; -} - -//***************************************************************************** -// -//! \brief Disable UART DMA operation. -//! -//! This function is used to disable UART DMA features that were enabled -//! by \ref UARTDMAEnable(). The specified UART DMA features are disabled. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32DMAFlags is a bit mask of the DMA features to disable. -//! The parameter is the bitwise OR of any of the following values: -//! - UART_DMA_RX : Enable DMA for receive. -//! - UART_DMA_TX : Enable DMA for transmit. -//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Clear the requested bits in the UART DMA control register. - HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags; -} - -//***************************************************************************** -// -//! \brief Gets current receiver errors. -//! -//! This function returns the current state of each of the 4 receiver error -//! sources. The returned errors are equivalent to the four error bits -//! returned via the previous call to \ref UARTCharGet() or \ref UARTCharGetNonBlocking() -//! with the exception that the overrun error is set immediately the overrun -//! occurs rather than when a character is next read. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns a bitwise OR combination of the receiver error flags: -//! - \ref UART_RXERROR_FRAMING -//! - \ref UART_RXERROR_PARITY -//! - \ref UART_RXERROR_BREAK -//! - \ref UART_RXERROR_OVERRUN -// -//***************************************************************************** -__STATIC_INLINE uint32_t -UARTRxErrorGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Return the current value of the receive status register. - return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F); -} - -//***************************************************************************** -// -//! \brief Clears all reported receiver errors. -//! -//! This function is used to clear all receiver error conditions reported via -//! \ref UARTRxErrorGet(). If using the overrun, framing error, parity error or -//! break interrupts, this function must be called after clearing the interrupt -//! to ensure that later errors of the same type trigger another interrupt. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTRxErrorClear(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Any write to the Error Clear Register will clear all bits which are - // currently set. - HWREG(ui32Base + UART_O_ECR) = 0; -} - -//***************************************************************************** -// -//! \brief Enables hardware flow control for both CTS and RTS -//! -//! Hardware flow control is disabled by default. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTHwFlowControlEnable( uint32_t ui32Base ) -{ - // Check the arguments. - ASSERT( UARTBaseValid( ui32Base )); - - HWREG( ui32Base + UART_O_CTL ) |= ( UART_CTL_CTSEN | UART_CTL_RTSEN ); -} - -//***************************************************************************** -// -//! \brief Disables hardware flow control for both CTS and RTS -//! -//! Hardware flow control is disabled by default. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTHwFlowControlDisable( uint32_t ui32Base ) -{ - // Check the arguments. - ASSERT( UARTBaseValid( ui32Base )); - - HWREG( ui32Base + UART_O_CTL ) &= ~( UART_CTL_CTSEN | UART_CTL_RTSEN ); -} - - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_UARTFIFOLevelGet - #undef UARTFIFOLevelGet - #define UARTFIFOLevelGet ROM_UARTFIFOLevelGet - #endif - #ifdef ROM_UARTConfigSetExpClk - #undef UARTConfigSetExpClk - #define UARTConfigSetExpClk ROM_UARTConfigSetExpClk - #endif - #ifdef ROM_UARTConfigGetExpClk - #undef UARTConfigGetExpClk - #define UARTConfigGetExpClk ROM_UARTConfigGetExpClk - #endif - #ifdef ROM_UARTDisable - #undef UARTDisable - #define UARTDisable ROM_UARTDisable - #endif - #ifdef ROM_UARTCharGetNonBlocking - #undef UARTCharGetNonBlocking - #define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking - #endif - #ifdef ROM_UARTCharGet - #undef UARTCharGet - #define UARTCharGet ROM_UARTCharGet - #endif - #ifdef ROM_UARTCharPutNonBlocking - #undef UARTCharPutNonBlocking - #define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking - #endif - #ifdef ROM_UARTCharPut - #undef UARTCharPut - #define UARTCharPut ROM_UARTCharPut - #endif - #ifdef ROM_UARTIntRegister - #undef UARTIntRegister - #define UARTIntRegister ROM_UARTIntRegister - #endif - #ifdef ROM_UARTIntUnregister - #undef UARTIntUnregister - #define UARTIntUnregister ROM_UARTIntUnregister - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/udma.c b/third_party/ti/devices/cc26x0/driverlib/udma.c deleted file mode 100644 index 32807e11d..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/udma.c +++ /dev/null @@ -1,448 +0,0 @@ -/****************************************************************************** -* Filename: udma.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the uDMA controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "udma.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef uDMAChannelAttributeEnable - #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable - #undef uDMAChannelAttributeDisable - #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable - #undef uDMAChannelAttributeGet - #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet - #undef uDMAChannelControlSet - #define uDMAChannelControlSet NOROM_uDMAChannelControlSet - #undef uDMAChannelTransferSet - #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet - #undef uDMAChannelScatterGatherSet - #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet - #undef uDMAChannelSizeGet - #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet - #undef uDMAChannelModeGet - #define uDMAChannelModeGet NOROM_uDMAChannelModeGet -#endif - -//***************************************************************************** -// -// Enables attributes of a uDMA channel -// -//***************************************************************************** -void -uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, - uint32_t ui32Attr) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // Set the useburst bit for this channel if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_USEBURST) - { - HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; - } - - // Set the alternate control select bit for this channel, - // if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_ALTSELECT) - { - HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; - } - - // Set the high priority bit for this channel, if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; - } - - // Set the request mask bit for this channel, if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_REQMASK) - { - HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; - } -} - -//***************************************************************************** -// -// Disables attributes of an uDMA channel -// -//***************************************************************************** -void -uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, - uint32_t ui32Attr) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // Clear the useburst bit for this channel if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_USEBURST) - { - HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; - } - - // Clear the alternate control select bit for this channel, if set in - // ululAttr. - if(ui32Attr & UDMA_ATTR_ALTSELECT) - { - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; - } - - // Clear the high priority bit for this channel, if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; - } - - // Clear the request mask bit for this channel, if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_REQMASK) - { - HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; - } -} - -//***************************************************************************** -// -// Gets the enabled attributes of a uDMA channel -// -//***************************************************************************** -uint32_t -uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - uint32_t ui32Attr = 0; - - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Check to see if useburst bit is set for this channel. - if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_USEBURST; - } - - // Check to see if the alternate control bit is set for this channel. - if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_ALTSELECT; - } - - // Check to see if the high priority bit is set for this channel. - if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; - } - - // Check to see if the request mask bit is set for this channel. - if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_REQMASK; - } - - // Return the configuration flags. - return(ui32Attr); -} - -//***************************************************************************** -// -// Sets the control parameters for a uDMA channel control structure -// -//***************************************************************************** -void -uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, - uint32_t ui32Control) -{ - tDMAControlTable *pControlTable; - - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - - // Get the base address of the control table. - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // Get the current control word value and mask off the fields to be - // changed, then OR in the new settings. - pControlTable[ui32ChannelStructIndex].ui32Control = - ((pControlTable[ui32ChannelStructIndex].ui32Control & - ~(UDMA_DST_INC_M | - UDMA_SRC_INC_M | - UDMA_SIZE_M | - UDMA_ARB_M | - UDMA_NEXT_USEBURST)) | - ui32Control); -} - -//***************************************************************************** -// -// Sets the transfer parameters for a uDMA channel control structure -// -//***************************************************************************** -void -uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, - uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, - uint32_t ui32TransferSize) -{ - tDMAControlTable *pControlTable; - uint32_t ui32Control; - uint32_t ui32Inc; - uint32_t ui32BufferBytes; - - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); - ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); - ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); - ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); - - // Get the base address of the control table. - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // Get the current control word value and mask off the mode and size - // fields. - ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & - ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); - - // Adjust the mode if the alt control structure is selected. - if(ui32ChannelStructIndex & UDMA_ALT_SELECT) - { - if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - ui32Mode |= UDMA_MODE_ALT_SELECT; - } - } - - // Set the transfer size and mode in the control word (but don't write the - // control word yet as it could kick off a transfer). - ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); - - // Get the address increment value for the source, from the control word. - ui32Inc = (ui32Control & UDMA_SRC_INC_M); - - // Compute the ending source address of the transfer. If the source - // increment is set to none, then the ending address is the same as the - // beginning. - if(ui32Inc != UDMA_SRC_INC_NONE) - { - ui32Inc = ui32Inc >> UDMA_SRC_INC_S; - ui32BufferBytes = ui32TransferSize << ui32Inc; - pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - (1 << ui32Inc)); - } - - // Load the source ending address into the control block. - pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; - - // Get the address increment value for the destination, from the control - // word. - ui32Inc = ui32Control & UDMA_DST_INC_M; - - // Compute the ending destination address of the transfer. If the - // destination increment is set to none, then the ending address is the - // same as the beginning. - if(ui32Inc != UDMA_DST_INC_NONE) - { - // There is a special case if this is setting up a scatter-gather - // transfer. The destination pointer needs to point to the end of - // the alternate structure for this channel instead of calculating - // the end of the buffer in the normal way. - if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - pvDstAddr = - (void *)&pControlTable[ui32ChannelStructIndex | - UDMA_ALT_SELECT].ui32Spare; - } - // Not a scatter-gather transfer, calculate end pointer normally. - else - { - ui32Inc = ui32Inc >> UDMA_DST_INC_S; - ui32BufferBytes = ui32TransferSize << ui32Inc; - pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); - } - } - - // Load the destination ending address into the control block. - pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; - - // Write the new control word value. - pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; -} - -//***************************************************************************** -// -// Configures a uDMA channel for scatter-gather mode -// -//***************************************************************************** -void -uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, - uint32_t ui32TaskCount, void *pvTaskList, - uint32_t ui32IsPeriphSG) -{ - tDMAControlTable *pControlTable; - tDMAControlTable *pTaskTable; - - // Check the parameters. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - ASSERT(pvTaskList != 0); - ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); - ASSERT(ui32TaskCount != 0); - - // Get the base address of the control table. - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // Get a handy pointer to the task list. - pTaskTable = (tDMAControlTable *)pvTaskList; - - // Compute the ending address for the source pointer. This will be the - // last element of the last task in the task table. - pControlTable[ui32ChannelNum].pvSrcEndAddr = - &pTaskTable[ui32TaskCount - 1].ui32Spare; - - // Compute the ending address for the destination pointer. This will be - // the end of the alternate structure for this channel. - pControlTable[ui32ChannelNum].pvDstEndAddr = - &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; - - // Compute the control word. Most configurable items are fixed for - // scatter-gather. Item and increment sizes are all 32-bit and arb - // size must be 4. The count is the number of items in the task list - // times 4 (4 words per task). - pControlTable[ui32ChannelNum].ui32Control = - (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | - UDMA_SIZE_32 | UDMA_ARB_4 | - (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | - (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : - UDMA_MODE_MEM_SCATTER_GATHER)); - - // Scatter-gather operations can leave the alt bit set. So if doing - // back to back scatter-gather transfers, the second attempt may not - // work correctly because the alt bit is set. Therefore, clear the - // alt bit here to ensure that it is always cleared before a new SG - // transfer is started. - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; - -} - -//***************************************************************************** -// -// Gets the current transfer size for a uDMA channel control structure -// -//***************************************************************************** -uint32_t -uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) -{ - tDMAControlTable *pControlTable; - uint32_t ui32Control; - - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - - // Get the base address of the control table. - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // Get the current control word value and mask off all but the size field - // and the mode field. - ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & - (UDMA_XFER_SIZE_M | UDMA_MODE_M)); - - // If the size field and mode field are 0 then the transfer is finished - // and there are no more items to transfer. - if(ui32Control == 0) - { - return(0); - } - - // Otherwise, if either the size field or more field is non-zero, then - // not all the items have been transferred. - else - { - // Shift the size field and add one, then return to user. - return((ui32Control >> UDMA_XFER_SIZE_S) + 1); - } -} - -//***************************************************************************** -// -// Gets the transfer mode for a uDMA channel control structure -// -//***************************************************************************** -uint32_t -uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) -{ - tDMAControlTable *pControlTable; - uint32_t ui32Control; - - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - - // Get the base address of the control table. - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // Get the current control word value and mask off all but the mode field. - ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & - UDMA_MODE_M); - - // Check if scatter/gather mode, and if so, mask off the alt bit. - if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || - ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) - { - ui32Control &= ~UDMA_MODE_ALT_SELECT; - } - - // Return the mode to the caller. - return(ui32Control); -} diff --git a/third_party/ti/devices/cc26x0/driverlib/udma.h b/third_party/ti/devices/cc26x0/driverlib/udma.h deleted file mode 100644 index 510691b29..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/udma.h +++ /dev/null @@ -1,1240 +0,0 @@ -/****************************************************************************** -* Filename: udma.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the uDMA controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup udma_api -//! @{ -// -//***************************************************************************** - -#ifndef __UDMA_H__ -#define __UDMA_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_udma.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable - #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable - #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet - #define uDMAChannelControlSet NOROM_uDMAChannelControlSet - #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet - #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet - #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet - #define uDMAChannelModeGet NOROM_uDMAChannelModeGet -#endif - -//***************************************************************************** -// -//! \brief A structure that defines an entry in the channel control table. -//! -//! These fields are used by the uDMA controller and normally it is not necessary for -//! software to directly read or write fields in the table. -// -//***************************************************************************** -typedef struct -{ - volatile void *pvSrcEndAddr; //!< The ending source address of the data transfer. - volatile void *pvDstEndAddr; //!< The ending destination address of the data transfer. - volatile uint32_t ui32Control; //!< The channel control mode. - volatile uint32_t ui32Spare; //!< An unused location. -} -tDMAControlTable; - -//***************************************************************************** -// -//! \brief A helper macro for building scatter-gather task table entries. -//! -//! This macro is intended to be used to help populate a table of uDMA tasks -//! for a scatter-gather transfer. This macro will calculate the values for -//! the fields of a task structure entry based on the input parameters. -//! -//! There are specific requirements for the values of each parameter. No -//! checking is done so it is up to the caller to ensure that correct values -//! are used for the parameters. -//! -//! This macro is intended to be used to initialize individual entries of -//! a structure of tDMAControlTable type, like this: -//! -/*! -\verbatim - tDMAControlTable MyTaskList[] = - { - uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, - UDMA_SRC_INC_8, MySourceBuf, - UDMA_DST_INC_8, MyDestBuf, - UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), - uDMATaskStructEntry(Task2Count, ... ), - } -\endverbatim -*/ -//! \param ui32TransferCount is the count of items to transfer for this task. -//! It must be in the range 1-1024. -//! \param ui32ItemSize is the bit size of the items to transfer for this task. -//! It must be one of: -//! - \ref UDMA_SIZE_8 -//! - \ref UDMA_SIZE_16 -//! - \ref UDMA_SIZE_32 -//! \param ui32SrcIncrement is the bit size increment for source data. -//! It must be one of: -//! - \ref UDMA_SRC_INC_8 -//! - \ref UDMA_SRC_INC_16 -//! - \ref UDMA_SRC_INC_32 -//! - \ref UDMA_SRC_INC_NONE -//! \param pvSrcAddr is the starting address of the data to transfer. -//! \param ui32DstIncrement is the bit size increment for destination data. -//! It must be one of: -//! - \ref UDMA_DST_INC_8 -//! - \ref UDMA_DST_INC_16 -//! - \ref UDMA_DST_INC_32 -//! - \ref UDMA_DST_INC_NONE -//! \param pvDstAddr is the starting address of the destination data. -//! \param ui32ArbSize is the arbitration size to use for the transfer task. -//! This is used to select the arbitration size in powers of 2, from 1 to 1024. -//! It must be one of: -//! - \ref UDMA_ARB_1 -//! - \ref UDMA_ARB_2 -//! - \ref UDMA_ARB_4 -//! - ... -//! - \ref UDMA_ARB_1024 -//! \param ui32Mode is the transfer mode for this task. -//! Note that normally all tasks will be one of the scatter-gather modes while the -//! last task is a task list will be AUTO or BASIC. -//! It must be one of: -//! - \ref UDMA_MODE_BASIC -//! - \ref UDMA_MODE_AUTO -//! - \ref UDMA_MODE_MEM_SCATTER_GATHER -//! - \ref UDMA_MODE_PER_SCATTER_GATHER -//! -//! \return None (this is not a function) -// -//***************************************************************************** -#define uDMATaskStructEntry(ui32TransferCount, \ - ui32ItemSize, \ - ui32SrcIncrement, \ - pvSrcAddr, \ - ui32DstIncrement, \ - pvDstAddr, \ - ui32ArbSize, \ - ui32Mode) \ - { \ - (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \ - ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ - ((ui32SrcIncrement) >> 26)) - 1]))), \ - (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \ - ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ - ((ui32DstIncrement) >> 30)) - 1]))), \ - (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ - (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ - ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ - ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ - (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ - } - -//***************************************************************************** -// -// The hardware configured number of uDMA channels. -// -//***************************************************************************** -#define UDMA_NUM_CHANNELS 21 - -//***************************************************************************** -// -// The level of priority for the uDMA channels -// -//***************************************************************************** -#define UDMA_PRIORITY_LOW 0x00000000 -#define UDMA_PRIORITY_HIGH 0x00000001 - -//***************************************************************************** -// -// Flags that can be passed to uDMAChannelAttributeEnable(), -// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). -// -//***************************************************************************** -#define UDMA_ATTR_USEBURST 0x00000001 -#define UDMA_ATTR_ALTSELECT 0x00000002 -#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 -#define UDMA_ATTR_REQMASK 0x00000008 -#define UDMA_ATTR_ALL 0x0000000F - -//***************************************************************************** -// -// DMA control modes that can be passed to uDMAChannelModeSet() and returned -// uDMAChannelModeGet(). -// -//***************************************************************************** -#define UDMA_MODE_STOP 0x00000000 -#define UDMA_MODE_BASIC 0x00000001 -#define UDMA_MODE_AUTO 0x00000002 -#define UDMA_MODE_PINGPONG 0x00000003 -#define UDMA_MODE_MEM_SCATTER_GATHER \ - 0x00000004 -#define UDMA_MODE_PER_SCATTER_GATHER \ - 0x00000006 -#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_MODE_ALT_SELECT 0x00000001 - -//***************************************************************************** -// -// Channel configuration values that can be passed to uDMAControlSet(). -// -//***************************************************************************** -#define UDMA_DST_INC_8 0x00000000 -#define UDMA_DST_INC_16 0x40000000 -#define UDMA_DST_INC_32 0x80000000 -#define UDMA_DST_INC_NONE 0xC0000000 -#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment -#define UDMA_DST_INC_S 30 -#define UDMA_SRC_INC_8 0x00000000 -#define UDMA_SRC_INC_16 0x04000000 -#define UDMA_SRC_INC_32 0x08000000 -#define UDMA_SRC_INC_NONE 0x0c000000 -#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment -#define UDMA_SRC_INC_S 26 -#define UDMA_SIZE_8 0x00000000 -#define UDMA_SIZE_16 0x11000000 -#define UDMA_SIZE_32 0x22000000 -#define UDMA_SIZE_M 0x33000000 // Data Size -#define UDMA_SIZE_S 24 -#define UDMA_ARB_1 0x00000000 -#define UDMA_ARB_2 0x00004000 -#define UDMA_ARB_4 0x00008000 -#define UDMA_ARB_8 0x0000c000 -#define UDMA_ARB_16 0x00010000 -#define UDMA_ARB_32 0x00014000 -#define UDMA_ARB_64 0x00018000 -#define UDMA_ARB_128 0x0001c000 -#define UDMA_ARB_256 0x00020000 -#define UDMA_ARB_512 0x00024000 -#define UDMA_ARB_1024 0x00028000 -#define UDMA_ARB_M 0x0003C000 // Arbitration Size -#define UDMA_ARB_S 14 -#define UDMA_NEXT_USEBURST 0x00000008 -#define UDMA_XFER_SIZE_MAX 1024 -#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size -#define UDMA_XFER_SIZE_S 4 - -//***************************************************************************** -// -// Channel numbers to be passed to API functions that require a channel number -// ID. -// -//***************************************************************************** -#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 -#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data -#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data -#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data -#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data -#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event -#define UDMA_CHAN_AUX_SW 8 // AUX Software event -#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event -#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event -#define UDMA_CHAN_TIMER1_A 11 -#define UDMA_CHAN_TIMER1_B 12 -#define UDMA_CHAN_AON_PROG2 13 -#define UDMA_CHAN_DMA_PROG 14 -#define UDMA_CHAN_AON_RTC 15 -#define UDMA_CHAN_SSI1_RX 16 -#define UDMA_CHAN_SSI1_TX 17 -#define UDMA_CHAN_SW_EVT1 18 -#define UDMA_CHAN_SW_EVT2 19 -#define UDMA_CHAN_SW_EVT3 20 - -//***************************************************************************** -// -// Flags to be OR'd with the channel ID to indicate if the primary or alternate -// control structure should be used. -// -//***************************************************************************** -#define UDMA_PRI_SELECT 0x00000000 -#define UDMA_ALT_SELECT 0x00000020 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Checks a uDMA base address. -//! -//! This function determines if a uDMA module base address is valid. -//! -//! \param ui32Base specifies the uDMA module base address. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -uDMABaseValid(uint32_t ui32Base) -{ - return(ui32Base == UDMA0_BASE); -} -#endif - -//***************************************************************************** -// -//! \brief Enables the uDMA controller for use. -//! -//! This function enables the uDMA controller. The uDMA controller must be -//! enabled before it can be configured and used. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Set the master enable bit in the config register. - HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE; -} - -//***************************************************************************** -// -//! \brief Disables the uDMA controller for use. -//! -//! This function disables the uDMA controller. Once disabled, the uDMA -//! controller will not operate until re-enabled with \ref uDMAEnable(). -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -uDMADisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Clear the master enable bit in the config register. - HWREG(ui32Base + UDMA_O_CFG) = 0; -} - -//***************************************************************************** -// -//! \brief Gets the uDMA error status. -//! -//! This function returns the uDMA error status. It should be called from -//! within the uDMA error interrupt handler to determine if a uDMA error -//! occurred. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return Returns non-zero if a uDMA error is pending. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -uDMAErrorStatusGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Return the uDMA error status. - return(HWREG(ui32Base + UDMA_O_ERROR)); -} - -//***************************************************************************** -// -//! \brief Clears the uDMA error interrupt. -//! -//! This function clears a pending uDMA error interrupt. It should be called -//! from within the uDMA error interrupt handler to clear the interrupt. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAErrorStatusClear(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Clear the uDMA error interrupt. - HWREG(ui32Base + UDMA_O_ERROR) = UDMA_ERROR_STATUS; -} - -//***************************************************************************** -// -//! \brief Enables a uDMA channel for operation. -//! -//! This function enables a specific uDMA channel for use. This function must -//! be used to enable a channel before it can be used to perform a uDMA -//! transfer. -//! -//! When a uDMA transfer is completed, the channel will be automatically -//! disabled by the uDMA controller. Therefore, this function should be called -//! prior to starting up any new transfer. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel number to enable. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Set the bit for this channel in the enable set register. - HWREG(ui32Base + UDMA_O_SETCHANNELEN) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -//! \brief Disables a uDMA channel for operation. -//! -//! This function disables a specific uDMA channel. Once disabled, a channel -//! will not respond to uDMA transfer requests until re-enabled via -//! \ref uDMAChannelEnable(). -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel number to disable. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Set the bit for this channel in the enable clear register. - HWREG(ui32Base + UDMA_O_CLEARCHANNELEN) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -//! \brief Checks if a uDMA channel is enabled for operation. -//! -//! This function checks to see if a specific uDMA channel is enabled. This -//! can be used to check the status of a transfer, since the channel will -//! be automatically disabled at the end of a transfer. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel number to check. -//! -//! \return Returns status of uDMA channel. -//! - \c true : Channel is enabled. -//! - \c false : Disabled. -// -//***************************************************************************** -__STATIC_INLINE bool -uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // AND the specified channel bit with the enable register, and return the - // result. - return((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? - true : false); -} - -//***************************************************************************** -// -//! \brief Sets the base address for the channel control table. -//! -//! This function sets the base address of the channel control table. This -//! table resides in system memory and holds control information for each uDMA -//! channel. The table must be aligned on a 1024 byte boundary. The base -//! address must be set before any of the channel functions can be used. -//! Setting the base address of the primary control table will automatically -//! set the address for the alternate control table as the next memory -//! location after the primary control table. -//! -//! The size of the channel control table depends on the number of uDMA -//! channels, and which transfer modes are used. Refer to the introductory -//! text and the microcontroller datasheet for more information about the -//! channel control table. -//! -//! \note This register cannot be read when the controller is in the reset -//! state. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param pControlTable is a pointer to the 1024 byte aligned base address -//! of the uDMA channel control table. The address must be an absolute address -//! in system memory space. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(((uint32_t)pControlTable & ~0x3FF) == - (uint32_t)pControlTable); - ASSERT((uint32_t)pControlTable >= SRAM_BASE); - - // Program the base address into the register. - HWREG(ui32Base + UDMA_O_CTRL) = (uint32_t)pControlTable; -} - -//***************************************************************************** -// -//! \brief Gets the base address for the channel control table. -//! -//! This function gets the base address of the channel control table. This -//! table resides in system memory and holds control information for each uDMA -//! channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return Returns a pointer to the base address of the channel control table. -// -//***************************************************************************** -__STATIC_INLINE void * -uDMAControlBaseGet(uint32_t ui32Base) -{ - // Check the arguments. - - ASSERT(uDMABaseValid(ui32Base)); - // Read the current value of the control base register, and return it to - // the caller. - return((void *)HWREG(ui32Base + UDMA_O_CTRL)); -} - -//***************************************************************************** -// -//! \brief Gets the base address for the channel control table alternate structures. -//! -//! This function gets the base address of the second half of the channel -//! control table that holds the alternate control structures for each channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return Returns a pointer to the base address of the second half of the -//! channel control table. -// -//***************************************************************************** -__STATIC_INLINE void * -uDMAControlAlternateBaseGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Read the current value of the control base register, and return it to - // the caller. - return((void *)HWREG(ui32Base + UDMA_O_ALTCTRL)); -} - -//***************************************************************************** -// -//! \brief Requests a uDMA channel to start a transfer. -//! -//! This function allows software to request a uDMA channel to begin a -//! transfer. This could be used for performing a memory to memory transfer, -//! or if for some reason a transfer needs to be initiated by software instead -//! of the peripheral associated with that channel. -//! -//! \note If the channel is a software channel and interrupts are used, then -//! the completion will be signaled on the uDMA dedicated interrupt. If a -//! peripheral channel is used, then the completion will be signaled on the -//! peripheral's interrupt. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel number on which to request a uDMA -//! transfer. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Set the bit for this channel in the software uDMA request register. - HWREG(ui32Base + UDMA_O_SOFTREQ) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -//! \brief Enables attributes of a uDMA channel. -//! -//! This function is used to enable attributes of a uDMA channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel to configure. -//! \param ui32Attr is a combination of attributes for the channel. -//! The parameter is the bitwise OR of any of the following: -//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. -//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None -// -//***************************************************************************** -extern void uDMAChannelAttributeEnable(uint32_t ui32Base, - uint32_t ui32ChannelNum, - uint32_t ui32Attr); - -//***************************************************************************** -// -//! \brief Disables attributes of an uDMA channel. -//! -//! This function is used to disable attributes of a uDMA channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel to configure. -//! \param ui32Attr is a combination of attributes for the channel. -//! The parameter is the bitwise OR of any of the following: -//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. -//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None -// -//***************************************************************************** -extern void uDMAChannelAttributeDisable(uint32_t ui32Base, - uint32_t ui32ChannelNum, - uint32_t ui32Attr); - -//***************************************************************************** -// -//! \brief Gets the enabled attributes of a uDMA channel. -//! -//! This function returns a combination of flags representing the attributes of -//! the uDMA channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel to configure. -//! -//! \return Returns the bitwise OR of the attributes of the uDMA channel, which -//! can be any of the following: -//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. -//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -// -//***************************************************************************** -extern uint32_t uDMAChannelAttributeGet(uint32_t ui32Base, - uint32_t ui32ChannelNum); - -//***************************************************************************** -// -//! \brief Sets the control parameters for a uDMA channel control structure. -//! -//! This function is used to set control parameters for a uDMA transfer. These -//! are typically parameters that are not changed often. -//! -//! \note The address increment cannot be smaller than the data size. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: -//! - \ref UDMA_PRI_SELECT : Use primary data structure. -//! - \ref UDMA_ALT_SELECT : Use alternate data structure. -//! \param ui32Control is the bitwise OR of five values: -//! - Data size -//! - \ref UDMA_SIZE_8 : 8 bits. -//! - \ref UDMA_SIZE_16 : 16 bits. -//! - \ref UDMA_SIZE_32 : 32 bits. -//! - Source address increment -//! - \ref UDMA_SRC_INC_8 : 8 bits. -//! - \ref UDMA_SRC_INC_16 : 16 bits. -//! - \ref UDMA_SRC_INC_32 : 32 bits. -//! - \ref UDMA_SRC_INC_NONE : Non-incrementing. -//! - Destination address increment -//! - \ref UDMA_DST_INC_8 : 8 bits. -//! - \ref UDMA_DST_INC_16 : 16 bits. -//! - \ref UDMA_DST_INC_32 : 32 bits. -//! - \ref UDMA_DST_INC_NONE : Non-incrementing. -//! - Arbitration size. Determines how many items are transferred before -//! the uDMA controller re-arbitrates for the bus. In power of 2. -//! - \ref UDMA_ARB_1 -//! - \ref UDMA_ARB_2 -//! - \ref UDMA_ARB_4 -//! - \ref UDMA_ARB_8 -//! - ... -//! - \ref UDMA_ARB_1024 -//! - Force the channel to only respond to burst requests at the tail end of a scatter-gather transfer. -//! - \ref UDMA_NEXT_USEBURST -//! -//! \return None -// -//***************************************************************************** -extern void uDMAChannelControlSet(uint32_t ui32Base, - uint32_t ui32ChannelStructIndex, - uint32_t ui32Control); - -//***************************************************************************** -// -//! \brief Sets the transfer parameters for a uDMA channel control structure. -//! -//! This function is used to set the parameters for a uDMA transfer. These are -//! typically parameters that are changed often. The function -//! \ref uDMAChannelControlSet() MUST be called at least once for this channel prior -//! to calling this function. -//! -//! The \c pvSrcAddr and \c pvDstAddr parameters are pointers to the first -//! location of the data to be transferred. These addresses should be aligned -//! according to the item size. The compiler will take care of this if the -//! pointers are pointing to storage of the appropriate data type. -//! -//! The two scatter/gather modes, MEMORY and PERIPHERAL, are actually different -//! depending on whether the primary or alternate control structure is -//! selected. This function will look for the \ref UDMA_PRI_SELECT and -//! \ref UDMA_ALT_SELECT flag along with the channel number and will set the -//! scatter/gather mode as appropriate for the primary or alternate control -//! structure. -//! -//! The channel must also be enabled using \ref uDMAChannelEnable() after calling -//! this function. The transfer will not begin until the channel has been set -//! up and enabled. Note that the channel is automatically disabled after the -//! transfer is completed, meaning that \ref uDMAChannelEnable() must be called -//! again after setting up the next transfer. -//! -//! \note Great care must be taken to not modify a channel control structure -//! that is in use or else the results will be unpredictable, including the -//! possibility of undesired data transfers to or from memory or peripherals. -//! For BASIC and AUTO modes, it is safe to make changes when the channel is -//! disabled, or the \ref uDMAChannelModeGet() returns \ref UDMA_MODE_STOP. For -//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the -//! primary or alternate control structure only when the other is being used. -//! The \ref uDMAChannelModeGet() function will return \ref UDMA_MODE_STOP when a -//! channel control structure is inactive and safe to modify. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: -//! - \ref UDMA_PRI_SELECT : Use primary data structure. -//! - \ref UDMA_ALT_SELECT : Use alternate data structure. -//! \param ui32Mode is the type of uDMA transfer. -//! The parameter should be one of the following values: -//! - \ref UDMA_MODE_STOP : Stops the uDMA transfer. The controller sets the mode -//! to this value at the end of a transfer. -//! - \ref UDMA_MODE_BASIC : Perform a basic transfer based on request. -//! - \ref UDMA_MODE_AUTO to perform a transfer that will always complete once -//! started even if request is removed. -//! - \ref UDMA_MODE_PINGPONG : Set up a transfer that switches between the -//! primary and alternate control structures for the channel. This allows -//! use of ping-pong buffering for uDMA transfers. -//! - \ref UDMA_MODE_MEM_SCATTER_GATHER : Set up a memory scatter-gather transfer. -//! - \ref UDMA_MODE_PER_SCATTER_GATHER : Set up a peripheral scatter-gather transfer. -//! \param pvSrcAddr is the source address for the transfer. -//! \param pvDstAddr is the destination address for the transfer. -//! \param ui32TransferSize is the number of data items to transfer (\b NOT bytes). -//! -//! \return None -// -//***************************************************************************** -extern void uDMAChannelTransferSet(uint32_t ui32Base, - uint32_t ui32ChannelStructIndex, - uint32_t ui32Mode, void *pvSrcAddr, - void *pvDstAddr, uint32_t ui32TransferSize); - -//***************************************************************************** -// -//! \brief Configures a uDMA channel for scatter-gather mode. -//! -//! This function is used to configure a channel for scatter-gather mode. -//! The caller must have already set up a task list, and pass a pointer to -//! the start of the task list as the \c pvTaskList parameter. -//! -//! The \c ui32TaskCount parameter is the count of tasks in the task list, not the -//! size of the task list. -//! -//! The flag \c bIsPeriphSG should be used to indicate -//! if the scatter-gather should be configured for a peripheral or memory -//! scatter-gather operation. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the uDMA channel number. -//! \param ui32TaskCount is the number of scatter-gather tasks to execute. -//! \param pvTaskList is a pointer to the beginning of the scatter-gather -//! task list. -//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral -//! scatter-gather transfer (else it will be memory scatter-gather transfer) -//! -//! \return None -//! -//! \sa \ref uDMATaskStructEntry() -// -//***************************************************************************** -extern void uDMAChannelScatterGatherSet(uint32_t ui32Base, - uint32_t ui32ChannelNum, - uint32_t ui32TaskCount, - void *pvTaskList, - uint32_t ui32IsPeriphSG); - -//***************************************************************************** -// -//! \brief Gets the current transfer size for a uDMA channel control structure. -//! -//! This function is used to get the uDMA transfer size for a channel. The -//! transfer size is the number of items to transfer, where the size of an item -//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, -//! then the number of remaining items will be returned. If the transfer is -//! complete, then 0 will be returned. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: -//! - \ref UDMA_PRI_SELECT -//! - \ref UDMA_ALT_SELECT -//! -//! \return Returns the number of items remaining to transfer. -// -//***************************************************************************** -extern uint32_t uDMAChannelSizeGet(uint32_t ui32Base, - uint32_t ui32ChannelStructIndex); - -//***************************************************************************** -// -//! \brief Gets the transfer mode for a uDMA channel control structure. -//! -//! This function is used to get the transfer mode for the uDMA channel. It -//! can be used to query the status of a transfer on a channel. When the -//! transfer is complete the mode will be \ref UDMA_MODE_STOP. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: -//! - \ref UDMA_PRI_SELECT -//! - \ref UDMA_ALT_SELECT -//! -//! \return Returns the transfer mode of the specified channel and control -//! structure, which will be one of the following values: -//! - \ref UDMA_MODE_STOP -//! - \ref UDMA_MODE_BASIC -//! - \ref UDMA_MODE_AUTO -//! - \ref UDMA_MODE_PINGPONG -//! - \ref UDMA_MODE_MEM_SCATTER_GATHER -//! - \ref UDMA_MODE_PER_SCATTER_GATHER -// -//***************************************************************************** -extern uint32_t uDMAChannelModeGet(uint32_t ui32Base, - uint32_t ui32ChannelStructIndex); - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the uDMA controller in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! \note The interrupt handler for uDMA is for transfer completion when the -//! software channel is used, and for error interrupts. The interrupts for each -//! peripheral channel are handled through the individual peripheral interrupt -//! handlers. -//! -//! \param ui32Base is the base address of the uDMA module. -//! \param ui32IntChannel specifies which uDMA interrupt is to be registered. -//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts -//! from the uDMA software channel. -//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error -//! interrupts. -//! \param pfnHandler is a pointer to the function to be called when the -//! interrupt is activated. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel, - void (*pfnHandler)(void)) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(pfnHandler); - ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); - - // Register the interrupt handler. - IntRegister(ui32IntChannel, pfnHandler); - - // Enable the memory management fault. - IntEnable(ui32IntChannel); -} - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for the uDMA controller in the dynamic interrupt table. -//! -//! This function will disable and clear the handler to be called for the -//! specified uDMA interrupt. -//! -//! \param ui32Base is the base address of the uDMA module. -//! \param ui32IntChannel specifies which uDMA interrupt to unregister. -//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts -//! from the uDMA software channel. -//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error -//! interrupts. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); - - // Disable the interrupt. - IntDisable(ui32IntChannel); - - // Unregister the interrupt handler. - IntUnregister(ui32IntChannel); -} - -//***************************************************************************** -// -//! \brief Clears uDMA interrupt done status. -//! -//! Clears bits in the uDMA interrupt status register according to which bits -//! are set in \c ui32ChanMask. There is one bit for each channel. If a a bit -//! is set in \c ui32ChanMask, then that corresponding channel's interrupt -//! status will be cleared (if it was set). -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Clear the requested bits in the uDMA interrupt status register. - HWREG(ui32Base + UDMA_O_REQDONE) = ui32ChanMask; -} - -//***************************************************************************** -// -//! \brief Get the uDMA interrupt status. -//! -//! This function returns the interrupt status for the specified UDMA. This -//! function does not differentiate between software or hardware activated -//! interrupts. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE uint32_t -uDMAIntStatus(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Return the uDMA interrupt status register. - return (HWREG(ui32Base + UDMA_O_REQDONE)); -} - -//***************************************************************************** -// -//! \brief Enable interrupt on software event driven uDMA transfers. -//! -//! \note The main purpose of this function is to prevent propagation of uDMA -//! status signals to a peripheral, if a peripheral and a software event is -//! sharing the uDMA channel. If it is desired to initiate a transfer by -//! writing to a register inside the uDMA (this means a software driven -//! channel), then the uDMA status signals propagation need to be blocked to -//! the hardware peripherals. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32IntChannel identifies which uDMA interrupt to enable software -//! interrupts for. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); - - // Enable the channel. - HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 1; -} - -//***************************************************************************** -// -//! \brief Disable interrupt on software event driven uDMA transfers. -//! -//! This register disables the blocking of the uDMA status signals propagation -//! to the hardware peripheral connected to the uDMA on the \c ui32IntChannel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32IntChannel identifies which uDMA interrupt to disable software -//! interrupts for. -//! -//! \return None -//! -//! \sa \ref uDMAIntSwEventEnable() -// -//***************************************************************************** -__STATIC_INLINE void -uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); - - // Disable the SW channel. - HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 0; -} - -//***************************************************************************** -// -//! \brief Return the status of the uDMA module. -//! -//! \note This status register cannot be read when the controller is in the reset state. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return Current status of the uDMA module. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -uDMAGetStatus(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Read and return the status register. - return HWREG(ui32Base + UDMA_O_STATUS); -} - -//***************************************************************************** -// -//! \brief Set the priority of a uDMA channel. -//! -//! \note Writing 0 to a bit has no effect on the priority. To reset a channel -//! priority to the default value use \ref uDMAChannelPriorityClear(). -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is uDMA channel to set the priority for. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Set the channel priority to high. - HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -//! \brief Get the priority of a uDMA channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum The uDMA channel to get the priority for. -//! -//! \return Returns one of: -//! - \ref UDMA_PRIORITY_HIGH -//! - \ref UDMA_PRIORITY_LOW -// -//***************************************************************************** -__STATIC_INLINE bool -uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Return the channel priority. - return(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? - UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); -} - -//***************************************************************************** -// -//! \brief Clear the priority of a uDMA channel. -//! -//! \note Writing 0 to a bit has no effect on the priority. To set a channel -//! priority to high use \ref uDMAChannelPrioritySet(). -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum The uDMA channel to clear the priority for. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Clear the channel priority. - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_uDMAChannelAttributeEnable - #undef uDMAChannelAttributeEnable - #define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable - #endif - #ifdef ROM_uDMAChannelAttributeDisable - #undef uDMAChannelAttributeDisable - #define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable - #endif - #ifdef ROM_uDMAChannelAttributeGet - #undef uDMAChannelAttributeGet - #define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet - #endif - #ifdef ROM_uDMAChannelControlSet - #undef uDMAChannelControlSet - #define uDMAChannelControlSet ROM_uDMAChannelControlSet - #endif - #ifdef ROM_uDMAChannelTransferSet - #undef uDMAChannelTransferSet - #define uDMAChannelTransferSet ROM_uDMAChannelTransferSet - #endif - #ifdef ROM_uDMAChannelScatterGatherSet - #undef uDMAChannelScatterGatherSet - #define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet - #endif - #ifdef ROM_uDMAChannelSizeGet - #undef uDMAChannelSizeGet - #define uDMAChannelSizeGet ROM_uDMAChannelSizeGet - #endif - #ifdef ROM_uDMAChannelModeGet - #undef uDMAChannelModeGet - #define uDMAChannelModeGet ROM_uDMAChannelModeGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __UDMA_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/vims.c b/third_party/ti/devices/cc26x0/driverlib/vims.c deleted file mode 100644 index 42cc2da73..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/vims.c +++ /dev/null @@ -1,189 +0,0 @@ -/****************************************************************************** -* Filename: vims.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the VIMS. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "vims.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef VIMSConfigure - #define VIMSConfigure NOROM_VIMSConfigure - #undef VIMSModeSet - #define VIMSModeSet NOROM_VIMSModeSet - #undef VIMSModeGet - #define VIMSModeGet NOROM_VIMSModeGet - #undef VIMSModeSafeSet - #define VIMSModeSafeSet NOROM_VIMSModeSafeSet -#endif - -//***************************************************************************** -// -// Configures the VIMS. -// -//***************************************************************************** -void -VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT(VIMSBaseValid(ui32Base)); - - ui32Reg = HWREG(ui32Base + VIMS_O_CTL); - ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); - if(bRoundRobin) - { - ui32Reg |= VIMS_CTL_ARB_CFG; - } - if(bPrefetch) - { - ui32Reg |= VIMS_CTL_PREF_EN; - } - - // Set the Arbitration and prefetch mode. - HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; -} - -//***************************************************************************** -// -// Set the operational mode of the VIMS -// -//***************************************************************************** -void -VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT(VIMSBaseValid(ui32Base)); - - ASSERT((ui32Mode == VIMS_MODE_DISABLED) || - (ui32Mode == VIMS_MODE_ENABLED) || - (ui32Mode == VIMS_MODE_OFF)); - - // Set the mode. - ui32Reg = HWREG(ui32Base + VIMS_O_CTL); - ui32Reg &= ~VIMS_CTL_MODE_M; - ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); - - HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; -} - -//***************************************************************************** -// -// Get the current operational mode of the VIMS. -// -//***************************************************************************** -uint32_t -VIMSModeGet(uint32_t ui32Base) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT(VIMSBaseValid(ui32Base)); - - ui32Reg = HWREG(ui32Base + VIMS_O_STAT); - if(ui32Reg & VIMS_STAT_MODE_CHANGING) - { - return (VIMS_MODE_CHANGING); - } - else - { - return (ui32Reg & VIMS_STAT_MODE_M); - } -} - -//***************************************************************************** -// -// Safe setting of new VIMS mode -// - Function might be blocking -// - Can be called for any mode change (also if actually not changing mode) -// -//***************************************************************************** -void -VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) -{ - uint32_t currentMode; - - // Check the arguments. - ASSERT(VIMSBaseValid(ui32Base)); - ASSERT((ui32NewMode == VIMS_MODE_DISABLED) || - (ui32NewMode == VIMS_MODE_ENABLED) || - (ui32NewMode == VIMS_MODE_OFF)); - - // Make sure that only the mode bits are set in the input parameter - // (done just for security since it is critical to the code flow) - ui32NewMode &= VIMS_CTL_MODE_M; - - // Wait for any pending change to complete and get current VIMS mode - // (This is a blocking point but will typically only be a blocking point - // only if mode is changed multiple times with blocking=0) - do { - currentMode = VIMSModeGet( ui32Base ); - } while ( currentMode == VIMS_MODE_CHANGING ); - - // First check that it actually is a mode change request - if ( ui32NewMode != currentMode ) { - // Due to a hw-problem it is strongly recommended to go via VIMS_MODE_OFF - // when leaving VIMS_MODE_ENABLED (=VIMS_CTL_MODE_CACHE) - // (And no need to go via OFF, if OFF is the final state and will be set later) - if (( currentMode == VIMS_CTL_MODE_CACHE ) && - ( ui32NewMode != VIMS_CTL_MODE_OFF ) ) - { - VIMSModeSet( ui32Base, VIMS_MODE_OFF ); - - while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { - // Do nothing - wait for change to complete. - // (Needed blocking point but it takes only some few cycles) - } - } - // Set new mode - VIMSModeSet( ui32Base, ui32NewMode ); - - // Wait for final mode change to complete - if blocking is requested - if ( blocking ) { - while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { - // Do nothing - wait for change to complete. - } - } - } -} diff --git a/third_party/ti/devices/cc26x0/driverlib/vims.h b/third_party/ti/devices/cc26x0/driverlib/vims.h deleted file mode 100644 index 7a35af53d..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/vims.h +++ /dev/null @@ -1,371 +0,0 @@ -/****************************************************************************** -* Filename: vims.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the VIMS. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup vims_api -//! @{ -// -//***************************************************************************** - -#ifndef __VIMS_H__ -#define __VIMS_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_vims.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define VIMSConfigure NOROM_VIMSConfigure - #define VIMSModeSet NOROM_VIMSModeSet - #define VIMSModeGet NOROM_VIMSModeGet - #define VIMSModeSafeSet NOROM_VIMSModeSafeSet -#endif - -//***************************************************************************** -// -// Values that can be passed to VIMSModeSet() as the ui32IntFlags parameter, -// and returned from VIMSModeGet(). -// -//***************************************************************************** -#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE - // can not be changed at moment. -#define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled). -#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. -#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \brief Checks a VIMS base address. -//! -//! This function determines if the VIMS base address is valid. -//! -//! \param ui32Base is the base address of the VIMS. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -VIMSBaseValid(uint32_t ui32Base) -{ - return(ui32Base == VIMS_BASE); -} -#endif - -//***************************************************************************** -// -//! \brief Configures the VIMS. -//! -//! This function sets general control settings of the VIMS system. -//! -//! \note The VIMS mode must be set using the \ref VIMSModeSet() call. -//! -//! \param ui32Base is the base address of the VIMS. -//! \param bRoundRobin specifies the arbitration method. -//! - \c true : Round Robin arbitration between the two available read/write interfaces -//! (i.e. Icode/Dcode and Sysbus) is to be used. -//! - \c false : Strict arbitration will be used, where Icode/Dcode -//! is preferred over the Sysbus. -//! \param bPrefetch specifies if prefetching is to be used. -//! - \c true : Cache is to prefetch tag data for the following address. -//! - \c false : No prefetch. -//! -//! \return None -//! -//! \sa \ref VIMSModeSet() -// -//***************************************************************************** -extern void VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, - bool bPrefetch); - -//***************************************************************************** -// -//! \brief Set the operational mode of the VIMS. -//! -//! This function sets the operational mode of the VIMS. -//! -//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. -//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). -//! The GP RAM will not be operational (read/write will result in bus fault). -//! The Cache will not be operational. -//! Reads and writes to flash will be uncached. -//! After a short delay (approx. 1029 clock cycles) the VIMS will -//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). -//! -//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is -//! accessible: -//! The GP RAM will be accessible. -//! The Cache will not be operational. -//! Reads from flash will be uncached. -//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). -//! -//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. -//! The GP RAM will not be operational (read/write will result in bus fault). -//! The Cache will be operational for SYSCODE space. -//! Reads from flash in USERCODE space will be uncached. -//! -//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. -//! -//! \note The VIMS must be invalidated when switching mode. -//! This is done by setting VIMS_MODE_OFF before setting any new mode. -//! This is automatically handled in \ref VIMSModeSafeSet() -//! -//! \note It is highly recommended that the VIMS is put in disabled mode before -//! \b writing to flash, since the cache will not be updated nor invalidated -//! by flash writes. The line buffers should also be disabled when updating the -//! flash. Once \ref VIMSModeSet() is used to set the VIMS in -//! \ref VIMS_MODE_CHANGING mode, the user should check using -//! \ref VIMSModeGet() when the mode switches to \ref VIMS_MODE_DISABLED. Only when -//! the mode has changed the cache has been completely invalidated. -//! -//! \note Access from System Bus is never cached. Only access through ICODE -//! DCODE bus from the System CPU is cached. -//! -//! \param ui32Base is the base address of the VIMS. -//! \param ui32Mode is the operational mode. -//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) -//! - \ref VIMS_MODE_ENABLED (CACHE mode) -//! - \ref VIMS_MODE_OFF -//! -//! \return None -//! -//! \sa \ref VIMSModeGet() and \ref VIMSModeSafeSet() -// -//***************************************************************************** -extern void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode); - -//***************************************************************************** -// -//! \brief Get the current operational mode of the VIMS. -//! -//! This function returns the operational mode of the VIMS. -//! -//! \param ui32Base is the base address of the VIMS. -//! -//! \return Returns one of: -//! - \ref VIMS_MODE_CHANGING -//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) -//! - \ref VIMS_MODE_ENABLED (CACHE mode) -//! - \ref VIMS_MODE_OFF -//! -//! \sa \ref VIMSModeSet() -// -//***************************************************************************** -extern uint32_t VIMSModeGet(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Set the operational mode of the VIMS in a safe sequence. -//! -//! This function sets the operational mode of the VIMS in a safe sequence -//! -//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. -//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). -//! The GP RAM will not be operational (read/write will result in bus fault). -//! The Cache will not be operational (read/write to flash will be uncached). -//! After a short delay (approx. 1029 clock cycles) the VIMS will -//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). -//! -//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is -//! accessible: -//! The GP RAM will be accessible. -//! The Cache will not be operational. -//! Reads from flash will be uncached. -//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). -//! -//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. -//! The GP RAM will not be operational (read/write will result in bus fault). -//! The Cache will be operational for SYSCODE space. -//! Reads from flash in USERCODE space will be uncached. -//! -//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. -//! -//! \note The VIMS must be invalidated when switching mode. -//! This is done by setting VIMS_MODE_OFF before setting any new mode. -//! This is automatically handled in this function. -//! -//! \note It is highly recommended that the VIMS is put in disabled mode before -//! \b writing to flash, since the cache will not be updated nor invalidated -//! by flash writes. The line buffers should also be disabled when updating the -//! flash. -//! -//! \note Access from System Bus is never cached. Only access through ICODE -//! DCODE bus from the System CPU is cached. -//! -//! \param ui32Base is the base address of the VIMS. -//! \param ui32NewMode is the new operational mode: -//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) -//! - \ref VIMS_MODE_ENABLED (CACHE mode) -//! - \ref VIMS_MODE_OFF -//! \param blocking shall be set to TRUE if further code execution shall be -//! blocked (delayed) until mode change is completed. -//! -//! \return None -//! -//! \sa \ref VIMSModeSet() and \ref VIMSModeGet() -// -//***************************************************************************** -extern void VIMSModeSafeSet( uint32_t ui32Base , - uint32_t ui32NewMode , - bool blocking ); - -//***************************************************************************** -// -//! \brief Disable VIMS linebuffers. -//! -//! Linebuffers should only be disabled when attempting to update the flash, to -//! ensure that the content of the buffers is not stale. As soon as flash is -//! updated the linebuffers should be reenabled. Failing to enable -//! will have a performance impact. -//! -//! \param ui32Base is the base address of the VIMS. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -VIMSLineBufDisable(uint32_t ui32Base) -{ - // Disable line buffers - HWREG(ui32Base + VIMS_O_CTL) |= VIMS_CTL_IDCODE_LB_DIS_M | - VIMS_CTL_SYSBUS_LB_DIS_M; -} - -//***************************************************************************** -// -//! \brief Enable VIMS linebuffers. -//! -//! Linebuffers should only be disabled when attempting to update the flash, to -//! ensure that the content of the buffers is not stale. As soon as flash is -//! updated the linebuffers should be reenabled. Failing to enable -//! will have a performance impact. -//! -//! \param ui32Base is the base address of the VIMS. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -VIMSLineBufEnable(uint32_t ui32Base) -{ - // Enable linebuffers - HWREG(ui32Base + VIMS_O_CTL) &= ~(VIMS_CTL_IDCODE_LB_DIS_M | - VIMS_CTL_SYSBUS_LB_DIS_M); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_VIMSConfigure - #undef VIMSConfigure - #define VIMSConfigure ROM_VIMSConfigure - #endif - #ifdef ROM_VIMSModeSet - #undef VIMSModeSet - #define VIMSModeSet ROM_VIMSModeSet - #endif - #ifdef ROM_VIMSModeGet - #undef VIMSModeGet - #define VIMSModeGet ROM_VIMSModeGet - #endif - #ifdef ROM_VIMSModeSafeSet - #undef VIMSModeSafeSet - #define VIMSModeSafeSet ROM_VIMSModeSafeSet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __VIMS_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/watchdog.c b/third_party/ti/devices/cc26x0/driverlib/watchdog.c deleted file mode 100644 index 3527cff08..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/watchdog.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: wdt.c -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Driver for the Watchdog Timer. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "watchdog.h" - -// See watchdog.h for implementation diff --git a/third_party/ti/devices/cc26x0/driverlib/watchdog.h b/third_party/ti/devices/cc26x0/driverlib/watchdog.h deleted file mode 100644 index 3d8de3684..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/watchdog.h +++ /dev/null @@ -1,520 +0,0 @@ -/****************************************************************************** -* Filename: wdt.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the Watchdog Timer. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup wdt_api -//! @{ -// -//***************************************************************************** - -#ifndef __WDT_H__ -#define __WDT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_wdt.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOCK register. -// -//***************************************************************************** -#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked -#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and -// WDT_MIS registers. -// -//***************************************************************************** -#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The type of interrupt that can be generated by the watchdog. -// -//***************************************************************************** -#define WATCHDOG_INT_TYPE_INT 0x00000000 -#define WATCHDOG_INT_TYPE_NMI 0x00000004 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Determines if the watchdog timer is enabled. -//! -//! This function checks to see if the watchdog timer is enabled. -//! -//! \return Returns status of Watchdog Timer: -//! - \c true : Watchdog timer is enabled. -//! - \c false : Watchdog timer is disabled. -// -//***************************************************************************** -__STATIC_INLINE bool -WatchdogRunning(void) -{ - // See if the watchdog timer module is enabled, and return. - return((HWREG(WDT_BASE + WDT_O_CTL) & WDT_CTL_INTEN) ? true : false); -} - -//***************************************************************************** -// -//! \brief Enables the watchdog timer. -//! -//! This function enables the watchdog timer counter and interrupt. -//! -//! Once enabled, the watchdog interrupt can only be disabled by a hardware reset. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None -//! -//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogEnable(void) -{ - // Enable the watchdog timer module. - HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTEN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Enables the watchdog timer reset. -//! -//! This function enables the capability of the watchdog timer to issue a reset -//! to the processor after a second timeout condition. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None -//! -//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogResetEnable(void) -{ - // Enable the watchdog reset. - HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disables the watchdog timer reset. -//! -//! This function disables the capability of the watchdog timer to issue a -//! reset to the processor after a second timeout condition. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None -//! -//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogResetDisable(void) -{ - // Disable the watchdog reset. - HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Enables the watchdog timer lock mechanism. -//! -//! This function locks out write access to the watchdog timer configuration -//! registers. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogLock(void) -{ - // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK - // register causes the lock to go into effect. - HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_LOCKED; -} - -//***************************************************************************** -// -//! \brief Disables the watchdog timer lock mechanism. -//! -//! This function enables write access to the watchdog timer configuration -//! registers. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogUnlock(void) -{ - // Unlock watchdog register writes. - HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_UNLOCK; -} - -//***************************************************************************** -// -//! \brief Gets the state of the watchdog timer lock mechanism. -//! -//! This function returns the lock state of the watchdog timer registers. -//! -//! \return Returns state of lock mechanism. -//! - \c true : Watchdog timer registers are locked. -//! - \c false : Registers are not locked. -// -//***************************************************************************** -__STATIC_INLINE bool -WatchdogLockState(void) -{ - // Get the lock state. - return((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? - true : false); -} - -//***************************************************************************** -// -//! \brief Sets the watchdog timer reload value. -//! -//! This function configures the value to load into the watchdog timer when the -//! count reaches zero for the first time; if the watchdog timer is running -//! when this function is called, then the value is immediately loaded into the -//! watchdog timer counter. If the \c ui32LoadVal parameter is 0, then an -//! interrupt is immediately generated. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \param ui32LoadVal is the load value for the watchdog timer. -//! -//! \return None -//! -//! \sa \ref WatchdogLock(), \ref WatchdogUnlock(), \ref WatchdogReloadGet() -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogReloadSet(uint32_t ui32LoadVal) -{ - // Set the load register. - HWREG(WDT_BASE + WDT_O_LOAD) = ui32LoadVal; -} - -//***************************************************************************** -// -//! \brief Gets the watchdog timer reload value. -//! -//! This function gets the value that is loaded into the watchdog timer when -//! the count reaches zero for the first time. -//! -//! \return None -//! -//! \sa \ref WatchdogReloadSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -WatchdogReloadGet(void) -{ - // Get the load register. - return(HWREG(WDT_BASE + WDT_O_LOAD)); -} - -//***************************************************************************** -// -//! \brief Gets the current watchdog timer value. -//! -//! This function reads the current value of the watchdog timer. -//! -//! \return Returns the current value of the watchdog timer. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -WatchdogValueGet(void) -{ - // Get the current watchdog timer register value. - return(HWREG(WDT_BASE + WDT_O_VALUE)); -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! The watchdog timer interrupt must be enabled via \ref WatchdogIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! \ref WatchdogIntClear(). -//! -//! \note This function registers the standard watchdog interrupt handler. To -//! register the NMI watchdog handler, use \ref IntRegister() to register the -//! handler for the \b INT_NMI_FAULT interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! watchdog timer interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogIntRegister(void (*pfnHandler)(void)) -{ - // Register the interrupt handler. - IntRegister(INT_WDT_IRQ, pfnHandler); - - // Enable the watchdog timer interrupt. - IntEnable(INT_WDT_IRQ); -} - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. -//! -//! This function does the actual unregistering of the interrupt handler. This -//! function clears the handler to be called when a watchdog timer interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \note This function registers the standard watchdog interrupt handler. To -//! register the NMI watchdog handler, use \ref IntRegister() to register the -//! handler for the \b INT_NMI_FAULT interrupt. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogIntUnregister(void) -{ - // Disable the interrupt. - IntDisable(INT_WDT_IRQ); - - // Unregister the interrupt handler. - IntUnregister(INT_WDT_IRQ); -} - -//***************************************************************************** -// -//! \brief Enables the watchdog timer. -//! -//! This function enables the watchdog timer interrupt by calling \ref WatchdogEnable(). -//! -//! \return None -//! -//! \sa \ref WatchdogEnable() -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogIntEnable(void) -{ - // Enable the Watchdog interrupt. - WatchdogEnable(); -} - -//***************************************************************************** -// -//! \brief Gets the current watchdog timer interrupt status. -//! -//! This function returns the interrupt status for the watchdog timer module. -//! -//! \return Returns the interrupt status. -//! - 1 : Watchdog time-out has occurred. -//! - 0 : Watchdog time-out has not occurred. -//! -//! \sa \ref WatchdogIntClear(); -// -//***************************************************************************** -__STATIC_INLINE uint32_t -WatchdogIntStatus(void) -{ - // Return either the interrupt status or the raw interrupt status as - // requested. - return(HWREG(WDT_BASE + WDT_O_RIS)); -} - -//***************************************************************************** -// -//! \brief Clears the watchdog timer interrupt. -//! -//! The watchdog timer interrupt source is cleared, so that it no longer -//! asserts. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogIntClear(void) -{ - // Clear the interrupt source. - HWREG(WDT_BASE + WDT_O_ICR) = WATCHDOG_INT_TIMEOUT; -} - -//***************************************************************************** -// -//! \brief Sets the type of interrupt generated by the watchdog. -//! -//! This function sets the type of interrupt that is generated if the watchdog -//! timer expires. -//! -//! When configured to generate an NMI, the watchdog interrupt must still be -//! enabled with \ref WatchdogIntEnable(), and it must still be cleared inside the -//! NMI handler with \ref WatchdogIntClear(). -//! -//! \param ui32Type is the type of interrupt to generate. -//! - \ref WATCHDOG_INT_TYPE_INT : Generate a standard interrupt (default). -//! - \ref WATCHDOG_INT_TYPE_NMI : Generate a non-maskable interrupt (NMI). -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogIntTypeSet(uint32_t ui32Type) -{ - // Check the arguments. - ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) || - (ui32Type == WATCHDOG_INT_TYPE_NMI)); - - // Set the interrupt type. - HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTTYPE_BITN) = (ui32Type == WATCHDOG_INT_TYPE_INT)? 0 : 1; -} - -//***************************************************************************** -// -//! \brief Enables stalling of the watchdog timer during debug events. -//! -//! This function allows the watchdog timer to stop counting when the processor -//! is stopped by the debugger. By doing so, the watchdog is prevented from -//! expiring and resetting the system (if reset is enabled). The watchdog instead expires -//! after the appropriate number of processor cycles have been executed while -//! debugging (or at the appropriate time after the processor has been -//! restarted). -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogStallEnable(void) -{ - // Enable timer stalling. - HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disables stalling of the watchdog timer during debug events. -//! -//! This function disables the debug mode stall of the watchdog timer. By -//! doing so, the watchdog timer continues to count regardless of the processor -//! debug state. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogStallDisable(void) -{ - // Disable timer stalling. - HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 0; -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __WDT_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/driverlib/watchdog_doc.h b/third_party/ti/devices/cc26x0/driverlib/watchdog_doc.h deleted file mode 100644 index 799bf7c71..000000000 --- a/third_party/ti/devices/cc26x0/driverlib/watchdog_doc.h +++ /dev/null @@ -1,98 +0,0 @@ -/****************************************************************************** -* Filename: watchdog_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup wdt_api -//! @{ -//! \section sec_wdt Introduction -//! -//! The watchdog timer (WDT) is used to regain control when the system has failed due to unexpected -//! software behavior. The WDT can generate a non-maskable interrupt (NMI), a regular interrupt, or a -//! reset if the software fails to reload the watchdog before it times out. -//! -//! WDT has the following features: -//! - 32-bit down counter with a programmable load register. -//! - Programmable interrupt generation logic with interrupt masking and optional NMI function. -//! - Optional reset generation. -//! - Register protection from runaway software (lock). -//! - User-enabled stalling when the system CPU asserts the CPU Halt flag during debug. -//! -//! After the first time-out event, the 32-bit counter is re-loaded with the value of the Load register, -//! and the timer resumes counting down from that value. -//! If the timer counts down to its zero state again before the first time-out interrupt is cleared, -//! and the reset signal has been enabled, the WDT asserts its reset signal to the system. If the interrupt -//! is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the -//! value in the Load register, and counting resumes from that value. -//! -//! If Load register is written with a new value while the WDT counter is counting, then the counter is -//! loaded with the new value and continues counting. -//! Writing to the Load register does not clear an active interrupt. An interrupt must be explicitly cleared -//! by clearing the interrupt. -//! -//! The WDT counter runs at system HF clock divided by 32; however, when in powerdown it runs at -//! LF clock (32 kHz) - if the LF clock to the MCU domain has been enabled. -//! -//! \section sec_wdt_api API -//! -//! The API functions can be grouped like this: -//! -//! Watchdog configuration: -//! - \ref WatchdogIntTypeSet() -//! - \ref WatchdogResetEnable() -//! - \ref WatchdogResetDisable() -//! - \ref WatchdogReloadSet() -//! - \ref WatchdogEnable() -//! -//! Status: -//! - \ref WatchdogRunning() -//! - \ref WatchdogValueGet() -//! - \ref WatchdogReloadGet() -//! - \ref WatchdogIntStatus() -//! -//! Interrupt configuration: -//! - \ref WatchdogIntEnable() -//! - \ref WatchdogIntClear() -//! - \ref WatchdogIntRegister() -//! - \ref WatchdogIntUnregister() -//! -//! Register protection: -//! - \ref WatchdogLock() -//! - \ref WatchdogLockState() -//! - \ref WatchdogUnlock() -//! -//! Stall configuration for debugging: -//! - \ref WatchdogStallDisable() -//! - \ref WatchdogStallEnable() -//! -//! @} diff --git a/third_party/ti/devices/cc26x0/inc/asmdefs.h b/third_party/ti/devices/cc26x0/inc/asmdefs.h deleted file mode 100644 index 9e5a81587..000000000 --- a/third_party/ti/devices/cc26x0/inc/asmdefs.h +++ /dev/null @@ -1,151 +0,0 @@ -/****************************************************************************** -* Filename: asmdefs.h -* Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) -* Revision: 43803 -* -* Description: Macros to allow assembly code be portable among tool chains. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ASMDEFS_H__ -#define __ASMDEFS_H__ - -//***************************************************************************** -// -// The defines required for EW-ARM. -// -//***************************************************************************** -#ifdef __IAR_SYSTEMS_ICC__ - -// -// Section headers. -// -#define __LIBRARY__ module -#define __TEXT__ rseg CODE:CODE(2) -#define __DATA__ rseg DATA:DATA(2) -#define __BSS__ rseg DATA:DATA(2) -#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) - -// -// Assembler mnemonics. -// -#define __ALIGN__ alignrom 2 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ thumb -#define __WORD__ dcd -#define __INLINE_DATA__ data - -#endif // __IAR_SYSTEMS_ICC__ - -//***************************************************************************** -// -// The defines required for GCC. -// -//***************************************************************************** -#if defined(__GNUC__) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler mnemonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // __GNUC__ - -//***************************************************************************** -// -// The defines required for RV-MDK. -// -//***************************************************************************** -#if defined(__CC_ARM) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - thumb - require8 - preserve8 - -// -// Section headers. -// -#define __LIBRARY__ ; -#define __TEXT__ area ||.text||, code, readonly, align=2 -#define __DATA__ area ||.data||, data, align=2 -#define __BSS__ area ||.bss||, noinit, align=2 -#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 - -// -// Assembler mnemonics. -// -#define __ALIGN__ align 4 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ -#define __WORD__ dcd -#define __INLINE_DATA__ - -#endif // __CC_ARM - - -#endif // __ASMDEF_H__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_adi.h b/third_party/ti/devices/cc26x0/inc/hw_adi.h deleted file mode 100644 index b14a5f6b0..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_adi.h +++ /dev/null @@ -1,1182 +0,0 @@ -/****************************************************************************** -* Filename: hw_adi.h -* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) -* Revision: 42365 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_ADI_H__ -#define __HW_ADI_H__ - -//***************************************************************************** -// -// This file contains macros for controlling the ADI master and -// accessing ADI slave registers via the ADI Master. -// There are 3 categories of macros in this file: -// - macros that provide an offset to a register -// located within the DDI Master itself. -// - macros that define bits or bitfields -// within the DDI Master Registers. -// - macros that provide an "instruction offset" -// that are used when accessing a ADI Slave. -// -// The macros that that provide ADI Master register offsets and -// define bits and bitfields for those registers are the typical -// macros that appear in most hw_.h header files. In -// the following example ADI_O_SLAVECONF is a macro for a -// register offset and ADI_SLAVECONF_WAITFORACK is a macro for -// a bit in that register. This example code will set the WAITFORACK -// bit in register ADI_O_SLAVECONF of the ADI Master. (Note: this -// access the Master not the Slave). -// -// HWREG(ADI3_BASE + ADI_O_SLAVECONF) |= ADI_SLAVECONF_WAITFORACK; -// -// The "instruction offset" macros are used to pass an instruction to -// the ADI Master when accessing ADI slave registers. These macros are -// only used when accessing ADI Slave Registers. (Remember ADI -// Master Registers are accessed normally). -// -// The instructions supported when accessing an ADI Slave Register follow: -// - Direct Access to an ADI Slave register. I.e. read or -// write the register. -// - Set the specified bits in a ADI Slave register. -// - Clear the specified bits in a ADI Slave register. -// - Mask write of 4 bits to the a ADI Slave register. -// - Mask write of 8 bits to the a ADI Slave register. -// - Mask write of 16 bits to the a ADI Slave register. -// -// Note: only the "Direct Access" offset should be used when reading -// a ADI Slave register. Only 4-bit reads are supported and 8 bits write are -// supported natively. If accessing wider bitfields, the read/write operation -// will be spread out over a number of transactions. This is hidden for the -// user, but can potentially be very timeconsuming. Especially of running -// on a slow clock. -// -// The generic format of using these macros for a read follows: -// // Read low 8-bits in ADI_SLAVE_OFF -// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); -// -// // Read high 8-bits in ADI_SLAVE_OFF (data[31:16]) -// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); -// -// Notes: In the above example: -// - ADI_MASTER_BASE is the base address of the ADI Master defined -// in the hw_memmap.h header file. -// - ADI_SLAVE_OFF is the ADI Slave offset defined in the -// hw_.h header file (e.g. hw_adi_3_refsys_top.h for the refsys -// module). -// - ADI_O_DIR is the "instruction offset" macro defined in this -// file that specifies the Direct Access instruction. -// -// Writes can use any of the "instruction macros". -// The following examples do a "direct write" to an ADI Slave register -// ADI_SLAVE_OFF using different size operands: -// -// // ---------- DIRECT WRITES ---------- -// // Write 32-bits aligned -// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x12345678; -// -// // Write 16-bits aligned to high 16-bits then low 16-bits -// // Add 2 to get to high 16-bits. -// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0xabcd; -// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0xef01; -// -// // Write each byte at ADI_SLAVE_OFF, one at a time. -// // Add 1,2,or 3 to get to bytes 1,2, or 3. -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x33; -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 1) = 0x44; -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0x55; -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 3) = 0x66; -// -// // ---------- SET/CLR ---------- -// The set and clear functions behave similarly to eachother. Each -// can be performed on an 8-, 16-, or 32-bit operand. -// Examples follow: -// // Set all odd bits in a 32-bit words -// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_SET) = 0xaaaaaaaa; -// -// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand -// HWREG(DDI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_CLR) = 0x00ff0000; -// -// // Set even bits in byte 2 (data[23:16]) using 8-bit operand -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + 2 + ADI_O_CLR) = 0x55; -// -// // ---------- MASKED WRITES ---------- -// The mask writes are a bit different. They operate on nibbles, -// bytes, and 16-bit elements. Two operands are required; a 'mask' -// and 'data'; The operands are concatenated and written to the master. -// e.g. the mask and data are combined as follows for a 16 bit masked -// write: -// (mask << 16) | data; -// Examples follow: -// -// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). -// // Byte write is needed. -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_MASK4B01) = 0xf7; -// -// // Do an 4 bit masked write of 4 to data[7:4]). -// // Add 1 for next nibble -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + ADI_O_MASK4B01 + 1) = 0xf4; -// -//***************************************************************************** - -//***************************************************************************** -// -// The following are defines for the ADI master instruction offsets. -// -//***************************************************************************** -#define ADI_O_DIR 0x00000000 // Offset for the direct access - // instruction -#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. -#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. -#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. - // Data bit[n] is written if mask - // bit[n] is set ('1'). - // Bits 7:4 are mask. Bits 3:0 are data. - // Requires 'byte' write. -#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. - // Data bit[n] is written if mask - // bit[n] is set ('1'). Bits 15:8 are - // mask. Bits 7:0 are data. Requires - // 'short' write. -#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. - // Data bit[n] is written if mask - // bit[n] is set ('1'). Bits 31:16 - // are mask. Bits 15:0 are data. - // Requires 'long' write. - -//***************************************************************************** -// -// The following are defines for the ADI register offsets. -// -//***************************************************************************** -#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register -#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_SLAVESTAT register. -// -//***************************************************************************** -#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ - // signal. Writing 0 to this bit - // forces a sync with slave, - // ensuring that req will be 0. It - // is recommended to write 0 to - // this register before power down - // of the master. -#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 -#define ADI_SLAVESTAT_DI_REQ_S 1 -#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK - // signal -#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 -#define ADI_SLAVESTAT_DI_ACK_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_SLAVECONF register. -// -//***************************************************************************** -#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer - // accessible when this bit is set. - // (unless sticky_bit_overwrite is - // asserted on top module) -#define ADI_SLAVECONF_CONFLOCK_M \ - 0x00000080 -#define ADI_SLAVECONF_CONFLOCK_S 7 -#define ADI_SLAVECONF_WAITFORACK \ - 0x00000004 // A transaction on the ADI - // interface does not end until ack - // has been received from the slave - // when this bit is set. - -#define ADI_SLAVECONF_WAITFORACK_M \ - 0x00000004 -#define ADI_SLAVECONF_WAITFORACK_S 2 -#define ADI_SLAVECONF_ADICLKSPEED_M \ - 0x00000003 // Sets the period of an ADI - // transactions. All transactions - // takes an even number of clock - // cycles,- ADI clock rising edge - // occurs in the middle of the - // period. Data and ctrl to slave - // is set up in beginning of cycle, - // and data from slave is read in - // after the transaction 00: An ADI - // transaction takes 2 master clock - // cyclkes 01: An ADI transaction - // takes 4 master clock cycles 10: - // And ADI Transaction takes 8 - // master clock cycles 11: An ADI - // transaction takes 16 master - // clock cycles - -#define ADI_SLAVECONF_ADICLKSPEED_S 0 - -//***************************************************************************** -// -// The following are defines pseudo-magic numbers that should go away. -// New code should not use these registers and old code should be ported -// to not use these. -// -//***************************************************************************** -#define ADI_O_DIR03 0x00000000 // Direct access for adi byte - // offsets 0 to 3 -#define ADI_O_DIR47 0x00000004 // Direct access for adi byte - // offsets 4 to 7 -#define ADI_O_DIR811 0x00000008 // Direct access for adi byte - // offsets 8 to 11 -#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte - // offsets 12 to 15 -#define ADI_O_SET03 0x00000010 // Set register for ADI byte - // offsets 0 to 3 -#define ADI_O_SET47 0x00000014 // Set register for ADI byte - // offsets 4 to 7 -#define ADI_O_SET811 0x00000018 // Set register for ADI byte - // offsets 8 to 11 -#define ADI_O_SET1215 0x0000001C // Set register for ADI byte - // offsets 12 to 15 -#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte - // offsets 0 to 3 -#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte - // offsets 4 to 7 -#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte - // offsets 8 to 11 -#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte - // offsets 12 to 15 -#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register -#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration - // register -#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI - // Registers at byte offsets 0 and - // 1 -#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI - // Registers at byte offsets 2 and - // 3 -#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI - // Registers at byte offsets 4 and - // 5 -#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI - // Registers at byte offsets 6 and - // 7 -#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI - // Registers at byte offsets 8 and - // 9 -#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI - // Registers at byte offsets 10 and - // 11 -#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI - // Registers at byte offsets 12 and - // 13 -#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI - // Registers at byte offsets 14 and - // 15 -#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI - // Registers at byte offsets 0 and - // 1 -#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI - // Registers at byte offsets 2 and - // 3 -#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI - // Registers at byte offsets 4 and - // 5 -#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI - // Registers at byte offsets 6 and - // 7 -#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI - // Registers at byte offsets 8 and - // 9 -#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI - // Registers at byte offsets 10 and - // 11 -#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI - // Registers at byte offsets 12 and - // 13 -#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI - // Registers at byte offsets 14 and - // 15 -#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI - // Registers at byte offsets 0 and - // 1 -#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI - // Registers at byte offsets 2 and - // 3 -#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI - // Registers at byte offsets 4 and - // 5 -#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI - // Registers at byte offsets 6 and - // 7 -#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI - // Registers at byte offsets 8 and - // 9 -#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI - // Registers at byte offsets 10 and - // 11 -#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI - // Registers at byte offsets 12 and - // 13 -#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI - // Registers at byte offsets 14 and - // 15 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_DIR03 register. -// -//***************************************************************************** -#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 -#define ADI_DIR03_B3_S 24 -#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 -#define ADI_DIR03_B2_S 16 -#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 -#define ADI_DIR03_B1_S 8 -#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 -#define ADI_DIR03_B0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_DIR47 register. -// -//***************************************************************************** -#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 -#define ADI_DIR47_B3_S 24 -#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 -#define ADI_DIR47_B2_S 16 -#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 -#define ADI_DIR47_B1_S 8 -#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 -#define ADI_DIR47_B0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_DIR811 register. -// -//***************************************************************************** -#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register - // 11 -#define ADI_DIR811_B3_S 24 -#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register - // 10 -#define ADI_DIR811_B2_S 16 -#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 -#define ADI_DIR811_B1_S 8 -#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 -#define ADI_DIR811_B0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_DIR1215 register. -// -//***************************************************************************** -#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register - // 15 -#define ADI_DIR1215_B3_S 24 -#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register - // 14 -#define ADI_DIR1215_B2_S 16 -#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register - // 13 -#define ADI_DIR1215_B1_S 8 -#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register - // 12 -#define ADI_DIR1215_B0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_SET03 register. -// -//***************************************************************************** -#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the - // corresponding bit in ADI - // register 3. Read returns 0. -#define ADI_SET03_S3_S 24 -#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the - // corresponding bit in ADI - // register 2. Read returns 0. -#define ADI_SET03_S2_S 16 -#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the - // corresponding bit in ADI - // register 1. Read returns 0. -#define ADI_SET03_S1_S 8 -#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the - // corresponding bit in ADI - // register 0. Read returns 0. -#define ADI_SET03_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_SET47 register. -// -//***************************************************************************** -#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the - // corresponding bit in ADI - // register 7. Read returns 0. -#define ADI_SET47_S3_S 24 -#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the - // corresponding bit in ADI - // register 6. Read returns 0. -#define ADI_SET47_S2_S 16 -#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the - // corresponding bit in ADI - // register 5. Read returns 0. -#define ADI_SET47_S1_S 8 -#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the - // corresponding bit in ADI - // register 4. Read returns 0. -#define ADI_SET47_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_SET811 register. -// -//***************************************************************************** -#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the - // corresponding bit in ADI - // register 11. Read returns 0. -#define ADI_SET811_S3_S 24 -#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the - // corresponding bit in ADI - // register 10. Read returns 0. -#define ADI_SET811_S2_S 16 -#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the - // corresponding bit in ADI - // register 9. Read returns 0. -#define ADI_SET811_S1_S 8 -#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the - // corresponding bit in ADI - // register 8. Read returns 0. -#define ADI_SET811_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_SET1215 register. -// -//***************************************************************************** -#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the - // corresponding bit in ADI - // register 15. Read returns 0. -#define ADI_SET1215_S3_S 24 -#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the - // corresponding bit in ADI - // register 14. Read returns 0. -#define ADI_SET1215_S2_S 16 -#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the - // corresponding bit in ADI - // register 13. Read returns 0. -#define ADI_SET1215_S1_S 8 -#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the - // corresponding bit in ADI - // register 12. Read returns 0. -#define ADI_SET1215_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_CLR03 register. -// -//***************************************************************************** -#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the - // corresponding bit in ADI - // register 3 -#define ADI_CLR03_S3_S 24 -#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the - // corresponding bit in ADI - // register 2 -#define ADI_CLR03_S2_S 16 -#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the - // corresponding bit in ADI - // register 1 -#define ADI_CLR03_S1_S 8 -#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the - // corresponding bit in ADI - // register 0 -#define ADI_CLR03_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_CLR47 register. -// -//***************************************************************************** -#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the - // corresponding bit in ADI - // register 7 -#define ADI_CLR47_S3_S 24 -#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the - // corresponding bit in ADI - // register 6 -#define ADI_CLR47_S2_S 16 -#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the - // corresponding bit in ADI - // register 5 -#define ADI_CLR47_S1_S 8 -#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the - // corresponding bit in ADI - // register 4 -#define ADI_CLR47_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_CLR811 register. -// -//***************************************************************************** -#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the - // corresponding bit in ADI - // register 11 -#define ADI_CLR811_S3_S 24 -#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the - // corresponding bit in ADI - // register 10 -#define ADI_CLR811_S2_S 16 -#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the - // corresponding bit in ADI - // register 9 -#define ADI_CLR811_S1_S 8 -#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the - // corresponding bit in ADI - // register 8 -#define ADI_CLR811_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_CLR1215 register. -// -//***************************************************************************** -#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the - // corresponding bit in ADI - // register 15 -#define ADI_CLR1215_S3_S 24 -#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the - // corresponding bit in ADI - // register 14 -#define ADI_CLR1215_S2_S 16 -#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the - // corresponding bit in ADI - // register 13 -#define ADI_CLR1215_S1_S 8 -#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the - // corresponding bit in ADI - // register 12 -#define ADI_CLR1215_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_SLAVESTAT register. -// -//***************************************************************************** -#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ - // signal. Writing 0 to this bit - // forces a sync with slave, - // ensuring that req will be 0. It - // is recommended to write 0 to - // this register before power down - // of the master. -#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 -#define ADI_SLAVESTAT_DI_REQ_S 1 -#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK - // signal -#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 -#define ADI_SLAVESTAT_DI_ACK_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_SLAVECONF register. -// -//***************************************************************************** -#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer - // accessible when this bit is set. - // (unless sticky_bit_overwrite is - // asserted on top module) -#define ADI_SLAVECONF_CONFLOCK_M \ - 0x00000080 -#define ADI_SLAVECONF_CONFLOCK_S 7 -#define ADI_SLAVECONF_WAITFORACK \ - 0x00000004 // A transaction on the ADI - // interface does not end until ack - // has been received from the slave - // when this bit is set. - -#define ADI_SLAVECONF_WAITFORACK_M \ - 0x00000004 -#define ADI_SLAVECONF_WAITFORACK_S 2 -#define ADI_SLAVECONF_ADICLKSPEED_M \ - 0x00000003 // Sets the period of an ADI - // transactions. All transactions - // takes an even number of clock - // cycles,- ADI clock rising edge - // occurs in the middle of the - // period. Data and ctrl to slave - // is set up in beginning of cycle, - // and data from slave is read in - // after the transaction 00: An ADI - // transaction takes 2 master clock - // cyclkes 01: An ADI transaction - // takes 4 master clock cycles 10: - // And ADI Transaction takes 8 - // master clock cycles 11: An ADI - // transaction takes 16 master - // clock cycles - -#define ADI_SLAVECONF_ADICLKSPEED_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK4B01 register. -// -//***************************************************************************** -#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 1 -#define ADI_MASK4B01_M1H_S 28 -#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 1, - only bits selected - // by mask M1H will be affected by - // access -#define ADI_MASK4B01_D1H_S 24 -#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 1 -#define ADI_MASK4B01_M1L_S 20 -#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 1, - only bits selected - // by mask M1L will be affected by - // access -#define ADI_MASK4B01_D1L_S 16 -#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 0 -#define ADI_MASK4B01_M0H_S 12 -#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 0, - only bits selected - // by mask M0H will be affected by - // access -#define ADI_MASK4B01_D0H_S 8 -#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 0 -#define ADI_MASK4B01_M0L_S 4 -#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 0, - only bits selected - // by mask M0L will be affected by - // access -#define ADI_MASK4B01_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK4B23 register. -// -//***************************************************************************** -#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 3 -#define ADI_MASK4B23_M1H_S 28 -#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 3, - only bits selected - // by mask M1H will be affected by - // access -#define ADI_MASK4B23_D1H_S 24 -#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 3 -#define ADI_MASK4B23_M1L_S 20 -#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 3, - only bits selected - // by mask M1L will be affected by - // access -#define ADI_MASK4B23_D1L_S 16 -#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 2 -#define ADI_MASK4B23_M0H_S 12 -#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 2, - only bits selected - // by mask M0H will be affected by - // access -#define ADI_MASK4B23_D0H_S 8 -#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 2 -#define ADI_MASK4B23_M0L_S 4 -#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 2, - only bits selected - // by mask M0L will be affected by - // access -#define ADI_MASK4B23_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK4B45 register. -// -//***************************************************************************** -#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 5 -#define ADI_MASK4B45_M1H_S 28 -#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 5, - only bits selected - // by mask M1H will be affected by - // access -#define ADI_MASK4B45_D1H_S 24 -#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 5 -#define ADI_MASK4B45_M1L_S 20 -#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 5, - only bits selected - // by mask M1L will be affected by - // access -#define ADI_MASK4B45_D1L_S 16 -#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 4 -#define ADI_MASK4B45_M0H_S 12 -#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 4, - only bits selected - // by mask M0H will be affected by - // access -#define ADI_MASK4B45_D0H_S 8 -#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 4 -#define ADI_MASK4B45_M0L_S 4 -#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 4, - only bits selected - // by mask M0L will be affected by - // access -#define ADI_MASK4B45_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK4B67 register. -// -//***************************************************************************** -#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 7 -#define ADI_MASK4B67_M1H_S 28 -#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 7, - only bits selected - // by mask M1H will be affected by - // access -#define ADI_MASK4B67_D1H_S 24 -#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 7 -#define ADI_MASK4B67_M1L_S 20 -#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 7, - only bits selected - // by mask M1L will be affected by - // access -#define ADI_MASK4B67_D1L_S 16 -#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 6 -#define ADI_MASK4B67_M0H_S 12 -#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 6, - only bits selected - // by mask M0H will be affected by - // access -#define ADI_MASK4B67_D0H_S 8 -#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 6 -#define ADI_MASK4B67_M0L_S 4 -#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 6, - only bits selected - // by mask M0L will be affected by - // access -#define ADI_MASK4B67_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK4B89 register. -// -//***************************************************************************** -#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 9 -#define ADI_MASK4B89_M1H_S 28 -#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 9, - only bits selected - // by mask M1H will be affected by - // access -#define ADI_MASK4B89_D1H_S 24 -#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 9 -#define ADI_MASK4B89_M1L_S 20 -#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 9, - only bits selected - // by mask M1L will be affected by - // access -#define ADI_MASK4B89_D1L_S 16 -#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 8 -#define ADI_MASK4B89_M0H_S 12 -#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 8, - only bits selected - // by mask M0H will be affected by - // access -#define ADI_MASK4B89_D0H_S 8 -#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 8 -#define ADI_MASK4B89_M0L_S 4 -#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 8, - only bits selected - // by mask M0L will be affected by - // access -#define ADI_MASK4B89_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK4B1011 register. -// -//***************************************************************************** -#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 11 -#define ADI_MASK4B1011_M1H_S 28 -#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 11, - only bits - // selected by mask M1H will be - // affected by access -#define ADI_MASK4B1011_D1H_S 24 -#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 11 -#define ADI_MASK4B1011_M1L_S 20 -#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 11, - only bits - // selected by mask M1L will be - // affected by access -#define ADI_MASK4B1011_D1L_S 16 -#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 10 -#define ADI_MASK4B1011_M0H_S 12 -#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 10, - only bits - // selected by mask M0H will be - // affected by access -#define ADI_MASK4B1011_D0H_S 8 -#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 10 -#define ADI_MASK4B1011_M0L_S 4 -#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 10, - only bits - // selected by mask M0L will be - // affected by access -#define ADI_MASK4B1011_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK4B1213 register. -// -//***************************************************************************** -#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 13 -#define ADI_MASK4B1213_M1H_S 28 -#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 13, - only bits - // selected by mask M1H will be - // affected by access -#define ADI_MASK4B1213_D1H_S 24 -#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 13 -#define ADI_MASK4B1213_M1L_S 20 -#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 13, - only bits - // selected by mask M1L will be - // affected by access -#define ADI_MASK4B1213_D1L_S 16 -#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 12 -#define ADI_MASK4B1213_M0H_S 12 -#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 12, - only bits - // selected by mask M0H will be - // affected by access -#define ADI_MASK4B1213_D0H_S 8 -#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 12 -#define ADI_MASK4B1213_M0L_S 4 -#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 12, - only bits - // selected by mask M0L will be - // affected by access -#define ADI_MASK4B1213_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK4B1415 register. -// -//***************************************************************************** -#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 15 -#define ADI_MASK4B1415_M1H_S 28 -#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 15, - only bits - // selected by mask M1H will be - // affected by access -#define ADI_MASK4B1415_D1H_S 24 -#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 15 -#define ADI_MASK4B1415_M1L_S 20 -#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 15, - only bits - // selected by mask M1L will be - // affected by access -#define ADI_MASK4B1415_D1L_S 16 -#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 14 -#define ADI_MASK4B1415_M0H_S 12 -#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 14, - only bits - // selected by mask M0H will be - // affected by access -#define ADI_MASK4B1415_D0H_S 8 -#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 14 -#define ADI_MASK4B1415_M0L_S 4 -#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 14, - only bits - // selected by mask M0L will be - // affected by access -#define ADI_MASK4B1415_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK8B01 register. -// -//***************************************************************************** -#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 -#define ADI_MASK8B01_M1_S 24 -#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only - // bits selected by mask M1 will be - // affected by access -#define ADI_MASK8B01_D1_S 16 -#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 -#define ADI_MASK8B01_M0_S 8 -#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only - // bits selected by mask M0 will be - // affected by access -#define ADI_MASK8B01_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK8B23 register. -// -//***************************************************************************** -#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 -#define ADI_MASK8B23_M1_S 24 -#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only - // bits selected by mask M1 will be - // affected by access -#define ADI_MASK8B23_D1_S 16 -#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 -#define ADI_MASK8B23_M0_S 8 -#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only - // bits selected by mask M0 will be - // affected by access -#define ADI_MASK8B23_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK8B45 register. -// -//***************************************************************************** -#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 -#define ADI_MASK8B45_M1_S 24 -#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only - // bits selected by mask M1 will be - // affected by access -#define ADI_MASK8B45_D1_S 16 -#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 -#define ADI_MASK8B45_M0_S 8 -#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only - // bits selected by mask M0 will be - // affected by access -#define ADI_MASK8B45_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK8B67 register. -// -//***************************************************************************** -#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 -#define ADI_MASK8B67_M1_S 24 -#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only - // bits selected by mask M1 will be - // affected by access -#define ADI_MASK8B67_D1_S 16 -#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 -#define ADI_MASK8B67_M0_S 8 -#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only - // bits selected by mask M0 will be - // affected by access -#define ADI_MASK8B67_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK8B89 register. -// -//***************************************************************************** -#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 -#define ADI_MASK8B89_M1_S 24 -#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only - // bits selected by mask M1 will be - // affected by access -#define ADI_MASK8B89_D1_S 16 -#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 -#define ADI_MASK8B89_M0_S 8 -#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only - // bits selected by mask M0 will be - // affected by access -#define ADI_MASK8B89_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK8B1011 register. -// -//***************************************************************************** -#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 -#define ADI_MASK8B1011_M1_S 24 -#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - - // only bits selected by mask M1 - // will be affected by access -#define ADI_MASK8B1011_D1_S 16 -#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 -#define ADI_MASK8B1011_M0_S 8 -#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - - // only bits selected by mask M0 - // will be affected by access -#define ADI_MASK8B1011_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK8B1213 register. -// -//***************************************************************************** -#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 -#define ADI_MASK8B1213_M1_S 24 -#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - - // only bits selected by mask M1 - // will be affected by access -#define ADI_MASK8B1213_D1_S 16 -#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 -#define ADI_MASK8B1213_M0_S 8 -#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - - // only bits selected by mask M0 - // will be affected by access -#define ADI_MASK8B1213_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK8B1415 register. -// -//***************************************************************************** -#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 -#define ADI_MASK8B1415_M1_S 24 -#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - - // only bits selected by mask M1 - // will be affected by access -#define ADI_MASK8B1415_D1_S 16 -#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 -#define ADI_MASK8B1415_M0_S 8 -#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - - // only bits selected by mask M0 - // will be affected by access -#define ADI_MASK8B1415_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B01 register. -// -//***************************************************************************** -#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 -#define ADI_MASK16B01_M_S 16 -#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at - // offsets 0 and 1, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B01_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B23 register. -// -//***************************************************************************** -#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 -#define ADI_MASK16B23_M_S 16 -#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at - // offsets 2 and 3, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B23_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B45 register. -// -//***************************************************************************** -#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 -#define ADI_MASK16B45_M_S 16 -#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at - // offsets 4 and 5, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B45_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B67 register. -// -//***************************************************************************** -#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 -#define ADI_MASK16B67_M_S 16 -#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at - // offsets 6 and 7, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B67_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B89 register. -// -//***************************************************************************** -#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 -#define ADI_MASK16B89_M_S 16 -#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at - // offsets 8 and 9, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B89_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B1011 register. -// -//***************************************************************************** -#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 -#define ADI_MASK16B1011_M_S 16 -#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at - // offsets 10 and 11, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B1011_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B1213 register. -// -//***************************************************************************** -#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 -#define ADI_MASK16B1213_M_S 16 -#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at - // offsets 12 and 13, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B1213_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B1415 register. -// -//***************************************************************************** -#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 -#define ADI_MASK16B1415_M_S 16 -#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at - // offsets 14 and 15, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B1415_D_S 0 - -#endif // __HW_ADI_H__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_adi_2_refsys.h b/third_party/ti/devices/cc26x0/inc/hw_adi_2_refsys.h deleted file mode 100644 index 07f45f3cd..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_adi_2_refsys.h +++ /dev/null @@ -1,362 +0,0 @@ -/****************************************************************************** -* Filename: hw_adi_2_refsys_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_ADI_2_REFSYS_H__ -#define __HW_ADI_2_REFSYS_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// ADI_2_REFSYS component -// -//***************************************************************************** -// Internal -#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 - -// Internal -#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A - -// Internal -#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B - -// Internal -#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_REFSYSCTL0 -// -//***************************************************************************** -// Field: [4:0] TRIM_IREF -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL0 -// -//***************************************************************************** -// Field: [7:4] VTRIM_UDIG -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 - -// Field: [3:0] VTRIM_BOD -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL1 -// -//***************************************************************************** -// Field: [7:4] VTRIM_COARSE -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 - -// Field: [3:0] VTRIM_DIG -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL2 -// -//***************************************************************************** -// Field: [2:0] VTRIM_DELTA -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL3 -// -//***************************************************************************** -// Field: [7:6] ITRIM_DIGLDO_LOAD -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 - -// Field: [5:3] ITRIM_DIGLDO -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// BIAS_120P Internal. Only to be used through TI provided API. -// BIAS_100P Internal. Only to be used through TI provided API. -// BIAS_80P Internal. Only to be used through TI provided API. -// BIAS_60P Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 - -// Field: [2:0] ITRIM_UDIGLDO -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL4 -// -//***************************************************************************** -// Field: [6:5] UDIG_ITEST_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 - -// Field: [4:2] DIG_ITEST_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 - -// Field: [1] BIAS_DIS -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 - -// Field: [0] UDIG_LDO_EN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// EN Internal. Only to be used through TI provided API. -// DIS Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL5 -// -//***************************************************************************** -// Field: [3] IMON_ITEST_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 - -// Field: [2:0] TESTSEL -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// VDD_AON Internal. Only to be used through TI provided API. -// VREF_AMP Internal. Only to be used through TI provided API. -// ITEST Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_HPOSCCTL0 -// -//***************************************************************************** -// Field: [7] FILTER_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 - -// Field: [6:5] BIAS_RECHARGE_DLY -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// MIN_DLY_X8 Internal. Only to be used through TI provided API. -// MIN_DLY_X4 Internal. Only to be used through TI provided API. -// MIN_DLY_X2 Internal. Only to be used through TI provided API. -// MIN_DLY_X1 Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 - -// Field: [4:3] TUNE_CAP -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// SHIFT_M108 Internal. Only to be used through TI provided API. -// SHIFT_M70 Internal. Only to be used through TI provided API. -// SHIFT_M35 Internal. Only to be used through TI provided API. -// SHIFT_0 Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 - -// Field: [2:1] SERIES_CAP -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 - -// Field: [0] DIV3_BYPASS -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// HPOSC_2520MHZ Internal. Only to be used through TI provided API. -// HPOSC_840MHZ Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_HPOSCCTL1 -// -//***************************************************************************** -// Field: [5] BIAS_DIS -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 - -// Field: [4] PWRDET_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 - -// Field: [3:0] BIAS_RES_SET -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_HPOSCCTL2 -// -//***************************************************************************** -// Field: [7] BIAS_HOLD_MODE_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 - -// Field: [6] TESTMUX_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 - -// Field: [5:4] ATEST_SEL -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 - -// Field: [3:0] CURRMIRR_RATIO -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 - - -#endif // __ADI_2_REFSYS__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_adi_3_refsys.h b/third_party/ti/devices/cc26x0/inc/hw_adi_3_refsys.h deleted file mode 100644 index d9e0ced9b..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_adi_3_refsys.h +++ /dev/null @@ -1,481 +0,0 @@ -/****************************************************************************** -* Filename: hw_adi_3_refsys_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_ADI_3_REFSYS_H__ -#define __HW_ADI_3_REFSYS_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// ADI_3_REFSYS component -// -//***************************************************************************** -// Analog Test Control -#define ADI_3_REFSYS_O_SPARE0 0x00000001 - -// Internal -#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 - -// Internal -#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 - -// Internal -#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 - -// Internal -#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 - -// DCDC Control 0 -#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 - -// DCDC Control 1 -#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 - -// DCDC Control 2 -#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 - -// DCDC Control 3 -#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 - -// Internal -#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A - -// Internal -#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_SPARE0 -// -//***************************************************************************** -// Field: [7:0] SPARE0 -// -// Software should not rely on the value of a reserved. Writing any other value -// than the reset value may result in undefined behavior. -#define ADI_3_REFSYS_SPARE0_SPARE0_W 8 -#define ADI_3_REFSYS_SPARE0_SPARE0_M 0x000000FF -#define ADI_3_REFSYS_SPARE0_SPARE0_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_REFSYSCTL0 -// -//***************************************************************************** -// Field: [7:0] TESTCTL -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// BMCOMPOUT Internal. Only to be used through TI provided API. -// VTEMP Internal. Only to be used through TI provided API. -// VREF0P8V Internal. Only to be used through TI provided API. -// VBGUNBUFF Internal. Only to be used through TI provided API. -// VBG Internal. Only to be used through TI provided API. -// IREF4U Internal. Only to be used through TI provided API. -// IVREF4U Internal. Only to be used through TI provided API. -// IPTAT2U Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_REFSYSCTL1 -// -//***************************************************************************** -// Field: [7:3] TRIM_VDDS_BOD -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// POS_27 Internal. Only to be used through TI provided API. -// POS_26 Internal. Only to be used through TI provided API. -// POS_25 Internal. Only to be used through TI provided API. -// POS_24 Internal. Only to be used through TI provided API. -// POS_31 Internal. Only to be used through TI provided API. -// POS_30 Internal. Only to be used through TI provided API. -// POS_29 Internal. Only to be used through TI provided API. -// POS_28 Internal. Only to be used through TI provided API. -// POS_19 Internal. Only to be used through TI provided API. -// POS_18 Internal. Only to be used through TI provided API. -// POS_17 Internal. Only to be used through TI provided API. -// POS_16 Internal. Only to be used through TI provided API. -// POS_23 Internal. Only to be used through TI provided API. -// POS_22 Internal. Only to be used through TI provided API. -// POS_21 Internal. Only to be used through TI provided API. -// POS_20 Internal. Only to be used through TI provided API. -// POS_11 Internal. Only to be used through TI provided API. -// POS_10 Internal. Only to be used through TI provided API. -// POS_9 Internal. Only to be used through TI provided API. -// POS_8 Internal. Only to be used through TI provided API. -// POS_15 Internal. Only to be used through TI provided API. -// POS_14 Internal. Only to be used through TI provided API. -// POS_13 Internal. Only to be used through TI provided API. -// POS_12 Internal. Only to be used through TI provided API. -// POS_3 Internal. Only to be used through TI provided API. -// POS_2 Internal. Only to be used through TI provided API. -// POS_1 Internal. Only to be used through TI provided API. -// POS_0 Internal. Only to be used through TI provided API. -// POS_7 Internal. Only to be used through TI provided API. -// POS_6 Internal. Only to be used through TI provided API. -// POS_5 Internal. Only to be used through TI provided API. -// POS_4 Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 - -// Field: [2] BATMON_COMP_TEST_EN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// EN Internal. Only to be used through TI provided API. -// DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 - -// Field: [1:0] TESTCTL -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// IPTAT1U Internal. Only to be used through TI provided API. -// BMCOMPIN Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_REFSYSCTL2 -// -//***************************************************************************** -// Field: [7:4] TRIM_VREF -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 - -// Field: [1:0] TRIM_TSENSE -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_REFSYSCTL3 -// -//***************************************************************************** -// Field: [7] BOD_BG_TRIM_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 - -// Field: [6] VTEMP_EN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// EN Internal. Only to be used through TI provided API. -// DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 - -// Field: [5:0] TRIM_VBG -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL0 -// -//***************************************************************************** -// Field: [7:5] GLDO_ISRC -// -// Set charge and re-charge current level. -// 2's complement encoding. -// -// 0x0: Default 11mA. -// 0x3: Max 15mA. -// 0x4: Max 5mA -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 - -// Field: [4:0] VDDR_TRIM -// -// Set the VDDR voltage. -// Proprietary encoding. -// -// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. -// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. -// Step size = 16mV -// -// 0x00: Default, about 1.63V. -// 0x05: Typical voltage after trim voltage 1.71V. -// 0x15: Max voltage 1.96V. -// 0x16: Min voltage 1.47V. -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL1 -// -//***************************************************************************** -// Field: [7:6] IPTAT_TRIM -// -// Trim GLDO bias current. -// Proprietary encoding. -// -// 0x0: Default -// 0x1: Increase GLDO bias by 1.3x. -// 0x2: Increase GLDO bias by 1.6x. -// 0x3: Decrease GLDO bias by 0.7x. -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 - -// Field: [5] VDDR_OK_HYST -// -// Increase the hysteresis for when VDDR is considered ok. -// -// 0: Hysteresis = 60mV -// 1: Hysteresis = 70mV -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 - -// Field: [4:0] VDDR_TRIM_SLEEP -// -// Set the min VDDR voltage threshold during sleep mode. -// Proprietary encoding. -// -// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. -// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. -// Step size = 16mV -// -// 0x00: Default, about 1.63V. -// 0x19: Typical voltage after trim voltage 1.52V. -// 0x15: Max voltage 1.96V. -// 0x16: Min voltage 1.47V. -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL2 -// -//***************************************************************************** -// Field: [6] TURNON_EA_SW -// -// Turn on erroramp switch -// -// 0: Erroramp Off (Default) -// 1: Erroramp On. Turns on GLDO error amp switch. -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 - -// Field: [5] TEST_VDDR -// -// Connect VDDR to ATEST bus -// -// 0: Not connected. -// 1: Connected -// -// Set TESTSEL = 0x0 first before setting this bit. -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 - -// Field: [4] BIAS_DIS -// -// Disable dummy bias current. -// -// 0: Dummy bias current on (Default) -// 1: Dummy bias current off -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 - -// Field: [3:0] TESTSEL -// -// Select signal for test bus, one hot. -// ENUMs: -// VDDROK VDDR_OK connected to test bus. -// IB1U 1uA bias current connected to test bus. -// PASSGATE Pass transistor gate voltage connected to test -// bus. -// ERRAMP_OUT Error amp output voltage connected to test bus. -// NC No signal connected to test bus. -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL3 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL4 -// -//***************************************************************************** -// Field: [7:6] DEADTIME_TRIM -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 - -// Field: [5:3] LOW_EN_SEL -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 - -// Field: [2:0] HIGH_EN_SEL -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL5 -// -//***************************************************************************** -// Field: [5] TESTN -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 -#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 - -// Field: [4] TESTP -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 -#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 -#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 - -// Field: [3] DITHER_EN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// EN Internal. Only to be used through TI provided API. -// DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 - -// Field: [2:0] IPEAK -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 - - -#endif // __ADI_3_REFSYS__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_adi_4_aux.h b/third_party/ti/devices/cc26x0/inc/hw_adi_4_aux.h deleted file mode 100644 index 5af3ce4ac..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_adi_4_aux.h +++ /dev/null @@ -1,490 +0,0 @@ -/****************************************************************************** -* Filename: hw_adi_4_aux_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_ADI_4_AUX_H__ -#define __HW_ADI_4_AUX_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// ADI_4_AUX component -// -//***************************************************************************** -// Internal -#define ADI_4_AUX_O_MUX0 0x00000000 - -// Internal -#define ADI_4_AUX_O_MUX1 0x00000001 - -// Internal -#define ADI_4_AUX_O_MUX2 0x00000002 - -// Internal -#define ADI_4_AUX_O_MUX3 0x00000003 - -// Current Source -#define ADI_4_AUX_O_ISRC 0x00000004 - -// Comparator -#define ADI_4_AUX_O_COMP 0x00000005 - -// Internal -#define ADI_4_AUX_O_MUX4 0x00000007 - -// ADC Control 0 -#define ADI_4_AUX_O_ADC0 0x00000008 - -// ADC Control 1 -#define ADI_4_AUX_O_ADC1 0x00000009 - -// ADC Reference 0 -#define ADI_4_AUX_O_ADCREF0 0x0000000A - -// ADC Reference 1 -#define ADI_4_AUX_O_ADCREF1 0x0000000B - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_MUX0 -// -//***************************************************************************** -// Field: [3:0] COMPA_REF -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// ADCVREFP Internal. Only to be used through TI provided API. -// VDDS Internal. Only to be used through TI provided API. -// VSS Internal. Only to be used through TI provided API. -// DCOUPL Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX0_COMPA_REF_W 4 -#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F -#define ADI_4_AUX_MUX0_COMPA_REF_S 0 -#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 -#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 -#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 -#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 -#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_MUX1 -// -//***************************************************************************** -// Field: [7:0] COMPA_IN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// AUXIO0 Internal. Only to be used through TI provided API. -// AUXIO1 Internal. Only to be used through TI provided API. -// AUXIO2 Internal. Only to be used through TI provided API. -// AUXIO3 Internal. Only to be used through TI provided API. -// AUXIO4 Internal. Only to be used through TI provided API. -// AUXIO5 Internal. Only to be used through TI provided API. -// AUXIO6 Internal. Only to be used through TI provided API. -// AUXIO7 Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX1_COMPA_IN_W 8 -#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF -#define ADI_4_AUX_MUX1_COMPA_IN_S 0 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO0 0x00000080 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO1 0x00000040 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO2 0x00000020 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO3 0x00000010 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO4 0x00000008 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO5 0x00000004 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO6 0x00000002 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO7 0x00000001 -#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_MUX2 -// -//***************************************************************************** -// Field: [7:3] ADCCOMPB_IN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// VDDS Internal. Only to be used through TI provided API. -// VSS Internal. Only to be used through TI provided API. -// DCOUPL Internal. Only to be used through TI provided API. -// ATEST1 Internal. Only to be used through TI provided API. -// ATEST0 Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 - -// Field: [2:0] COMPB_REF -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// VDDS Internal. Only to be used through TI provided API. -// VSS Internal. Only to be used through TI provided API. -// DCOUPL Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX2_COMPB_REF_W 3 -#define ADI_4_AUX_MUX2_COMPB_REF_M 0x00000007 -#define ADI_4_AUX_MUX2_COMPB_REF_S 0 -#define ADI_4_AUX_MUX2_COMPB_REF_VDDS 0x00000004 -#define ADI_4_AUX_MUX2_COMPB_REF_VSS 0x00000002 -#define ADI_4_AUX_MUX2_COMPB_REF_DCOUPL 0x00000001 -#define ADI_4_AUX_MUX2_COMPB_REF_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_MUX3 -// -//***************************************************************************** -// Field: [7:0] ADCCOMPB_IN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// AUXIO0 Internal. Only to be used through TI provided API. -// AUXIO1 Internal. Only to be used through TI provided API. -// AUXIO2 Internal. Only to be used through TI provided API. -// AUXIO3 Internal. Only to be used through TI provided API. -// AUXIO4 Internal. Only to be used through TI provided API. -// AUXIO5 Internal. Only to be used through TI provided API. -// AUXIO6 Internal. Only to be used through TI provided API. -// AUXIO7 Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO0 0x00000080 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO1 0x00000040 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO2 0x00000020 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO3 0x00000010 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO4 0x00000008 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO5 0x00000004 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO6 0x00000002 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO7 0x00000001 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_ISRC -// -//***************************************************************************** -// Field: [7:2] TRIM -// -// Adjust current from current source. -// -// Output currents may be combined to get desired total current. -// ENUMs: -// 11P75U 11.75 uA -// 4P5U 4.5 uA -// 2P0U 2.0 uA -// 1P0U 1.0 uA -// 0P5U 0.5 uA -// 0P25U 0.25 uA -// NC No current connected -#define ADI_4_AUX_ISRC_TRIM_W 6 -#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC -#define ADI_4_AUX_ISRC_TRIM_S 2 -#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 -#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 -#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 -#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 -#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 -#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 -#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 - -// Field: [0] EN -// -// Current source enable -#define ADI_4_AUX_ISRC_EN 0x00000001 -#define ADI_4_AUX_ISRC_EN_M 0x00000001 -#define ADI_4_AUX_ISRC_EN_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_COMP -// -//***************************************************************************** -// Field: [7] COMPA_REF_RES_EN -// -// Enables 400kohm resistance from COMPA reference node to ground. Used with -// COMPA_REF_CURR_EN to generate voltage reference for cap-sense. -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 - -// Field: [6] COMPA_REF_CURR_EN -// -// Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires -// ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for -// cap-sense. -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 - -// Field: [5:3] COMPB_TRIM -// -// COMPB voltage reference trim temperature coded: -// ENUMs: -// DIV4 Divide reference by 4 -// DIV3 Divide reference by 3 -// DIV2 Divide reference by 2 -// DIV1 No reference division -#define ADI_4_AUX_COMP_COMPB_TRIM_W 3 -#define ADI_4_AUX_COMP_COMPB_TRIM_M 0x00000038 -#define ADI_4_AUX_COMP_COMPB_TRIM_S 3 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV4 0x00000038 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV3 0x00000018 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV2 0x00000008 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV1 0x00000000 - -// Field: [2] COMPB_EN -// -// COMPB enable -#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 -#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 -#define ADI_4_AUX_COMP_COMPB_EN_S 2 - -// Field: [0] COMPA_EN -// -// COMPA enable -#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 -#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 -#define ADI_4_AUX_COMP_COMPA_EN_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_MUX4 -// -//***************************************************************************** -// Field: [7:0] COMPA_REF -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// AUXIO0 Internal. Only to be used through TI provided API. -// AUXIO1 Internal. Only to be used through TI provided API. -// AUXIO2 Internal. Only to be used through TI provided API. -// AUXIO3 Internal. Only to be used through TI provided API. -// AUXIO4 Internal. Only to be used through TI provided API. -// AUXIO5 Internal. Only to be used through TI provided API. -// AUXIO6 Internal. Only to be used through TI provided API. -// AUXIO7 Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX4_COMPA_REF_W 8 -#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF -#define ADI_4_AUX_MUX4_COMPA_REF_S 0 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO0 0x00000080 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO1 0x00000040 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO2 0x00000020 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO3 0x00000010 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO4 0x00000008 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO5 0x00000004 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO6 0x00000002 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO7 0x00000001 -#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_ADC0 -// -//***************************************************************************** -// Field: [7] SMPL_MODE -// -// ADC Sampling mode: -// -// 0: Synchronous mode -// 1: Asynchronous mode -// -// The ADC does a sample-and-hold before conversion. In synchronous mode the -// sampling starts when the ADC clock detects a rising edge on the trigger -// signal. Jitter/uncertainty will be inferred in the detection if the trigger -// signal originates from a domain that is asynchronous to the ADC clock. -// SMPL_CYCLE_EXP determines the the duration of sampling. -// Conversion starts immediately after sampling ends. -// -// In asynchronous mode the sampling is continuous when enabled. Sampling ends -// and conversion starts immediately with the rising edge of the trigger -// signal. Sampling restarts when the conversion has finished. -// Asynchronous mode is useful when it is important to avoid jitter in the -// sampling instant of an externally driven signal -#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 -#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 -#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 - -// Field: [6:3] SMPL_CYCLE_EXP -// -// Controls the sampling duration before conversion when the ADC is operated in -// synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous -// mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us. -// ENUMs: -// 10P9_MS 65536x 6 MHz clock periods = 10.9ms -// 5P46_MS 32768x 6 MHz clock periods = 5.46ms -// 2P73_MS 16384x 6 MHz clock periods = 2.73ms -// 1P37_MS 8192x 6 MHz clock periods = 1.37ms -// 682_US 4096x 6 MHz clock periods = 682us -// 341_US 2048x 6 MHz clock periods = 341us -// 170_US 1024x 6 MHz clock periods = 170us -// 85P3_US 512x 6 MHz clock periods = 85.3us -// 42P6_US 256x 6 MHz clock periods = 42.6us -// 21P3_US 128x 6 MHz clock periods = 21.3us -// 10P6_US 64x 6 MHz clock periods = 10.6us -// 5P3_US 32x 6 MHz clock periods = 5.3us -// 2P7_US 16x 6 MHz clock periods = 2.7us -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 - -// Field: [1] RESET_N -// -// Reset ADC digital subchip, active low. ADC must be reset every time it is -// reconfigured. -// -// 0: Reset -// 1: Normal operation -#define ADI_4_AUX_ADC0_RESET_N 0x00000002 -#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 -#define ADI_4_AUX_ADC0_RESET_N_S 1 - -// Field: [0] EN -// -// ADC Enable -// -// 0: Disable -// 1: Enable -#define ADI_4_AUX_ADC0_EN 0x00000001 -#define ADI_4_AUX_ADC0_EN_M 0x00000001 -#define ADI_4_AUX_ADC0_EN_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_ADC1 -// -//***************************************************************************** -// Field: [0] SCALE_DIS -// -// Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 -#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 -#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_ADCREF0 -// -//***************************************************************************** -// Field: [6] REF_ON_IDLE -// -// Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE = 0. -// -// Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us sampling time) -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 - -// Field: [5] IOMUX -// -// Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 -#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 -#define ADI_4_AUX_ADCREF0_IOMUX_S 5 - -// Field: [4] EXT -// -// Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADCREF0_EXT 0x00000010 -#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 -#define ADI_4_AUX_ADCREF0_EXT_S 4 - -// Field: [3] SRC -// -// ADC reference source: -// -// 0: Fixed reference = 4.3V -// 1: Relative reference = VDDS -#define ADI_4_AUX_ADCREF0_SRC 0x00000008 -#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 -#define ADI_4_AUX_ADCREF0_SRC_S 3 - -// Field: [0] EN -// -// ADC reference module enable: -// -// 0: ADC reference module powered down -// 1: ADC reference module enabled -#define ADI_4_AUX_ADCREF0_EN 0x00000001 -#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 -#define ADI_4_AUX_ADCREF0_EN_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_ADCREF1 -// -//***************************************************************************** -// Field: [5:0] VTRIM -// -// Trim output voltage of ADC fixed reference (64 steps, 2's complement). -// Applies only for ADCREF0.SRC = 0. -// -// Examples: -// 0x00 - nominal voltage 1.43V -// 0x01 - nominal + 0.4% 1.435V -// 0x3F - nominal - 0.4% 1.425V -// 0x1F - maximum voltage 1.6V -// 0x20 - minimum voltage 1.3V -#define ADI_4_AUX_ADCREF1_VTRIM_W 6 -#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F -#define ADI_4_AUX_ADCREF1_VTRIM_S 0 - - -#endif // __ADI_4_AUX__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aon_batmon.h b/third_party/ti/devices/cc26x0/inc/hw_aon_batmon.h deleted file mode 100644 index 8b19b7af5..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aon_batmon.h +++ /dev/null @@ -1,340 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_batmon_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_BATMON_H__ -#define __HW_AON_BATMON_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_BATMON component -// -//***************************************************************************** -// Internal -#define AON_BATMON_O_CTL 0x00000000 - -// Internal -#define AON_BATMON_O_MEASCFG 0x00000004 - -// Internal -#define AON_BATMON_O_TEMPP0 0x0000000C - -// Internal -#define AON_BATMON_O_TEMPP1 0x00000010 - -// Internal -#define AON_BATMON_O_TEMPP2 0x00000014 - -// Internal -#define AON_BATMON_O_BATMONP0 0x00000018 - -// Internal -#define AON_BATMON_O_BATMONP1 0x0000001C - -// Internal -#define AON_BATMON_O_IOSTRP0 0x00000020 - -// Internal -#define AON_BATMON_O_FLASHPUMPP0 0x00000024 - -// Last Measured Battery Voltage -#define AON_BATMON_O_BAT 0x00000028 - -// Battery Update -#define AON_BATMON_O_BATUPD 0x0000002C - -// Temperature -#define AON_BATMON_O_TEMP 0x00000030 - -// Temperature Update -#define AON_BATMON_O_TEMPUPD 0x00000034 - -//***************************************************************************** -// -// Register: AON_BATMON_O_CTL -// -//***************************************************************************** -// Field: [1] CALC_EN -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_CTL_CALC_EN 0x00000002 -#define AON_BATMON_CTL_CALC_EN_BITN 1 -#define AON_BATMON_CTL_CALC_EN_M 0x00000002 -#define AON_BATMON_CTL_CALC_EN_S 1 - -// Field: [0] MEAS_EN -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_CTL_MEAS_EN 0x00000001 -#define AON_BATMON_CTL_MEAS_EN_BITN 0 -#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 -#define AON_BATMON_CTL_MEAS_EN_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_MEASCFG -// -//***************************************************************************** -// Field: [1:0] PER -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// 32CYC Internal. Only to be used through TI provided API. -// 16CYC Internal. Only to be used through TI provided API. -// 8CYC Internal. Only to be used through TI provided API. -// CONT Internal. Only to be used through TI provided API. -#define AON_BATMON_MEASCFG_PER_W 2 -#define AON_BATMON_MEASCFG_PER_M 0x00000003 -#define AON_BATMON_MEASCFG_PER_S 0 -#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 -#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 -#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 -#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMPP0 -// -//***************************************************************************** -// Field: [7:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP0_CFG_W 8 -#define AON_BATMON_TEMPP0_CFG_M 0x000000FF -#define AON_BATMON_TEMPP0_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMPP1 -// -//***************************************************************************** -// Field: [5:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP1_CFG_W 6 -#define AON_BATMON_TEMPP1_CFG_M 0x0000003F -#define AON_BATMON_TEMPP1_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMPP2 -// -//***************************************************************************** -// Field: [4:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP2_CFG_W 5 -#define AON_BATMON_TEMPP2_CFG_M 0x0000001F -#define AON_BATMON_TEMPP2_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_BATMONP0 -// -//***************************************************************************** -// Field: [5:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_BATMONP0_CFG_W 6 -#define AON_BATMON_BATMONP0_CFG_M 0x0000003F -#define AON_BATMON_BATMONP0_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_BATMONP1 -// -//***************************************************************************** -// Field: [5:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_BATMONP1_CFG_W 6 -#define AON_BATMON_BATMONP1_CFG_M 0x0000003F -#define AON_BATMON_BATMONP1_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_IOSTRP0 -// -//***************************************************************************** -// Field: [5:4] CFG2 -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_IOSTRP0_CFG2_W 2 -#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 -#define AON_BATMON_IOSTRP0_CFG2_S 4 - -// Field: [3:0] CFG1 -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_IOSTRP0_CFG1_W 4 -#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F -#define AON_BATMON_IOSTRP0_CFG1_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_FLASHPUMPP0 -// -//***************************************************************************** -// Field: [8] FALLB -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 -#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 -#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 -#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 - -// Field: [7:6] HIGHLIM -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 - -// Field: [5] LOWLIM -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 - -// Field: [4] OVR -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 -#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 -#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 -#define AON_BATMON_FLASHPUMPP0_OVR_S 4 - -// Field: [3:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_CFG_W 4 -#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F -#define AON_BATMON_FLASHPUMPP0_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_BAT -// -//***************************************************************************** -// Field: [10:8] INT -// -// Integer part: -// -// 0x0: 0V + fractional part -// ... -// 0x3: 3V + fractional part -// 0x4: 4V + fractional part -#define AON_BATMON_BAT_INT_W 3 -#define AON_BATMON_BAT_INT_M 0x00000700 -#define AON_BATMON_BAT_INT_S 8 - -// Field: [7:0] FRAC -// -// Fractional part, standard binary fractional encoding. -// -// 0x00: .0V -// ... -// 0x20: 1/8 = .125V -// 0x40: 1/4 = .25V -// 0x80: 1/2 = .5V -// ... -// 0xA0: 1/2 + 1/8 = .625V -// ... -// 0xFF: Max -#define AON_BATMON_BAT_FRAC_W 8 -#define AON_BATMON_BAT_FRAC_M 0x000000FF -#define AON_BATMON_BAT_FRAC_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_BATUPD -// -//***************************************************************************** -// Field: [0] STAT -// -// -// 0: No update since last clear -// 1: New battery voltage is present. -// -// Write 1 to clear the status. -#define AON_BATMON_BATUPD_STAT 0x00000001 -#define AON_BATMON_BATUPD_STAT_BITN 0 -#define AON_BATMON_BATUPD_STAT_M 0x00000001 -#define AON_BATMON_BATUPD_STAT_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMP -// -//***************************************************************************** -// Field: [16:8] INT -// -// Integer part (signed) of temperature value. -// Total value = INTEGER + FRACTIONAL -// 2's complement encoding -// -// 0x100: Min value -// 0x1D8: -40C -// 0x1FF: -1C -// 0x00: 0C -// 0x1B: 27C -// 0x55: 85C -// 0xFF: Max value -#define AON_BATMON_TEMP_INT_W 9 -#define AON_BATMON_TEMP_INT_M 0x0001FF00 -#define AON_BATMON_TEMP_INT_S 8 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMPUPD -// -//***************************************************************************** -// Field: [0] STAT -// -// -// 0: No update since last clear -// 1: New temperature is present. -// -// Write 1 to clear the status. -#define AON_BATMON_TEMPUPD_STAT 0x00000001 -#define AON_BATMON_TEMPUPD_STAT_BITN 0 -#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 -#define AON_BATMON_TEMPUPD_STAT_S 0 - - -#endif // __AON_BATMON__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aon_event.h b/third_party/ti/devices/cc26x0/inc/hw_aon_event.h deleted file mode 100644 index fad920bb9..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aon_event.h +++ /dev/null @@ -1,1533 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_event_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_EVENT_H__ -#define __HW_AON_EVENT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_EVENT component -// -//***************************************************************************** -// Wake-up Selector For MCU -#define AON_EVENT_O_MCUWUSEL 0x00000000 - -// Wake-up Selector For AUX -#define AON_EVENT_O_AUXWUSEL 0x00000004 - -// Event Selector For MCU Event Fabric -#define AON_EVENT_O_EVTOMCUSEL 0x00000008 - -// RTC Capture Event Selector For AON_RTC -#define AON_EVENT_O_RTCSEL 0x0000000C - -//***************************************************************************** -// -// Register: AON_EVENT_O_MCUWUSEL -// -//***************************************************************************** -// Field: [29:24] WU3_EV -// -// MCU Wakeup Source #3 -// -// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the -// MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 -#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD31 0x1F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD30 0x1E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD29 0x1D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD28 0x1C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD27 0x1B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD26 0x1A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD25 0x19000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD24 0x18000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD23 0x17000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD22 0x16000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD21 0x15000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD20 0x14000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD19 0x13000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD18 0x12000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD17 0x11000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD16 0x10000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD15 0x0F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD14 0x0E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD13 0x0D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD12 0x0C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD11 0x0B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD10 0x0A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD9 0x09000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD8 0x08000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD7 0x07000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD6 0x06000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD5 0x05000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD4 0x04000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD3 0x03000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD2 0x02000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD1 0x01000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD0 0x00000000 - -// Field: [21:16] WU2_EV -// -// MCU Wakeup Source #2 -// -// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the -// MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 -#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD31 0x001F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD30 0x001E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD29 0x001D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD28 0x001C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD27 0x001B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD26 0x001A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD25 0x00190000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD24 0x00180000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD23 0x00170000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD22 0x00160000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD21 0x00150000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD20 0x00140000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD19 0x00130000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD18 0x00120000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD17 0x00110000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD16 0x00100000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD15 0x000F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD14 0x000E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD13 0x000D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD12 0x000C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD11 0x000B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD10 0x000A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD9 0x00090000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD8 0x00080000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD7 0x00070000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD6 0x00060000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD5 0x00050000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD4 0x00040000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD3 0x00030000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD2 0x00020000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD1 0x00010000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD0 0x00000000 - -// Field: [13:8] WU1_EV -// -// MCU Wakeup Source #1 -// -// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the -// MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 -#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD31 0x00001F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD30 0x00001E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD29 0x00001D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD28 0x00001C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD27 0x00001B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD26 0x00001A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD25 0x00001900 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD24 0x00001800 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD23 0x00001700 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD22 0x00001600 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD21 0x00001500 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD20 0x00001400 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD19 0x00001300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD18 0x00001200 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD17 0x00001100 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD16 0x00001000 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD15 0x00000F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD14 0x00000E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD13 0x00000D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD12 0x00000C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD11 0x00000B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD10 0x00000A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD9 0x00000900 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD8 0x00000800 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD7 0x00000700 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD6 0x00000600 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD5 0x00000500 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD4 0x00000400 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD3 0x00000300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD2 0x00000200 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD1 0x00000100 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD0 0x00000000 - -// Field: [5:0] WU0_EV -// -// MCU Wakeup Source #0 -// -// AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the -// MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F -#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 -#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD31 0x0000001F -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD30 0x0000001E -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD29 0x0000001D -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD28 0x0000001C -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD27 0x0000001B -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD26 0x0000001A -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD25 0x00000019 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD24 0x00000018 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD23 0x00000017 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD22 0x00000016 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD21 0x00000015 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD20 0x00000014 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD19 0x00000013 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD18 0x00000012 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD17 0x00000011 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD16 0x00000010 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD15 0x0000000F -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD14 0x0000000E -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD13 0x0000000D -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD12 0x0000000C -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD11 0x0000000B -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD10 0x0000000A -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD9 0x00000009 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD8 0x00000008 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD7 0x00000007 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD6 0x00000006 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD5 0x00000005 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD4 0x00000004 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD3 0x00000003 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD2 0x00000002 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD1 0x00000001 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD0 0x00000000 - -//***************************************************************************** -// -// Register: AON_EVENT_O_AUXWUSEL -// -//***************************************************************************** -// Field: [21:16] WU2_EV -// -// AUX Wakeup Source #2 -// -// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the -// AUX domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_AUXWUSEL_WU2_EV_W 6 -#define AON_EVENT_AUXWUSEL_WU2_EV_M 0x003F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_S 16 -#define AON_EVENT_AUXWUSEL_WU2_EV_NONE 0x003F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_JTAG 0x002B0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD 0x00200000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD31 0x001F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD30 0x001E0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD29 0x001D0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD28 0x001C0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD27 0x001B0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD26 0x001A0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD25 0x00190000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD24 0x00180000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD23 0x00170000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD22 0x00160000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD21 0x00150000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD20 0x00140000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD19 0x00130000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD18 0x00120000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD17 0x00110000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD16 0x00100000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD15 0x000F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD14 0x000E0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD13 0x000D0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD12 0x000C0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD11 0x000B0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD10 0x000A0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD9 0x00090000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD8 0x00080000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD7 0x00070000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD6 0x00060000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD5 0x00050000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD4 0x00040000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD3 0x00030000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD2 0x00020000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD1 0x00010000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD0 0x00000000 - -// Field: [13:8] WU1_EV -// -// AUX Wakeup Source #1 -// -// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the -// AUX domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_AUXWUSEL_WU1_EV_W 6 -#define AON_EVENT_AUXWUSEL_WU1_EV_M 0x00003F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_S 8 -#define AON_EVENT_AUXWUSEL_WU1_EV_NONE 0x00003F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_AUXWUSEL_WU1_EV_JTAG 0x00002B00 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD 0x00002000 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD31 0x00001F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD30 0x00001E00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD29 0x00001D00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD28 0x00001C00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD27 0x00001B00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD26 0x00001A00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD25 0x00001900 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD24 0x00001800 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD23 0x00001700 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD22 0x00001600 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD21 0x00001500 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD20 0x00001400 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD19 0x00001300 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD18 0x00001200 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD17 0x00001100 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD16 0x00001000 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD15 0x00000F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD14 0x00000E00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD13 0x00000D00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD12 0x00000C00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD11 0x00000B00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD10 0x00000A00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD9 0x00000900 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD8 0x00000800 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD7 0x00000700 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD6 0x00000600 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD5 0x00000500 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD4 0x00000400 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD3 0x00000300 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD2 0x00000200 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD1 0x00000100 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD0 0x00000000 - -// Field: [5:0] WU0_EV -// -// AUX Wakeup Source #0 -// -// AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the -// AUX domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_AUXWUSEL_WU0_EV_W 6 -#define AON_EVENT_AUXWUSEL_WU0_EV_M 0x0000003F -#define AON_EVENT_AUXWUSEL_WU0_EV_S 0 -#define AON_EVENT_AUXWUSEL_WU0_EV_NONE 0x0000003F -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_AUXWUSEL_WU0_EV_JTAG 0x0000002B -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD 0x00000020 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD31 0x0000001F -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD30 0x0000001E -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD29 0x0000001D -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD28 0x0000001C -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD27 0x0000001B -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD26 0x0000001A -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD25 0x00000019 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD24 0x00000018 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD23 0x00000017 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD22 0x00000016 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD21 0x00000015 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD20 0x00000014 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD19 0x00000013 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD18 0x00000012 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD17 0x00000011 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD16 0x00000010 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD15 0x0000000F -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD14 0x0000000E -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD13 0x0000000D -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD12 0x0000000C -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD11 0x0000000B -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD10 0x0000000A -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD9 0x00000009 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD8 0x00000008 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD7 0x00000007 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD6 0x00000006 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD5 0x00000005 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD4 0x00000004 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD3 0x00000003 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD2 0x00000002 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD1 0x00000001 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD0 0x00000000 - -//***************************************************************************** -// -// Register: AON_EVENT_O_EVTOMCUSEL -// -//***************************************************************************** -// Field: [21:16] AON_PROG2_EV -// -// Event selector for AON_PROG2 event. -// -// AON Event Source id# selecting event routed to EVENT as AON_PROG2 event. -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD31 0x001F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD30 0x001E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD29 0x001D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD28 0x001C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD27 0x001B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD26 0x001A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD25 0x00190000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD24 0x00180000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD23 0x00170000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD22 0x00160000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD21 0x00150000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD20 0x00140000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD19 0x00130000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD18 0x00120000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD17 0x00110000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD16 0x00100000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD15 0x000F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD14 0x000E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD13 0x000D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD12 0x000C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD11 0x000B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD10 0x000A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD9 0x00090000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD8 0x00080000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD7 0x00070000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD6 0x00060000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD5 0x00050000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD4 0x00040000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD3 0x00030000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD2 0x00020000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD1 0x00010000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD0 0x00000000 - -// Field: [13:8] AON_PROG1_EV -// -// Event selector for AON_PROG1 event. -// -// AON Event Source id# selecting event routed to EVENT as AON_PROG1 event. -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD31 0x00001F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD30 0x00001E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD29 0x00001D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD28 0x00001C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD27 0x00001B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD26 0x00001A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD25 0x00001900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD24 0x00001800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD23 0x00001700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD22 0x00001600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD21 0x00001500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD20 0x00001400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD19 0x00001300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD18 0x00001200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD17 0x00001100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD16 0x00001000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD15 0x00000F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD14 0x00000E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD13 0x00000D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD12 0x00000C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD11 0x00000B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD10 0x00000A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD9 0x00000900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD8 0x00000800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD7 0x00000700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD6 0x00000600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD5 0x00000500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD4 0x00000400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD3 0x00000300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD2 0x00000200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD1 0x00000100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD0 0x00000000 - -// Field: [5:0] AON_PROG0_EV -// -// Event selector for AON_PROG0 event. -// -// AON Event Source id# selecting event routed to EVENT as AON_PROG0 event. -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD31 0x0000001F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD30 0x0000001E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD29 0x0000001D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD28 0x0000001C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD27 0x0000001B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD26 0x0000001A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD25 0x00000019 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD24 0x00000018 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD23 0x00000017 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD22 0x00000016 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD21 0x00000015 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD20 0x00000014 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD19 0x00000013 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD18 0x00000012 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD17 0x00000011 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD16 0x00000010 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD15 0x0000000F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD14 0x0000000E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD13 0x0000000D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD12 0x0000000C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD11 0x0000000B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD10 0x0000000A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD9 0x00000009 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD8 0x00000008 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD7 0x00000007 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD6 0x00000006 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD5 0x00000005 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD4 0x00000004 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD3 0x00000003 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD2 0x00000002 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD1 0x00000001 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD0 0x00000000 - -//***************************************************************************** -// -// Register: AON_EVENT_O_RTCSEL -// -//***************************************************************************** -// Field: [5:0] RTC_CH1_CAPT_EV -// -// AON Event Source id# for RTCSEL event which is fed to AON_RTC. Please refer -// to AON_RTC:CH1CAPT -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// PAD31 Edge detect on PAD31 -// PAD30 Edge detect on PAD30 -// PAD29 Edge detect on PAD29 -// PAD28 Edge detect on PAD28 -// PAD27 Edge detect on PAD27 -// PAD26 Edge detect on PAD26 -// PAD25 Edge detect on PAD25 -// PAD24 Edge detect on PAD24 -// PAD23 Edge detect on PAD23 -// PAD22 Edge detect on PAD22 -// PAD21 Edge detect on PAD21 -// PAD20 Edge detect on PAD20 -// PAD19 Edge detect on PAD19 -// PAD18 Edge detect on PAD18 -// PAD17 Edge detect on PAD17 -// PAD16 Edge detect on PAD16 -// PAD15 Edge detect on PAD15 -// PAD14 Edge detect on PAD14 -// PAD13 Edge detect on PAD13 -// PAD12 Edge detect on PAD12 -// PAD11 Edge detect on PAD11 -// PAD10 Edge detect on PAD10 -// PAD9 Edge detect on PAD9 -// PAD8 Edge detect on PAD8 -// PAD7 Edge detect on PAD7 -// PAD6 Edge detect on PAD6 -// PAD5 Edge detect on PAD5 -// PAD4 Edge detect on PAD4 -// PAD3 Edge detect on PAD3 -// PAD2 Edge detect on PAD2 -// PAD1 Edge detect on PAD1 -// PAD0 Edge detect on PAD0 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD31 0x0000001F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD30 0x0000001E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD29 0x0000001D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD28 0x0000001C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD27 0x0000001B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD26 0x0000001A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD25 0x00000019 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD24 0x00000018 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD23 0x00000017 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD22 0x00000016 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD21 0x00000015 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD20 0x00000014 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD19 0x00000013 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD18 0x00000012 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD17 0x00000011 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD16 0x00000010 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD15 0x0000000F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD14 0x0000000E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD13 0x0000000D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD12 0x0000000C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD11 0x0000000B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD10 0x0000000A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD9 0x00000009 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD8 0x00000008 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD7 0x00000007 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD6 0x00000006 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD5 0x00000005 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD4 0x00000004 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD3 0x00000003 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD2 0x00000002 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD1 0x00000001 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD0 0x00000000 - - -#endif // __AON_EVENT__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aon_ioc.h b/third_party/ti/devices/cc26x0/inc/hw_aon_ioc.h deleted file mode 100644 index 22bedd9a4..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aon_ioc.h +++ /dev/null @@ -1,141 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_ioc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_IOC_H__ -#define __HW_AON_IOC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_IOC component -// -//***************************************************************************** -// Internal -#define AON_IOC_O_IOSTRMIN 0x00000000 - -// Internal -#define AON_IOC_O_IOSTRMED 0x00000004 - -// Internal -#define AON_IOC_O_IOSTRMAX 0x00000008 - -// IO Latch Control -#define AON_IOC_O_IOCLATCH 0x0000000C - -// SCLK_LF External Output Control -#define AON_IOC_O_CLK32KCTL 0x00000010 - -//***************************************************************************** -// -// Register: AON_IOC_O_IOSTRMIN -// -//***************************************************************************** -// Field: [2:0] GRAY_CODE -// -// Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 - -//***************************************************************************** -// -// Register: AON_IOC_O_IOSTRMED -// -//***************************************************************************** -// Field: [2:0] GRAY_CODE -// -// Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 - -//***************************************************************************** -// -// Register: AON_IOC_O_IOSTRMAX -// -//***************************************************************************** -// Field: [2:0] GRAY_CODE -// -// Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 - -//***************************************************************************** -// -// Register: AON_IOC_O_IOCLATCH -// -//***************************************************************************** -// Field: [0] EN -// -// Controls latches between MCU IOC and AON_IOC. -// -// The latches are transparent by default. -// -// They must be closed prior to power off the domain(s) controlling the IOs in -// order to preserve IO values on external pins. -// ENUMs: -// TRANSP Latches are transparent, meaning the value of the -// IO is directly controlled by the GPIO or -// peripheral value -// STATIC Latches are static, meaning the current value on -// the IO pin is frozen by latches and kept even -// if GPIO module or a peripheral module is turned -// off -#define AON_IOC_IOCLATCH_EN 0x00000001 -#define AON_IOC_IOCLATCH_EN_BITN 0 -#define AON_IOC_IOCLATCH_EN_M 0x00000001 -#define AON_IOC_IOCLATCH_EN_S 0 -#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 -#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 - -//***************************************************************************** -// -// Register: AON_IOC_O_CLK32KCTL -// -//***************************************************************************** -// Field: [0] OE_N -// -// 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (e.g. -// IOC:IOCFG0.PORT_ID) set to AON_CLK32K. -// 1: Output enable not active -#define AON_IOC_CLK32KCTL_OE_N 0x00000001 -#define AON_IOC_CLK32KCTL_OE_N_BITN 0 -#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 -#define AON_IOC_CLK32KCTL_OE_N_S 0 - - -#endif // __AON_IOC__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aon_rtc.h b/third_party/ti/devices/cc26x0/inc/hw_aon_rtc.h deleted file mode 100644 index 8d5955a59..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aon_rtc.h +++ /dev/null @@ -1,508 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_rtc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_RTC_H__ -#define __HW_AON_RTC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_RTC component -// -//***************************************************************************** -// Control -#define AON_RTC_O_CTL 0x00000000 - -// Event Flags, RTC Status -#define AON_RTC_O_EVFLAGS 0x00000004 - -// Second Counter Value, Integer Part -#define AON_RTC_O_SEC 0x00000008 - -// Second Counter Value, Fractional Part -#define AON_RTC_O_SUBSEC 0x0000000C - -// Subseconds Increment -#define AON_RTC_O_SUBSECINC 0x00000010 - -// Channel Configuration -#define AON_RTC_O_CHCTL 0x00000014 - -// Channel 0 Compare Value -#define AON_RTC_O_CH0CMP 0x00000018 - -// Channel 1 Compare Value -#define AON_RTC_O_CH1CMP 0x0000001C - -// Channel 2 Compare Value -#define AON_RTC_O_CH2CMP 0x00000020 - -// Channel 2 Compare Value Auto-increment -#define AON_RTC_O_CH2CMPINC 0x00000024 - -// Channel 1 Capture Value -#define AON_RTC_O_CH1CAPT 0x00000028 - -// AON Synchronization -#define AON_RTC_O_SYNC 0x0000002C - -//***************************************************************************** -// -// Register: AON_RTC_O_CTL -// -//***************************************************************************** -// Field: [18:16] COMB_EV_MASK -// -// Eventmask selecting which delayed events that form the combined event. -// ENUMs: -// CH2 Use Channel 2 delayed event in combined event -// CH1 Use Channel 1 delayed event in combined event -// CH0 Use Channel 0 delayed event in combined event -// NONE No event is selected for combined event. -#define AON_RTC_CTL_COMB_EV_MASK_W 3 -#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 -#define AON_RTC_CTL_COMB_EV_MASK_S 16 -#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 -#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 -#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 -#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 - -// Field: [11:8] EV_DELAY -// -// Number of SCLK_LF clock cycles waited before generating delayed events. -// (Common setting for all RTC cannels) the delayed event is delayed -// ENUMs: -// D144 Delay by 144 clock cycles -// D128 Delay by 128 clock cycles -// D112 Delay by 112 clock cycles -// D96 Delay by 96 clock cycles -// D80 Delay by 80 clock cycles -// D64 Delay by 64 clock cycles -// D48 Delay by 48 clock cycles -// D32 Delay by 32 clock cycles -// D16 Delay by 16 clock cycles -// D8 Delay by 8 clock cycles -// D4 Delay by 4 clock cycles -// D2 Delay by 2 clock cycles -// D1 Delay by 1 clock cycles -// D0 No delay on delayed event -#define AON_RTC_CTL_EV_DELAY_W 4 -#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 -#define AON_RTC_CTL_EV_DELAY_S 8 -#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 -#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 -#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 -#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 -#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 -#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 -#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 -#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 -#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 -#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 -#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 -#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 -#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 -#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 - -// Field: [7] RESET -// -// RTC Counter reset. -// -// Writing 1 to this bit will reset the RTC counter. -// -// This bit is cleared when reset takes effect -#define AON_RTC_CTL_RESET 0x00000080 -#define AON_RTC_CTL_RESET_BITN 7 -#define AON_RTC_CTL_RESET_M 0x00000080 -#define AON_RTC_CTL_RESET_S 7 - -// Field: [2] RTC_4KHZ_EN -// -// RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 -// which is used by AUX timer. -// -// 0: RTC_4KHZ signal is forced to 0 -// 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) -#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 -#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 -#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 -#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 - -// Field: [1] RTC_UPD_EN -// -// RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is -// SCLK_LF divided by 2 -// -// 0: RTC_UPD signal is forced to 0 -// 1: RTC_UPD signal is toggling @16 kHz -#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 -#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 -#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 -#define AON_RTC_CTL_RTC_UPD_EN_S 1 - -// Field: [0] EN -// -// Enable RTC counter -// -// 0: Halted (frozen) -// 1: Running -#define AON_RTC_CTL_EN 0x00000001 -#define AON_RTC_CTL_EN_BITN 0 -#define AON_RTC_CTL_EN_M 0x00000001 -#define AON_RTC_CTL_EN_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_EVFLAGS -// -//***************************************************************************** -// Field: [16] CH2 -// -// Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or -// passes the CH2CMP value. -// -// An event will be scheduled to occur as soon as possible when writing to -// CH2CMP provided that the channel is enabled and the new value matches any -// time between next RTC value and 1 second in the past -// -// Writing 1 clears this flag. Note that a new event can not occur on this -// channel in first 2 SCLK_LF cycles after a clearance. -// -// AUX_SCE can read the flag through AUX_WUC:WUEVFLAGS.AON_RTC_CH2 and clear it -// using AUX_WUC:WUEVCLR.AON_RTC_CH2. -#define AON_RTC_EVFLAGS_CH2 0x00010000 -#define AON_RTC_EVFLAGS_CH2_BITN 16 -#define AON_RTC_EVFLAGS_CH2_M 0x00010000 -#define AON_RTC_EVFLAGS_CH2_S 16 - -// Field: [8] CH1 -// -// Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: -// - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP -// value. -// - CHCTL.CH1_CAPT_EN = 1 and capture occurs. -// -// An event will be scheduled to occur as soon as possible when writing to -// CH1CMP provided that the channel is enabled, in compare mode and the new -// value matches any time between next RTC value and 1 second in the past. -// -// Writing 1 clears this flag. Note that a new event can not occur on this -// channel in first 2 SCLK_LF cycles after a clearance. -#define AON_RTC_EVFLAGS_CH1 0x00000100 -#define AON_RTC_EVFLAGS_CH1_BITN 8 -#define AON_RTC_EVFLAGS_CH1_M 0x00000100 -#define AON_RTC_EVFLAGS_CH1_S 8 - -// Field: [0] CH0 -// -// Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or -// passes the CH0CMP value. -// -// An event will be scheduled to occur as soon as possible when writing to -// CH0CMP provided that the channels is enabled and the new value matches any -// time between next RTC value and 1 second in the past. -// -// Writing 1 clears this flag. Note that a new event can not occur on this -// channel in first 2 SCLK_LF cycles after a clearance. -#define AON_RTC_EVFLAGS_CH0 0x00000001 -#define AON_RTC_EVFLAGS_CH0_BITN 0 -#define AON_RTC_EVFLAGS_CH0_M 0x00000001 -#define AON_RTC_EVFLAGS_CH0_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_SEC -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// Unsigned integer representing Real Time Clock in seconds. -// -// When reading this register the content of SUBSEC.VALUE is simultaneously -// latched. A consistent reading of the combined Real Time Clock can be -// obtained by first reading this register, then reading SUBSEC register. -#define AON_RTC_SEC_VALUE_W 32 -#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF -#define AON_RTC_SEC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_SUBSEC -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// Unsigned integer representing Real Time Clock in fractions of a second -// (VALUE/2^32 seconds) at the time when SEC register was read. -// -// Examples : -// - 0x0000_0000 = 0.0 sec -// - 0x4000_0000 = 0.25 sec -// - 0x8000_0000 = 0.5 sec -// - 0xC000_0000 = 0.75 sec -#define AON_RTC_SUBSEC_VALUE_W 32 -#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF -#define AON_RTC_SUBSEC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_SUBSECINC -// -//***************************************************************************** -// Field: [23:0] VALUEINC -// -// This value compensates for a SCLK_LF clock which has an offset from 32768 -// Hz. -// -// The compensation value can be found as 2^38 / freq, where freq is SCLK_LF -// clock frequency in Hertz -// -// This value is added to SUBSEC.VALUE on every cycle, and carry of this is -// added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with -// SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a -// hidden 6-bit register that generates a carry into the above mentioned -// addition on overflow. -// The default value corresponds to incrementing by precisely 1/32768 of a -// second. -// -// NOTE: This register is read only. Modification of the register value must be -// done using registers AUX_WUC:RTCSUBSECINC1 , AUX_WUC:RTCSUBSECINC0 and -// AUX_WUC:RTCSUBSECINCCTL -#define AON_RTC_SUBSECINC_VALUEINC_W 24 -#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF -#define AON_RTC_SUBSECINC_VALUEINC_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CHCTL -// -//***************************************************************************** -// Field: [18] CH2_CONT_EN -// -// Set to enable continuous operation of Channel 2 -#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 -#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 -#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 -#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 - -// Field: [16] CH2_EN -// -// RTC Channel 2 Enable -// -// 0: Disable RTC Channel 2 -// 1: Enable RTC Channel 2 -#define AON_RTC_CHCTL_CH2_EN 0x00010000 -#define AON_RTC_CHCTL_CH2_EN_BITN 16 -#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 -#define AON_RTC_CHCTL_CH2_EN_S 16 - -// Field: [9] CH1_CAPT_EN -// -// Set Channel 1 mode -// -// 0: Compare mode (default) -// 1: Capture mode -#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 -#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 -#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 -#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 - -// Field: [8] CH1_EN -// -// RTC Channel 1 Enable -// -// 0: Disable RTC Channel 1 -// 1: Enable RTC Channel 1 -#define AON_RTC_CHCTL_CH1_EN 0x00000100 -#define AON_RTC_CHCTL_CH1_EN_BITN 8 -#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 -#define AON_RTC_CHCTL_CH1_EN_S 8 - -// Field: [0] CH0_EN -// -// RTC Channel 0 Enable -// -// 0: Disable RTC Channel 0 -// 1: Enable RTC Channel 0 -#define AON_RTC_CHCTL_CH0_EN 0x00000001 -#define AON_RTC_CHCTL_CH0_EN_BITN 0 -#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 -#define AON_RTC_CHCTL_CH0_EN_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CH0CMP -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// RTC Channel 0 compare value. -// -// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of -// the compare value. -// -// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE -// (31:16) values of the Real Time Clock register. A Cannel 0 event is -// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or -// exciting the compare value. -// -// Writing to this register can trigger an immediate*) event in case the new -// compare value matches a Real Time Clock value from 1 second in the past up -// till current Real Time Clock value. -// -// Example: -// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 -// -// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to -// synchronization. -#define AON_RTC_CH0CMP_VALUE_W 32 -#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH0CMP_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CH1CMP -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// RTC Channel 1 compare value. -// -// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of -// the compare value. -// -// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE -// (31:16) values of the Real Time Clock register. A Cannel 0 event is -// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or -// exciting the compare value. -// -// Writing to this register can trigger an immediate*) event in case the new -// compare value matches a Real Time Clock value from 1 second in the past up -// till current Real Time Clock value. -// -// Example: -// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 -// -// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to -// synchronization. -#define AON_RTC_CH1CMP_VALUE_W 32 -#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH1CMP_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CH2CMP -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// RTC Channel 2 compare value. -// -// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of -// the compare value. -// -// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE -// (31:16) values of the Real Time Clock register. A Cannel 0 event is -// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or -// exciting the compare value. -// -// Writing to this register can trigger an immediate*) event in case the new -// compare value matches a Real Time Clock value from 1 second in the past up -// till current Real Time Clock value. -// -// Example: -// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 -// -// *) It can take up to 2 SCLK_LF clock cycles before event occurs due to -// synchronization. -#define AON_RTC_CH2CMP_VALUE_W 32 -#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH2CMP_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CH2CMPINC -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every -// channel 2 compare event. -#define AON_RTC_CH2CMPINC_VALUE_W 32 -#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH2CMPINC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CH1CAPT -// -//***************************************************************************** -// Field: [31:16] SEC -// -// Value of SEC.VALUE bits 15:0 at capture time. -#define AON_RTC_CH1CAPT_SEC_W 16 -#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 -#define AON_RTC_CH1CAPT_SEC_S 16 - -// Field: [15:0] SUBSEC -// -// Value of SUBSEC.VALUE bits 31:16 at capture time. -#define AON_RTC_CH1CAPT_SUBSEC_W 16 -#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF -#define AON_RTC_CH1CAPT_SUBSEC_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_SYNC -// -//***************************************************************************** -// Field: [0] WBUSY -// -// This register will always return 0,- however it will not return the value -// until there are no outstanding write requests between MCU and AON -// -// Note: Writing to this register prior to reading will force a wait until next -// SCLK_LF edge. This is recommended for syncing read registers from AON when -// waking up from sleep -// Failure to do so may result in reading AON values from prior to going to -// sleep -#define AON_RTC_SYNC_WBUSY 0x00000001 -#define AON_RTC_SYNC_WBUSY_BITN 0 -#define AON_RTC_SYNC_WBUSY_M 0x00000001 -#define AON_RTC_SYNC_WBUSY_S 0 - - -#endif // __AON_RTC__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aon_sysctl.h b/third_party/ti/devices/cc26x0/inc/hw_aon_sysctl.h deleted file mode 100644 index 13102459a..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aon_sysctl.h +++ /dev/null @@ -1,348 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_sysctl_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_SYSCTL_H__ -#define __HW_AON_SYSCTL_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_SYSCTL component -// -//***************************************************************************** -// Power Management -#define AON_SYSCTL_O_PWRCTL 0x00000000 - -// Reset Management -#define AON_SYSCTL_O_RESETCTL 0x00000004 - -// Sleep Mode -#define AON_SYSCTL_O_SLEEPCTL 0x00000008 - -//***************************************************************************** -// -// Register: AON_SYSCTL_O_PWRCTL -// -//***************************************************************************** -// Field: [2] DCDC_ACTIVE -// -// Select to use DCDC regulator for VDDR in active mode -// -// 0: Use GLDO for regulation of VDDRin active mode. -// 1: Use DCDC for regulation of VDDRin active mode. -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE 0x00000004 -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN 2 -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_S 2 - -// Field: [1] EXT_REG_MODE -// -// Status of source for VDDRsupply: -// -// 0: DCDC/GLDO are generating VDDR -// 1: DCDC/GLDO are bypassed, external regulator supplies VDDR -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE 0x00000002 -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_BITN 1 -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_S 1 - -// Field: [0] DCDC_EN -// -// Select to use DCDC regulator during recharge of VDDR -// -// 0: Use GLDO for recharge of VDDR -// 1: Use DCDC for recharge of VDDR -// -// Note: This bitfield should be set to the same as DCDC_ACTIVE -#define AON_SYSCTL_PWRCTL_DCDC_EN 0x00000001 -#define AON_SYSCTL_PWRCTL_DCDC_EN_BITN 0 -#define AON_SYSCTL_PWRCTL_DCDC_EN_M 0x00000001 -#define AON_SYSCTL_PWRCTL_DCDC_EN_S 0 - -//***************************************************************************** -// -// Register: AON_SYSCTL_O_RESETCTL -// -//***************************************************************************** -// Field: [31] SYSRESET -// -// Cold reset register. Writing 1 to this bitfield will reset the entire chip -// and cause boot code to run again. -// -// 0: No effect -// 1: Generate system reset. Appears as SYSRESET in RESET_SRC. -#define AON_SYSCTL_RESETCTL_SYSRESET 0x80000000 -#define AON_SYSCTL_RESETCTL_SYSRESET_BITN 31 -#define AON_SYSCTL_RESETCTL_SYSRESET_M 0x80000000 -#define AON_SYSCTL_RESETCTL_SYSRESET_S 31 - -// Field: [25] BOOT_DET_1_CLR -// -// Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_S 25 - -// Field: [24] BOOT_DET_0_CLR -// -// Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_S 24 - -// Field: [17] BOOT_DET_1_SET -// -// Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_S 17 - -// Field: [16] BOOT_DET_0_SET -// -// Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_S 16 - -// Field: [15] WU_FROM_SD -// -// A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from -// SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin -// being forced low) -// -// Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup -// sources. -// -// 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC -// 1: A wakeup has occurred from SHUTDOWN -// -// Note: This flag can not be cleared and will therefor remain valid untill -// poweroff/reset -#define AON_SYSCTL_RESETCTL_WU_FROM_SD 0x00008000 -#define AON_SYSCTL_RESETCTL_WU_FROM_SD_BITN 15 -#define AON_SYSCTL_RESETCTL_WU_FROM_SD_M 0x00008000 -#define AON_SYSCTL_RESETCTL_WU_FROM_SD_S 15 - -// Field: [14] GPIO_WU_FROM_SD -// -// A wakeup from SHUTDOWN on an IO event has occurred -// -// Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup -// sources. -// -// 0: The wakeup did not occur from SHUTDOWN on an IO event -// 1: A wakeup from SHUTDOWN occurred from an IO event -// -// The case where WU_FROM_SD is asserted but this bitfield is not asserted will -// only occur in a debug session. The boot code will not proceed with wakeup -// from SHUTDOWN procedure until this bitfield is asserted as well. -// -// Note: This flag can not be cleared and will therefor remain valid untill -// poweroff/reset -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 - -// Field: [13] BOOT_DET_1 -// -// Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_1 0x00002000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_BITN 13 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_M 0x00002000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_S 13 - -// Field: [12] BOOT_DET_0 -// -// Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_0 0x00001000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_BITN 12 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_M 0x00001000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_S 12 - -// Field: [11] VDDS_LOSS_EN_OVR -// -// Override of VDDS_LOSS_EN -// -// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN=1 -// 1: Brown out detect of VDDS generates system reset (regardless of -// VDDS_LOSS_EN) -// -// This bit can be locked -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR 0x00000800 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_BITN 11 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_M 0x00000800 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_S 11 - -// Field: [10] VDDR_LOSS_EN_OVR -// -// Override of VDDR_LOSS_EN -// -// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN=1 -// 1: Brown out detect of VDDR generates system reset (regardless of -// VDDR_LOSS_EN) -// -// This bit can be locked -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR 0x00000400 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_BITN 10 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_M 0x00000400 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_S 10 - -// Field: [9] VDD_LOSS_EN_OVR -// -// Override of VDD_LOSS_EN -// -// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN=1 -// 1: Brown out detect of VDD generates system reset (regardless of -// VDD_LOSS_EN) -// -// This bit can be locked -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR 0x00000200 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_BITN 9 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_M 0x00000200 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_S 9 - -// Field: [7] VDDS_LOSS_EN -// -// Controls reset generation in case VDDS is lost -// -// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 -// 1: Brown out detect of VDDS generates system reset -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN 0x00000080 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_BITN 7 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000080 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_S 7 - -// Field: [6] VDDR_LOSS_EN -// -// Controls reset generation in case VDDR is lost -// -// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 -// 1: Brown out detect of VDDR generates system reset -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN 0x00000040 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN 6 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000040 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_S 6 - -// Field: [5] VDD_LOSS_EN -// -// Controls reset generation in case VDD is lost -// -// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 -// 1: Brown out detect of VDD generates system reset -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN 0x00000020 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_BITN 5 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_M 0x00000020 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_S 5 - -// Field: [4] CLK_LOSS_EN -// -// Controls reset generation in case SCLK_LF is lost. (provided that clock -// loss detection is enabled by DDI_0_OSC:CTL0.CLK_LOSS_EN) -// -// Note: Clock loss reset generation must be disabled before SCLK_LF clock -// source is changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and remain disabled -// untill the change is confirmed in DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do -// so may result in a spurious system reset. Clock loss reset generation can be -// disabled through this bitfield or by clearing DDI_0_OSC:CTL0.CLK_LOSS_EN -// -// 0: Clock loss is ignored -// 1: Clock loss generates system reset -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN 0x00000010 -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN 4 -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_M 0x00000010 -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_S 4 - -// Field: [3:1] RESET_SRC -// -// Shows the source of the last system reset: -// Occurrence of one of the reset sources may trigger several other reset -// sources as essential parts of the system are undergoing reset. This field -// will report the root cause of the reset (not the other resets that are -// consequence of the system reset). -// To support this feature the actual register is not captured before the reset -// source being released. If a new reset source is triggered, in a window of -// four 32 kHz periods after the previous has been released, this register -// may indicate Power on reset as source. -// ENUMs: -// WARMRESET Software reset via PRCM warm reset request -// SYSRESET Software reset via SYSRESET register -// CLK_LOSS Clock loss detect -// VDDR_LOSS Brown out detect on VDDR -// VDD_LOSS Brown out detect on VDD -// VDDS_LOSS Brown out detect on VDDS -// PIN_RESET Reset pin -// PWR_ON Power on reset -#define AON_SYSCTL_RESETCTL_RESET_SRC_W 3 -#define AON_SYSCTL_RESETCTL_RESET_SRC_M 0x0000000E -#define AON_SYSCTL_RESETCTL_RESET_SRC_S 1 -#define AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E -#define AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C -#define AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A -#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 -#define AON_SYSCTL_RESETCTL_RESET_SRC_VDD_LOSS 0x00000006 -#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 -#define AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 -#define AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 - -//***************************************************************************** -// -// Register: AON_SYSCTL_O_SLEEPCTL -// -//***************************************************************************** -// Field: [0] IO_PAD_SLEEP_DIS -// -// Controls the I/O pad sleep mode. The boot code will set this bitfield -// automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set -// ). -// -// 0: I/O pad sleep mode is enabled, ie all pads are latched and can not -// toggle. -// 1: I/O pad sleep mode is disabled -// -// Application software may want to reconfigure the state for all IO's before -// setting this bitfield upon waking up from a SHUTDOWN. -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 - - -#endif // __AON_SYSCTL__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aon_wuc.h b/third_party/ti/devices/cc26x0/inc/hw_aon_wuc.h deleted file mode 100644 index ddeda6045..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aon_wuc.h +++ /dev/null @@ -1,674 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_wuc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_WUC_H__ -#define __HW_AON_WUC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_WUC component -// -//***************************************************************************** -// MCU Clock Management -#define AON_WUC_O_MCUCLK 0x00000000 - -// AUX Clock Management -#define AON_WUC_O_AUXCLK 0x00000004 - -// MCU Configuration -#define AON_WUC_O_MCUCFG 0x00000008 - -// AUX Configuration -#define AON_WUC_O_AUXCFG 0x0000000C - -// AUX Control -#define AON_WUC_O_AUXCTL 0x00000010 - -// Power Status -#define AON_WUC_O_PWRSTAT 0x00000014 - -// Shutdown Control -#define AON_WUC_O_SHUTDOWN 0x00000018 - -// Control 0 -#define AON_WUC_O_CTL0 0x00000020 - -// Control 1 -#define AON_WUC_O_CTL1 0x00000024 - -// Recharge Controller Configuration -#define AON_WUC_O_RECHARGECFG 0x00000030 - -// Recharge Controller Status -#define AON_WUC_O_RECHARGESTAT 0x00000034 - -// Oscillator Configuration -#define AON_WUC_O_OSCCFG 0x00000038 - -// JTAG Configuration -#define AON_WUC_O_JTAGCFG 0x00000040 - -// JTAG USERCODE -#define AON_WUC_O_JTAGUSERCODE 0x00000044 - -//***************************************************************************** -// -// Register: AON_WUC_O_MCUCLK -// -//***************************************************************************** -// Field: [2] RCOSC_HF_CAL_DONE -// -// MCU bootcode will set this bit when RCOSC_HF is calibrated. The FLASH can -// not be used until this bit is set. -// -// 1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up. -// 0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that the SCLK_HF -// is safe -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE 0x00000004 -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_BITN 2 -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_M 0x00000004 -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_S 2 - -// Field: [1:0] PWR_DWN_SRC -// -// Controls the clock source for the entire MCU domain while MCU is requesting -// powerdown. -// -// When MCU requests powerdown with SCLK_HF as source, then WUC will switch -// over to this clock source during powerdown, and automatically switch back to -// SCLK_HF when MCU is no longer requesting powerdown and system is back in -// active mode. -// ENUMs: -// SCLK_LF Use SCLK_LF in Powerdown -// NONE No clock in Powerdown -#define AON_WUC_MCUCLK_PWR_DWN_SRC_W 2 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_M 0x00000003 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_S 0 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_SCLK_LF 0x00000001 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AON_WUC_O_AUXCLK -// -//***************************************************************************** -// Field: [12:11] PWR_DWN_SRC -// -// When AUX requests powerdown with SCLK_HF as source, then WUC will switch -// over to this clock source during powerdown, and automatically switch back to -// SCLK_HF when AUX system is back in active mode -// ENUMs: -// SCLK_LF Use SCLK_LF in Powerdown -// NONE No clock in Powerdown -#define AON_WUC_AUXCLK_PWR_DWN_SRC_W 2 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_M 0x00001800 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_S 11 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_SCLK_LF 0x00000800 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_NONE 0x00000000 - -// Field: [10:8] SCLK_HF_DIV -// -// Select the AUX clock divider for SCLK_HF -// -// NB: It is not supported to change the AUX clock divider while SCLK_HF is -// active source for AUX -// ENUMs: -// DIV256 Divide by 256 -// DIV128 Divide by 128 -// DIV64 Divide by 64 -// DIV32 Divide by 32 -// DIV16 Divide by 16 -// DIV8 Divide by 8 -// DIV4 Divide by 4 -// DIV2 Divide by 2 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_W 3 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_M 0x00000700 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_S 8 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 0x00000700 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 0x00000600 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 0x00000500 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 0x00000400 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 0x00000300 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 0x00000200 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 0x00000100 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 0x00000000 - -// Field: [2:0] SRC -// -// Selects the clock source for AUX: -// -// NB: Switching the clock source is guaranteed to be glitchless -// ENUMs: -// SCLK_LF LF Clock (SCLK_LF) -// SCLK_HF HF Clock (SCLK_HF) -#define AON_WUC_AUXCLK_SRC_W 3 -#define AON_WUC_AUXCLK_SRC_M 0x00000007 -#define AON_WUC_AUXCLK_SRC_S 0 -#define AON_WUC_AUXCLK_SRC_SCLK_LF 0x00000004 -#define AON_WUC_AUXCLK_SRC_SCLK_HF 0x00000001 - -//***************************************************************************** -// -// Register: AON_WUC_O_MCUCFG -// -//***************************************************************************** -// Field: [17] VIRT_OFF -// -// Internal. Only to be used through TI provided API. -#define AON_WUC_MCUCFG_VIRT_OFF 0x00020000 -#define AON_WUC_MCUCFG_VIRT_OFF_BITN 17 -#define AON_WUC_MCUCFG_VIRT_OFF_M 0x00020000 -#define AON_WUC_MCUCFG_VIRT_OFF_S 17 - -// Field: [16] FIXED_WU_EN -// -// Internal. Only to be used through TI provided API. -#define AON_WUC_MCUCFG_FIXED_WU_EN 0x00010000 -#define AON_WUC_MCUCFG_FIXED_WU_EN_BITN 16 -#define AON_WUC_MCUCFG_FIXED_WU_EN_M 0x00010000 -#define AON_WUC_MCUCFG_FIXED_WU_EN_S 16 - -// Field: [3:0] SRAM_RET_EN -// -// MCU SRAM is partitioned into 4 banks . This register controls which of the -// banks that has retention during MCU power off -// ENUMs: -// RET_FULL Retention on for all banks (SRAM:BANK0, SRAM:BANK1 -// ,SRAM:BANK2 and SRAM:BANK3) -// RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 and -// SRAM:BANK2 -// RET_LEVEL2 Retention on for SRAM:BANK0 and SRAM:BANK1 -// RET_LEVEL1 Retention on for SRAM:BANK0 -// RET_NONE Retention is disabled -#define AON_WUC_MCUCFG_SRAM_RET_EN_W 4 -#define AON_WUC_MCUCFG_SRAM_RET_EN_M 0x0000000F -#define AON_WUC_MCUCFG_SRAM_RET_EN_S 0 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_FULL 0x0000000F -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL3 0x00000007 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL2 0x00000003 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL1 0x00000001 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AON_WUC_O_AUXCFG -// -//***************************************************************************** -// Field: [0] RAM_RET_EN -// -// This bit controls retention mode for the AUX_RAM:BANK0: -// -// 0: Retention is disabled -// 1: Retention is enabled -// -// NB: If retention is disabled, the AUX_RAM will be powered off when it would -// otherwise be put in retention mode -#define AON_WUC_AUXCFG_RAM_RET_EN 0x00000001 -#define AON_WUC_AUXCFG_RAM_RET_EN_BITN 0 -#define AON_WUC_AUXCFG_RAM_RET_EN_M 0x00000001 -#define AON_WUC_AUXCFG_RAM_RET_EN_S 0 - -//***************************************************************************** -// -// Register: AON_WUC_O_AUXCTL -// -//***************************************************************************** -// Field: [31] RESET_REQ -// -// Reset request for AUX. Writing 1 to this register will assert reset to AUX. -// The reset will be held until the bit is cleared again. -// -// 0: AUX reset pin will be deasserted -// 1: AUX reset pin will be asserted -#define AON_WUC_AUXCTL_RESET_REQ 0x80000000 -#define AON_WUC_AUXCTL_RESET_REQ_BITN 31 -#define AON_WUC_AUXCTL_RESET_REQ_M 0x80000000 -#define AON_WUC_AUXCTL_RESET_REQ_S 31 - -// Field: [2] SCE_RUN_EN -// -// Enables (1) or disables (0) AUX_SCE execution. AUX_SCE execution will begin -// when AUX Domain is powered and either this or AUX_SCE:CTL.CLK_EN is set. -// -// Setting this bit will assure that AUX_SCE execution starts as soon as AUX -// power domain is woken up. ( AUX_SCE:CTL.CLK_EN will be reset to 0 if AUX -// power domain has been off) -// -// 0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is 0 -// 1: AUX_SCE execution is enabled. -#define AON_WUC_AUXCTL_SCE_RUN_EN 0x00000004 -#define AON_WUC_AUXCTL_SCE_RUN_EN_BITN 2 -#define AON_WUC_AUXCTL_SCE_RUN_EN_M 0x00000004 -#define AON_WUC_AUXCTL_SCE_RUN_EN_S 2 - -// Field: [1] SWEV -// -// Writing 1 sets the software event to the AUX domain, which can be read -// through AUX_WUC:WUEVFLAGS.AON_SW. -// -// This event is normally cleared by AUX_SCE through the -// AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0 to this -// register. -// -// Reading 0 means that there is no outstanding software event for AUX. -// -// Note that it can take up to 1,5 SCLK_LF clock cycles to clear the event from -// AUX. -#define AON_WUC_AUXCTL_SWEV 0x00000002 -#define AON_WUC_AUXCTL_SWEV_BITN 1 -#define AON_WUC_AUXCTL_SWEV_M 0x00000002 -#define AON_WUC_AUXCTL_SWEV_S 1 - -// Field: [0] AUX_FORCE_ON -// -// Forces the AUX domain into active mode, overriding the requests from -// AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and AUX_WUC:MCUBUSCTL. -// Note that an ongoing AUX_WUC:PWROFFREQ will complete before this bit will -// set the AUX domain into active mode. -// -// MCU must set this bit in order to access the AUX peripherals. -// The AUX domain status can be read from PWRSTAT.AUX_PD_ON -// -// 0: AUX is allowed to Power Off, Power Down or Disconnect. -// 1: AUX Power OFF, Power Down or Disconnect requests will be overruled -#define AON_WUC_AUXCTL_AUX_FORCE_ON 0x00000001 -#define AON_WUC_AUXCTL_AUX_FORCE_ON_BITN 0 -#define AON_WUC_AUXCTL_AUX_FORCE_ON_M 0x00000001 -#define AON_WUC_AUXCTL_AUX_FORCE_ON_S 0 - -//***************************************************************************** -// -// Register: AON_WUC_O_PWRSTAT -// -//***************************************************************************** -// Field: [9] AUX_PWR_DWN -// -// Indicates the AUX powerdown state when AUX domain is powered up. -// -// 0: Active mode -// 1: AUX Powerdown request has been granted -#define AON_WUC_PWRSTAT_AUX_PWR_DWN 0x00000200 -#define AON_WUC_PWRSTAT_AUX_PWR_DWN_BITN 9 -#define AON_WUC_PWRSTAT_AUX_PWR_DWN_M 0x00000200 -#define AON_WUC_PWRSTAT_AUX_PWR_DWN_S 9 - -// Field: [6] JTAG_PD_ON -// -// Indicates JTAG power state: -// -// 0: JTAG is powered off -// 1: JTAG is powered on -#define AON_WUC_PWRSTAT_JTAG_PD_ON 0x00000040 -#define AON_WUC_PWRSTAT_JTAG_PD_ON_BITN 6 -#define AON_WUC_PWRSTAT_JTAG_PD_ON_M 0x00000040 -#define AON_WUC_PWRSTAT_JTAG_PD_ON_S 6 - -// Field: [5] AUX_PD_ON -// -// Indicates AUX power state: -// -// 0: AUX is not ready for use ( may be powered off or in power state -// transition ) -// 1: AUX is powered on, connected to bus and ready for use, -#define AON_WUC_PWRSTAT_AUX_PD_ON 0x00000020 -#define AON_WUC_PWRSTAT_AUX_PD_ON_BITN 5 -#define AON_WUC_PWRSTAT_AUX_PD_ON_M 0x00000020 -#define AON_WUC_PWRSTAT_AUX_PD_ON_S 5 - -// Field: [4] MCU_PD_ON -// -// Indicates MCU power state: -// -// 0: MCU Power sequencing is not yet finalized and MCU_AONIF registers may not -// be reliable -// 1: MCU Power sequencing is finalized and all MCU_AONIF registers are -// reliable -#define AON_WUC_PWRSTAT_MCU_PD_ON 0x00000010 -#define AON_WUC_PWRSTAT_MCU_PD_ON_BITN 4 -#define AON_WUC_PWRSTAT_MCU_PD_ON_M 0x00000010 -#define AON_WUC_PWRSTAT_MCU_PD_ON_S 4 - -// Field: [2] AUX_BUS_CONNECTED -// -// Indicates that AUX Bus is connected: -// -// 0: AUX bus is not connected -// 1: AUX bus is connected ( idle_ack = 0 ) -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED 0x00000004 -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_BITN 2 -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_M 0x00000004 -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_S 2 - -// Field: [1] AUX_RESET_DONE -// -// Indicates Reset Done from AUX: -// -// 0: AUX is being reset -// 1: AUX reset is released -#define AON_WUC_PWRSTAT_AUX_RESET_DONE 0x00000002 -#define AON_WUC_PWRSTAT_AUX_RESET_DONE_BITN 1 -#define AON_WUC_PWRSTAT_AUX_RESET_DONE_M 0x00000002 -#define AON_WUC_PWRSTAT_AUX_RESET_DONE_S 1 - -//***************************************************************************** -// -// Register: AON_WUC_O_SHUTDOWN -// -//***************************************************************************** -// Field: [0] EN -// -// Writing a 1 to this bit forces a shutdown request to be registered and all -// I/O values to be latched - in the PAD ring, possibly enabling I/O wakeup. -// Writing 0 will cancel a registered shutdown request and open th I/O latches -// residing in the PAD ring. -// -// A registered shutdown request takes effect the next time power down -// conditions exists. At this time, the will not enter Powerdown mode, but -// instead it will turn off all internal powersupplies, effectively putting the -// device into Shutdown mode. -#define AON_WUC_SHUTDOWN_EN 0x00000001 -#define AON_WUC_SHUTDOWN_EN_BITN 0 -#define AON_WUC_SHUTDOWN_EN_M 0x00000001 -#define AON_WUC_SHUTDOWN_EN_S 0 - -//***************************************************************************** -// -// Register: AON_WUC_O_CTL0 -// -//***************************************************************************** -// Field: [8] PWR_DWN_DIS -// -// Controls whether MCU and AUX requesting to be powered off will enable a -// transition to powerdown: -// -// 0: Enabled -// 1: Disabled -#define AON_WUC_CTL0_PWR_DWN_DIS 0x00000100 -#define AON_WUC_CTL0_PWR_DWN_DIS_BITN 8 -#define AON_WUC_CTL0_PWR_DWN_DIS_M 0x00000100 -#define AON_WUC_CTL0_PWR_DWN_DIS_S 8 - -// Field: [3] AUX_SRAM_ERASE -// -// Internal. Only to be used through TI provided API. -#define AON_WUC_CTL0_AUX_SRAM_ERASE 0x00000008 -#define AON_WUC_CTL0_AUX_SRAM_ERASE_BITN 3 -#define AON_WUC_CTL0_AUX_SRAM_ERASE_M 0x00000008 -#define AON_WUC_CTL0_AUX_SRAM_ERASE_S 3 - -// Field: [2] MCU_SRAM_ERASE -// -// Internal. Only to be used through TI provided API. -#define AON_WUC_CTL0_MCU_SRAM_ERASE 0x00000004 -#define AON_WUC_CTL0_MCU_SRAM_ERASE_BITN 2 -#define AON_WUC_CTL0_MCU_SRAM_ERASE_M 0x00000004 -#define AON_WUC_CTL0_MCU_SRAM_ERASE_S 2 - -//***************************************************************************** -// -// Register: AON_WUC_O_CTL1 -// -//***************************************************************************** -// Field: [1] MCU_RESET_SRC -// -// Indicates source of last MCU Voltage Domain warm reset request: -// -// 0: MCU SW reset -// 1: JTAG reset -// -// This bit can only be cleared by writing a 1 to it -#define AON_WUC_CTL1_MCU_RESET_SRC 0x00000002 -#define AON_WUC_CTL1_MCU_RESET_SRC_BITN 1 -#define AON_WUC_CTL1_MCU_RESET_SRC_M 0x00000002 -#define AON_WUC_CTL1_MCU_RESET_SRC_S 1 - -// Field: [0] MCU_WARM_RESET -// -// Indicates type of last MCU Voltage Domain reset: -// -// 0: Last MCU reset was not a warm reset -// 1: Last MCU reset was a warm reset (requested from MCU or JTAG as indicated -// in MCU_RESET_SRC) -// -// This bit can only be cleared by writing a 1 to it -#define AON_WUC_CTL1_MCU_WARM_RESET 0x00000001 -#define AON_WUC_CTL1_MCU_WARM_RESET_BITN 0 -#define AON_WUC_CTL1_MCU_WARM_RESET_M 0x00000001 -#define AON_WUC_CTL1_MCU_WARM_RESET_S 0 - -//***************************************************************************** -// -// Register: AON_WUC_O_RECHARGECFG -// -//***************************************************************************** -// Field: [31] ADAPTIVE_EN -// -// Enable adaptive recharge -// -// Note: Recharge can be turned completely of by setting MAX_PER_E=7 and -// MAX_PER_M=31 and this bitfield to 0 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN 0x80000000 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_BITN 31 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_M 0x80000000 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_S 31 - -// Field: [23:20] C2 -// -// Gain factor for adaptive recharge algorithm -// -// period_new=period * ( 1+/-(2^-C1+2^-C2) ) -// Valid values for C2 is 2 to 10 -// -// Note: Rounding may cause adaptive recharge not to start for very small -// values of both Gain and Initial period. Criteria for algorithm to start is -// MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 -#define AON_WUC_RECHARGECFG_C2_W 4 -#define AON_WUC_RECHARGECFG_C2_M 0x00F00000 -#define AON_WUC_RECHARGECFG_C2_S 20 - -// Field: [19:16] C1 -// -// Gain factor for adaptive recharge algorithm -// -// period_new=period * ( 1+/-(2^-C1+2^-C2) ) -// Valid values for C1 is 1 to 10 -// -// Note: Rounding may cause adaptive recharge not to start for very small -// values of both Gain and Initial period. Criteria for algorithm to start is -// MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 -#define AON_WUC_RECHARGECFG_C1_W 4 -#define AON_WUC_RECHARGECFG_C1_M 0x000F0000 -#define AON_WUC_RECHARGECFG_C1_S 16 - -// Field: [15:11] MAX_PER_M -// -// This register defines the maximum period that the recharge algorithm can -// take, i.e. it defines the maximum number of cycles between 2 recharges. -// The maximum number of cycles is specified with a 5 bit mantissa and 3 bit -// exponent: -// MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E -// This field sets the mantissa of MAXCYCLES -#define AON_WUC_RECHARGECFG_MAX_PER_M_W 5 -#define AON_WUC_RECHARGECFG_MAX_PER_M_M 0x0000F800 -#define AON_WUC_RECHARGECFG_MAX_PER_M_S 11 - -// Field: [10:8] MAX_PER_E -// -// This register defines the maximum period that the recharge algorithm can -// take, i.e. it defines the maximum number of cycles between 2 recharges. -// The maximum number of cycles is specified with a 5 bit mantissa and 3 bit -// exponent: -// MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E -// This field sets the exponent MAXCYCLES -#define AON_WUC_RECHARGECFG_MAX_PER_E_W 3 -#define AON_WUC_RECHARGECFG_MAX_PER_E_M 0x00000700 -#define AON_WUC_RECHARGECFG_MAX_PER_E_S 8 - -// Field: [7:3] PER_M -// -// Number of 32 KHz clocks between activation of recharge controller -// For recharge algorithm, PERIOD is the initial period when entering powerdown -// mode. The adaptive recharge algorithm will not change this register -// PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 -// bit exponent: -// This field sets the Mantissa of the Period. -// PERIOD=(PER_M*16+15)*2^PER_E -#define AON_WUC_RECHARGECFG_PER_M_W 5 -#define AON_WUC_RECHARGECFG_PER_M_M 0x000000F8 -#define AON_WUC_RECHARGECFG_PER_M_S 3 - -// Field: [2:0] PER_E -// -// Number of 32 KHz clocks between activation of recharge controller -// For recharge algorithm, PERIOD is the initial period when entering powerdown -// mode. The adaptive recharge algorithm will not change this register -// PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 -// bit exponent: -// This field sets the Exponent of the Period. -// PERIOD=(PER_M*16+15)*2^PER_E -#define AON_WUC_RECHARGECFG_PER_E_W 3 -#define AON_WUC_RECHARGECFG_PER_E_M 0x00000007 -#define AON_WUC_RECHARGECFG_PER_E_S 0 - -//***************************************************************************** -// -// Register: AON_WUC_O_RECHARGESTAT -// -//***************************************************************************** -// Field: [19:16] VDDR_SMPLS -// -// The last 4 VDDR samples, bit 0 being the newest. -// -// The register is being updated in every recharge period with a shift left, -// and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet in in case -// VDDR > VDDR_threshold just before recharge starts. Otherwise a 0 will be -// shifted in. -#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_W 4 -#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 -#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_S 16 - -// Field: [15:0] MAX_USED_PER -// -// The maximum value of recharge period seen with VDDR>threshold. -// -// The VDDR voltage is compared against the threshold voltage at just before -// each recharge. If VDDR is above threshold, MAX_USED_PER is updated with max -// ( current recharge peride; MAX_USED_PER ) This way MAX_USED_PER can track -// the recharge period where VDDR is decharged to the threshold value. We can -// therefore use the value as an indication of the leakage current during -// recharge. -// -// This bitfield is cleared to 0 when writing this register. -#define AON_WUC_RECHARGESTAT_MAX_USED_PER_W 16 -#define AON_WUC_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF -#define AON_WUC_RECHARGESTAT_MAX_USED_PER_S 0 - -//***************************************************************************** -// -// Register: AON_WUC_O_OSCCFG -// -//***************************************************************************** -// Field: [7:3] PER_M -// -// Number of 32 KHz clocks between oscillator amplitude calibrations. -// When this counter expires, an oscillator amplitude compensation is triggered -// immediately in Active mode. When this counter expires in Powerdown mode an -// internal flag is set such that the amplitude compensation is postponed until -// the next recharge occurs. -// -// The Period will effectively be a 16 bit value coded in a 5 bit mantissa and -// 3 bit exponent -// PERIOD=(PER_M*16+15)*2^PER_E -// This field sets the mantissa -// Note: Oscillator amplitude calibration is turned of when both this bitfield -// and PER_E are set to 0 -#define AON_WUC_OSCCFG_PER_M_W 5 -#define AON_WUC_OSCCFG_PER_M_M 0x000000F8 -#define AON_WUC_OSCCFG_PER_M_S 3 - -// Field: [2:0] PER_E -// -// Number of 32 KHz clocks between oscillator amplitude calibrations. -// When this counter expires, an oscillator amplitude compensation is triggered -// immediately in Active mode. When this counter expires in Powerdown mode an -// internal flag is set such that the amplitude compensation is postponed until -// the next recharge occurs. -// The Period will effectively be a 16 bit value coded in a 5 bit mantissa and -// 3 bit exponent -// PERIOD=(PER_M*16+15)*2^PER_E -// This field sets the exponent -// Note: Oscillator amplitude calibration is turned of when both PER_M and -// this bitfield are set to 0 -#define AON_WUC_OSCCFG_PER_E_W 3 -#define AON_WUC_OSCCFG_PER_E_M 0x00000007 -#define AON_WUC_OSCCFG_PER_E_S 0 - -//***************************************************************************** -// -// Register: AON_WUC_O_JTAGCFG -// -//***************************************************************************** -// Field: [8] JTAG_PD_FORCE_ON -// -// Controls JTAG PowerDomain power state: -// -// 0: Controlled exclusively by debug subsystem. (JTAG Powerdomain will be -// powered off unless a debugger is attached) -// 1: JTAG Power Domain is forced on, independent of debug subsystem. -// -// NB: The reset value causes JTAG Power Domain to be powered on by default. -// Software must clear this bit to turn off the JTAG Power Domain -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_S 8 - -//***************************************************************************** -// -// Register: AON_WUC_O_JTAGUSERCODE -// -//***************************************************************************** -// Field: [31:0] USER_CODE -// -// 32-bit JTAG USERCODE register feeding main JTAG TAP -// NB: This field can be locked -#define AON_WUC_JTAGUSERCODE_USER_CODE_W 32 -#define AON_WUC_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF -#define AON_WUC_JTAGUSERCODE_USER_CODE_S 0 - - -#endif // __AON_WUC__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aux_aiodio.h b/third_party/ti/devices/cc26x0/inc/hw_aux_aiodio.h deleted file mode 100644 index d102f6ff5..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aux_aiodio.h +++ /dev/null @@ -1,481 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_aiodio_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_AIODIO_H__ -#define __HW_AUX_AIODIO_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_AIODIO component -// -//***************************************************************************** -// General Purpose Input Output Data Out -#define AUX_AIODIO_O_GPIODOUT 0x00000000 - -// Input Output Mode -#define AUX_AIODIO_O_IOMODE 0x00000004 - -// General Purpose Input Output Data In -#define AUX_AIODIO_O_GPIODIN 0x00000008 - -// General Purpose Input Output Data Out Set -#define AUX_AIODIO_O_GPIODOUTSET 0x0000000C - -// General Purpose Input Output Data Out Clear -#define AUX_AIODIO_O_GPIODOUTCLR 0x00000010 - -// General Purpose Input Output Data Out Toggle -#define AUX_AIODIO_O_GPIODOUTTGL 0x00000014 - -// General Purpose Input Output Digital Input Enable -#define AUX_AIODIO_O_GPIODIE 0x00000018 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODOUT -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. -// Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. -#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IOMODE -// -//***************************************************************************** -// Field: [15:14] IO7 -// -// Select mode for AUXIO[8i+7]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When GPIODOUT bit 7 is 0: -// AUXIO[8i+7] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When GPIODOUT bit 7 is 1: -// AUXIO[8i+7] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When GPIODOUT bit 7 is 0: -// AUXIO[8i+7] is driven low. -// -// When GPIODOUT bit 7 is 1: -// AUXIO[8i+7] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 7 is 0: -// AUXIO[8i+7] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 7 is 1: -// AUXIO[8i+7] is enabled for digital input. -// OUT Output Mode: -// -// GPIODOUT bit 7 drives -// AUXIO[8i+7]. -#define AUX_AIODIO_IOMODE_IO7_W 2 -#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 -#define AUX_AIODIO_IOMODE_IO7_S 14 -#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 -#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 -#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 -#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 - -// Field: [13:12] IO6 -// -// Select mode for AUXIO[8i+6]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When GPIODOUT bit 6 is 0: -// AUXIO[8i+6] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When GPIODOUT bit 6 is 1: -// AUXIO[8i+6] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When GPIODOUT bit 6 is 0: -// AUXIO[8i+6] is driven low. -// -// When GPIODOUT bit 6 is 1: -// AUXIO[8i+6] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 6 is 0: -// AUXIO[8i+6] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 6 is 1: -// AUXIO[8i+6] is enabled for digital input. -// OUT Output Mode: -// -// GPIODOUT bit 6 drives -// AUXIO[8i+6]. -#define AUX_AIODIO_IOMODE_IO6_W 2 -#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 -#define AUX_AIODIO_IOMODE_IO6_S 12 -#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 -#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 -#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 -#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 - -// Field: [11:10] IO5 -// -// Select mode for AUXIO[8i+5]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When GPIODOUT bit 5 is 0: -// AUXIO[8i+5] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When GPIODOUT bit 5 is 1: -// AUXIO[8i+5] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When GPIODOUT bit 5 is 0: -// AUXIO[8i+5] is driven low. -// -// When GPIODOUT bit 5 is 1: -// AUXIO[8i+5] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 5 is 0: -// AUXIO[8i+5] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 5 is 1: -// AUXIO[8i+5] is enabled for digital input. -// OUT Output Mode: -// -// GPIODOUT bit 5 drives -// AUXIO[8i+5]. -#define AUX_AIODIO_IOMODE_IO5_W 2 -#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 -#define AUX_AIODIO_IOMODE_IO5_S 10 -#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 -#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 -#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 -#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 - -// Field: [9:8] IO4 -// -// Select mode for AUXIO[8i+4]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When GPIODOUT bit 4 is 0: -// AUXIO[8i+4] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When GPIODOUT bit 4 is 1: -// AUXIO[8i+4] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When GPIODOUT bit 4 is 0: -// AUXIO[8i+4] is driven low. -// -// When GPIODOUT bit 4 is 1: -// AUXIO[8i+4] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 4 is 0: -// AUXIO[8i+4] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 4 is 1: -// AUXIO[8i+4] is enabled for digital input. -// OUT Output Mode: -// -// GPIODOUT bit 4 drives -// AUXIO[8i+4]. -#define AUX_AIODIO_IOMODE_IO4_W 2 -#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 -#define AUX_AIODIO_IOMODE_IO4_S 8 -#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 -#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 -#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 -#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 - -// Field: [7:6] IO3 -// -// Select mode for AUXIO[8i+3]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When GPIODOUT bit 3 is 0: -// AUXIO[8i+3] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When GPIODOUT bit 3 is 1: -// AUXIO[8i+3] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When GPIODOUT bit 3 is 0: -// AUXIO[8i+3] is driven low. -// -// When GPIODOUT bit 3 is 1: -// AUXIO[8i+3] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 3 is 0: -// AUXIO[8i+3] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 3 is 1: -// AUXIO[8i+3] is enabled for digital input. -// OUT Output Mode: -// -// GPIODOUT bit 3 drives -// AUXIO[8i+3]. -#define AUX_AIODIO_IOMODE_IO3_W 2 -#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 -#define AUX_AIODIO_IOMODE_IO3_S 6 -#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 -#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 -#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 -#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 - -// Field: [5:4] IO2 -// -// Select mode for AUXIO[8i+2]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When GPIODOUT bit 2 is 0: -// AUXIO[8i+2] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When GPIODOUT bit 2 is 1: -// AUXIO[8i+2] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When GPIODOUT bit 2 is 0: -// AUXIO[8i+2] is driven low. -// -// When GPIODOUT bit 2 is 1: -// AUXIO[8i+2] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 2 is 0: -// AUXIO[8i+2] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 2 is 1: -// AUXIO[8i+2] is enabled for digital input. -// OUT Output Mode: -// -// GPIODOUT bit 2 drives -// AUXIO[8i+2]. -#define AUX_AIODIO_IOMODE_IO2_W 2 -#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 -#define AUX_AIODIO_IOMODE_IO2_S 4 -#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 -#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 -#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 -#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 - -// Field: [3:2] IO1 -// -// Select mode for AUXIO[8i+1]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When GPIODOUT bit 1 is 0: -// AUXIO[8i+1] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When GPIODOUT bit 1 is 1: -// AUXIO[8i+1] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When GPIODOUT bit 1 is 0: -// AUXIO[8i+1] is driven low. -// -// When GPIODOUT bit 1 is 1: -// AUXIO[8i+1] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 1 is 0: -// AUXIO[8i+1] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 1 is 1: -// AUXIO[8i+1] is enabled for digital input. -// OUT Output Mode: -// -// GPIODOUT bit 1 drives -// AUXIO[8i+1]. -#define AUX_AIODIO_IOMODE_IO1_W 2 -#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C -#define AUX_AIODIO_IOMODE_IO1_S 2 -#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C -#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 -#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 -#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 - -// Field: [1:0] IO0 -// -// Select mode for AUXIO[8i+0]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When GPIODOUT bit 0 is 0: -// AUXIO[8i+0] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When GPIODOUT bit 0 is 1: -// AUXIO[8i+0] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When GPIODOUT bit 0 is 0: -// AUXIO[8i+0] is driven low. -// -// When GPIODOUT bit 0 is 1: -// AUXIO[8i+0] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 0 is 0: -// AUXIO[8i+0] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 0 is 1: -// AUXIO[8i+0] is enabled for digital input. -// OUT Output Mode: -// -// GPIODOUT bit 0 drives -// AUXIO[8i+0]. -#define AUX_AIODIO_IOMODE_IO0_W 2 -#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 -#define AUX_AIODIO_IOMODE_IO0_S 0 -#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 -#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 -#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 -#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODIN -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit -// n is set. Otherwise, bit n value is old. -#define AUX_AIODIO_GPIODIN_IO7_0_W 8 -#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODIN_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODOUTSET -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to set GPIODOUT bit n. -// -// Read value is 0. -#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODOUTCLR -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. -// -// Read value is 0. -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODOUTTGL -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. -// -// Read value is 0. -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODIE -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to enable digital input buffer for -// AUXIO[8i+n]. -// Write 0 to bit index n in this bit vector to disable digital input buffer -// for AUXIO[8i+n]. -// -// You must enable the digital input buffer for AUXIO[8i+n] to read the pin -// value in GPIODIN. -// You must disable the digital input buffer for analog input or pins that -// float to avoid current leakage. -#define AUX_AIODIO_GPIODIE_IO7_0_W 8 -#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODIE_IO7_0_S 0 - - -#endif // __AUX_AIODIO__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aux_anaif.h b/third_party/ti/devices/cc26x0/inc/hw_aux_anaif.h deleted file mode 100644 index 5a75caca6..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aux_anaif.h +++ /dev/null @@ -1,305 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_anaif_h -* Revised: 2017-05-30 11:42:02 +0200 (Tue, 30 May 2017) -* Revision: 49074 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_ANAIF_H__ -#define __HW_AUX_ANAIF_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_ANAIF component -// -//***************************************************************************** -// ADC Control -#define AUX_ANAIF_O_ADCCTL 0x00000010 - -// ADC FIFO Status -#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 - -// ADC FIFO -#define AUX_ANAIF_O_ADCFIFO 0x00000018 - -// ADC Trigger -#define AUX_ANAIF_O_ADCTRIG 0x0000001C - -// Current Source Control -#define AUX_ANAIF_O_ISRCCTL 0x00000020 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_ADCCTL -// -//***************************************************************************** -// Field: [13] START_POL -// -// Select active polarity for START_SRC event. -// ENUMs: -// FALL Set ADC trigger on falling edge of event source. -// RISE Set ADC trigger on rising edge of event source. -#define AUX_ANAIF_ADCCTL_START_POL 0x00002000 -#define AUX_ANAIF_ADCCTL_START_POL_BITN 13 -#define AUX_ANAIF_ADCCTL_START_POL_M 0x00002000 -#define AUX_ANAIF_ADCCTL_START_POL_S 13 -#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00002000 -#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 - -// Field: [12:8] START_SRC -// -// Select ADC trigger event source from the asynchronous AUX event bus. -// -// Set START_SRC to NO_EVENT if you want to trigger the ADC manually through -// ADCTRIG.START. -// ENUMs: -// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ -// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF -// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU -// AON_SW AUX_EVCTL:EVSTAT0.AON_SW -// NO_EVENT1 No event. -// NO_EVENT0 No event. -// RESERVED1 Reserved - Do not use. -// RESERVED0 Reserved - Do not use. -// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV -// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV -// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE -// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA -// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_ANAIF_ADCCTL_START_SRC_W 5 -#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00001F00 -#define AUX_ANAIF_ADCCTL_START_SRC_S 8 -#define AUX_ANAIF_ADCCTL_START_SRC_ADC_IRQ 0x00001F00 -#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00001E00 -#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00001D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00001C00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00001B00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00001A00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00001900 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00001800 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00001700 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00001600 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00001500 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00001400 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00001300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00001200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00001100 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00001000 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000E00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_PROG_WU 0x00000C00 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_SW 0x00000B00 -#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT1 0x00000A00 -#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 0x00000900 -#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED1 0x00000800 -#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED0 0x00000700 -#define AUX_ANAIF_ADCCTL_START_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_ANAIF_ADCCTL_START_SRC_TIMER1_EV 0x00000500 -#define AUX_ANAIF_ADCCTL_START_SRC_TIMER0_EV 0x00000400 -#define AUX_ANAIF_ADCCTL_START_SRC_TDC_DONE 0x00000300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00000200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00000100 -#define AUX_ANAIF_ADCCTL_START_SRC_RTC_CH2_EV 0x00000000 - -// Field: [1:0] CMD -// -// ADC interface command. -// -// Non-enumerated values are not supported. The written value is returned when -// read. -// ENUMs: -// FLUSH Flush ADC FIFO. -// -// You must set CMD to EN or -// DIS after flush. -// -// System CPU must wait two -// clock cycles before it sets CMD to EN or DIS. -// EN Enable ADC interface. -// DIS Disable ADC interface. -#define AUX_ANAIF_ADCCTL_CMD_W 2 -#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 -#define AUX_ANAIF_ADCCTL_CMD_S 0 -#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 -#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 -#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_ADCFIFOSTAT -// -//***************************************************************************** -// Field: [4] OVERFLOW -// -// FIFO overflow flag. -// -// 0: FIFO has not overflowed. -// 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. -// -// When the flag is set, the ADC FIFO write pointer is static. It is not -// possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 - -// Field: [3] UNDERFLOW -// -// FIFO underflow flag. -// -// 0: FIFO has not underflowed. -// 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. -// -// When the flag is set, the ADC FIFO read pointer is static. Read returns the -// previous sample that was read. Flush FIFO to clear the flag. -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 - -// Field: [2] FULL -// -// FIFO full flag. -// -// 0: FIFO is not full, there is less than 4 samples in the FIFO. -// 1: FIFO is full, there are 4 samples in the FIFO. -// -// When the flag is set, it is not possible to add more samples to the ADC -// FIFO. An attempt to add samples sets the OVERFLOW flag. -#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 - -// Field: [1] ALMOST_FULL -// -// FIFO almost full flag. -// -// 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL -// flag is also asserted in the latter case. -// 1: There are 3 samples in the FIFO, there is room for one more sample. -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 - -// Field: [0] EMPTY -// -// FIFO empty flag. -// -// 0: FIFO contains one or more samples. -// 1: FIFO is empty. -// -// When the flag is set, read returns the previous sample that was read and -// sets the UNDERFLOW flag. -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_ADCFIFO -// -//***************************************************************************** -// Field: [11:0] DATA -// -// FIFO data. -// -// Read: -// Get oldest ADC sample from FIFO. -// -// Write: -// Write dummy sample to FIFO. This is useful for code development when you do -// not have real ADC samples. -#define AUX_ANAIF_ADCFIFO_DATA_W 12 -#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF -#define AUX_ANAIF_ADCFIFO_DATA_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_ADCTRIG -// -//***************************************************************************** -// Field: [0] START -// -// Manual ADC trigger. -// -// 0: No effect. -// 1: Single ADC trigger. -// -// To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to -// avoid conflict with event-driven ADC trigger. -#define AUX_ANAIF_ADCTRIG_START 0x00000001 -#define AUX_ANAIF_ADCTRIG_START_BITN 0 -#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 -#define AUX_ANAIF_ADCTRIG_START_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_ISRCCTL -// -//***************************************************************************** -// Field: [0] RESET_N -// -// ISRC reset control. -// -// 0: ISRC drives 0 uA. -// 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. -#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 -#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 -#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 -#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 - - -#endif // __AUX_ANAIF__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aux_evctl.h b/third_party/ti/devices/cc26x0/inc/hw_aux_evctl.h deleted file mode 100644 index 49bb69c0f..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aux_evctl.h +++ /dev/null @@ -1,1852 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_evctl_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_EVCTL_H__ -#define __HW_AUX_EVCTL_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_EVCTL component -// -//***************************************************************************** -// Vector Configuration 0 -#define AUX_EVCTL_O_VECCFG0 0x00000000 - -// Vector Configuration 1 -#define AUX_EVCTL_O_VECCFG1 0x00000004 - -// Sensor Controller Engine Wait Event Selection -#define AUX_EVCTL_O_SCEWEVSEL 0x00000008 - -// Events To AON Flags -#define AUX_EVCTL_O_EVTOAONFLAGS 0x0000000C - -// Events To AON Polarity -#define AUX_EVCTL_O_EVTOAONPOL 0x00000010 - -// Direct Memory Access Control -#define AUX_EVCTL_O_DMACTL 0x00000014 - -// Software Event Set -#define AUX_EVCTL_O_SWEVSET 0x00000018 - -// Event Status 0 -#define AUX_EVCTL_O_EVSTAT0 0x0000001C - -// Event Status 1 -#define AUX_EVCTL_O_EVSTAT1 0x00000020 - -// Event To MCU Polarity -#define AUX_EVCTL_O_EVTOMCUPOL 0x00000024 - -// Events to MCU Flags -#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000028 - -// Combined Event To MCU Mask -#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000002C - -// Vector Flags -#define AUX_EVCTL_O_VECFLAGS 0x00000034 - -// Events To MCU Flags Clear -#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 - -// Events To AON Clear -#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000003C - -// Vector Flags Clear -#define AUX_EVCTL_O_VECFLAGSCLR 0x00000040 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_VECCFG0 -// -//***************************************************************************** -// Field: [14] VEC1_POL -// -// Vector 1 trigger event polarity. -// -// To manually trigger vector 1 execution: -// - AUX_SCE must sleep. -// - Set VEC1_EV to a known static value. -// - Toggle VEC1_POL twice. -// ENUMs: -// FALL Falling edge triggers vector 1 execution. -// RISE Rising edge triggers vector 1 execution. -#define AUX_EVCTL_VECCFG0_VEC1_POL 0x00004000 -#define AUX_EVCTL_VECCFG0_VEC1_POL_BITN 14 -#define AUX_EVCTL_VECCFG0_VEC1_POL_M 0x00004000 -#define AUX_EVCTL_VECCFG0_VEC1_POL_S 14 -#define AUX_EVCTL_VECCFG0_VEC1_POL_FALL 0x00004000 -#define AUX_EVCTL_VECCFG0_VEC1_POL_RISE 0x00000000 - -// Field: [13] VEC1_EN -// -// Vector 1 trigger enable. -// -// When enabled, VEC1_EV event with VEC1_POL polarity triggers a jump to vector -// # 1 when AUX_SCE sleeps. -// -// Lower vectors (0) have priority. -// ENUMs: -// EN Enable vector 1 trigger. -// DIS Disable vector 1 trigger. -#define AUX_EVCTL_VECCFG0_VEC1_EN 0x00002000 -#define AUX_EVCTL_VECCFG0_VEC1_EN_BITN 13 -#define AUX_EVCTL_VECCFG0_VEC1_EN_M 0x00002000 -#define AUX_EVCTL_VECCFG0_VEC1_EN_S 13 -#define AUX_EVCTL_VECCFG0_VEC1_EN_EN 0x00002000 -#define AUX_EVCTL_VECCFG0_VEC1_EN_DIS 0x00000000 - -// Field: [12:8] VEC1_EV -// -// Select vector 1 trigger source event. -// ENUMs: -// ADC_IRQ EVSTAT1.ADC_IRQ -// MCU_EV EVSTAT1.MCU_EV -// ACLK_REF EVSTAT1.ACLK_REF -// AUXIO15 EVSTAT1.AUXIO15 -// AUXIO14 EVSTAT1.AUXIO14 -// AUXIO13 EVSTAT1.AUXIO13 -// AUXIO12 EVSTAT1.AUXIO12 -// AUXIO11 EVSTAT1.AUXIO11 -// AUXIO10 EVSTAT1.AUXIO10 -// AUXIO9 EVSTAT1.AUXIO9 -// AUXIO8 EVSTAT1.AUXIO8 -// AUXIO7 EVSTAT1.AUXIO7 -// AUXIO6 EVSTAT1.AUXIO6 -// AUXIO5 EVSTAT1.AUXIO5 -// AUXIO4 EVSTAT1.AUXIO4 -// AUXIO3 EVSTAT1.AUXIO3 -// AUXIO2 EVSTAT0.AUXIO2 -// AUXIO1 EVSTAT0.AUXIO1 -// AUXIO0 EVSTAT0.AUXIO0 -// AON_PROG_WU EVSTAT0.AON_PROG_WU -// AON_SW EVSTAT0.AON_SW -// OBSMUX1 EVSTAT0.OBSMUX1 -// OBSMUX0 EVSTAT0.OBSMUX0 -// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL -// ADC_DONE EVSTAT0.ADC_DONE -// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER1_EV EVSTAT0.TIMER1_EV -// TIMER0_EV EVSTAT0.TIMER0_EV -// TDC_DONE EVSTAT0.TDC_DONE -// AUX_COMPB EVSTAT0.AUX_COMPB -// AUX_COMPA EVSTAT0.AUX_COMPA -// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG0_VEC1_EV_W 5 -#define AUX_EVCTL_VECCFG0_VEC1_EV_M 0x00001F00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_S 8 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_IRQ 0x00001F00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_MCU_EV 0x00001E00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ACLK_REF 0x00001D00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO15 0x00001C00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO14 0x00001B00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO13 0x00001A00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO12 0x00001900 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO11 0x00001800 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO10 0x00001700 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO9 0x00001600 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO8 0x00001500 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO7 0x00001400 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO6 0x00001300 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO5 0x00001200 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO4 0x00001100 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO3 0x00001000 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO2 0x00000F00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO1 0x00000E00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO0 0x00000D00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_PROG_WU 0x00000C00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_SW 0x00000B00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX1 0x00000A00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX0 0x00000900 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_DONE 0x00000700 -#define AUX_EVCTL_VECCFG0_VEC1_EV_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER1_EV 0x00000500 -#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER0_EV 0x00000400 -#define AUX_EVCTL_VECCFG0_VEC1_EV_TDC_DONE 0x00000300 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPB 0x00000200 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPA 0x00000100 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_RTC_CH2 0x00000000 - -// Field: [6] VEC0_POL -// -// Vector 0 trigger event polarity. -// -// To manually trigger vector 0 execution: -// - AUX_SCE must sleep. -// - Set VEC0_EV to a known static value. -// - Toggle VEC0_POL twice. -// ENUMs: -// FALL Falling edge triggers vector 0 execution. -// RISE Rising edge triggers vector 0 execution. -#define AUX_EVCTL_VECCFG0_VEC0_POL 0x00000040 -#define AUX_EVCTL_VECCFG0_VEC0_POL_BITN 6 -#define AUX_EVCTL_VECCFG0_VEC0_POL_M 0x00000040 -#define AUX_EVCTL_VECCFG0_VEC0_POL_S 6 -#define AUX_EVCTL_VECCFG0_VEC0_POL_FALL 0x00000040 -#define AUX_EVCTL_VECCFG0_VEC0_POL_RISE 0x00000000 - -// Field: [5] VEC0_EN -// -// Vector 0 trigger enable. -// -// When enabled, VEC0_EV event with VEC0_POL polarity triggers a jump to vector -// # 0 when AUX_SCE sleeps. -// ENUMs: -// EN Enable vector 0 trigger. -// DIS Disable vector 0 trigger. -#define AUX_EVCTL_VECCFG0_VEC0_EN 0x00000020 -#define AUX_EVCTL_VECCFG0_VEC0_EN_BITN 5 -#define AUX_EVCTL_VECCFG0_VEC0_EN_M 0x00000020 -#define AUX_EVCTL_VECCFG0_VEC0_EN_S 5 -#define AUX_EVCTL_VECCFG0_VEC0_EN_EN 0x00000020 -#define AUX_EVCTL_VECCFG0_VEC0_EN_DIS 0x00000000 - -// Field: [4:0] VEC0_EV -// -// Select vector 0 trigger source event. -// ENUMs: -// ADC_IRQ EVSTAT1.ADC_IRQ -// MCU_EV EVSTAT1.MCU_EV -// ACLK_REF EVSTAT1.ACLK_REF -// AUXIO15 EVSTAT1.AUXIO15 -// AUXIO14 EVSTAT1.AUXIO14 -// AUXIO13 EVSTAT1.AUXIO13 -// AUXIO12 EVSTAT1.AUXIO12 -// AUXIO11 EVSTAT1.AUXIO11 -// AUXIO10 EVSTAT1.AUXIO10 -// AUXIO9 EVSTAT1.AUXIO9 -// AUXIO8 EVSTAT1.AUXIO8 -// AUXIO7 EVSTAT1.AUXIO7 -// AUXIO6 EVSTAT1.AUXIO6 -// AUXIO5 EVSTAT1.AUXIO5 -// AUXIO4 EVSTAT1.AUXIO4 -// AUXIO3 EVSTAT1.AUXIO3 -// AUXIO2 EVSTAT0.AUXIO2 -// AUXIO1 EVSTAT0.AUXIO1 -// AUXIO0 EVSTAT0.AUXIO0 -// AON_PROG_WU EVSTAT0.AON_PROG_WU -// AON_SW EVSTAT0.AON_SW -// OBSMUX1 EVSTAT0.OBSMUX1 -// OBSMUX0 EVSTAT0.OBSMUX0 -// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL -// ADC_DONE EVSTAT0.ADC_DONE -// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER1_EV EVSTAT0.TIMER1_EV -// TIMER0_EV EVSTAT0.TIMER0_EV -// TDC_DONE EVSTAT0.TDC_DONE -// AUX_COMPB EVSTAT0.AUX_COMPB -// AUX_COMPA EVSTAT0.AUX_COMPA -// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG0_VEC0_EV_W 5 -#define AUX_EVCTL_VECCFG0_VEC0_EV_M 0x0000001F -#define AUX_EVCTL_VECCFG0_VEC0_EV_S 0 -#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_IRQ 0x0000001F -#define AUX_EVCTL_VECCFG0_VEC0_EV_MCU_EV 0x0000001E -#define AUX_EVCTL_VECCFG0_VEC0_EV_ACLK_REF 0x0000001D -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO15 0x0000001C -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO14 0x0000001B -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO13 0x0000001A -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO12 0x00000019 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO11 0x00000018 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO10 0x00000017 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO9 0x00000016 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO8 0x00000015 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO7 0x00000014 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO6 0x00000013 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO5 0x00000012 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO4 0x00000011 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO3 0x00000010 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO2 0x0000000F -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO1 0x0000000E -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO0 0x0000000D -#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_PROG_WU 0x0000000C -#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_SW 0x0000000B -#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX1 0x0000000A -#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX0 0x00000009 -#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_DONE 0x00000007 -#define AUX_EVCTL_VECCFG0_VEC0_EV_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER1_EV 0x00000005 -#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER0_EV 0x00000004 -#define AUX_EVCTL_VECCFG0_VEC0_EV_TDC_DONE 0x00000003 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPB 0x00000002 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPA 0x00000001 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_RTC_CH2 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_VECCFG1 -// -//***************************************************************************** -// Field: [14] VEC3_POL -// -// Vector 3 trigger event polarity. -// -// To manually trigger vector 3 execution: -// - AUX_SCE must sleep. -// - Set VEC3_EV to a known static value. -// - Toggle VEC3_POL twice. -// ENUMs: -// FALL Falling edge triggers vector 3 execution. -// RISE Rising edge triggers vector 3 execution. -#define AUX_EVCTL_VECCFG1_VEC3_POL 0x00004000 -#define AUX_EVCTL_VECCFG1_VEC3_POL_BITN 14 -#define AUX_EVCTL_VECCFG1_VEC3_POL_M 0x00004000 -#define AUX_EVCTL_VECCFG1_VEC3_POL_S 14 -#define AUX_EVCTL_VECCFG1_VEC3_POL_FALL 0x00004000 -#define AUX_EVCTL_VECCFG1_VEC3_POL_RISE 0x00000000 - -// Field: [13] VEC3_EN -// -// Vector 3 trigger enable. -// -// When enabled, VEC3_EV event with VEC3_POL polarity triggers a jump to vector -// # 3 when AUX_SCE sleeps. -// -// Lower vectors (0, 1, and 2) have priority. -// ENUMs: -// EN Enable vector 3 trigger. -// DIS Disable vector 3 trigger. -#define AUX_EVCTL_VECCFG1_VEC3_EN 0x00002000 -#define AUX_EVCTL_VECCFG1_VEC3_EN_BITN 13 -#define AUX_EVCTL_VECCFG1_VEC3_EN_M 0x00002000 -#define AUX_EVCTL_VECCFG1_VEC3_EN_S 13 -#define AUX_EVCTL_VECCFG1_VEC3_EN_EN 0x00002000 -#define AUX_EVCTL_VECCFG1_VEC3_EN_DIS 0x00000000 - -// Field: [12:8] VEC3_EV -// -// Select vector 3 trigger source event. -// ENUMs: -// ADC_IRQ EVSTAT1.ADC_IRQ -// MCU_EV EVSTAT1.MCU_EV -// ACLK_REF EVSTAT1.ACLK_REF -// AUXIO15 EVSTAT1.AUXIO15 -// AUXIO14 EVSTAT1.AUXIO14 -// AUXIO13 EVSTAT1.AUXIO13 -// AUXIO12 EVSTAT1.AUXIO12 -// AUXIO11 EVSTAT1.AUXIO11 -// AUXIO10 EVSTAT1.AUXIO10 -// AUXIO9 EVSTAT1.AUXIO9 -// AUXIO8 EVSTAT1.AUXIO8 -// AUXIO7 EVSTAT1.AUXIO7 -// AUXIO6 EVSTAT1.AUXIO6 -// AUXIO5 EVSTAT1.AUXIO5 -// AUXIO4 EVSTAT1.AUXIO4 -// AUXIO3 EVSTAT1.AUXIO3 -// AUXIO2 EVSTAT0.AUXIO2 -// AUXIO1 EVSTAT0.AUXIO1 -// AUXIO0 EVSTAT0.AUXIO0 -// AON_PROG_WU EVSTAT0.AON_PROG_WU -// AON_SW EVSTAT0.AON_SW -// OBSMUX1 EVSTAT0.OBSMUX1 -// OBSMUX0 EVSTAT0.OBSMUX0 -// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL -// ADC_DONE EVSTAT0.ADC_DONE -// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER1_EV EVSTAT0.TIMER1_EV -// TIMER0_EV EVSTAT0.TIMER0_EV -// TDC_DONE EVSTAT0.TDC_DONE -// AUX_COMPB EVSTAT0.AUX_COMPB -// AUX_COMPA EVSTAT0.AUX_COMPA -// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG1_VEC3_EV_W 5 -#define AUX_EVCTL_VECCFG1_VEC3_EV_M 0x00001F00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_S 8 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_IRQ 0x00001F00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_MCU_EV 0x00001E00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ACLK_REF 0x00001D00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO15 0x00001C00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO14 0x00001B00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO13 0x00001A00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO12 0x00001900 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO11 0x00001800 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO10 0x00001700 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO9 0x00001600 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO8 0x00001500 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO7 0x00001400 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO6 0x00001300 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO5 0x00001200 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO4 0x00001100 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO3 0x00001000 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO2 0x00000F00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO1 0x00000E00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO0 0x00000D00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_PROG_WU 0x00000C00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_SW 0x00000B00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX1 0x00000A00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX0 0x00000900 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_DONE 0x00000700 -#define AUX_EVCTL_VECCFG1_VEC3_EV_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER1_EV 0x00000500 -#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER0_EV 0x00000400 -#define AUX_EVCTL_VECCFG1_VEC3_EV_TDC_DONE 0x00000300 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPB 0x00000200 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPA 0x00000100 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_RTC_CH2 0x00000000 - -// Field: [6] VEC2_POL -// -// Vector 2 trigger event polarity. -// -// To manually trigger vector 2 execution: -// - AUX_SCE must sleep. -// - Set VEC2_EV to a known static value. -// - Toggle VEC2_POL twice. -// ENUMs: -// FALL Falling edge triggers vector 2 execution. -// RISE Rising edge triggers vector 2 execution. -#define AUX_EVCTL_VECCFG1_VEC2_POL 0x00000040 -#define AUX_EVCTL_VECCFG1_VEC2_POL_BITN 6 -#define AUX_EVCTL_VECCFG1_VEC2_POL_M 0x00000040 -#define AUX_EVCTL_VECCFG1_VEC2_POL_S 6 -#define AUX_EVCTL_VECCFG1_VEC2_POL_FALL 0x00000040 -#define AUX_EVCTL_VECCFG1_VEC2_POL_RISE 0x00000000 - -// Field: [5] VEC2_EN -// -// Vector 2 trigger enable. -// -// When enabled, VEC2_EV event with VEC2_POL polarity triggers a jump to vector -// # 2 when AUX_SCE sleeps. -// -// Lower vectors (0 and 1) have priority. -// ENUMs: -// EN Enable vector 2 trigger. -// DIS Disable vector 2 trigger. -#define AUX_EVCTL_VECCFG1_VEC2_EN 0x00000020 -#define AUX_EVCTL_VECCFG1_VEC2_EN_BITN 5 -#define AUX_EVCTL_VECCFG1_VEC2_EN_M 0x00000020 -#define AUX_EVCTL_VECCFG1_VEC2_EN_S 5 -#define AUX_EVCTL_VECCFG1_VEC2_EN_EN 0x00000020 -#define AUX_EVCTL_VECCFG1_VEC2_EN_DIS 0x00000000 - -// Field: [4:0] VEC2_EV -// -// Select vector 2 trigger source event. -// ENUMs: -// ADC_IRQ EVSTAT1.ADC_IRQ -// MCU_EV EVSTAT1.MCU_EV -// ACLK_REF EVSTAT1.ACLK_REF -// AUXIO15 EVSTAT1.AUXIO15 -// AUXIO14 EVSTAT1.AUXIO14 -// AUXIO13 EVSTAT1.AUXIO13 -// AUXIO12 EVSTAT1.AUXIO12 -// AUXIO11 EVSTAT1.AUXIO11 -// AUXIO10 EVSTAT1.AUXIO10 -// AUXIO9 EVSTAT1.AUXIO9 -// AUXIO8 EVSTAT1.AUXIO8 -// AUXIO7 EVSTAT1.AUXIO7 -// AUXIO6 EVSTAT1.AUXIO6 -// AUXIO5 EVSTAT1.AUXIO5 -// AUXIO4 EVSTAT1.AUXIO4 -// AUXIO3 EVSTAT1.AUXIO3 -// AUXIO2 EVSTAT0.AUXIO2 -// AUXIO1 EVSTAT0.AUXIO1 -// AUXIO0 EVSTAT0.AUXIO0 -// AON_PROG_WU EVSTAT0.AON_PROG_WU -// AON_SW EVSTAT0.AON_SW -// OBSMUX1 EVSTAT0.OBSMUX1 -// OBSMUX0 EVSTAT0.OBSMUX0 -// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL -// ADC_DONE EVSTAT0.ADC_DONE -// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER1_EV EVSTAT0.TIMER1_EV -// TIMER0_EV EVSTAT0.TIMER0_EV -// TDC_DONE EVSTAT0.TDC_DONE -// AUX_COMPB EVSTAT0.AUX_COMPB -// AUX_COMPA EVSTAT0.AUX_COMPA -// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG1_VEC2_EV_W 5 -#define AUX_EVCTL_VECCFG1_VEC2_EV_M 0x0000001F -#define AUX_EVCTL_VECCFG1_VEC2_EV_S 0 -#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_IRQ 0x0000001F -#define AUX_EVCTL_VECCFG1_VEC2_EV_MCU_EV 0x0000001E -#define AUX_EVCTL_VECCFG1_VEC2_EV_ACLK_REF 0x0000001D -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO15 0x0000001C -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO14 0x0000001B -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO13 0x0000001A -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO12 0x00000019 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO11 0x00000018 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO10 0x00000017 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO9 0x00000016 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO8 0x00000015 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO7 0x00000014 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO6 0x00000013 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO5 0x00000012 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO4 0x00000011 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO3 0x00000010 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO2 0x0000000F -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO1 0x0000000E -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO0 0x0000000D -#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_PROG_WU 0x0000000C -#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_SW 0x0000000B -#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX1 0x0000000A -#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX0 0x00000009 -#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_DONE 0x00000007 -#define AUX_EVCTL_VECCFG1_VEC2_EV_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER1_EV 0x00000005 -#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER0_EV 0x00000004 -#define AUX_EVCTL_VECCFG1_VEC2_EV_TDC_DONE 0x00000003 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPB 0x00000002 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPA 0x00000001 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_RTC_CH2 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_SCEWEVSEL -// -//***************************************************************************** -// Field: [4:0] WEV7_EV -// -// Select event source to connect to AUX_SCE:WUSTAT.EV_SIGNALS bit 7. -// ENUMs: -// ADC_IRQ EVSTAT1.ADC_IRQ -// MCU_EV EVSTAT1.MCU_EV -// ACLK_REF EVSTAT1.ACLK_REF -// AUXIO15 EVSTAT1.AUXIO15 -// AUXIO14 EVSTAT1.AUXIO14 -// AUXIO13 EVSTAT1.AUXIO13 -// AUXIO12 EVSTAT1.AUXIO12 -// AUXIO11 EVSTAT1.AUXIO11 -// AUXIO10 EVSTAT1.AUXIO10 -// AUXIO9 EVSTAT1.AUXIO9 -// AUXIO8 EVSTAT1.AUXIO8 -// AUXIO7 EVSTAT1.AUXIO7 -// AUXIO6 EVSTAT1.AUXIO6 -// AUXIO5 EVSTAT1.AUXIO5 -// AUXIO4 EVSTAT1.AUXIO4 -// AUXIO3 EVSTAT1.AUXIO3 -// AUXIO2 EVSTAT0.AUXIO2 -// AUXIO1 EVSTAT0.AUXIO1 -// AUXIO0 EVSTAT0.AUXIO0 -// AON_PROG_WU EVSTAT0.AON_PROG_WU -// AON_SW EVSTAT0.AON_SW -// OBSMUX1 EVSTAT0.OBSMUX1 -// OBSMUX0 EVSTAT0.OBSMUX0 -// ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL -// ADC_DONE EVSTAT0.ADC_DONE -// SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER1_EV EVSTAT0.TIMER1_EV -// TIMER0_EV EVSTAT0.TIMER0_EV -// TDC_DONE EVSTAT0.TDC_DONE -// AUX_COMPB EVSTAT0.AUX_COMPB -// AUX_COMPA EVSTAT0.AUX_COMPA -// AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_W 5 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_M 0x0000001F -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_S 0 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_IRQ 0x0000001F -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_MCU_EV 0x0000001E -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ACLK_REF 0x0000001D -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO15 0x0000001C -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO14 0x0000001B -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO13 0x0000001A -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO12 0x00000019 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO11 0x00000018 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO10 0x00000017 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO9 0x00000016 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO8 0x00000015 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO7 0x00000014 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO6 0x00000013 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO5 0x00000012 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO4 0x00000011 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO3 0x00000010 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO2 0x0000000F -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO1 0x0000000E -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO0 0x0000000D -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_PROG_WU 0x0000000C -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_SW 0x0000000B -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX1 0x0000000A -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX0 0x00000009 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_DONE 0x00000007 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER1_EV 0x00000005 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER0_EV 0x00000004 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TDC_DONE 0x00000003 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPB 0x00000002 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPA 0x00000001 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_RTC_CH2 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOAONFLAGS -// -//***************************************************************************** -// Field: [8] TIMER1_EV -// -// This event flag is set when level selected by EVTOAONPOL.TIMER1_EV occurs on -// EVSTAT0.TIMER1_EV. -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_S 8 - -// Field: [7] TIMER0_EV -// -// This event flag is set when level selected by EVTOAONPOL.TIMER0_EV occurs on -// EVSTAT0.TIMER0_EV. -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_S 7 - -// Field: [6] TDC_DONE -// -// This event flag is set when level selected by EVTOAONPOL.TDC_DONE occurs on -// EVSTAT0.TDC_DONE. -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_S 6 - -// Field: [5] ADC_DONE -// -// This event flag is set when level selected by EVTOAONPOL.ADC_DONE occurs on -// EVSTAT0.ADC_DONE. -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_S 5 - -// Field: [4] AUX_COMPB -// -// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on -// EVSTAT0.AUX_COMPB. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 - -// Field: [3] AUX_COMPA -// -// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on -// EVSTAT0.AUX_COMPA. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 - -// Field: [2] SWEV2 -// -// This event flag is set when software writes a 1 to SWEVSET.SWEV2. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 - -// Field: [1] SWEV1 -// -// This event flag is set when software writes a 1 to SWEVSET.SWEV1. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 - -// Field: [0] SWEV0 -// -// This event flag is set when software writes a 1 to SWEVSET.SWEV0. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOAONPOL -// -//***************************************************************************** -// Field: [8] TIMER1_EV -// -// Select the level of EVSTAT0.TIMER1_EV that sets EVTOAONFLAGS.TIMER1_EV. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_S 8 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_LOW 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_HIGH 0x00000000 - -// Field: [7] TIMER0_EV -// -// Select the level of EVSTAT0.TIMER0_EV that sets EVTOAONFLAGS.TIMER0_EV. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_S 7 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_LOW 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_HIGH 0x00000000 - -// Field: [6] TDC_DONE -// -// Select level of EVSTAT0.TDC_DONE that sets EVTOAONFLAGS.TDC_DONE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_S 6 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_LOW 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_HIGH 0x00000000 - -// Field: [5] ADC_DONE -// -// Select the level of EVSTAT0.ADC_DONE that sets EVTOAONFLAGS.ADC_DONE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_S 5 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_LOW 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_HIGH 0x00000000 - -// Field: [4] AUX_COMPB -// -// Select the edge of EVSTAT0.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB. -// ENUMs: -// LOW Falling edge -// HIGH Rising edge -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_LOW 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_HIGH 0x00000000 - -// Field: [3] AUX_COMPA -// -// Select the edge of EVSTAT0.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA. -// ENUMs: -// LOW Falling edge -// HIGH Rising edge -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_LOW 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_HIGH 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_DMACTL -// -//***************************************************************************** -// Field: [2] REQ_MODE -// -// UDMA0 Request mode -// ENUMs: -// SINGLE Single requests are generated on UDMA0 channel 7 -// when the condition configured in SEL is met. -// BURST Burst requests are generated on UDMA0 channel 7 -// when the condition configured in SEL is met. -#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 -#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 -#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 - -// Field: [1] EN -// -// uDMA ADC interface enable. -// -// 0: Disable UDMA0 interface to ADC. -// 1: Enable UDMA0 interface to ADC. -#define AUX_EVCTL_DMACTL_EN 0x00000002 -#define AUX_EVCTL_DMACTL_EN_BITN 1 -#define AUX_EVCTL_DMACTL_EN_M 0x00000002 -#define AUX_EVCTL_DMACTL_EN_S 1 - -// Field: [0] SEL -// -// Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO -// data. -// ENUMs: -// FIFO_ALMOST_FULL UDMA0 trigger event will be generated when the ADC -// FIFO is almost full (3/4 full). -// FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there -// are samples in the ADC FIFO. -#define AUX_EVCTL_DMACTL_SEL 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_BITN 0 -#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_S 0 -#define AUX_EVCTL_DMACTL_SEL_FIFO_ALMOST_FULL 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_SWEVSET -// -//***************************************************************************** -// Field: [2] SWEV2 -// -// Software event flag 2. -// -// 0: No effect. -// 1: Set software event flag 2. -#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 -#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 -#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 -#define AUX_EVCTL_SWEVSET_SWEV2_S 2 - -// Field: [1] SWEV1 -// -// Software event flag 1. -// -// 0: No effect. -// 1: Set software event flag 1. -#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 -#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 -#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 -#define AUX_EVCTL_SWEVSET_SWEV1_S 1 - -// Field: [0] SWEV0 -// -// Software event flag 0. -// -// 0: No effect. -// 1: Set software event flag 0. -#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 -#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 -#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 -#define AUX_EVCTL_SWEVSET_SWEV0_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT0 -// -//***************************************************************************** -// Field: [15] AUXIO2 -// -// AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00008000 -#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 15 -#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00008000 -#define AUX_EVCTL_EVSTAT0_AUXIO2_S 15 - -// Field: [14] AUXIO1 -// -// AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00004000 -#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 14 -#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00004000 -#define AUX_EVCTL_EVSTAT0_AUXIO1_S 14 - -// Field: [13] AUXIO0 -// -// AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00002000 -#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 13 -#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00002000 -#define AUX_EVCTL_EVSTAT0_AUXIO0_S 13 - -// Field: [12] AON_PROG_WU -// -// AON_EVENT:AUXWUSEL.WU2_EV OR AON_EVENT:AUXWUSEL.WU1_EV OR -// AON_EVENT:AUXWUSEL.WU0_EV -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU 0x00001000 -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_BITN 12 -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_M 0x00001000 -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_S 12 - -// Field: [11] AON_SW -// -// AON_WUC:AUXCTL.SWEV -#define AUX_EVCTL_EVSTAT0_AON_SW 0x00000800 -#define AUX_EVCTL_EVSTAT0_AON_SW_BITN 11 -#define AUX_EVCTL_EVSTAT0_AON_SW_M 0x00000800 -#define AUX_EVCTL_EVSTAT0_AON_SW_S 11 - -// Field: [10] OBSMUX1 -// -// Observation input 1 from IOC. -// This event is configured by IOC:OBSAUXOUTPUT.SEL1. -#define AUX_EVCTL_EVSTAT0_OBSMUX1 0x00000400 -#define AUX_EVCTL_EVSTAT0_OBSMUX1_BITN 10 -#define AUX_EVCTL_EVSTAT0_OBSMUX1_M 0x00000400 -#define AUX_EVCTL_EVSTAT0_OBSMUX1_S 10 - -// Field: [9] OBSMUX0 -// -// Observation input 0 from IOC. -// This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by -// IOC:OBSAUXOUTPUT.SEL_MISC. -#define AUX_EVCTL_EVSTAT0_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVSTAT0_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVSTAT0_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVSTAT0_OBSMUX0_S 9 - -// Field: [8] ADC_FIFO_ALMOST_FULL -// -// AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_S 8 - -// Field: [7] ADC_DONE -// -// AUX_ANAIF ADC conversion done event. -#define AUX_EVCTL_EVSTAT0_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVSTAT0_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVSTAT0_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVSTAT0_ADC_DONE_S 7 - -// Field: [6] SMPH_AUTOTAKE_DONE -// -// See AUX_SMPH:AUTOTAKE.SMPH_ID for description. -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_S 6 - -// Field: [5] TIMER1_EV -// -// AUX_TIMER1_EV event, see AUX_TIMER:T1TARGET for description. -#define AUX_EVCTL_EVSTAT0_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVSTAT0_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVSTAT0_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVSTAT0_TIMER1_EV_S 5 - -// Field: [4] TIMER0_EV -// -// AUX_TIMER0_EV event, see AUX_TIMER:T0TARGET for description. -#define AUX_EVCTL_EVSTAT0_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVSTAT0_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVSTAT0_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVSTAT0_TIMER0_EV_S 4 - -// Field: [3] TDC_DONE -// -// AUX_TDC:STAT.DONE -#define AUX_EVCTL_EVSTAT0_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVSTAT0_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVSTAT0_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVSTAT0_TDC_DONE_S 3 - -// Field: [2] AUX_COMPB -// -// Comparator B output -#define AUX_EVCTL_EVSTAT0_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVSTAT0_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVSTAT0_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVSTAT0_AUX_COMPB_S 2 - -// Field: [1] AUX_COMPA -// -// Comparator A output -#define AUX_EVCTL_EVSTAT0_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVSTAT0_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVSTAT0_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVSTAT0_AUX_COMPA_S 1 - -// Field: [0] AON_RTC_CH2 -// -// AON_RTC:EVFLAGS.CH2 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2 0x00000001 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_BITN 0 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_M 0x00000001 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT1 -// -//***************************************************************************** -// Field: [15] ADC_IRQ -// -// The logical function for this event is configurable. -// -// When DMACTL.EN = 1 : -// Event = UDMA0 Channel 7 done event OR -// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW -// -// When DMACTL.EN = 0 : -// Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR -// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW -// -// Bit 7 in UDMA0:DONEMASK must be 0. -#define AUX_EVCTL_EVSTAT1_ADC_IRQ 0x00008000 -#define AUX_EVCTL_EVSTAT1_ADC_IRQ_BITN 15 -#define AUX_EVCTL_EVSTAT1_ADC_IRQ_M 0x00008000 -#define AUX_EVCTL_EVSTAT1_ADC_IRQ_S 15 - -// Field: [14] MCU_EV -// -// Event from EVENT configured by EVENT:AUXSEL0. -#define AUX_EVCTL_EVSTAT1_MCU_EV 0x00004000 -#define AUX_EVCTL_EVSTAT1_MCU_EV_BITN 14 -#define AUX_EVCTL_EVSTAT1_MCU_EV_M 0x00004000 -#define AUX_EVCTL_EVSTAT1_MCU_EV_S 14 - -// Field: [13] ACLK_REF -// -// TDC reference clock. -// It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by -// AUX_WUC:REFCLKCTL.REQ. -#define AUX_EVCTL_EVSTAT1_ACLK_REF 0x00002000 -#define AUX_EVCTL_EVSTAT1_ACLK_REF_BITN 13 -#define AUX_EVCTL_EVSTAT1_ACLK_REF_M 0x00002000 -#define AUX_EVCTL_EVSTAT1_ACLK_REF_S 13 - -// Field: [12] AUXIO15 -// -// AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT1_AUXIO15 0x00001000 -#define AUX_EVCTL_EVSTAT1_AUXIO15_BITN 12 -#define AUX_EVCTL_EVSTAT1_AUXIO15_M 0x00001000 -#define AUX_EVCTL_EVSTAT1_AUXIO15_S 12 - -// Field: [11] AUXIO14 -// -// AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT1_AUXIO14 0x00000800 -#define AUX_EVCTL_EVSTAT1_AUXIO14_BITN 11 -#define AUX_EVCTL_EVSTAT1_AUXIO14_M 0x00000800 -#define AUX_EVCTL_EVSTAT1_AUXIO14_S 11 - -// Field: [10] AUXIO13 -// -// AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT1_AUXIO13 0x00000400 -#define AUX_EVCTL_EVSTAT1_AUXIO13_BITN 10 -#define AUX_EVCTL_EVSTAT1_AUXIO13_M 0x00000400 -#define AUX_EVCTL_EVSTAT1_AUXIO13_S 10 - -// Field: [9] AUXIO12 -// -// AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT1_AUXIO12 0x00000200 -#define AUX_EVCTL_EVSTAT1_AUXIO12_BITN 9 -#define AUX_EVCTL_EVSTAT1_AUXIO12_M 0x00000200 -#define AUX_EVCTL_EVSTAT1_AUXIO12_S 9 - -// Field: [8] AUXIO11 -// -// AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT1_AUXIO11 0x00000100 -#define AUX_EVCTL_EVSTAT1_AUXIO11_BITN 8 -#define AUX_EVCTL_EVSTAT1_AUXIO11_M 0x00000100 -#define AUX_EVCTL_EVSTAT1_AUXIO11_S 8 - -// Field: [7] AUXIO10 -// -// AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT1_AUXIO10 0x00000080 -#define AUX_EVCTL_EVSTAT1_AUXIO10_BITN 7 -#define AUX_EVCTL_EVSTAT1_AUXIO10_M 0x00000080 -#define AUX_EVCTL_EVSTAT1_AUXIO10_S 7 - -// Field: [6] AUXIO9 -// -// AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT1_AUXIO9 0x00000040 -#define AUX_EVCTL_EVSTAT1_AUXIO9_BITN 6 -#define AUX_EVCTL_EVSTAT1_AUXIO9_M 0x00000040 -#define AUX_EVCTL_EVSTAT1_AUXIO9_S 6 - -// Field: [5] AUXIO8 -// -// AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT1_AUXIO8 0x00000020 -#define AUX_EVCTL_EVSTAT1_AUXIO8_BITN 5 -#define AUX_EVCTL_EVSTAT1_AUXIO8_M 0x00000020 -#define AUX_EVCTL_EVSTAT1_AUXIO8_S 5 - -// Field: [4] AUXIO7 -// -// AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT1_AUXIO7 0x00000010 -#define AUX_EVCTL_EVSTAT1_AUXIO7_BITN 4 -#define AUX_EVCTL_EVSTAT1_AUXIO7_M 0x00000010 -#define AUX_EVCTL_EVSTAT1_AUXIO7_S 4 - -// Field: [3] AUXIO6 -// -// AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT1_AUXIO6 0x00000008 -#define AUX_EVCTL_EVSTAT1_AUXIO6_BITN 3 -#define AUX_EVCTL_EVSTAT1_AUXIO6_M 0x00000008 -#define AUX_EVCTL_EVSTAT1_AUXIO6_S 3 - -// Field: [2] AUXIO5 -// -// AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT1_AUXIO5 0x00000004 -#define AUX_EVCTL_EVSTAT1_AUXIO5_BITN 2 -#define AUX_EVCTL_EVSTAT1_AUXIO5_M 0x00000004 -#define AUX_EVCTL_EVSTAT1_AUXIO5_S 2 - -// Field: [1] AUXIO4 -// -// AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT1_AUXIO4 0x00000002 -#define AUX_EVCTL_EVSTAT1_AUXIO4_BITN 1 -#define AUX_EVCTL_EVSTAT1_AUXIO4_M 0x00000002 -#define AUX_EVCTL_EVSTAT1_AUXIO4_S 1 - -// Field: [0] AUXIO3 -// -// AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT1_AUXIO3 0x00000001 -#define AUX_EVCTL_EVSTAT1_AUXIO3_BITN 0 -#define AUX_EVCTL_EVSTAT1_AUXIO3_M 0x00000001 -#define AUX_EVCTL_EVSTAT1_AUXIO3_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOMCUPOL -// -//***************************************************************************** -// Field: [10] ADC_IRQ -// -// Select the event source level that sets EVTOMCUFLAGS.ADC_IRQ. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_S 10 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_LOW 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_HIGH 0x00000000 - -// Field: [9] OBSMUX0 -// -// Select the event source level that sets EVTOMCUFLAGS.OBSMUX0. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_S 9 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_LOW 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_HIGH 0x00000000 - -// Field: [8] ADC_FIFO_ALMOST_FULL -// -// Select the event source level that sets EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_S 8 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 - -// Field: [7] ADC_DONE -// -// Select the event source level that sets EVTOMCUFLAGS.ADC_DONE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_S 7 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_LOW 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_HIGH 0x00000000 - -// Field: [6] SMPH_AUTOTAKE_DONE -// -// Select the event source level that sets EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_S 6 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_LOW 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 - -// Field: [5] TIMER1_EV -// -// Select the event source level that sets EVTOMCUFLAGS.TIMER1_EV. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_S 5 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_LOW 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_HIGH 0x00000000 - -// Field: [4] TIMER0_EV -// -// Select the event source level that sets EVTOMCUFLAGS.TIMER0_EV. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_S 4 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_LOW 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_HIGH 0x00000000 - -// Field: [3] TDC_DONE -// -// Select the event source level that sets EVTOMCUFLAGS.TDC_DONE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_S 3 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_LOW 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_HIGH 0x00000000 - -// Field: [2] AUX_COMPB -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_COMPB. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_LOW 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_HIGH 0x00000000 - -// Field: [1] AUX_COMPA -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_COMPA. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_LOW 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_HIGH 0x00000000 - -// Field: [0] AON_WU_EV -// -// Select the event source level that sets EVTOMCUFLAGS.AON_WU_EV. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_S 0 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_LOW 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_HIGH 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOMCUFLAGS -// -//***************************************************************************** -// Field: [10] ADC_IRQ -// -// This event flag is set when level selected by EVTOMCUPOL.ADC_IRQ occurs on -// EVSTAT0.ADC_IRQ. -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_S 10 - -// Field: [9] OBSMUX0 -// -// This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs -// on EVSTAT0.MCU_OBSMUX0. -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_S 9 - -// Field: [8] ADC_FIFO_ALMOST_FULL -// -// This event flag is set when level selected by -// EVTOMCUPOL.ADC_FIFO_ALMOST_FULL occurs on EVSTAT0.ADC_FIFO_ALMOST_FULL. -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_S 8 - -// Field: [7] ADC_DONE -// -// This event flag is set when level selected by EVTOMCUPOL.ADC_DONE occurs on -// EVSTAT0.ADC_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_S 7 - -// Field: [6] SMPH_AUTOTAKE_DONE -// -// This event flag is set when level selected by EVTOMCUPOL.SMPH_AUTOTAKE_DONE -// occurs on EVSTAT0.SMPH_AUTOTAKE_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_S 6 - -// Field: [5] TIMER1_EV -// -// This event flag is set when level selected by EVTOMCUPOL.TIMER1_EV occurs on -// EVSTAT0.TIMER1_EV. -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_S 5 - -// Field: [4] TIMER0_EV -// -// This event flag is set when level selected by EVTOMCUPOL.TIMER0_EV occurs on -// EVSTAT0.TIMER0_EV. -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_S 4 - -// Field: [3] TDC_DONE -// -// This event flag is set when level selected by EVTOMCUPOL.TDC_DONE occurs on -// EVSTAT0.TDC_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_S 3 - -// Field: [2] AUX_COMPB -// -// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on -// EVSTAT0.AUX_COMPB. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 - -// Field: [1] AUX_COMPA -// -// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on -// EVSTAT0.AUX_COMPA. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 - -// Field: [0] AON_WU_EV -// -// This event flag is set when level selected by EVTOMCUPOL.AON_WU_EV occurs on -// the reduction-OR of the AUX_EVCTL:EVSTAT0.RTC_CH2_EV, -// AUX_EVCTL:EVSTAT0.AON_SW, and AUX_EVCTL:EVSTAT0.AON_PROG_WU events. -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_COMBEVTOMCUMASK -// -//***************************************************************************** -// Field: [10] ADC_IRQ -// -// EVTOMCUFLAGS.ADC_IRQ contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ 0x00000400 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_BITN 10 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_S 10 - -// Field: [9] OBSMUX0 -// -// EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0 0x00000200 -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_BITN 9 -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_S 9 - -// Field: [8] ADC_FIFO_ALMOST_FULL -// -// EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_S 8 - -// Field: [7] ADC_DONE -// -// EVTOMCUFLAGS.ADC_DONE contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE 0x00000080 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_BITN 7 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_S 7 - -// Field: [6] SMPH_AUTOTAKE_DONE -// -// EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_S 6 - -// Field: [5] TIMER1_EV -// -// EVTOMCUFLAGS.TIMER1_EV contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV 0x00000020 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_BITN 5 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_S 5 - -// Field: [4] TIMER0_EV -// -// EVTOMCUFLAGS.TIMER0_EV contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV 0x00000010 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_BITN 4 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_S 4 - -// Field: [3] TDC_DONE -// -// EVTOMCUFLAGS.TDC_DONE contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE 0x00000008 -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_BITN 3 -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_S 3 - -// Field: [2] AUX_COMPB -// -// EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. -// -// 0: Exclude -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 - -// Field: [1] AUX_COMPA -// -// EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 - -// Field: [0] AON_WU_EV -// -// EVTOMCUFLAGS.AON_WU_EV contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV 0x00000001 -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_BITN 0 -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_VECFLAGS -// -//***************************************************************************** -// Field: [3] VEC3 -// -// Vector flag 3. -// -// The vector flag is set if the edge selected VECCFG1.VEC3_POL occurs on the -// event selected in VECCFG1.VEC3_EV. -// -// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to -// VECFLAGSCLR.VEC3. -#define AUX_EVCTL_VECFLAGS_VEC3 0x00000008 -#define AUX_EVCTL_VECFLAGS_VEC3_BITN 3 -#define AUX_EVCTL_VECFLAGS_VEC3_M 0x00000008 -#define AUX_EVCTL_VECFLAGS_VEC3_S 3 - -// Field: [2] VEC2 -// -// Vector flag 2. -// -// The vector flag is set if the edge selected VECCFG1.VEC2_POL occurs on the -// event selected in VECCFG1.VEC2_EV. -// -// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to -// VECFLAGSCLR.VEC2. -#define AUX_EVCTL_VECFLAGS_VEC2 0x00000004 -#define AUX_EVCTL_VECFLAGS_VEC2_BITN 2 -#define AUX_EVCTL_VECFLAGS_VEC2_M 0x00000004 -#define AUX_EVCTL_VECFLAGS_VEC2_S 2 - -// Field: [1] VEC1 -// -// Vector flag 1. -// -// The vector flag is set if the edge selected VECCFG0.VEC1_POL occurs on the -// event selected in VECCFG0.VEC1_EV. -// -// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to -// VECFLAGSCLR.VEC1. -#define AUX_EVCTL_VECFLAGS_VEC1 0x00000002 -#define AUX_EVCTL_VECFLAGS_VEC1_BITN 1 -#define AUX_EVCTL_VECFLAGS_VEC1_M 0x00000002 -#define AUX_EVCTL_VECFLAGS_VEC1_S 1 - -// Field: [0] VEC0 -// -// Vector flag 0. -// -// The vector flag is set if the edge selected VECCFG0.VEC0_POL occurs on the -// event selected in VECCFG0.VEC0_EV. -// -// The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to -// VECFLAGSCLR.VEC0. -#define AUX_EVCTL_VECFLAGS_VEC0 0x00000001 -#define AUX_EVCTL_VECFLAGS_VEC0_BITN 0 -#define AUX_EVCTL_VECFLAGS_VEC0_M 0x00000001 -#define AUX_EVCTL_VECFLAGS_VEC0_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOMCUFLAGSCLR -// -//***************************************************************************** -// Field: [10] ADC_IRQ -// -// Write 1 to clear EVTOMCUFLAGS.ADC_IRQ. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_S 10 - -// Field: [9] OBSMUX0 -// -// Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_S 9 - -// Field: [8] ADC_FIFO_ALMOST_FULL -// -// Write 1 to clear EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_S 8 - -// Field: [7] ADC_DONE -// -// Write 1 to clear EVTOMCUFLAGS.ADC_DONE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_S 7 - -// Field: [6] SMPH_AUTOTAKE_DONE -// -// Write 1 to clear EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_S 6 - -// Field: [5] TIMER1_EV -// -// Write 1 to clear EVTOMCUFLAGS.TIMER1_EV. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_S 5 - -// Field: [4] TIMER0_EV -// -// Write 1 to clear EVTOMCUFLAGS.TIMER0_EV. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_S 4 - -// Field: [3] TDC_DONE -// -// Write 1 to clear EVTOMCUFLAGS.TDC_DONE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_S 3 - -// Field: [2] AUX_COMPB -// -// Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 - -// Field: [1] AUX_COMPA -// -// Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 - -// Field: [0] AON_WU_EV -// -// Write 1 to clear EVTOMCUFLAGS.AON_WU_EV. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOAONFLAGSCLR -// -//***************************************************************************** -// Field: [8] TIMER1_EV -// -// Write 1 to clear EVTOAONFLAGS.TIMER1_EV. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_S 8 - -// Field: [7] TIMER0_EV -// -// Write 1 to clear EVTOAONFLAGS.TIMER0_EV. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_S 7 - -// Field: [6] TDC_DONE -// -// Write 1 to clear EVTOAONFLAGS.TDC_DONE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_S 6 - -// Field: [5] ADC_DONE -// -// Write 1 to clear EVTOAONFLAGS.ADC_DONE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_S 5 - -// Field: [4] AUX_COMPB -// -// Write 1 to clear EVTOAONFLAGS.AUX_COMPB. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 - -// Field: [3] AUX_COMPA -// -// Write 1 to clear EVTOAONFLAGS.AUX_COMPA. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 - -// Field: [2] SWEV2 -// -// Write 1 to clear EVTOAONFLAGS.SWEV2. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 - -// Field: [1] SWEV1 -// -// Write 1 to clear EVTOAONFLAGS.SWEV1. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 - -// Field: [0] SWEV0 -// -// Write 1 to clear EVTOAONFLAGS.SWEV0. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_VECFLAGSCLR -// -//***************************************************************************** -// Field: [3] VEC3 -// -// Clear vector flag 3. -// -// 0: No effect. -// 1: Clear VECFLAGS.VEC3. -// -// Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC3 0x00000008 -#define AUX_EVCTL_VECFLAGSCLR_VEC3_BITN 3 -#define AUX_EVCTL_VECFLAGSCLR_VEC3_M 0x00000008 -#define AUX_EVCTL_VECFLAGSCLR_VEC3_S 3 - -// Field: [2] VEC2 -// -// Clear vector flag 2. -// -// 0: No effect. -// 1: Clear VECFLAGS.VEC2. -// -// Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC2 0x00000004 -#define AUX_EVCTL_VECFLAGSCLR_VEC2_BITN 2 -#define AUX_EVCTL_VECFLAGSCLR_VEC2_M 0x00000004 -#define AUX_EVCTL_VECFLAGSCLR_VEC2_S 2 - -// Field: [1] VEC1 -// -// Clear vector flag 1. -// -// 0: No effect. -// 1: Clear VECFLAGS.VEC1. -// -// Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC1 0x00000002 -#define AUX_EVCTL_VECFLAGSCLR_VEC1_BITN 1 -#define AUX_EVCTL_VECFLAGSCLR_VEC1_M 0x00000002 -#define AUX_EVCTL_VECFLAGSCLR_VEC1_S 1 - -// Field: [0] VEC0 -// -// Clear vector flag 0. -// -// 0: No effect. -// 1: Clear VECFLAGS.VEC0. -// -// Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC0 0x00000001 -#define AUX_EVCTL_VECFLAGSCLR_VEC0_BITN 0 -#define AUX_EVCTL_VECFLAGSCLR_VEC0_M 0x00000001 -#define AUX_EVCTL_VECFLAGSCLR_VEC0_S 0 - - -#endif // __AUX_EVCTL__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aux_sce.h b/third_party/ti/devices/cc26x0/inc/hw_aux_sce.h deleted file mode 100644 index 3528fd68e..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aux_sce.h +++ /dev/null @@ -1,381 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_sce_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_SCE_H__ -#define __HW_AUX_SCE_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_SCE component -// -//***************************************************************************** -// Internal -#define AUX_SCE_O_CTL 0x00000000 - -// Internal -#define AUX_SCE_O_FETCHSTAT 0x00000004 - -// Internal -#define AUX_SCE_O_CPUSTAT 0x00000008 - -// Internal -#define AUX_SCE_O_WUSTAT 0x0000000C - -// Internal -#define AUX_SCE_O_REG1_0 0x00000010 - -// Internal -#define AUX_SCE_O_REG3_2 0x00000014 - -// Internal -#define AUX_SCE_O_REG5_4 0x00000018 - -// Internal -#define AUX_SCE_O_REG7_6 0x0000001C - -// Internal -#define AUX_SCE_O_LOOPADDR 0x00000020 - -// Internal -#define AUX_SCE_O_LOOPCNT 0x00000024 - -//***************************************************************************** -// -// Register: AUX_SCE_O_CTL -// -//***************************************************************************** -// Field: [31:24] FORCE_EV_LOW -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 -#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 -#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 - -// Field: [23:16] FORCE_EV_HIGH -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 -#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 -#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 - -// Field: [11:8] RESET_VECTOR -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_RESET_VECTOR_W 4 -#define AUX_SCE_CTL_RESET_VECTOR_M 0x00000F00 -#define AUX_SCE_CTL_RESET_VECTOR_S 8 - -// Field: [6] DBG_FREEZE_EN -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 -#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 -#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 -#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 - -// Field: [5] FORCE_WU_LOW -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 -#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 -#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 -#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 - -// Field: [4] FORCE_WU_HIGH -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 -#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 -#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 -#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 - -// Field: [3] RESTART -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_RESTART 0x00000008 -#define AUX_SCE_CTL_RESTART_BITN 3 -#define AUX_SCE_CTL_RESTART_M 0x00000008 -#define AUX_SCE_CTL_RESTART_S 3 - -// Field: [2] SINGLE_STEP -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 -#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 -#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 -#define AUX_SCE_CTL_SINGLE_STEP_S 2 - -// Field: [1] SUSPEND -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_SUSPEND 0x00000002 -#define AUX_SCE_CTL_SUSPEND_BITN 1 -#define AUX_SCE_CTL_SUSPEND_M 0x00000002 -#define AUX_SCE_CTL_SUSPEND_S 1 - -// Field: [0] CLK_EN -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_CLK_EN 0x00000001 -#define AUX_SCE_CTL_CLK_EN_BITN 0 -#define AUX_SCE_CTL_CLK_EN_M 0x00000001 -#define AUX_SCE_CTL_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_FETCHSTAT -// -//***************************************************************************** -// Field: [31:16] OPCODE -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_FETCHSTAT_OPCODE_W 16 -#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 -#define AUX_SCE_FETCHSTAT_OPCODE_S 16 - -// Field: [15:0] PC -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_FETCHSTAT_PC_W 16 -#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF -#define AUX_SCE_FETCHSTAT_PC_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_CPUSTAT -// -//***************************************************************************** -// Field: [11] BUS_ERROR -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 -#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 -#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 -#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 - -// Field: [10] SLEEP -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 -#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 -#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 -#define AUX_SCE_CPUSTAT_SLEEP_S 10 - -// Field: [9] WEV -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_WEV 0x00000200 -#define AUX_SCE_CPUSTAT_WEV_BITN 9 -#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 -#define AUX_SCE_CPUSTAT_WEV_S 9 - -// Field: [8] SELF_STOP -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_SELF_STOP 0x00000100 -#define AUX_SCE_CPUSTAT_SELF_STOP_BITN 8 -#define AUX_SCE_CPUSTAT_SELF_STOP_M 0x00000100 -#define AUX_SCE_CPUSTAT_SELF_STOP_S 8 - -// Field: [3] V_FLAG -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 -#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 -#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 -#define AUX_SCE_CPUSTAT_V_FLAG_S 3 - -// Field: [2] C_FLAG -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 -#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 -#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 -#define AUX_SCE_CPUSTAT_C_FLAG_S 2 - -// Field: [1] N_FLAG -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 -#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 -#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 -#define AUX_SCE_CPUSTAT_N_FLAG_S 1 - -// Field: [0] Z_FLAG -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 -#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 -#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 -#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_WUSTAT -// -//***************************************************************************** -// Field: [17:16] EXC_VECTOR -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_EXC_VECTOR_W 2 -#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00030000 -#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 - -// Field: [8] WU_SIGNAL -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 -#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 -#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 -#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 - -// Field: [7:0] EV_SIGNALS -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 -#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF -#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_REG1_0 -// -//***************************************************************************** -// Field: [31:16] REG1 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG1_0_REG1_W 16 -#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 -#define AUX_SCE_REG1_0_REG1_S 16 - -// Field: [15:0] REG0 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG1_0_REG0_W 16 -#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF -#define AUX_SCE_REG1_0_REG0_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_REG3_2 -// -//***************************************************************************** -// Field: [31:16] REG3 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG3_2_REG3_W 16 -#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 -#define AUX_SCE_REG3_2_REG3_S 16 - -// Field: [15:0] REG2 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG3_2_REG2_W 16 -#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF -#define AUX_SCE_REG3_2_REG2_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_REG5_4 -// -//***************************************************************************** -// Field: [31:16] REG5 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG5_4_REG5_W 16 -#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 -#define AUX_SCE_REG5_4_REG5_S 16 - -// Field: [15:0] REG4 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG5_4_REG4_W 16 -#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF -#define AUX_SCE_REG5_4_REG4_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_REG7_6 -// -//***************************************************************************** -// Field: [31:16] REG7 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG7_6_REG7_W 16 -#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 -#define AUX_SCE_REG7_6_REG7_S 16 - -// Field: [15:0] REG6 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG7_6_REG6_W 16 -#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF -#define AUX_SCE_REG7_6_REG6_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_LOOPADDR -// -//***************************************************************************** -// Field: [31:16] STOP -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPADDR_STOP_W 16 -#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 -#define AUX_SCE_LOOPADDR_STOP_S 16 - -// Field: [15:0] START -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPADDR_START_W 16 -#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF -#define AUX_SCE_LOOPADDR_START_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_LOOPCNT -// -//***************************************************************************** -// Field: [7:0] ITER_LEFT -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 -#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF -#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 - - -#endif // __AUX_SCE__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aux_smph.h b/third_party/ti/devices/cc26x0/inc/hw_aux_smph.h deleted file mode 100644 index a8ea2d0e5..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aux_smph.h +++ /dev/null @@ -1,282 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_smph_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_SMPH_H__ -#define __HW_AUX_SMPH_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_SMPH component -// -//***************************************************************************** -// Semaphore 0 -#define AUX_SMPH_O_SMPH0 0x00000000 - -// Semaphore 1 -#define AUX_SMPH_O_SMPH1 0x00000004 - -// Semaphore 2 -#define AUX_SMPH_O_SMPH2 0x00000008 - -// Semaphore 3 -#define AUX_SMPH_O_SMPH3 0x0000000C - -// Semaphore 4 -#define AUX_SMPH_O_SMPH4 0x00000010 - -// Semaphore 5 -#define AUX_SMPH_O_SMPH5 0x00000014 - -// Semaphore 6 -#define AUX_SMPH_O_SMPH6 0x00000018 - -// Semaphore 7 -#define AUX_SMPH_O_SMPH7 0x0000001C - -// Auto Take -#define AUX_SMPH_O_AUTOTAKE 0x00000020 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH0 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH0_STAT 0x00000001 -#define AUX_SMPH_SMPH0_STAT_BITN 0 -#define AUX_SMPH_SMPH0_STAT_M 0x00000001 -#define AUX_SMPH_SMPH0_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH1 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH1_STAT 0x00000001 -#define AUX_SMPH_SMPH1_STAT_BITN 0 -#define AUX_SMPH_SMPH1_STAT_M 0x00000001 -#define AUX_SMPH_SMPH1_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH2 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH2_STAT 0x00000001 -#define AUX_SMPH_SMPH2_STAT_BITN 0 -#define AUX_SMPH_SMPH2_STAT_M 0x00000001 -#define AUX_SMPH_SMPH2_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH3 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH3_STAT 0x00000001 -#define AUX_SMPH_SMPH3_STAT_BITN 0 -#define AUX_SMPH_SMPH3_STAT_M 0x00000001 -#define AUX_SMPH_SMPH3_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH4 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH4_STAT 0x00000001 -#define AUX_SMPH_SMPH4_STAT_BITN 0 -#define AUX_SMPH_SMPH4_STAT_M 0x00000001 -#define AUX_SMPH_SMPH4_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH5 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH5_STAT 0x00000001 -#define AUX_SMPH_SMPH5_STAT_BITN 0 -#define AUX_SMPH_SMPH5_STAT_M 0x00000001 -#define AUX_SMPH_SMPH5_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH6 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH6_STAT 0x00000001 -#define AUX_SMPH_SMPH6_STAT_BITN 0 -#define AUX_SMPH_SMPH6_STAT_M 0x00000001 -#define AUX_SMPH_SMPH6_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH7 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH7_STAT 0x00000001 -#define AUX_SMPH_SMPH7_STAT_BITN 0 -#define AUX_SMPH_SMPH7_STAT_M 0x00000001 -#define AUX_SMPH_SMPH7_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_AUTOTAKE -// -//***************************************************************************** -// Field: [2:0] SMPH_ID -// -// Write the semaphore ID,0x0-0x7, to SMPH_ID to request this semaphore until -// it is granted. -// -// When semaphore SMPH_ID is granted, event -// AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE becomes 1. -// -// The event becomes 0 when software releases the semaphore or writes a new -// value to SMPH_ID. -// -// To avoid corrupted semaphores: -// - Usage of this functionality must be restricted to one CPU core. -// - Software must wait until AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE is 1 -// before it writes a new value to SMPH_ID. -#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 -#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 -#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 - - -#endif // __AUX_SMPH__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aux_tdc.h b/third_party/ti/devices/cc26x0/inc/hw_aux_tdc.h deleted file mode 100644 index 69d68cb09..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aux_tdc.h +++ /dev/null @@ -1,694 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_tdc_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_TDC_H__ -#define __HW_AUX_TDC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_TDC component -// -//***************************************************************************** -// Control -#define AUX_TDC_O_CTL 0x00000000 - -// Status -#define AUX_TDC_O_STAT 0x00000004 - -// Result -#define AUX_TDC_O_RESULT 0x00000008 - -// Saturation Configuration -#define AUX_TDC_O_SATCFG 0x0000000C - -// Trigger Source -#define AUX_TDC_O_TRIGSRC 0x00000010 - -// Trigger Counter -#define AUX_TDC_O_TRIGCNT 0x00000014 - -// Trigger Counter Load -#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 - -// Trigger Counter Configuration -#define AUX_TDC_O_TRIGCNTCFG 0x0000001C - -// Prescaler Control -#define AUX_TDC_O_PRECTL 0x00000020 - -// Prescaler Counter -#define AUX_TDC_O_PRECNT 0x00000024 - -//***************************************************************************** -// -// Register: AUX_TDC_O_CTL -// -//***************************************************************************** -// Field: [1:0] CMD -// -// TDC commands. -// ENUMs: -// ABORT Force TDC state machine back to IDLE state. -// -// Never write this command -// while AUX_TDC:STAT.STATE equals CLR_CNT or -// WAIT_CLR_CNT_DONE. -// RUN Asynchronous counter start. -// -// The counter starts to -// count when the start event is high. To achieve -// precise edge-to-edge measurements you must -// ensure that the start event is low for at least -// 420 ns after you write this command. -// RUN_SYNC_START Synchronous counter start. -// -// The counter looks for the -// opposite edge of the selected start event -// before it starts to count when the selected -// edge occurs. This guarantees an edge-triggered -// start and is recommended for frequency -// measurements. -// CLR_RESULT Clear STAT.SAT, STAT.DONE, and RESULT.VALUE. -// -// This is not needed as -// prerequisite for a measurement. Reliable clear -// is only guaranteed from IDLE state. -#define AUX_TDC_CTL_CMD_W 2 -#define AUX_TDC_CTL_CMD_M 0x00000003 -#define AUX_TDC_CTL_CMD_S 0 -#define AUX_TDC_CTL_CMD_ABORT 0x00000003 -#define AUX_TDC_CTL_CMD_RUN 0x00000002 -#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 -#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TDC_O_STAT -// -//***************************************************************************** -// Field: [7] SAT -// -// TDC measurement saturation flag. -// -// 0: Conversion has not saturated. -// 1: Conversion stopped due to saturation. -// -// This field is cleared when a new measurement is started or when CLR_RESULT -// is written to CTL.CMD. -#define AUX_TDC_STAT_SAT 0x00000080 -#define AUX_TDC_STAT_SAT_BITN 7 -#define AUX_TDC_STAT_SAT_M 0x00000080 -#define AUX_TDC_STAT_SAT_S 7 - -// Field: [6] DONE -// -// TDC measurement complete flag. -// -// 0: TDC measurement has not yet completed. -// 1: TDC measurement has completed. -// -// This field clears when a new TDC measurement starts or when you write -// CLR_RESULT to CTL.CMD. -#define AUX_TDC_STAT_DONE 0x00000040 -#define AUX_TDC_STAT_DONE_BITN 6 -#define AUX_TDC_STAT_DONE_M 0x00000040 -#define AUX_TDC_STAT_DONE_S 6 - -// Field: [5:0] STATE -// -// TDC state machine status. -// ENUMs: -// FORCE_STOP Current state is TDC_FORCESTOP. -// You wrote ABORT to -// CTL.CMD to abort the TDC measurement. -// START_FALL Current state is TDC_WAIT_STARTFALL. -// The fast-counter circuit -// waits for a falling edge on the start event. -// WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE. -// The state machine waits -// for fast-counter circuit to finish reset. -// POR Current state is TDC_STATE_POR. -// This is the reset state. -// GET_RESULT Current state is TDC_STATE_GETRESULTS. -// The state machine copies -// the counter value from the fast-counter -// circuit. -// WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN. -// The fast-counter circuit -// looks for the stop condition. It will ignore a -// number of stop events configured in -// TRIGCNTLOAD.CNT. -// WAIT_STOP Current state is TDC_STATE_WAIT_STOP. -// The state machine waits -// for the fast-counter circuit to stop. -// CLR_CNT Current state is TDC_STATE_CLRCNT. The -// fast-counter circuit is reset. -// IDLE Current state is TDC_STATE_IDLE. -// This is the default state -// after reset and abortion. State will change -// when you write CTL.CMD to either RUN_SYNC_START -// or RUN. -// WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN. -// The fast-counter circuit -// looks for the start condition. The state -// machine waits for the fast-counter to -// increment. -// WAIT_START Current state is TDC_STATE_WAIT_START. -// The fast-counter circuit -// looks for the start condition. The state -// machine waits for the fast-counter to -// increment. -#define AUX_TDC_STAT_STATE_W 6 -#define AUX_TDC_STAT_STATE_M 0x0000003F -#define AUX_TDC_STAT_STATE_S 0 -#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E -#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E -#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 -#define AUX_TDC_STAT_STATE_POR 0x0000000F -#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E -#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C -#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 -#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 -#define AUX_TDC_STAT_STATE_IDLE 0x00000006 -#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 -#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TDC_O_RESULT -// -//***************************************************************************** -// Field: [24:0] VALUE -// -// TDC conversion result. -// -// The result of the TDC conversion is given in number of clock edges of the -// clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and -// falling edges are counted. -// -// If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it -// takes a non-zero time to stop the measurement. Hence, the maximum value of -// this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT -// to R24. -#define AUX_TDC_RESULT_VALUE_W 25 -#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF -#define AUX_TDC_RESULT_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TDC_O_SATCFG -// -//***************************************************************************** -// Field: [3:0] LIMIT -// -// Saturation limit. -// -// The flag STAT.SAT is set when the TDC counter saturates. -// -// Values not enumerated are not supported -// ENUMs: -// R24 Result bit 24: TDC conversion saturates and stops -// when RESULT.VALUE[24] is set. -// R23 Result bit 23: TDC conversion saturates and stops -// when RESULT.VALUE[23] is set. -// R22 Result bit 22: TDC conversion saturates and stops -// when RESULT.VALUE[22] is set. -// R21 Result bit 21: TDC conversion saturates and stops -// when RESULT.VALUE[21] is set. -// R20 Result bit 20: TDC conversion saturates and stops -// when RESULT.VALUE[20] is set. -// R19 Result bit 19: TDC conversion saturates and stops -// when RESULT.VALUE[19] is set. -// R18 Result bit 18: TDC conversion saturates and stops -// when RESULT.VALUE[18] is set. -// R17 Result bit 17: TDC conversion saturates and stops -// when RESULT.VALUE[17] is set. -// R16 Result bit 16: TDC conversion saturates and stops -// when RESULT.VALUE[16] is set. -// R15 Result bit 15: TDC conversion saturates and stops -// when RESULT.VALUE[15] is set. -// R14 Result bit 14: TDC conversion saturates and stops -// when RESULT.VALUE[14] is set. -// R13 Result bit 13: TDC conversion saturates and stops -// when RESULT.VALUE[13] is set. -// R12 Result bit 12: TDC conversion saturates and stops -// when RESULT.VALUE[12] is set. -#define AUX_TDC_SATCFG_LIMIT_W 4 -#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F -#define AUX_TDC_SATCFG_LIMIT_S 0 -#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F -#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E -#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D -#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C -#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B -#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A -#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 -#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 -#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 -#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 -#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 -#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 -#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 - -//***************************************************************************** -// -// Register: AUX_TDC_O_TRIGSRC -// -//***************************************************************************** -// Field: [13] STOP_POL -// -// Polarity of stop source. -// -// Change only while STAT.STATE is IDLE. -// ENUMs: -// LOW TDC conversion stops when low level is detected. -// HIGH TDC conversion stops when high level is detected. -#define AUX_TDC_TRIGSRC_STOP_POL 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_POL_BITN 13 -#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_POL_S 13 -#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 - -// Field: [12:8] STOP_SRC -// -// Select stop source from the asynchronous AUX event bus. -// -// Change only while STAT.STATE is IDLE. -// ENUMs: -// TDC_PRE Select TDC Prescaler event which is generated by -// configuration of PRECTL. -// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF -// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU -// AON_SW AUX_EVCTL:EVSTAT0.AON_SW -// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 -// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 -// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL -// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE -// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV -// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV -// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N -// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA -// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TDC_TRIGSRC_STOP_SRC_W 5 -#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00001F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 -#define AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE 0x00001F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00001E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00001D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00001C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00001B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00001A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00001900 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00001800 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00001700 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00001600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00001500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00001400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00001300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00001200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00001100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00001000 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU 0x00000C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_SW 0x00000B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1 0x00000A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0 0x00000900 -#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE 0x00000700 -#define AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV 0x00000500 -#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV 0x00000400 -#define AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET 0x00000300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00000200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00000100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00000000 - -// Field: [5] START_POL -// -// Polarity of start source. -// -// Change only while STAT.STATE is IDLE. -// ENUMs: -// LOW TDC conversion starts when low level is detected. -// HIGH TDC conversion starts when high level is detected. -#define AUX_TDC_TRIGSRC_START_POL 0x00000020 -#define AUX_TDC_TRIGSRC_START_POL_BITN 5 -#define AUX_TDC_TRIGSRC_START_POL_M 0x00000020 -#define AUX_TDC_TRIGSRC_START_POL_S 5 -#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000020 -#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 - -// Field: [4:0] START_SRC -// -// Select start source from the asynchronous AUX event bus. -// -// Change only while STAT.STATE is IDLE. -// ENUMs: -// TDC_PRE Select TDC Prescaler event which is generated by -// configuration of PRECTL. -// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF -// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU -// AON_SW AUX_EVCTL:EVSTAT0.AON_SW -// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 -// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 -// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL -// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE -// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV -// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV -// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N -// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA -// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TDC_TRIGSRC_START_SRC_W 5 -#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000001F -#define AUX_TDC_TRIGSRC_START_SRC_S 0 -#define AUX_TDC_TRIGSRC_START_SRC_TDC_PRE 0x0000001F -#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000001E -#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000001D -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000001C -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000001B -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000001A -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x00000019 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x00000018 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x00000017 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000016 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000015 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000014 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000013 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000012 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000011 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000010 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x0000000F -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x0000000E -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x0000000D -#define AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU 0x0000000C -#define AUX_TDC_TRIGSRC_START_SRC_AON_SW 0x0000000B -#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX1 0x0000000A -#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX0 0x00000009 -#define AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_TDC_TRIGSRC_START_SRC_ADC_DONE 0x00000007 -#define AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV 0x00000005 -#define AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV 0x00000004 -#define AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET 0x00000003 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x00000002 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x00000001 -#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TDC_O_TRIGCNT -// -//***************************************************************************** -// Field: [15:0] CNT -// -// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. -// -// Read CNT to get the remaining number of stop events to ignore during a TDC -// measurement. -// -// Write CNT to update the remaining number of stop events to ignore during a -// TDC measurement. The TDC measurement ignores updates of CNT if there are no -// more stop events left to ignore. -// -// When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the -// start of the measurement. -#define AUX_TDC_TRIGCNT_CNT_W 16 -#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF -#define AUX_TDC_TRIGCNT_CNT_S 0 - -//***************************************************************************** -// -// Register: AUX_TDC_O_TRIGCNTLOAD -// -//***************************************************************************** -// Field: [15:0] CNT -// -// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. -// -// To measure frequency of an event source: -// - Set start event equal to stop event. -// - Set CNT to number of periods to measure. Both 0 and 1 values measures a -// single event source period. -// -// To measure pulse width of an event source: -// - Set start event source equal to stop event source. -// - Select different polarity for start and stop event. -// - Set CNT to 0. -// -// To measure time from the start event to the Nth stop event when N > 1: -// - Select different start and stop event source. -// - Set CNT to (N-1). -// -// See the Technical Reference Manual for event timing requirements. -// -// When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start -// of the measurement. -#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 -#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF -#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 - -//***************************************************************************** -// -// Register: AUX_TDC_O_TRIGCNTCFG -// -//***************************************************************************** -// Field: [0] EN -// -// Enable stop-counter. -// -// 0: Disable stop-counter. -// 1: Enable stop-counter. -// -// Change only while STAT.STATE is IDLE. -#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 -#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 -#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 -#define AUX_TDC_TRIGCNTCFG_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_TDC_O_PRECTL -// -//***************************************************************************** -// Field: [7] RESET_N -// -// Prescaler reset. -// -// 0: Reset prescaler. -// 1: Release reset of prescaler. -// -// AUX_TDC_PRE event becomes 0 when you reset the prescaler. -#define AUX_TDC_PRECTL_RESET_N 0x00000080 -#define AUX_TDC_PRECTL_RESET_N_BITN 7 -#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 -#define AUX_TDC_PRECTL_RESET_N_S 7 - -// Field: [6] RATIO -// -// Prescaler ratio. -// -// This controls how often the AUX_TDC_PRE event is generated by the prescaler. -// ENUMs: -// DIV64 Prescaler divides input by 64. -// -// AUX_TDC_PRE event has a -// rising edge for every 64 rising edges of the -// input. AUX_TDC_PRE event toggles on every 32nd -// rising edge of the input. -// DIV16 Prescaler divides input by 16. -// -// AUX_TDC_PRE event has a -// rising edge for every 16 rising edges of the -// input. AUX_TDC_PRE event toggles on every 8th -// rising edge of the input. -#define AUX_TDC_PRECTL_RATIO 0x00000040 -#define AUX_TDC_PRECTL_RATIO_BITN 6 -#define AUX_TDC_PRECTL_RATIO_M 0x00000040 -#define AUX_TDC_PRECTL_RATIO_S 6 -#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 -#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 - -// Field: [4:0] SRC -// -// Prescaler event source. -// -// Select an event from the asynchronous AUX event bus to connect to the -// prescaler input. -// -// Configure only while RESET_N is 0. -// ENUMs: -// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ -// MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF -// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU -// AON_SW AUX_EVCTL:EVSTAT0.AON_SW -// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 -// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 -// ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL -// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE -// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV -// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV -// ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N -// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA -// AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TDC_PRECTL_SRC_W 5 -#define AUX_TDC_PRECTL_SRC_M 0x0000001F -#define AUX_TDC_PRECTL_SRC_S 0 -#define AUX_TDC_PRECTL_SRC_ADC_IRQ 0x0000001F -#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000001E -#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000001D -#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000001C -#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000001B -#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000001A -#define AUX_TDC_PRECTL_SRC_AUXIO12 0x00000019 -#define AUX_TDC_PRECTL_SRC_AUXIO11 0x00000018 -#define AUX_TDC_PRECTL_SRC_AUXIO10 0x00000017 -#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000016 -#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000015 -#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000014 -#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000013 -#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000012 -#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000011 -#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000010 -#define AUX_TDC_PRECTL_SRC_AUXIO2 0x0000000F -#define AUX_TDC_PRECTL_SRC_AUXIO1 0x0000000E -#define AUX_TDC_PRECTL_SRC_AUXIO0 0x0000000D -#define AUX_TDC_PRECTL_SRC_AON_PROG_WU 0x0000000C -#define AUX_TDC_PRECTL_SRC_AON_SW 0x0000000B -#define AUX_TDC_PRECTL_SRC_OBSMUX1 0x0000000A -#define AUX_TDC_PRECTL_SRC_OBSMUX0 0x00000009 -#define AUX_TDC_PRECTL_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_TDC_PRECTL_SRC_ADC_DONE 0x00000007 -#define AUX_TDC_PRECTL_SRC_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_TDC_PRECTL_SRC_TIMER1_EV 0x00000005 -#define AUX_TDC_PRECTL_SRC_TIMER0_EV 0x00000004 -#define AUX_TDC_PRECTL_SRC_ISRC_RESET 0x00000003 -#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x00000002 -#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x00000001 -#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TDC_O_PRECNT -// -//***************************************************************************** -// Field: [15:0] CNT -// -// Prescaler counter value. -// -// Write a value to CNT to capture the value of the 16-bit prescaler counter -// into CNT. Read CNT to get the captured value. -// -// The read value gets 1 LSB uncertainty if the event source level rises when -// you release the reset. -// -// You must capture the prescaler counter value when the event source level is -// stable, either high or low: -// - Disable AUX I/O input buffer to clamp AUXIO event low. -// - Disable COMPA to clamp AUX_COMPA event low. -// The read value can in general get 1 LSB uncertainty when you gate the event -// source asynchronously. -// -// Please note the following: -// - The prescaler counter is reset to 2 by PRECTL.RESET_N. -// - The captured value is 2 when the number of rising edges on prescaler input -// is less than 3. Otherwise, captured value equals number of event pulses - 1. -#define AUX_TDC_PRECNT_CNT_W 16 -#define AUX_TDC_PRECNT_CNT_M 0x0000FFFF -#define AUX_TDC_PRECNT_CNT_S 0 - - -#endif // __AUX_TDC__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aux_timer.h b/third_party/ti/devices/cc26x0/inc/hw_aux_timer.h deleted file mode 100644 index ad58a779e..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aux_timer.h +++ /dev/null @@ -1,447 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_timer_h -* Revised: 2017-05-22 18:50:33 +0200 (Mon, 22 May 2017) -* Revision: 49040 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_TIMER_H__ -#define __HW_AUX_TIMER_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_TIMER component -// -//***************************************************************************** -// Timer 0 Configuration -#define AUX_TIMER_O_T0CFG 0x00000000 - -// Timer 1 Configuration -#define AUX_TIMER_O_T1CFG 0x00000004 - -// Timer 0 Control -#define AUX_TIMER_O_T0CTL 0x00000008 - -// Timer 0 Target -#define AUX_TIMER_O_T0TARGET 0x0000000C - -// Timer 1 Target -#define AUX_TIMER_O_T1TARGET 0x00000010 - -// Timer 1 Control -#define AUX_TIMER_O_T1CTL 0x00000014 - -//***************************************************************************** -// -// Register: AUX_TIMER_O_T0CFG -// -//***************************************************************************** -// Field: [13] TICK_SRC_POL -// -// Tick source polarity for Timer 0. -// ENUMs: -// FALL Count on falling edges of TICK_SRC. -// RISE Count on rising edges of TICK_SRC. -#define AUX_TIMER_T0CFG_TICK_SRC_POL 0x00002000 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_BITN 13 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_M 0x00002000 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_S 13 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_FALL 0x00002000 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_RISE 0x00000000 - -// Field: [12:8] TICK_SRC -// -// Select Timer 0 tick source from the synchronous event bus. -// ENUMs: -// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ -// MCU_EVENT AUX_EVCTL:EVSTAT1.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF -// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU -// AON_SW AUX_EVCTL:EVSTAT0.AON_SW -// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 -// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 -// RTC_4KHZ AON_RTC:SUBSEC.VALUE bit 19. -// AON_RTC:CTL.RTC_4KHZ_EN enables this event. -// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE -// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV -// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE -// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA -// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TIMER_T0CFG_TICK_SRC_W 5 -#define AUX_TIMER_T0CFG_TICK_SRC_M 0x00001F00 -#define AUX_TIMER_T0CFG_TICK_SRC_S 8 -#define AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ 0x00001F00 -#define AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT 0x00001E00 -#define AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF 0x00001D00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO15 0x00001C00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO14 0x00001B00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO13 0x00001A00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO12 0x00001900 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO11 0x00001800 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO10 0x00001700 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO9 0x00001600 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO8 0x00001500 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO7 0x00001400 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO6 0x00001300 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO5 0x00001200 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO4 0x00001100 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO3 0x00001000 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO2 0x00000F00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO1 0x00000E00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO0 0x00000D00 -#define AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU 0x00000C00 -#define AUX_TIMER_T0CFG_TICK_SRC_AON_SW 0x00000B00 -#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1 0x00000A00 -#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0 0x00000900 -#define AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ 0x00000800 -#define AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE 0x00000700 -#define AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV 0x00000500 -#define AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE 0x00000300 -#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB 0x00000200 -#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA 0x00000100 -#define AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV 0x00000000 - -// Field: [7:4] PRE -// -// Prescaler division ratio is 2^PRE: -// -// 0x0: Divide by 1. -// 0x1: Divide by 2. -// 0x2: Divide by 4. -// ... -// 0xF: Divide by 32,768. -#define AUX_TIMER_T0CFG_PRE_W 4 -#define AUX_TIMER_T0CFG_PRE_M 0x000000F0 -#define AUX_TIMER_T0CFG_PRE_S 4 - -// Field: [1] MODE -// -// Timer 0 mode. -// -// Configure source for Timer 0 prescaler. -// ENUMs: -// TICK Use event set by TICK_SRC as source for prescaler. -// CLK Use AUX clock as source for prescaler. -#define AUX_TIMER_T0CFG_MODE 0x00000002 -#define AUX_TIMER_T0CFG_MODE_BITN 1 -#define AUX_TIMER_T0CFG_MODE_M 0x00000002 -#define AUX_TIMER_T0CFG_MODE_S 1 -#define AUX_TIMER_T0CFG_MODE_TICK 0x00000002 -#define AUX_TIMER_T0CFG_MODE_CLK 0x00000000 - -// Field: [0] RELOAD -// -// Timer 0 reload mode. -// ENUMs: -// CONT Continuous mode. -// -// Timer 0 restarts when the -// counter value becomes equal to or greater than -// ( T0TARGET.VALUE - 1). -// MAN Manual mode. -// -// Timer 0 stops and -// T0CTL.EN becomes 0 when the counter value -// becomes equal to or greater than -// T0TARGET.VALUE. -#define AUX_TIMER_T0CFG_RELOAD 0x00000001 -#define AUX_TIMER_T0CFG_RELOAD_BITN 0 -#define AUX_TIMER_T0CFG_RELOAD_M 0x00000001 -#define AUX_TIMER_T0CFG_RELOAD_S 0 -#define AUX_TIMER_T0CFG_RELOAD_CONT 0x00000001 -#define AUX_TIMER_T0CFG_RELOAD_MAN 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER_O_T1CFG -// -//***************************************************************************** -// Field: [13] TICK_SRC_POL -// -// Tick source polarity for Timer 1. -// ENUMs: -// FALL Count on falling edges of TICK_SRC. -// RISE Count on rising edges of TICK_SRC. -#define AUX_TIMER_T1CFG_TICK_SRC_POL 0x00002000 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_BITN 13 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_M 0x00002000 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_S 13 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_FALL 0x00002000 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_RISE 0x00000000 - -// Field: [12:8] TICK_SRC -// -// Select Timer 1 tick source from the synchronous event bus. -// ENUMs: -// ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ -// MCU_EVENT AUX_EVCTL:EVSTAT1.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF -// AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -// AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU -// AON_SW AUX_EVCTL:EVSTAT0.AON_SW -// OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1 -// OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0 -// RTC_4KHZ AON_RTC:SUBSEC.VALUE bit 19. -// AON_RTC:CTL.RTC_4KHZ_EN enables this event. -// ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE -// SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE -// TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV -// TDC_DONE AUX_EVCTL:EVSTAT0.TDC_DONE -// AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA -// RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TIMER_T1CFG_TICK_SRC_W 5 -#define AUX_TIMER_T1CFG_TICK_SRC_M 0x00001F00 -#define AUX_TIMER_T1CFG_TICK_SRC_S 8 -#define AUX_TIMER_T1CFG_TICK_SRC_ADC_IRQ 0x00001F00 -#define AUX_TIMER_T1CFG_TICK_SRC_MCU_EVENT 0x00001E00 -#define AUX_TIMER_T1CFG_TICK_SRC_ACLK_REF 0x00001D00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO15 0x00001C00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO14 0x00001B00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO13 0x00001A00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO12 0x00001900 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO11 0x00001800 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO10 0x00001700 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO9 0x00001600 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO8 0x00001500 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO7 0x00001400 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO6 0x00001300 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO5 0x00001200 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO4 0x00001100 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO3 0x00001000 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO2 0x00000F00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO1 0x00000E00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO0 0x00000D00 -#define AUX_TIMER_T1CFG_TICK_SRC_AON_PROG_WU 0x00000C00 -#define AUX_TIMER_T1CFG_TICK_SRC_AON_SW 0x00000B00 -#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX1 0x00000A00 -#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX0 0x00000900 -#define AUX_TIMER_T1CFG_TICK_SRC_RTC_4KHZ 0x00000800 -#define AUX_TIMER_T1CFG_TICK_SRC_ADC_DONE 0x00000700 -#define AUX_TIMER_T1CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV 0x00000400 -#define AUX_TIMER_T1CFG_TICK_SRC_TDC_DONE 0x00000300 -#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPB 0x00000200 -#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPA 0x00000100 -#define AUX_TIMER_T1CFG_TICK_SRC_RTC_CH2_EV 0x00000000 - -// Field: [7:4] PRE -// -// Prescaler division ratio is 2^PRE: -// -// 0x0: Divide by 1. -// 0x1: Divide by 2. -// 0x2: Divide by 4. -// ... -// 0xF: Divide by 32,768. -#define AUX_TIMER_T1CFG_PRE_W 4 -#define AUX_TIMER_T1CFG_PRE_M 0x000000F0 -#define AUX_TIMER_T1CFG_PRE_S 4 - -// Field: [1] MODE -// -// Timer 1 mode. -// -// Configure source for Timer 1 prescaler. -// ENUMs: -// TICK Use event set by TICK_SRC as source for prescaler. -// CLK Use AUX clock as source for prescaler. -#define AUX_TIMER_T1CFG_MODE 0x00000002 -#define AUX_TIMER_T1CFG_MODE_BITN 1 -#define AUX_TIMER_T1CFG_MODE_M 0x00000002 -#define AUX_TIMER_T1CFG_MODE_S 1 -#define AUX_TIMER_T1CFG_MODE_TICK 0x00000002 -#define AUX_TIMER_T1CFG_MODE_CLK 0x00000000 - -// Field: [0] RELOAD -// -// Timer 1 reload mode. -// ENUMs: -// CONT Continuous mode. -// -// Timer 1 restarts when the -// counter value becomes equal to or greater than -// ( T1TARGET.VALUE - 1). -// MAN Manual mode. -// -// Timer 1 stops and -// T1CTL.EN becomes 0 when the counter value -// becomes equal to or greater than -// T1TARGET.VALUE. -#define AUX_TIMER_T1CFG_RELOAD 0x00000001 -#define AUX_TIMER_T1CFG_RELOAD_BITN 0 -#define AUX_TIMER_T1CFG_RELOAD_M 0x00000001 -#define AUX_TIMER_T1CFG_RELOAD_S 0 -#define AUX_TIMER_T1CFG_RELOAD_CONT 0x00000001 -#define AUX_TIMER_T1CFG_RELOAD_MAN 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER_O_T0CTL -// -//***************************************************************************** -// Field: [0] EN -// -// Timer 0 enable. -// -// 0: Disable Timer 0. -// 1: Enable Timer 0. -// -// The counter restarts from 0 when you enable Timer 0. -#define AUX_TIMER_T0CTL_EN 0x00000001 -#define AUX_TIMER_T0CTL_EN_BITN 0 -#define AUX_TIMER_T0CTL_EN_M 0x00000001 -#define AUX_TIMER_T0CTL_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER_O_T0TARGET -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Timer 0 target value. -// -// Manual Reload Mode: -// - Timer 0 increments until the counter value becomes equal to or greater -// than VALUE. -// - AUX_TIMER0_EV pulses high for 1 AUX clock period when the counter value is -// equal to or greater than VALUE. -// -// Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 -// AUX clock period. -// -// Continuous Reload Mode: -// - Timer 0 increments until the counter value becomes equal to or greater -// than ( VALUE - 1), then restarts from 0. -// - AUX_TIMER0_EV pulses high for 1 AUX clock period when the counter value is -// 0, except for when you enable the timer. -// -// Note: When VALUE is less than 2, Timer 0 counter value remains 0. -// AUX_TIMER0_EV goes high and remains high 1 AUX clock period after you enable -// the timer. -// -// -// It is allowed to update the VALUE while the timer runs. -#define AUX_TIMER_T0TARGET_VALUE_W 16 -#define AUX_TIMER_T0TARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER_T0TARGET_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER_O_T1TARGET -// -//***************************************************************************** -// Field: [7:0] VALUE -// -// Timer 1 target value. -// -// Manual Reload Mode: -// - Timer 1 increments until the counter value becomes equal to or greater -// than VALUE. -// - AUX_TIMER1_EV pulses high for 1 AUX clock period when the counter value is -// equal to or greater than VALUE. -// -// Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 -// AUX clock period. -// -// Continuous Reload Mode: -// - Timer 1 increments until the counter value becomes equal to or greater -// than ( VALUE - 1), then restarts from 0. -// - AUX_TIMER1_EV pulses high for 1 AUX clock period when the counter value is -// 0, except for when you enable the timer. -// -// Note: When VALUE is less than 2, Timer 1 counter value remains 0. -// AUX_TIMER1_EV goes high and remains high 1 AUX clock period after you enable -// the timer. -// -// -// It is allowed to update the VALUE while the timer runs. -#define AUX_TIMER_T1TARGET_VALUE_W 8 -#define AUX_TIMER_T1TARGET_VALUE_M 0x000000FF -#define AUX_TIMER_T1TARGET_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER_O_T1CTL -// -//***************************************************************************** -// Field: [0] EN -// -// Timer 1 enable. -// -// 0: Disable Timer 1. -// 1: Enable Timer 1. -// -// The counter restarts from 0 when you enable Timer 1. -#define AUX_TIMER_T1CTL_EN 0x00000001 -#define AUX_TIMER_T1CTL_EN_BITN 0 -#define AUX_TIMER_T1CTL_EN_M 0x00000001 -#define AUX_TIMER_T1CTL_EN_S 0 - - -#endif // __AUX_TIMER__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_aux_wuc.h b/third_party/ti/devices/cc26x0/inc/hw_aux_wuc.h deleted file mode 100644 index d21d1ba67..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_aux_wuc.h +++ /dev/null @@ -1,705 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_wuc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_WUC_H__ -#define __HW_AUX_WUC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_WUC component -// -//***************************************************************************** -// Module Clock Enable -#define AUX_WUC_O_MODCLKEN0 0x00000000 - -// Power Off Request -#define AUX_WUC_O_PWROFFREQ 0x00000004 - -// Power Down Request -#define AUX_WUC_O_PWRDWNREQ 0x00000008 - -// Power Down Acknowledgment -#define AUX_WUC_O_PWRDWNACK 0x0000000C - -// Low Frequency Clock Request -#define AUX_WUC_O_CLKLFREQ 0x00000010 - -// Low Frequency Clock Acknowledgment -#define AUX_WUC_O_CLKLFACK 0x00000014 - -// Wake-up Event Flags -#define AUX_WUC_O_WUEVFLAGS 0x00000028 - -// Wake-up Event Clear -#define AUX_WUC_O_WUEVCLR 0x0000002C - -// ADC Clock Control -#define AUX_WUC_O_ADCCLKCTL 0x00000030 - -// TDC Clock Control -#define AUX_WUC_O_TDCCLKCTL 0x00000034 - -// Reference Clock Control -#define AUX_WUC_O_REFCLKCTL 0x00000038 - -// Real Time Counter Sub Second Increment 0 -#define AUX_WUC_O_RTCSUBSECINC0 0x0000003C - -// Real Time Counter Sub Second Increment 1 -#define AUX_WUC_O_RTCSUBSECINC1 0x00000040 - -// Real Time Counter Sub Second Increment Control -#define AUX_WUC_O_RTCSUBSECINCCTL 0x00000044 - -// MCU Bus Control -#define AUX_WUC_O_MCUBUSCTL 0x00000048 - -// MCU Bus Status -#define AUX_WUC_O_MCUBUSSTAT 0x0000004C - -// AON Domain Control Status -#define AUX_WUC_O_AONCTLSTAT 0x00000050 - -// AUX Input Output Latch -#define AUX_WUC_O_AUXIOLATCH 0x00000054 - -// Module Clock Enable 1 -#define AUX_WUC_O_MODCLKEN1 0x0000005C - -//***************************************************************************** -// -// Register: AUX_WUC_O_MODCLKEN0 -// -//***************************************************************************** -// Field: [7] AUX_ADI4 -// -// Enables (1) or disables (0) clock for AUX_ADI4. -// ENUMs: -// EN System CPU has requested clock for AUX_ADI4 -// DIS System CPU has not requested clock for AUX_ADI4 -#define AUX_WUC_MODCLKEN0_AUX_ADI4 0x00000080 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_BITN 7 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_M 0x00000080 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_S 7 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_EN 0x00000080 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_DIS 0x00000000 - -// Field: [6] AUX_DDI0_OSC -// -// Enables (1) or disables (0) clock for AUX_DDI0_OSC. -// ENUMs: -// EN System CPU has requested clock for AUX_DDI0_OSC -// DIS System CPU has not requested clock for -// AUX_DDI0_OSC -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC 0x00000040 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_BITN 6 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_M 0x00000040 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_S 6 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN 0x00000040 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_DIS 0x00000000 - -// Field: [5] TDC -// -// Enables (1) or disables (0) clock for AUX_TDCIF. -// -// Note that the TDC counter and reference clock sources must be requested -// separately using TDCCLKCTL and REFCLKCTL, respectively. -// ENUMs: -// EN System CPU has requested clock for TDC -// DIS System CPU has not requested clock for TDC -#define AUX_WUC_MODCLKEN0_TDC 0x00000020 -#define AUX_WUC_MODCLKEN0_TDC_BITN 5 -#define AUX_WUC_MODCLKEN0_TDC_M 0x00000020 -#define AUX_WUC_MODCLKEN0_TDC_S 5 -#define AUX_WUC_MODCLKEN0_TDC_EN 0x00000020 -#define AUX_WUC_MODCLKEN0_TDC_DIS 0x00000000 - -// Field: [4] ANAIF -// -// Enables (1) or disables (0) clock for AUX_ANAIF. -// -// Note that the ADC internal clock must be requested separately using -// ADCCLKCTL. -// ENUMs: -// EN System CPU has requested clock for ANAIF -// DIS System CPU has not requested clock for ANAIF -#define AUX_WUC_MODCLKEN0_ANAIF 0x00000010 -#define AUX_WUC_MODCLKEN0_ANAIF_BITN 4 -#define AUX_WUC_MODCLKEN0_ANAIF_M 0x00000010 -#define AUX_WUC_MODCLKEN0_ANAIF_S 4 -#define AUX_WUC_MODCLKEN0_ANAIF_EN 0x00000010 -#define AUX_WUC_MODCLKEN0_ANAIF_DIS 0x00000000 - -// Field: [3] TIMER -// -// Enables (1) or disables (0) clock for AUX_TIMER. -// ENUMs: -// EN System CPU has requested clock for TIMER -// DIS System CPU has not requested clock for TIMER -#define AUX_WUC_MODCLKEN0_TIMER 0x00000008 -#define AUX_WUC_MODCLKEN0_TIMER_BITN 3 -#define AUX_WUC_MODCLKEN0_TIMER_M 0x00000008 -#define AUX_WUC_MODCLKEN0_TIMER_S 3 -#define AUX_WUC_MODCLKEN0_TIMER_EN 0x00000008 -#define AUX_WUC_MODCLKEN0_TIMER_DIS 0x00000000 - -// Field: [2] AIODIO1 -// -// Enables (1) or disables (0) clock for AUX_AIODIO1. -// ENUMs: -// EN System CPU has requested clock for AIODIO1 -// DIS System CPU has not requested clock for AIODIO1 -#define AUX_WUC_MODCLKEN0_AIODIO1 0x00000004 -#define AUX_WUC_MODCLKEN0_AIODIO1_BITN 2 -#define AUX_WUC_MODCLKEN0_AIODIO1_M 0x00000004 -#define AUX_WUC_MODCLKEN0_AIODIO1_S 2 -#define AUX_WUC_MODCLKEN0_AIODIO1_EN 0x00000004 -#define AUX_WUC_MODCLKEN0_AIODIO1_DIS 0x00000000 - -// Field: [1] AIODIO0 -// -// Enables (1) or disables (0) clock for AUX_AIODIO0. -// ENUMs: -// EN System CPU has requested clock for AIODIO0 -// DIS System CPU has not requested clock for AIODIO0 -#define AUX_WUC_MODCLKEN0_AIODIO0 0x00000002 -#define AUX_WUC_MODCLKEN0_AIODIO0_BITN 1 -#define AUX_WUC_MODCLKEN0_AIODIO0_M 0x00000002 -#define AUX_WUC_MODCLKEN0_AIODIO0_S 1 -#define AUX_WUC_MODCLKEN0_AIODIO0_EN 0x00000002 -#define AUX_WUC_MODCLKEN0_AIODIO0_DIS 0x00000000 - -// Field: [0] SMPH -// -// Enables (1) or disables (0) clock for AUX_SMPH. -// ENUMs: -// EN System CPU has requested clock for SMPH -// DIS System CPU has not requested clock for SMPH -#define AUX_WUC_MODCLKEN0_SMPH 0x00000001 -#define AUX_WUC_MODCLKEN0_SMPH_BITN 0 -#define AUX_WUC_MODCLKEN0_SMPH_M 0x00000001 -#define AUX_WUC_MODCLKEN0_SMPH_S 0 -#define AUX_WUC_MODCLKEN0_SMPH_EN 0x00000001 -#define AUX_WUC_MODCLKEN0_SMPH_DIS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_WUC_O_PWROFFREQ -// -//***************************************************************************** -// Field: [0] REQ -// -// Power off request -// -// 0: No action -// 1: Request to power down AUX. Once set, this bit shall not be cleared. The -// bit will be reset again when AUX is powered up again. -// -// The request will only happen if AONCTLSTAT.AUX_FORCE_ON = 0 and -// MCUBUSSTAT.DISCONNECTED=1. -#define AUX_WUC_PWROFFREQ_REQ 0x00000001 -#define AUX_WUC_PWROFFREQ_REQ_BITN 0 -#define AUX_WUC_PWROFFREQ_REQ_M 0x00000001 -#define AUX_WUC_PWROFFREQ_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_PWRDWNREQ -// -//***************************************************************************** -// Field: [0] REQ -// -// Power down request -// -// 0: Request for system to be in active mode -// 1: Request for system to be in power down mode -// -// When REQ is 1 one shall assume that the system is in power down, and that -// current supply is limited. When setting REQ = 0, one shall assume that the -// system is in power down until PWRDWNACK.ACK = 0 -#define AUX_WUC_PWRDWNREQ_REQ 0x00000001 -#define AUX_WUC_PWRDWNREQ_REQ_BITN 0 -#define AUX_WUC_PWRDWNREQ_REQ_M 0x00000001 -#define AUX_WUC_PWRDWNREQ_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_PWRDWNACK -// -//***************************************************************************** -// Field: [0] ACK -// -// Power down acknowledgment. Indicates whether the power down request given by -// PWRDWNREQ.REQ is captured by the AON domain or not -// -// 0: AUX can assume that the system is in active mode -// 1: The request for power down is acknowledged and the AUX must act like the -// system is in power down mode and power supply is limited -// -// The system CPU cannot use this bit since the bus bridge between MCU domain -// and AUX domain is always disconnected when this bit is set. For AUX_SCE use -// only -#define AUX_WUC_PWRDWNACK_ACK 0x00000001 -#define AUX_WUC_PWRDWNACK_ACK_BITN 0 -#define AUX_WUC_PWRDWNACK_ACK_M 0x00000001 -#define AUX_WUC_PWRDWNACK_ACK_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_CLKLFREQ -// -//***************************************************************************** -// Field: [0] REQ -// -// Low frequency request -// -// 0: Request clock frequency to be controlled by AON_WUC:AUXCLK and the system -// state -// 1: Request low frequency clock SCLK_LF as the clock source for AUX -// -// This bit must not be modified unless CLKLFACK.ACK matches the current value -#define AUX_WUC_CLKLFREQ_REQ 0x00000001 -#define AUX_WUC_CLKLFREQ_REQ_BITN 0 -#define AUX_WUC_CLKLFREQ_REQ_M 0x00000001 -#define AUX_WUC_CLKLFREQ_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_CLKLFACK -// -//***************************************************************************** -// Field: [0] ACK -// -// Acknowledgment of CLKLFREQ.REQ -// -// 0: Acknowledgement that clock frequency is controlled by AON_WUC:AUXCLK and -// the system state -// 1: Acknowledgement that the low frequency clock SCLK_LF is the clock source -// for AUX -#define AUX_WUC_CLKLFACK_ACK 0x00000001 -#define AUX_WUC_CLKLFACK_ACK_BITN 0 -#define AUX_WUC_CLKLFACK_ACK_M 0x00000001 -#define AUX_WUC_CLKLFACK_ACK_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_WUEVFLAGS -// -//***************************************************************************** -// Field: [2] AON_RTC_CH2 -// -// Indicates pending event from AON_RTC_CH2 compare. Note that this flag will -// be set whenever the AON_RTC_CH2 event happens, but that does not mean that -// this event is a wake-up event. To make the AON_RTC_CH2 a wake-up event for -// the AUX domain configure it as a wake-up event in AON_EVENT:AUXWUSEL.WU0_EV, -// AON_EVENT:AUXWUSEL.WU1_EV or AON_EVENT:AUXWUSEL.WU2_EV. -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2 0x00000004 -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_BITN 2 -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_M 0x00000004 -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_S 2 - -// Field: [1] AON_SW -// -// Indicates pending event triggered by system CPU writing a 1 to -// AON_WUC:AUXCTL.SWEV. -#define AUX_WUC_WUEVFLAGS_AON_SW 0x00000002 -#define AUX_WUC_WUEVFLAGS_AON_SW_BITN 1 -#define AUX_WUC_WUEVFLAGS_AON_SW_M 0x00000002 -#define AUX_WUC_WUEVFLAGS_AON_SW_S 1 - -// Field: [0] AON_PROG_WU -// -// Indicates pending event triggered by the sources selected in -// AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV and -// AON_EVENT:AUXWUSEL.WU2_EV. -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU 0x00000001 -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_BITN 0 -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_M 0x00000001 -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_WUEVCLR -// -//***************************************************************************** -// Field: [2] AON_RTC_CH2 -// -// Set to clear the WUEVFLAGS.AON_RTC_CH2 wake-up event. Note that if RTC -// channel 2 is also set as source for AON_PROG_WU this field can also clear -// WUEVFLAGS.AON_PROG_WU -// -// This bit must remain set until WUEVFLAGS.AON_RTC_CH2 returns to 0. -#define AUX_WUC_WUEVCLR_AON_RTC_CH2 0x00000004 -#define AUX_WUC_WUEVCLR_AON_RTC_CH2_BITN 2 -#define AUX_WUC_WUEVCLR_AON_RTC_CH2_M 0x00000004 -#define AUX_WUC_WUEVCLR_AON_RTC_CH2_S 2 - -// Field: [1] AON_SW -// -// Set to clear the WUEVFLAGS.AON_SW wake-up event. -// -// This bit must remain set until WUEVFLAGS.AON_SW returns to 0. -#define AUX_WUC_WUEVCLR_AON_SW 0x00000002 -#define AUX_WUC_WUEVCLR_AON_SW_BITN 1 -#define AUX_WUC_WUEVCLR_AON_SW_M 0x00000002 -#define AUX_WUC_WUEVCLR_AON_SW_S 1 - -// Field: [0] AON_PROG_WU -// -// Set to clear the WUEVFLAGS.AON_PROG_WU wake-up event. Note only if an IO -// event is selected as wake-up event, is it possible to use this field to -// clear the source. Other sources cannot be cleared using this field. -// -// The IO pin needs to be assigned to AUX in the IOC and the input enable for -// the pin needs to be set in AIODIO0 or AIODIO1 for this clearing to take -// effect. -// -// This bit must remain set until WUEVFLAGS.AON_PROG_WU returns to 0. -#define AUX_WUC_WUEVCLR_AON_PROG_WU 0x00000001 -#define AUX_WUC_WUEVCLR_AON_PROG_WU_BITN 0 -#define AUX_WUC_WUEVCLR_AON_PROG_WU_M 0x00000001 -#define AUX_WUC_WUEVCLR_AON_PROG_WU_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_ADCCLKCTL -// -//***************************************************************************** -// Field: [1] ACK -// -// Acknowledges the last value written to REQ. -#define AUX_WUC_ADCCLKCTL_ACK 0x00000002 -#define AUX_WUC_ADCCLKCTL_ACK_BITN 1 -#define AUX_WUC_ADCCLKCTL_ACK_M 0x00000002 -#define AUX_WUC_ADCCLKCTL_ACK_S 1 - -// Field: [0] REQ -// -// Enables(1) or disables (0) the ADC internal clock. -// -// This bit must not be modified unless ACK matches the current value. -#define AUX_WUC_ADCCLKCTL_REQ 0x00000001 -#define AUX_WUC_ADCCLKCTL_REQ_BITN 0 -#define AUX_WUC_ADCCLKCTL_REQ_M 0x00000001 -#define AUX_WUC_ADCCLKCTL_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_TDCCLKCTL -// -//***************************************************************************** -// Field: [1] ACK -// -// Acknowledges the last value written to REQ. -#define AUX_WUC_TDCCLKCTL_ACK 0x00000002 -#define AUX_WUC_TDCCLKCTL_ACK_BITN 1 -#define AUX_WUC_TDCCLKCTL_ACK_M 0x00000002 -#define AUX_WUC_TDCCLKCTL_ACK_S 1 - -// Field: [0] REQ -// -// Enables(1) or disables (0) the TDC counter clock source. -// -// This bit must not be modified unless ACK matches the current value. -#define AUX_WUC_TDCCLKCTL_REQ 0x00000001 -#define AUX_WUC_TDCCLKCTL_REQ_BITN 0 -#define AUX_WUC_TDCCLKCTL_REQ_M 0x00000001 -#define AUX_WUC_TDCCLKCTL_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_REFCLKCTL -// -//***************************************************************************** -// Field: [1] ACK -// -// Acknowledges the last value written to REQ. -#define AUX_WUC_REFCLKCTL_ACK 0x00000002 -#define AUX_WUC_REFCLKCTL_ACK_BITN 1 -#define AUX_WUC_REFCLKCTL_ACK_M 0x00000002 -#define AUX_WUC_REFCLKCTL_ACK_S 1 - -// Field: [0] REQ -// -// Enables(1) or disables (0) the TDC reference clock source. -// -// This bit must not be modified unless ACK matches the current value. -#define AUX_WUC_REFCLKCTL_REQ 0x00000001 -#define AUX_WUC_REFCLKCTL_REQ_BITN 0 -#define AUX_WUC_REFCLKCTL_REQ_M 0x00000001 -#define AUX_WUC_REFCLKCTL_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_RTCSUBSECINC0 -// -//***************************************************************************** -// Field: [15:0] INC15_0 -// -// Bits 15:0 of the RTC sub-second increment value. -#define AUX_WUC_RTCSUBSECINC0_INC15_0_W 16 -#define AUX_WUC_RTCSUBSECINC0_INC15_0_M 0x0000FFFF -#define AUX_WUC_RTCSUBSECINC0_INC15_0_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_RTCSUBSECINC1 -// -//***************************************************************************** -// Field: [7:0] INC23_16 -// -// Bits 23:16 of the RTC sub-second increment value. -#define AUX_WUC_RTCSUBSECINC1_INC23_16_W 8 -#define AUX_WUC_RTCSUBSECINC1_INC23_16_M 0x000000FF -#define AUX_WUC_RTCSUBSECINC1_INC23_16_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_RTCSUBSECINCCTL -// -//***************************************************************************** -// Field: [1] UPD_ACK -// -// Acknowledgment of the UPD_REQ. -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 0x00000002 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN 1 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_S 1 - -// Field: [0] UPD_REQ -// -// Signal that a new real time counter sub second increment value is available -// -// 0: New sub second increment is not available -// 1: New sub second increment is available -// -// This bit must not be modified unless UPD_ACK matches the current value. -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 0x00000001 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_BITN 0 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_MCUBUSCTL -// -//***************************************************************************** -// Field: [0] DISCONNECT_REQ -// -// Requests the AUX domain bus to be disconnected from the MCU domain bus. The -// request has no effect when AON_WUC:AUX_CTL.AUX_FORCE_ON is set. -// -// The disconnection status can be monitored through MCUBUSSTAT. Note however -// that this register cannot be read by the system CPU while disconnected. -// -// It is recommended that this bit is set and remains set after initial -// power-up, and that the system CPU uses AON_WUC:AUX_CTL.AUX_FORCE_ON to -// connect/disconnect the bus. -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ 0x00000001 -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_BITN 0 -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_M 0x00000001 -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_MCUBUSSTAT -// -//***************************************************************************** -// Field: [1] DISCONNECTED -// -// Indicates whether the AUX domain and MCU domain buses are currently -// disconnected (1) or connected (0). -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED 0x00000002 -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_BITN 1 -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_M 0x00000002 -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_S 1 - -// Field: [0] DISCONNECT_ACK -// -// Acknowledges reception of the bus disconnection request, by matching the -// value of MCUBUSCTL.DISCONNECT_REQ. -// -// Note that if AON_WUC:AUXCTL.AUX_FORCE_ON = 1 a reconnect to the MCU domain -// bus will be made regardless of the state of MCUBUSCTL.DISCONNECT_REQ -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK 0x00000001 -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_BITN 0 -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_M 0x00000001 -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_AONCTLSTAT -// -//***************************************************************************** -// Field: [1] AUX_FORCE_ON -// -// Status of AON_WUC:AUX_CTL.AUX_FORCE_ON. -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON 0x00000002 -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_BITN 1 -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_M 0x00000002 -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_S 1 - -// Field: [0] SCE_RUN_EN -// -// Status of AON_WUC:AUX_CTL.SCE_RUN_EN. -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN 0x00000001 -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_BITN 0 -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_M 0x00000001 -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_WUC_O_AUXIOLATCH -// -//***************************************************************************** -// Field: [0] EN -// -// Opens (1) or closes (0) the AUX_AIODIO0/AUX_AIODIO1 signal latching. -// -// At startup, set EN = TRANSP before configuring AUX_AIODIO0/AUX_AIODIO1 and -// subsequently selecting AUX mode in the AON_IOC. -// -// When powering off the AUX domain (using PWROFFREQ.REQ), set EN = STATIC in -// advance preserve the current state (mode and output value) of the I/O pins. -// ENUMs: -// TRANSP Latches are transparent ( open ) -// STATIC Latches are static ( closed ) -#define AUX_WUC_AUXIOLATCH_EN 0x00000001 -#define AUX_WUC_AUXIOLATCH_EN_BITN 0 -#define AUX_WUC_AUXIOLATCH_EN_M 0x00000001 -#define AUX_WUC_AUXIOLATCH_EN_S 0 -#define AUX_WUC_AUXIOLATCH_EN_TRANSP 0x00000001 -#define AUX_WUC_AUXIOLATCH_EN_STATIC 0x00000000 - -//***************************************************************************** -// -// Register: AUX_WUC_O_MODCLKEN1 -// -//***************************************************************************** -// Field: [7] AUX_ADI4 -// -// Enables (1) or disables (0) clock for AUX_ADI4. -// ENUMs: -// EN AUX_SCE has requested clock for AUX_ADI4 -// DIS AUX_SCE has not requested clock for AUX_ADI4 -#define AUX_WUC_MODCLKEN1_AUX_ADI4 0x00000080 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_BITN 7 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_M 0x00000080 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_S 7 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_EN 0x00000080 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_DIS 0x00000000 - -// Field: [6] AUX_DDI0_OSC -// -// Enables (1) or disables (0) clock for AUX_DDI0_OSC. -// ENUMs: -// EN AUX_SCE has requested clock for AUX_DDI0_OSC -// DIS AUX_SCE has not requested clock for AUX_DDI0_OSC -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC 0x00000040 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_BITN 6 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_M 0x00000040 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_S 6 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_EN 0x00000040 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_DIS 0x00000000 - -// Field: [4] ANAIF -// -// Enables (1) or disables (0) clock for AUX_ANAIF. -// ENUMs: -// EN AUX_SCE has requested clock for ANAIF -// DIS AUX_SCE has not requested clock for ANAIF -#define AUX_WUC_MODCLKEN1_ANAIF 0x00000010 -#define AUX_WUC_MODCLKEN1_ANAIF_BITN 4 -#define AUX_WUC_MODCLKEN1_ANAIF_M 0x00000010 -#define AUX_WUC_MODCLKEN1_ANAIF_S 4 -#define AUX_WUC_MODCLKEN1_ANAIF_EN 0x00000010 -#define AUX_WUC_MODCLKEN1_ANAIF_DIS 0x00000000 - -// Field: [3] TIMER -// -// Enables (1) or disables (0) clock for AUX_TIMER. -// ENUMs: -// EN AUX_SCE has requested clock for TIMER -// DIS AUX_SCE has not requested clock for TIMER -#define AUX_WUC_MODCLKEN1_TIMER 0x00000008 -#define AUX_WUC_MODCLKEN1_TIMER_BITN 3 -#define AUX_WUC_MODCLKEN1_TIMER_M 0x00000008 -#define AUX_WUC_MODCLKEN1_TIMER_S 3 -#define AUX_WUC_MODCLKEN1_TIMER_EN 0x00000008 -#define AUX_WUC_MODCLKEN1_TIMER_DIS 0x00000000 - -// Field: [2] AIODIO1 -// -// Enables (1) or disables (0) clock for AUX_AIODIO1. -// ENUMs: -// EN AUX_SCE has requested clock for AIODIO1 -// DIS AUX_SCE has not requested clock for AIODIO1 -#define AUX_WUC_MODCLKEN1_AIODIO1 0x00000004 -#define AUX_WUC_MODCLKEN1_AIODIO1_BITN 2 -#define AUX_WUC_MODCLKEN1_AIODIO1_M 0x00000004 -#define AUX_WUC_MODCLKEN1_AIODIO1_S 2 -#define AUX_WUC_MODCLKEN1_AIODIO1_EN 0x00000004 -#define AUX_WUC_MODCLKEN1_AIODIO1_DIS 0x00000000 - -// Field: [1] AIODIO0 -// -// Enables (1) or disables (0) clock for AUX_AIODIO0. -// ENUMs: -// EN AUX_SCE has requested clock for AIODIO0 -// DIS AUX_SCE has not requested clock for AIODIO0 -#define AUX_WUC_MODCLKEN1_AIODIO0 0x00000002 -#define AUX_WUC_MODCLKEN1_AIODIO0_BITN 1 -#define AUX_WUC_MODCLKEN1_AIODIO0_M 0x00000002 -#define AUX_WUC_MODCLKEN1_AIODIO0_S 1 -#define AUX_WUC_MODCLKEN1_AIODIO0_EN 0x00000002 -#define AUX_WUC_MODCLKEN1_AIODIO0_DIS 0x00000000 - -// Field: [0] SMPH -// -// Enables (1) or disables (0) clock for AUX_SMPH. -// ENUMs: -// EN AUX_SCE has requested clock for SMPH -// DIS AUX_SCE has not requested clock for SMPH -#define AUX_WUC_MODCLKEN1_SMPH 0x00000001 -#define AUX_WUC_MODCLKEN1_SMPH_BITN 0 -#define AUX_WUC_MODCLKEN1_SMPH_M 0x00000001 -#define AUX_WUC_MODCLKEN1_SMPH_S 0 -#define AUX_WUC_MODCLKEN1_SMPH_EN 0x00000001 -#define AUX_WUC_MODCLKEN1_SMPH_DIS 0x00000000 - - -#endif // __AUX_WUC__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_ccfg.h b/third_party/ti/devices/cc26x0/inc/hw_ccfg.h deleted file mode 100644 index 2b04a904f..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_ccfg.h +++ /dev/null @@ -1,1919 +0,0 @@ -/****************************************************************************** -* Filename: hw_ccfg_h -* Revised: 2017-02-06 19:32:22 +0100 (Mon, 06 Feb 2017) -* Revision: 48408 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CCFG_H__ -#define __HW_CCFG_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CCFG component -// -//***************************************************************************** -// Extern LF clock configuration -#define CCFG_O_EXT_LF_CLK 0x00000FA8 - -// Mode Configuration 1 -#define CCFG_O_MODE_CONF_1 0x00000FAC - -// CCFG Size and Disable Flags -#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00000FB0 - -// Mode Configuration 0 -#define CCFG_O_MODE_CONF 0x00000FB4 - -// Voltage Load 0 -#define CCFG_O_VOLT_LOAD_0 0x00000FB8 - -// Voltage Load 1 -#define CCFG_O_VOLT_LOAD_1 0x00000FBC - -// Real Time Clock Offset -#define CCFG_O_RTC_OFFSET 0x00000FC0 - -// Frequency Offset -#define CCFG_O_FREQ_OFFSET 0x00000FC4 - -// IEEE MAC Address 0 -#define CCFG_O_IEEE_MAC_0 0x00000FC8 - -// IEEE MAC Address 1 -#define CCFG_O_IEEE_MAC_1 0x00000FCC - -// IEEE BLE Address 0 -#define CCFG_O_IEEE_BLE_0 0x00000FD0 - -// IEEE BLE Address 1 -#define CCFG_O_IEEE_BLE_1 0x00000FD4 - -// Bootloader Configuration -#define CCFG_O_BL_CONFIG 0x00000FD8 - -// Erase Configuration -#define CCFG_O_ERASE_CONF 0x00000FDC - -// TI Options -#define CCFG_O_CCFG_TI_OPTIONS 0x00000FE0 - -// Test Access Points Enable 0 -#define CCFG_O_CCFG_TAP_DAP_0 0x00000FE4 - -// Test Access Points Enable 1 -#define CCFG_O_CCFG_TAP_DAP_1 0x00000FE8 - -// Image Valid -#define CCFG_O_IMAGE_VALID_CONF 0x00000FEC - -// Protect Sectors 0-31 -#define CCFG_O_CCFG_PROT_31_0 0x00000FF0 - -// Protect Sectors 32-63 -#define CCFG_O_CCFG_PROT_63_32 0x00000FF4 - -// Protect Sectors 64-95 -#define CCFG_O_CCFG_PROT_95_64 0x00000FF8 - -// Protect Sectors 96-127 -#define CCFG_O_CCFG_PROT_127_96 0x00000FFC - -//***************************************************************************** -// -// Register: CCFG_O_EXT_LF_CLK -// -//***************************************************************************** -// Field: [31:24] DIO -// -// Unsigned integer, selecting the DIO to supply external 32kHz clock as -// SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO -// will be marked as reserved by the pin driver (TI-RTOS environment) and hence -// not selectable for other usage. -#define CCFG_EXT_LF_CLK_DIO_W 8 -#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 -#define CCFG_EXT_LF_CLK_DIO_S 24 - -// Field: [23:0] RTC_INCREMENT -// -// Unsigned integer, defining the input frequency of the external clock and is -// written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: -// EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: -// RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_MODE_CONF_1 -// -//***************************************************************************** -// Field: [23:20] ALT_DCDC_VMIN -// -// Minimum voltage for when DC/DC should be used if alternate DC/DC setting is -// enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). -// Voltage = (28 + ALT_DCDC_VMIN) / 16. -// 0: 1.75V -// 1: 1.8125V -// ... -// 14: 2.625V -// 15: 2.6875V -// -// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must -// be called regularly to apply this field (handled automatically if using TI -// RTOS!). -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 - -// Field: [19] ALT_DCDC_DITHER_EN -// -// Enable DC/DC dithering if alternate DC/DC setting is enabled -// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). -// 0: Dither disable -// 1: Dither enable -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 - -// Field: [18:16] ALT_DCDC_IPEAK -// -// Inductor peak current if alternate DC/DC setting is enabled -// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external -// inductor! -// Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) : -// 0: 31mA (min) -// ... -// 4: 47mA -// ... -// 7: 59mA (max) -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 - -// Field: [15:12] DELTA_IBIAS_INIT -// -// Signed delta value for IBIAS_INIT. Delta value only applies if -// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. -// See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 - -// Field: [11:8] DELTA_IBIAS_OFFSET -// -// Signed delta value for IBIAS_OFFSET. Delta value only applies if -// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. -// See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 - -// Field: [7:0] XOSC_MAX_START -// -// Unsigned value of maximum XOSC startup time (worst case) in units of 100us. -// Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. -#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 -#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF -#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_SIZE_AND_DIS_FLAGS -// -//***************************************************************************** -// Field: [31:16] SIZE_OF_CCFG -// -// Total size of CCFG in bytes. -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 - -// Field: [15:4] DISABLE_FLAGS -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 - -// Field: [3] DIS_TCXO -// -// Disable TCXO. -// 0: TCXO functionality enabled. -// 1: TCXO functionality disabled. -// Note: -// An external TCXO is required if DIS_TCXO = 0. -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 - -// Field: [2] DIS_GPRAM -// -// Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). -// 0: GPRAM is enabled and hence CACHE disabled. -// 1: GPRAM is disabled and instead CACHE is enabled (default). -// Notes: -// - Disabling CACHE will reduce CPU execution speed (up to 60%). -// - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if -// enabled. -// See: -// VIMS:CTL.MODE -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 - -// Field: [1] DIS_ALT_DCDC_SETTING -// -// Disable alternate DC/DC settings. -// 0: Enable alternate DC/DC settings. -// 1: Disable alternate DC/DC settings. -// See: -// MODE_CONF_1.ALT_DCDC_VMIN -// MODE_CONF_1.ALT_DCDC_DITHER_EN -// MODE_CONF_1.ALT_DCDC_IPEAK -// -// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must -// be called regularly to apply this field (handled automatically if using TI -// RTOS!). -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 - -// Field: [0] DIS_XOSC_OVR -// -// Disable XOSC override functionality. -// 0: Enable XOSC override functionality. -// 1: Disable XOSC override functionality. -// See: -// MODE_CONF_1.DELTA_IBIAS_INIT -// MODE_CONF_1.DELTA_IBIAS_OFFSET -// MODE_CONF_1.XOSC_MAX_START -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_MODE_CONF -// -//***************************************************************************** -// Field: [31:28] VDDR_TRIM_SLEEP_DELTA -// -// Signed delta value to apply to the -// VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. -// 0x8 (-8) : Delta = -7 -// ... -// 0xF (-1) : Delta = 0 -// 0x0 (0) : Delta = +1 -// ... -// 0x7 (7) : Delta = +8 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 - -// Field: [27] DCDC_RECHARGE -// -// DC/DC during recharge in powerdown. -// 0: Use the DC/DC during recharge in powerdown. -// 1: Do not use the DC/DC during recharge in powerdown (default). -// -// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must -// be called regularly to apply this field (handled automatically if using TI -// RTOS!). -#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 -#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 -#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 -#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 - -// Field: [26] DCDC_ACTIVE -// -// DC/DC in active mode. -// 0: Use the DC/DC during active mode. -// 1: Do not use the DC/DC during active mode (default). -// -// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must -// be called regularly to apply this field (handled automatically if using TI -// RTOS!). -#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 -#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 -#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 -#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 - -// Field: [25] VDDR_EXT_LOAD -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 - -// Field: [24] VDDS_BOD_LEVEL -// -// VDDS BOD level. -// 0: VDDS BOD level is 2.0 V (necessary for maximum PA output power on -// CC13x0). -// 1: VDDS BOD level is 1.8 V (or 1.7 V for external regulator mode) (default). -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 - -// Field: [23:22] SCLK_LF_OPTION -// -// Select source for SCLK_LF. -// ENUMs: -// RCOSC_LF Low frequency RCOSC (default) -// XOSC_LF 32.768kHz low frequency XOSC -// EXTERNAL_LF External low frequency clock on DIO defined by -// EXT_LF_CLK.DIO. The RTC tick speed -// AON_RTC:SUBSECINC is updated to -// EXT_LF_CLK.RTC_INCREMENT (done in the -// trimDevice() xxWare boot function). External -// clock must always be running when the chip is -// in standby for VDDR recharge timing. -// XOSC_HF_DLF 31.25kHz clock derived from 24MHz XOSC (dividing -// by 768 in HW). The RTC tick speed -// [AON_RTC.SUBSECINC.*] is updated to 0x8637BD, -// corresponding to a 31.25kHz clock (done in the -// trimDevice() xxWare boot function). Standby -// power mode is not supported when using this -// clock source. -#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 - -// Field: [21] VDDR_TRIM_SLEEP_TC -// -// 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated -// 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time -// standby mode is entered. This improves low-temperature RCOSC_LF frequency -// stability in standby mode. -// -// When temperature compensation is performed, the delta is calculates this -// way: -// Delta = max (delta, min(8, floor(62-temp)/8)) -// Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current -// temperature in degrees C. -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 - -// Field: [20] RTC_COMP -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_MODE_CONF_RTC_COMP 0x00100000 -#define CCFG_MODE_CONF_RTC_COMP_BITN 20 -#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 -#define CCFG_MODE_CONF_RTC_COMP_S 20 - -// Field: [19:18] XOSC_FREQ -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -// ENUMs: -// 24M 24 MHz XOSC_HF -// 48M 48 MHz XOSC_HF -// HPOSC HPOSC -#define CCFG_MODE_CONF_XOSC_FREQ_W 2 -#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 -#define CCFG_MODE_CONF_XOSC_FREQ_S 18 -#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 -#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 -#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 - -// Field: [17] XOSC_CAP_MOD -// -// Enable modification (delta) to XOSC cap-array. Value specified in -// XOSC_CAPARRAY_DELTA. -// 0: Apply cap-array delta -// 1: Do not apply cap-array delta (default) -#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 - -// Field: [16] HF_COMP -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_MODE_CONF_HF_COMP 0x00010000 -#define CCFG_MODE_CONF_HF_COMP_BITN 16 -#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 -#define CCFG_MODE_CONF_HF_COMP_S 16 - -// Field: [15:8] XOSC_CAPARRAY_DELTA -// -// Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. -// Enabled by XOSC_CAP_MOD. -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 - -// Field: [7:0] VDDR_CAP -// -// Unsigned 8-bit integer, representing the minimum decoupling capacitance -// (worst case) on VDDR, in units of 100nF. This should take into account -// capacitor tolerance and voltage dependent capacitance variation. This bit -// affects the recharge period calculation when going into powerdown or -// standby. -// -// NOTE! If using the following functions this field must be configured (used -// by TI RTOS): -// SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() -#define CCFG_MODE_CONF_VDDR_CAP_W 8 -#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF -#define CCFG_MODE_CONF_VDDR_CAP_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_VOLT_LOAD_0 -// -//***************************************************************************** -// Field: [31:24] VDDR_EXT_TP45 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 - -// Field: [23:16] VDDR_EXT_TP25 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 - -// Field: [15:8] VDDR_EXT_TP5 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 - -// Field: [7:0] VDDR_EXT_TM15 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_VOLT_LOAD_1 -// -//***************************************************************************** -// Field: [31:24] VDDR_EXT_TP125 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 - -// Field: [23:16] VDDR_EXT_TP105 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 - -// Field: [15:8] VDDR_EXT_TP85 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 - -// Field: [7:0] VDDR_EXT_TP65 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_RTC_OFFSET -// -//***************************************************************************** -// Field: [31:16] RTC_COMP_P0 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 -#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 -#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 - -// Field: [15:8] RTC_COMP_P1 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 -#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 -#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 - -// Field: [7:0] RTC_COMP_P2 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 -#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF -#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_FREQ_OFFSET -// -//***************************************************************************** -// Field: [31:16] HF_COMP_P0 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 -#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 -#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 - -// Field: [15:8] HF_COMP_P1 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 -#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 -#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 - -// Field: [7:0] HF_COMP_P2 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 -#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF -#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_IEEE_MAC_0 -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Bits[31:0] of the 64-bits custom IEEE MAC address. -// If different from 0xFFFFFFFF then the value of this field is applied; -// otherwise use value from FCFG. -#define CCFG_IEEE_MAC_0_ADDR_W 32 -#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_MAC_0_ADDR_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_IEEE_MAC_1 -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Bits[63:32] of the 64-bits custom IEEE MAC address. -// If different from 0xFFFFFFFF then the value of this field is applied; -// otherwise use value from FCFG. -#define CCFG_IEEE_MAC_1_ADDR_W 32 -#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_MAC_1_ADDR_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_IEEE_BLE_0 -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Bits[31:0] of the 64-bits custom IEEE BLE address. -// If different from 0xFFFFFFFF then the value of this field is applied; -// otherwise use value from FCFG. -#define CCFG_IEEE_BLE_0_ADDR_W 32 -#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_BLE_0_ADDR_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_IEEE_BLE_1 -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Bits[63:32] of the 64-bits custom IEEE BLE address. -// If different from 0xFFFFFFFF then the value of this field is applied; -// otherwise use value from FCFG. -#define CCFG_IEEE_BLE_1_ADDR_W 32 -#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_BLE_1_ADDR_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_BL_CONFIG -// -//***************************************************************************** -// Field: [31:24] BOOTLOADER_ENABLE -// -// Bootloader enable. Boot loader can be accessed if -// IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and -// conditions for boot loader backdoor are met). -// 0xC5: Boot loader is enabled. -// Any other value: Boot loader is disabled. -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 - -// Field: [16] BL_LEVEL -// -// Sets the active level of the selected DIO number BL_PIN_NUMBER if boot -// loader backdoor is enabled by the BL_ENABLE field. -// 0: Active low. -// 1: Active high. -#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 -#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 -#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 -#define CCFG_BL_CONFIG_BL_LEVEL_S 16 - -// Field: [15:8] BL_PIN_NUMBER -// -// DIO number that is level checked if the boot loader backdoor is enabled by -// the BL_ENABLE field. -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 - -// Field: [7:0] BL_ENABLE -// -// Enables the boot loader backdoor. -// 0xC5: Boot loader backdoor is enabled. -// Any other value: Boot loader backdoor is disabled. -// -// NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader -// backdoor is enabled. -#define CCFG_BL_CONFIG_BL_ENABLE_W 8 -#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF -#define CCFG_BL_CONFIG_BL_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_ERASE_CONF -// -//***************************************************************************** -// Field: [8] CHIP_ERASE_DIS_N -// -// Chip erase. -// This bit controls if a chip erase requested through the JTAG WUC TAP will be -// ignored in a following boot caused by a reset of the MCU VD. -// A successful chip erase operation will force the content of the flash main -// bank back to the state as it was when delivered by TI. -// 0: Disable. Any chip erase request detected during boot will be ignored. -// 1: Enable. Any chip erase request detected during boot will be performed by -// the boot FW. -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 - -// Field: [0] BANK_ERASE_DIS_N -// -// Bank erase. -// This bit controls if the ROM serial boot loader will accept a received Bank -// Erase command (COMMAND_BANK_ERASE). -// A successful Bank Erase operation will erase all main bank sectors not -// protected by write protect configuration bits in CCFG. -// 0: Disable the boot loader bank erase function. -// 1: Enable the boot loader bank erase function. -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_TI_OPTIONS -// -//***************************************************************************** -// Field: [7:0] TI_FA_ENABLE -// -// TI Failure Analysis. -// 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) -// option with the unlock code. -// All other values: Disable the functionality of unlocking the TI FA option -// with the unlock code. -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_TAP_DAP_0 -// -//***************************************************************************** -// Field: [23:16] CPU_DAP_ENABLE -// -// Enable CPU DAP. -// 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM -// boot FW. -// Any other value: Main CPU DAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 - -// Field: [15:8] PRCM_TAP_ENABLE -// -// Enable PRCM TAP. -// 0xC5: PRCM TAP access is enabled during power-up/system-reset by ROM boot FW -// if enabled by corresponding configuration value in FCFG1 defined by TI. -// Any other value: PRCM TAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M 0x0000FF00 -#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S 8 - -// Field: [7:0] TEST_TAP_ENABLE -// -// Enable Test TAP. -// 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW -// if enabled by corresponding configuration value in FCFG1 defined by TI. -// Any other value: TEST TAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_TAP_DAP_1 -// -//***************************************************************************** -// Field: [23:16] PBIST2_TAP_ENABLE -// -// Enable PBIST2 TAP. -// 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot -// FW if enabled by corresponding configuration value in FCFG1 defined by TI. -// Any other value: PBIST2 TAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 - -// Field: [15:8] PBIST1_TAP_ENABLE -// -// Enable PBIST1 TAP. -// 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot -// FW if enabled by corresponding configuration value in FCFG1 defined by TI. -// Any other value: PBIST1 TAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 - -// Field: [7:0] WUC_TAP_ENABLE -// -// Enable WUC TAP -// 0xC5: WUC TAP access is enabled during power-up/system-reset by ROM boot FW -// if enabled by corresponding configuration value in FCFG1 defined by TI. -// Any other value: WUC TAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M 0x000000FF -#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_IMAGE_VALID_CONF -// -//***************************************************************************** -// Field: [31:0] IMAGE_VALID -// -// This field must have a value of 0x00000000 in order for enabling the boot -// sequence to transfer control to a flash image. -// A non-zero value forces the boot sequence to call the boot loader. -// -// For CC2640R2: -// This field must have the address value of the start of the flash vector -// table in order for enabling the boot sequence to transfer control to a flash -// image. -// Any illegal vector table start address value forces the boot sequence to -// call the boot loader. -// Note that if any other legal vector table start address value than 0x0 is -// selected the PRCM:WARMRESET.WR_TO_PINRESET must be set to 1. -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_PROT_31_0 -// -//***************************************************************************** -// Field: [31] WRT_PROT_SEC_31 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 - -// Field: [30] WRT_PROT_SEC_30 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 - -// Field: [29] WRT_PROT_SEC_29 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 - -// Field: [28] WRT_PROT_SEC_28 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 - -// Field: [27] WRT_PROT_SEC_27 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 - -// Field: [26] WRT_PROT_SEC_26 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 - -// Field: [25] WRT_PROT_SEC_25 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 - -// Field: [24] WRT_PROT_SEC_24 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 - -// Field: [23] WRT_PROT_SEC_23 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 - -// Field: [22] WRT_PROT_SEC_22 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 - -// Field: [21] WRT_PROT_SEC_21 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 - -// Field: [20] WRT_PROT_SEC_20 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 - -// Field: [19] WRT_PROT_SEC_19 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 - -// Field: [18] WRT_PROT_SEC_18 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 - -// Field: [17] WRT_PROT_SEC_17 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 - -// Field: [16] WRT_PROT_SEC_16 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 - -// Field: [15] WRT_PROT_SEC_15 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 - -// Field: [14] WRT_PROT_SEC_14 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 - -// Field: [13] WRT_PROT_SEC_13 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 - -// Field: [12] WRT_PROT_SEC_12 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 - -// Field: [11] WRT_PROT_SEC_11 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 - -// Field: [10] WRT_PROT_SEC_10 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 - -// Field: [9] WRT_PROT_SEC_9 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 - -// Field: [8] WRT_PROT_SEC_8 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 - -// Field: [7] WRT_PROT_SEC_7 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 - -// Field: [6] WRT_PROT_SEC_6 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 - -// Field: [5] WRT_PROT_SEC_5 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 - -// Field: [4] WRT_PROT_SEC_4 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 - -// Field: [3] WRT_PROT_SEC_3 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 - -// Field: [2] WRT_PROT_SEC_2 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 - -// Field: [1] WRT_PROT_SEC_1 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 - -// Field: [0] WRT_PROT_SEC_0 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_PROT_63_32 -// -//***************************************************************************** -// Field: [31] WRT_PROT_SEC_63 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 - -// Field: [30] WRT_PROT_SEC_62 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 - -// Field: [29] WRT_PROT_SEC_61 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 - -// Field: [28] WRT_PROT_SEC_60 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 - -// Field: [27] WRT_PROT_SEC_59 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 - -// Field: [26] WRT_PROT_SEC_58 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 - -// Field: [25] WRT_PROT_SEC_57 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 - -// Field: [24] WRT_PROT_SEC_56 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 - -// Field: [23] WRT_PROT_SEC_55 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 - -// Field: [22] WRT_PROT_SEC_54 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 - -// Field: [21] WRT_PROT_SEC_53 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 - -// Field: [20] WRT_PROT_SEC_52 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 - -// Field: [19] WRT_PROT_SEC_51 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 - -// Field: [18] WRT_PROT_SEC_50 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 - -// Field: [17] WRT_PROT_SEC_49 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 - -// Field: [16] WRT_PROT_SEC_48 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 - -// Field: [15] WRT_PROT_SEC_47 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 - -// Field: [14] WRT_PROT_SEC_46 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 - -// Field: [13] WRT_PROT_SEC_45 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 - -// Field: [12] WRT_PROT_SEC_44 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 - -// Field: [11] WRT_PROT_SEC_43 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 - -// Field: [10] WRT_PROT_SEC_42 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 - -// Field: [9] WRT_PROT_SEC_41 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 - -// Field: [8] WRT_PROT_SEC_40 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 - -// Field: [7] WRT_PROT_SEC_39 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 - -// Field: [6] WRT_PROT_SEC_38 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 - -// Field: [5] WRT_PROT_SEC_37 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 - -// Field: [4] WRT_PROT_SEC_36 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 - -// Field: [3] WRT_PROT_SEC_35 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 - -// Field: [2] WRT_PROT_SEC_34 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 - -// Field: [1] WRT_PROT_SEC_33 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 - -// Field: [0] WRT_PROT_SEC_32 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_PROT_95_64 -// -//***************************************************************************** -// Field: [31] WRT_PROT_SEC_95 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 - -// Field: [30] WRT_PROT_SEC_94 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 - -// Field: [29] WRT_PROT_SEC_93 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 - -// Field: [28] WRT_PROT_SEC_92 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 - -// Field: [27] WRT_PROT_SEC_91 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 - -// Field: [26] WRT_PROT_SEC_90 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 - -// Field: [25] WRT_PROT_SEC_89 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 - -// Field: [24] WRT_PROT_SEC_88 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 - -// Field: [23] WRT_PROT_SEC_87 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 - -// Field: [22] WRT_PROT_SEC_86 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 - -// Field: [21] WRT_PROT_SEC_85 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 - -// Field: [20] WRT_PROT_SEC_84 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 - -// Field: [19] WRT_PROT_SEC_83 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 - -// Field: [18] WRT_PROT_SEC_82 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 - -// Field: [17] WRT_PROT_SEC_81 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 - -// Field: [16] WRT_PROT_SEC_80 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 - -// Field: [15] WRT_PROT_SEC_79 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 - -// Field: [14] WRT_PROT_SEC_78 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 - -// Field: [13] WRT_PROT_SEC_77 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 - -// Field: [12] WRT_PROT_SEC_76 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 - -// Field: [11] WRT_PROT_SEC_75 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 - -// Field: [10] WRT_PROT_SEC_74 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 - -// Field: [9] WRT_PROT_SEC_73 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 - -// Field: [8] WRT_PROT_SEC_72 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 - -// Field: [7] WRT_PROT_SEC_71 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 - -// Field: [6] WRT_PROT_SEC_70 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 - -// Field: [5] WRT_PROT_SEC_69 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 - -// Field: [4] WRT_PROT_SEC_68 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 - -// Field: [3] WRT_PROT_SEC_67 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 - -// Field: [2] WRT_PROT_SEC_66 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 - -// Field: [1] WRT_PROT_SEC_65 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 - -// Field: [0] WRT_PROT_SEC_64 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_PROT_127_96 -// -//***************************************************************************** -// Field: [31] WRT_PROT_SEC_127 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 - -// Field: [30] WRT_PROT_SEC_126 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 - -// Field: [29] WRT_PROT_SEC_125 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 - -// Field: [28] WRT_PROT_SEC_124 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 - -// Field: [27] WRT_PROT_SEC_123 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 - -// Field: [26] WRT_PROT_SEC_122 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 - -// Field: [25] WRT_PROT_SEC_121 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 - -// Field: [24] WRT_PROT_SEC_120 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 - -// Field: [23] WRT_PROT_SEC_119 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 - -// Field: [22] WRT_PROT_SEC_118 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 - -// Field: [21] WRT_PROT_SEC_117 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 - -// Field: [20] WRT_PROT_SEC_116 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 - -// Field: [19] WRT_PROT_SEC_115 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 - -// Field: [18] WRT_PROT_SEC_114 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 - -// Field: [17] WRT_PROT_SEC_113 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 - -// Field: [16] WRT_PROT_SEC_112 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 - -// Field: [15] WRT_PROT_SEC_111 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 - -// Field: [14] WRT_PROT_SEC_110 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 - -// Field: [13] WRT_PROT_SEC_109 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 - -// Field: [12] WRT_PROT_SEC_108 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 - -// Field: [11] WRT_PROT_SEC_107 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 - -// Field: [10] WRT_PROT_SEC_106 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 - -// Field: [9] WRT_PROT_SEC_105 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 - -// Field: [8] WRT_PROT_SEC_104 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 - -// Field: [7] WRT_PROT_SEC_103 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 - -// Field: [6] WRT_PROT_SEC_102 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 - -// Field: [5] WRT_PROT_SEC_101 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 - -// Field: [4] WRT_PROT_SEC_100 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 - -// Field: [3] WRT_PROT_SEC_99 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 - -// Field: [2] WRT_PROT_SEC_98 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 - -// Field: [1] WRT_PROT_SEC_97 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 - -// Field: [0] WRT_PROT_SEC_96 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 - - -#endif // __CCFG__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_ccfg_simple_struct.h b/third_party/ti/devices/cc26x0/inc/hw_ccfg_simple_struct.h deleted file mode 100644 index 62aee89a8..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_ccfg_simple_struct.h +++ /dev/null @@ -1,81 +0,0 @@ -/****************************************************************************** -* Filename: hw_ccfg_simple_struct_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CCFG_SIMPLE_STRUCT_H__ -#define __HW_CCFG_SIMPLE_STRUCT_H__ - -//***************************************************************************** -// -// Customer configuration (ccfg) typedef. -// The implementation of this struct is required by device ROM boot code -// and must be placed at the end of flash. Do not modify this struct! -// -//***************************************************************************** -typedef struct -{ // Mapped to address - uint32_t CCFG_EXT_LF_CLK ; // 0x50003FA8 - uint32_t CCFG_MODE_CONF_1 ; // 0x50003FAC - uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50003FB0 - uint32_t CCFG_MODE_CONF ; // 0x50003FB4 - uint32_t CCFG_VOLT_LOAD_0 ; // 0x50003FB8 - uint32_t CCFG_VOLT_LOAD_1 ; // 0x50003FBC - uint32_t CCFG_RTC_OFFSET ; // 0x50003FC0 - uint32_t CCFG_FREQ_OFFSET ; // 0x50003FC4 - uint32_t CCFG_IEEE_MAC_0 ; // 0x50003FC8 - uint32_t CCFG_IEEE_MAC_1 ; // 0x50003FCC - uint32_t CCFG_IEEE_BLE_0 ; // 0x50003FD0 - uint32_t CCFG_IEEE_BLE_1 ; // 0x50003FD4 - uint32_t CCFG_BL_CONFIG ; // 0x50003FD8 - uint32_t CCFG_ERASE_CONF ; // 0x50003FDC - uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50003FE0 - uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50003FE4 - uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50003FE8 - uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50003FEC - uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50003FF0 - uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50003FF4 - uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50003FF8 - uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50003FFC -} ccfg_t; - -//***************************************************************************** -// -// Define the extern ccfg structure (__ccfg) -// -//***************************************************************************** -extern const ccfg_t __ccfg; - - -#endif // __HW_CCFG_SIMPLE_STRUCT__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_chip_def.h b/third_party/ti/devices/cc26x0/inc/hw_chip_def.h deleted file mode 100644 index 42255c69c..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_chip_def.h +++ /dev/null @@ -1,237 +0,0 @@ -/****************************************************************************** -* Filename: hw_chip_def.h -* Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) -* Revision: 49227 -* -* Description: Defines for device properties. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup config_api -//! @{ -// -//***************************************************************************** - -#ifndef __HW_CHIP_DEF_H__ -#define __HW_CHIP_DEF_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Define CC_CHIP_ID code used in the following macros defined at the bottom: -// CC_GET_CHIP_FAMILY/DEVICE/PACKAGE/HWREV -// -//***************************************************************************** -/* CC2620F128 */ -#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) - #define CC_CHIP_ID 0x26200720 -#elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21) - #define CC_CHIP_ID 0x26200520 -#elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21) - #define CC_CHIP_ID 0x26200420 -#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) - #define CC_CHIP_ID 0x26200020 -#elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ) - #define CC_CHIP_ID 0x26200722 -#elif defined(CC2620F128RHB_R22) || defined(CC2620F128RHB) - #define CC_CHIP_ID 0x26200522 -#elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM) - #define CC_CHIP_ID 0x26200422 -#elif defined(CC2620F128_R22) || defined(CC2620F128) - #define CC_CHIP_ID 0x26200022 -/* CC2630F128 */ -#elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21) - #define CC_CHIP_ID 0x26300720 -#elif defined(CC2630F128RHB_R20) || defined(CC2630F128RHB_R21) - #define CC_CHIP_ID 0x26300520 -#elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21) - #define CC_CHIP_ID 0x26300420 -#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) - #define CC_CHIP_ID 0x26300020 -#elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ) - #define CC_CHIP_ID 0x26300722 -#elif defined(CC2630F128RHB_R22) || defined(CC2630F128RHB) - #define CC_CHIP_ID 0x26300522 -#elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM) - #define CC_CHIP_ID 0x26300422 -#elif defined(CC2630F128_R22) || defined(CC2630F128) - #define CC_CHIP_ID 0x26300022 -/* CC2640F128 */ -#elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21) - #define CC_CHIP_ID 0x26400720 -#elif defined(CC2640F128RHB_R20) || defined(CC2640F128RHB_R21) - #define CC_CHIP_ID 0x26400520 -#elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21) - #define CC_CHIP_ID 0x26400420 -#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) - #define CC_CHIP_ID 0x26400020 -#elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ) - #define CC_CHIP_ID 0x26400722 -#elif defined(CC2640F128RHB_R22) || defined(CC2640F128RHB) - #define CC_CHIP_ID 0x26400522 -#elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM) - #define CC_CHIP_ID 0x26400422 -#elif defined(CC2640F128_R22) || defined(CC2640F128) - #define CC_CHIP_ID 0x26400022 -/* CC2650F128 */ -#elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21) - #define CC_CHIP_ID 0x26500720 -#elif defined(CC2650F128RHB_R20) || defined(CC2650F128RHB_R21) - #define CC_CHIP_ID 0x26500520 -#elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21) - #define CC_CHIP_ID 0x26500420 -#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) - #define CC_CHIP_ID 0x26500020 -#elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ) - #define CC_CHIP_ID 0x26500722 -#elif defined(CC2650F128RHB_R22) || defined(CC2650F128RHB) - #define CC_CHIP_ID 0x26500522 -#elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM) - #define CC_CHIP_ID 0x26500422 -#elif defined(CC2650F128_R22) || defined(CC2650F128) - #define CC_CHIP_ID 0x26500022 -/* CC2650L128 (OTP) */ -#elif defined(CC2650L128) - #define CC_CHIP_ID 0x26501710 -/* CC1310F128 */ -#elif defined(CC1310F128RGZ_R20) || defined(CC1310F128RGZ) - #define CC_CHIP_ID 0x13100720 -#elif defined(CC1310F128RHB_R20) || defined(CC1310F128RHB) - #define CC_CHIP_ID 0x13100520 -#elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM) - #define CC_CHIP_ID 0x13100420 -#elif defined(CC1310F128_R20) || defined(CC1310F128) - #define CC_CHIP_ID 0x13100020 -/* CC1350F128 */ -#elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ) - #define CC_CHIP_ID 0x13500720 -#elif defined(CC1350F128RHB_R20) || defined(CC1350F128RHB) - #define CC_CHIP_ID 0x13500520 -#elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM) - #define CC_CHIP_ID 0x13500420 -#elif defined(CC1350F128_R20) || defined(CC1350F128) - #define CC_CHIP_ID 0x13500020 -/* CC2640R2F */ -#elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ) - #define CC_CHIP_ID 0x26401710 -#elif defined(CC2640R2FRHB_R25) || defined(CC2640R2FRHB) - #define CC_CHIP_ID 0x26401510 -#elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM) - #define CC_CHIP_ID 0x26401410 -#elif defined(CC2640R2F_R25) || defined(CC2640R2F) - #define CC_CHIP_ID 0x26401010 -/* CC2652R1F */ -#elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ) - #define CC_CHIP_ID 0x26523710 -#elif defined(CC2652R1F_R10) || defined(CC2652R1F) - #define CC_CHIP_ID 0x26523010 -/* CC2644R1F */ -#elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ) - #define CC_CHIP_ID 0x26443710 -#elif defined(CC2644R1F_R10) || defined(CC2644R1F) - #define CC_CHIP_ID 0x26443010 -/* CC2642R1F */ -#elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ) - #define CC_CHIP_ID 0x26423710 -#elif defined(CC2642R1F_R10) || defined(CC2642R1F) - #define CC_CHIP_ID 0x26423010 -/* CC1354R1F */ -#elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ) - #define CC_CHIP_ID 0x13543710 -#elif defined(CC1354R1F_R10) || defined(CC1354R1F) - #define CC_CHIP_ID 0x13543010 -/* CC1352R1F */ -#elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ) - #define CC_CHIP_ID 0x13523710 -#elif defined(CC1352R1F_R10) || defined(CC1352R1F) - #define CC_CHIP_ID 0x13523010 -/* CC1312R1F */ -#elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ) - #define CC_CHIP_ID 0x13123710 -#elif defined(CC1312R1F_R10) || defined(CC1312R1F) - #define CC_CHIP_ID 0x13123010 -#endif - -#define CC_GET_CHIP_FAMILY 0x26 -#define CC_GET_CHIP_OPTION 0x0 -#define CC_GET_CHIP_HWREV 0x22 - -#ifdef CC_CHIP_ID - /* Define chip package only if specified */ - #if (CC_CHIP_ID & 0x00000F00) != 0 - #define CC_GET_CHIP_PACKAGE (((CC_CHIP_ID) & 0x00000F00) >> 8) - #endif - - /* Define chip device */ - #define CC_GET_CHIP_DEVICE (((CC_CHIP_ID) & 0xFFFF0000) >> 16) - - /* The chip family, option and package shall match the DriverLib release */ - #if (CC_GET_CHIP_FAMILY != ((CC_CHIP_ID & 0xFF000000) >> 24)) - #error "Specified chip family does not match DriverLib release" - #endif - #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12)) - #error "Specified chip option does not match DriverLib release" - #endif - #if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) - #error "Specified chip hardware revision does not match DriverLib release" - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __HW_CHIP_DEF_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/third_party/ti/devices/cc26x0/inc/hw_cpu_dwt.h b/third_party/ti/devices/cc26x0/inc/hw_cpu_dwt.h deleted file mode 100644 index 56a559c5f..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_cpu_dwt.h +++ /dev/null @@ -1,856 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_dwt_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_DWT_H__ -#define __HW_CPU_DWT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_DWT component -// -//***************************************************************************** -// Control -#define CPU_DWT_O_CTRL 0x00000000 - -// Current PC Sampler Cycle Count -#define CPU_DWT_O_CYCCNT 0x00000004 - -// CPI Count -#define CPU_DWT_O_CPICNT 0x00000008 - -// Exception Overhead Count -#define CPU_DWT_O_EXCCNT 0x0000000C - -// Sleep Count -#define CPU_DWT_O_SLEEPCNT 0x00000010 - -// LSU Count -#define CPU_DWT_O_LSUCNT 0x00000014 - -// Fold Count -#define CPU_DWT_O_FOLDCNT 0x00000018 - -// Program Counter Sample -#define CPU_DWT_O_PCSR 0x0000001C - -// Comparator 0 -#define CPU_DWT_O_COMP0 0x00000020 - -// Mask 0 -#define CPU_DWT_O_MASK0 0x00000024 - -// Function 0 -#define CPU_DWT_O_FUNCTION0 0x00000028 - -// Comparator 1 -#define CPU_DWT_O_COMP1 0x00000030 - -// Mask 1 -#define CPU_DWT_O_MASK1 0x00000034 - -// Function 1 -#define CPU_DWT_O_FUNCTION1 0x00000038 - -// Comparator 2 -#define CPU_DWT_O_COMP2 0x00000040 - -// Mask 2 -#define CPU_DWT_O_MASK2 0x00000044 - -// Function 2 -#define CPU_DWT_O_FUNCTION2 0x00000048 - -// Comparator 3 -#define CPU_DWT_O_COMP3 0x00000050 - -// Mask 3 -#define CPU_DWT_O_MASK3 0x00000054 - -// Function 3 -#define CPU_DWT_O_FUNCTION3 0x00000058 - -//***************************************************************************** -// -// Register: CPU_DWT_O_CTRL -// -//***************************************************************************** -// Field: [25] NOCYCCNT -// -// When set, CYCCNT is not supported. -#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 -#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 -#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 -#define CPU_DWT_CTRL_NOCYCCNT_S 25 - -// Field: [24] NOPRFCNT -// -// When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. -#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 -#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 -#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 -#define CPU_DWT_CTRL_NOPRFCNT_S 24 - -// Field: [22] CYCEVTENA -// -// Enables Cycle count event. Emits an event when the POSTCNT counter triggers -// it. See CYCTAP and POSTPRESET for details. This event is only emitted if -// PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. -// -// 0: Cycle count events disabled -// 1: Cycle count events enabled -#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 -#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 -#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 -#define CPU_DWT_CTRL_CYCEVTENA_S 22 - -// Field: [21] FOLDEVTENA -// -// Enables Folded instruction count event. Emits an event when FOLDCNT -// overflows (every 256 cycles of folded instructions). A folded instruction is -// one that does not incur even one cycle to execute. For example, an IT -// instruction is folded away and so does not use up one cycle. -// -// 0: Folded instruction count events disabled. -// 1: Folded instruction count events enabled. -#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 -#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 -#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 -#define CPU_DWT_CTRL_FOLDEVTENA_S 21 - -// Field: [20] LSUEVTENA -// -// Enables LSU count event. Emits an event when LSUCNT overflows (every 256 -// cycles of LSU operation). LSU counts include all LSU costs after the initial -// cycle for the instruction. -// -// 0: LSU count events disabled. -// 1: LSU count events enabled. -#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 -#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 -#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 -#define CPU_DWT_CTRL_LSUEVTENA_S 20 - -// Field: [19] SLEEPEVTENA -// -// Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 -// cycles that the processor is sleeping). -// -// 0: Sleep count events disabled. -// 1: Sleep count events enabled. -#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 -#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 -#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 -#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 - -// Field: [18] EXCEVTENA -// -// Enables Interrupt overhead event. Emits an event when EXCCNT overflows -// (every 256 cycles of interrupt overhead). -// -// 0x0: Interrupt overhead event disabled. -// 0x1: Interrupt overhead event enabled. -#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 -#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 -#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 -#define CPU_DWT_CTRL_EXCEVTENA_S 18 - -// Field: [17] CPIEVTENA -// -// Enables CPI count event. Emits an event when CPICNT overflows (every 256 -// cycles of multi-cycle instructions). -// -// 0: CPI counter events disabled. -// 1: CPI counter events enabled. -#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 -#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 -#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 -#define CPU_DWT_CTRL_CPIEVTENA_S 17 - -// Field: [16] EXCTRCENA -// -// Enables Interrupt event tracing. -// -// 0: Interrupt event trace disabled. -// 1: Interrupt event trace enabled. -#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 -#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 -#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 -#define CPU_DWT_CTRL_EXCTRCENA_S 16 - -// Field: [12] PCSAMPLEENA -// -// Enables PC Sampling event. A PC sample event is emitted when the POSTCNT -// counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this -// bit overrides CYCEVTENA. -// -// 0: PC Sampling event disabled. -// 1: Sampling event enabled. -#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 -#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 -#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 -#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 - -// Field: [11:10] SYNCTAP -// -// Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA -// must also be enabled for this feature. -// Synchronization packets (if enabled) are generated on tap transitions (0 to1 -// or 1 to 0). -// ENUMs: -// BIT28 Tap at bit 28 of CYCCNT -// BIT26 Tap at bit 26 of CYCCNT -// BIT24 Tap at bit 24 of CYCCNT -// DIS Disabled. No synchronization packets -#define CPU_DWT_CTRL_SYNCTAP_W 2 -#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 -#define CPU_DWT_CTRL_SYNCTAP_S 10 -#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 -#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 -#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 -#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 - -// Field: [9] CYCTAP -// -// Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the -// selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the -// POSTCNT, post-scalar counter. That counter then counts down. On a bit change -// when post-scalar is 0, it triggers an event for PC sampling or cycle count -// event (see details in CYCEVTENA). -// ENUMs: -// BIT10 Selects bit [10] to tap -// BIT6 Selects bit [6] to tap -#define CPU_DWT_CTRL_CYCTAP 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_BITN 9 -#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_S 9 -#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 - -// Field: [8:5] POSTCNT -// -// Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 -// to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it -// triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the -// value from POSTPRESET. -#define CPU_DWT_CTRL_POSTCNT_W 4 -#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 -#define CPU_DWT_CTRL_POSTCNT_S 5 - -// Field: [4:1] POSTPRESET -// -// Reload value for post-scalar counter POSTCNT. When 0, events are triggered -// on each tap change (a power of 2). If this field has a non-0 value, it forms -// a count-down value, to be reloaded into POSTCNT each time it reaches 0. For -// example, a value 1 in this register means an event is formed every other tap -// change. -#define CPU_DWT_CTRL_POSTPRESET_W 4 -#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E -#define CPU_DWT_CTRL_POSTPRESET_S 1 - -// Field: [0] CYCCNTENA -// -// Enable CYCCNT, allowing it to increment and generate synchronization and -// count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. -#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 -#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 -#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 -#define CPU_DWT_CTRL_CYCCNTENA_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_CYCCNT -// -//***************************************************************************** -// Field: [31:0] CYCCNT -// -// Current PC Sampler Cycle Counter count value. When enabled, this counter -// counts the number of core cycles, except when the core is halted. The cycle -// counter is a free running counter, counting upwards (this counter will not -// advance in power modes where free-running clock to CPU stops). It wraps -// around to 0 on overflow. The debugger must initialize this to 0 when first -// enabling. -#define CPU_DWT_CYCCNT_CYCCNT_W 32 -#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF -#define CPU_DWT_CYCCNT_CYCCNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_CPICNT -// -//***************************************************************************** -// Field: [7:0] CPICNT -// -// Current CPI counter value. Increments on the additional cycles (the first -// cycle is not counted) required to execute all instructions except those -// recorded by LSUCNT. This counter also increments on all instruction fetch -// stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter -// overflows. This counter initializes to 0 when it is enabled using -// CTRL.CPIEVTENA. -#define CPU_DWT_CPICNT_CPICNT_W 8 -#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF -#define CPU_DWT_CPICNT_CPICNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_EXCCNT -// -//***************************************************************************** -// Field: [7:0] EXCCNT -// -// Current interrupt overhead counter value. Counts the total cycles spent in -// interrupt processing (for example entry stacking, return unstacking, -// pre-emption). An event is emitted on counter overflow (every 256 cycles). -// This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. -#define CPU_DWT_EXCCNT_EXCCNT_W 8 -#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF -#define CPU_DWT_EXCCNT_EXCCNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_SLEEPCNT -// -//***************************************************************************** -// Field: [7:0] SLEEPCNT -// -// Sleep counter. Counts the number of cycles during which the processor is -// sleeping. An event is emitted on counter overflow (every 256 cycles). This -// counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note -// that the sleep counter is clocked using CPU's free-running clock. In some -// power modes the free-running clock to CPU is gated to minimize power -// consumption. This means that the sleep counter will be invalid in these -// power modes. -#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 -#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF -#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_LSUCNT -// -//***************************************************************************** -// Field: [7:0] LSUCNT -// -// LSU counter. This counts the total number of cycles that the processor is -// processing an LSU operation. The initial execution cost of the instruction -// is not counted. For example, an LDR that takes two cycles to complete -// increments this counter one cycle. Equivalently, an LDR that stalls for two -// cycles (i.e. takes four cycles to execute), increments this counter three -// times. An event is emitted on counter overflow (every 256 cycles). This -// counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. -#define CPU_DWT_LSUCNT_LSUCNT_W 8 -#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF -#define CPU_DWT_LSUCNT_LSUCNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_FOLDCNT -// -//***************************************************************************** -// Field: [7:0] FOLDCNT -// -// This counts the total number folded instructions. This counter initializes -// to 0 when it is enabled using CTRL.FOLDEVTENA. -#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 -#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF -#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_PCSR -// -//***************************************************************************** -// Field: [31:0] EIASAMPLE -// -// Execution instruction address sample, or 0xFFFFFFFF if the core is halted. -#define CPU_DWT_PCSR_EIASAMPLE_W 32 -#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF -#define CPU_DWT_PCSR_EIASAMPLE_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_COMP0 -// -//***************************************************************************** -// Field: [31:0] COMP -// -// Reference value to compare against PC or the data address as given by -// FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler -// Counter (CYCCNT). -#define CPU_DWT_COMP0_COMP_W 32 -#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP0_COMP_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_MASK0 -// -//***************************************************************************** -// Field: [3:0] MASK -// -// Mask on data address when matching against COMP0. This is the size of the -// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF -// left bit-shifted by MASK)) == COMP0. However, the actual comparison is -// slightly more complex to enable matching an address wherever it appears on a -// bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be -// within the word. -#define CPU_DWT_MASK0_MASK_W 4 -#define CPU_DWT_MASK0_MASK_M 0x0000000F -#define CPU_DWT_MASK0_MASK_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_FUNCTION0 -// -//***************************************************************************** -// Field: [24] MATCHED -// -// This bit is set when the comparator matches, and indicates that the -// operation defined by FUNCTION has occurred since this bit was last read. -// This bit is cleared on read. -#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION0_MATCHED_S 24 - -// Field: [7] CYCMATCH -// -// This bit is only available in comparator 0. When set, COMP0 will compare -// against the cycle counter (CYCCNT). -#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 -#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 -#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 -#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 - -// Field: [5] EMITRANGE -// -// Emit range field. This bit permits emitting offset when range match occurs. -// PC sampling is not supported when emit range is enabled. -// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 - -// Field: [3:0] FUNCTION -// -// Function settings. -// -// 0x0: Disabled -// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit -// address offset through ITM -// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, -// emit data and address offset through ITM on read or write. -// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. -// EMITRANGE = 1, emit address offset and data value through ITM on read or -// write. -// 0x4: Watchpoint on PC match. -// 0x5: Watchpoint on read. -// 0x6: Watchpoint on write. -// 0x7: Watchpoint on read or write. -// 0x8: ETM trigger on PC match -// 0x9: ETM trigger on read -// 0xA: ETM trigger on write -// 0xB: ETM trigger on read or write -// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for read transfers -// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for write transfers -// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for read transfers -// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for write transfers -// -// Note 1: If the ETM is not fitted, then ETM trigger is not possible. -// Note 2: Data value is only sampled for accesses that do not fault (MPU or -// bus fault). The PC is sampled irrespective of any faults. The PC is only -// sampled for the first address of a burst. -// Note 3: PC match is not recommended for watchpoints because it stops after -// the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION0_FUNCTION_W 4 -#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION0_FUNCTION_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_COMP1 -// -//***************************************************************************** -// Field: [31:0] COMP -// -// Reference value to compare against PC or the data address as given by -// FUNCTION1. -// Comparator 1 can also compare data values. So this register can contain -// reference values for data matching. -#define CPU_DWT_COMP1_COMP_W 32 -#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP1_COMP_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_MASK1 -// -//***************************************************************************** -// Field: [3:0] MASK -// -// Mask on data address when matching against COMP1. This is the size of the -// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF -// left bit-shifted by MASK)) == COMP1. However, the actual comparison is -// slightly more complex to enable matching an address wherever it appears on a -// bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be -// within the word. -#define CPU_DWT_MASK1_MASK_W 4 -#define CPU_DWT_MASK1_MASK_M 0x0000000F -#define CPU_DWT_MASK1_MASK_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_FUNCTION1 -// -//***************************************************************************** -// Field: [24] MATCHED -// -// This bit is set when the comparator matches, and indicates that the -// operation defined by FUNCTION has occurred since this bit was last read. -// This bit is cleared on read. -#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION1_MATCHED_S 24 - -// Field: [19:16] DATAVADDR1 -// -// Identity of a second linked address comparator for data value matching when -// DATAVMATCH == 1 and LNK1ENA == 1. -#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 -#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 -#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 - -// Field: [15:12] DATAVADDR0 -// -// Identity of a linked address comparator for data value matching when -// DATAVMATCH == 1. -#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 -#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 -#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 - -// Field: [11:10] DATAVSIZE -// -// Defines the size of the data in the COMP1 register that is to be matched: -// -// 0x0: Byte -// 0x1: Halfword -// 0x2: Word -// 0x3: Unpredictable. -#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 -#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 -#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 - -// Field: [9] LNK1ENA -// -// Read only bit-field only supported in comparator 1. -// -// 0: DATAVADDR1 not supported -// 1: DATAVADDR1 supported (enabled) -#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 -#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 -#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 -#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 - -// Field: [8] DATAVMATCH -// -// Data match feature: -// -// 0: Perform address comparison -// 1: Perform data value compare. The comparators given by DATAVADDR0 and -// DATAVADDR1 provide the address for the data comparison. The FUNCTION setting -// for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and -// those comparators only provide the address match for the data comparison. -// -// This bit is only available in comparator 1. -#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 -#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 -#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 -#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 - -// Field: [5] EMITRANGE -// -// Emit range field. This bit permits emitting offset when range match occurs. -// PC sampling is not supported when emit range is enabled. -// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 - -// Field: [3:0] FUNCTION -// -// Function settings: -// -// 0x0: Disabled -// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit -// address offset through ITM -// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, -// emit data and address offset through ITM on read or write. -// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. -// EMITRANGE = 1, emit address offset and data value through ITM on read or -// write. -// 0x4: Watchpoint on PC match. -// 0x5: Watchpoint on read. -// 0x6: Watchpoint on write. -// 0x7: Watchpoint on read or write. -// 0x8: ETM trigger on PC match -// 0x9: ETM trigger on read -// 0xA: ETM trigger on write -// 0xB: ETM trigger on read or write -// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for read transfers -// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for write transfers -// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for read transfers -// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for write transfers -// -// Note 1: If the ETM is not fitted, then ETM trigger is not possible. -// Note 2: Data value is only sampled for accesses that do not fault (MPU or -// bus fault). The PC is sampled irrespective of any faults. The PC is only -// sampled for the first address of a burst. -// Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and -// DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 -// and DATAVADDR1 can then only perform address comparator matches for -// comparator 1 data matches. -// Note 4: If the data matching functionality is not included during -// implementation it is not possible to set DATAVADDR0, DATAVADDR1, or -// DATAVMATCH. This means that the data matching functionality is not available -// in the implementation. Test the availability of data matching by writing and -// reading DATAVMATCH. If it is not settable then data matching is unavailable. -// Note 5: PC match is not recommended for watchpoints because it stops after -// the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION1_FUNCTION_W 4 -#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION1_FUNCTION_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_COMP2 -// -//***************************************************************************** -// Field: [31:0] COMP -// -// Reference value to compare against PC or the data address as given by -// FUNCTION2. -#define CPU_DWT_COMP2_COMP_W 32 -#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP2_COMP_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_MASK2 -// -//***************************************************************************** -// Field: [3:0] MASK -// -// Mask on data address when matching against COMP2. This is the size of the -// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF -// left bit-shifted by MASK)) == COMP2. However, the actual comparison is -// slightly more complex to enable matching an address wherever it appears on a -// bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be -// within the word. -#define CPU_DWT_MASK2_MASK_W 4 -#define CPU_DWT_MASK2_MASK_M 0x0000000F -#define CPU_DWT_MASK2_MASK_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_FUNCTION2 -// -//***************************************************************************** -// Field: [24] MATCHED -// -// This bit is set when the comparator matches, and indicates that the -// operation defined by FUNCTION has occurred since this bit was last read. -// This bit is cleared on read. -#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION2_MATCHED_S 24 - -// Field: [5] EMITRANGE -// -// Emit range field. This bit permits emitting offset when range match occurs. -// PC sampling is not supported when emit range is enabled. -// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 - -// Field: [3:0] FUNCTION -// -// Function settings. -// -// 0x0: Disabled -// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit -// address offset through ITM -// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, -// emit data and address offset through ITM on read or write. -// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. -// EMITRANGE = 1, emit address offset and data value through ITM on read or -// write. -// 0x4: Watchpoint on PC match. -// 0x5: Watchpoint on read. -// 0x6: Watchpoint on write. -// 0x7: Watchpoint on read or write. -// 0x8: ETM trigger on PC match -// 0x9: ETM trigger on read -// 0xA: ETM trigger on write -// 0xB: ETM trigger on read or write -// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for read transfers -// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for write transfers -// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for read transfers -// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for write transfers -// -// Note 1: If the ETM is not fitted, then ETM trigger is not possible. -// Note 2: Data value is only sampled for accesses that do not fault (MPU or -// bus fault). The PC is sampled irrespective of any faults. The PC is only -// sampled for the first address of a burst. -// Note 3: PC match is not recommended for watchpoints because it stops after -// the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION2_FUNCTION_W 4 -#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION2_FUNCTION_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_COMP3 -// -//***************************************************************************** -// Field: [31:0] COMP -// -// Reference value to compare against PC or the data address as given by -// FUNCTION3. -#define CPU_DWT_COMP3_COMP_W 32 -#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP3_COMP_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_MASK3 -// -//***************************************************************************** -// Field: [3:0] MASK -// -// Mask on data address when matching against COMP3. This is the size of the -// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF -// left bit-shifted by MASK)) == COMP3. However, the actual comparison is -// slightly more complex to enable matching an address wherever it appears on a -// bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be -// within the word. -#define CPU_DWT_MASK3_MASK_W 4 -#define CPU_DWT_MASK3_MASK_M 0x0000000F -#define CPU_DWT_MASK3_MASK_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_FUNCTION3 -// -//***************************************************************************** -// Field: [24] MATCHED -// -// This bit is set when the comparator matches, and indicates that the -// operation defined by FUNCTION has occurred since this bit was last read. -// This bit is cleared on read. -#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION3_MATCHED_S 24 - -// Field: [5] EMITRANGE -// -// Emit range field. This bit permits emitting offset when range match occurs. -// PC sampling is not supported when emit range is enabled. -// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 - -// Field: [3:0] FUNCTION -// -// Function settings. -// -// 0x0: Disabled -// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit -// address offset through ITM -// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, -// emit data and address offset through ITM on read or write. -// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. -// EMITRANGE = 1, emit address offset and data value through ITM on read or -// write. -// 0x4: Watchpoint on PC match. -// 0x5: Watchpoint on read. -// 0x6: Watchpoint on write. -// 0x7: Watchpoint on read or write. -// 0x8: ETM trigger on PC match -// 0x9: ETM trigger on read -// 0xA: ETM trigger on write -// 0xB: ETM trigger on read or write -// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for read transfers -// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for write transfers -// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for read transfers -// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for write transfers -// -// Note 1: If the ETM is not fitted, then ETM trigger is not possible. -// Note 2: Data value is only sampled for accesses that do not fault (MPU or -// bus fault). The PC is sampled irrespective of any faults. The PC is only -// sampled for the first address of a burst. -// Note 3: PC match is not recommended for watchpoints because it stops after -// the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION3_FUNCTION_W 4 -#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION3_FUNCTION_S 0 - - -#endif // __CPU_DWT__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_cpu_fpb.h b/third_party/ti/devices/cc26x0/inc/hw_cpu_fpb.h deleted file mode 100644 index c37760f16..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_cpu_fpb.h +++ /dev/null @@ -1,443 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_fpb_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_FPB_H__ -#define __HW_CPU_FPB_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_FPB component -// -//***************************************************************************** -// Control -#define CPU_FPB_O_CTRL 0x00000000 - -// Remap -#define CPU_FPB_O_REMAP 0x00000004 - -// Comparator 0 -#define CPU_FPB_O_COMP0 0x00000008 - -// Comparator 1 -#define CPU_FPB_O_COMP1 0x0000000C - -// Comparator 2 -#define CPU_FPB_O_COMP2 0x00000010 - -// Comparator 3 -#define CPU_FPB_O_COMP3 0x00000014 - -// Comparator 4 -#define CPU_FPB_O_COMP4 0x00000018 - -// Comparator 5 -#define CPU_FPB_O_COMP5 0x0000001C - -// Comparator 6 -#define CPU_FPB_O_COMP6 0x00000020 - -// Comparator 7 -#define CPU_FPB_O_COMP7 0x00000024 - -//***************************************************************************** -// -// Register: CPU_FPB_O_CTRL -// -//***************************************************************************** -// Field: [13:12] NUM_CODE2 -// -// Number of full banks of code comparators, sixteen comparators per bank. -// Where less than sixteen code comparators are provided, the bank count is -// zero, and the number present indicated by NUM_CODE1. This read only field -// contains 3'b000 to indicate 0 banks for Cortex-M processor. -#define CPU_FPB_CTRL_NUM_CODE2_W 2 -#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 -#define CPU_FPB_CTRL_NUM_CODE2_S 12 - -// Field: [11:8] NUM_LIT -// -// Number of literal slots field. -// -// 0x0: No literal slots -// 0x2: Two literal slots -#define CPU_FPB_CTRL_NUM_LIT_W 4 -#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 -#define CPU_FPB_CTRL_NUM_LIT_S 8 - -// Field: [7:4] NUM_CODE1 -// -// Number of code slots field. -// -// 0x0: No code slots -// 0x2: Two code slots -// 0x6: Six code slots -#define CPU_FPB_CTRL_NUM_CODE1_W 4 -#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 -#define CPU_FPB_CTRL_NUM_CODE1_S 4 - -// Field: [1] KEY -// -// Key field. In order to write to this register, this bit-field must be -// written to '1'. This bit always reads 0. -#define CPU_FPB_CTRL_KEY 0x00000002 -#define CPU_FPB_CTRL_KEY_BITN 1 -#define CPU_FPB_CTRL_KEY_M 0x00000002 -#define CPU_FPB_CTRL_KEY_S 1 - -// Field: [0] ENABLE -// -// Flash patch unit enable bit -// -// 0x0: Flash patch unit disabled -// 0x1: Flash patch unit enabled -#define CPU_FPB_CTRL_ENABLE 0x00000001 -#define CPU_FPB_CTRL_ENABLE_BITN 0 -#define CPU_FPB_CTRL_ENABLE_M 0x00000001 -#define CPU_FPB_CTRL_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_REMAP -// -//***************************************************************************** -// Field: [28:5] REMAP -// -// Remap base address field. -#define CPU_FPB_REMAP_REMAP_W 24 -#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 -#define CPU_FPB_REMAP_REMAP_S 5 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP0 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP0_REPLACE_W 2 -#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP0_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP0_COMP_W 27 -#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP0_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 0. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 0 disabled -// 0x1: Compare and remap for comparator 0 enabled -#define CPU_FPB_COMP0_ENABLE 0x00000001 -#define CPU_FPB_COMP0_ENABLE_BITN 0 -#define CPU_FPB_COMP0_ENABLE_M 0x00000001 -#define CPU_FPB_COMP0_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP1 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP1_REPLACE_W 2 -#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP1_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP1_COMP_W 27 -#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP1_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 1. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 1 disabled -// 0x1: Compare and remap for comparator 1 enabled -#define CPU_FPB_COMP1_ENABLE 0x00000001 -#define CPU_FPB_COMP1_ENABLE_BITN 0 -#define CPU_FPB_COMP1_ENABLE_M 0x00000001 -#define CPU_FPB_COMP1_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP2 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP2_REPLACE_W 2 -#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP2_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP2_COMP_W 27 -#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP2_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 2. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 2 disabled -// 0x1: Compare and remap for comparator 2 enabled -#define CPU_FPB_COMP2_ENABLE 0x00000001 -#define CPU_FPB_COMP2_ENABLE_BITN 0 -#define CPU_FPB_COMP2_ENABLE_M 0x00000001 -#define CPU_FPB_COMP2_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP3 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP3_REPLACE_W 2 -#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP3_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP3_COMP_W 27 -#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP3_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 3. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 3 disabled -// 0x1: Compare and remap for comparator 3 enabled -#define CPU_FPB_COMP3_ENABLE 0x00000001 -#define CPU_FPB_COMP3_ENABLE_BITN 0 -#define CPU_FPB_COMP3_ENABLE_M 0x00000001 -#define CPU_FPB_COMP3_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP4 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP4_REPLACE_W 2 -#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP4_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP4_COMP_W 27 -#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP4_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 4. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 4 disabled -// 0x1: Compare and remap for comparator 4 enabled -#define CPU_FPB_COMP4_ENABLE 0x00000001 -#define CPU_FPB_COMP4_ENABLE_BITN 0 -#define CPU_FPB_COMP4_ENABLE_M 0x00000001 -#define CPU_FPB_COMP4_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP5 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP5_REPLACE_W 2 -#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP5_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP5_COMP_W 27 -#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP5_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 5. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 5 disabled -// 0x1: Compare and remap for comparator 5 enabled -#define CPU_FPB_COMP5_ENABLE 0x00000001 -#define CPU_FPB_COMP5_ENABLE_BITN 0 -#define CPU_FPB_COMP5_ENABLE_M 0x00000001 -#define CPU_FPB_COMP5_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP6 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Comparator 6 is -// a literal comparator and the only supported setting is 0x0. Other settings -// will be ignored. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP6_REPLACE_W 2 -#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP6_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP6_COMP_W 27 -#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP6_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 6. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 6 disabled -// 0x1: Compare and remap for comparator 6 enabled -#define CPU_FPB_COMP6_ENABLE 0x00000001 -#define CPU_FPB_COMP6_ENABLE_BITN 0 -#define CPU_FPB_COMP6_ENABLE_M 0x00000001 -#define CPU_FPB_COMP6_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP7 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Comparator 7 is -// a literal comparator and the only supported setting is 0x0. Other settings -// will be ignored. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP7_REPLACE_W 2 -#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP7_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP7_COMP_W 27 -#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP7_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 7. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 7 disabled -// 0x1: Compare and remap for comparator 7 enabled -#define CPU_FPB_COMP7_ENABLE 0x00000001 -#define CPU_FPB_COMP7_ENABLE_BITN 0 -#define CPU_FPB_COMP7_ENABLE_M 0x00000001 -#define CPU_FPB_COMP7_ENABLE_S 0 - - -#endif // __CPU_FPB__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_cpu_itm.h b/third_party/ti/devices/cc26x0/inc/hw_cpu_itm.h deleted file mode 100644 index 09f044627..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_cpu_itm.h +++ /dev/null @@ -1,1122 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_itm_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_ITM_H__ -#define __HW_CPU_ITM_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_ITM component -// -//***************************************************************************** -// Stimulus Port 0 -#define CPU_ITM_O_STIM0 0x00000000 - -// Stimulus Port 1 -#define CPU_ITM_O_STIM1 0x00000004 - -// Stimulus Port 2 -#define CPU_ITM_O_STIM2 0x00000008 - -// Stimulus Port 3 -#define CPU_ITM_O_STIM3 0x0000000C - -// Stimulus Port 4 -#define CPU_ITM_O_STIM4 0x00000010 - -// Stimulus Port 5 -#define CPU_ITM_O_STIM5 0x00000014 - -// Stimulus Port 6 -#define CPU_ITM_O_STIM6 0x00000018 - -// Stimulus Port 7 -#define CPU_ITM_O_STIM7 0x0000001C - -// Stimulus Port 8 -#define CPU_ITM_O_STIM8 0x00000020 - -// Stimulus Port 9 -#define CPU_ITM_O_STIM9 0x00000024 - -// Stimulus Port 10 -#define CPU_ITM_O_STIM10 0x00000028 - -// Stimulus Port 11 -#define CPU_ITM_O_STIM11 0x0000002C - -// Stimulus Port 12 -#define CPU_ITM_O_STIM12 0x00000030 - -// Stimulus Port 13 -#define CPU_ITM_O_STIM13 0x00000034 - -// Stimulus Port 14 -#define CPU_ITM_O_STIM14 0x00000038 - -// Stimulus Port 15 -#define CPU_ITM_O_STIM15 0x0000003C - -// Stimulus Port 16 -#define CPU_ITM_O_STIM16 0x00000040 - -// Stimulus Port 17 -#define CPU_ITM_O_STIM17 0x00000044 - -// Stimulus Port 18 -#define CPU_ITM_O_STIM18 0x00000048 - -// Stimulus Port 19 -#define CPU_ITM_O_STIM19 0x0000004C - -// Stimulus Port 20 -#define CPU_ITM_O_STIM20 0x00000050 - -// Stimulus Port 21 -#define CPU_ITM_O_STIM21 0x00000054 - -// Stimulus Port 22 -#define CPU_ITM_O_STIM22 0x00000058 - -// Stimulus Port 23 -#define CPU_ITM_O_STIM23 0x0000005C - -// Stimulus Port 24 -#define CPU_ITM_O_STIM24 0x00000060 - -// Stimulus Port 25 -#define CPU_ITM_O_STIM25 0x00000064 - -// Stimulus Port 26 -#define CPU_ITM_O_STIM26 0x00000068 - -// Stimulus Port 27 -#define CPU_ITM_O_STIM27 0x0000006C - -// Stimulus Port 28 -#define CPU_ITM_O_STIM28 0x00000070 - -// Stimulus Port 29 -#define CPU_ITM_O_STIM29 0x00000074 - -// Stimulus Port 30 -#define CPU_ITM_O_STIM30 0x00000078 - -// Stimulus Port 31 -#define CPU_ITM_O_STIM31 0x0000007C - -// Trace Enable -#define CPU_ITM_O_TER 0x00000E00 - -// Trace Privilege -#define CPU_ITM_O_TPR 0x00000E40 - -// Trace Control -#define CPU_ITM_O_TCR 0x00000E80 - -// Lock Access -#define CPU_ITM_O_LAR 0x00000FB0 - -// Lock Status -#define CPU_ITM_O_LSR 0x00000FB4 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM0 -// -//***************************************************************************** -// Field: [31:0] STIM0 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM0_STIM0_W 32 -#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF -#define CPU_ITM_STIM0_STIM0_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM1 -// -//***************************************************************************** -// Field: [31:0] STIM1 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM1_STIM1_W 32 -#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF -#define CPU_ITM_STIM1_STIM1_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM2 -// -//***************************************************************************** -// Field: [31:0] STIM2 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM2_STIM2_W 32 -#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF -#define CPU_ITM_STIM2_STIM2_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM3 -// -//***************************************************************************** -// Field: [31:0] STIM3 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM3_STIM3_W 32 -#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF -#define CPU_ITM_STIM3_STIM3_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM4 -// -//***************************************************************************** -// Field: [31:0] STIM4 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM4_STIM4_W 32 -#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF -#define CPU_ITM_STIM4_STIM4_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM5 -// -//***************************************************************************** -// Field: [31:0] STIM5 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM5_STIM5_W 32 -#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF -#define CPU_ITM_STIM5_STIM5_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM6 -// -//***************************************************************************** -// Field: [31:0] STIM6 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM6_STIM6_W 32 -#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF -#define CPU_ITM_STIM6_STIM6_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM7 -// -//***************************************************************************** -// Field: [31:0] STIM7 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM7_STIM7_W 32 -#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF -#define CPU_ITM_STIM7_STIM7_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM8 -// -//***************************************************************************** -// Field: [31:0] STIM8 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM8_STIM8_W 32 -#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF -#define CPU_ITM_STIM8_STIM8_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM9 -// -//***************************************************************************** -// Field: [31:0] STIM9 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM9_STIM9_W 32 -#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF -#define CPU_ITM_STIM9_STIM9_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM10 -// -//***************************************************************************** -// Field: [31:0] STIM10 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM10_STIM10_W 32 -#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF -#define CPU_ITM_STIM10_STIM10_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM11 -// -//***************************************************************************** -// Field: [31:0] STIM11 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM11_STIM11_W 32 -#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF -#define CPU_ITM_STIM11_STIM11_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM12 -// -//***************************************************************************** -// Field: [31:0] STIM12 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM12_STIM12_W 32 -#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF -#define CPU_ITM_STIM12_STIM12_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM13 -// -//***************************************************************************** -// Field: [31:0] STIM13 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM13_STIM13_W 32 -#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF -#define CPU_ITM_STIM13_STIM13_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM14 -// -//***************************************************************************** -// Field: [31:0] STIM14 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM14_STIM14_W 32 -#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF -#define CPU_ITM_STIM14_STIM14_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM15 -// -//***************************************************************************** -// Field: [31:0] STIM15 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM15_STIM15_W 32 -#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF -#define CPU_ITM_STIM15_STIM15_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM16 -// -//***************************************************************************** -// Field: [31:0] STIM16 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM16_STIM16_W 32 -#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF -#define CPU_ITM_STIM16_STIM16_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM17 -// -//***************************************************************************** -// Field: [31:0] STIM17 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM17_STIM17_W 32 -#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF -#define CPU_ITM_STIM17_STIM17_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM18 -// -//***************************************************************************** -// Field: [31:0] STIM18 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM18_STIM18_W 32 -#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF -#define CPU_ITM_STIM18_STIM18_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM19 -// -//***************************************************************************** -// Field: [31:0] STIM19 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM19_STIM19_W 32 -#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF -#define CPU_ITM_STIM19_STIM19_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM20 -// -//***************************************************************************** -// Field: [31:0] STIM20 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM20_STIM20_W 32 -#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF -#define CPU_ITM_STIM20_STIM20_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM21 -// -//***************************************************************************** -// Field: [31:0] STIM21 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM21_STIM21_W 32 -#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF -#define CPU_ITM_STIM21_STIM21_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM22 -// -//***************************************************************************** -// Field: [31:0] STIM22 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM22_STIM22_W 32 -#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF -#define CPU_ITM_STIM22_STIM22_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM23 -// -//***************************************************************************** -// Field: [31:0] STIM23 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM23_STIM23_W 32 -#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF -#define CPU_ITM_STIM23_STIM23_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM24 -// -//***************************************************************************** -// Field: [31:0] STIM24 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM24_STIM24_W 32 -#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF -#define CPU_ITM_STIM24_STIM24_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM25 -// -//***************************************************************************** -// Field: [31:0] STIM25 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM25_STIM25_W 32 -#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF -#define CPU_ITM_STIM25_STIM25_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM26 -// -//***************************************************************************** -// Field: [31:0] STIM26 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM26_STIM26_W 32 -#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF -#define CPU_ITM_STIM26_STIM26_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM27 -// -//***************************************************************************** -// Field: [31:0] STIM27 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM27_STIM27_W 32 -#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF -#define CPU_ITM_STIM27_STIM27_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM28 -// -//***************************************************************************** -// Field: [31:0] STIM28 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM28_STIM28_W 32 -#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF -#define CPU_ITM_STIM28_STIM28_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM29 -// -//***************************************************************************** -// Field: [31:0] STIM29 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM29_STIM29_W 32 -#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF -#define CPU_ITM_STIM29_STIM29_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM30 -// -//***************************************************************************** -// Field: [31:0] STIM30 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM30_STIM30_W 32 -#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF -#define CPU_ITM_STIM30_STIM30_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM31 -// -//***************************************************************************** -// Field: [31:0] STIM31 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM31_STIM31_W 32 -#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF -#define CPU_ITM_STIM31_STIM31_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_TER -// -//***************************************************************************** -// Field: [31] STIMENA31 -// -// Bit mask to enable tracing on ITM stimulus port 31. -#define CPU_ITM_TER_STIMENA31 0x80000000 -#define CPU_ITM_TER_STIMENA31_BITN 31 -#define CPU_ITM_TER_STIMENA31_M 0x80000000 -#define CPU_ITM_TER_STIMENA31_S 31 - -// Field: [30] STIMENA30 -// -// Bit mask to enable tracing on ITM stimulus port 30. -#define CPU_ITM_TER_STIMENA30 0x40000000 -#define CPU_ITM_TER_STIMENA30_BITN 30 -#define CPU_ITM_TER_STIMENA30_M 0x40000000 -#define CPU_ITM_TER_STIMENA30_S 30 - -// Field: [29] STIMENA29 -// -// Bit mask to enable tracing on ITM stimulus port 29. -#define CPU_ITM_TER_STIMENA29 0x20000000 -#define CPU_ITM_TER_STIMENA29_BITN 29 -#define CPU_ITM_TER_STIMENA29_M 0x20000000 -#define CPU_ITM_TER_STIMENA29_S 29 - -// Field: [28] STIMENA28 -// -// Bit mask to enable tracing on ITM stimulus port 28. -#define CPU_ITM_TER_STIMENA28 0x10000000 -#define CPU_ITM_TER_STIMENA28_BITN 28 -#define CPU_ITM_TER_STIMENA28_M 0x10000000 -#define CPU_ITM_TER_STIMENA28_S 28 - -// Field: [27] STIMENA27 -// -// Bit mask to enable tracing on ITM stimulus port 27. -#define CPU_ITM_TER_STIMENA27 0x08000000 -#define CPU_ITM_TER_STIMENA27_BITN 27 -#define CPU_ITM_TER_STIMENA27_M 0x08000000 -#define CPU_ITM_TER_STIMENA27_S 27 - -// Field: [26] STIMENA26 -// -// Bit mask to enable tracing on ITM stimulus port 26. -#define CPU_ITM_TER_STIMENA26 0x04000000 -#define CPU_ITM_TER_STIMENA26_BITN 26 -#define CPU_ITM_TER_STIMENA26_M 0x04000000 -#define CPU_ITM_TER_STIMENA26_S 26 - -// Field: [25] STIMENA25 -// -// Bit mask to enable tracing on ITM stimulus port 25. -#define CPU_ITM_TER_STIMENA25 0x02000000 -#define CPU_ITM_TER_STIMENA25_BITN 25 -#define CPU_ITM_TER_STIMENA25_M 0x02000000 -#define CPU_ITM_TER_STIMENA25_S 25 - -// Field: [24] STIMENA24 -// -// Bit mask to enable tracing on ITM stimulus port 24. -#define CPU_ITM_TER_STIMENA24 0x01000000 -#define CPU_ITM_TER_STIMENA24_BITN 24 -#define CPU_ITM_TER_STIMENA24_M 0x01000000 -#define CPU_ITM_TER_STIMENA24_S 24 - -// Field: [23] STIMENA23 -// -// Bit mask to enable tracing on ITM stimulus port 23. -#define CPU_ITM_TER_STIMENA23 0x00800000 -#define CPU_ITM_TER_STIMENA23_BITN 23 -#define CPU_ITM_TER_STIMENA23_M 0x00800000 -#define CPU_ITM_TER_STIMENA23_S 23 - -// Field: [22] STIMENA22 -// -// Bit mask to enable tracing on ITM stimulus port 22. -#define CPU_ITM_TER_STIMENA22 0x00400000 -#define CPU_ITM_TER_STIMENA22_BITN 22 -#define CPU_ITM_TER_STIMENA22_M 0x00400000 -#define CPU_ITM_TER_STIMENA22_S 22 - -// Field: [21] STIMENA21 -// -// Bit mask to enable tracing on ITM stimulus port 21. -#define CPU_ITM_TER_STIMENA21 0x00200000 -#define CPU_ITM_TER_STIMENA21_BITN 21 -#define CPU_ITM_TER_STIMENA21_M 0x00200000 -#define CPU_ITM_TER_STIMENA21_S 21 - -// Field: [20] STIMENA20 -// -// Bit mask to enable tracing on ITM stimulus port 20. -#define CPU_ITM_TER_STIMENA20 0x00100000 -#define CPU_ITM_TER_STIMENA20_BITN 20 -#define CPU_ITM_TER_STIMENA20_M 0x00100000 -#define CPU_ITM_TER_STIMENA20_S 20 - -// Field: [19] STIMENA19 -// -// Bit mask to enable tracing on ITM stimulus port 19. -#define CPU_ITM_TER_STIMENA19 0x00080000 -#define CPU_ITM_TER_STIMENA19_BITN 19 -#define CPU_ITM_TER_STIMENA19_M 0x00080000 -#define CPU_ITM_TER_STIMENA19_S 19 - -// Field: [18] STIMENA18 -// -// Bit mask to enable tracing on ITM stimulus port 18. -#define CPU_ITM_TER_STIMENA18 0x00040000 -#define CPU_ITM_TER_STIMENA18_BITN 18 -#define CPU_ITM_TER_STIMENA18_M 0x00040000 -#define CPU_ITM_TER_STIMENA18_S 18 - -// Field: [17] STIMENA17 -// -// Bit mask to enable tracing on ITM stimulus port 17. -#define CPU_ITM_TER_STIMENA17 0x00020000 -#define CPU_ITM_TER_STIMENA17_BITN 17 -#define CPU_ITM_TER_STIMENA17_M 0x00020000 -#define CPU_ITM_TER_STIMENA17_S 17 - -// Field: [16] STIMENA16 -// -// Bit mask to enable tracing on ITM stimulus port 16. -#define CPU_ITM_TER_STIMENA16 0x00010000 -#define CPU_ITM_TER_STIMENA16_BITN 16 -#define CPU_ITM_TER_STIMENA16_M 0x00010000 -#define CPU_ITM_TER_STIMENA16_S 16 - -// Field: [15] STIMENA15 -// -// Bit mask to enable tracing on ITM stimulus port 15. -#define CPU_ITM_TER_STIMENA15 0x00008000 -#define CPU_ITM_TER_STIMENA15_BITN 15 -#define CPU_ITM_TER_STIMENA15_M 0x00008000 -#define CPU_ITM_TER_STIMENA15_S 15 - -// Field: [14] STIMENA14 -// -// Bit mask to enable tracing on ITM stimulus port 14. -#define CPU_ITM_TER_STIMENA14 0x00004000 -#define CPU_ITM_TER_STIMENA14_BITN 14 -#define CPU_ITM_TER_STIMENA14_M 0x00004000 -#define CPU_ITM_TER_STIMENA14_S 14 - -// Field: [13] STIMENA13 -// -// Bit mask to enable tracing on ITM stimulus port 13. -#define CPU_ITM_TER_STIMENA13 0x00002000 -#define CPU_ITM_TER_STIMENA13_BITN 13 -#define CPU_ITM_TER_STIMENA13_M 0x00002000 -#define CPU_ITM_TER_STIMENA13_S 13 - -// Field: [12] STIMENA12 -// -// Bit mask to enable tracing on ITM stimulus port 12. -#define CPU_ITM_TER_STIMENA12 0x00001000 -#define CPU_ITM_TER_STIMENA12_BITN 12 -#define CPU_ITM_TER_STIMENA12_M 0x00001000 -#define CPU_ITM_TER_STIMENA12_S 12 - -// Field: [11] STIMENA11 -// -// Bit mask to enable tracing on ITM stimulus port 11. -#define CPU_ITM_TER_STIMENA11 0x00000800 -#define CPU_ITM_TER_STIMENA11_BITN 11 -#define CPU_ITM_TER_STIMENA11_M 0x00000800 -#define CPU_ITM_TER_STIMENA11_S 11 - -// Field: [10] STIMENA10 -// -// Bit mask to enable tracing on ITM stimulus port 10. -#define CPU_ITM_TER_STIMENA10 0x00000400 -#define CPU_ITM_TER_STIMENA10_BITN 10 -#define CPU_ITM_TER_STIMENA10_M 0x00000400 -#define CPU_ITM_TER_STIMENA10_S 10 - -// Field: [9] STIMENA9 -// -// Bit mask to enable tracing on ITM stimulus port 9. -#define CPU_ITM_TER_STIMENA9 0x00000200 -#define CPU_ITM_TER_STIMENA9_BITN 9 -#define CPU_ITM_TER_STIMENA9_M 0x00000200 -#define CPU_ITM_TER_STIMENA9_S 9 - -// Field: [8] STIMENA8 -// -// Bit mask to enable tracing on ITM stimulus port 8. -#define CPU_ITM_TER_STIMENA8 0x00000100 -#define CPU_ITM_TER_STIMENA8_BITN 8 -#define CPU_ITM_TER_STIMENA8_M 0x00000100 -#define CPU_ITM_TER_STIMENA8_S 8 - -// Field: [7] STIMENA7 -// -// Bit mask to enable tracing on ITM stimulus port 7. -#define CPU_ITM_TER_STIMENA7 0x00000080 -#define CPU_ITM_TER_STIMENA7_BITN 7 -#define CPU_ITM_TER_STIMENA7_M 0x00000080 -#define CPU_ITM_TER_STIMENA7_S 7 - -// Field: [6] STIMENA6 -// -// Bit mask to enable tracing on ITM stimulus port 6. -#define CPU_ITM_TER_STIMENA6 0x00000040 -#define CPU_ITM_TER_STIMENA6_BITN 6 -#define CPU_ITM_TER_STIMENA6_M 0x00000040 -#define CPU_ITM_TER_STIMENA6_S 6 - -// Field: [5] STIMENA5 -// -// Bit mask to enable tracing on ITM stimulus port 5. -#define CPU_ITM_TER_STIMENA5 0x00000020 -#define CPU_ITM_TER_STIMENA5_BITN 5 -#define CPU_ITM_TER_STIMENA5_M 0x00000020 -#define CPU_ITM_TER_STIMENA5_S 5 - -// Field: [4] STIMENA4 -// -// Bit mask to enable tracing on ITM stimulus port 4. -#define CPU_ITM_TER_STIMENA4 0x00000010 -#define CPU_ITM_TER_STIMENA4_BITN 4 -#define CPU_ITM_TER_STIMENA4_M 0x00000010 -#define CPU_ITM_TER_STIMENA4_S 4 - -// Field: [3] STIMENA3 -// -// Bit mask to enable tracing on ITM stimulus port 3. -#define CPU_ITM_TER_STIMENA3 0x00000008 -#define CPU_ITM_TER_STIMENA3_BITN 3 -#define CPU_ITM_TER_STIMENA3_M 0x00000008 -#define CPU_ITM_TER_STIMENA3_S 3 - -// Field: [2] STIMENA2 -// -// Bit mask to enable tracing on ITM stimulus port 2. -#define CPU_ITM_TER_STIMENA2 0x00000004 -#define CPU_ITM_TER_STIMENA2_BITN 2 -#define CPU_ITM_TER_STIMENA2_M 0x00000004 -#define CPU_ITM_TER_STIMENA2_S 2 - -// Field: [1] STIMENA1 -// -// Bit mask to enable tracing on ITM stimulus port 1. -#define CPU_ITM_TER_STIMENA1 0x00000002 -#define CPU_ITM_TER_STIMENA1_BITN 1 -#define CPU_ITM_TER_STIMENA1_M 0x00000002 -#define CPU_ITM_TER_STIMENA1_S 1 - -// Field: [0] STIMENA0 -// -// Bit mask to enable tracing on ITM stimulus port 0. -#define CPU_ITM_TER_STIMENA0 0x00000001 -#define CPU_ITM_TER_STIMENA0_BITN 0 -#define CPU_ITM_TER_STIMENA0_M 0x00000001 -#define CPU_ITM_TER_STIMENA0_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_TPR -// -//***************************************************************************** -// Field: [3:0] PRIVMASK -// -// Bit mask to enable unprivileged (User) access to ITM stimulus ports: -// -// Bit [0] enables stimulus ports 0, 1, ..., and 7. -// Bit [1] enables stimulus ports 8, 9, ..., and 15. -// Bit [2] enables stimulus ports 16, 17, ..., and 23. -// Bit [3] enables stimulus ports 24, 25, ..., and 31. -// -// 0: User access allowed to stimulus ports -// 1: Privileged access only to stimulus ports -#define CPU_ITM_TPR_PRIVMASK_W 4 -#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F -#define CPU_ITM_TPR_PRIVMASK_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_TCR -// -//***************************************************************************** -// Field: [23] BUSY -// -// Set when ITM events present and being drained. -#define CPU_ITM_TCR_BUSY 0x00800000 -#define CPU_ITM_TCR_BUSY_BITN 23 -#define CPU_ITM_TCR_BUSY_M 0x00800000 -#define CPU_ITM_TCR_BUSY_S 23 - -// Field: [22:16] ATBID -// -// Trace Bus ID for CoreSight system. Optional identifier for multi-source -// trace stream formatting. If multi-source trace is in use, this field must be -// written with a non-zero value. -#define CPU_ITM_TCR_ATBID_W 7 -#define CPU_ITM_TCR_ATBID_M 0x007F0000 -#define CPU_ITM_TCR_ATBID_S 16 - -// Field: [9:8] TSPRESCALE -// -// Timestamp prescaler -// ENUMs: -// DIV64 Divide by 64 -// DIV16 Divide by 16 -// DIV4 Divide by 4 -// NOPRESCALING No prescaling -#define CPU_ITM_TCR_TSPRESCALE_W 2 -#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 -#define CPU_ITM_TCR_TSPRESCALE_S 8 -#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 -#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 -#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 -#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 - -// Field: [4] SWOENA -// -// Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If -// TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of -// the timestamp counter. -// -// 0x0: Mode disabled. Timestamp counter uses system clock from the core and -// counts continuously. -// 0x1: Timestamp counter uses lineout (data related) clock from TPIU -// interface. The timestamp counter is held in reset while the output line is -// idle. -#define CPU_ITM_TCR_SWOENA 0x00000010 -#define CPU_ITM_TCR_SWOENA_BITN 4 -#define CPU_ITM_TCR_SWOENA_M 0x00000010 -#define CPU_ITM_TCR_SWOENA_S 4 - -// Field: [3] DWTENA -// -// Enables the DWT stimulus (hardware event packet emission to the TPIU from -// the DWT) -#define CPU_ITM_TCR_DWTENA 0x00000008 -#define CPU_ITM_TCR_DWTENA_BITN 3 -#define CPU_ITM_TCR_DWTENA_M 0x00000008 -#define CPU_ITM_TCR_DWTENA_S 3 - -// Field: [2] SYNCENA -// -// Enables synchronization packet transmission for a synchronous TPIU. -// CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization -// speed. -#define CPU_ITM_TCR_SYNCENA 0x00000004 -#define CPU_ITM_TCR_SYNCENA_BITN 2 -#define CPU_ITM_TCR_SYNCENA_M 0x00000004 -#define CPU_ITM_TCR_SYNCENA_S 2 - -// Field: [1] TSENA -// -// Enables differential timestamps. Differential timestamps are emitted when a -// packet is written to the FIFO with a non-zero timestamp counter, and when -// the timestamp counter overflows. Timestamps are emitted during idle times -// after a fixed number of two million cycles. This provides a time reference -// for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps -// are triggered by activity on the internal trace bus only. In this case there -// is no regular timestamp output when the ITM is idle. -#define CPU_ITM_TCR_TSENA 0x00000002 -#define CPU_ITM_TCR_TSENA_BITN 1 -#define CPU_ITM_TCR_TSENA_M 0x00000002 -#define CPU_ITM_TCR_TSENA_S 1 - -// Field: [0] ITMENA -// -// Enables ITM. This is the master enable, and must be set before ITM Stimulus -// and Trace Enable registers can be written. -#define CPU_ITM_TCR_ITMENA 0x00000001 -#define CPU_ITM_TCR_ITMENA_BITN 0 -#define CPU_ITM_TCR_ITMENA_M 0x00000001 -#define CPU_ITM_TCR_ITMENA_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_LAR -// -//***************************************************************************** -// Field: [31:0] LOCK_ACCESS -// -// A privileged write of 0xC5ACCE55 enables more write access to Control -// Registers TER, TPR and TCR. An invalid write removes write access. -#define CPU_ITM_LAR_LOCK_ACCESS_W 32 -#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF -#define CPU_ITM_LAR_LOCK_ACCESS_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_LSR -// -//***************************************************************************** -// Field: [2] BYTEACC -// -// Reads 0 which means 8-bit lock access is not be implemented. -#define CPU_ITM_LSR_BYTEACC 0x00000004 -#define CPU_ITM_LSR_BYTEACC_BITN 2 -#define CPU_ITM_LSR_BYTEACC_M 0x00000004 -#define CPU_ITM_LSR_BYTEACC_S 2 - -// Field: [1] ACCESS -// -// Write access to component is blocked. All writes are ignored, reads are -// permitted. -#define CPU_ITM_LSR_ACCESS 0x00000002 -#define CPU_ITM_LSR_ACCESS_BITN 1 -#define CPU_ITM_LSR_ACCESS_M 0x00000002 -#define CPU_ITM_LSR_ACCESS_S 1 - -// Field: [0] PRESENT -// -// Indicates that a lock mechanism exists for this component. -#define CPU_ITM_LSR_PRESENT 0x00000001 -#define CPU_ITM_LSR_PRESENT_BITN 0 -#define CPU_ITM_LSR_PRESENT_M 0x00000001 -#define CPU_ITM_LSR_PRESENT_S 0 - - -#endif // __CPU_ITM__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_cpu_rom_table.h b/third_party/ti/devices/cc26x0/inc/hw_cpu_rom_table.h deleted file mode 100644 index 6ab07aae6..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_cpu_rom_table.h +++ /dev/null @@ -1,220 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_rom_table_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_ROM_TABLE_H__ -#define __HW_CPU_ROM_TABLE_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_ROM_TABLE component -// -//***************************************************************************** -// System Control Space Component -#define CPU_ROM_TABLE_O_SCS 0x00000000 - -// Data Watchpoint and Trace Component -#define CPU_ROM_TABLE_O_DWT 0x00000004 - -// Flash Patch and Breakpoint Component -#define CPU_ROM_TABLE_O_FPB 0x00000008 - -// Instrumentation Trace Component -#define CPU_ROM_TABLE_O_ITM 0x0000000C - -// Trace Port Interface Component -#define CPU_ROM_TABLE_O_TPIU 0x00000010 - -// Enhanced Trace Component -#define CPU_ROM_TABLE_O_ETM 0x00000014 - -// End Marker -#define CPU_ROM_TABLE_O_END 0x00000018 - -// System Memory Map Access for DAP -#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_SCS -// -//***************************************************************************** -// Field: [31:0] SCS -// -// Points to the SCS at 0xE000E000. -// (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. -#define CPU_ROM_TABLE_SCS_SCS_W 32 -#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF -#define CPU_ROM_TABLE_SCS_SCS_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_DWT -// -//***************************************************************************** -// Field: [31:1] DWT -// -// Points to the Data Watchpoint and Trace block at 0xE0001000. -// (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. -#define CPU_ROM_TABLE_DWT_DWT_W 31 -#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE -#define CPU_ROM_TABLE_DWT_DWT_S 1 - -// Field: [0] DWT_PRESENT -// -// 0: DWT is not present -// 1: DWT is present. -#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_FPB -// -//***************************************************************************** -// Field: [31:1] FPB -// -// Points to the Flash Patch and Breakpoint block at 0xE0002000. -// (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. -#define CPU_ROM_TABLE_FPB_FPB_W 31 -#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE -#define CPU_ROM_TABLE_FPB_FPB_S 1 - -// Field: [0] FPB_PRESENT -// -// 0: FPB is not present -// 1: FPB is present. -#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_ITM -// -//***************************************************************************** -// Field: [31:1] ITM -// -// Points to the Instrumentation Trace block at 0xE0000000. -// (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. -#define CPU_ROM_TABLE_ITM_ITM_W 31 -#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE -#define CPU_ROM_TABLE_ITM_ITM_S 1 - -// Field: [0] ITM_PRESENT -// -// 0: ITM is not present -// 1: ITM is present. -#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_TPIU -// -//***************************************************************************** -// Field: [31:1] TPIU -// -// Points to the TPIU. TPIU is at 0xE0040000. -// (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. -#define CPU_ROM_TABLE_TPIU_TPIU_W 31 -#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE -#define CPU_ROM_TABLE_TPIU_TPIU_S 1 - -// Field: [0] TPIU_PRESENT -// -// 0: TPIU is not present -// 1: TPIU is present. -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_ETM -// -//***************************************************************************** -// Field: [31:1] ETM -// -// Points to the ETM. ETM is at 0xE0041000. -// (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. -#define CPU_ROM_TABLE_ETM_ETM_W 31 -#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE -#define CPU_ROM_TABLE_ETM_ETM_S 1 - -// Field: [0] ETM_PRESENT -// -// 0: ETM is not present -// 1: ETM is present. -#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_END -// -//***************************************************************************** -// Field: [31:0] END -// -// End of the ROM table -#define CPU_ROM_TABLE_END_END_W 32 -#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF -#define CPU_ROM_TABLE_END_END_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_SYSTEM_ACCESS -// -//***************************************************************************** -// Field: [0] SYSTEM_ACCESS -// -// 1: The system memory map is accessible using the DAP -// 0: Only debug resources are accessible using the DAP -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 - - -#endif // __CPU_ROM_TABLE__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_cpu_scs.h b/third_party/ti/devices/cc26x0/inc/hw_cpu_scs.h deleted file mode 100644 index fca2d59e4..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_cpu_scs.h +++ /dev/null @@ -1,3885 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_scs_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_SCS_H__ -#define __HW_CPU_SCS_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_SCS component -// -//***************************************************************************** -// Interrupt Control Type -#define CPU_SCS_O_ICTR 0x00000004 - -// Auxiliary Control -#define CPU_SCS_O_ACTLR 0x00000008 - -// SysTick Control and Status -#define CPU_SCS_O_STCSR 0x00000010 - -// SysTick Reload Value -#define CPU_SCS_O_STRVR 0x00000014 - -// SysTick Current Value -#define CPU_SCS_O_STCVR 0x00000018 - -// SysTick Calibration Value -#define CPU_SCS_O_STCR 0x0000001C - -// Irq 0 to 31 Set Enable -#define CPU_SCS_O_NVIC_ISER0 0x00000100 - -// Irq 32 to 63 Set Enable -#define CPU_SCS_O_NVIC_ISER1 0x00000104 - -// Irq 0 to 31 Clear Enable -#define CPU_SCS_O_NVIC_ICER0 0x00000180 - -// Irq 32 to 63 Clear Enable -#define CPU_SCS_O_NVIC_ICER1 0x00000184 - -// Irq 0 to 31 Set Pending -#define CPU_SCS_O_NVIC_ISPR0 0x00000200 - -// Irq 32 to 63 Set Pending -#define CPU_SCS_O_NVIC_ISPR1 0x00000204 - -// Irq 0 to 31 Clear Pending -#define CPU_SCS_O_NVIC_ICPR0 0x00000280 - -// Irq 32 to 63 Clear Pending -#define CPU_SCS_O_NVIC_ICPR1 0x00000284 - -// Irq 0 to 31 Active Bit -#define CPU_SCS_O_NVIC_IABR0 0x00000300 - -// Irq 32 to 63 Active Bit -#define CPU_SCS_O_NVIC_IABR1 0x00000304 - -// Irq 0 to 3 Priority -#define CPU_SCS_O_NVIC_IPR0 0x00000400 - -// Irq 4 to 7 Priority -#define CPU_SCS_O_NVIC_IPR1 0x00000404 - -// Irq 8 to 11 Priority -#define CPU_SCS_O_NVIC_IPR2 0x00000408 - -// Irq 12 to 15 Priority -#define CPU_SCS_O_NVIC_IPR3 0x0000040C - -// Irq 16 to 19 Priority -#define CPU_SCS_O_NVIC_IPR4 0x00000410 - -// Irq 20 to 23 Priority -#define CPU_SCS_O_NVIC_IPR5 0x00000414 - -// Irq 24 to 27 Priority -#define CPU_SCS_O_NVIC_IPR6 0x00000418 - -// Irq 28 to 31 Priority -#define CPU_SCS_O_NVIC_IPR7 0x0000041C - -// Irq 32 to 35 Priority -#define CPU_SCS_O_NVIC_IPR8 0x00000420 - -// CPUID Base -#define CPU_SCS_O_CPUID 0x00000D00 - -// Interrupt Control State -#define CPU_SCS_O_ICSR 0x00000D04 - -// Vector Table Offset -#define CPU_SCS_O_VTOR 0x00000D08 - -// Application Interrupt/Reset Control -#define CPU_SCS_O_AIRCR 0x00000D0C - -// System Control -#define CPU_SCS_O_SCR 0x00000D10 - -// Configuration Control -#define CPU_SCS_O_CCR 0x00000D14 - -// System Handlers 4-7 Priority -#define CPU_SCS_O_SHPR1 0x00000D18 - -// System Handlers 8-11 Priority -#define CPU_SCS_O_SHPR2 0x00000D1C - -// System Handlers 12-15 Priority -#define CPU_SCS_O_SHPR3 0x00000D20 - -// System Handler Control and State -#define CPU_SCS_O_SHCSR 0x00000D24 - -// Configurable Fault Status -#define CPU_SCS_O_CFSR 0x00000D28 - -// Hard Fault Status -#define CPU_SCS_O_HFSR 0x00000D2C - -// Debug Fault Status -#define CPU_SCS_O_DFSR 0x00000D30 - -// Mem Manage Fault Address -#define CPU_SCS_O_MMFAR 0x00000D34 - -// Bus Fault Address -#define CPU_SCS_O_BFAR 0x00000D38 - -// Auxiliary Fault Status -#define CPU_SCS_O_AFSR 0x00000D3C - -// Processor Feature 0 -#define CPU_SCS_O_ID_PFR0 0x00000D40 - -// Processor Feature 1 -#define CPU_SCS_O_ID_PFR1 0x00000D44 - -// Debug Feature 0 -#define CPU_SCS_O_ID_DFR0 0x00000D48 - -// Auxiliary Feature 0 -#define CPU_SCS_O_ID_AFR0 0x00000D4C - -// Memory Model Feature 0 -#define CPU_SCS_O_ID_MMFR0 0x00000D50 - -// Memory Model Feature 1 -#define CPU_SCS_O_ID_MMFR1 0x00000D54 - -// Memory Model Feature 2 -#define CPU_SCS_O_ID_MMFR2 0x00000D58 - -// Memory Model Feature 3 -#define CPU_SCS_O_ID_MMFR3 0x00000D5C - -// ISA Feature 0 -#define CPU_SCS_O_ID_ISAR0 0x00000D60 - -// ISA Feature 1 -#define CPU_SCS_O_ID_ISAR1 0x00000D64 - -// ISA Feature 2 -#define CPU_SCS_O_ID_ISAR2 0x00000D68 - -// ISA Feature 3 -#define CPU_SCS_O_ID_ISAR3 0x00000D6C - -// ISA Feature 4 -#define CPU_SCS_O_ID_ISAR4 0x00000D70 - -// Coprocessor Access Control -#define CPU_SCS_O_CPACR 0x00000D88 - -// Debug Halting Control and Status -#define CPU_SCS_O_DHCSR 0x00000DF0 - -// Deubg Core Register Selector -#define CPU_SCS_O_DCRSR 0x00000DF4 - -// Debug Core Register Data -#define CPU_SCS_O_DCRDR 0x00000DF8 - -// Debug Exception and Monitor Control -#define CPU_SCS_O_DEMCR 0x00000DFC - -// Software Trigger Interrupt -#define CPU_SCS_O_STIR 0x00000F00 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ICTR -// -//***************************************************************************** -// Field: [2:0] INTLINESNUM -// -// Total number of interrupt lines in groups of 32. -// -// 0: 0...32 -// 1: 33...64 -// 2: 65...96 -// 3: 97...128 -// 4: 129...160 -// 5: 161...192 -// 6: 193...224 -// 7: 225...256 -#define CPU_SCS_ICTR_INTLINESNUM_W 3 -#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 -#define CPU_SCS_ICTR_INTLINESNUM_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ACTLR -// -//***************************************************************************** -// Field: [2] DISFOLD -// -// Disables folding of IT instruction. -#define CPU_SCS_ACTLR_DISFOLD 0x00000004 -#define CPU_SCS_ACTLR_DISFOLD_BITN 2 -#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 -#define CPU_SCS_ACTLR_DISFOLD_S 2 - -// Field: [1] DISDEFWBUF -// -// Disables write buffer use during default memory map accesses. This causes -// all bus faults to be precise bus faults but decreases the performance of the -// processor because the stores to memory have to complete before the next -// instruction can be executed. -#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 -#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 -#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 -#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 - -// Field: [0] DISMCYCINT -// -// Disables interruption of multi-cycle instructions. This increases the -// interrupt latency of the processor becuase LDM/STM completes before -// interrupt stacking occurs. -#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 -#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 -#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 -#define CPU_SCS_ACTLR_DISMCYCINT_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_STCSR -// -//***************************************************************************** -// Field: [16] COUNTFLAG -// -// Returns 1 if timer counted to 0 since last time this was read. Clears on -// read by application of any part of the SysTick Control and Status Register. -// If read by the debugger using the DAP, this bit is cleared on read-only if -// the MasterType bit in the **AHB-AP** Control Register is set to 0. -// Otherwise, COUNTFLAG is not changed by the debugger read. -#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 -#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 -#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 -#define CPU_SCS_STCSR_COUNTFLAG_S 16 - -// Field: [2] CLKSOURCE -// -// Clock source: -// -// 0: External reference clock. -// 1: Core clock -// -// External clock is not available in this device. Writes to this field will be -// ignored. -#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 -#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 -#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 -#define CPU_SCS_STCSR_CLKSOURCE_S 2 - -// Field: [1] TICKINT -// -// 0: Counting down to zero does not pend the SysTick handler. Software can use -// COUNTFLAG to determine if the SysTick handler has ever counted to zero. -// 1: Counting down to zero pends the SysTick handler. -#define CPU_SCS_STCSR_TICKINT 0x00000002 -#define CPU_SCS_STCSR_TICKINT_BITN 1 -#define CPU_SCS_STCSR_TICKINT_M 0x00000002 -#define CPU_SCS_STCSR_TICKINT_S 1 - -// Field: [0] ENABLE -// -// Enable SysTick counter -// -// 0: Counter disabled -// 1: Counter operates in a multi-shot way. That is, counter loads with the -// Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it -// sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on -// TICKINT. It then loads STRVR.RELOAD again, and begins counting. -#define CPU_SCS_STCSR_ENABLE 0x00000001 -#define CPU_SCS_STCSR_ENABLE_BITN 0 -#define CPU_SCS_STCSR_ENABLE_M 0x00000001 -#define CPU_SCS_STCSR_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_STRVR -// -//***************************************************************************** -// Field: [23:0] RELOAD -// -// Value to load into the SysTick Current Value Register STCVR.CURRENT when the -// counter reaches 0. -#define CPU_SCS_STRVR_RELOAD_W 24 -#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF -#define CPU_SCS_STRVR_RELOAD_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_STCVR -// -//***************************************************************************** -// Field: [23:0] CURRENT -// -// Current value at the time the register is accessed. No read-modify-write -// protection is provided, so change with care. Writing to it with any value -// clears the register to 0. Clearing this register also clears -// STCSR.COUNTFLAG. -#define CPU_SCS_STCVR_CURRENT_W 24 -#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF -#define CPU_SCS_STCVR_CURRENT_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_STCR -// -//***************************************************************************** -// Field: [31] NOREF -// -// Reads as one. Indicates that no separate reference clock is provided. -#define CPU_SCS_STCR_NOREF 0x80000000 -#define CPU_SCS_STCR_NOREF_BITN 31 -#define CPU_SCS_STCR_NOREF_M 0x80000000 -#define CPU_SCS_STCR_NOREF_S 31 - -// Field: [30] SKEW -// -// Reads as one. The calibration value is not exactly 10ms because of clock -// frequency. This could affect its suitability as a software real time clock. -#define CPU_SCS_STCR_SKEW 0x40000000 -#define CPU_SCS_STCR_SKEW_BITN 30 -#define CPU_SCS_STCR_SKEW_M 0x40000000 -#define CPU_SCS_STCR_SKEW_S 30 - -// Field: [23:0] TENMS -// -// An optional Reload value to be used for 10ms (100Hz) timing, subject to -// system clock skew errors. The value read is valid only when core clock is at -// 48MHz. -#define CPU_SCS_STCR_TENMS_W 24 -#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF -#define CPU_SCS_STCR_TENMS_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ISER0 -// -//***************************************************************************** -// Field: [31] SETENA31 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 -#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 -#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 -#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 - -// Field: [30] SETENA30 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 -#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 -#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 -#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 - -// Field: [29] SETENA29 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 -#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 -#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 -#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 - -// Field: [28] SETENA28 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 -#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 -#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 -#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 - -// Field: [27] SETENA27 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 -#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 -#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 -#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 - -// Field: [26] SETENA26 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 -#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 -#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 -#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 - -// Field: [25] SETENA25 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 -#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 -#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 -#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 - -// Field: [24] SETENA24 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 -#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 -#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 -#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 - -// Field: [23] SETENA23 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 -#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 -#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 -#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 - -// Field: [22] SETENA22 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 -#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 -#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 -#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 - -// Field: [21] SETENA21 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 -#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 -#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 -#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 - -// Field: [20] SETENA20 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 -#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 -#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 -#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 - -// Field: [19] SETENA19 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 -#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 -#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 -#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 - -// Field: [18] SETENA18 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 -#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 -#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 -#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 - -// Field: [17] SETENA17 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 -#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 -#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 -#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 - -// Field: [16] SETENA16 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 -#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 -#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 -#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 - -// Field: [15] SETENA15 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 -#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 -#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 -#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 - -// Field: [14] SETENA14 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 -#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 -#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 -#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 - -// Field: [13] SETENA13 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 -#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 -#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 -#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 - -// Field: [12] SETENA12 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 -#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 -#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 -#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 - -// Field: [11] SETENA11 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 -#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 -#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 -#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 - -// Field: [10] SETENA10 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 -#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 -#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 -#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 - -// Field: [9] SETENA9 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 -#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 -#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 -#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 - -// Field: [8] SETENA8 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 -#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 -#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 -#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 - -// Field: [7] SETENA7 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 -#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 -#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 -#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 - -// Field: [6] SETENA6 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 -#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 -#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 -#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 - -// Field: [5] SETENA5 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 -#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 -#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 -#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 - -// Field: [4] SETENA4 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 -#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 -#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 -#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 - -// Field: [3] SETENA3 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 -#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 -#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 -#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 - -// Field: [2] SETENA2 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 -#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 -#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 -#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 - -// Field: [1] SETENA1 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 -#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 -#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 -#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 - -// Field: [0] SETENA0 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 -#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 -#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 -#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ISER1 -// -//***************************************************************************** -// Field: [1] SETENA33 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 -#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 -#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 -#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 - -// Field: [0] SETENA32 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 -#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 -#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 -#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ICER0 -// -//***************************************************************************** -// Field: [31] CLRENA31 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 -#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 -#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 -#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 - -// Field: [30] CLRENA30 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 -#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 -#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 -#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 - -// Field: [29] CLRENA29 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 -#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 -#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 -#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 - -// Field: [28] CLRENA28 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 -#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 -#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 -#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 - -// Field: [27] CLRENA27 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 -#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 -#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 -#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 - -// Field: [26] CLRENA26 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 -#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 -#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 -#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 - -// Field: [25] CLRENA25 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 -#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 -#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 -#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 - -// Field: [24] CLRENA24 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 -#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 -#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 -#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 - -// Field: [23] CLRENA23 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 -#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 -#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 -#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 - -// Field: [22] CLRENA22 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 -#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 -#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 -#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 - -// Field: [21] CLRENA21 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 -#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 -#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 -#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 - -// Field: [20] CLRENA20 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 -#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 -#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 -#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 - -// Field: [19] CLRENA19 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 -#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 -#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 -#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 - -// Field: [18] CLRENA18 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 -#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 -#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 -#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 - -// Field: [17] CLRENA17 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 -#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 -#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 -#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 - -// Field: [16] CLRENA16 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 -#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 -#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 -#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 - -// Field: [15] CLRENA15 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 -#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 -#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 -#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 - -// Field: [14] CLRENA14 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 -#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 -#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 -#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 - -// Field: [13] CLRENA13 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 -#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 -#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 -#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 - -// Field: [12] CLRENA12 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 -#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 -#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 -#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 - -// Field: [11] CLRENA11 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 -#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 -#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 -#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 - -// Field: [10] CLRENA10 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 -#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 -#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 -#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 - -// Field: [9] CLRENA9 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 -#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 -#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 -#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 - -// Field: [8] CLRENA8 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 -#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 -#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 -#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 - -// Field: [7] CLRENA7 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 -#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 -#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 -#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 - -// Field: [6] CLRENA6 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 -#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 -#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 -#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 - -// Field: [5] CLRENA5 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 -#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 -#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 -#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 - -// Field: [4] CLRENA4 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 -#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 -#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 -#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 - -// Field: [3] CLRENA3 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 -#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 -#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 -#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 - -// Field: [2] CLRENA2 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 -#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 -#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 -#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 - -// Field: [1] CLRENA1 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 -#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 -#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 -#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 - -// Field: [0] CLRENA0 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 -#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 -#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 -#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ICER1 -// -//***************************************************************************** -// Field: [1] CLRENA33 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 -#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 -#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 -#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 - -// Field: [0] CLRENA32 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 -#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 -#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 -#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ISPR0 -// -//***************************************************************************** -// Field: [31] SETPEND31 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 - -// Field: [30] SETPEND30 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 - -// Field: [29] SETPEND29 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 - -// Field: [28] SETPEND28 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 - -// Field: [27] SETPEND27 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 - -// Field: [26] SETPEND26 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 - -// Field: [25] SETPEND25 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 - -// Field: [24] SETPEND24 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 - -// Field: [23] SETPEND23 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 - -// Field: [22] SETPEND22 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 - -// Field: [21] SETPEND21 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 - -// Field: [20] SETPEND20 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 - -// Field: [19] SETPEND19 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 - -// Field: [18] SETPEND18 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 - -// Field: [17] SETPEND17 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 - -// Field: [16] SETPEND16 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 - -// Field: [15] SETPEND15 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 - -// Field: [14] SETPEND14 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 - -// Field: [13] SETPEND13 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 - -// Field: [12] SETPEND12 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 - -// Field: [11] SETPEND11 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 - -// Field: [10] SETPEND10 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 - -// Field: [9] SETPEND9 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 - -// Field: [8] SETPEND8 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 - -// Field: [7] SETPEND7 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 - -// Field: [6] SETPEND6 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 - -// Field: [5] SETPEND5 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 - -// Field: [4] SETPEND4 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 - -// Field: [3] SETPEND3 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 - -// Field: [2] SETPEND2 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 - -// Field: [1] SETPEND1 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 - -// Field: [0] SETPEND0 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ISPR1 -// -//***************************************************************************** -// Field: [1] SETPEND33 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 - -// Field: [0] SETPEND32 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ICPR0 -// -//***************************************************************************** -// Field: [31] CLRPEND31 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 - -// Field: [30] CLRPEND30 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 - -// Field: [29] CLRPEND29 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 - -// Field: [28] CLRPEND28 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 - -// Field: [27] CLRPEND27 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 - -// Field: [26] CLRPEND26 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 - -// Field: [25] CLRPEND25 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 - -// Field: [24] CLRPEND24 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 - -// Field: [23] CLRPEND23 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 - -// Field: [22] CLRPEND22 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 - -// Field: [21] CLRPEND21 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 - -// Field: [20] CLRPEND20 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 - -// Field: [19] CLRPEND19 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 - -// Field: [18] CLRPEND18 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 - -// Field: [17] CLRPEND17 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 - -// Field: [16] CLRPEND16 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 - -// Field: [15] CLRPEND15 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 - -// Field: [14] CLRPEND14 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 - -// Field: [13] CLRPEND13 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 - -// Field: [12] CLRPEND12 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 - -// Field: [11] CLRPEND11 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 - -// Field: [10] CLRPEND10 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 - -// Field: [9] CLRPEND9 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 - -// Field: [8] CLRPEND8 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 - -// Field: [7] CLRPEND7 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 - -// Field: [6] CLRPEND6 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 - -// Field: [5] CLRPEND5 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 - -// Field: [4] CLRPEND4 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 - -// Field: [3] CLRPEND3 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 - -// Field: [2] CLRPEND2 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 - -// Field: [1] CLRPEND1 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 - -// Field: [0] CLRPEND0 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ICPR1 -// -//***************************************************************************** -// Field: [1] CLRPEND33 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 - -// Field: [0] CLRPEND32 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IABR0 -// -//***************************************************************************** -// Field: [31] ACTIVE31 -// -// Reading 0 from this bit implies that interrupt line 31 is not active. -// Reading 1 from this bit implies that the interrupt line 31 is active (See -// EVENT:CPUIRQSEL31.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 - -// Field: [30] ACTIVE30 -// -// Reading 0 from this bit implies that interrupt line 30 is not active. -// Reading 1 from this bit implies that the interrupt line 30 is active (See -// EVENT:CPUIRQSEL30.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 - -// Field: [29] ACTIVE29 -// -// Reading 0 from this bit implies that interrupt line 29 is not active. -// Reading 1 from this bit implies that the interrupt line 29 is active (See -// EVENT:CPUIRQSEL29.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 - -// Field: [28] ACTIVE28 -// -// Reading 0 from this bit implies that interrupt line 28 is not active. -// Reading 1 from this bit implies that the interrupt line 28 is active (See -// EVENT:CPUIRQSEL28.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 - -// Field: [27] ACTIVE27 -// -// Reading 0 from this bit implies that interrupt line 27 is not active. -// Reading 1 from this bit implies that the interrupt line 27 is active (See -// EVENT:CPUIRQSEL27.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 - -// Field: [26] ACTIVE26 -// -// Reading 0 from this bit implies that interrupt line 26 is not active. -// Reading 1 from this bit implies that the interrupt line 26 is active (See -// EVENT:CPUIRQSEL26.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 - -// Field: [25] ACTIVE25 -// -// Reading 0 from this bit implies that interrupt line 25 is not active. -// Reading 1 from this bit implies that the interrupt line 25 is active (See -// EVENT:CPUIRQSEL25.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 - -// Field: [24] ACTIVE24 -// -// Reading 0 from this bit implies that interrupt line 24 is not active. -// Reading 1 from this bit implies that the interrupt line 24 is active (See -// EVENT:CPUIRQSEL24.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 - -// Field: [23] ACTIVE23 -// -// Reading 0 from this bit implies that interrupt line 23 is not active. -// Reading 1 from this bit implies that the interrupt line 23 is active (See -// EVENT:CPUIRQSEL23.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 - -// Field: [22] ACTIVE22 -// -// Reading 0 from this bit implies that interrupt line 22 is not active. -// Reading 1 from this bit implies that the interrupt line 22 is active (See -// EVENT:CPUIRQSEL22.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 - -// Field: [21] ACTIVE21 -// -// Reading 0 from this bit implies that interrupt line 21 is not active. -// Reading 1 from this bit implies that the interrupt line 21 is active (See -// EVENT:CPUIRQSEL21.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 - -// Field: [20] ACTIVE20 -// -// Reading 0 from this bit implies that interrupt line 20 is not active. -// Reading 1 from this bit implies that the interrupt line 20 is active (See -// EVENT:CPUIRQSEL20.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 - -// Field: [19] ACTIVE19 -// -// Reading 0 from this bit implies that interrupt line 19 is not active. -// Reading 1 from this bit implies that the interrupt line 19 is active (See -// EVENT:CPUIRQSEL19.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 - -// Field: [18] ACTIVE18 -// -// Reading 0 from this bit implies that interrupt line 18 is not active. -// Reading 1 from this bit implies that the interrupt line 18 is active (See -// EVENT:CPUIRQSEL18.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 - -// Field: [17] ACTIVE17 -// -// Reading 0 from this bit implies that interrupt line 17 is not active. -// Reading 1 from this bit implies that the interrupt line 17 is active (See -// EVENT:CPUIRQSEL17.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 - -// Field: [16] ACTIVE16 -// -// Reading 0 from this bit implies that interrupt line 16 is not active. -// Reading 1 from this bit implies that the interrupt line 16 is active (See -// EVENT:CPUIRQSEL16.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 - -// Field: [15] ACTIVE15 -// -// Reading 0 from this bit implies that interrupt line 15 is not active. -// Reading 1 from this bit implies that the interrupt line 15 is active (See -// EVENT:CPUIRQSEL15.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 - -// Field: [14] ACTIVE14 -// -// Reading 0 from this bit implies that interrupt line 14 is not active. -// Reading 1 from this bit implies that the interrupt line 14 is active (See -// EVENT:CPUIRQSEL14.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 - -// Field: [13] ACTIVE13 -// -// Reading 0 from this bit implies that interrupt line 13 is not active. -// Reading 1 from this bit implies that the interrupt line 13 is active (See -// EVENT:CPUIRQSEL13.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 - -// Field: [12] ACTIVE12 -// -// Reading 0 from this bit implies that interrupt line 12 is not active. -// Reading 1 from this bit implies that the interrupt line 12 is active (See -// EVENT:CPUIRQSEL12.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 - -// Field: [11] ACTIVE11 -// -// Reading 0 from this bit implies that interrupt line 11 is not active. -// Reading 1 from this bit implies that the interrupt line 11 is active (See -// EVENT:CPUIRQSEL11.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 - -// Field: [10] ACTIVE10 -// -// Reading 0 from this bit implies that interrupt line 10 is not active. -// Reading 1 from this bit implies that the interrupt line 10 is active (See -// EVENT:CPUIRQSEL10.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 - -// Field: [9] ACTIVE9 -// -// Reading 0 from this bit implies that interrupt line 9 is not active. Reading -// 1 from this bit implies that the interrupt line 9 is active (See -// EVENT:CPUIRQSEL9.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 - -// Field: [8] ACTIVE8 -// -// Reading 0 from this bit implies that interrupt line 8 is not active. Reading -// 1 from this bit implies that the interrupt line 8 is active (See -// EVENT:CPUIRQSEL8.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 - -// Field: [7] ACTIVE7 -// -// Reading 0 from this bit implies that interrupt line 7 is not active. Reading -// 1 from this bit implies that the interrupt line 7 is active (See -// EVENT:CPUIRQSEL7.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 - -// Field: [6] ACTIVE6 -// -// Reading 0 from this bit implies that interrupt line 6 is not active. Reading -// 1 from this bit implies that the interrupt line 6 is active (See -// EVENT:CPUIRQSEL6.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 - -// Field: [5] ACTIVE5 -// -// Reading 0 from this bit implies that interrupt line 5 is not active. Reading -// 1 from this bit implies that the interrupt line 5 is active (See -// EVENT:CPUIRQSEL5.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 - -// Field: [4] ACTIVE4 -// -// Reading 0 from this bit implies that interrupt line 4 is not active. Reading -// 1 from this bit implies that the interrupt line 4 is active (See -// EVENT:CPUIRQSEL4.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 - -// Field: [3] ACTIVE3 -// -// Reading 0 from this bit implies that interrupt line 3 is not active. Reading -// 1 from this bit implies that the interrupt line 3 is active (See -// EVENT:CPUIRQSEL3.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 - -// Field: [2] ACTIVE2 -// -// Reading 0 from this bit implies that interrupt line 2 is not active. Reading -// 1 from this bit implies that the interrupt line 2 is active (See -// EVENT:CPUIRQSEL2.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 - -// Field: [1] ACTIVE1 -// -// Reading 0 from this bit implies that interrupt line 1 is not active. Reading -// 1 from this bit implies that the interrupt line 1 is active (See -// EVENT:CPUIRQSEL1.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 - -// Field: [0] ACTIVE0 -// -// Reading 0 from this bit implies that interrupt line 0 is not active. Reading -// 1 from this bit implies that the interrupt line 0 is active (See -// EVENT:CPUIRQSEL0.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IABR1 -// -//***************************************************************************** -// Field: [1] ACTIVE33 -// -// Reading 0 from this bit implies that interrupt line 33 is not active. -// Reading 1 from this bit implies that the interrupt line 33 is active (See -// EVENT:CPUIRQSEL33.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 - -// Field: [0] ACTIVE32 -// -// Reading 0 from this bit implies that interrupt line 32 is not active. -// Reading 1 from this bit implies that the interrupt line 32 is active (See -// EVENT:CPUIRQSEL32.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR0 -// -//***************************************************************************** -// Field: [31:24] PRI_3 -// -// Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 -#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 - -// Field: [23:16] PRI_2 -// -// Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 - -// Field: [15:8] PRI_1 -// -// Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 - -// Field: [7:0] PRI_0 -// -// Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF -#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR1 -// -//***************************************************************************** -// Field: [31:24] PRI_7 -// -// Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 -#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 - -// Field: [23:16] PRI_6 -// -// Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 - -// Field: [15:8] PRI_5 -// -// Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 - -// Field: [7:0] PRI_4 -// -// Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF -#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR2 -// -//***************************************************************************** -// Field: [31:24] PRI_11 -// -// Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 -#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 - -// Field: [23:16] PRI_10 -// -// Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 - -// Field: [15:8] PRI_9 -// -// Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 - -// Field: [7:0] PRI_8 -// -// Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF -#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR3 -// -//***************************************************************************** -// Field: [31:24] PRI_15 -// -// Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 -#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 - -// Field: [23:16] PRI_14 -// -// Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 - -// Field: [15:8] PRI_13 -// -// Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 - -// Field: [7:0] PRI_12 -// -// Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF -#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR4 -// -//***************************************************************************** -// Field: [31:24] PRI_19 -// -// Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 -#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 - -// Field: [23:16] PRI_18 -// -// Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 - -// Field: [15:8] PRI_17 -// -// Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 - -// Field: [7:0] PRI_16 -// -// Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF -#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR5 -// -//***************************************************************************** -// Field: [31:24] PRI_23 -// -// Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 -#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 - -// Field: [23:16] PRI_22 -// -// Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 - -// Field: [15:8] PRI_21 -// -// Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 - -// Field: [7:0] PRI_20 -// -// Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF -#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR6 -// -//***************************************************************************** -// Field: [31:24] PRI_27 -// -// Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 -#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 - -// Field: [23:16] PRI_26 -// -// Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 - -// Field: [15:8] PRI_25 -// -// Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 - -// Field: [7:0] PRI_24 -// -// Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF -#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR7 -// -//***************************************************************************** -// Field: [31:24] PRI_31 -// -// Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 -#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 - -// Field: [23:16] PRI_30 -// -// Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 - -// Field: [15:8] PRI_29 -// -// Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 - -// Field: [7:0] PRI_28 -// -// Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF -#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR8 -// -//***************************************************************************** -// Field: [15:8] PRI_33 -// -// Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 - -// Field: [7:0] PRI_32 -// -// Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF -#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_CPUID -// -//***************************************************************************** -// Field: [31:24] IMPLEMENTER -// -// Implementor code. -#define CPU_SCS_CPUID_IMPLEMENTER_W 8 -#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 -#define CPU_SCS_CPUID_IMPLEMENTER_S 24 - -// Field: [23:20] VARIANT -// -// Implementation defined variant number. -#define CPU_SCS_CPUID_VARIANT_W 4 -#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 -#define CPU_SCS_CPUID_VARIANT_S 20 - -// Field: [19:16] CONSTANT -// -// Reads as 0xF -#define CPU_SCS_CPUID_CONSTANT_W 4 -#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 -#define CPU_SCS_CPUID_CONSTANT_S 16 - -// Field: [15:4] PARTNO -// -// Number of processor within family. -#define CPU_SCS_CPUID_PARTNO_W 12 -#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 -#define CPU_SCS_CPUID_PARTNO_S 4 - -// Field: [3:0] REVISION -// -// Implementation defined revision number. -#define CPU_SCS_CPUID_REVISION_W 4 -#define CPU_SCS_CPUID_REVISION_M 0x0000000F -#define CPU_SCS_CPUID_REVISION_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ICSR -// -//***************************************************************************** -// Field: [31] NMIPENDSET -// -// Set pending NMI bit. Setting this bit pends and activates an NMI. Because -// NMI is the highest-priority interrupt, it takes effect as soon as it -// registers. -// -// 0: No action -// 1: Set pending NMI -#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 -#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 -#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 -#define CPU_SCS_ICSR_NMIPENDSET_S 31 - -// Field: [28] PENDSVSET -// -// Set pending pendSV bit. -// -// 0: No action -// 1: Set pending PendSV -#define CPU_SCS_ICSR_PENDSVSET 0x10000000 -#define CPU_SCS_ICSR_PENDSVSET_BITN 28 -#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 -#define CPU_SCS_ICSR_PENDSVSET_S 28 - -// Field: [27] PENDSVCLR -// -// Clear pending pendSV bit -// -// 0: No action -// 1: Clear pending pendSV -#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 -#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 -#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 -#define CPU_SCS_ICSR_PENDSVCLR_S 27 - -// Field: [26] PENDSTSET -// -// Set a pending SysTick bit. -// -// 0: No action -// 1: Set pending SysTick -#define CPU_SCS_ICSR_PENDSTSET 0x04000000 -#define CPU_SCS_ICSR_PENDSTSET_BITN 26 -#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 -#define CPU_SCS_ICSR_PENDSTSET_S 26 - -// Field: [25] PENDSTCLR -// -// Clear pending SysTick bit -// -// 0: No action -// 1: Clear pending SysTick -#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 -#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 -#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 -#define CPU_SCS_ICSR_PENDSTCLR_S 25 - -// Field: [23] ISRPREEMPT -// -// This field can only be used at debug time. It indicates that a pending -// interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, -// the interrupt is serviced. -// -// 0: A pending exception is not serviced. -// 1: A pending exception is serviced on exit from the debug halt state -#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 -#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 -#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 -#define CPU_SCS_ICSR_ISRPREEMPT_S 23 - -// Field: [22] ISRPENDING -// -// Interrupt pending flag. Excludes NMI and faults. -// -// 0x0: Interrupt not pending -// 0x1: Interrupt pending -#define CPU_SCS_ICSR_ISRPENDING 0x00400000 -#define CPU_SCS_ICSR_ISRPENDING_BITN 22 -#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 -#define CPU_SCS_ICSR_ISRPENDING_S 22 - -// Field: [17:12] VECTPENDING -// -// Pending ISR number field. This field contains the interrupt number of the -// highest priority pending ISR. -#define CPU_SCS_ICSR_VECTPENDING_W 6 -#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 -#define CPU_SCS_ICSR_VECTPENDING_S 12 - -// Field: [11] RETTOBASE -// -// Indicates whether there are preempted active exceptions: -// -// 0: There are preempted active exceptions to execute -// 1: There are no active exceptions, or the currently-executing exception is -// the only active exception. -#define CPU_SCS_ICSR_RETTOBASE 0x00000800 -#define CPU_SCS_ICSR_RETTOBASE_BITN 11 -#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 -#define CPU_SCS_ICSR_RETTOBASE_S 11 - -// Field: [8:0] VECTACTIVE -// -// Active ISR number field. Reset clears this field. -#define CPU_SCS_ICSR_VECTACTIVE_W 9 -#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF -#define CPU_SCS_ICSR_VECTACTIVE_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_VTOR -// -//***************************************************************************** -// Field: [29:7] TBLOFF -// -// Bits 29 down to 7 of the vector table base offset. -#define CPU_SCS_VTOR_TBLOFF_W 23 -#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 -#define CPU_SCS_VTOR_TBLOFF_S 7 - -//***************************************************************************** -// -// Register: CPU_SCS_O_AIRCR -// -//***************************************************************************** -// Field: [31:16] VECTKEY -// -// Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. -// Otherwise the write value is ignored. Read always returns 0xFA05. -#define CPU_SCS_AIRCR_VECTKEY_W 16 -#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 -#define CPU_SCS_AIRCR_VECTKEY_S 16 - -// Field: [15] ENDIANESS -// -// Data endianness bit -// ENUMs: -// BIG Big endian -// LITTLE Little endian -#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 -#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_S 15 -#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 - -// Field: [10:8] PRIGROUP -// -// Interrupt priority grouping field. This field is a binary point position -// indicator for creating subpriorities for exceptions that share the same -// pre-emption level. It divides the PRI_n field in the Interrupt Priority -// Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption -// level and a subpriority level. The binary point is a left-of value. This -// means that the PRIGROUP value represents a point starting at the left of the -// Least Significant Bit (LSB). The lowest value might not be 0 depending on -// the number of bits allocated for priorities, and implementation choices. -#define CPU_SCS_AIRCR_PRIGROUP_W 3 -#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 -#define CPU_SCS_AIRCR_PRIGROUP_S 8 - -// Field: [2] SYSRESETREQ -// -// Requests a warm reset. Setting this bit does not prevent Halting Debug from -// running. -#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 -#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 -#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 -#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 - -// Field: [1] VECTCLRACTIVE -// -// Clears all active state information for active NMI, fault, and interrupts. -// It is the responsibility of the application to reinitialize the stack. This -// bit is for returning to a known state during debug. The bit self-clears. -// IPSR is not cleared by this operation. So, if used by an application, it -// must only be used at the base level of activation, or within a system -// handler whose active bit can be set. -#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 - -// Field: [0] VECTRESET -// -// System Reset bit. Resets the system, with the exception of debug components. -// This bit is reserved for debug use and can be written to 1 only when the -// core is halted. The bit self-clears. Writing this bit to 1 while core is not -// halted may result in unpredictable behavior. -#define CPU_SCS_AIRCR_VECTRESET 0x00000001 -#define CPU_SCS_AIRCR_VECTRESET_BITN 0 -#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 -#define CPU_SCS_AIRCR_VECTRESET_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_SCR -// -//***************************************************************************** -// Field: [4] SEVONPEND -// -// Send Event on Pending bit: -// -// 0: Only enabled interrupts or events can wakeup the processor, disabled -// interrupts are excluded -// 1: Enabled events and all interrupts, including disabled interrupts, can -// wakeup the processor. -// -// When an event or interrupt enters pending state, the event signal wakes up -// the processor from WFE. If -// the processor is not waiting for an event, the event is registered and -// affects the next WFE. -// The processor also wakes up on execution of an SEV instruction. -#define CPU_SCS_SCR_SEVONPEND 0x00000010 -#define CPU_SCS_SCR_SEVONPEND_BITN 4 -#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 -#define CPU_SCS_SCR_SEVONPEND_S 4 - -// Field: [2] SLEEPDEEP -// -// Controls whether the processor uses sleep or deep sleep as its low power -// mode -// ENUMs: -// DEEPSLEEP Deep sleep -// SLEEP Sleep -#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 -#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_S 2 -#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 - -// Field: [1] SLEEPONEXIT -// -// Sleep on exit when returning from Handler mode to Thread mode. Enables -// interrupt driven applications to avoid returning to empty main application. -// -// 0: Do not sleep when returning to thread mode -// 1: Sleep on ISR exit -#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 -#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 -#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 -#define CPU_SCS_SCR_SLEEPONEXIT_S 1 - -//***************************************************************************** -// -// Register: CPU_SCS_O_CCR -// -//***************************************************************************** -// Field: [9] STKALIGN -// -// Stack alignment bit. -// -// 0: Only 4-byte alignment is guaranteed for the SP used prior to the -// exception on exception entry. -// 1: On exception entry, the SP used prior to the exception is adjusted to be -// 8-byte aligned and the context to restore it is saved. The SP is restored on -// the associated exception return. -#define CPU_SCS_CCR_STKALIGN 0x00000200 -#define CPU_SCS_CCR_STKALIGN_BITN 9 -#define CPU_SCS_CCR_STKALIGN_M 0x00000200 -#define CPU_SCS_CCR_STKALIGN_S 9 - -// Field: [8] BFHFNMIGN -// -// Enables handlers with priority -1 or -2 to ignore data BusFaults caused by -// load and store instructions. This applies to the HardFault, NMI, and -// FAULTMASK escalated handlers: -// -// 0: Data BusFaults caused by load and store instructions cause a lock-up -// 1: Data BusFaults caused by load and store instructions are ignored. -// -// Set this bit to 1 only when the handler and its data are in absolutely safe -// memory. The normal use -// of this bit is to probe system devices and bridges to detect problems. -#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 -#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 -#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 -#define CPU_SCS_CCR_BFHFNMIGN_S 8 - -// Field: [4] DIV_0_TRP -// -// Enables faulting or halting when the processor executes an SDIV or UDIV -// instruction with a divisor of 0: -// -// 0: Do not trap divide by 0. In this mode, a divide by zero returns a -// quotient of 0. -// 1: Trap divide by 0. The relevant Usage Fault Status Register bit is -// CFSR.DIVBYZERO. -#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 -#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 -#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 -#define CPU_SCS_CCR_DIV_0_TRP_S 4 - -// Field: [3] UNALIGN_TRP -// -// Enables unaligned access traps: -// -// 0: Do not trap unaligned halfword and word accesses -// 1: Trap unaligned halfword and word accesses. The relevant Usage Fault -// Status Register bit is CFSR.UNALIGNED. -// -// If this bit is set to 1, an unaligned access generates a UsageFault. -// Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of -// the value in UNALIGN_TRP. -#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 -#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 -#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 -#define CPU_SCS_CCR_UNALIGN_TRP_S 3 - -// Field: [1] USERSETMPEND -// -// Enables unprivileged software access to STIR: -// -// 0: User code is not allowed to write to the Software Trigger Interrupt -// register (STIR). -// 1: User code can write the Software Trigger Interrupt register (STIR) to -// trigger (pend) a Main exception, which is associated with the Main stack -// pointer. -#define CPU_SCS_CCR_USERSETMPEND 0x00000002 -#define CPU_SCS_CCR_USERSETMPEND_BITN 1 -#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 -#define CPU_SCS_CCR_USERSETMPEND_S 1 - -// Field: [0] NONBASETHREDENA -// -// Indicates how the processor enters Thread mode: -// -// 0: Processor can enter Thread mode only when no exception is active. -// 1: Processor can enter Thread mode from any level using the appropriate -// return value (EXC_RETURN). -// -// Exception returns occur when one of the following instructions loads a value -// of 0xFXXXXXXX into the PC while in Handler mode: -// - POP/LDM which includes loading the PC. -// - LDR with PC as a destination. -// - BX with any register. -// The value written to the PC is intercepted and is referred to as the -// EXC_RETURN value. -#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 -#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 -#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 -#define CPU_SCS_CCR_NONBASETHREDENA_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_SHPR1 -// -//***************************************************************************** -// Field: [23:16] PRI_6 -// -// Priority of system handler 6. UsageFault -#define CPU_SCS_SHPR1_PRI_6_W 8 -#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 -#define CPU_SCS_SHPR1_PRI_6_S 16 - -// Field: [15:8] PRI_5 -// -// Priority of system handler 5: BusFault -#define CPU_SCS_SHPR1_PRI_5_W 8 -#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 -#define CPU_SCS_SHPR1_PRI_5_S 8 - -// Field: [7:0] PRI_4 -// -// Priority of system handler 4: MemManage -#define CPU_SCS_SHPR1_PRI_4_W 8 -#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF -#define CPU_SCS_SHPR1_PRI_4_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_SHPR2 -// -//***************************************************************************** -// Field: [31:24] PRI_11 -// -// Priority of system handler 11. SVCall -#define CPU_SCS_SHPR2_PRI_11_W 8 -#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 -#define CPU_SCS_SHPR2_PRI_11_S 24 - -//***************************************************************************** -// -// Register: CPU_SCS_O_SHPR3 -// -//***************************************************************************** -// Field: [31:24] PRI_15 -// -// Priority of system handler 15. SysTick exception -#define CPU_SCS_SHPR3_PRI_15_W 8 -#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 -#define CPU_SCS_SHPR3_PRI_15_S 24 - -// Field: [23:16] PRI_14 -// -// Priority of system handler 14. Pend SV -#define CPU_SCS_SHPR3_PRI_14_W 8 -#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 -#define CPU_SCS_SHPR3_PRI_14_S 16 - -// Field: [7:0] PRI_12 -// -// Priority of system handler 12. Debug Monitor -#define CPU_SCS_SHPR3_PRI_12_W 8 -#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF -#define CPU_SCS_SHPR3_PRI_12_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_SHCSR -// -//***************************************************************************** -// Field: [18] USGFAULTENA -// -// Usage fault system handler enable -// ENUMs: -// EN Exception enabled -// DIS Exception disabled -#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 -#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_S 18 -#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 - -// Field: [17] BUSFAULTENA -// -// Bus fault system handler enable -// ENUMs: -// EN Exception enabled -// DIS Exception disabled -#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 -#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 -#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 - -// Field: [16] MEMFAULTENA -// -// MemManage fault system handler enable -// ENUMs: -// EN Exception enabled -// DIS Exception disabled -#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 -#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 -#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 - -// Field: [15] SVCALLPENDED -// -// SVCall pending -// ENUMs: -// PENDING Exception is pending. -// NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 -#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 -#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 - -// Field: [14] BUSFAULTPENDED -// -// BusFault pending -// ENUMs: -// PENDING Exception is pending. -// NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 - -// Field: [13] MEMFAULTPENDED -// -// MemManage exception pending -// ENUMs: -// PENDING Exception is pending. -// NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 - -// Field: [12] USGFAULTPENDED -// -// Usage fault pending -// ENUMs: -// PENDING Exception is pending. -// NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 -#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 -#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 - -// Field: [11] SYSTICKACT -// -// SysTick active flag. -// -// 0x0: Not active -// 0x1: Active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 -#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_S 11 -#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 - -// Field: [10] PENDSVACT -// -// PendSV active -// -// 0x0: Not active -// 0x1: Active -#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 -#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 -#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 -#define CPU_SCS_SHCSR_PENDSVACT_S 10 - -// Field: [8] MONITORACT -// -// Debug monitor active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_MONITORACT 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_BITN 8 -#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_S 8 -#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 - -// Field: [7] SVCALLACT -// -// SVCall active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 -#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_S 7 -#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 - -// Field: [3] USGFAULTACT -// -// UsageFault exception active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 -#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_S 3 -#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 - -// Field: [1] BUSFAULTACT -// -// BusFault exception active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 -#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 -#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 - -// Field: [0] MEMFAULTACT -// -// MemManage exception active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 -#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 -#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 - -//***************************************************************************** -// -// Register: CPU_SCS_O_CFSR -// -//***************************************************************************** -// Field: [25] DIVBYZERO -// -// When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is -// enabled and an SDIV or UDIV instruction is used with a divisor of 0, this -// fault occurs The instruction is executed and the return PC points to it. If -// CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. -#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 -#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 -#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 -#define CPU_SCS_CFSR_DIVBYZERO_S 25 - -// Field: [24] UNALIGNED -// -// When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an -// unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD -// instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. -#define CPU_SCS_CFSR_UNALIGNED 0x01000000 -#define CPU_SCS_CFSR_UNALIGNED_BITN 24 -#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 -#define CPU_SCS_CFSR_UNALIGNED_S 24 - -// Field: [19] NOCP -// -// Attempt to use a coprocessor instruction. The processor does not support -// coprocessor instructions. -#define CPU_SCS_CFSR_NOCP 0x00080000 -#define CPU_SCS_CFSR_NOCP_BITN 19 -#define CPU_SCS_CFSR_NOCP_M 0x00080000 -#define CPU_SCS_CFSR_NOCP_S 19 - -// Field: [18] INVPC -// -// Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid -// context, invalid value. The return PC points to the instruction that tried -// to set the PC. -#define CPU_SCS_CFSR_INVPC 0x00040000 -#define CPU_SCS_CFSR_INVPC_BITN 18 -#define CPU_SCS_CFSR_INVPC_M 0x00040000 -#define CPU_SCS_CFSR_INVPC_S 18 - -// Field: [17] INVSTATE -// -// Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX -// type instruction has changed state). This includes state change after entry -// to or return from exception, as well as from inter-working instructions. -// Return PC points to faulting instruction, with the invalid state. -#define CPU_SCS_CFSR_INVSTATE 0x00020000 -#define CPU_SCS_CFSR_INVSTATE_BITN 17 -#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 -#define CPU_SCS_CFSR_INVSTATE_S 17 - -// Field: [16] UNDEFINSTR -// -// This bit is set when the processor attempts to execute an undefined -// instruction. This is an instruction that the processor cannot decode. The -// return PC points to the undefined instruction. -#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 -#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 -#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 -#define CPU_SCS_CFSR_UNDEFINSTR_S 16 - -// Field: [15] BFARVALID -// -// This bit is set if the Bus Fault Address Register (BFAR) contains a valid -// address. This is true after a bus fault where the address is known. Other -// faults can clear this bit, such as a Mem Manage fault occurring later. If a -// Bus fault occurs that is escalated to a Hard Fault because of priority, the -// Hard Fault handler must clear this bit. This prevents problems if returning -// to a stacked active Bus fault handler whose BFAR value has been overwritten. -#define CPU_SCS_CFSR_BFARVALID 0x00008000 -#define CPU_SCS_CFSR_BFARVALID_BITN 15 -#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 -#define CPU_SCS_CFSR_BFARVALID_S 15 - -// Field: [12] STKERR -// -// Stacking from exception has caused one or more bus faults. The SP is still -// adjusted and the values in the context area on the stack might be incorrect. -// BFAR is not written. -#define CPU_SCS_CFSR_STKERR 0x00001000 -#define CPU_SCS_CFSR_STKERR_BITN 12 -#define CPU_SCS_CFSR_STKERR_M 0x00001000 -#define CPU_SCS_CFSR_STKERR_S 12 - -// Field: [11] UNSTKERR -// -// Unstack from exception return has caused one or more bus faults. This is -// chained to the handler, so that the original return stack is still present. -// SP is not adjusted from failing return and new save is not performed. BFAR -// is not written. -#define CPU_SCS_CFSR_UNSTKERR 0x00000800 -#define CPU_SCS_CFSR_UNSTKERR_BITN 11 -#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 -#define CPU_SCS_CFSR_UNSTKERR_S 11 - -// Field: [10] IMPRECISERR -// -// Imprecise data bus error. It is a BusFault, but the Return PC is not related -// to the causing instruction. This is not a synchronous fault. So, if detected -// when the priority of the current activation is higher than the Bus Fault, it -// only pends. Bus fault activates when returning to a lower priority -// activation. If a precise fault occurs before returning to a lower priority -// exception, the handler detects both IMPRECISERR set and one of the precise -// fault status bits set at the same time. BFAR is not written. -#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 -#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 -#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 -#define CPU_SCS_CFSR_IMPRECISERR_S 10 - -// Field: [9] PRECISERR -// -// Precise data bus error return. -#define CPU_SCS_CFSR_PRECISERR 0x00000200 -#define CPU_SCS_CFSR_PRECISERR_BITN 9 -#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 -#define CPU_SCS_CFSR_PRECISERR_S 9 - -// Field: [8] IBUSERR -// -// Instruction bus error flag. This flag is set by a prefetch error. The fault -// stops on the instruction, so if the error occurs under a branch shadow, no -// fault occurs. BFAR is not written. -#define CPU_SCS_CFSR_IBUSERR 0x00000100 -#define CPU_SCS_CFSR_IBUSERR_BITN 8 -#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 -#define CPU_SCS_CFSR_IBUSERR_S 8 - -// Field: [7] MMARVALID -// -// Memory Manage Address Register (MMFAR) address valid flag. A later-arriving -// fault, such as a bus fault, can clear a memory manage fault.. If a MemManage -// fault occurs that is escalated to a Hard Fault because of priority, the Hard -// Fault handler must clear this bit. This prevents problems on return to a -// stacked active MemManage handler whose MMFAR value has been overwritten. -#define CPU_SCS_CFSR_MMARVALID 0x00000080 -#define CPU_SCS_CFSR_MMARVALID_BITN 7 -#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 -#define CPU_SCS_CFSR_MMARVALID_S 7 - -// Field: [4] MSTKERR -// -// Stacking from exception has caused one or more access violations. The SP is -// still adjusted and the values in the context area on the stack might be -// incorrect. MMFAR is not written. -#define CPU_SCS_CFSR_MSTKERR 0x00000010 -#define CPU_SCS_CFSR_MSTKERR_BITN 4 -#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 -#define CPU_SCS_CFSR_MSTKERR_S 4 - -// Field: [3] MUNSTKERR -// -// Unstack from exception return has caused one or more access violations. This -// is chained to the handler, so that the original return stack is still -// present. SP is not adjusted from failing return and new save is not -// performed. MMFAR is not written. -#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 -#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 -#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 -#define CPU_SCS_CFSR_MUNSTKERR_S 3 - -// Field: [1] DACCVIOL -// -// Data access violation flag. Attempting to load or store at a location that -// does not permit the operation sets this flag. The return PC points to the -// faulting instruction. This error loads MMFAR with the address of the -// attempted access. -#define CPU_SCS_CFSR_DACCVIOL 0x00000002 -#define CPU_SCS_CFSR_DACCVIOL_BITN 1 -#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 -#define CPU_SCS_CFSR_DACCVIOL_S 1 - -// Field: [0] IACCVIOL -// -// Instruction access violation flag. Attempting to fetch an instruction from a -// location that does not permit execution sets this flag. This occurs on any -// access to an XN region, even when the MPU is disabled or not present. The -// return PC points to the faulting instruction. MMFAR is not written. -#define CPU_SCS_CFSR_IACCVIOL 0x00000001 -#define CPU_SCS_CFSR_IACCVIOL_BITN 0 -#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 -#define CPU_SCS_CFSR_IACCVIOL_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_HFSR -// -//***************************************************************************** -// Field: [31] DEBUGEVT -// -// This bit is set if there is a fault related to debug. This is only possible -// when halting debug is not enabled. For monitor enabled debug, it only -// happens for BKPT when the current priority is higher than the monitor. When -// both halting and monitor debug are disabled, it only happens for debug -// events that are not ignored (minimally, BKPT). The Debug Fault Status -// Register is updated. -#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 -#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 -#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 -#define CPU_SCS_HFSR_DEBUGEVT_S 31 - -// Field: [30] FORCED -// -// Hard Fault activated because a Configurable Fault was received and cannot -// activate because of priority or because the Configurable Fault is disabled. -// The Hard Fault handler then has to read the other fault status registers to -// determine cause. -#define CPU_SCS_HFSR_FORCED 0x40000000 -#define CPU_SCS_HFSR_FORCED_BITN 30 -#define CPU_SCS_HFSR_FORCED_M 0x40000000 -#define CPU_SCS_HFSR_FORCED_S 30 - -// Field: [1] VECTTBL -// -// This bit is set if there is a fault because of vector table read on -// exception processing (Bus Fault). This case is always a Hard Fault. The -// return PC points to the pre-empted instruction. -#define CPU_SCS_HFSR_VECTTBL 0x00000002 -#define CPU_SCS_HFSR_VECTTBL_BITN 1 -#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 -#define CPU_SCS_HFSR_VECTTBL_S 1 - -//***************************************************************************** -// -// Register: CPU_SCS_O_DFSR -// -//***************************************************************************** -// Field: [4] EXTERNAL -// -// External debug request flag. The processor stops on next instruction -// boundary. -// -// 0x0: External debug request signal not asserted -// 0x1: External debug request signal asserted -#define CPU_SCS_DFSR_EXTERNAL 0x00000010 -#define CPU_SCS_DFSR_EXTERNAL_BITN 4 -#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 -#define CPU_SCS_DFSR_EXTERNAL_S 4 - -// Field: [3] VCATCH -// -// Vector catch flag. When this flag is set, a flag in one of the local fault -// status registers is also set to indicate the type of fault. -// -// 0x0: No vector catch occurred -// 0x1: Vector catch occurred -#define CPU_SCS_DFSR_VCATCH 0x00000008 -#define CPU_SCS_DFSR_VCATCH_BITN 3 -#define CPU_SCS_DFSR_VCATCH_M 0x00000008 -#define CPU_SCS_DFSR_VCATCH_S 3 - -// Field: [2] DWTTRAP -// -// Data Watchpoint and Trace (DWT) flag. The processor stops at the current -// instruction or at the next instruction. -// -// 0x0: No DWT match -// 0x1: DWT match -#define CPU_SCS_DFSR_DWTTRAP 0x00000004 -#define CPU_SCS_DFSR_DWTTRAP_BITN 2 -#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 -#define CPU_SCS_DFSR_DWTTRAP_S 2 - -// Field: [1] BKPT -// -// BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, -// and also by normal code. Return PC points to breakpoint containing -// instruction. -// -// 0x0: No BKPT instruction execution -// 0x1: BKPT instruction execution -#define CPU_SCS_DFSR_BKPT 0x00000002 -#define CPU_SCS_DFSR_BKPT_BITN 1 -#define CPU_SCS_DFSR_BKPT_M 0x00000002 -#define CPU_SCS_DFSR_BKPT_S 1 - -// Field: [0] HALTED -// -// Halt request flag. The processor is halted on the next instruction. -// -// 0x0: No halt request -// 0x1: Halt requested by NVIC, including step -#define CPU_SCS_DFSR_HALTED 0x00000001 -#define CPU_SCS_DFSR_HALTED_BITN 0 -#define CPU_SCS_DFSR_HALTED_M 0x00000001 -#define CPU_SCS_DFSR_HALTED_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MMFAR -// -//***************************************************************************** -// Field: [31:0] ADDRESS -// -// Mem Manage fault address field. -// This field is the data address of a faulted load or store attempt. When an -// unaligned access faults, the address is the actual address that faulted. -// Because an access can be split into multiple parts, each aligned, this -// address can be any offset in the range of the requested size. Flags -// CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination -// with CFSR.MMARVALIDindicate the cause of the fault. -#define CPU_SCS_MMFAR_ADDRESS_W 32 -#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF -#define CPU_SCS_MMFAR_ADDRESS_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_BFAR -// -//***************************************************************************** -// Field: [31:0] ADDRESS -// -// Bus fault address field. This field is the data address of a faulted load or -// store attempt. When an unaligned access faults, the address is the address -// requested by the instruction, even if that is not the address that faulted. -// Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and -// CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the -// fault. -#define CPU_SCS_BFAR_ADDRESS_W 32 -#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF -#define CPU_SCS_BFAR_ADDRESS_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_AFSR -// -//***************************************************************************** -// Field: [31:0] IMPDEF -// -// Implementation defined. The bits map directly onto the signal assignment to -// the auxiliary fault inputs. Tied to 0 -#define CPU_SCS_AFSR_IMPDEF_W 32 -#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF -#define CPU_SCS_AFSR_IMPDEF_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_PFR0 -// -//***************************************************************************** -// Field: [7:4] STATE1 -// -// State1 (T-bit == 1) -// -// 0x0: N/A -// 0x1: N/A -// 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit -// Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit -// instructions can be added using the appropriate instruction attribute, but -// other 32-bit basic instructions cannot.) -// 0x3: Thumb-2 encoding with all Thumb-2 basic instructions -#define CPU_SCS_ID_PFR0_STATE1_W 4 -#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 -#define CPU_SCS_ID_PFR0_STATE1_S 4 - -// Field: [3:0] STATE0 -// -// State0 (T-bit == 0) -// -// 0x0: No ARM encoding -// 0x1: N/A -#define CPU_SCS_ID_PFR0_STATE0_W 4 -#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F -#define CPU_SCS_ID_PFR0_STATE0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_PFR1 -// -//***************************************************************************** -// Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL -// -// Microcontroller programmer's model -// -// 0x0: Not supported -// 0x2: Two-stack support -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_DFR0 -// -//***************************************************************************** -// Field: [23:20] MICROCONTROLLER_DEBUG_MODEL -// -// Microcontroller Debug Model - memory mapped -// -// 0x0: Not supported -// 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_AFR0 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_MMFR0 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_MMFR1 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_MMFR2 -// -//***************************************************************************** -// Field: [24] WAIT_FOR_INTERRUPT_STALLING -// -// wait for interrupt stalling -// -// 0x0: Not supported -// 0x1: Wait for interrupt supported -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_MMFR3 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_ISAR0 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_ISAR1 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_ISAR2 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_ISAR3 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_ISAR4 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_CPACR -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_DHCSR -// -//***************************************************************************** -// Field: [25] S_RESET_ST -// -// Indicates that the core has been reset, or is now being reset, since the -// last time this bit was read. This a sticky bit that clears on read. So, -// reading twice and getting 1 then 0 means it was reset in the past. Reading -// twice and getting 1 both times means that it is being reset now (held in -// reset still). -// When writing to this register, 0 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 -#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 -#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 -#define CPU_SCS_DHCSR_S_RESET_ST_S 25 - -// Field: [24] S_RETIRE_ST -// -// Indicates that an instruction has completed since last read. This is a -// sticky bit that clears on read. This determines if the core is stalled on a -// load/store or fetch. -// When writing to this register, 0 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 -#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 -#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 -#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 - -// Field: [19] S_LOCKUP -// -// Reads as one if the core is running (not halted) and a lockup condition is -// present. -// When writing to this register, 1 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 -#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 -#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 -#define CPU_SCS_DHCSR_S_LOCKUP_S 19 - -// Field: [18] S_SLEEP -// -// Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must -// use C_HALT to gain control or wait for interrupt to wake-up. -// When writing to this register, 1 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 -#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 -#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 -#define CPU_SCS_DHCSR_S_SLEEP_S 18 - -// Field: [17] S_HALT -// -// The core is in debug state when this bit is set. -// When writing to this register, 1 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_HALT 0x00020000 -#define CPU_SCS_DHCSR_S_HALT_BITN 17 -#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 -#define CPU_SCS_DHCSR_S_HALT_S 17 - -// Field: [16] S_REGRDY -// -// Register Read/Write on the Debug Core Register Selector register is -// available. Last transfer is complete. -// When writing to this register, 1 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 -#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 -#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 -#define CPU_SCS_DHCSR_S_REGRDY_S 16 - -// Field: [5] C_SNAPSTALL -// -// If the core is stalled on a load/store operation the stall ceases and the -// instruction is forced to complete. This enables Halting debug to gain -// control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. -// The core reads S_RETIRE_ST as 0. This indicates that no instruction has -// advanced. This prevents misuse. The bus state is Unpredictable when this is -// used. S_RETIRE_ST can detect core stalls on load/store operations. -#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 -#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 -#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 -#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 - -// Field: [3] C_MASKINTS -// -// Mask interrupts when stepping or running in halted debug. This masking does -// not affect NMI, fault exceptions and SVC caused by execution of the -// instructions. This bit must only be modified when the processor is halted -// (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released -// (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must -// be separate). Modifying C_MASKINTS while the system is running with halting -// debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable -// behavior. -#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 -#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 -#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 -#define CPU_SCS_DHCSR_C_MASKINTS_S 3 - -// Field: [2] C_STEP -// -// Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. -// Must only be modified when the processor is halted (S_HALT == 1). -// Modifying C_STEP while the system is running with halting debug support -// enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. -#define CPU_SCS_DHCSR_C_STEP 0x00000004 -#define CPU_SCS_DHCSR_C_STEP_BITN 2 -#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 -#define CPU_SCS_DHCSR_C_STEP_S 2 - -// Field: [1] C_HALT -// -// Halts the core. This bit is set automatically when the core Halts. For -// example Breakpoint. This bit clears on core reset. -#define CPU_SCS_DHCSR_C_HALT 0x00000002 -#define CPU_SCS_DHCSR_C_HALT_BITN 1 -#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 -#define CPU_SCS_DHCSR_C_HALT_S 1 - -// Field: [0] C_DEBUGEN -// -// Enables debug. This can only be written by AHB-AP and not by the core. It is -// ignored when written by the core, which cannot set or clear it. The core -// must write a 1 to it when writing C_HALT to halt itself. -// The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when -// C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will -// be unknown to software when C_DEBUGEN = 0. -#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 -#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 -#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 -#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_DCRSR -// -//***************************************************************************** -// Field: [16] REGWNR -// -// 1: Write -// 0: Read -#define CPU_SCS_DCRSR_REGWNR 0x00010000 -#define CPU_SCS_DCRSR_REGWNR_BITN 16 -#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 -#define CPU_SCS_DCRSR_REGWNR_S 16 - -// Field: [4:0] REGSEL -// -// Register select -// -// 0x00: R0 -// 0x01: R1 -// 0x02: R2 -// 0x03: R3 -// 0x04: R4 -// 0x05: R5 -// 0x06: R6 -// 0x07: R7 -// 0x08: R8 -// 0x09: R9 -// 0x0A: R10 -// 0x0B: R11 -// 0x0C: R12 -// 0x0D: Current SP -// 0x0E: LR -// 0x0F: DebugReturnAddress -// 0x10: XPSR/flags, execution state information, and exception number -// 0x11: MSP (Main SP) -// 0x12: PSP (Process SP) -// 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK -#define CPU_SCS_DCRSR_REGSEL_W 5 -#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F -#define CPU_SCS_DCRSR_REGSEL_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_DCRDR -// -//***************************************************************************** -// Field: [31:0] DCRDR -// -// This register holds data for reading and writing registers to and from the -// processor. This is the data value written to the register selected by DCRSR. -// When the processor receives a request from DCRSR, this register is read or -// written by the processor using a normal load-store unit operation. If core -// register transfers are not being performed, software-based debug monitors -// can use this register for communication in non-halting debug. This enables -// flags and bits to acknowledge state and indicate if commands have been -// accepted to, replied to, or accepted and replied to. -#define CPU_SCS_DCRDR_DCRDR_W 32 -#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF -#define CPU_SCS_DCRDR_DCRDR_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_DEMCR -// -//***************************************************************************** -// Field: [24] TRCENA -// -// This bit must be set to 1 to enable use of the trace and debug blocks: DWT, -// ITM, ETM and TPIU. This enables control of power usage unless tracing is -// required. The application can enable this, for ITM use, or use by a -// debugger. -#define CPU_SCS_DEMCR_TRCENA 0x01000000 -#define CPU_SCS_DEMCR_TRCENA_BITN 24 -#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 -#define CPU_SCS_DEMCR_TRCENA_S 24 - -// Field: [19] MON_REQ -// -// This enables the monitor to identify how it wakes up. This bit clears on a -// Core Reset. -// -// 0x0: Woken up by debug exception. -// 0x1: Woken up by MON_PEND -#define CPU_SCS_DEMCR_MON_REQ 0x00080000 -#define CPU_SCS_DEMCR_MON_REQ_BITN 19 -#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 -#define CPU_SCS_DEMCR_MON_REQ_S 19 - -// Field: [18] MON_STEP -// -// When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. -// This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped -// according to the priority of the monitor and settings of PRIMASK, FAULTMASK, -// or BASEPRI. -#define CPU_SCS_DEMCR_MON_STEP 0x00040000 -#define CPU_SCS_DEMCR_MON_STEP_BITN 18 -#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 -#define CPU_SCS_DEMCR_MON_STEP_S 18 - -// Field: [17] MON_PEND -// -// Pend the monitor to activate when priority permits. This can wake up the -// monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for -// Monitor debug. This register does not reset on a system reset. It is only -// reset by a power-on reset. Software in the reset handler or later, or by the -// DAP must enable the debug monitor. -#define CPU_SCS_DEMCR_MON_PEND 0x00020000 -#define CPU_SCS_DEMCR_MON_PEND_BITN 17 -#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 -#define CPU_SCS_DEMCR_MON_PEND_S 17 - -// Field: [16] MON_EN -// -// Enable the debug monitor. -// When enabled, the System handler priority register controls its priority -// level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN -// overrides this bit. Vector catching is semi-synchronous. When a matching -// event is seen, a Halt is requested. Because the processor can only halt on -// an instruction boundary, it must wait until the next instruction boundary. -// As a result, it stops on the first instruction of the exception handler. -// However, two special cases exist when a vector catch has triggered: 1. If a -// fault is taken during vectoring, vector read or stack push error, the halt -// occurs on the corresponding fault handler, for the vector error or stack -// push. 2. If a late arriving interrupt comes in during vectoring, it is not -// taken. That is, an implementation that supports the late arrival -// optimization must suppress it in this case. -#define CPU_SCS_DEMCR_MON_EN 0x00010000 -#define CPU_SCS_DEMCR_MON_EN_BITN 16 -#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 -#define CPU_SCS_DEMCR_MON_EN_S 16 - -// Field: [10] VC_HARDERR -// -// Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 -#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 -#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 -#define CPU_SCS_DEMCR_VC_HARDERR_S 10 - -// Field: [9] VC_INTERR -// -// Debug trap on a fault occurring during an exception entry or return -// sequence. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 -#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 -#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 -#define CPU_SCS_DEMCR_VC_INTERR_S 9 - -// Field: [8] VC_BUSERR -// -// Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 -#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 -#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 -#define CPU_SCS_DEMCR_VC_BUSERR_S 8 - -// Field: [7] VC_STATERR -// -// Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is -// cleared. -#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 -#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 -#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 -#define CPU_SCS_DEMCR_VC_STATERR_S 7 - -// Field: [6] VC_CHKERR -// -// Debug trap on Usage Fault enabled checking errors. Ignored when -// DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 -#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 -#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 -#define CPU_SCS_DEMCR_VC_CHKERR_S 6 - -// Field: [5] VC_NOCPERR -// -// Debug trap on a UsageFault access to a Coprocessor. Ignored when -// DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 -#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 -#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 -#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 - -// Field: [4] VC_MMERR -// -// Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is -// cleared. -#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 -#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 -#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 -#define CPU_SCS_DEMCR_VC_MMERR_S 4 - -// Field: [0] VC_CORERESET -// -// Reset Vector Catch. Halt running system if Core reset occurs. Ignored when -// DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 -#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 -#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 -#define CPU_SCS_DEMCR_VC_CORERESET_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_STIR -// -//***************************************************************************** -// Field: [8:0] INTID -// -// Interrupt ID field. Writing a value to this bit-field is the same as -// manually pending an interrupt by setting the corresponding interrupt bit in -// an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. -#define CPU_SCS_STIR_INTID_W 9 -#define CPU_SCS_STIR_INTID_M 0x000001FF -#define CPU_SCS_STIR_INTID_S 0 - - -#endif // __CPU_SCS__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_cpu_tiprop.h b/third_party/ti/devices/cc26x0/inc/hw_cpu_tiprop.h deleted file mode 100644 index f06a1671b..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_cpu_tiprop.h +++ /dev/null @@ -1,83 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_tiprop_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_TIPROP_H__ -#define __HW_CPU_TIPROP_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_TIPROP component -// -//***************************************************************************** -// Internal -#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 - -// Internal -#define CPU_TIPROP_O_DYN_CG 0x00000FFC - -//***************************************************************************** -// -// Register: CPU_TIPROP_O_TRACECLKMUX -// -//***************************************************************************** -// Field: [0] TRACECLK_N_SWV -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// TRACECLK Internal. Only to be used through TI provided API. -// SWV Internal. Only to be used through TI provided API. -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 - -//***************************************************************************** -// -// Register: CPU_TIPROP_O_DYN_CG -// -//***************************************************************************** -// Field: [1:0] DYN_CG -// -// Internal. Only to be used through TI provided API. -#define CPU_TIPROP_DYN_CG_DYN_CG_W 2 -#define CPU_TIPROP_DYN_CG_DYN_CG_M 0x00000003 -#define CPU_TIPROP_DYN_CG_DYN_CG_S 0 - - -#endif // __CPU_TIPROP__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_cpu_tpiu.h b/third_party/ti/devices/cc26x0/inc/hw_cpu_tpiu.h deleted file mode 100644 index 27ee88446..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_cpu_tpiu.h +++ /dev/null @@ -1,347 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_tpiu_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_TPIU_H__ -#define __HW_CPU_TPIU_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_TPIU component -// -//***************************************************************************** -// Supported Sync Port Sizes -#define CPU_TPIU_O_SSPSR 0x00000000 - -// Current Sync Port Size -#define CPU_TPIU_O_CSPSR 0x00000004 - -// Async Clock Prescaler -#define CPU_TPIU_O_ACPR 0x00000010 - -// Selected Pin Protocol -#define CPU_TPIU_O_SPPR 0x000000F0 - -// Formatter and Flush Status -#define CPU_TPIU_O_FFSR 0x00000300 - -// Formatter and Flush Control -#define CPU_TPIU_O_FFCR 0x00000304 - -// Formatter Synchronization Counter -#define CPU_TPIU_O_FSCR 0x00000308 - -// Claim Tag Mask -#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 - -// Claim Tag Set -#define CPU_TPIU_O_CLAIMSET 0x00000FA0 - -// Current Claim Tag -#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 - -// Claim Tag Clear -#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 - -// Device ID -#define CPU_TPIU_O_DEVID 0x00000FC8 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_SSPSR -// -//***************************************************************************** -// Field: [3] FOUR -// -// 4-bit port size support -// -// 0x0: Not supported -// 0x1: Supported -#define CPU_TPIU_SSPSR_FOUR 0x00000008 -#define CPU_TPIU_SSPSR_FOUR_BITN 3 -#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 -#define CPU_TPIU_SSPSR_FOUR_S 3 - -// Field: [2] THREE -// -// 3-bit port size support -// -// 0x0: Not supported -// 0x1: Supported -#define CPU_TPIU_SSPSR_THREE 0x00000004 -#define CPU_TPIU_SSPSR_THREE_BITN 2 -#define CPU_TPIU_SSPSR_THREE_M 0x00000004 -#define CPU_TPIU_SSPSR_THREE_S 2 - -// Field: [1] TWO -// -// 2-bit port size support -// -// 0x0: Not supported -// 0x1: Supported -#define CPU_TPIU_SSPSR_TWO 0x00000002 -#define CPU_TPIU_SSPSR_TWO_BITN 1 -#define CPU_TPIU_SSPSR_TWO_M 0x00000002 -#define CPU_TPIU_SSPSR_TWO_S 1 - -// Field: [0] ONE -// -// 1-bit port size support -// -// 0x0: Not supported -// 0x1: Supported -#define CPU_TPIU_SSPSR_ONE 0x00000001 -#define CPU_TPIU_SSPSR_ONE_BITN 0 -#define CPU_TPIU_SSPSR_ONE_M 0x00000001 -#define CPU_TPIU_SSPSR_ONE_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_CSPSR -// -//***************************************************************************** -// Field: [3] FOUR -// -// 4-bit port enable -// Writing values with more than one bit set in CSPSR, or setting a bit that is -// not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_FOUR 0x00000008 -#define CPU_TPIU_CSPSR_FOUR_BITN 3 -#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 -#define CPU_TPIU_CSPSR_FOUR_S 3 - -// Field: [2] THREE -// -// 3-bit port enable -// Writing values with more than one bit set in CSPSR, or setting a bit that is -// not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_THREE 0x00000004 -#define CPU_TPIU_CSPSR_THREE_BITN 2 -#define CPU_TPIU_CSPSR_THREE_M 0x00000004 -#define CPU_TPIU_CSPSR_THREE_S 2 - -// Field: [1] TWO -// -// 2-bit port enable -// Writing values with more than one bit set in CSPSR, or setting a bit that is -// not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_TWO 0x00000002 -#define CPU_TPIU_CSPSR_TWO_BITN 1 -#define CPU_TPIU_CSPSR_TWO_M 0x00000002 -#define CPU_TPIU_CSPSR_TWO_S 1 - -// Field: [0] ONE -// -// 1-bit port enable -// Writing values with more than one bit set in CSPSR, or setting a bit that is -// not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_ONE 0x00000001 -#define CPU_TPIU_CSPSR_ONE_BITN 0 -#define CPU_TPIU_CSPSR_ONE_M 0x00000001 -#define CPU_TPIU_CSPSR_ONE_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_ACPR -// -//***************************************************************************** -// Field: [12:0] PRESCALER -// -// Divisor for input trace clock is (PRESCALER + 1). -#define CPU_TPIU_ACPR_PRESCALER_W 13 -#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF -#define CPU_TPIU_ACPR_PRESCALER_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_SPPR -// -//***************************************************************************** -// Field: [1:0] PROTOCOL -// -// Trace output protocol -// ENUMs: -// SWO_NRZ SerialWire Output (NRZ) -// SWO_MANCHESTER SerialWire Output (Manchester). This is the reset -// value. -// TRACEPORT TracePort mode -#define CPU_TPIU_SPPR_PROTOCOL_W 2 -#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 -#define CPU_TPIU_SPPR_PROTOCOL_S 0 -#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 -#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 -#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_FFSR -// -//***************************************************************************** -// Field: [3] FTNONSTOP -// -// 0: Formatter can be stopped -// 1: Formatter cannot be stopped -#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 -#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 -#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 -#define CPU_TPIU_FFSR_FTNONSTOP_S 3 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_FFCR -// -//***************************************************************************** -// Field: [8] TRIGIN -// -// Indicates that triggers are inserted when a trigger pin is asserted. -#define CPU_TPIU_FFCR_TRIGIN 0x00000100 -#define CPU_TPIU_FFCR_TRIGIN_BITN 8 -#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 -#define CPU_TPIU_FFCR_TRIGIN_S 8 - -// Field: [1] ENFCONT -// -// Enable continuous formatting: -// -// 0: Continuous formatting disabled -// 1: Continuous formatting enabled -#define CPU_TPIU_FFCR_ENFCONT 0x00000002 -#define CPU_TPIU_FFCR_ENFCONT_BITN 1 -#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 -#define CPU_TPIU_FFCR_ENFCONT_S 1 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_FSCR -// -//***************************************************************************** -// Field: [31:0] FSCR -// -// The global synchronization trigger is generated by the Program Counter (PC) -// Sampler block. This means that there is no synchronization counter in the -// TPIU. -#define CPU_TPIU_FSCR_FSCR_W 32 -#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF -#define CPU_TPIU_FSCR_FSCR_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_CLAIMMASK -// -//***************************************************************************** -// Field: [31:0] CLAIMMASK -// -// This register forms one half of the Claim Tag value. When reading this -// register returns the number of bits that can be set (each bit is considered -// separately): -// -// 0: This claim tag bit is not implemented -// 1: This claim tag bit is not implemented -// -// The behavior when writing to this register is described in CLAIMSET. -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_CLAIMSET -// -//***************************************************************************** -// Field: [31:0] CLAIMSET -// -// This register forms one half of the Claim Tag value. Writing to this -// location allows individual bits to be set (each bit is considered -// separately): -// -// 0: No effect -// 1: Set this bit in the claim tag -// -// The behavior when reading from this location is described in CLAIMMASK. -#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 -#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_CLAIMTAG -// -//***************************************************************************** -// Field: [31:0] CLAIMTAG -// -// This register forms one half of the Claim Tag value. Reading this register -// returns the current Claim Tag value. -// Reading CLAIMMASK determines how many bits from this register must be used. -// -// The behavior when writing to this register is described in CLAIMCLR. -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_CLAIMCLR -// -//***************************************************************************** -// Field: [31:0] CLAIMCLR -// -// This register forms one half of the Claim Tag value. Writing to this -// location enables individual bits to be cleared (each bit is considered -// separately): -// -// 0: No effect -// 1: Clear this bit in the claim tag. -// -// The behavior when reading from this location is described in CLAIMTAG. -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_DEVID -// -//***************************************************************************** -// Field: [31:0] DEVID -// -// This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no -// ETM present. -#define CPU_TPIU_DEVID_DEVID_W 32 -#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF -#define CPU_TPIU_DEVID_DEVID_S 0 - - -#endif // __CPU_TPIU__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_crypto.h b/third_party/ti/devices/cc26x0/inc/hw_crypto.h deleted file mode 100644 index 7971306fe..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_crypto.h +++ /dev/null @@ -1,1914 +0,0 @@ -/****************************************************************************** -* Filename: hw_crypto_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CRYPTO_H__ -#define __HW_CRYPTO_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CRYPTO component -// -//***************************************************************************** -// DMA Channel 0 Control -#define CRYPTO_O_DMACH0CTL 0x00000000 - -// DMA Channel 0 External Address -#define CRYPTO_O_DMACH0EXTADDR 0x00000004 - -// DMA Channel 0 Length -#define CRYPTO_O_DMACH0LEN 0x0000000C - -// DMA Controller Status -#define CRYPTO_O_DMASTAT 0x00000018 - -// DMA Controller Software Reset -#define CRYPTO_O_DMASWRESET 0x0000001C - -// DMA Channel 1 Control -#define CRYPTO_O_DMACH1CTL 0x00000020 - -// DMA Channel 1 External Address -#define CRYPTO_O_DMACH1EXTADDR 0x00000024 - -// DMA Channel 1 Length -#define CRYPTO_O_DMACH1LEN 0x0000002C - -// DMA Controller Master Configuration -#define CRYPTO_O_DMABUSCFG 0x00000078 - -// DMA Controller Port Error -#define CRYPTO_O_DMAPORTERR 0x0000007C - -// DMA Controller Version -#define CRYPTO_O_DMAHWVER 0x000000FC - -// Key Write Area -#define CRYPTO_O_KEYWRITEAREA 0x00000400 - -// Key Written Area Status -#define CRYPTO_O_KEYWRITTENAREA 0x00000404 - -// Key Size -#define CRYPTO_O_KEYSIZE 0x00000408 - -// Key Read Area -#define CRYPTO_O_KEYREADAREA 0x0000040C - -// Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY20 0x00000500 - -// Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY21 0x00000504 - -// Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY22 0x00000508 - -// Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY23 0x0000050C - -// Clear AES_KEY3 -#define CRYPTO_O_AESKEY30 0x00000510 - -// Clear AES_KEY3 -#define CRYPTO_O_AESKEY31 0x00000514 - -// Clear AES_KEY3 -#define CRYPTO_O_AESKEY32 0x00000518 - -// Clear AES_KEY3 -#define CRYPTO_O_AESKEY33 0x0000051C - -// AES Initialization Vector -#define CRYPTO_O_AESIV0 0x00000540 - -// AES Initialization Vector -#define CRYPTO_O_AESIV1 0x00000544 - -// AES Initialization Vector -#define CRYPTO_O_AESIV2 0x00000548 - -// AES Initialization Vector -#define CRYPTO_O_AESIV3 0x0000054C - -// AES Input/Output Buffer Control -#define CRYPTO_O_AESCTL 0x00000550 - -// Crypto Data Length LSW -#define CRYPTO_O_AESDATALEN0 0x00000554 - -// Crypto Data Length MSW -#define CRYPTO_O_AESDATALEN1 0x00000558 - -// AES Authentication Length -#define CRYPTO_O_AESAUTHLEN 0x0000055C - -// Data Input/Output -#define CRYPTO_O_AESDATAOUT0 0x00000560 - -// AES Data Input/Output 0 -#define CRYPTO_O_AESDATAIN0 0x00000560 - -// AES Data Input/Output 3 -#define CRYPTO_O_AESDATAOUT1 0x00000564 - -// AES Data Input/Output 1 -#define CRYPTO_O_AESDATAIN1 0x00000564 - -// AES Data Input/Output 2 -#define CRYPTO_O_AESDATAOUT2 0x00000568 - -// AES Data Input/Output 2 -#define CRYPTO_O_AESDATAIN2 0x00000568 - -// AES Data Input/Output 3 -#define CRYPTO_O_AESDATAOUT3 0x0000056C - -// Data Input/Output -#define CRYPTO_O_AESDATAIN3 0x0000056C - -// AES Tag Output -#define CRYPTO_O_AESTAGOUT0 0x00000570 - -// AES Tag Output -#define CRYPTO_O_AESTAGOUT1 0x00000574 - -// AES Tag Output -#define CRYPTO_O_AESTAGOUT2 0x00000578 - -// AES Tag Output -#define CRYPTO_O_AESTAGOUT3 0x0000057C - -// Master Algorithm Select -#define CRYPTO_O_ALGSEL 0x00000700 - -// Master Protection Control -#define CRYPTO_O_DMAPROTCTL 0x00000704 - -// Software Reset -#define CRYPTO_O_SWRESET 0x00000740 - -// Control Interrupt Configuration -#define CRYPTO_O_IRQTYPE 0x00000780 - -// Interrupt Enable -#define CRYPTO_O_IRQEN 0x00000784 - -// Interrupt Clear -#define CRYPTO_O_IRQCLR 0x00000788 - -// Interrupt Set -#define CRYPTO_O_IRQSET 0x0000078C - -// Interrupt Status -#define CRYPTO_O_IRQSTAT 0x00000790 - -// CTRL Module Version -#define CRYPTO_O_HWVER 0x000007FC - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH0CTL -// -//***************************************************************************** -// Field: [1] PRIO -// -// Channel priority: -// -// A channel with high priority will be served before a channel with low -// priority in cases with simultaneous access requests. If both channels have -// the same priority access of the channels to the external port is arbitrated -// using a Round Robin scheme. -// ENUMs: -// HIGH Priority high -// LOW Priority low -#define CRYPTO_DMACH0CTL_PRIO 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_BITN 1 -#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_S 1 -#define CRYPTO_DMACH0CTL_PRIO_HIGH 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_LOW 0x00000000 - -// Field: [0] EN -// -// DMA Channel 0 Control -// ENUMs: -// EN Channel enabled -// DIS Channel disabled -#define CRYPTO_DMACH0CTL_EN 0x00000001 -#define CRYPTO_DMACH0CTL_EN_BITN 0 -#define CRYPTO_DMACH0CTL_EN_M 0x00000001 -#define CRYPTO_DMACH0CTL_EN_S 0 -#define CRYPTO_DMACH0CTL_EN_EN 0x00000001 -#define CRYPTO_DMACH0CTL_EN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH0EXTADDR -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Channel external address value. -// Holds the last updated external address after being sent to the master -// interface. -#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 -#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF -#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH0LEN -// -//***************************************************************************** -// Field: [15:0] LEN -// -// DMA transfer length in bytes. -// During configuration, this register contains the DMA transfer length in -// bytes. During operation, it contains the last updated value of the DMA -// transfer length after being sent to the master interface. -// Note: Writing a non-zero value to this register field starts the transfer if -// the channel is enabled by setting DMACH0CTL.EN. -#define CRYPTO_DMACH0LEN_LEN_W 16 -#define CRYPTO_DMACH0LEN_LEN_M 0x0000FFFF -#define CRYPTO_DMACH0LEN_LEN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMASTAT -// -//***************************************************************************** -// Field: [17] PORT_ERR -// -// Reflects possible transfer errors on the AHB port. -#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 -#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 -#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 -#define CRYPTO_DMASTAT_PORT_ERR_S 17 - -// Field: [1] CH1_ACTIVE -// -// This register field indicates if DMA channel 1 is active or not. -// 0: Not active -// 1: Active -#define CRYPTO_DMASTAT_CH1_ACTIVE 0x00000002 -#define CRYPTO_DMASTAT_CH1_ACTIVE_BITN 1 -#define CRYPTO_DMASTAT_CH1_ACTIVE_M 0x00000002 -#define CRYPTO_DMASTAT_CH1_ACTIVE_S 1 - -// Field: [0] CH0_ACTIVE -// -// This register field indicates if DMA channel 0 is active or not. -// 0: Not active -// 1: Active -#define CRYPTO_DMASTAT_CH0_ACTIVE 0x00000001 -#define CRYPTO_DMASTAT_CH0_ACTIVE_BITN 0 -#define CRYPTO_DMASTAT_CH0_ACTIVE_M 0x00000001 -#define CRYPTO_DMASTAT_CH0_ACTIVE_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMASWRESET -// -//***************************************************************************** -// Field: [0] RESET -// -// Software reset enable -// -// 0: Disable -// 1: Enable (self-cleared to zero). -// -// Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE -// and DMASTAT.CH1_ACTIVE. -#define CRYPTO_DMASWRESET_RESET 0x00000001 -#define CRYPTO_DMASWRESET_RESET_BITN 0 -#define CRYPTO_DMASWRESET_RESET_M 0x00000001 -#define CRYPTO_DMASWRESET_RESET_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH1CTL -// -//***************************************************************************** -// Field: [1] PRIO -// -// Channel priority: -// -// A channel with high priority will be served before a channel with low -// priority in cases with simultaneous access requests. If both channels have -// the same priority access of the channels to the external port is arbitrated -// using a Round Robin scheme. -// ENUMs: -// HIGH Priority high -// LOW Priority low -#define CRYPTO_DMACH1CTL_PRIO 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_BITN 1 -#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_S 1 -#define CRYPTO_DMACH1CTL_PRIO_HIGH 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_LOW 0x00000000 - -// Field: [0] EN -// -// Channel enable: -// -// Note: Disabling an active channel will interrupt the DMA operation. The -// ongoing block transfer will be completed, but no new transfers will be -// requested. -// ENUMs: -// EN Channel enabled -// DIS Channel disabled -#define CRYPTO_DMACH1CTL_EN 0x00000001 -#define CRYPTO_DMACH1CTL_EN_BITN 0 -#define CRYPTO_DMACH1CTL_EN_M 0x00000001 -#define CRYPTO_DMACH1CTL_EN_S 0 -#define CRYPTO_DMACH1CTL_EN_EN 0x00000001 -#define CRYPTO_DMACH1CTL_EN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH1EXTADDR -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Channel external address value. -// Holds the last updated external address after being sent to the master -// interface. -#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 -#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF -#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH1LEN -// -//***************************************************************************** -// Field: [15:0] LEN -// -// DMA transfer length in bytes. -// During configuration, this register contains the DMA transfer length in -// bytes. During operation, it contains the last updated value of the DMA -// transfer length after being sent to the master interface. -// Note: Writing a non-zero value to this register field starts the transfer if -// the channel is enabled by setting DMACH1CTL.EN. -#define CRYPTO_DMACH1LEN_LEN_W 16 -#define CRYPTO_DMACH1LEN_LEN_M 0x0000FFFF -#define CRYPTO_DMACH1LEN_LEN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMABUSCFG -// -//***************************************************************************** -// Field: [15:12] AHB_MST1_BURST_SIZE -// -// Maximum burst size that can be performed on the AHB bus -// ENUMs: -// 64_BYTE 64 bytes -// 32_BYTE 32 bytes -// 16_BYTE 16 bytes -// 8_BYTE 8 bytes -// 4_BYTE 4 bytes -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 - -// Field: [11] AHB_MST1_IDLE_EN -// -// Idle transfer insertion between consecutive burst transfers on AHB -// ENUMs: -// IDLE Idle transfer insertion enabled -// NO_IDLE Do not insert idle transfers. -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 - -// Field: [10] AHB_MST1_INCR_EN -// -// Burst length type of AHB transfer -// ENUMs: -// SPECIFIED Fixed length bursts or single transfers -// UNSPECIFIED Unspecified length burst transfers -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 - -// Field: [9] AHB_MST1_LOCK_EN -// -// Locked transform on AHB -// ENUMs: -// LOCKED Transfers are locked -// NOT_LOCKED Transfers are not locked -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 - -// Field: [8] AHB_MST1_BIGEND -// -// Endianess for the AHB master -// ENUMs: -// BIG_ENDIAN Big Endian -// LITTLE_ENDIAN Little Endian -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMAPORTERR -// -//***************************************************************************** -// Field: [12] AHB_ERR -// -// A 1 indicates that the Crypto peripheral has detected an AHB bus error -#define CRYPTO_DMAPORTERR_AHB_ERR 0x00001000 -#define CRYPTO_DMAPORTERR_AHB_ERR_BITN 12 -#define CRYPTO_DMAPORTERR_AHB_ERR_M 0x00001000 -#define CRYPTO_DMAPORTERR_AHB_ERR_S 12 - -// Field: [9] LAST_CH -// -// Indicates which channel was serviced last (channel 0 or channel 1) by the -// AHB master port. -#define CRYPTO_DMAPORTERR_LAST_CH 0x00000200 -#define CRYPTO_DMAPORTERR_LAST_CH_BITN 9 -#define CRYPTO_DMAPORTERR_LAST_CH_M 0x00000200 -#define CRYPTO_DMAPORTERR_LAST_CH_S 9 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMAHWVER -// -//***************************************************************************** -// Field: [27:24] HW_MAJOR_VER -// -// Major version number -#define CRYPTO_DMAHWVER_HW_MAJOR_VER_W 4 -#define CRYPTO_DMAHWVER_HW_MAJOR_VER_M 0x0F000000 -#define CRYPTO_DMAHWVER_HW_MAJOR_VER_S 24 - -// Field: [23:20] HW_MINOR_VER -// -// Minor version number -#define CRYPTO_DMAHWVER_HW_MINOR_VER_W 4 -#define CRYPTO_DMAHWVER_HW_MINOR_VER_M 0x00F00000 -#define CRYPTO_DMAHWVER_HW_MINOR_VER_S 20 - -// Field: [19:16] HW_PATCH_LVL -// -// Patch level. -#define CRYPTO_DMAHWVER_HW_PATCH_LVL_W 4 -#define CRYPTO_DMAHWVER_HW_PATCH_LVL_M 0x000F0000 -#define CRYPTO_DMAHWVER_HW_PATCH_LVL_S 16 - -// Field: [15:8] VER_NUM_COMPL -// -// Bit-by-bit complement of the VER_NUM field bits. -#define CRYPTO_DMAHWVER_VER_NUM_COMPL_W 8 -#define CRYPTO_DMAHWVER_VER_NUM_COMPL_M 0x0000FF00 -#define CRYPTO_DMAHWVER_VER_NUM_COMPL_S 8 - -// Field: [7:0] VER_NUM -// -// Version number of the DMA Controller (209) -#define CRYPTO_DMAHWVER_VER_NUM_W 8 -#define CRYPTO_DMAHWVER_VER_NUM_M 0x000000FF -#define CRYPTO_DMAHWVER_VER_NUM_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_KEYWRITEAREA -// -//***************************************************************************** -// Field: [7] RAM_AREA7 -// -// Represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written. -// -// Writing to multiple RAM locations is only possible when the selected RAM -// areas are sequential. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 - -// Field: [6] RAM_AREA6 -// -// Represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written. -// -// Writing to multiple RAM locations is only possible when the selected RAM -// areas are sequential. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 - -// Field: [5] RAM_AREA5 -// -// Represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written. -// -// Writing to multiple RAM locations is only possible when the selected RAM -// areas are sequential. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 - -// Field: [4] RAM_AREA4 -// -// Represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written. -// -// Writing to multiple RAM locations is only possible when the selected RAM -// areas are sequential. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 - -// Field: [3] RAM_AREA3 -// -// Represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written. -// -// Writing to multiple RAM locations is only possible when the selected RAM -// areas are sequential. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 - -// Field: [2] RAM_AREA2 -// -// Represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written. -// -// Writing to multiple RAM locations is only possible when the selected RAM -// areas are sequential. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 - -// Field: [1] RAM_AREA1 -// -// Represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written. -// -// Writing to multiple RAM locations is only possible when the selected RAM -// areas are sequential. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 - -// Field: [0] RAM_AREA0 -// -// Represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written. -// -// Writing to multiple RAM locations is only possible when the selected RAM -// areas are sequential. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 - -//***************************************************************************** -// -// Register: CRYPTO_O_KEYWRITTENAREA -// -//***************************************************************************** -// Field: [7] RAM_AREA_WRITTEN7 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 - -// Field: [6] RAM_AREA_WRITTEN6 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 - -// Field: [5] RAM_AREA_WRITTEN5 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 - -// Field: [4] RAM_AREA_WRITTEN4 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 - -// Field: [3] RAM_AREA_WRITTEN3 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 - -// Field: [2] RAM_AREA_WRITTEN2 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 - -// Field: [1] RAM_AREA_WRITTEN1 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 - -// Field: [0] RAM_AREA_WRITTEN0 -// -// On read this bit returns the key area written status. -// -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_WRITTEN 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_NOT_WRITTEN 0x00000000 - -//***************************************************************************** -// -// Register: CRYPTO_O_KEYSIZE -// -//***************************************************************************** -// Field: [1:0] SIZE -// -// Key size -// -// When writing to this register, KEYWRITTENAREA will be reset. -// -// Note: For the Crypto peripheral this field is fixed to 128 bits. For -// software compatibility KEYWRITTENAREA will be reset when writing to this -// register. -// ENUMs: -// 256_BIT Not supported -// 192_BIT Not supported -// 128_BIT 128 bits -#define CRYPTO_KEYSIZE_SIZE_W 2 -#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 -#define CRYPTO_KEYSIZE_SIZE_S 0 -#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 -#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 -#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 - -//***************************************************************************** -// -// Register: CRYPTO_O_KEYREADAREA -// -//***************************************************************************** -// Field: [31] BUSY -// -// Key store operation busy status flag (read only) -// -// 0: operation is completed. -// 1: operation is not completed and the key store is busy. -#define CRYPTO_KEYREADAREA_BUSY 0x80000000 -#define CRYPTO_KEYREADAREA_BUSY_BITN 31 -#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 -#define CRYPTO_KEYREADAREA_BUSY_S 31 - -// Field: [3:0] RAM_AREA -// -// Selects the area of the key store RAM from where the key needs to be read -// that will be written to the AES engine. -// -// Only RAM areas that contain valid written keys can be selected. -// ENUMs: -// NO_RAM No RAM -// RAM_AREA7 RAM Area 7 -// RAM_AREA6 RAM Area 6 -// RAM_AREA5 RAM Area 5 -// RAM_AREA4 RAM Area 4 -// RAM_AREA3 RAM Area 3 -// RAM_AREA2 RAM Area 2 -// RAM_AREA1 RAM Area 1 -// RAM_AREA0 RAM Area 0 -#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 -#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F -#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 -#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY20 -// -//***************************************************************************** -// Field: [31:0] KEY2 -// -// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, -// 96 ordered from the LSW entry of this 4-deep register array. -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY20_KEY2_W 32 -#define CRYPTO_AESKEY20_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY20_KEY2_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY21 -// -//***************************************************************************** -// Field: [31:0] KEY2 -// -// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, -// 96 ordered from the LSW entry of this 4-deep register array. -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY21_KEY2_W 32 -#define CRYPTO_AESKEY21_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY21_KEY2_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY22 -// -//***************************************************************************** -// Field: [31:0] KEY2 -// -// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, -// 96 ordered from the LSW entry of this 4-deep register array. -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY22_KEY2_W 32 -#define CRYPTO_AESKEY22_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY22_KEY2_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY23 -// -//***************************************************************************** -// Field: [31:0] KEY2 -// -// AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, -// 96 ordered from the LSW entry of this 4-deep register array. -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY23_KEY2_W 32 -#define CRYPTO_AESKEY23_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY23_KEY2_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY30 -// -//***************************************************************************** -// Field: [31:0] KEY3 -// -// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, -// 96 ordered from the LSW entry of this 4-deep register arrary. -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY30_KEY3_W 32 -#define CRYPTO_AESKEY30_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY30_KEY3_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY31 -// -//***************************************************************************** -// Field: [31:0] KEY3 -// -// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, -// 96 ordered from the LSW entry of this 4-deep register arrary. -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY31_KEY3_W 32 -#define CRYPTO_AESKEY31_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY31_KEY3_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY32 -// -//***************************************************************************** -// Field: [31:0] KEY3 -// -// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, -// 96 ordered from the LSW entry of this 4-deep register arrary. -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY32_KEY3_W 32 -#define CRYPTO_AESKEY32_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY32_KEY3_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY33 -// -//***************************************************************************** -// Field: [31:0] KEY3 -// -// AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, -// 96 ordered from the LSW entry of this 4-deep register arrary. -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY33_KEY3_W 32 -#define CRYPTO_AESKEY33_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY33_KEY3_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESIV0 -// -//***************************************************************************** -// Field: [31:0] IV -// -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV0_IV_W 32 -#define CRYPTO_AESIV0_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV0_IV_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESIV1 -// -//***************************************************************************** -// Field: [31:0] IV -// -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV1_IV_W 32 -#define CRYPTO_AESIV1_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV1_IV_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESIV2 -// -//***************************************************************************** -// Field: [31:0] IV -// -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV2_IV_W 32 -#define CRYPTO_AESIV2_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV2_IV_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESIV3 -// -//***************************************************************************** -// Field: [31:0] IV -// -// The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV3_IV_W 32 -#define CRYPTO_AESIV3_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV3_IV_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESCTL -// -//***************************************************************************** -// Field: [31] CONTEXT_RDY -// -// If 1, this status bit indicates that the context data registers can be -// overwritten and the Host is permitted to write the next context. Writing a -// context means writing either a mode, the crypto length or -// AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers -#define CRYPTO_AESCTL_CONTEXT_RDY 0x80000000 -#define CRYPTO_AESCTL_CONTEXT_RDY_BITN 31 -#define CRYPTO_AESCTL_CONTEXT_RDY_M 0x80000000 -#define CRYPTO_AESCTL_CONTEXT_RDY_S 31 - -// Field: [30] SAVED_CONTEXT_RDY -// -// If read as 1, this status bit indicates that an AES authentication TAG -// and/or IV block(s) is/are available for the Host to retrieve. This bit is -// only asserted if SAVE_CONTEXT is set to 1. The bit is mutually exclusive -// with CONTEXT_RDY. -// -// Writing 1 clears the bit to zero, indicating the Crypto peripheral can start -// its next operation. This bit is also cleared when the 4th word of the output -// TAG and/or IV is read. -// -// Note: All other mode bit writes will be ignored when this mode bit is -// written with 1. -// -// Note: This bit is controlled automatically by the Crypto peripheral for TAG -// read DMA operations. -// -// For typical use, this bit does NOT need to be written, but is used for -// status reading only. In this case, this status bit is automatically -// maintained by the Crypto peripheral. -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 - -// Field: [29] SAVE_CONTEXT -// -// IV must be read before the AES engine can start a new operation. -#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 -#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 -#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 -#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 - -// Field: [24:22] CCM_M -// -// Defines M that indicates the length of the authentication field for CCM -// operations; the authentication field length equals two times the value of -// CCM_M plus one. -// Note: The Crypto peripheral always returns a 128-bit authentication field, -// of which the M least significant bytes are valid. All values are supported. -#define CRYPTO_AESCTL_CCM_M_W 3 -#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 -#define CRYPTO_AESCTL_CCM_M_S 22 - -// Field: [21:19] CCM_L -// -// Defines L that indicates the width of the length field for CCM operations; -// the length field in bytes equals the value of CMM_L plus one. All values are -// supported. -#define CRYPTO_AESCTL_CCM_L_W 3 -#define CRYPTO_AESCTL_CCM_L_M 0x00380000 -#define CRYPTO_AESCTL_CCM_L_S 19 - -// Field: [18] CCM -// -// AES-CCM mode enable. -// AES-CCM is a combined mode, using AES for both authentication and -// encryption. -// Note: Selecting AES-CCM mode requires writing of AESDATALEN1.LEN_MSW and -// AESDATALEN0.LEN_LSW after all other registers. -// Note: The CTR mode bit in this register must also be set to 1 to enable -// AES-CTR; selecting other AES modes than CTR mode is invalid. -#define CRYPTO_AESCTL_CCM 0x00040000 -#define CRYPTO_AESCTL_CCM_BITN 18 -#define CRYPTO_AESCTL_CCM_M 0x00040000 -#define CRYPTO_AESCTL_CCM_S 18 - -// Field: [15] CBC_MAC -// -// MAC mode enable. -// The DIR bit must be set to 1 for this mode. -// Selecting this mode requires writing the AESDATALEN1.LEN_MSW and -// AESDATALEN0.LEN_LSW registers after all other registers. -#define CRYPTO_AESCTL_CBC_MAC 0x00008000 -#define CRYPTO_AESCTL_CBC_MAC_BITN 15 -#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 -#define CRYPTO_AESCTL_CBC_MAC_S 15 - -// Field: [8:7] CTR_WIDTH -// -// Specifies the counter width for AES-CTR mode -// ENUMs: -// 128_BIT 128 bits -// 96_BIT 96 bits -// 64_BIT 64 bits -// 32_BIT 32 bits -#define CRYPTO_AESCTL_CTR_WIDTH_W 2 -#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 -#define CRYPTO_AESCTL_CTR_WIDTH_S 7 -#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 -#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 -#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 -#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 - -// Field: [6] CTR -// -// AES-CTR mode enable -// This bit must also be set for CCM, when encryption/decryption is required. -#define CRYPTO_AESCTL_CTR 0x00000040 -#define CRYPTO_AESCTL_CTR_BITN 6 -#define CRYPTO_AESCTL_CTR_M 0x00000040 -#define CRYPTO_AESCTL_CTR_S 6 - -// Field: [5] CBC -// -// CBC mode enable -#define CRYPTO_AESCTL_CBC 0x00000020 -#define CRYPTO_AESCTL_CBC_BITN 5 -#define CRYPTO_AESCTL_CBC_M 0x00000020 -#define CRYPTO_AESCTL_CBC_S 5 - -// Field: [4:3] KEY_SIZE -// -// This field specifies the key size. -// The key size is automatically configured when a new key is loaded via the -// key store module. -// 00 = N/A - reserved -// 01 = 128 bits -// 10 = N/A - reserved -// 11 = N/A - reserved -// For the Crypto peripheral this field is fixed to 128 bits. -#define CRYPTO_AESCTL_KEY_SIZE_W 2 -#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 -#define CRYPTO_AESCTL_KEY_SIZE_S 3 - -// Field: [2] DIR -// -// Direction. -// 0 : Decrypt operation is performed. -// 1 : Encrypt operation is performed. -// -// This bit must be written with a 1 when CBC-MAC is selected. -#define CRYPTO_AESCTL_DIR 0x00000004 -#define CRYPTO_AESCTL_DIR_BITN 2 -#define CRYPTO_AESCTL_DIR_M 0x00000004 -#define CRYPTO_AESCTL_DIR_S 2 - -// Field: [1] INPUT_RDY -// -// If read as 1, this status bit indicates that the 16-byte AES input buffer is -// empty. The Host is permitted to write the next block of data. -// -// Writing a 0 clears the bit to zero and indicates that the AES engine can use -// the provided input data block. -// -// Writing a 1 to this bit will be ignored. -// -// Note: For DMA operations, this bit is automatically controlled by the Crypto -// peripheral. -// After reset, this bit is 0. After writing a context (note 1), this bit will -// become 1. -// -// For typical use, this bit does NOT need to be written, but is used for -// status reading only. In this case, this status bit is automatically -// maintained by the Crypto peripheral. -#define CRYPTO_AESCTL_INPUT_RDY 0x00000002 -#define CRYPTO_AESCTL_INPUT_RDY_BITN 1 -#define CRYPTO_AESCTL_INPUT_RDY_M 0x00000002 -#define CRYPTO_AESCTL_INPUT_RDY_S 1 - -// Field: [0] OUTPUT_RDY -// -// If read as 1, this status bit indicates that an AES output block is -// available to be retrieved by the Host. -// -// Writing a 0 clears the bit to zero and indicates that output data is read by -// the Host. The AES engine can provide a next output data block. -// -// Writing a 1 to this bit will be ignored. -// -// Note: For DMA operations, this bit is automatically controlled by the Crypto -// peripheral. -// -// For typical use, this bit does NOT need to be written, but is used for -// status reading only. In this case, this status bit is automatically -// maintained by the Crypto peripheral. -#define CRYPTO_AESCTL_OUTPUT_RDY 0x00000001 -#define CRYPTO_AESCTL_OUTPUT_RDY_BITN 0 -#define CRYPTO_AESCTL_OUTPUT_RDY_M 0x00000001 -#define CRYPTO_AESCTL_OUTPUT_RDY_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATALEN0 -// -//***************************************************************************** -// Field: [31:0] LEN_LSW -// -// Used to write the Length values to the Crypto peripheral. -// -// This register contains bits [31:0] of the combined data length. -#define CRYPTO_AESDATALEN0_LEN_LSW_W 32 -#define CRYPTO_AESDATALEN0_LEN_LSW_M 0xFFFFFFFF -#define CRYPTO_AESDATALEN0_LEN_LSW_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATALEN1 -// -//***************************************************************************** -// Field: [28:0] LEN_MSW -// -// Bits [60:32] of the combined data length. -// -// Bits [60:0] of the crypto length registers AESDATALEN1 and AESDATALEN0 store -// the cryptographic data length in bytes for all modes. Once processing with -// this context is started, this length decrements to zero. Data lengths up to -// (2^61 - 1) bytes are allowed. -// For GCM, any value up to 2^36 - 32 bytes can be used. This is because a -// 32-bit counter mode is used; the maximum number of 128-bit blocks is 2^32 - -// 2, resulting in a maximum number of bytes of 2^36 - 32. -// Writing to this register triggers the engine to start using this context. -// This is valid for all modes except GCM and CCM. -// Note: For the combined modes (GCM and CCM), this length does not include the -// authentication only data; the authentication length is specified in the -// AESAUTHLEN.LEN. -// All modes must have a length > 0. For the combined modes, it is allowed to -// have one of the lengths equal to zero. -// For the basic encryption modes (ECB/CBC/CTR) it is allowed to program zero -// to the length field; in that case the length is assumed infinite. -// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned -// data streams are not supported by the Crypto peripheral. For block cipher -// modes, the data length must be programmed in multiples of the block cipher -// size, 16 bytes. -#define CRYPTO_AESDATALEN1_LEN_MSW_W 29 -#define CRYPTO_AESDATALEN1_LEN_MSW_M 0x1FFFFFFF -#define CRYPTO_AESDATALEN1_LEN_MSW_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESAUTHLEN -// -//***************************************************************************** -// Field: [31:0] LEN -// -// Authentication data length in bytes for combined mode, CCM only. -// Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes. Once -// processing with this context is started, this length decrements to zero. -// Writing this register triggers the engine to start using this context for -// CCM. -#define CRYPTO_AESAUTHLEN_LEN_W 32 -#define CRYPTO_AESAUTHLEN_LEN_M 0xFFFFFFFF -#define CRYPTO_AESAUTHLEN_LEN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAOUT0 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data register 0 for output block data from the Crypto peripheral. -// These bits = AES Output Data[31:0] of {127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range will read one word (4 bytes) of data out the 4-word deep -// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one -// full block) should be read before the core will move the next block to the -// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must -// be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAOUT0_DATA_W 32 -#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT0_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAIN0 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data registers for input block data to the Crypto peripheral. -// These bits = AES Input Data[31:0] of [127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host write operation, these registers must be written with the 128-bit -// input block for the next AES operation. Writing at a word-aligned offset -// within this address range will store the word (4 bytes) of data into the -// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data -// input buffer. This buffer is used for the next AES operation. If the last -// data block is not completely filled with valid data (see notes below), it is -// allowed to write only the words with valid data. Next AES operation is -// triggered by writing to AESCTL.INPUT_RDY. -// -// Note: AES typically operates on 128 bits block multiple input data. The CTR, -// GCM and CCM modes form an exception. The last block of a CTR-mode message -// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. -// For GCM/CCM, the last block of both AAD and message data may contain less -// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically -// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and -// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is -// ignored. -#define CRYPTO_AESDATAIN0_DATA_W 32 -#define CRYPTO_AESDATAIN0_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN0_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAOUT1 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data registers for output block data from the Crypto peripheral. -// These bits = AES Output Data[63:32] of [127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range will read one word (4 bytes) of data out the 4-word deep -// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one -// full block) should be read before the core will move the next block to the -// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must -// be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAOUT1_DATA_W 32 -#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT1_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAIN1 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data registers for input block data to the Crypto peripheral. -// These bits = AES Input Data[63:32] of [127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host write operation, these registers must be written with the 128-bit -// input block for the next AES operation. Writing at a word-aligned offset -// within this address range will store the word (4 bytes) of data into the -// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data -// input buffer. This buffer is used for the next AES operation. If the last -// data block is not completely filled with valid data (see notes below), it is -// allowed to write only the words with valid data. Next AES operation is -// triggered by writing to AESCTL.INPUT_RDY. -// -// Note: AES typically operates on 128 bits block multiple input data. The CTR, -// GCM and CCM modes form an exception. The last block of a CTR-mode message -// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. -// For GCM/CCM, the last block of both AAD and message data may contain less -// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically -// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and -// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is -// ignored. -#define CRYPTO_AESDATAIN1_DATA_W 32 -#define CRYPTO_AESDATAIN1_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN1_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAOUT2 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data registers for output block data from the Crypto peripheral. -// These bits = AES Output Data[95:64] of [127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range will read one word (4 bytes) of data out the 4-word deep -// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one -// full block) should be read before the core will move the next block to the -// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must -// be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAOUT2_DATA_W 32 -#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT2_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAIN2 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data registers for input block data to the Crypto peripheral. -// These bits = AES Input Data[95:64] of [127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host write operation, these registers must be written with the 128-bit -// input block for the next AES operation. Writing at a word-aligned offset -// within this address range will store the word (4 bytes) of data into the -// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data -// input buffer. This buffer is used for the next AES operation. If the last -// data block is not completely filled with valid data (see notes below), it is -// allowed to write only the words with valid data. Next AES operation is -// triggered by writing to AESCTL.INPUT_RDY. -// -// Note: AES typically operates on 128 bits block multiple input data. The CTR, -// GCM and CCM modes form an exception. The last block of a CTR-mode message -// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. -// For GCM/CCM, the last block of both AAD and message data may contain less -// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically -// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and -// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is -// ignored. -#define CRYPTO_AESDATAIN2_DATA_W 32 -#define CRYPTO_AESDATAIN2_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN2_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAOUT3 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data registers for output block data from the Crypto peripheral. -// These bits = AES Output Data[127:96] of [127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range will read one word (4 bytes) of data out the 4-word deep -// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one -// full block) should be read before the core will move the next block to the -// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must -// be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAOUT3_DATA_W 32 -#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT3_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAIN3 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data registers for input block data to the Crypto peripheral. -// These bits = AES Input Data[127:96] of [127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host write operation, these registers must be written with the 128-bit -// input block for the next AES operation. Writing at a word-aligned offset -// within this address range will store the word (4 bytes) of data into the -// corresponding position of 4-word deep (16 bytes = 128-bit AES block) data -// input buffer. This buffer is used for the next AES operation. If the last -// data block is not completely filled with valid data (see notes below), it is -// allowed to write only the words with valid data. Next AES operation is -// triggered by writing to AESCTL.INPUT_RDY. -// -// Note: AES typically operates on 128 bits block multiple input data. The CTR, -// GCM and CCM modes form an exception. The last block of a CTR-mode message -// may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. -// For GCM/CCM, the last block of both AAD and message data may contain less -// than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically -// pads or masks misaligned ending data blocks with zeroes for GCM, CCM and -// CBC-MAC. For CTR mode, the remaining data in an unaligned data block is -// ignored. -#define CRYPTO_AESDATAIN3_DATA_W 32 -#define CRYPTO_AESDATAIN3_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN3_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESTAGOUT0 -// -//***************************************************************************** -// Field: [31:0] TAG -// -// This register contains the authentication TAG for the combined and -// authentication-only modes. -#define CRYPTO_AESTAGOUT0_TAG_W 32 -#define CRYPTO_AESTAGOUT0_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT0_TAG_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESTAGOUT1 -// -//***************************************************************************** -// Field: [31:0] TAG -// -// This register contains the authentication TAG for the combined and -// authentication-only modes. -#define CRYPTO_AESTAGOUT1_TAG_W 32 -#define CRYPTO_AESTAGOUT1_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT1_TAG_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESTAGOUT2 -// -//***************************************************************************** -// Field: [31:0] TAG -// -// This register contains the authentication TAG for the combined and -// authentication-only modes. -#define CRYPTO_AESTAGOUT2_TAG_W 32 -#define CRYPTO_AESTAGOUT2_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT2_TAG_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESTAGOUT3 -// -//***************************************************************************** -// Field: [31:0] TAG -// -// This register contains the authentication TAG for the combined and -// authentication-only modes. -#define CRYPTO_AESTAGOUT3_TAG_W 32 -#define CRYPTO_AESTAGOUT3_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT3_TAG_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_ALGSEL -// -//***************************************************************************** -// Field: [31] TAG -// -// If this bit is cleared to 0, the DMA operation involves only data. -// If this bit is set, the DMA operation includes a TAG (Authentication Result -// / Digest). -#define CRYPTO_ALGSEL_TAG 0x80000000 -#define CRYPTO_ALGSEL_TAG_BITN 31 -#define CRYPTO_ALGSEL_TAG_M 0x80000000 -#define CRYPTO_ALGSEL_TAG_S 31 - -// Field: [1] AES -// -// If set to 1, the AES data is loaded via DMA -// Both Read and Write maximum transfer size to DMA engine is set to 16 bytes -#define CRYPTO_ALGSEL_AES 0x00000002 -#define CRYPTO_ALGSEL_AES_BITN 1 -#define CRYPTO_ALGSEL_AES_M 0x00000002 -#define CRYPTO_ALGSEL_AES_S 1 - -// Field: [0] KEY_STORE -// -// If set to 1, selects the Key Store to be loaded via DMA. -// The maximum transfer size to DMA engine is set to 32 bytes (however -// transfers of 16, 24 and 32 bytes are allowed) -#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 -#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 -#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 -#define CRYPTO_ALGSEL_KEY_STORE_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMAPROTCTL -// -//***************************************************************************** -// Field: [0] EN -// -// Select AHB transfer protection control for DMA transfers using the key store -// area as destination. -// 0 : transfers use 'USER' type access. -// 1 : transfers use 'PRIVILEGED' type access. -#define CRYPTO_DMAPROTCTL_EN 0x00000001 -#define CRYPTO_DMAPROTCTL_EN_BITN 0 -#define CRYPTO_DMAPROTCTL_EN_M 0x00000001 -#define CRYPTO_DMAPROTCTL_EN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_SWRESET -// -//***************************************************************************** -// Field: [0] RESET -// -// If this bit is set to 1, the following modules are reset: -// - Master control internal state is reset. That includes interrupt, error -// status register and result available interrupt generation FSM. -// - Key store module state is reset. That includes clearing the Written Area -// flags; therefore the keys must be reloaded to the key store module. -// Writing 0 has no effect. -// The bit is self cleared after executing the reset. -#define CRYPTO_SWRESET_RESET 0x00000001 -#define CRYPTO_SWRESET_RESET_BITN 0 -#define CRYPTO_SWRESET_RESET_M 0x00000001 -#define CRYPTO_SWRESET_RESET_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_IRQTYPE -// -//***************************************************************************** -// Field: [0] LEVEL -// -// If this bit is 0, the interrupt output is a pulse. -// If this bit is set to 1, the interrupt is a level interrupt that must be -// cleared by writing the interrupt clear register. -// This bit is applicable for both interrupt output signals. -#define CRYPTO_IRQTYPE_LEVEL 0x00000001 -#define CRYPTO_IRQTYPE_LEVEL_BITN 0 -#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 -#define CRYPTO_IRQTYPE_LEVEL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_IRQEN -// -//***************************************************************************** -// Field: [1] DMA_IN_DONE -// -// This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. -#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 - -// Field: [0] RESULT_AVAIL -// -// This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. -#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_IRQCLR -// -//***************************************************************************** -// Field: [31] DMA_BUS_ERR -// -// If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared. -#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 - -// Field: [30] KEY_ST_WR_ERR -// -// If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared. -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 - -// Field: [29] KEY_ST_RD_ERR -// -// If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared. -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 - -// Field: [1] DMA_IN_DONE -// -// If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. -#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 - -// Field: [0] RESULT_AVAIL -// -// If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. -#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_IRQSET -// -//***************************************************************************** -// Field: [1] DMA_IN_DONE -// -// If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. -// Writing 0 has no effect. -#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 - -// Field: [0] RESULT_AVAIL -// -// If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. -// Writing 0 has no effect. -#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_IRQSTAT -// -//***************************************************************************** -// Field: [31] DMA_BUS_ERR -// -// This bit is set when a DMA bus error is detected during a DMA operation. The -// value of this register is held until it is cleared via IRQCLR.DMA_BUS_ERR -// Note: This error is asserted if an error is detected on the AHB master -// interface during a DMA operation. -// Note: This is not an interrupt source. -#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 - -// Field: [30] KEY_ST_WR_ERR -// -// This bit is set when a write error is detected during the DMA write -// operation to the key store memory. The value of this register is held until -// it is cleared via IRQCLR.KEY_ST_WR_ERR -// Note: This error is asserted if a DMA operation does not cover a full key -// area or more areas are written than expected. -// Note: This is not an interrupt source. -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 - -// Field: [29] KEY_ST_RD_ERR -// -// This bit will be set when a read error is detected during the read of a key -// from the key store, while copying it to the AES engine. The value of this -// register is held until it is cleared via IRQCLR.KEY_ST_RD_ERR. -// Note: This error is asserted if a key location is selected in the key store -// that is not available. -// Note: This is not an interrupt source. -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 - -// Field: [1] DMA_IN_DONE -// -// This bit returns the status of DMA data in done interrupt. -#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 - -// Field: [0] RESULT_AVAIL -// -// This bit is set high when the Crypto peripheral has a result available. -#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HWVER -// -//***************************************************************************** -// Field: [27:24] HW_MAJOR_VER -// -// Major version number -#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 -#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 -#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 - -// Field: [23:20] HW_MINOR_VER -// -// Minor version number -#define CRYPTO_HWVER_HW_MINOR_VER_W 4 -#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 -#define CRYPTO_HWVER_HW_MINOR_VER_S 20 - -// Field: [19:16] HW_PATCH_LVL -// -// Patch level, starts at 0 at first delivery of this version. -#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 -#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 -#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 - -// Field: [15:8] VER_NUM_COMPL -// -// These bits simply contain the complement of VER_NUM (0x87), used by a driver -// to ascertain that the Crypto peripheral register is indeed read. -#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 -#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 -#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 - -// Field: [7:0] VER_NUM -// -// The version number for the Crypto peripheral, this field contains the value -// 120 (decimal) or 0x78. -#define CRYPTO_HWVER_VER_NUM_W 8 -#define CRYPTO_HWVER_VER_NUM_M 0x000000FF -#define CRYPTO_HWVER_VER_NUM_S 0 - - -#endif // __CRYPTO__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_ddi.h b/third_party/ti/devices/cc26x0/inc/hw_ddi.h deleted file mode 100644 index 42aafb1ba..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_ddi.h +++ /dev/null @@ -1,197 +0,0 @@ -/****************************************************************************** -* Filename: hw_ddi.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_DDI_H__ -#define __HW_DDI_H__ - -//***************************************************************************** -// -// This file contains macros for controlling the DDI master and -// accessing DDI Slave registers via the DDI Master. -// There are 3 categories of macros in this file: -// - macros that provide an offset to a register -// located within the DDI Master itself. -// - macros that define bits or bitfields -// within the DDI Master Registers. -// - macros that provide an "instruction offset" -// that are used when accessing a DDI Slave. -// -// The macros that that provide DDI Master register offsets and -// define bits and bitfields for those registers are the typical -// macros that appear in most hw_.h header files. In -// the following example DDI_O_CFG is a macro for a -// register offset and DDI_CFG_WAITFORACK is a macro for -// a bit in that register. This example code will set the WAITFORACK -// bit in register DDI_O_CFG of the DDI Master. (Note: this -// access the Master not the Slave). -// -// HWREG(AUX_OSCDDI_BASE + DDI_O_CFG) |= DDI_CFG_WAITFORACK; -// -// -// The "instruction offset" macros are used to pass an instruction to -// the DDI Master when accessing DDI slave registers. These macros are -// only used when accessing DDI Slave Registers. (Remember DDI -// Master Registers are accessed normally). -// -// The instructions supported when accessing a DDI Slave Regsiter follow: -// - Direct Access to a DDI Slave register. I.e. read or -// write the register. -// - Set the specified bits in a DDI Slave register. -// - Clear the specified bits in a DDI Slave register. -// - Mask write of 4 bits to the a DDI Slave register. -// - Mask write of 8 bits to the a DDI Slave register. -// - Mask write of 16 bits to the a DDI Slave register. -// -// Note: only the "Direct Access" offset should be used when reading -// a DDI Slave register. Only 8- and 16-bit reads are supported. -// -// The generic format of using this marcos for a read follows: -// // read low 16-bits in DDI_SLAVE_OFF -// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR); -// -// // read high 16-bits in DDI_SLAVE_OFF -// // add 2 for data[31:16] -// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_DIR); - -// // read data[31:24] byte in DDI_SLAVE_OFF -// // add 3 for data[31:24] -// myuchar = HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 3 + DDI_O_DIR); -// -// Notes: In the above example: -// - DDI_MASTER_BASE is the base address of the DDI Master defined -// in the hw_memmap.h header file. -// - DDI_SLAVE_OFF is the DDI Slave offset defined in the -// hw_.h header file (e.g. hw_osc_top.h for the oscsc -// oscillator modules. -// - DDI_O_DIR is the "instruction offset" macro defined in this -// file that specifies the Direct Access instruction. -// -// Writes can use any of the "instruction macros". -// The following examples do a "direct write" to DDI Slave register -// DDI_SLAVE_OFF using different size operands: -// -// // ---------- DIRECT WRITES ---------- -// // Write 32-bits aligned -// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x12345678; - -// // Write 16-bits aligned to high 16-bits then low 16-bits -// // Add 2 to get to high 16-bits. -// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0xabcd; -// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0xef01; -// -// // Write each byte at DDI_SLAVE_OFF, one at a time. -// // Add 1,2,or 3 to get to bytes 1,2, or 3. -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x33; -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 1) = 0x44; -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0x55; -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 3) = 0x66; -// -// // ---------- SET/CLR ---------- -// The set and clear functions behave similarly to eachother. Each -// can be performed on an 8-, 16-, or 32-bit operand. -// Examples follow: -// // Set all odd bits in a 32-bit words -// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_SET) = 0xaaaaaaaa; -// -// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand -// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_CLR) = 0x00ff0000; -// -// // Set even bits in byte 2 (data[23:16]) using 8-bit operand -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_CLR) = 0x55; -// -// // ---------- MASKED WRITES ---------- -// The mask writes are a bit different. They operate on nibbles, -// bytes, and 16-bit elements. Two operands are required; a 'mask' -// and 'data'; The operands are concatenated and written to the master. -// e.g. the mask and data are combined as follows for a 16 bit masked -// write: -// (mask << 16) | data; -// Examples follow: -// -// // Write 5555 to low 16-bits of DDI_SLAVE_OFF register -// // a long write is needed (32-bits). -// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xffff5555; - -// // Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register -// // Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff! -// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 4) = 0x01ff01aa; -// -// // Do an 8 bit masked write of 00 to low byte of register (data[7:0]). -// // a short write is needed (16-bits). -// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xff00; -// -// // Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]). -// // add 2 to get to byte 1. -// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 2) = 0xff11; -// -// // Do an 8 bit masked write of 33 to high byte of register (data[31:24]). -// // add 6 to get to byte 3. -// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 6) = 0xff33; -// -// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). -// // Byte write is needed. -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xf7; -// -// // Do an 4 bit masked write of 4 to data[7:4]). -// // Add 1 for next nibble -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 1) = 0xf4; -// -//***************************************************************************** - -//***************************************************************************** -// -// The following are defines for the DDI master instruction offsets. -// -//***************************************************************************** -#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction -#define DDI_O_SET 0x00000040 // Offset for 'Set' instruction. -#define DDI_O_CLR 0x00000080 // Offset for 'Clear' instruction. -#define DDI_O_MASK4B 0x00000100 // Offset for 4-bit masked access. - // Data bit[n] is written if mask bit[n] is set ('1'). - // Bits 7:4 are mask. Bits 3:0 are data. - // Requires 'byte' write. -#define DDI_O_MASK8B 0x00000180 // Offset for 8-bit masked access. - // Data bit[n] is written if mask bit[n] is set ('1'). - // Bits 15:8 are mask. Bits 7:0 are data. - // Requires 'short' write. -#define DDI_O_MASK16B 0x00000200 // Offset for 16-bit masked access. - // Data bit[n] is written if mask bit[n] is set ('1'). - // Bits 31:16 are mask. Bits 15:0 are data. - // Requires 'long' write. - - - -#endif // __HW_DDI_H__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_ddi_0_osc.h b/third_party/ti/devices/cc26x0/inc/hw_ddi_0_osc.h deleted file mode 100644 index 5cc645257..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_ddi_0_osc.h +++ /dev/null @@ -1,1071 +0,0 @@ -/****************************************************************************** -* Filename: hw_ddi_0_osc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_DDI_0_OSC_H__ -#define __HW_DDI_0_OSC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// DDI_0_OSC component -// -//***************************************************************************** -// Control 0 -#define DDI_0_OSC_O_CTL0 0x00000000 - -// Control 1 -#define DDI_0_OSC_O_CTL1 0x00000004 - -// RADC External Configuration -#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 - -// Amplitude Compensation Control -#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C - -// Amplitude Compensation Threshold 1 -#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 - -// Amplitude Compensation Threshold 2 -#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 - -// Analog Bypass Values 1 -#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 - -// Internal -#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C - -// Analog Test Control -#define DDI_0_OSC_O_ATESTCTL 0x00000020 - -// ADC Doubler Nanoamp Control -#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 - -// XOSCHF Control -#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 - -// Low Frequency Oscillator Control -#define DDI_0_OSC_O_LFOSCCTL 0x0000002C - -// RCOSCHF Control -#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 - -// Status 0 -#define DDI_0_OSC_O_STAT0 0x00000034 - -// Status 1 -#define DDI_0_OSC_O_STAT1 0x00000038 - -// Status 2 -#define DDI_0_OSC_O_STAT2 0x0000003C - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_CTL0 -// -//***************************************************************************** -// Field: [31] XTAL_IS_24M -// -// Set based on the accurate high frequency XTAL. -// ENUMs: -// 24M Internal. Only to be used through TI provided API. -// 48M Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 - -// Field: [29] BYPASS_XOSC_LF_CLK_QUAL -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 - -// Field: [28] BYPASS_RCOSC_LF_CLK_QUAL -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 - -// Field: [27:26] DOUBLER_START_DURATION -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 - -// Field: [25] DOUBLER_RESET_DURATION -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 - -// Field: [22] FORCE_KICKSTART_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x00400000 -#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_M 0x00400000 -#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_S 22 - -// Field: [16] ALLOW_SCLK_HF_SWITCHING -// -// 0: Default - Switching of HF clock source is disabled . -// 1: Allows switching of sclk_hf source. -// -// Provided to prevent switching of the SCLK_HF source when running from flash -// (a long period during switching could corrupt flash). When sclk_hf -// switching is disabled, a new source can be started when SCLK_HF_SRC_SEL is -// changed, but the switch will not occur until this bit is set. This bit -// should be set to enable clock switching after STAT0.PENDINGSCLKHFSWITCHING -// indicates the new HF clock is ready. When switching completes (also -// indicated by STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be -// disabled to prevent flash corruption. Switching should not be enabled when -// running from flash. -#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x00010000 -#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_M 0x00010000 -#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_S 16 - -// Field: [14] HPOSC_MODE_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 - -// Field: [12] RCOSC_LF_TRIMMED -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 - -// Field: [11] XOSC_HF_POWER_MODE -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 - -// Field: [10] XOSC_LF_DIG_BYPASS -// -// Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf -// clock. -// -// 0: Use 32kHz XOSC as xosc_lf clock source -// 1: Use digital input (from AON) as xosc_lf clock source. -// -// This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf -// as the sclk_lf source. The muxing performed by this bit is not glitch free. -// The following procedure must be followed when changing this field to avoid -// glitches on sclk_lf. -// -// 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock -// source. -// 2) Set or clear this bit to bypass or not bypass the xosc_lf. -// 3) Set SCLK_LF_SRC_SEL to use xosc_lf. -// -// It is recommended that either the rcosc_hf or xosc_hf (whichever is -// currently active) be selected as the source in step 1 above. This provides a -// faster clock change. -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 - -// Field: [9] CLK_LOSS_EN -// -// Enable clock loss detection and hence the indicators to system controller. -// Checks both SCLK_HF and SCLK_LF clock loss indicators. -// -// 0: Disable -// 1: Enable -// -// Clock loss detection must be disabled when changing the sclk_lf source. -// STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf -// source has completed. -#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 -#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 -#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 - -// Field: [8:7] ACLK_TDC_SRC_SEL -// -// Source select for aclk_tdc. -// -// 00: RCOSC_HF (48MHz) -// 01: RCOSC_HF (24MHz) -// 10: XOSC_HF (24MHz) -// 11: Not used -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 - -// Field: [6:5] ACLK_REF_SRC_SEL -// -// Source select for aclk_ref -// -// 00: RCOSC_HF derived (31.25kHz) -// 01: XOSC_HF derived (31.25kHz) -// 10: RCOSC_LF (32kHz) -// 11: XOSC_LF (32.768kHz) -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000060 -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 5 - -// Field: [3:2] SCLK_LF_SRC_SEL -// -// Source select for sclk_lf -// ENUMs: -// XOSCLF Low frequency XOSC -// RCOSCLF Low frequency RCOSC -// XOSCHFDLF Low frequency clock derived from High Frequency -// XOSC -// RCOSCHFDLF Low frequency clock derived from High Frequency -// RCOSC -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 - -// Field: [1] SCLK_MF_SRC_SEL -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// XCOSCHFDMF Medium frequency clock derived from high frequency -// XOSC. -// RCOSCHFDMF Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x00000002 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M 0x00000002 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S 1 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF 0x00000002 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0x00000000 - -// Field: [0] SCLK_HF_SRC_SEL -// -// Source select for sclk_hf. XOSC option is supported for test and debug only -// and should be used when the XOSC_HF is running. -// ENUMs: -// XOSC High frequency XOSC clk -// RCOSC High frequency RCOSC clock -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_CTL1 -// -//***************************************************************************** -// Field: [22:18] RCOSCHFCTRIMFRACT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 - -// Field: [17] RCOSCHFCTRIMFRACT_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 - -// Field: [1:0] XOSC_HF_FAST_START -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_RADCEXTCFG -// -//***************************************************************************** -// Field: [31:22] HPM_IBIAS_WAIT_CNT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 - -// Field: [21:16] LPM_IBIAS_WAIT_CNT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 - -// Field: [15:12] IDAC_STEP -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 - -// Field: [11:6] RADC_DAC_TH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 - -// Field: [5] RADC_MODE_IS_SAR -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_AMPCOMPCTL -// -//***************************************************************************** -// Field: [30] AMPCOMP_REQ_MODE -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 - -// Field: [29:28] AMPCOMP_FSM_UPDATE_RATE -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// 250KHZ Internal. Only to be used through TI provided API. -// 500KHZ Internal. Only to be used through TI provided API. -// 1MHZ Internal. Only to be used through TI provided API. -// 2MHZ Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 - -// Field: [27] AMPCOMP_SW_CTRL -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 - -// Field: [26] AMPCOMP_SW_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 - -// Field: [23:20] IBIAS_OFFSET -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 - -// Field: [19:16] IBIAS_INIT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 - -// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 - -// Field: [7:4] CAP_STEP -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 - -// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_AMPCOMPTH1 -// -//***************************************************************************** -// Field: [23:18] HPMRAMP3_LTH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 - -// Field: [15:10] HPMRAMP3_HTH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 - -// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 - -// Field: [5:0] HPMRAMP1_TH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_AMPCOMPTH2 -// -//***************************************************************************** -// Field: [31:26] LPMUPDATE_LTH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 - -// Field: [23:18] LPMUPDATE_HTH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 - -// Field: [15:10] ADC_COMP_AMPTH_LPM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 - -// Field: [7:2] ADC_COMP_AMPTH_HPM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_ANABYPASSVAL1 -// -//***************************************************************************** -// Field: [19:16] XOSC_HF_ROW_Q12 -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 - -// Field: [15:0] XOSC_HF_COLUMN_Q12 -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_ANABYPASSVAL2 -// -//***************************************************************************** -// Field: [13:0] XOSC_HF_IBIASTHERM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_ATESTCTL -// -//***************************************************************************** -// Field: [29] SCLK_LF_AUX_EN -// -// Enable 32 kHz clock to AUX_COMPB. -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x20000000 -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x20000000 -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 29 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL -// -//***************************************************************************** -// Field: [24] NANOAMP_BIAS_ENABLE -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 - -// Field: [23] SPARE23 -// -// Software should not rely on the value of a reserved. Writing any other value -// than the reset value may result in undefined behavior -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 - -// Field: [5] ADC_SH_MODE_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 - -// Field: [4] ADC_SH_VBUF_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 - -// Field: [1:0] ADC_IREF_CTRL -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_XOSCHFCTL -// -//***************************************************************************** -// Field: [9:8] PEAK_DET_ITRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 - -// Field: [6] BYPASS -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 -#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 -#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 - -// Field: [4:2] HP_BUF_ITRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 - -// Field: [1:0] LP_BUF_ITRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_LFOSCCTL -// -//***************************************************************************** -// Field: [23:22] XOSCLF_REGULATOR_TRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 - -// Field: [21:18] XOSCLF_CMIRRWR_RATIO -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 - -// Field: [9:8] RCOSCLF_RTUNE_TRIM -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// 6P0MEG Internal. Only to be used through TI provided API. -// 6P5MEG Internal. Only to be used through TI provided API. -// 7P0MEG Internal. Only to be used through TI provided API. -// 7P5MEG Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 - -// Field: [7:0] RCOSCLF_CTUNE_TRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_RCOSCHFCTL -// -//***************************************************************************** -// Field: [15:8] RCOSCHF_CTRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_STAT0 -// -//***************************************************************************** -// Field: [30:29] SCLK_LF_SRC -// -// Indicates source for the sclk_lf -// ENUMs: -// XOSCLF Low frequency XOSC -// RCOSCLF Low frequency RCOSC -// XOSCHFDLF Low frequency clock derived from High Frequency -// XOSC -// RCOSCHFDLF Low frequency clock derived from High Frequency -// RCOSC -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 - -// Field: [28] SCLK_HF_SRC -// -// Indicates source for the sclk_hf -// ENUMs: -// XOSC High frequency XOSC -// RCOSC High frequency RCOSC clock -#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 - -// Field: [22] RCOSC_HF_EN -// -// RCOSC_HF_EN -#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 -#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 -#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 - -// Field: [21] RCOSC_LF_EN -// -// RCOSC_LF_EN -#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 -#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 -#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 - -// Field: [20] XOSC_LF_EN -// -// XOSC_LF_EN -#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 -#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 -#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 - -// Field: [19] CLK_DCDC_RDY -// -// CLK_DCDC_RDY -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 - -// Field: [18] CLK_DCDC_RDY_ACK -// -// CLK_DCDC_RDY_ACK -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 - -// Field: [17] SCLK_HF_LOSS -// -// Indicates sclk_hf is lost -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 - -// Field: [16] SCLK_LF_LOSS -// -// Indicates sclk_lf is lost -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 - -// Field: [15] XOSC_HF_EN -// -// Indicates that XOSC_HF is enabled. -#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 -#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 -#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 - -// Field: [13] XB_48M_CLK_EN -// -// Indicates that the 48MHz clock from the DOUBLER is enabled. -// -// It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler -// bypass for the 48MHz crystal). -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 - -// Field: [11] XOSC_HF_LP_BUF_EN -// -// XOSC_HF_LP_BUF_EN -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 - -// Field: [10] XOSC_HF_HP_BUF_EN -// -// XOSC_HF_HP_BUF_EN -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 - -// Field: [8] ADC_THMET -// -// ADC_THMET -#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 -#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 -#define DDI_0_OSC_STAT0_ADC_THMET_S 8 - -// Field: [7] ADC_DATA_READY -// -// indicates when adc_data is ready. -#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 -#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 -#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 - -// Field: [6:1] ADC_DATA -// -// adc_data -#define DDI_0_OSC_STAT0_ADC_DATA_W 6 -#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E -#define DDI_0_OSC_STAT0_ADC_DATA_S 1 - -// Field: [0] PENDINGSCLKHFSWITCHING -// -// Indicates when sclk_hf is ready to be switched -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_STAT1 -// -//***************************************************************************** -// Field: [31:28] RAMPSTATE -// -// AMPCOMP FSM State -// ENUMs: -// FAST_START_SETTLE FAST_START_SETTLE -// FAST_START FAST_START -// DUMMY_TO_INIT_1 DUMMY_TO_INIT_1 -// IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE -// IBIAS_INC IBIAS_INCREMENT -// LPM_UPDATE LPM_UPDATE -// IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE -// IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE -// IDAC_INCREMENT IDAC_INCREMENT -// HPM_UPDATE HPM_UPDATE -// HPM_RAMP3 HPM_RAMP3 -// HPM_RAMP2 HPM_RAMP2 -// HPM_RAMP1 HPM_RAMP1 -// INITIALIZATION INITIALIZATION -// RESET RESET -#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 -#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 -#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 - -// Field: [27:22] HPM_UPDATE_AMP -// -// OSC amplitude during HPM_UPDATE state. -// When amplitude compensation of XOSC_HF is enabled in high performance mode, -// this value is the amplitude of the crystal oscillations measured by the -// on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 -// would indicate that the amplitude of the crystal is approximately 480 mV. -// To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero -// value. -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 - -// Field: [21:16] LPM_UPDATE_AMP -// -// OSC amplitude during LPM_UPDATE state -// When amplitude compensation of XOSC_HF is enabled in low power mode, this -// value is the amplitude of the crystal oscillations measured by the on-chip -// oscillator ADC, divided by 15 mV. For example, a value of 0x20 would -// indicate that the amplitude of the crystal is approximately 480 mV. To -// enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero -// value. -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 - -// Field: [15] FORCE_RCOSC_HF -// -// force_rcosc_hf -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 - -// Field: [14] SCLK_HF_EN -// -// SCLK_HF_EN -#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 -#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 -#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 - -// Field: [13] SCLK_MF_EN -// -// SCLK_MF_EN -#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 -#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 -#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 - -// Field: [12] ACLK_ADC_EN -// -// ACLK_ADC_EN -#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 -#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 -#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 - -// Field: [11] ACLK_TDC_EN -// -// ACLK_TDC_EN -#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 -#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 -#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 - -// Field: [10] ACLK_REF_EN -// -// ACLK_REF_EN -#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 -#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 -#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 - -// Field: [9] CLK_CHP_EN -// -// CLK_CHP_EN -#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 -#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 -#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 - -// Field: [8] CLK_DCDC_EN -// -// CLK_DCDC_EN -#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 -#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 -#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 - -// Field: [7] SCLK_HF_GOOD -// -// SCLK_HF_GOOD -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 - -// Field: [6] SCLK_MF_GOOD -// -// SCLK_MF_GOOD -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 - -// Field: [5] SCLK_LF_GOOD -// -// SCLK_LF_GOOD -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 - -// Field: [4] ACLK_ADC_GOOD -// -// ACLK_ADC_GOOD -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 - -// Field: [3] ACLK_TDC_GOOD -// -// ACLK_TDC_GOOD -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 - -// Field: [2] ACLK_REF_GOOD -// -// ACLK_REF_GOOD -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 - -// Field: [1] CLK_CHP_GOOD -// -// CLK_CHP_GOOD -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 - -// Field: [0] CLK_DCDC_GOOD -// -// CLK_DCDC_GOOD -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_STAT2 -// -//***************************************************************************** -// Field: [31:26] ADC_DCBIAS -// -// DC Bias read by RADC during SAR mode -// The value is an unsigned integer. It is used for debug only. -#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 -#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 -#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 - -// Field: [25] HPM_RAMP1_THMET -// -// Indication of threshold is met for hpm_ramp1 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 - -// Field: [24] HPM_RAMP2_THMET -// -// Indication of threshold is met for hpm_ramp2 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 - -// Field: [23] HPM_RAMP3_THMET -// -// Indication of threshold is met for hpm_ramp3 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 - -// Field: [15:12] RAMPSTATE -// -// xosc_hf amplitude compensation FSM -// -// This is identical to STAT1.RAMPSTATE. See that description for encoding. -#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 -#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 -#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 - -// Field: [3] AMPCOMP_REQ -// -// ampcomp_req -#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 -#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 -#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 - -// Field: [2] XOSC_HF_AMPGOOD -// -// amplitude of xosc_hf is within the required threshold (set by DDI). Not used -// for anything just for debug/status -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 - -// Field: [1] XOSC_HF_FREQGOOD -// -// frequency of xosc_hf is good to use for the digital clocks -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 - -// Field: [0] XOSC_HF_RF_FREQGOOD -// -// frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio -// operations. Used for SW to start synthesizer. -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 - - -#endif // __DDI_0_OSC__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_device.h b/third_party/ti/devices/cc26x0/inc/hw_device.h deleted file mode 100644 index 2a6e42512..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_device.h +++ /dev/null @@ -1,168 +0,0 @@ -/****************************************************************************** -* Filename: hw_device.h -* Revised: 2017-06-21 10:06:25 +0200 (Wed, 21 Jun 2017) -* Revision: 49177 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_DEVICE_H__ -#define __HW_DEVICE_H__ - -#include "../inc/hw_chip_def.h" - -#ifdef CC_GET_CHIP_PACKAGE - -#if ( CC_GET_CHIP_PACKAGE == 0x7 ) -//***************************************************************************** -// -// The following are defines for edge detection on wake up events for the -// CC26xx 7x7 packaged device. -// -//***************************************************************************** -#define AON_EVENT_DIO0 18 -#define AON_EVENT_DIO1 17 -#define AON_EVENT_DIO2 16 -#define AON_EVENT_DIO3 15 -#define AON_EVENT_DIO4 14 -#define AON_EVENT_DIO5 13 -#define AON_EVENT_DIO6 12 -#define AON_EVENT_DIO7 11 -#define AON_EVENT_DIO8 10 -#define AON_EVENT_DIO9 9 -#define AON_EVENT_DIO10 8 -#define AON_EVENT_DIO11 7 -#define AON_EVENT_DIO12 6 -#define AON_EVENT_DIO13 5 -#define AON_EVENT_DIO14 4 -#define AON_EVENT_DIO15 3 -#define AON_EVENT_DIO16 2 -#define AON_EVENT_DIO17 1 -#define AON_EVENT_DIO18 31 -#define AON_EVENT_DIO19 30 -#define AON_EVENT_DIO20 29 -#define AON_EVENT_DIO21 28 -#define AON_EVENT_DIO22 27 -#define AON_EVENT_DIO23 26 -#define AON_EVENT_DIO24 25 -#define AON_EVENT_DIO25 24 -#define AON_EVENT_DIO26 23 -#define AON_EVENT_DIO27 22 -#define AON_EVENT_DIO28 21 -#define AON_EVENT_DIO29 20 -#define AON_EVENT_DIO30 19 -#define AON_EVENT_DIO31 0x3F -#endif // ( CC_GET_CHIP_PACKAGE == 0x7 ) - -#if ( CC_GET_CHIP_PACKAGE == 0x5 ) -//***************************************************************************** -// -// The following are defines for edge detection on wake up events for the -// CC26xx 5x5 packaged device. -// -//***************************************************************************** -#define AON_EVENT_DIO0 15 -#define AON_EVENT_DIO1 14 -#define AON_EVENT_DIO2 13 -#define AON_EVENT_DIO3 12 -#define AON_EVENT_DIO4 11 -#define AON_EVENT_DIO5 2 -#define AON_EVENT_DIO6 1 -#define AON_EVENT_DIO7 26 -#define AON_EVENT_DIO8 25 -#define AON_EVENT_DIO9 23 -#define AON_EVENT_DIO10 24 -#define AON_EVENT_DIO11 22 -#define AON_EVENT_DIO12 21 -#define AON_EVENT_DIO13 20 -#define AON_EVENT_DIO14 19 -#define AON_EVENT_DIO15 0x3F -#define AON_EVENT_DIO16 0x3F -#define AON_EVENT_DIO17 0x3F -#define AON_EVENT_DIO18 0x3F -#define AON_EVENT_DIO19 0x3F -#define AON_EVENT_DIO20 0x3F -#define AON_EVENT_DIO21 0x3F -#define AON_EVENT_DIO22 0x3F -#define AON_EVENT_DIO23 0x3F -#define AON_EVENT_DIO24 0x3F -#define AON_EVENT_DIO25 0x3F -#define AON_EVENT_DIO26 0x3F -#define AON_EVENT_DIO27 0x3F -#define AON_EVENT_DIO28 0x3F -#define AON_EVENT_DIO29 0x3F -#define AON_EVENT_DIO30 0x3F -#define AON_EVENT_DIO31 0x3F -#endif // ( CC_GET_CHIP_PACKAGE == 0x5 ) - -#if ( CC_GET_CHIP_PACKAGE == 0x4 ) -//***************************************************************************** -// -// The following are defines for edge detection on wake up events for the -// CC26xx 4x4 packaged device. -// -//***************************************************************************** -#define AON_EVENT_DIO0 13 -#define AON_EVENT_DIO1 12 -#define AON_EVENT_DIO2 11 -#define AON_EVENT_DIO3 2 -#define AON_EVENT_DIO4 1 -#define AON_EVENT_DIO5 26 -#define AON_EVENT_DIO6 25 -#define AON_EVENT_DIO7 24 -#define AON_EVENT_DIO8 23 -#define AON_EVENT_DIO9 22 -#define AON_EVENT_DIO10 0x3F -#define AON_EVENT_DIO11 0x3F -#define AON_EVENT_DIO12 0x3F -#define AON_EVENT_DIO13 0x3F -#define AON_EVENT_DIO14 0x3F -#define AON_EVENT_DIO15 0x3F -#define AON_EVENT_DIO16 0x3F -#define AON_EVENT_DIO17 0x3F -#define AON_EVENT_DIO18 0x3F -#define AON_EVENT_DIO19 0x3F -#define AON_EVENT_DIO20 0x3F -#define AON_EVENT_DIO21 0x3F -#define AON_EVENT_DIO22 0x3F -#define AON_EVENT_DIO23 0x3F -#define AON_EVENT_DIO24 0x3F -#define AON_EVENT_DIO25 0x3F -#define AON_EVENT_DIO26 0x3F -#define AON_EVENT_DIO27 0x3F -#define AON_EVENT_DIO28 0x3F -#define AON_EVENT_DIO29 0x3F -#define AON_EVENT_DIO30 0x3F -#define AON_EVENT_DIO31 0x3F -#endif // ( CC_GET_CHIP_PACKAGE == 0x4 ) - -#endif // defined( CC_GET_CHIP_PACKAGE ) -#endif // __HW_DEVICE_H__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_event.h b/third_party/ti/devices/cc26x0/inc/hw_event.h deleted file mode 100644 index 64e77d78e..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_event.h +++ /dev/null @@ -1,3301 +0,0 @@ -/****************************************************************************** -* Filename: hw_event_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_EVENT_H__ -#define __HW_EVENT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// EVENT component -// -//***************************************************************************** -// Output Selection for CPU Interrupt 0 -#define EVENT_O_CPUIRQSEL0 0x00000000 - -// Output Selection for CPU Interrupt 1 -#define EVENT_O_CPUIRQSEL1 0x00000004 - -// Output Selection for CPU Interrupt 2 -#define EVENT_O_CPUIRQSEL2 0x00000008 - -// Output Selection for CPU Interrupt 3 -#define EVENT_O_CPUIRQSEL3 0x0000000C - -// Output Selection for CPU Interrupt 4 -#define EVENT_O_CPUIRQSEL4 0x00000010 - -// Output Selection for CPU Interrupt 5 -#define EVENT_O_CPUIRQSEL5 0x00000014 - -// Output Selection for CPU Interrupt 6 -#define EVENT_O_CPUIRQSEL6 0x00000018 - -// Output Selection for CPU Interrupt 7 -#define EVENT_O_CPUIRQSEL7 0x0000001C - -// Output Selection for CPU Interrupt 8 -#define EVENT_O_CPUIRQSEL8 0x00000020 - -// Output Selection for CPU Interrupt 9 -#define EVENT_O_CPUIRQSEL9 0x00000024 - -// Output Selection for CPU Interrupt 10 -#define EVENT_O_CPUIRQSEL10 0x00000028 - -// Output Selection for CPU Interrupt 11 -#define EVENT_O_CPUIRQSEL11 0x0000002C - -// Output Selection for CPU Interrupt 12 -#define EVENT_O_CPUIRQSEL12 0x00000030 - -// Output Selection for CPU Interrupt 13 -#define EVENT_O_CPUIRQSEL13 0x00000034 - -// Output Selection for CPU Interrupt 14 -#define EVENT_O_CPUIRQSEL14 0x00000038 - -// Output Selection for CPU Interrupt 15 -#define EVENT_O_CPUIRQSEL15 0x0000003C - -// Output Selection for CPU Interrupt 16 -#define EVENT_O_CPUIRQSEL16 0x00000040 - -// Output Selection for CPU Interrupt 17 -#define EVENT_O_CPUIRQSEL17 0x00000044 - -// Output Selection for CPU Interrupt 18 -#define EVENT_O_CPUIRQSEL18 0x00000048 - -// Output Selection for CPU Interrupt 19 -#define EVENT_O_CPUIRQSEL19 0x0000004C - -// Output Selection for CPU Interrupt 20 -#define EVENT_O_CPUIRQSEL20 0x00000050 - -// Output Selection for CPU Interrupt 21 -#define EVENT_O_CPUIRQSEL21 0x00000054 - -// Output Selection for CPU Interrupt 22 -#define EVENT_O_CPUIRQSEL22 0x00000058 - -// Output Selection for CPU Interrupt 23 -#define EVENT_O_CPUIRQSEL23 0x0000005C - -// Output Selection for CPU Interrupt 24 -#define EVENT_O_CPUIRQSEL24 0x00000060 - -// Output Selection for CPU Interrupt 25 -#define EVENT_O_CPUIRQSEL25 0x00000064 - -// Output Selection for CPU Interrupt 26 -#define EVENT_O_CPUIRQSEL26 0x00000068 - -// Output Selection for CPU Interrupt 27 -#define EVENT_O_CPUIRQSEL27 0x0000006C - -// Output Selection for CPU Interrupt 28 -#define EVENT_O_CPUIRQSEL28 0x00000070 - -// Output Selection for CPU Interrupt 29 -#define EVENT_O_CPUIRQSEL29 0x00000074 - -// Output Selection for CPU Interrupt 30 -#define EVENT_O_CPUIRQSEL30 0x00000078 - -// Output Selection for CPU Interrupt 31 -#define EVENT_O_CPUIRQSEL31 0x0000007C - -// Output Selection for CPU Interrupt 32 -#define EVENT_O_CPUIRQSEL32 0x00000080 - -// Output Selection for CPU Interrupt 33 -#define EVENT_O_CPUIRQSEL33 0x00000084 - -// Output Selection for RFC Event 0 -#define EVENT_O_RFCSEL0 0x00000100 - -// Output Selection for RFC Event 1 -#define EVENT_O_RFCSEL1 0x00000104 - -// Output Selection for RFC Event 2 -#define EVENT_O_RFCSEL2 0x00000108 - -// Output Selection for RFC Event 3 -#define EVENT_O_RFCSEL3 0x0000010C - -// Output Selection for RFC Event 4 -#define EVENT_O_RFCSEL4 0x00000110 - -// Output Selection for RFC Event 5 -#define EVENT_O_RFCSEL5 0x00000114 - -// Output Selection for RFC Event 6 -#define EVENT_O_RFCSEL6 0x00000118 - -// Output Selection for RFC Event 7 -#define EVENT_O_RFCSEL7 0x0000011C - -// Output Selection for RFC Event 8 -#define EVENT_O_RFCSEL8 0x00000120 - -// Output Selection for RFC Event 9 -#define EVENT_O_RFCSEL9 0x00000124 - -// Output Selection for GPT0 0 -#define EVENT_O_GPT0ACAPTSEL 0x00000200 - -// Output Selection for GPT0 1 -#define EVENT_O_GPT0BCAPTSEL 0x00000204 - -// Output Selection for GPT1 0 -#define EVENT_O_GPT1ACAPTSEL 0x00000300 - -// Output Selection for GPT1 1 -#define EVENT_O_GPT1BCAPTSEL 0x00000304 - -// Output Selection for GPT2 0 -#define EVENT_O_GPT2ACAPTSEL 0x00000400 - -// Output Selection for GPT2 1 -#define EVENT_O_GPT2BCAPTSEL 0x00000404 - -// Output Selection for DMA Channel 1 SREQ -#define EVENT_O_UDMACH1SSEL 0x00000508 - -// Output Selection for DMA Channel 1 REQ -#define EVENT_O_UDMACH1BSEL 0x0000050C - -// Output Selection for DMA Channel 2 SREQ -#define EVENT_O_UDMACH2SSEL 0x00000510 - -// Output Selection for DMA Channel 2 REQ -#define EVENT_O_UDMACH2BSEL 0x00000514 - -// Output Selection for DMA Channel 3 SREQ -#define EVENT_O_UDMACH3SSEL 0x00000518 - -// Output Selection for DMA Channel 3 REQ -#define EVENT_O_UDMACH3BSEL 0x0000051C - -// Output Selection for DMA Channel 4 SREQ -#define EVENT_O_UDMACH4SSEL 0x00000520 - -// Output Selection for DMA Channel 4 REQ -#define EVENT_O_UDMACH4BSEL 0x00000524 - -// Output Selection for DMA Channel 5 SREQ -#define EVENT_O_UDMACH5SSEL 0x00000528 - -// Output Selection for DMA Channel 5 REQ -#define EVENT_O_UDMACH5BSEL 0x0000052C - -// Output Selection for DMA Channel 6 SREQ -#define EVENT_O_UDMACH6SSEL 0x00000530 - -// Output Selection for DMA Channel 6 REQ -#define EVENT_O_UDMACH6BSEL 0x00000534 - -// Output Selection for DMA Channel 7 SREQ -#define EVENT_O_UDMACH7SSEL 0x00000538 - -// Output Selection for DMA Channel 7 REQ -#define EVENT_O_UDMACH7BSEL 0x0000053C - -// Output Selection for DMA Channel 8 SREQ -#define EVENT_O_UDMACH8SSEL 0x00000540 - -// Output Selection for DMA Channel 8 REQ -#define EVENT_O_UDMACH8BSEL 0x00000544 - -// Output Selection for DMA Channel 9 SREQ -#define EVENT_O_UDMACH9SSEL 0x00000548 - -// Output Selection for DMA Channel 9 REQ -#define EVENT_O_UDMACH9BSEL 0x0000054C - -// Output Selection for DMA Channel 10 SREQ -#define EVENT_O_UDMACH10SSEL 0x00000550 - -// Output Selection for DMA Channel 10 REQ -#define EVENT_O_UDMACH10BSEL 0x00000554 - -// Output Selection for DMA Channel 11 SREQ -#define EVENT_O_UDMACH11SSEL 0x00000558 - -// Output Selection for DMA Channel 11 REQ -#define EVENT_O_UDMACH11BSEL 0x0000055C - -// Output Selection for DMA Channel 12 SREQ -#define EVENT_O_UDMACH12SSEL 0x00000560 - -// Output Selection for DMA Channel 12 REQ -#define EVENT_O_UDMACH12BSEL 0x00000564 - -// Output Selection for DMA Channel 13 REQ -#define EVENT_O_UDMACH13BSEL 0x0000056C - -// Output Selection for DMA Channel 14 REQ -#define EVENT_O_UDMACH14BSEL 0x00000574 - -// Output Selection for DMA Channel 15 REQ -#define EVENT_O_UDMACH15BSEL 0x0000057C - -// Output Selection for DMA Channel 16 SREQ -#define EVENT_O_UDMACH16SSEL 0x00000580 - -// Output Selection for DMA Channel 16 REQ -#define EVENT_O_UDMACH16BSEL 0x00000584 - -// Output Selection for DMA Channel 17 SREQ -#define EVENT_O_UDMACH17SSEL 0x00000588 - -// Output Selection for DMA Channel 17 REQ -#define EVENT_O_UDMACH17BSEL 0x0000058C - -// Output Selection for DMA Channel 21 SREQ -#define EVENT_O_UDMACH21SSEL 0x000005A8 - -// Output Selection for DMA Channel 21 REQ -#define EVENT_O_UDMACH21BSEL 0x000005AC - -// Output Selection for DMA Channel 22 SREQ -#define EVENT_O_UDMACH22SSEL 0x000005B0 - -// Output Selection for DMA Channel 22 REQ -#define EVENT_O_UDMACH22BSEL 0x000005B4 - -// Output Selection for DMA Channel 23 SREQ -#define EVENT_O_UDMACH23SSEL 0x000005B8 - -// Output Selection for DMA Channel 23 REQ -#define EVENT_O_UDMACH23BSEL 0x000005BC - -// Output Selection for DMA Channel 24 SREQ -#define EVENT_O_UDMACH24SSEL 0x000005C0 - -// Output Selection for DMA Channel 24 REQ -#define EVENT_O_UDMACH24BSEL 0x000005C4 - -// Output Selection for GPT3 0 -#define EVENT_O_GPT3ACAPTSEL 0x00000600 - -// Output Selection for GPT3 1 -#define EVENT_O_GPT3BCAPTSEL 0x00000604 - -// Output Selection for AUX Subscriber 0 -#define EVENT_O_AUXSEL0 0x00000700 - -// Output Selection for NMI Subscriber 0 -#define EVENT_O_CM3NMISEL0 0x00000800 - -// Output Selection for I2S Subscriber 0 -#define EVENT_O_I2SSTMPSEL0 0x00000900 - -// Output Selection for FRZ Subscriber -#define EVENT_O_FRZSEL0 0x00000A00 - -// Set or Clear Software Events -#define EVENT_O_SWEV 0x00000F00 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -#define EVENT_CPUIRQSEL0_EV_W 7 -#define EVENT_CPUIRQSEL0_EV_M 0x0000007F -#define EVENT_CPUIRQSEL0_EV_S 0 -#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL1 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// I2C_IRQ Interrupt event from I2C -#define EVENT_CPUIRQSEL1_EV_W 7 -#define EVENT_CPUIRQSEL1_EV_M 0x0000007F -#define EVENT_CPUIRQSEL1_EV_S 0 -#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL2 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -#define EVENT_CPUIRQSEL2_EV_W 7 -#define EVENT_CPUIRQSEL2_EV_M 0x0000007F -#define EVENT_CPUIRQSEL2_EV_S 0 -#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL3 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL4 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -#define EVENT_CPUIRQSEL4_EV_W 7 -#define EVENT_CPUIRQSEL4_EV_M 0x0000007F -#define EVENT_CPUIRQSEL4_EV_S 0 -#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL5 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -#define EVENT_CPUIRQSEL5_EV_W 7 -#define EVENT_CPUIRQSEL5_EV_M 0x0000007F -#define EVENT_CPUIRQSEL5_EV_S 0 -#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL6 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_SWEV0 AUX software event 0, triggered by -// AUX_EVCTL:SWEVSET.SWEV0, also available as -// AUX_EVENT0 AON wake up event. -// MCU domain wakeup control -// AON_EVENT:MCUWUSEL -// AUX domain wakeup control -// AON_EVENT:AUXWUSEL -#define EVENT_CPUIRQSEL6_EV_W 7 -#define EVENT_CPUIRQSEL6_EV_M 0x0000007F -#define EVENT_CPUIRQSEL6_EV_S 0 -#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL7 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -#define EVENT_CPUIRQSEL7_EV_W 7 -#define EVENT_CPUIRQSEL7_EV_M 0x0000007F -#define EVENT_CPUIRQSEL7_EV_S 0 -#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL8 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -#define EVENT_CPUIRQSEL8_EV_W 7 -#define EVENT_CPUIRQSEL8_EV_M 0x0000007F -#define EVENT_CPUIRQSEL8_EV_S 0 -#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL9 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -#define EVENT_CPUIRQSEL9_EV_W 7 -#define EVENT_CPUIRQSEL9_EV_M 0x0000007F -#define EVENT_CPUIRQSEL9_EV_S 0 -#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL10 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -#define EVENT_CPUIRQSEL10_EV_W 7 -#define EVENT_CPUIRQSEL10_EV_M 0x0000007F -#define EVENT_CPUIRQSEL10_EV_S 0 -#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL11 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -#define EVENT_CPUIRQSEL11_EV_W 7 -#define EVENT_CPUIRQSEL11_EV_M 0x0000007F -#define EVENT_CPUIRQSEL11_EV_S 0 -#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL12 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// I2S_IRQ Interrupt event from I2S -#define EVENT_CPUIRQSEL12_EV_W 7 -#define EVENT_CPUIRQSEL12_EV_M 0x0000007F -#define EVENT_CPUIRQSEL12_EV_S 0 -#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL13 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_SWEV1 AUX software event 1, triggered by -// AUX_EVCTL:SWEVSET.SWEV1, also available as -// AUX_EVENT2 AON wake up event. -// MCU domain wakeup control -// AON_EVENT:MCUWUSEL -// AUX domain wakeup control -// AON_EVENT:AUXWUSEL -#define EVENT_CPUIRQSEL13_EV_W 7 -#define EVENT_CPUIRQSEL13_EV_M 0x0000007F -#define EVENT_CPUIRQSEL13_EV_S 0 -#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL14 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// WDT_IRQ Watchdog interrupt event, controlled by -// WDT:CTL.INTEN -#define EVENT_CPUIRQSEL14_EV_W 7 -#define EVENT_CPUIRQSEL14_EV_M 0x0000007F -#define EVENT_CPUIRQSEL14_EV_S 0 -#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL15 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR -#define EVENT_CPUIRQSEL15_EV_W 7 -#define EVENT_CPUIRQSEL15_EV_M 0x0000007F -#define EVENT_CPUIRQSEL15_EV_S 0 -#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL16 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR -#define EVENT_CPUIRQSEL16_EV_W 7 -#define EVENT_CPUIRQSEL16_EV_M 0x0000007F -#define EVENT_CPUIRQSEL16_EV_S 0 -#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL17 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR -#define EVENT_CPUIRQSEL17_EV_W 7 -#define EVENT_CPUIRQSEL17_EV_M 0x0000007F -#define EVENT_CPUIRQSEL17_EV_S 0 -#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL18 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR -#define EVENT_CPUIRQSEL18_EV_W 7 -#define EVENT_CPUIRQSEL18_EV_M 0x0000007F -#define EVENT_CPUIRQSEL18_EV_S 0 -#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL19 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR -#define EVENT_CPUIRQSEL19_EV_W 7 -#define EVENT_CPUIRQSEL19_EV_M 0x0000007F -#define EVENT_CPUIRQSEL19_EV_S 0 -#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL20 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR -#define EVENT_CPUIRQSEL20_EV_W 7 -#define EVENT_CPUIRQSEL20_EV_M 0x0000007F -#define EVENT_CPUIRQSEL20_EV_S 0 -#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL21 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR -#define EVENT_CPUIRQSEL21_EV_W 7 -#define EVENT_CPUIRQSEL21_EV_M 0x0000007F -#define EVENT_CPUIRQSEL21_EV_S 0 -#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL22 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR -#define EVENT_CPUIRQSEL22_EV_W 7 -#define EVENT_CPUIRQSEL22_EV_M 0x0000007F -#define EVENT_CPUIRQSEL22_EV_S 0 -#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL23 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the -// corresponding flag is found here -// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by -// CRYPTO:IRQSTAT.RESULT_AVAIL -#define EVENT_CPUIRQSEL23_EV_W 7 -#define EVENT_CPUIRQSEL23_EV_M 0x0000007F -#define EVENT_CPUIRQSEL23_EV_S 0 -#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL24 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// DMA_DONE_COMB Combined DMA done, corresponding flags are here -// UDMA0:REQDONE -#define EVENT_CPUIRQSEL24_EV_W 7 -#define EVENT_CPUIRQSEL24_EV_M 0x0000007F -#define EVENT_CPUIRQSEL24_EV_S 0 -#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL25 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS -#define EVENT_CPUIRQSEL25_EV_W 7 -#define EVENT_CPUIRQSEL25_EV_M 0x0000007F -#define EVENT_CPUIRQSEL25_EV_S 0 -#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL26 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -#define EVENT_CPUIRQSEL26_EV_W 7 -#define EVENT_CPUIRQSEL26_EV_M 0x0000007F -#define EVENT_CPUIRQSEL26_EV_S 0 -#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL27 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_CPUIRQSEL27_EV_W 7 -#define EVENT_CPUIRQSEL27_EV_M 0x0000007F -#define EVENT_CPUIRQSEL27_EV_S 0 -#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL28 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -#define EVENT_CPUIRQSEL28_EV_W 7 -#define EVENT_CPUIRQSEL28_EV_M 0x0000007F -#define EVENT_CPUIRQSEL28_EV_S 0 -#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL29 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_PROG0 AON programmable event 0. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV -#define EVENT_CPUIRQSEL29_EV_W 7 -#define EVENT_CPUIRQSEL29_EV_M 0x0000007F -#define EVENT_CPUIRQSEL29_EV_S 0 -#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL30 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg -// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled -// by CRYPTO:IRQEN.DMA_IN_DONE -// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, -// see UDMA0:SOFTREQ -// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see -// UDMA0:SOFTREQ -// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 -// I2S_IRQ Interrupt event from I2S -// AON_PROG2 AON programmable event 2. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV -// AON_PROG1 AON programmable event 1. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV -// NONE Always inactive -#define EVENT_CPUIRQSEL30_EV_W 7 -#define EVENT_CPUIRQSEL30_EV_M 0x0000007F -#define EVENT_CPUIRQSEL30_EV_S 0 -#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 -#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B -#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E -#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 -#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 -#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 -#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 -#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 -#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL31 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -#define EVENT_CPUIRQSEL31_EV_W 7 -#define EVENT_CPUIRQSEL31_EV_M 0x0000007F -#define EVENT_CPUIRQSEL31_EV_S 0 -#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL32 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -#define EVENT_CPUIRQSEL32_EV_W 7 -#define EVENT_CPUIRQSEL32_EV_M 0x0000007F -#define EVENT_CPUIRQSEL32_EV_S 0 -#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL33 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN -#define EVENT_CPUIRQSEL33_EV_W 7 -#define EVENT_CPUIRQSEL33_EV_M 0x0000007F -#define EVENT_CPUIRQSEL33_EV_S 0 -#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -#define EVENT_RFCSEL0_EV_W 7 -#define EVENT_RFCSEL0_EV_M 0x0000007F -#define EVENT_RFCSEL0_EV_S 0 -#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL1 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -#define EVENT_RFCSEL1_EV_W 7 -#define EVENT_RFCSEL1_EV_M 0x0000007F -#define EVENT_RFCSEL1_EV_S 0 -#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL2 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -#define EVENT_RFCSEL2_EV_W 7 -#define EVENT_RFCSEL2_EV_M 0x0000007F -#define EVENT_RFCSEL2_EV_S 0 -#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL3 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -#define EVENT_RFCSEL3_EV_W 7 -#define EVENT_RFCSEL3_EV_M 0x0000007F -#define EVENT_RFCSEL3_EV_S 0 -#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL4 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -#define EVENT_RFCSEL4_EV_W 7 -#define EVENT_RFCSEL4_EV_M 0x0000007F -#define EVENT_RFCSEL4_EV_S 0 -#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL5 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -#define EVENT_RFCSEL5_EV_W 7 -#define EVENT_RFCSEL5_EV_M 0x0000007F -#define EVENT_RFCSEL5_EV_S 0 -#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL6 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -#define EVENT_RFCSEL6_EV_W 7 -#define EVENT_RFCSEL6_EV_M 0x0000007F -#define EVENT_RFCSEL6_EV_S 0 -#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL7 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -#define EVENT_RFCSEL7_EV_W 7 -#define EVENT_RFCSEL7_EV_M 0x0000007F -#define EVENT_RFCSEL7_EV_S 0 -#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL8 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -#define EVENT_RFCSEL8_EV_W 7 -#define EVENT_RFCSEL8_EV_M 0x0000007F -#define EVENT_RFCSEL8_EV_S 0 -#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL9 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// SWEV1 Software event 1, triggered by SWEV.SWEV1 -// SWEV0 Software event 0, triggered by SWEV.SWEV0 -// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the -// corresponding flag is found here -// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by -// CRYPTO:IRQSTAT.RESULT_AVAIL -// DMA_DONE_COMB Combined DMA done, corresponding flags are here -// UDMA0:REQDONE -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// WDT_IRQ Watchdog interrupt event, controlled by -// WDT:CTL.INTEN -// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 -// I2S_IRQ Interrupt event from I2S -// AON_PROG1 AON programmable event 1. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV -// AON_PROG0 AON programmable event 0. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV -// NONE Always inactive -#define EVENT_RFCSEL9_EV_W 7 -#define EVENT_RFCSEL9_EV_M 0x0000007F -#define EVENT_RFCSEL9_EV_S 0 -#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B -#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A -#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 -#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 -#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D -#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 -#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 -#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 -#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 -#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 -#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 -#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 -#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 -#define EVENT_RFCSEL9_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT0ACAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// PORT_EVENT1 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT1 wil be routed here. -// PORT_EVENT0 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT0 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT0ACAPTSEL_EV_W 7 -#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT0ACAPTSEL_EV_S 0 -#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT0BCAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// PORT_EVENT1 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT1 wil be routed here. -// PORT_EVENT0 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT0 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT0BCAPTSEL_EV_W 7 -#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT0BCAPTSEL_EV_S 0 -#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT1ACAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// PORT_EVENT3 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT3 wil be routed here. -// PORT_EVENT2 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT2 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT1ACAPTSEL_EV_W 7 -#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT1ACAPTSEL_EV_S 0 -#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT1BCAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// PORT_EVENT3 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT3 wil be routed here. -// PORT_EVENT2 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT2 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT1BCAPTSEL_EV_W 7 -#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT1BCAPTSEL_EV_S 0 -#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT2ACAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// PORT_EVENT5 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// PORT_EVENT4 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT2ACAPTSEL_EV_W 7 -#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT2ACAPTSEL_EV_S 0 -#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT2BCAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// PORT_EVENT5 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// PORT_EVENT4 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT2BCAPTSEL_EV_W 7 -#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT2BCAPTSEL_EV_S 0 -#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH1SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by -// UART0:DMACTL.RXDMAE -#define EVENT_UDMACH1SSEL_EV_W 7 -#define EVENT_UDMACH1SSEL_EV_M 0x0000007F -#define EVENT_UDMACH1SSEL_EV_S 0 -#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH1BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by -// UART0:DMACTL.RXDMAE -#define EVENT_UDMACH1BSEL_EV_W 7 -#define EVENT_UDMACH1BSEL_EV_M 0x0000007F -#define EVENT_UDMACH1BSEL_EV_S 0 -#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH2SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by -// UART0:DMACTL.TXDMAE -#define EVENT_UDMACH2SSEL_EV_W 7 -#define EVENT_UDMACH2SSEL_EV_M 0x0000007F -#define EVENT_UDMACH2SSEL_EV_S 0 -#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH2BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by -// UART0:DMACTL.TXDMAE -#define EVENT_UDMACH2BSEL_EV_W 7 -#define EVENT_UDMACH2BSEL_EV_M 0x0000007F -#define EVENT_UDMACH2BSEL_EV_S 0 -#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH3SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by -// SSI0:DMACR.RXDMAE -#define EVENT_UDMACH3SSEL_EV_W 7 -#define EVENT_UDMACH3SSEL_EV_M 0x0000007F -#define EVENT_UDMACH3SSEL_EV_S 0 -#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH3BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by -// SSI0:DMACR.RXDMAE -#define EVENT_UDMACH3BSEL_EV_W 7 -#define EVENT_UDMACH3BSEL_EV_M 0x0000007F -#define EVENT_UDMACH3BSEL_EV_S 0 -#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH4SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by -// SSI0:DMACR.TXDMAE -#define EVENT_UDMACH4SSEL_EV_W 7 -#define EVENT_UDMACH4SSEL_EV_M 0x0000007F -#define EVENT_UDMACH4SSEL_EV_S 0 -#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH4BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by -// SSI0:DMACR.TXDMAE -#define EVENT_UDMACH4BSEL_EV_W 7 -#define EVENT_UDMACH4BSEL_EV_M 0x0000007F -#define EVENT_UDMACH4BSEL_EV_S 0 -#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH5SSEL -// -//***************************************************************************** -//***************************************************************************** -// -// Register: EVENT_O_UDMACH5BSEL -// -//***************************************************************************** -//***************************************************************************** -// -// Register: EVENT_O_UDMACH6SSEL -// -//***************************************************************************** -//***************************************************************************** -// -// Register: EVENT_O_UDMACH6BSEL -// -//***************************************************************************** -//***************************************************************************** -// -// Register: EVENT_O_UDMACH7SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_DMASREQ DMA single request event from AUX, configured by -// AUX_EVCTL:DMACTL -#define EVENT_UDMACH7SSEL_EV_W 7 -#define EVENT_UDMACH7SSEL_EV_M 0x0000007F -#define EVENT_UDMACH7SSEL_EV_S 0 -#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH7BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_DMABREQ DMA burst request event from AUX, configured by -// AUX_EVCTL:DMACTL -#define EVENT_UDMACH7BSEL_EV_W 7 -#define EVENT_UDMACH7BSEL_EV_M 0x0000007F -#define EVENT_UDMACH7BSEL_EV_S 0 -#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH8SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by -// AUX_EVCTL:DMASWREQ.START -#define EVENT_UDMACH8SSEL_EV_W 7 -#define EVENT_UDMACH8SSEL_EV_M 0x0000007F -#define EVENT_UDMACH8SSEL_EV_S 0 -#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH8BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by -// AUX_EVCTL:DMASWREQ.START -#define EVENT_UDMACH8BSEL_EV_W 7 -#define EVENT_UDMACH8BSEL_EV_M 0x0000007F -#define EVENT_UDMACH8BSEL_EV_S 0 -#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH9SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// TIE_LOW Not used tied to 0 -// NONE Always inactive -#define EVENT_UDMACH9SSEL_EV_W 7 -#define EVENT_UDMACH9SSEL_EV_M 0x0000007F -#define EVENT_UDMACH9SSEL_EV_S 0 -#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 -#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH9BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// NONE Always inactive -#define EVENT_UDMACH9BSEL_EV_W 7 -#define EVENT_UDMACH9BSEL_EV_M 0x0000007F -#define EVENT_UDMACH9BSEL_EV_S 0 -#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH10SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// TIE_LOW Not used tied to 0 -// NONE Always inactive -#define EVENT_UDMACH10SSEL_EV_W 7 -#define EVENT_UDMACH10SSEL_EV_M 0x0000007F -#define EVENT_UDMACH10SSEL_EV_S 0 -#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 -#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH10BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// NONE Always inactive -#define EVENT_UDMACH10BSEL_EV_W 7 -#define EVENT_UDMACH10BSEL_EV_M 0x0000007F -#define EVENT_UDMACH10BSEL_EV_S 0 -#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH11SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// TIE_LOW Not used tied to 0 -// NONE Always inactive -#define EVENT_UDMACH11SSEL_EV_W 7 -#define EVENT_UDMACH11SSEL_EV_M 0x0000007F -#define EVENT_UDMACH11SSEL_EV_S 0 -#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 -#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH11BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// NONE Always inactive -#define EVENT_UDMACH11BSEL_EV_W 7 -#define EVENT_UDMACH11BSEL_EV_M 0x0000007F -#define EVENT_UDMACH11BSEL_EV_S 0 -#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH12SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// TIE_LOW Not used tied to 0 -// NONE Always inactive -#define EVENT_UDMACH12SSEL_EV_W 7 -#define EVENT_UDMACH12SSEL_EV_M 0x0000007F -#define EVENT_UDMACH12SSEL_EV_S 0 -#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 -#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH12BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// NONE Always inactive -#define EVENT_UDMACH12BSEL_EV_W 7 -#define EVENT_UDMACH12BSEL_EV_M 0x0000007F -#define EVENT_UDMACH12BSEL_EV_S 0 -#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH13BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_PROG2 AON programmable event 2. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV -#define EVENT_UDMACH13BSEL_EV_W 7 -#define EVENT_UDMACH13BSEL_EV_M 0x0000007F -#define EVENT_UDMACH13BSEL_EV_S 0 -#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH14BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// CPU_HALTED CPU halted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_DMABREQ DMA burst request event from AUX, configured by -// AUX_EVCTL:DMACTL -// AUX_DMASREQ DMA single request event from AUX, configured by -// AUX_EVCTL:DMACTL -// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by -// AUX_EVCTL:DMASWREQ.START -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN -// SWEV3 Software event 3, triggered by SWEV.SWEV3 -// SWEV2 Software event 2, triggered by SWEV.SWEV2 -// SWEV1 Software event 1, triggered by SWEV.SWEV1 -// SWEV0 Software event 0, triggered by SWEV.SWEV0 -// WDT_NMI Watchdog non maskable interrupt event, controlled -// by WDT:CTL.INTTYPE -// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg -// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled -// by CRYPTO:IRQEN.DMA_IN_DONE -// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the -// corresponding flag is found here -// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by -// CRYPTO:IRQSTAT.RESULT_AVAIL -// PORT_EVENT7 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT7 wil be routed here. -// PORT_EVENT6 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT6 wil be routed here. -// PORT_EVENT5 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// PORT_EVENT4 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// PORT_EVENT3 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT3 wil be routed here. -// PORT_EVENT2 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT2 wil be routed here. -// PORT_EVENT1 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT1 wil be routed here. -// PORT_EVENT0 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT0 wil be routed here. -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by -// UART0:DMACTL.TXDMAE -// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by -// UART0:DMACTL.TXDMAE -// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by -// UART0:DMACTL.RXDMAE -// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by -// UART0:DMACTL.RXDMAE -// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by -// SSI0:DMACR.TXDMAE -// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by -// SSI0:DMACR.TXDMAE -// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by -// SSI0:DMACR.RXDMAE -// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by -// SSI0:DMACR.RXDMAE -// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by -// SSI0:DMACR.TXDMAE -// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by -// SSI0:DMACR.TXDMAE -// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by -// SSI0:DMACR.RXDMAE -// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by -// SSI0:DMACR.RXDMAE -// DMA_DONE_COMB Combined DMA done, corresponding flags are here -// UDMA0:REQDONE -// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// AUX_SWEV1 AUX software event 1, triggered by -// AUX_EVCTL:SWEVSET.SWEV1, also available as -// AUX_EVENT2 AON wake up event. -// MCU domain wakeup control -// AON_EVENT:MCUWUSEL -// AUX domain wakeup control -// AON_EVENT:AUXWUSEL -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// WDT_IRQ Watchdog interrupt event, controlled by -// WDT:CTL.INTEN -// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, -// see UDMA0:SOFTREQ -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see -// UDMA0:SOFTREQ -// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR -// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR -// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR -// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR -// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR -// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR -// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR -// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 -// I2C_IRQ Interrupt event from I2C -// I2S_IRQ Interrupt event from I2S -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// AON_PROG2 AON programmable event 2. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV -// AON_PROG1 AON programmable event 1. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV -// AON_PROG0 AON programmable event 0. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV -// NONE Always inactive -#define EVENT_UDMACH14BSEL_EV_W 7 -#define EVENT_UDMACH14BSEL_EV_M 0x0000007F -#define EVENT_UDMACH14BSEL_EV_S 0 -#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 -#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 -#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 -#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 -#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 -#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 -#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 -#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 -#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 -#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E -#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 -#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 -#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 -#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 -#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F -#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E -#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D -#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C -#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B -#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A -#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 -#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 -#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 -#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 -#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 -#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D -#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 -#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 -#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 -#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 -#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 -#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 -#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 -#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 -#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F -#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E -#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D -#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C -#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B -#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 -#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 -#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 -#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 -#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH15BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -#define EVENT_UDMACH15BSEL_EV_W 7 -#define EVENT_UDMACH15BSEL_EV_M 0x0000007F -#define EVENT_UDMACH15BSEL_EV_S 0 -#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH16SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by -// SSI0:DMACR.RXDMAE -#define EVENT_UDMACH16SSEL_EV_W 7 -#define EVENT_UDMACH16SSEL_EV_M 0x0000007F -#define EVENT_UDMACH16SSEL_EV_S 0 -#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH16BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by -// SSI0:DMACR.RXDMAE -#define EVENT_UDMACH16BSEL_EV_W 7 -#define EVENT_UDMACH16BSEL_EV_M 0x0000007F -#define EVENT_UDMACH16BSEL_EV_S 0 -#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH17SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by -// SSI0:DMACR.TXDMAE -#define EVENT_UDMACH17SSEL_EV_W 7 -#define EVENT_UDMACH17SSEL_EV_M 0x0000007F -#define EVENT_UDMACH17SSEL_EV_S 0 -#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH17BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by -// SSI0:DMACR.TXDMAE -#define EVENT_UDMACH17BSEL_EV_W 7 -#define EVENT_UDMACH17BSEL_EV_M 0x0000007F -#define EVENT_UDMACH17BSEL_EV_S 0 -#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH21SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_UDMACH21SSEL_EV_W 7 -#define EVENT_UDMACH21SSEL_EV_M 0x0000007F -#define EVENT_UDMACH21SSEL_EV_S 0 -#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH21BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_UDMACH21BSEL_EV_W 7 -#define EVENT_UDMACH21BSEL_EV_M 0x0000007F -#define EVENT_UDMACH21BSEL_EV_S 0 -#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH22SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV1 Software event 1, triggered by SWEV.SWEV1 -#define EVENT_UDMACH22SSEL_EV_W 7 -#define EVENT_UDMACH22SSEL_EV_M 0x0000007F -#define EVENT_UDMACH22SSEL_EV_S 0 -#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH22BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV1 Software event 1, triggered by SWEV.SWEV1 -#define EVENT_UDMACH22BSEL_EV_W 7 -#define EVENT_UDMACH22BSEL_EV_M 0x0000007F -#define EVENT_UDMACH22BSEL_EV_S 0 -#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH23SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV2 Software event 2, triggered by SWEV.SWEV2 -#define EVENT_UDMACH23SSEL_EV_W 7 -#define EVENT_UDMACH23SSEL_EV_M 0x0000007F -#define EVENT_UDMACH23SSEL_EV_S 0 -#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH23BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV2 Software event 2, triggered by SWEV.SWEV2 -#define EVENT_UDMACH23BSEL_EV_W 7 -#define EVENT_UDMACH23BSEL_EV_M 0x0000007F -#define EVENT_UDMACH23BSEL_EV_S 0 -#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH24SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV3 Software event 3, triggered by SWEV.SWEV3 -#define EVENT_UDMACH24SSEL_EV_W 7 -#define EVENT_UDMACH24SSEL_EV_M 0x0000007F -#define EVENT_UDMACH24SSEL_EV_S 0 -#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH24BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV3 Software event 3, triggered by SWEV.SWEV3 -#define EVENT_UDMACH24BSEL_EV_W 7 -#define EVENT_UDMACH24BSEL_EV_M 0x0000007F -#define EVENT_UDMACH24BSEL_EV_S 0 -#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 - -//***************************************************************************** -// -// Register: EVENT_O_GPT3ACAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// PORT_EVENT7 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT7 wil be routed here. -// PORT_EVENT6 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT6 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT3ACAPTSEL_EV_W 7 -#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT3ACAPTSEL_EV_S 0 -#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT3BCAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags -// are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.TDC_DONE and the -// AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, corresponds flags are here -// AUX_EVCTL:EVTOMCUFLAGS.AON_WU_EV -// PORT_EVENT7 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT7 wil be routed here. -// PORT_EVENT6 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT6 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT3BCAPTSEL_EV_W 7 -#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT3BCAPTSEL_EV_S 0 -#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_AUXSEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR -// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR -// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR -// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR -// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR -// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR -// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR -// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR -// NONE Always inactive -#define EVENT_AUXSEL0_EV_W 7 -#define EVENT_AUXSEL0_EV_M 0x0000007F -#define EVENT_AUXSEL0_EV_S 0 -#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 -#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 -#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 -#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 -#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F -#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E -#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D -#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C -#define EVENT_AUXSEL0_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_CM3NMISEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// WDT_NMI Watchdog non maskable interrupt event, controlled -// by WDT:CTL.INTTYPE -#define EVENT_CM3NMISEL0_EV_W 7 -#define EVENT_CM3NMISEL0_EV_M 0x0000007F -#define EVENT_CM3NMISEL0_EV_S 0 -#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 - -//***************************************************************************** -// -// Register: EVENT_O_I2SSTMPSEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// NONE Always inactive -#define EVENT_I2SSTMPSEL0_EV_W 7 -#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F -#define EVENT_I2SSTMPSEL0_EV_S 0 -#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_FRZSEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// CPU_HALTED CPU halted -// NONE Always inactive -#define EVENT_FRZSEL0_EV_W 7 -#define EVENT_FRZSEL0_EV_M 0x0000007F -#define EVENT_FRZSEL0_EV_S 0 -#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 -#define EVENT_FRZSEL0_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_SWEV -// -//***************************************************************************** -// Field: [24] SWEV3 -// -// Writing "1" to this bit when the value is "0" triggers the Software 3 event. -#define EVENT_SWEV_SWEV3 0x01000000 -#define EVENT_SWEV_SWEV3_BITN 24 -#define EVENT_SWEV_SWEV3_M 0x01000000 -#define EVENT_SWEV_SWEV3_S 24 - -// Field: [16] SWEV2 -// -// Writing "1" to this bit when the value is "0" triggers the Software 2 event. -#define EVENT_SWEV_SWEV2 0x00010000 -#define EVENT_SWEV_SWEV2_BITN 16 -#define EVENT_SWEV_SWEV2_M 0x00010000 -#define EVENT_SWEV_SWEV2_S 16 - -// Field: [8] SWEV1 -// -// Writing "1" to this bit when the value is "0" triggers the Software 1 event. -#define EVENT_SWEV_SWEV1 0x00000100 -#define EVENT_SWEV_SWEV1_BITN 8 -#define EVENT_SWEV_SWEV1_M 0x00000100 -#define EVENT_SWEV_SWEV1_S 8 - -// Field: [0] SWEV0 -// -// Writing "1" to this bit when the value is "0" triggers the Software 0 event. -#define EVENT_SWEV_SWEV0 0x00000001 -#define EVENT_SWEV_SWEV0_BITN 0 -#define EVENT_SWEV_SWEV0_M 0x00000001 -#define EVENT_SWEV_SWEV0_S 0 - - -#endif // __EVENT__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_fcfg1.h b/third_party/ti/devices/cc26x0/inc/hw_fcfg1.h deleted file mode 100644 index a5bd61674..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_fcfg1.h +++ /dev/null @@ -1,2921 +0,0 @@ -/****************************************************************************** -* Filename: hw_fcfg1_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_FCFG1_H__ -#define __HW_FCFG1_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// FCFG1 component -// -//***************************************************************************** -// Misc configurations -#define FCFG1_O_MISC_CONF_1 0x000000A0 - -// Internal -#define FCFG1_O_MISC_CONF_2 0x000000A4 - -// Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV5 0x000000C4 - -// Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV6 0x000000C8 - -// Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV10 0x000000CC - -// Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV12 0x000000D0 - -// Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV15 0x000000D4 - -// Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV30 0x000000D8 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000DC - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV6 0x000000E0 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000E4 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV12 0x000000E8 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV15 0x000000EC - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV30 0x000000F0 - -// Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV5 0x000000F4 - -// Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV6 0x000000F8 - -// Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV10 0x000000FC - -// Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV12 0x00000100 - -// Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV15 0x00000104 - -// Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV30 0x00000108 - -// Shadow of EFUSE:DIE_ID_0 -#define FCFG1_O_SHDW_DIE_ID_0 0x00000118 - -// Shadow of EFUSE:DIE_ID_1 -#define FCFG1_O_SHDW_DIE_ID_1 0x0000011C - -// Shadow of EFUSE:DIE_ID_2 -#define FCFG1_O_SHDW_DIE_ID_2 0x00000120 - -// Shadow of EFUSE:DIE_ID_3 -#define FCFG1_O_SHDW_DIE_ID_3 0x00000124 - -// Internal -#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x00000138 - -// Internal -#define FCFG1_O_SHDW_ANA_TRIM 0x0000013C - -#define FCFG1_O_FLASH_NUMBER 0x00000164 - -#define FCFG1_O_FLASH_COORDINATE 0x0000016C - -// Internal -#define FCFG1_O_FLASH_E_P 0x00000170 - -// Internal -#define FCFG1_O_FLASH_C_E_P_R 0x00000174 - -// Internal -#define FCFG1_O_FLASH_P_R_PV 0x00000178 - -// Internal -#define FCFG1_O_FLASH_EH_SEQ 0x0000017C - -// Internal -#define FCFG1_O_FLASH_VHV_E 0x00000180 - -// Internal -#define FCFG1_O_FLASH_PP 0x00000184 - -// Internal -#define FCFG1_O_FLASH_PROG_EP 0x00000188 - -// Internal -#define FCFG1_O_FLASH_ERA_PW 0x0000018C - -// Internal -#define FCFG1_O_FLASH_VHV 0x00000190 - -// Internal -#define FCFG1_O_FLASH_VHV_PV 0x00000194 - -// Internal -#define FCFG1_O_FLASH_V 0x00000198 - -// User Identification. -#define FCFG1_O_USER_ID 0x00000294 - -// Internal -#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 - -// Internal -#define FCFG1_O_ANA2_TRIM 0x000002B4 - -// Internal -#define FCFG1_O_LDO_TRIM 0x000002B8 - -// Internal -#define FCFG1_O_BAT_RC_LDO_TRIM 0x000002BC - -// MAC BLE Address 0 -#define FCFG1_O_MAC_BLE_0 0x000002E8 - -// MAC BLE Address 1 -#define FCFG1_O_MAC_BLE_1 0x000002EC - -// MAC IEEE 802.15.4 Address 0 -#define FCFG1_O_MAC_15_4_0 0x000002F0 - -// MAC IEEE 802.15.4 Address 1 -#define FCFG1_O_MAC_15_4_1 0x000002F4 - -// Internal -#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 - -// Miscellaneous Trim Parameters -#define FCFG1_O_MISC_TRIM 0x0000030C - -// Internal -#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 - -// Internal -#define FCFG1_O_TRIM_CAL_REVISION 0x00000314 - -// IcePick Device Identification -#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 - -// Factory Configuration (FCFG1) Revision -#define FCFG1_O_FCFG1_REVISION 0x0000031C - -// Misc OTP Data -#define FCFG1_O_MISC_OTP_DATA 0x00000320 - -// IO Configuration -#define FCFG1_O_IOCONF 0x00000344 - -// Internal -#define FCFG1_O_CONFIG_IF_ADC 0x0000034C - -// Internal -#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 - -// Internal -#define FCFG1_O_CONFIG_RF_FRONTEND 0x00000354 - -// Internal -#define FCFG1_O_CONFIG_SYNTH 0x00000358 - -// AUX_ADC Gain in Absolute Reference Mode -#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C - -// AUX_ADC Gain in Relative Reference Mode -#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 - -// AUX_ADC Temperature Offsets in Absolute Reference Mode -#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 - -// Internal -#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C - -// Internal -#define FCFG1_O_AMPCOMP_TH1 0x00000370 - -// Internal -#define FCFG1_O_AMPCOMP_TH2 0x00000374 - -// Internal -#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 - -// Internal -#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C - -// Internal -#define FCFG1_O_CONFIG_MISC_ADC 0x00000380 - -// Internal -#define FCFG1_O_VOLT_TRIM 0x00000388 - -// OSC Configuration -#define FCFG1_O_OSC_CONF 0x0000038C - -// Internal -#define FCFG1_O_FREQ_OFFSET 0x00000390 - -// Internal -#define FCFG1_O_CAP_TRIM 0x00000394 - -// Internal -#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 - -// Power Down Current Control 20C -#define FCFG1_O_PWD_CURR_20C 0x0000039C - -// Power Down Current Control 35C -#define FCFG1_O_PWD_CURR_35C 0x000003A0 - -// Power Down Current Control 50C -#define FCFG1_O_PWD_CURR_50C 0x000003A4 - -// Power Down Current Control 65C -#define FCFG1_O_PWD_CURR_65C 0x000003A8 - -// Power Down Current Control 80C -#define FCFG1_O_PWD_CURR_80C 0x000003AC - -// Power Down Current Control 95C -#define FCFG1_O_PWD_CURR_95C 0x000003B0 - -// Power Down Current Control 110C -#define FCFG1_O_PWD_CURR_110C 0x000003B4 - -// Power Down Current Control 125C -#define FCFG1_O_PWD_CURR_125C 0x000003B8 - -//***************************************************************************** -// -// Register: FCFG1_O_MISC_CONF_1 -// -//***************************************************************************** -// Field: [7:0] DEVICE_MINOR_REV -// -// HW minor revision number (a value of 0xFF shall be treated equally to 0x00). -// Any test of this field by SW should be implemented as a 'greater or equal' -// comparison as signed integer. -// Value may change without warning. -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MISC_CONF_2 -// -//***************************************************************************** -// Field: [7:0] HPOSC_COMP_P3 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV5 -// -//***************************************************************************** -// Field: [31:28] IFAMP_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_S 28 - -// Field: [27:24] LNA_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_S 24 - -// Field: [23:19] IFAMP_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_S 19 - -// Field: [18:14] CTL_PA0_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_S 14 - -// Field: [6:0] RFLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV6 -// -//***************************************************************************** -// Field: [31:28] IFAMP_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_S 28 - -// Field: [27:24] LNA_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_S 24 - -// Field: [23:19] IFAMP_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_S 19 - -// Field: [18:14] CTL_PA0_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_S 14 - -// Field: [6:0] RFLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV10 -// -//***************************************************************************** -// Field: [31:28] IFAMP_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_S 28 - -// Field: [27:24] LNA_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_S 24 - -// Field: [23:19] IFAMP_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_S 19 - -// Field: [18:14] CTL_PA0_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_S 14 - -// Field: [6:0] RFLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV12 -// -//***************************************************************************** -// Field: [31:28] IFAMP_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_S 28 - -// Field: [27:24] LNA_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_S 24 - -// Field: [23:19] IFAMP_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_S 19 - -// Field: [18:14] CTL_PA0_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_S 14 - -// Field: [6:0] RFLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV15 -// -//***************************************************************************** -// Field: [31:28] IFAMP_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_S 28 - -// Field: [27:24] LNA_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_S 24 - -// Field: [23:19] IFAMP_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_S 19 - -// Field: [18:14] CTL_PA0_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_S 14 - -// Field: [6:0] RFLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_RF_FRONTEND_DIV30 -// -//***************************************************************************** -// Field: [31:28] IFAMP_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_S 28 - -// Field: [27:24] LNA_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_S 24 - -// Field: [23:19] IFAMP_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_S 19 - -// Field: [18:14] CTL_PA0_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_S 14 - -// Field: [6:0] RFLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV5 -// -//***************************************************************************** -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Trim value for RF Core. -// Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5:0] SLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV6 -// -//***************************************************************************** -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Trim value for RF Core. -// Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5:0] SLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV10 -// -//***************************************************************************** -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Trim value for RF Core. -// Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5:0] SLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV12 -// -//***************************************************************************** -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Trim value for RF Core. -// Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5:0] SLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV15 -// -//***************************************************************************** -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Trim value for RF Core. -// Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5:0] SLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV30 -// -//***************************************************************************** -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Trim value for RF Core. -// Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5:0] SLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_MISC_ADC_DIV5 -// -//***************************************************************************** -// Field: [16:9] RSSI_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_S 9 - -// Field: [8:6] QUANTCTLTHRES -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_S 6 - -// Field: [5:0] DACTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_MISC_ADC_DIV6 -// -//***************************************************************************** -// Field: [16:9] RSSI_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_S 9 - -// Field: [8:6] QUANTCTLTHRES -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_S 6 - -// Field: [5:0] DACTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_MISC_ADC_DIV10 -// -//***************************************************************************** -// Field: [16:9] RSSI_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_S 9 - -// Field: [8:6] QUANTCTLTHRES -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_S 6 - -// Field: [5:0] DACTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_MISC_ADC_DIV12 -// -//***************************************************************************** -// Field: [16:9] RSSI_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_S 9 - -// Field: [8:6] QUANTCTLTHRES -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_S 6 - -// Field: [5:0] DACTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_MISC_ADC_DIV15 -// -//***************************************************************************** -// Field: [16:9] RSSI_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_S 9 - -// Field: [8:6] QUANTCTLTHRES -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_S 6 - -// Field: [5:0] DACTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_MISC_ADC_DIV30 -// -//***************************************************************************** -// Field: [16:9] RSSI_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_S 9 - -// Field: [8:6] QUANTCTLTHRES -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_S 6 - -// Field: [5:0] DACTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_DIE_ID_0 -// -//***************************************************************************** -// Field: [31:0] ID_31_0 -// -// Shadow of DIE_ID_0 register in eFuse row number 3 -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_DIE_ID_1 -// -//***************************************************************************** -// Field: [31:0] ID_63_32 -// -// Shadow of DIE_ID_1 register in eFuse row number 4 -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_DIE_ID_2 -// -//***************************************************************************** -// Field: [31:0] ID_95_64 -// -// Shadow of DIE_ID_2 register in eFuse row number 5 -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_DIE_ID_3 -// -//***************************************************************************** -// Field: [31:0] ID_127_96 -// -// Shadow of DIE_ID_3 register in eFuse row number 6 -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM -// -//***************************************************************************** -// Field: [28:27] SET_RCOSC_HF_COARSE_RESISTOR -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_W \ - 2 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_M \ - 0x18000000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_S \ - 27 - -// Field: [26:23] TRIMMAG -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 - -// Field: [22:18] TRIMIREF -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 - -// Field: [17:16] ITRIM_DIG_LDO -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 - -// Field: [15:12] VTRIM_DIG -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 - -// Field: [11:8] VTRIM_COARSE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 - -// Field: [7:0] RCOSCHF_CTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_ANA_TRIM -// -//***************************************************************************** -// Field: [26:25] BOD_BANDGAP_TRIM_CNF -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 - -// Field: [24] VDDR_ENABLE_PG1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 - -// Field: [23] VDDR_OK_HYS -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 - -// Field: [22:21] IPTAT_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 - -// Field: [20:16] VDDR_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 - -// Field: [15:11] TRIMBOD_INTMODE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 - -// Field: [10:6] TRIMBOD_EXTMODE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 - -// Field: [5:0] TRIMTEMP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_NUMBER -// -//***************************************************************************** -// Field: [31:0] LOT_NUMBER -// -// Number of the manufacturing lot that produced this unit. -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_COORDINATE -// -//***************************************************************************** -// Field: [31:16] XCOORDINATE -// -// X coordinate of this unit on the wafer. -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 - -// Field: [15:0] YCOORDINATE -// -// Y coordinate of this unit on the wafer. -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_E_P -// -//***************************************************************************** -// Field: [31:24] PSU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_PSU_W 8 -#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 -#define FCFG1_FLASH_E_P_PSU_S 24 - -// Field: [23:16] ESU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_ESU_W 8 -#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 -#define FCFG1_FLASH_E_P_ESU_S 16 - -// Field: [15:8] PVSU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_PVSU_W 8 -#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 -#define FCFG1_FLASH_E_P_PVSU_S 8 - -// Field: [7:0] EVSU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_EVSU_W 8 -#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF -#define FCFG1_FLASH_E_P_EVSU_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_C_E_P_R -// -//***************************************************************************** -// Field: [31:24] RVSU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 -#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 -#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 - -// Field: [23:16] PV_ACCESS -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 - -// Field: [15:12] A_EXEZ_SETUP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 - -// Field: [11:0] CVSU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 -#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF -#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_P_R_PV -// -//***************************************************************************** -// Field: [31:24] PH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PH_W 8 -#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 -#define FCFG1_FLASH_P_R_PV_PH_S 24 - -// Field: [23:16] RH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_RH_W 8 -#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 -#define FCFG1_FLASH_P_R_PV_RH_S 16 - -// Field: [15:8] PVH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PVH_W 8 -#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 -#define FCFG1_FLASH_P_R_PV_PVH_S 8 - -// Field: [7:0] PVH2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PVH2_W 8 -#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF -#define FCFG1_FLASH_P_R_PV_PVH2_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_EH_SEQ -// -//***************************************************************************** -// Field: [31:24] EH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_EH_W 8 -#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 -#define FCFG1_FLASH_EH_SEQ_EH_S 24 - -// Field: [23:16] SEQ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 -#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 -#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 - -// Field: [15:12] VSTAT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 -#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 -#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 - -// Field: [11:0] SM_FREQUENCY -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_VHV_E -// -//***************************************************************************** -// Field: [31:16] VHV_E_START -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 -#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 -#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 - -// Field: [15:0] VHV_E_STEP_HIGHT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_PP -// -//***************************************************************************** -// Field: [31:24] PUMP_SU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_PUMP_SU_W 8 -#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 -#define FCFG1_FLASH_PP_PUMP_SU_S 24 - -// Field: [15:0] MAX_PP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_MAX_PP_W 16 -#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF -#define FCFG1_FLASH_PP_MAX_PP_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_PROG_EP -// -//***************************************************************************** -// Field: [31:16] MAX_EP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 -#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 -#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 - -// Field: [15:0] PROGRAM_PW -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_ERA_PW -// -//***************************************************************************** -// Field: [31:0] ERASE_PW -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 -#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF -#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_VHV -// -//***************************************************************************** -// Field: [27:24] TRIM13_P -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_TRIM13_P_W 4 -#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 -#define FCFG1_FLASH_VHV_TRIM13_P_S 24 - -// Field: [19:16] VHV_P -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_VHV_P_W 4 -#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 -#define FCFG1_FLASH_VHV_VHV_P_S 16 - -// Field: [11:8] TRIM13_E -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_TRIM13_E_W 4 -#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 -#define FCFG1_FLASH_VHV_TRIM13_E_S 8 - -// Field: [3:0] VHV_E -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_VHV_E_W 4 -#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F -#define FCFG1_FLASH_VHV_VHV_E_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_VHV_PV -// -//***************************************************************************** -// Field: [27:24] TRIM13_PV -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 - -// Field: [19:16] VHV_PV -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 -#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 -#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 - -// Field: [15:8] VCG2P5 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 -#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 -#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 - -// Field: [7:0] VINH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VINH_W 8 -#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF -#define FCFG1_FLASH_VHV_PV_VINH_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_V -// -//***************************************************************************** -// Field: [31:24] VSL_P -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_VSL_P_W 8 -#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 -#define FCFG1_FLASH_V_VSL_P_S 24 - -// Field: [23:16] VWL_P -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_VWL_P_W 8 -#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 -#define FCFG1_FLASH_V_VWL_P_S 16 - -// Field: [15:8] V_READ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_V_READ_W 8 -#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 -#define FCFG1_FLASH_V_V_READ_S 8 - -//***************************************************************************** -// -// Register: FCFG1_O_USER_ID -// -//***************************************************************************** -// Field: [31:28] PG_REV -// -// Field used to distinguish revisions of the device. -#define FCFG1_USER_ID_PG_REV_W 4 -#define FCFG1_USER_ID_PG_REV_M 0xF0000000 -#define FCFG1_USER_ID_PG_REV_S 28 - -// Field: [27:26] VER -// -// Version number. -// -// 0x0: Bits [25:12] of this register has the stated meaning. -// -// Any other setting indicate a different encoding of these bits. -#define FCFG1_USER_ID_VER_W 2 -#define FCFG1_USER_ID_VER_M 0x0C000000 -#define FCFG1_USER_ID_VER_S 26 - -// Field: [22:19] SEQUENCE -// -// Sequence. -// -// Used to differentiate between marketing/orderable product where other fields -// of USER_ID is the same (temp range, flash size, voltage range etc) -#define FCFG1_USER_ID_SEQUENCE_W 4 -#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 -#define FCFG1_USER_ID_SEQUENCE_S 19 - -// Field: [18:16] PKG -// -// Package type. -// -// 0x0: 4x4mm QFN (RHB) package -// 0x1: 5x5mm QFN (RSM) package -// 0x2: 7x7mm QFN (RGZ) package -// 0x3: Wafer sale package (naked die) -// 0x4: 2.7x2.7mm WCSP (YFV) -// 0x5: 7x7mm QFN package with Wettable Flanks -// -// Other values are reserved for future use. -// Packages available for a specific device are shown in the device datasheet. -#define FCFG1_USER_ID_PKG_W 3 -#define FCFG1_USER_ID_PKG_M 0x00070000 -#define FCFG1_USER_ID_PKG_S 16 - -// Field: [15:12] PROTOCOL -// -// Protocols supported. -// -// 0x1: BLE -// 0x2: RF4CE -// 0x4: Zigbee/6lowpan -// 0x8: Proprietary -// -// More than one protocol can be supported on same device - values above are -// then combined. -#define FCFG1_USER_ID_PROTOCOL_W 4 -#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 -#define FCFG1_USER_ID_PROTOCOL_S 12 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_OTP_DATA3 -// -//***************************************************************************** -// Field: [31:23] EC_STEP_SIZE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 - -// Field: [22] DO_PRECOND -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 - -// Field: [21:18] MAX_EC_LEVEL -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 - -// Field: [17:16] TRIM_1P7 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 - -// Field: [15:8] FLASH_SIZE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 - -// Field: [7:0] WAIT_SYSCODE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_ANA2_TRIM -// -//***************************************************************************** -// Field: [31] RCOSCHFCTRIMFRACT_EN -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 - -// Field: [30:26] RCOSCHFCTRIMFRACT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 - -// Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 - -// Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 - -// Field: [21:16] NANOAMP_RES_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 6 -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F0000 -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 16 - -// Field: [11] DITHER_EN -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 -#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 -#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 -#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 - -// Field: [10:8] DCDC_IPEAK -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 - -// Field: [7:6] DEAD_TIME_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 - -// Field: [5:3] DCDC_LOW_EN_SEL -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 - -// Field: [2:0] DCDC_HIGH_EN_SEL -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_LDO_TRIM -// -//***************************************************************************** -// Field: [28:24] VDDR_TRIM_SLEEP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 - -// Field: [18:16] GLDO_CURSRC -// -// Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 -#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 -#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 - -// Field: [12:11] ITRIM_DIGLDO_LOAD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 - -// Field: [10:8] ITRIM_UDIGLDO -// -// Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 - -// Field: [2:0] VTRIM_DELTA -// -// Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 -#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 -#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_BAT_RC_LDO_TRIM -// -//***************************************************************************** -// Field: [27:24] VTRIM_BOD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_W 4 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M 0x0F000000 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S 24 - -// Field: [19:16] VTRIM_UDIG -// -// Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_W 4 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M 0x000F0000 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S 16 - -// Field: [11:8] RCOSCHF_ITUNE_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_W 4 -#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_M 0x00000F00 -#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_S 8 - -// Field: [1:0] MEASUREPER -// -// Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_W 2 -#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_M 0x00000003 -#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MAC_BLE_0 -// -//***************************************************************************** -// Field: [31:0] ADDR_0_31 -// -// The first 32-bits of the 64-bit MAC BLE address -#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 -#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF -#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MAC_BLE_1 -// -//***************************************************************************** -// Field: [31:0] ADDR_32_63 -// -// The last 32-bits of the 64-bit MAC BLE address -#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 -#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF -#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MAC_15_4_0 -// -//***************************************************************************** -// Field: [31:0] ADDR_0_31 -// -// The first 32-bits of the 64-bit MAC 15.4 address -#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 -#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF -#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MAC_15_4_1 -// -//***************************************************************************** -// Field: [31:0] ADDR_32_63 -// -// The last 32-bits of the 64-bit MAC 15.4 address -#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 -#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF -#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_OTP_DATA4 -// -//***************************************************************************** -// Field: [31] STANDBY_MODE_SEL_INT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 - -// Field: [30:29] STANDBY_PW_SEL_INT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 - -// Field: [28] DIS_STANDBY_INT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 - -// Field: [27] DIS_IDLE_INT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 - -// Field: [26:24] VIN_AT_X_INT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 - -// Field: [23] STANDBY_MODE_SEL_EXT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 - -// Field: [22:21] STANDBY_PW_SEL_EXT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 - -// Field: [20] DIS_STANDBY_EXT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 - -// Field: [19] DIS_IDLE_EXT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 - -// Field: [18:16] VIN_AT_X_EXT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 - -// Field: [15] STANDBY_MODE_SEL_INT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 - -// Field: [14:13] STANDBY_PW_SEL_INT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 - -// Field: [12] DIS_STANDBY_INT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 - -// Field: [11] DIS_IDLE_INT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 - -// Field: [10:8] VIN_AT_X_INT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 - -// Field: [7] STANDBY_MODE_SEL_EXT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 - -// Field: [6:5] STANDBY_PW_SEL_EXT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 - -// Field: [4] DIS_STANDBY_EXT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 - -// Field: [3] DIS_IDLE_EXT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 - -// Field: [2:0] VIN_AT_X_EXT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MISC_TRIM -// -//***************************************************************************** -// Field: [7:0] TEMPVSLOPE -// -// Signed byte value representing the TEMP slope with battery voltage, in -// degrees C / V, with four fractional bits. -#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 -#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF -#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_RCOSC_HF_TEMPCOMP -// -//***************************************************************************** -// Field: [31:24] FINE_RESISTOR -// -// Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 - -// Field: [23:16] CTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 - -// Field: [15:8] CTRIMFRACT_QUAD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 - -// Field: [7:0] CTRIMFRACT_SLOPE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_TRIM_CAL_REVISION -// -//***************************************************************************** -// Field: [31:16] FT1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_TRIM_CAL_REVISION_FT1_W 16 -#define FCFG1_TRIM_CAL_REVISION_FT1_M 0xFFFF0000 -#define FCFG1_TRIM_CAL_REVISION_FT1_S 16 - -// Field: [15:0] MP1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_TRIM_CAL_REVISION_MP1_W 16 -#define FCFG1_TRIM_CAL_REVISION_MP1_M 0x0000FFFF -#define FCFG1_TRIM_CAL_REVISION_MP1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_ICEPICK_DEVICE_ID -// -//***************************************************************************** -// Field: [31:28] PG_REV -// -// Field used to distinguish revisions of the device. -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 - -// Field: [27:12] WAFER_ID -// -// Field used to identify silicon die. -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 - -// Field: [11:0] MANUFACTURER_ID -// -// Manufacturer code. -// -// 0x02F: Texas Instruments -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FCFG1_REVISION -// -//***************************************************************************** -// Field: [31:0] REV -// -// The revision number of the FCFG1 layout. This value will be read by -// application SW in order to determine which FCFG1 parameters that have valid -// values. This revision number must be incremented by 1 before any devices are -// to be produced if the FCFG1 layout has changed since the previous production -// of devices. -// Value migth change without warning. -#define FCFG1_FCFG1_REVISION_REV_W 32 -#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF -#define FCFG1_FCFG1_REVISION_REV_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MISC_OTP_DATA -// -//***************************************************************************** -// Field: [31:28] RCOSC_HF_ITUNE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 - -// Field: [27:20] RCOSC_HF_CRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 - -// Field: [19:15] PER_M -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PER_M_W 5 -#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 -#define FCFG1_MISC_OTP_DATA_PER_M_S 15 - -// Field: [14:12] PER_E -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PER_E_W 3 -#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 -#define FCFG1_MISC_OTP_DATA_PER_E_S 12 - -// Field: [11:8] PO_TAIL_RES_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_W 4 -#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_M 0x00000F00 -#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_S 8 - -// Field: [7:0] TEST_PROGRAM_REV -// -// The revision of the test program used in the production process when FCFG1 -// was programmed. -// Value migth change without warning. -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8 -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_IOCONF -// -//***************************************************************************** -// Field: [6:0] GPIO_CNT -// -// Number of available DIOs. -#define FCFG1_IOCONF_GPIO_CNT_W 7 -#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F -#define FCFG1_IOCONF_GPIO_CNT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_IF_ADC -// -//***************************************************************************** -// Field: [31:28] FF2ADJ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 - -// Field: [27:24] FF3ADJ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 - -// Field: [23:20] INT3ADJ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 - -// Field: [19:16] FF1ADJ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 - -// Field: [15:14] AAFCAP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 -#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 -#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 - -// Field: [13:10] INT2ADJ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 - -// Field: [9:5] IFDIGLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 - -// Field: [4:0] IFANALDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_OSC_TOP -// -//***************************************************************************** -// Field: [29:26] XOSC_HF_ROW_Q12 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 - -// Field: [25:10] XOSC_HF_COLUMN_Q12 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 - -// Field: [9:2] RCOSCLF_CTUNE_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 - -// Field: [1:0] RCOSCLF_RTUNE_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_RF_FRONTEND -// -//***************************************************************************** -// Field: [31:28] IFAMP_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_S 28 - -// Field: [27:24] LNA_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_S 24 - -// Field: [23:19] IFAMP_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_S 19 - -// Field: [18:14] CTL_PA0_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_S 14 - -// Field: [13] PATRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N 0x00002000 -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_BITN 13 -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_M 0x00002000 -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_S 13 - -// Field: [6:0] RFLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH -// -//***************************************************************************** -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5:0] SLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SOC_ADC_ABS_GAIN -// -//***************************************************************************** -// Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1 -// -// SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated -// in production test.. -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SOC_ADC_REL_GAIN -// -//***************************************************************************** -// Field: [15:0] SOC_ADC_REL_GAIN_TEMP1 -// -// SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated -// in production test.. -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SOC_ADC_OFFSET_INT -// -//***************************************************************************** -// Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1 -// -// SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed -// 8-bit number. Calculated in production test.. -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 - -// Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 -// -// SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed -// 8-bit number. Calculated in production test.. -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT -// -//***************************************************************************** -// Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \ - 6 -#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \ - 0x0000003F -#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \ - 0 - -//***************************************************************************** -// -// Register: FCFG1_O_AMPCOMP_TH1 -// -//***************************************************************************** -// Field: [23:18] HPMRAMP3_LTH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 - -// Field: [15:10] HPMRAMP3_HTH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 - -// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 - -// Field: [5:0] HPMRAMP1_TH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_AMPCOMP_TH2 -// -//***************************************************************************** -// Field: [31:26] LPMUPDATE_LTH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 - -// Field: [23:18] LPMUPDATE_HTM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 - -// Field: [15:10] ADC_COMP_AMPTH_LPM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 - -// Field: [7:2] ADC_COMP_AMPTH_HPM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 - -//***************************************************************************** -// -// Register: FCFG1_O_AMPCOMP_CTRL1 -// -//***************************************************************************** -// Field: [30] AMPCOMP_REQ_MODE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 - -// Field: [23:20] IBIAS_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 - -// Field: [19:16] IBIAS_INIT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 - -// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 - -// Field: [7:4] CAP_STEP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 - -// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_ANABYPASS_VALUE2 -// -//***************************************************************************** -// Field: [13:0] XOSC_HF_IBIASTHERM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_MISC_ADC -// -//***************************************************************************** -// Field: [17] RSSITRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N 0x00020000 -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_BITN 17 -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_M 0x00020000 -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_S 17 - -// Field: [16:9] RSSI_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_S 9 - -// Field: [8:6] QUANTCTLTHRES -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_S 6 - -// Field: [5:0] DACTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DACTRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_VOLT_TRIM -// -//***************************************************************************** -// Field: [28:24] VDDR_TRIM_HH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 - -// Field: [20:16] VDDR_TRIM_H -// -// Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 - -// Field: [12:8] VDDR_TRIM_SLEEP_H -// -// Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 - -// Field: [4:0] TRIMBOD_H -// -// Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 -#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F -#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_OSC_CONF -// -//***************************************************************************** -// Field: [29] ADC_SH_VBUF_EN -// -// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 - -// Field: [28] ADC_SH_MODE_EN -// -// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 - -// Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM -// -// Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 - -// Field: [26:25] XOSCLF_REGULATOR_TRIM -// -// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 - -// Field: [24:21] XOSCLF_CMIRRWR_RATIO -// -// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 - -// Field: [20:19] XOSC_HF_FAST_START -// -// Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 - -// Field: [18] XOSC_OPTION -// -// 0: XOSC_HF unavailable (may not be bonded out) -// 1: XOSC_HF available (default) -#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 -#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 -#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 -#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 - -// Field: [17] HPOSC_OPTION -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 -#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 -#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 -#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 - -// Field: [16] HPOSC_BIAS_HOLD_MODE_EN -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 - -// Field: [15:12] HPOSC_CURRMIRR_RATIO -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 - -// Field: [11:8] HPOSC_BIAS_RES_SET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 - -// Field: [7] HPOSC_FILTER_EN -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 - -// Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 - -// Field: [2:1] HPOSC_SERIES_CAP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 - -// Field: [0] HPOSC_DIV3_BYPASS -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FREQ_OFFSET -// -//***************************************************************************** -// Field: [31:16] HPOSC_COMP_P0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 - -// Field: [15:8] HPOSC_COMP_P1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 - -// Field: [7:0] HPOSC_COMP_P2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CAP_TRIM -// -//***************************************************************************** -// Field: [31:16] FLUX_CAP_0P28_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_W 16 -#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_M 0xFFFF0000 -#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_S 16 - -// Field: [15:0] FLUX_CAP_0P4_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_W 16 -#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_M 0x0000FFFF -#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MISC_OTP_DATA_1 -// -//***************************************************************************** -// Field: [28:27] PEAK_DET_ITRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 - -// Field: [26:24] HP_BUF_ITRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 - -// Field: [23:22] LP_BUF_ITRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 - -// Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 - -// Field: [19:10] HPM_IBIAS_WAIT_CNT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 - -// Field: [9:4] LPM_IBIAS_WAIT_CNT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 - -// Field: [3:0] IDAC_STEP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_20C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_20C_BASELINE_W 8 -#define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_20C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_35C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_35C_BASELINE_W 8 -#define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_35C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_50C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_50C_BASELINE_W 8 -#define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_50C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_65C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_65C_BASELINE_W 8 -#define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_65C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_80C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_80C_BASELINE_W 8 -#define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_80C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_95C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_95C_BASELINE_W 8 -#define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_95C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_110C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_110C_BASELINE_W 8 -#define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_110C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_125C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_125C_BASELINE_W 8 -#define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_125C_BASELINE_S 0 - - -#endif // __FCFG1__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_flash.h b/third_party/ti/devices/cc26x0/inc/hw_flash.h deleted file mode 100644 index f5af0e5d6..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_flash.h +++ /dev/null @@ -1,3475 +0,0 @@ -/****************************************************************************** -* Filename: hw_flash_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// FLASH component -// -//***************************************************************************** -// FMC and Efuse Status -#define FLASH_O_STAT 0x0000001C - -// Internal -#define FLASH_O_CFG 0x00000024 - -// Internal -#define FLASH_O_SYSCODE_START 0x00000028 - -// Internal -#define FLASH_O_FLASH_SIZE 0x0000002C - -// Internal -#define FLASH_O_FWLOCK 0x0000003C - -// Internal -#define FLASH_O_FWFLAG 0x00000040 - -// Internal -#define FLASH_O_EFUSE 0x00001000 - -// Internal -#define FLASH_O_EFUSEADDR 0x00001004 - -// Internal -#define FLASH_O_DATAUPPER 0x00001008 - -// Internal -#define FLASH_O_DATALOWER 0x0000100C - -// Internal -#define FLASH_O_EFUSECFG 0x00001010 - -// Internal -#define FLASH_O_EFUSESTAT 0x00001014 - -// Internal -#define FLASH_O_ACC 0x00001018 - -// Internal -#define FLASH_O_BOUNDARY 0x0000101C - -// Internal -#define FLASH_O_EFUSEFLAG 0x00001020 - -// Internal -#define FLASH_O_EFUSEKEY 0x00001024 - -// Internal -#define FLASH_O_EFUSERELEASE 0x00001028 - -// Internal -#define FLASH_O_EFUSEPINS 0x0000102C - -// Internal -#define FLASH_O_EFUSECRA 0x00001030 - -// Internal -#define FLASH_O_EFUSEREAD 0x00001034 - -// Internal -#define FLASH_O_EFUSEPROGRAM 0x00001038 - -// Internal -#define FLASH_O_EFUSEERROR 0x0000103C - -// Internal -#define FLASH_O_SINGLEBIT 0x00001040 - -// Internal -#define FLASH_O_TWOBIT 0x00001044 - -// Internal -#define FLASH_O_SELFTESTCYC 0x00001048 - -// Internal -#define FLASH_O_SELFTESTSIGN 0x0000104C - -// Internal -#define FLASH_O_FRDCTL 0x00002000 - -// Internal -#define FLASH_O_FSPRD 0x00002004 - -// Internal -#define FLASH_O_FEDACCTL1 0x00002008 - -// Internal -#define FLASH_O_FEDACSTAT 0x0000201C - -// Internal -#define FLASH_O_FBPROT 0x00002030 - -// Internal -#define FLASH_O_FBSE 0x00002034 - -// Internal -#define FLASH_O_FBBUSY 0x00002038 - -// Internal -#define FLASH_O_FBAC 0x0000203C - -// Internal -#define FLASH_O_FBFALLBACK 0x00002040 - -// Internal -#define FLASH_O_FBPRDY 0x00002044 - -// Internal -#define FLASH_O_FPAC1 0x00002048 - -// Internal -#define FLASH_O_FPAC2 0x0000204C - -// Internal -#define FLASH_O_FMAC 0x00002050 - -// Internal -#define FLASH_O_FMSTAT 0x00002054 - -// Internal -#define FLASH_O_FLOCK 0x00002064 - -// Internal -#define FLASH_O_FVREADCT 0x00002080 - -// Internal -#define FLASH_O_FVHVCT1 0x00002084 - -// Internal -#define FLASH_O_FVHVCT2 0x00002088 - -// Internal -#define FLASH_O_FVHVCT3 0x0000208C - -// Internal -#define FLASH_O_FVNVCT 0x00002090 - -// Internal -#define FLASH_O_FVSLP 0x00002094 - -// Internal -#define FLASH_O_FVWLCT 0x00002098 - -// Internal -#define FLASH_O_FEFUSECTL 0x0000209C - -// Internal -#define FLASH_O_FEFUSESTAT 0x000020A0 - -// Internal -#define FLASH_O_FEFUSEDATA 0x000020A4 - -// Internal -#define FLASH_O_FSEQPMP 0x000020A8 - -// Internal -#define FLASH_O_FBSTROBES 0x00002100 - -// Internal -#define FLASH_O_FPSTROBES 0x00002104 - -// Internal -#define FLASH_O_FBMODE 0x00002108 - -// Internal -#define FLASH_O_FTCR 0x0000210C - -// Internal -#define FLASH_O_FADDR 0x00002110 - -// Internal -#define FLASH_O_FTCTL 0x0000211C - -// Internal -#define FLASH_O_FWPWRITE0 0x00002120 - -// Internal -#define FLASH_O_FWPWRITE1 0x00002124 - -// Internal -#define FLASH_O_FWPWRITE2 0x00002128 - -// Internal -#define FLASH_O_FWPWRITE3 0x0000212C - -// Internal -#define FLASH_O_FWPWRITE4 0x00002130 - -// Internal -#define FLASH_O_FWPWRITE5 0x00002134 - -// Internal -#define FLASH_O_FWPWRITE6 0x00002138 - -// Internal -#define FLASH_O_FWPWRITE7 0x0000213C - -// Internal -#define FLASH_O_FWPWRITE_ECC 0x00002140 - -// Internal -#define FLASH_O_FSWSTAT 0x00002144 - -// Internal -#define FLASH_O_FSM_GLBCTL 0x00002200 - -// Internal -#define FLASH_O_FSM_STATE 0x00002204 - -// Internal -#define FLASH_O_FSM_STAT 0x00002208 - -// Internal -#define FLASH_O_FSM_CMD 0x0000220C - -// Internal -#define FLASH_O_FSM_PE_OSU 0x00002210 - -// Internal -#define FLASH_O_FSM_VSTAT 0x00002214 - -// Internal -#define FLASH_O_FSM_PE_VSU 0x00002218 - -// Internal -#define FLASH_O_FSM_CMP_VSU 0x0000221C - -// Internal -#define FLASH_O_FSM_EX_VAL 0x00002220 - -// Internal -#define FLASH_O_FSM_RD_H 0x00002224 - -// Internal -#define FLASH_O_FSM_P_OH 0x00002228 - -// Internal -#define FLASH_O_FSM_ERA_OH 0x0000222C - -// Internal -#define FLASH_O_FSM_SAV_PPUL 0x00002230 - -// Internal -#define FLASH_O_FSM_PE_VH 0x00002234 - -// Internal -#define FLASH_O_FSM_PRG_PW 0x00002240 - -// Internal -#define FLASH_O_FSM_ERA_PW 0x00002244 - -// Internal -#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 - -// Internal -#define FLASH_O_FSM_TIMER 0x00002258 - -// Internal -#define FLASH_O_FSM_MODE 0x0000225C - -// Internal -#define FLASH_O_FSM_PGM 0x00002260 - -// Internal -#define FLASH_O_FSM_ERA 0x00002264 - -// Internal -#define FLASH_O_FSM_PRG_PUL 0x00002268 - -// Internal -#define FLASH_O_FSM_ERA_PUL 0x0000226C - -// Internal -#define FLASH_O_FSM_STEP_SIZE 0x00002270 - -// Internal -#define FLASH_O_FSM_PUL_CNTR 0x00002274 - -// Internal -#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 - -// Internal -#define FLASH_O_FSM_ST_MACHINE 0x0000227C - -// Internal -#define FLASH_O_FSM_FLES 0x00002280 - -// Internal -#define FLASH_O_FSM_WR_ENA 0x00002288 - -// Internal -#define FLASH_O_FSM_ACC_PP 0x0000228C - -// Internal -#define FLASH_O_FSM_ACC_EP 0x00002290 - -// Internal -#define FLASH_O_FSM_ADDR 0x000022A0 - -// Internal -#define FLASH_O_FSM_SECTOR 0x000022A4 - -// Internal -#define FLASH_O_FMC_REV_ID 0x000022A8 - -// Internal -#define FLASH_O_FSM_ERR_ADDR 0x000022AC - -// Internal -#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 - -// Internal -#define FLASH_O_FSM_EXECUTE 0x000022B4 - -// Internal -#define FLASH_O_FSM_SECTOR1 0x000022C0 - -// Internal -#define FLASH_O_FSM_SECTOR2 0x000022C4 - -// Internal -#define FLASH_O_FSM_BSLE0 0x000022E0 - -// Internal -#define FLASH_O_FSM_BSLE1 0x000022E4 - -// Internal -#define FLASH_O_FSM_BSLP0 0x000022F0 - -// Internal -#define FLASH_O_FSM_BSLP1 0x000022F4 - -// Internal -#define FLASH_O_FCFG_BANK 0x00002400 - -// Internal -#define FLASH_O_FCFG_WRAPPER 0x00002404 - -// Internal -#define FLASH_O_FCFG_BNK_TYPE 0x00002408 - -// Internal -#define FLASH_O_FCFG_B0_START 0x00002410 - -// Internal -#define FLASH_O_FCFG_B1_START 0x00002414 - -// Internal -#define FLASH_O_FCFG_B2_START 0x00002418 - -// Internal -#define FLASH_O_FCFG_B3_START 0x0000241C - -// Internal -#define FLASH_O_FCFG_B4_START 0x00002420 - -// Internal -#define FLASH_O_FCFG_B5_START 0x00002424 - -// Internal -#define FLASH_O_FCFG_B6_START 0x00002428 - -// Internal -#define FLASH_O_FCFG_B7_START 0x0000242C - -// Internal -#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 - -//***************************************************************************** -// -// Register: FLASH_O_STAT -// -//***************************************************************************** -// Field: [15] EFUSE_BLANK -// -// Efuse scanning detected if fuse ROM is blank: -// 0 : Not blank -// 1 : Blank -#define FLASH_STAT_EFUSE_BLANK 0x00008000 -#define FLASH_STAT_EFUSE_BLANK_BITN 15 -#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 -#define FLASH_STAT_EFUSE_BLANK_S 15 - -// Field: [14] EFUSE_TIMEOUT -// -// Efuse scanning resulted in timeout error. -// 0 : No Timeout error -// 1 : Timeout Error -#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 -#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 -#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 -#define FLASH_STAT_EFUSE_TIMEOUT_S 14 - -// Field: [13] EFUSE_CRC_ERROR -// -// Efuse scanning resulted in scan chain CRC error. -// 0 : No CRC error -// 1 : CRC Error -#define FLASH_STAT_EFUSE_CRC_ERROR 0x00002000 -#define FLASH_STAT_EFUSE_CRC_ERROR_BITN 13 -#define FLASH_STAT_EFUSE_CRC_ERROR_M 0x00002000 -#define FLASH_STAT_EFUSE_CRC_ERROR_S 13 - -// Field: [12:8] EFUSE_ERRCODE -// -// Same as EFUSEERROR.CODE -#define FLASH_STAT_EFUSE_ERRCODE_W 5 -#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 -#define FLASH_STAT_EFUSE_ERRCODE_S 8 - -// Field: [2] SAMHOLD_DIS -// -// Status indicator of flash sample and hold sequencing logic. This bit will go -// to 1 some delay after CFG.DIS_IDLE is set to 1. -// 0: Not disabled -// 1: Sample and hold disabled and stable -#define FLASH_STAT_SAMHOLD_DIS 0x00000004 -#define FLASH_STAT_SAMHOLD_DIS_BITN 2 -#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 -#define FLASH_STAT_SAMHOLD_DIS_S 2 - -// Field: [1] BUSY -// -// Fast version of the FMC FMSTAT.BUSY bit. -// This flag is valid immediately after the operation setting it (FMSTAT.BUSY -// is delayed some cycles) -// 0 : Not busy -// 1 : Busy -#define FLASH_STAT_BUSY 0x00000002 -#define FLASH_STAT_BUSY_BITN 1 -#define FLASH_STAT_BUSY_M 0x00000002 -#define FLASH_STAT_BUSY_S 1 - -// Field: [0] POWER_MODE -// -// Power state of the flash sub-system. -// 0 : Active -// 1 : Low power -#define FLASH_STAT_POWER_MODE 0x00000001 -#define FLASH_STAT_POWER_MODE_BITN 0 -#define FLASH_STAT_POWER_MODE_M 0x00000001 -#define FLASH_STAT_POWER_MODE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_CFG -// -//***************************************************************************** -// Field: [8] STANDBY_MODE_SEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 -#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 -#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 -#define FLASH_CFG_STANDBY_MODE_SEL_S 8 - -// Field: [7:6] STANDBY_PW_SEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_STANDBY_PW_SEL_W 2 -#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 -#define FLASH_CFG_STANDBY_PW_SEL_S 6 - -// Field: [5] DIS_EFUSECLK -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_EFUSECLK 0x00000020 -#define FLASH_CFG_DIS_EFUSECLK_BITN 5 -#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 -#define FLASH_CFG_DIS_EFUSECLK_S 5 - -// Field: [4] DIS_READACCESS -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_READACCESS 0x00000010 -#define FLASH_CFG_DIS_READACCESS_BITN 4 -#define FLASH_CFG_DIS_READACCESS_M 0x00000010 -#define FLASH_CFG_DIS_READACCESS_S 4 - -// Field: [3] ENABLE_SWINTF -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_ENABLE_SWINTF 0x00000008 -#define FLASH_CFG_ENABLE_SWINTF_BITN 3 -#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 -#define FLASH_CFG_ENABLE_SWINTF_S 3 - -// Field: [1] DIS_STANDBY -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_STANDBY 0x00000002 -#define FLASH_CFG_DIS_STANDBY_BITN 1 -#define FLASH_CFG_DIS_STANDBY_M 0x00000002 -#define FLASH_CFG_DIS_STANDBY_S 1 - -// Field: [0] DIS_IDLE -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_IDLE 0x00000001 -#define FLASH_CFG_DIS_IDLE_BITN 0 -#define FLASH_CFG_DIS_IDLE_M 0x00000001 -#define FLASH_CFG_DIS_IDLE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_SYSCODE_START -// -//***************************************************************************** -// Field: [4:0] SYSCODE_START -// -// Internal. Only to be used through TI provided API. -#define FLASH_SYSCODE_START_SYSCODE_START_W 5 -#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000001F -#define FLASH_SYSCODE_START_SYSCODE_START_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FLASH_SIZE -// -//***************************************************************************** -// Field: [7:0] SECTORS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FLASH_SIZE_SECTORS_W 8 -#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF -#define FLASH_FLASH_SIZE_SECTORS_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWLOCK -// -//***************************************************************************** -// Field: [2:0] FWLOCK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWLOCK_FWLOCK_W 3 -#define FLASH_FWLOCK_FWLOCK_M 0x00000007 -#define FLASH_FWLOCK_FWLOCK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWFLAG -// -//***************************************************************************** -// Field: [2:0] FWFLAG -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWFLAG_FWFLAG_W 3 -#define FLASH_FWFLAG_FWFLAG_M 0x00000007 -#define FLASH_FWFLAG_FWFLAG_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSE -// -//***************************************************************************** -// Field: [28:24] INSTRUCTION -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSE_INSTRUCTION_W 5 -#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 -#define FLASH_EFUSE_INSTRUCTION_S 24 - -// Field: [15:0] DUMPWORD -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSE_DUMPWORD_W 16 -#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF -#define FLASH_EFUSE_DUMPWORD_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEADDR -// -//***************************************************************************** -// Field: [15:11] BLOCK -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEADDR_BLOCK_W 5 -#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 -#define FLASH_EFUSEADDR_BLOCK_S 11 - -// Field: [10:0] ROW -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEADDR_ROW_W 11 -#define FLASH_EFUSEADDR_ROW_M 0x000007FF -#define FLASH_EFUSEADDR_ROW_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_DATAUPPER -// -//***************************************************************************** -// Field: [7:3] SPARE -// -// Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_SPARE_W 5 -#define FLASH_DATAUPPER_SPARE_M 0x000000F8 -#define FLASH_DATAUPPER_SPARE_S 3 - -// Field: [2] P -// -// Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_P 0x00000004 -#define FLASH_DATAUPPER_P_BITN 2 -#define FLASH_DATAUPPER_P_M 0x00000004 -#define FLASH_DATAUPPER_P_S 2 - -// Field: [1] R -// -// Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_R 0x00000002 -#define FLASH_DATAUPPER_R_BITN 1 -#define FLASH_DATAUPPER_R_M 0x00000002 -#define FLASH_DATAUPPER_R_S 1 - -// Field: [0] EEN -// -// Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_EEN 0x00000001 -#define FLASH_DATAUPPER_EEN_BITN 0 -#define FLASH_DATAUPPER_EEN_M 0x00000001 -#define FLASH_DATAUPPER_EEN_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_DATALOWER -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Internal. Only to be used through TI provided API. -#define FLASH_DATALOWER_DATA_W 32 -#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF -#define FLASH_DATALOWER_DATA_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSECFG -// -//***************************************************************************** -// Field: [8] IDLEGATING -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_IDLEGATING 0x00000100 -#define FLASH_EFUSECFG_IDLEGATING_BITN 8 -#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 -#define FLASH_EFUSECFG_IDLEGATING_S 8 - -// Field: [4:3] SLAVEPOWER -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_SLAVEPOWER_W 2 -#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 -#define FLASH_EFUSECFG_SLAVEPOWER_S 3 - -// Field: [0] GATING -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_GATING 0x00000001 -#define FLASH_EFUSECFG_GATING_BITN 0 -#define FLASH_EFUSECFG_GATING_M 0x00000001 -#define FLASH_EFUSECFG_GATING_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSESTAT -// -//***************************************************************************** -// Field: [0] RESETDONE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSESTAT_RESETDONE 0x00000001 -#define FLASH_EFUSESTAT_RESETDONE_BITN 0 -#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 -#define FLASH_EFUSESTAT_RESETDONE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_ACC -// -//***************************************************************************** -// Field: [23:0] ACCUMULATOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_ACC_ACCUMULATOR_W 24 -#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF -#define FLASH_ACC_ACCUMULATOR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_BOUNDARY -// -//***************************************************************************** -// Field: [23] DISROW0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_DISROW0 0x00800000 -#define FLASH_BOUNDARY_DISROW0_BITN 23 -#define FLASH_BOUNDARY_DISROW0_M 0x00800000 -#define FLASH_BOUNDARY_DISROW0_S 23 - -// Field: [22] SPARE -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SPARE 0x00400000 -#define FLASH_BOUNDARY_SPARE_BITN 22 -#define FLASH_BOUNDARY_SPARE_M 0x00400000 -#define FLASH_BOUNDARY_SPARE_S 22 - -// Field: [21] EFC_SELF_TEST_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 - -// Field: [20] EFC_INSTRUCTION_INFO -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 - -// Field: [19] EFC_INSTRUCTION_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 - -// Field: [18] EFC_AUTOLOAD_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 - -// Field: [17:14] OUTPUTENABLE -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 -#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 -#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 - -// Field: [13] SYS_ECC_SELF_TEST_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 - -// Field: [12] SYS_ECC_OVERRIDE_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 - -// Field: [11] EFC_FDI -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_FDI 0x00000800 -#define FLASH_BOUNDARY_EFC_FDI_BITN 11 -#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 -#define FLASH_BOUNDARY_EFC_FDI_S 11 - -// Field: [10] SYS_DIEID_AUTOLOAD_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 - -// Field: [9:8] SYS_REPAIR_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 -#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 -#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 - -// Field: [7:4] SYS_WS_READ_STATES -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 - -// Field: [3:0] INPUTENABLE -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_INPUTENABLE_W 4 -#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F -#define FLASH_BOUNDARY_INPUTENABLE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEFLAG -// -//***************************************************************************** -// Field: [0] KEY -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEFLAG_KEY 0x00000001 -#define FLASH_EFUSEFLAG_KEY_BITN 0 -#define FLASH_EFUSEFLAG_KEY_M 0x00000001 -#define FLASH_EFUSEFLAG_KEY_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEKEY -// -//***************************************************************************** -// Field: [31:0] CODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEKEY_CODE_W 32 -#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF -#define FLASH_EFUSEKEY_CODE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSERELEASE -// -//***************************************************************************** -// Field: [31:25] ODPYEAR -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPYEAR_W 7 -#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 -#define FLASH_EFUSERELEASE_ODPYEAR_S 25 - -// Field: [24:21] ODPMONTH -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPMONTH_W 4 -#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 -#define FLASH_EFUSERELEASE_ODPMONTH_S 21 - -// Field: [20:16] ODPDAY -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPDAY_W 5 -#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 -#define FLASH_EFUSERELEASE_ODPDAY_S 16 - -// Field: [15:9] EFUSEYEAR -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 -#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 -#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 - -// Field: [8:5] EFUSEMONTH -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 -#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 -#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 - -// Field: [4:0] EFUSEDAY -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 -#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F -#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEPINS -// -//***************************************************************************** -// Field: [15] EFC_SELF_TEST_DONE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 - -// Field: [14] EFC_SELF_TEST_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 - -// Field: [13] SYS_ECC_SELF_TEST_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 - -// Field: [12] EFC_INSTRUCTION_INFO -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 - -// Field: [11] EFC_INSTRUCTION_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 - -// Field: [10] EFC_AUTOLOAD_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 - -// Field: [9] SYS_ECC_OVERRIDE_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 - -// Field: [8] EFC_READY -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_READY 0x00000100 -#define FLASH_EFUSEPINS_EFC_READY_BITN 8 -#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 -#define FLASH_EFUSEPINS_EFC_READY_S 8 - -// Field: [7] EFC_FCLRZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 -#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 -#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 -#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 - -// Field: [6] SYS_DIEID_AUTOLOAD_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 - -// Field: [5:4] SYS_REPAIR_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 - -// Field: [3:0] SYS_WS_READ_STATES -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSECRA -// -//***************************************************************************** -// Field: [5:0] DATA -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSECRA_DATA_W 6 -#define FLASH_EFUSECRA_DATA_M 0x0000003F -#define FLASH_EFUSECRA_DATA_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEREAD -// -//***************************************************************************** -// Field: [9:8] DATABIT -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_DATABIT_W 2 -#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 -#define FLASH_EFUSEREAD_DATABIT_S 8 - -// Field: [7:4] READCLOCK -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_READCLOCK_W 4 -#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 -#define FLASH_EFUSEREAD_READCLOCK_S 4 - -// Field: [3] DEBUG -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_DEBUG 0x00000008 -#define FLASH_EFUSEREAD_DEBUG_BITN 3 -#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 -#define FLASH_EFUSEREAD_DEBUG_S 3 - -// Field: [2] SPARE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_SPARE 0x00000004 -#define FLASH_EFUSEREAD_SPARE_BITN 2 -#define FLASH_EFUSEREAD_SPARE_M 0x00000004 -#define FLASH_EFUSEREAD_SPARE_S 2 - -// Field: [1:0] MARGIN -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_MARGIN_W 2 -#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 -#define FLASH_EFUSEREAD_MARGIN_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEPROGRAM -// -//***************************************************************************** -// Field: [30] COMPAREDISABLE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 - -// Field: [29:14] CLOCKSTALL -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 - -// Field: [13] VPPTOVDD -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 - -// Field: [12:9] ITERATIONS -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 -#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 -#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 - -// Field: [8:0] WRITECLOCK -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 -#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF -#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEERROR -// -//***************************************************************************** -// Field: [5] DONE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEERROR_DONE 0x00000020 -#define FLASH_EFUSEERROR_DONE_BITN 5 -#define FLASH_EFUSEERROR_DONE_M 0x00000020 -#define FLASH_EFUSEERROR_DONE_S 5 - -// Field: [4:0] CODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEERROR_CODE_W 5 -#define FLASH_EFUSEERROR_CODE_M 0x0000001F -#define FLASH_EFUSEERROR_CODE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_SINGLEBIT -// -//***************************************************************************** -// Field: [31:1] FROMN -// -// Internal. Only to be used through TI provided API. -#define FLASH_SINGLEBIT_FROMN_W 31 -#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE -#define FLASH_SINGLEBIT_FROMN_S 1 - -// Field: [0] FROM0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_SINGLEBIT_FROM0 0x00000001 -#define FLASH_SINGLEBIT_FROM0_BITN 0 -#define FLASH_SINGLEBIT_FROM0_M 0x00000001 -#define FLASH_SINGLEBIT_FROM0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_TWOBIT -// -//***************************************************************************** -// Field: [31:1] FROMN -// -// Internal. Only to be used through TI provided API. -#define FLASH_TWOBIT_FROMN_W 31 -#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE -#define FLASH_TWOBIT_FROMN_S 1 - -// Field: [0] FROM0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_TWOBIT_FROM0 0x00000001 -#define FLASH_TWOBIT_FROM0_BITN 0 -#define FLASH_TWOBIT_FROM0_M 0x00000001 -#define FLASH_TWOBIT_FROM0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_SELFTESTCYC -// -//***************************************************************************** -// Field: [31:0] CYCLES -// -// Internal. Only to be used through TI provided API. -#define FLASH_SELFTESTCYC_CYCLES_W 32 -#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF -#define FLASH_SELFTESTCYC_CYCLES_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_SELFTESTSIGN -// -//***************************************************************************** -// Field: [31:0] SIGNATURE -// -// Internal. Only to be used through TI provided API. -#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 -#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF -#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FRDCTL -// -//***************************************************************************** -// Field: [11:8] RWAIT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FRDCTL_RWAIT_W 4 -#define FLASH_FRDCTL_RWAIT_M 0x00000F00 -#define FLASH_FRDCTL_RWAIT_S 8 - -//***************************************************************************** -// -// Register: FLASH_O_FSPRD -// -//***************************************************************************** -// Field: [15:8] RMBSEM -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RMBSEM_W 8 -#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 -#define FLASH_FSPRD_RMBSEM_S 8 - -// Field: [1] RM1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RM1 0x00000002 -#define FLASH_FSPRD_RM1_BITN 1 -#define FLASH_FSPRD_RM1_M 0x00000002 -#define FLASH_FSPRD_RM1_S 1 - -// Field: [0] RM0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RM0 0x00000001 -#define FLASH_FSPRD_RM0_BITN 0 -#define FLASH_FSPRD_RM0_M 0x00000001 -#define FLASH_FSPRD_RM0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FEDACCTL1 -// -//***************************************************************************** -// Field: [24] SUSP_IGNR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 -#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 -#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 -#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 - -//***************************************************************************** -// -// Register: FLASH_O_FEDACSTAT -// -//***************************************************************************** -// Field: [25] RVF_INT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEDACSTAT_RVF_INT 0x02000000 -#define FLASH_FEDACSTAT_RVF_INT_BITN 25 -#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 -#define FLASH_FEDACSTAT_RVF_INT_S 25 - -// Field: [24] FSM_DONE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 -#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 -#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 -#define FLASH_FEDACSTAT_FSM_DONE_S 24 - -//***************************************************************************** -// -// Register: FLASH_O_FBPROT -// -//***************************************************************************** -// Field: [0] PROTL1DIS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBPROT_PROTL1DIS 0x00000001 -#define FLASH_FBPROT_PROTL1DIS_BITN 0 -#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 -#define FLASH_FBPROT_PROTL1DIS_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBSE -// -//***************************************************************************** -// Field: [15:0] BSE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSE_BSE_W 16 -#define FLASH_FBSE_BSE_M 0x0000FFFF -#define FLASH_FBSE_BSE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBBUSY -// -//***************************************************************************** -// Field: [7:0] BUSY -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBBUSY_BUSY_W 8 -#define FLASH_FBBUSY_BUSY_M 0x000000FF -#define FLASH_FBBUSY_BUSY_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBAC -// -//***************************************************************************** -// Field: [16] OTPPROTDIS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBAC_OTPPROTDIS 0x00010000 -#define FLASH_FBAC_OTPPROTDIS_BITN 16 -#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 -#define FLASH_FBAC_OTPPROTDIS_S 16 - -// Field: [15:8] BAGP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBAC_BAGP_W 8 -#define FLASH_FBAC_BAGP_M 0x0000FF00 -#define FLASH_FBAC_BAGP_S 8 - -// Field: [7:0] VREADS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBAC_VREADS_W 8 -#define FLASH_FBAC_VREADS_M 0x000000FF -#define FLASH_FBAC_VREADS_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBFALLBACK -// -//***************************************************************************** -// Field: [27:24] FSM_PWRSAV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 -#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 -#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 - -// Field: [19:16] REG_PWRSAV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 -#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 -#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 - -// Field: [15:14] BANKPWR7 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR7_W 2 -#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 -#define FLASH_FBFALLBACK_BANKPWR7_S 14 - -// Field: [13:12] BANKPWR6 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR6_W 2 -#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 -#define FLASH_FBFALLBACK_BANKPWR6_S 12 - -// Field: [11:10] BANKPWR5 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR5_W 2 -#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 -#define FLASH_FBFALLBACK_BANKPWR5_S 10 - -// Field: [9:8] BANKPWR4 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR4_W 2 -#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 -#define FLASH_FBFALLBACK_BANKPWR4_S 8 - -// Field: [7:6] BANKPWR3 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR3_W 2 -#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 -#define FLASH_FBFALLBACK_BANKPWR3_S 6 - -// Field: [5:4] BANKPWR2 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR2_W 2 -#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 -#define FLASH_FBFALLBACK_BANKPWR2_S 4 - -// Field: [3:2] BANKPWR1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR1_W 2 -#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C -#define FLASH_FBFALLBACK_BANKPWR1_S 2 - -// Field: [1:0] BANKPWR0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR0_W 2 -#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 -#define FLASH_FBFALLBACK_BANKPWR0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBPRDY -// -//***************************************************************************** -// Field: [16] BANKBUSY -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_BANKBUSY 0x00010000 -#define FLASH_FBPRDY_BANKBUSY_BITN 16 -#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 -#define FLASH_FBPRDY_BANKBUSY_S 16 - -// Field: [15] PUMPRDY -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_PUMPRDY 0x00008000 -#define FLASH_FBPRDY_PUMPRDY_BITN 15 -#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 -#define FLASH_FBPRDY_PUMPRDY_S 15 - -// Field: [0] BANKRDY -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_BANKRDY 0x00000001 -#define FLASH_FBPRDY_BANKRDY_BITN 0 -#define FLASH_FBPRDY_BANKRDY_M 0x00000001 -#define FLASH_FBPRDY_BANKRDY_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FPAC1 -// -//***************************************************************************** -// Field: [27:16] PSLEEPTDIS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PSLEEPTDIS_W 12 -#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 -#define FLASH_FPAC1_PSLEEPTDIS_S 16 - -// Field: [15:4] PUMPRESET_PW -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PUMPRESET_PW_W 12 -#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 -#define FLASH_FPAC1_PUMPRESET_PW_S 4 - -// Field: [1:0] PUMPPWR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PUMPPWR_W 2 -#define FLASH_FPAC1_PUMPPWR_M 0x00000003 -#define FLASH_FPAC1_PUMPPWR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FPAC2 -// -//***************************************************************************** -// Field: [15:0] PAGP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPAC2_PAGP_W 16 -#define FLASH_FPAC2_PAGP_M 0x0000FFFF -#define FLASH_FPAC2_PAGP_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FMAC -// -//***************************************************************************** -// Field: [2:0] BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMAC_BANK_W 3 -#define FLASH_FMAC_BANK_M 0x00000007 -#define FLASH_FMAC_BANK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FMSTAT -// -//***************************************************************************** -// Field: [17] RVSUSP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RVSUSP 0x00020000 -#define FLASH_FMSTAT_RVSUSP_BITN 17 -#define FLASH_FMSTAT_RVSUSP_M 0x00020000 -#define FLASH_FMSTAT_RVSUSP_S 17 - -// Field: [16] RDVER -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RDVER 0x00010000 -#define FLASH_FMSTAT_RDVER_BITN 16 -#define FLASH_FMSTAT_RDVER_M 0x00010000 -#define FLASH_FMSTAT_RDVER_S 16 - -// Field: [15] RVF -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RVF 0x00008000 -#define FLASH_FMSTAT_RVF_BITN 15 -#define FLASH_FMSTAT_RVF_M 0x00008000 -#define FLASH_FMSTAT_RVF_S 15 - -// Field: [14] ILA -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ILA 0x00004000 -#define FLASH_FMSTAT_ILA_BITN 14 -#define FLASH_FMSTAT_ILA_M 0x00004000 -#define FLASH_FMSTAT_ILA_S 14 - -// Field: [13] DBF -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_DBF 0x00002000 -#define FLASH_FMSTAT_DBF_BITN 13 -#define FLASH_FMSTAT_DBF_M 0x00002000 -#define FLASH_FMSTAT_DBF_S 13 - -// Field: [12] PGV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PGV 0x00001000 -#define FLASH_FMSTAT_PGV_BITN 12 -#define FLASH_FMSTAT_PGV_M 0x00001000 -#define FLASH_FMSTAT_PGV_S 12 - -// Field: [11] PCV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PCV 0x00000800 -#define FLASH_FMSTAT_PCV_BITN 11 -#define FLASH_FMSTAT_PCV_M 0x00000800 -#define FLASH_FMSTAT_PCV_S 11 - -// Field: [10] EV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_EV 0x00000400 -#define FLASH_FMSTAT_EV_BITN 10 -#define FLASH_FMSTAT_EV_M 0x00000400 -#define FLASH_FMSTAT_EV_S 10 - -// Field: [9] CV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_CV 0x00000200 -#define FLASH_FMSTAT_CV_BITN 9 -#define FLASH_FMSTAT_CV_M 0x00000200 -#define FLASH_FMSTAT_CV_S 9 - -// Field: [8] BUSY -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_BUSY 0x00000100 -#define FLASH_FMSTAT_BUSY_BITN 8 -#define FLASH_FMSTAT_BUSY_M 0x00000100 -#define FLASH_FMSTAT_BUSY_S 8 - -// Field: [7] ERS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ERS 0x00000080 -#define FLASH_FMSTAT_ERS_BITN 7 -#define FLASH_FMSTAT_ERS_M 0x00000080 -#define FLASH_FMSTAT_ERS_S 7 - -// Field: [6] PGM -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PGM 0x00000040 -#define FLASH_FMSTAT_PGM_BITN 6 -#define FLASH_FMSTAT_PGM_M 0x00000040 -#define FLASH_FMSTAT_PGM_S 6 - -// Field: [5] INVDAT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_INVDAT 0x00000020 -#define FLASH_FMSTAT_INVDAT_BITN 5 -#define FLASH_FMSTAT_INVDAT_M 0x00000020 -#define FLASH_FMSTAT_INVDAT_S 5 - -// Field: [4] CSTAT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_CSTAT 0x00000010 -#define FLASH_FMSTAT_CSTAT_BITN 4 -#define FLASH_FMSTAT_CSTAT_M 0x00000010 -#define FLASH_FMSTAT_CSTAT_S 4 - -// Field: [3] VOLSTAT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_VOLSTAT 0x00000008 -#define FLASH_FMSTAT_VOLSTAT_BITN 3 -#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 -#define FLASH_FMSTAT_VOLSTAT_S 3 - -// Field: [2] ESUSP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ESUSP 0x00000004 -#define FLASH_FMSTAT_ESUSP_BITN 2 -#define FLASH_FMSTAT_ESUSP_M 0x00000004 -#define FLASH_FMSTAT_ESUSP_S 2 - -// Field: [1] PSUSP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PSUSP 0x00000002 -#define FLASH_FMSTAT_PSUSP_BITN 1 -#define FLASH_FMSTAT_PSUSP_M 0x00000002 -#define FLASH_FMSTAT_PSUSP_S 1 - -// Field: [0] SLOCK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_SLOCK 0x00000001 -#define FLASH_FMSTAT_SLOCK_BITN 0 -#define FLASH_FMSTAT_SLOCK_M 0x00000001 -#define FLASH_FMSTAT_SLOCK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FLOCK -// -//***************************************************************************** -// Field: [15:0] ENCOM -// -// Internal. Only to be used through TI provided API. -#define FLASH_FLOCK_ENCOM_W 16 -#define FLASH_FLOCK_ENCOM_M 0x0000FFFF -#define FLASH_FLOCK_ENCOM_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FVREADCT -// -//***************************************************************************** -// Field: [3:0] VREADCT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVREADCT_VREADCT_W 4 -#define FLASH_FVREADCT_VREADCT_M 0x0000000F -#define FLASH_FVREADCT_VREADCT_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FVHVCT1 -// -//***************************************************************************** -// Field: [23:20] TRIM13_E -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_TRIM13_E_W 4 -#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 -#define FLASH_FVHVCT1_TRIM13_E_S 20 - -// Field: [19:16] VHVCT_E -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_VHVCT_E_W 4 -#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 -#define FLASH_FVHVCT1_VHVCT_E_S 16 - -// Field: [7:4] TRIM13_PV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_TRIM13_PV_W 4 -#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 -#define FLASH_FVHVCT1_TRIM13_PV_S 4 - -// Field: [3:0] VHVCT_PV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_VHVCT_PV_W 4 -#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F -#define FLASH_FVHVCT1_VHVCT_PV_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FVHVCT2 -// -//***************************************************************************** -// Field: [23:20] TRIM13_P -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT2_TRIM13_P_W 4 -#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 -#define FLASH_FVHVCT2_TRIM13_P_S 20 - -// Field: [19:16] VHVCT_P -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT2_VHVCT_P_W 4 -#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 -#define FLASH_FVHVCT2_VHVCT_P_S 16 - -//***************************************************************************** -// -// Register: FLASH_O_FVHVCT3 -// -//***************************************************************************** -// Field: [19:16] WCT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT3_WCT_W 4 -#define FLASH_FVHVCT3_WCT_M 0x000F0000 -#define FLASH_FVHVCT3_WCT_S 16 - -// Field: [3:0] VHVCT_READ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT3_VHVCT_READ_W 4 -#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F -#define FLASH_FVHVCT3_VHVCT_READ_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FVNVCT -// -//***************************************************************************** -// Field: [12:8] VCG2P5CT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVNVCT_VCG2P5CT_W 5 -#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 -#define FLASH_FVNVCT_VCG2P5CT_S 8 - -// Field: [4:0] VIN_CT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVNVCT_VIN_CT_W 5 -#define FLASH_FVNVCT_VIN_CT_M 0x0000001F -#define FLASH_FVNVCT_VIN_CT_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FVSLP -// -//***************************************************************************** -// Field: [15:12] VSL_P -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVSLP_VSL_P_W 4 -#define FLASH_FVSLP_VSL_P_M 0x0000F000 -#define FLASH_FVSLP_VSL_P_S 12 - -//***************************************************************************** -// -// Register: FLASH_O_FVWLCT -// -//***************************************************************************** -// Field: [4:0] VWLCT_P -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVWLCT_VWLCT_P_W 5 -#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F -#define FLASH_FVWLCT_VWLCT_P_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FEFUSECTL -// -//***************************************************************************** -// Field: [26:24] CHAIN_SEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 -#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 -#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 - -// Field: [17] WRITE_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 -#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 -#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 -#define FLASH_FEFUSECTL_WRITE_EN_S 17 - -// Field: [16] BP_SEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_BP_SEL 0x00010000 -#define FLASH_FEFUSECTL_BP_SEL_BITN 16 -#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 -#define FLASH_FEFUSECTL_BP_SEL_S 16 - -// Field: [8] EF_CLRZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 -#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 -#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 -#define FLASH_FEFUSECTL_EF_CLRZ_S 8 - -// Field: [4] EF_TEST -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EF_TEST 0x00000010 -#define FLASH_FEFUSECTL_EF_TEST_BITN 4 -#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 -#define FLASH_FEFUSECTL_EF_TEST_S 4 - -// Field: [3:0] EFUSE_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EFUSE_EN_W 4 -#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F -#define FLASH_FEFUSECTL_EFUSE_EN_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FEFUSESTAT -// -//***************************************************************************** -// Field: [0] SHIFT_DONE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 -#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 -#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 -#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FEFUSEDATA -// -//***************************************************************************** -// Field: [31:0] FEFUSEDATA -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 -#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF -#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSEQPMP -// -//***************************************************************************** -// Field: [27:24] TRIM_3P4 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_3P4_W 4 -#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 -#define FLASH_FSEQPMP_TRIM_3P4_S 24 - -// Field: [21:20] TRIM_1P7 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_1P7_W 2 -#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 -#define FLASH_FSEQPMP_TRIM_1P7_S 20 - -// Field: [19:16] TRIM_0P8 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_0P8_W 4 -#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 -#define FLASH_FSEQPMP_TRIM_0P8_S 16 - -// Field: [14:12] VIN_AT_X -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_VIN_AT_X_W 3 -#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 -#define FLASH_FSEQPMP_VIN_AT_X_S 12 - -// Field: [8] VIN_BY_PASS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 -#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 -#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 -#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 - -//***************************************************************************** -// -// Register: FLASH_O_FBSTROBES -// -//***************************************************************************** -// Field: [24] ECBIT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_ECBIT 0x01000000 -#define FLASH_FBSTROBES_ECBIT_BITN 24 -#define FLASH_FBSTROBES_ECBIT_M 0x01000000 -#define FLASH_FBSTROBES_ECBIT_S 24 - -// Field: [18] RWAIT2_FLCLK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 - -// Field: [17] RWAIT_FLCLK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 -#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 -#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 -#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 - -// Field: [16] FLCLKEN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_FLCLKEN 0x00010000 -#define FLASH_FBSTROBES_FLCLKEN_BITN 16 -#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 -#define FLASH_FBSTROBES_FLCLKEN_S 16 - -// Field: [8] CTRLENZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_CTRLENZ 0x00000100 -#define FLASH_FBSTROBES_CTRLENZ_BITN 8 -#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 -#define FLASH_FBSTROBES_CTRLENZ_S 8 - -// Field: [6] NOCOLRED -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_NOCOLRED 0x00000040 -#define FLASH_FBSTROBES_NOCOLRED_BITN 6 -#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 -#define FLASH_FBSTROBES_NOCOLRED_S 6 - -// Field: [5] PRECOL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_PRECOL 0x00000020 -#define FLASH_FBSTROBES_PRECOL_BITN 5 -#define FLASH_FBSTROBES_PRECOL_M 0x00000020 -#define FLASH_FBSTROBES_PRECOL_S 5 - -// Field: [4] TI_OTP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_TI_OTP 0x00000010 -#define FLASH_FBSTROBES_TI_OTP_BITN 4 -#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 -#define FLASH_FBSTROBES_TI_OTP_S 4 - -// Field: [3] OTP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_OTP 0x00000008 -#define FLASH_FBSTROBES_OTP_BITN 3 -#define FLASH_FBSTROBES_OTP_M 0x00000008 -#define FLASH_FBSTROBES_OTP_S 3 - -// Field: [2] TEZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_TEZ 0x00000004 -#define FLASH_FBSTROBES_TEZ_BITN 2 -#define FLASH_FBSTROBES_TEZ_M 0x00000004 -#define FLASH_FBSTROBES_TEZ_S 2 - -//***************************************************************************** -// -// Register: FLASH_O_FPSTROBES -// -//***************************************************************************** -// Field: [8] EXECUTEZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 -#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 -#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 -#define FLASH_FPSTROBES_EXECUTEZ_S 8 - -// Field: [1] V3PWRDNZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 -#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 -#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 -#define FLASH_FPSTROBES_V3PWRDNZ_S 1 - -// Field: [0] V5PWRDNZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 -#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 -#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 -#define FLASH_FPSTROBES_V5PWRDNZ_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBMODE -// -//***************************************************************************** -// Field: [2:0] MODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBMODE_MODE_W 3 -#define FLASH_FBMODE_MODE_M 0x00000007 -#define FLASH_FBMODE_MODE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FTCR -// -//***************************************************************************** -// Field: [6:0] TCR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FTCR_TCR_W 7 -#define FLASH_FTCR_TCR_M 0x0000007F -#define FLASH_FTCR_TCR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FADDR -// -//***************************************************************************** -// Field: [31:0] FADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FADDR_FADDR_W 32 -#define FLASH_FADDR_FADDR_M 0xFFFFFFFF -#define FLASH_FADDR_FADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FTCTL -// -//***************************************************************************** -// Field: [16] WDATA_BLK_CLR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 -#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 -#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 -#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 - -// Field: [1] TEST_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FTCTL_TEST_EN 0x00000002 -#define FLASH_FTCTL_TEST_EN_BITN 1 -#define FLASH_FTCTL_TEST_EN_M 0x00000002 -#define FLASH_FTCTL_TEST_EN_S 1 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE0 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE0_FWPWRITE0_W 32 -#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF -#define FLASH_FWPWRITE0_FWPWRITE0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE1 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE1_FWPWRITE1_W 32 -#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF -#define FLASH_FWPWRITE1_FWPWRITE1_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE2 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE2 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE2_FWPWRITE2_W 32 -#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF -#define FLASH_FWPWRITE2_FWPWRITE2_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE3 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE3 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE3_FWPWRITE3_W 32 -#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF -#define FLASH_FWPWRITE3_FWPWRITE3_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE4 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE4 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE4_FWPWRITE4_W 32 -#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF -#define FLASH_FWPWRITE4_FWPWRITE4_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE5 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE5 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE5_FWPWRITE5_W 32 -#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF -#define FLASH_FWPWRITE5_FWPWRITE5_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE6 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE6 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE6_FWPWRITE6_W 32 -#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF -#define FLASH_FWPWRITE6_FWPWRITE6_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE7 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE7 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE7_FWPWRITE7_W 32 -#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF -#define FLASH_FWPWRITE7_FWPWRITE7_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE_ECC -// -//***************************************************************************** -// Field: [31:24] ECCBYTES07_00 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 - -// Field: [23:16] ECCBYTES15_08 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 - -// Field: [15:8] ECCBYTES23_16 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 - -// Field: [7:0] ECCBYTES31_24 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSWSTAT -// -//***************************************************************************** -// Field: [0] SAFELV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSWSTAT_SAFELV 0x00000001 -#define FLASH_FSWSTAT_SAFELV_BITN 0 -#define FLASH_FSWSTAT_SAFELV_M 0x00000001 -#define FLASH_FSWSTAT_SAFELV_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_GLBCTL -// -//***************************************************************************** -// Field: [0] CLKSEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 -#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 -#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 -#define FLASH_FSM_GLBCTL_CLKSEL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_STATE -// -//***************************************************************************** -// Field: [11] CTRLENZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_CTRLENZ 0x00000800 -#define FLASH_FSM_STATE_CTRLENZ_BITN 11 -#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 -#define FLASH_FSM_STATE_CTRLENZ_S 11 - -// Field: [10] EXECUTEZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 -#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 -#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 -#define FLASH_FSM_STATE_EXECUTEZ_S 10 - -// Field: [8] FSM_ACT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_FSM_ACT 0x00000100 -#define FLASH_FSM_STATE_FSM_ACT_BITN 8 -#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 -#define FLASH_FSM_STATE_FSM_ACT_S 8 - -// Field: [7] TIOTP_ACT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 -#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 -#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 -#define FLASH_FSM_STATE_TIOTP_ACT_S 7 - -// Field: [6] OTP_ACT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_OTP_ACT 0x00000040 -#define FLASH_FSM_STATE_OTP_ACT_BITN 6 -#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 -#define FLASH_FSM_STATE_OTP_ACT_S 6 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_STAT -// -//***************************************************************************** -// Field: [2] NON_OP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_NON_OP 0x00000004 -#define FLASH_FSM_STAT_NON_OP_BITN 2 -#define FLASH_FSM_STAT_NON_OP_M 0x00000004 -#define FLASH_FSM_STAT_NON_OP_S 2 - -// Field: [1] OVR_PUL_CNT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 -#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 -#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 -#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 - -// Field: [0] INV_DAT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_INV_DAT 0x00000001 -#define FLASH_FSM_STAT_INV_DAT_BITN 0 -#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 -#define FLASH_FSM_STAT_INV_DAT_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_CMD -// -//***************************************************************************** -// Field: [5:0] FSMCMD -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_CMD_FSMCMD_W 6 -#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F -#define FLASH_FSM_CMD_FSMCMD_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PE_OSU -// -//***************************************************************************** -// Field: [15:8] PGM_OSU -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 -#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 -#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 - -// Field: [7:0] ERA_OSU -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 -#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF -#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_VSTAT -// -//***************************************************************************** -// Field: [15:12] VSTAT_CNT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 -#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 -#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PE_VSU -// -//***************************************************************************** -// Field: [15:8] PGM_VSU -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 -#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 -#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 - -// Field: [7:0] ERA_VSU -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 -#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF -#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_CMP_VSU -// -//***************************************************************************** -// Field: [15:12] ADD_EXZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 -#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 -#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_EX_VAL -// -//***************************************************************************** -// Field: [15:8] REP_VSU -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_EX_VAL_REP_VSU_W 8 -#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 -#define FLASH_FSM_EX_VAL_REP_VSU_S 8 - -// Field: [7:0] EXE_VALD -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 -#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF -#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_RD_H -// -//***************************************************************************** -// Field: [7:0] RD_H -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_RD_H_RD_H_W 8 -#define FLASH_FSM_RD_H_RD_H_M 0x000000FF -#define FLASH_FSM_RD_H_RD_H_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_P_OH -// -//***************************************************************************** -// Field: [15:8] PGM_OH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_P_OH_PGM_OH_W 8 -#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 -#define FLASH_FSM_P_OH_PGM_OH_S 8 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ERA_OH -// -//***************************************************************************** -// Field: [15:0] ERA_OH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_OH_ERA_OH_W 16 -#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF -#define FLASH_FSM_ERA_OH_ERA_OH_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_SAV_PPUL -// -//***************************************************************************** -// Field: [11:0] SAV_P_PUL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PE_VH -// -//***************************************************************************** -// Field: [15:8] PGM_VH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VH_PGM_VH_W 8 -#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 -#define FLASH_FSM_PE_VH_PGM_VH_S 8 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PRG_PW -// -//***************************************************************************** -// Field: [15:0] PROG_PUL_WIDTH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ERA_PW -// -//***************************************************************************** -// Field: [31:0] FSM_ERA_PW -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_SAV_ERA_PUL -// -//***************************************************************************** -// Field: [11:0] SAV_ERA_PUL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_TIMER -// -//***************************************************************************** -// Field: [31:0] FSM_TIMER -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_TIMER_FSM_TIMER_W 32 -#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF -#define FLASH_FSM_TIMER_FSM_TIMER_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_MODE -// -//***************************************************************************** -// Field: [19:18] RDV_SUBMODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 -#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 -#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 - -// Field: [17:16] PGM_SUBMODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 -#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 -#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 - -// Field: [15:14] ERA_SUBMODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 -#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 -#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 - -// Field: [13:12] SUBMODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SUBMODE_W 2 -#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 -#define FLASH_FSM_MODE_SUBMODE_S 12 - -// Field: [11:9] SAV_PGM_CMD -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 -#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 -#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 - -// Field: [8:6] SAV_ERA_MODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 -#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 -#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 - -// Field: [5:3] MODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_MODE_W 3 -#define FLASH_FSM_MODE_MODE_M 0x00000038 -#define FLASH_FSM_MODE_MODE_S 3 - -// Field: [2:0] CMD -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_CMD_W 3 -#define FLASH_FSM_MODE_CMD_M 0x00000007 -#define FLASH_FSM_MODE_CMD_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PGM -// -//***************************************************************************** -// Field: [25:23] PGM_BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_PGM_BANK_W 3 -#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 -#define FLASH_FSM_PGM_PGM_BANK_S 23 - -// Field: [22:0] PGM_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_PGM_ADDR_W 23 -#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF -#define FLASH_FSM_PGM_PGM_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ERA -// -//***************************************************************************** -// Field: [25:23] ERA_BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_ERA_BANK_W 3 -#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 -#define FLASH_FSM_ERA_ERA_BANK_S 23 - -// Field: [22:0] ERA_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_ERA_ADDR_W 23 -#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF -#define FLASH_FSM_ERA_ERA_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PRG_PUL -// -//***************************************************************************** -// Field: [19:16] BEG_EC_LEVEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 - -// Field: [11:0] MAX_PRG_PUL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ERA_PUL -// -//***************************************************************************** -// Field: [19:16] MAX_EC_LEVEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 - -// Field: [11:0] MAX_ERA_PUL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_STEP_SIZE -// -//***************************************************************************** -// Field: [24:16] EC_STEP_SIZE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PUL_CNTR -// -//***************************************************************************** -// Field: [24:16] CUR_EC_LEVEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 - -// Field: [11:0] PUL_CNTR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_EC_STEP_HEIGHT -// -//***************************************************************************** -// Field: [3:0] EC_STEP_HEIGHT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ST_MACHINE -// -//***************************************************************************** -// Field: [23] DO_PRECOND -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 - -// Field: [22] FSM_INT_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 - -// Field: [21] ALL_BANKS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 - -// Field: [20] CMPV_ALLOWED -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 - -// Field: [19] RANDOM -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 -#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 -#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 -#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 - -// Field: [18] RV_SEC_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 - -// Field: [17] RV_RES -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 -#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 -#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 -#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 - -// Field: [16] RV_INT_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 - -// Field: [14] ONE_TIME_GOOD -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 - -// Field: [11] DO_REDU_COL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 - -// Field: [10:7] DBG_SHORT_ROW -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 - -// Field: [5] PGM_SEC_COF_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 - -// Field: [4] PREC_STOP_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 - -// Field: [3] DIS_TST_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 - -// Field: [2] CMD_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 -#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 -#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 -#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 - -// Field: [1] INV_DATA -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 -#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 -#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 -#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 - -// Field: [0] OVERRIDE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_FLES -// -//***************************************************************************** -// Field: [11:8] BLK_TIOTP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_FLES_BLK_TIOTP_W 4 -#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 -#define FLASH_FSM_FLES_BLK_TIOTP_S 8 - -// Field: [7:0] BLK_OTP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_FLES_BLK_OTP_W 8 -#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF -#define FLASH_FSM_FLES_BLK_OTP_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_WR_ENA -// -//***************************************************************************** -// Field: [2:0] WR_ENA -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_WR_ENA_WR_ENA_W 3 -#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 -#define FLASH_FSM_WR_ENA_WR_ENA_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ACC_PP -// -//***************************************************************************** -// Field: [31:0] FSM_ACC_PP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ACC_EP -// -//***************************************************************************** -// Field: [15:0] ACC_EP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ACC_EP_ACC_EP_W 16 -#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF -#define FLASH_FSM_ACC_EP_ACC_EP_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ADDR -// -//***************************************************************************** -// Field: [30:28] BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ADDR_BANK_W 3 -#define FLASH_FSM_ADDR_BANK_M 0x70000000 -#define FLASH_FSM_ADDR_BANK_S 28 - -// Field: [27:0] CUR_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ADDR_CUR_ADDR_W 28 -#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF -#define FLASH_FSM_ADDR_CUR_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_SECTOR -// -//***************************************************************************** -// Field: [31:16] SECT_ERASED -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 -#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 -#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 - -// Field: [15:8] FSM_SECTOR_EXTENSION -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 - -// Field: [7:4] SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SECTOR_W 4 -#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 -#define FLASH_FSM_SECTOR_SECTOR_S 4 - -// Field: [3:0] SEC_OUT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SEC_OUT_W 4 -#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F -#define FLASH_FSM_SECTOR_SEC_OUT_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FMC_REV_ID -// -//***************************************************************************** -// Field: [31:12] MOD_VERSION -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 -#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 -#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 - -// Field: [11:0] CONFIG_CRC -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 -#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF -#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ERR_ADDR -// -//***************************************************************************** -// Field: [31:8] FSM_ERR_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 - -// Field: [3:0] FSM_ERR_BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PGM_MAXPUL -// -//***************************************************************************** -// Field: [11:0] FSM_PGM_MAXPUL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_EXECUTE -// -//***************************************************************************** -// Field: [19:16] SUSPEND_NOW -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 - -// Field: [4:0] FSMEXECUTE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 -#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F -#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_SECTOR1 -// -//***************************************************************************** -// Field: [31:0] FSM_SECTOR1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_SECTOR2 -// -//***************************************************************************** -// Field: [31:0] FSM_SECTOR2 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_BSLE0 -// -//***************************************************************************** -// Field: [31:0] FSM_BSLE0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 -#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF -#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_BSLE1 -// -//***************************************************************************** -// Field: [31:0] FSM_BSL1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 -#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF -#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_BSLP0 -// -//***************************************************************************** -// Field: [31:0] FSM_BSLP0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 -#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF -#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_BSLP1 -// -//***************************************************************************** -// Field: [31:0] FSM_BSL1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 -#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF -#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_BANK -// -//***************************************************************************** -// Field: [31:20] EE_BANK_WIDTH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 - -// Field: [19:16] EE_NUM_BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 -#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 -#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 - -// Field: [15:4] MAIN_BANK_WIDTH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 - -// Field: [3:0] MAIN_NUM_BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_WRAPPER -// -//***************************************************************************** -// Field: [31:24] FAMILY_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 - -// Field: [20] MEM_MAP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 -#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 -#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 -#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 - -// Field: [19:16] CPU2 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_CPU2_W 4 -#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 -#define FLASH_FCFG_WRAPPER_CPU2_S 16 - -// Field: [15:12] EE_IN_MAIN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 - -// Field: [11] ROM -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_ROM 0x00000800 -#define FLASH_FCFG_WRAPPER_ROM_BITN 11 -#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 -#define FLASH_FCFG_WRAPPER_ROM_S 11 - -// Field: [10] IFLUSH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 -#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 -#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 -#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 - -// Field: [9] SIL3 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 -#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 -#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 -#define FLASH_FCFG_WRAPPER_SIL3_S 9 - -// Field: [8] ECCA -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 -#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 -#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 -#define FLASH_FCFG_WRAPPER_ECCA_S 8 - -// Field: [7:6] AUTO_SUSP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 - -// Field: [5:4] UERR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_UERR_W 2 -#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 -#define FLASH_FCFG_WRAPPER_UERR_S 4 - -// Field: [3:0] CPU_TYPE1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_BNK_TYPE -// -//***************************************************************************** -// Field: [31:28] B7_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 - -// Field: [27:24] B6_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 - -// Field: [23:20] B5_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 - -// Field: [19:16] B4_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 - -// Field: [15:12] B3_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 - -// Field: [11:8] B2_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 - -// Field: [7:4] B1_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 - -// Field: [3:0] B0_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B0_START -// -//***************************************************************************** -// Field: [31:28] B0_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 - -// Field: [27:24] B0_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 - -// Field: [23:0] B0_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 -#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B1_START -// -//***************************************************************************** -// Field: [31:28] B1_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 - -// Field: [27:24] B1_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 - -// Field: [23:0] B1_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 -#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B2_START -// -//***************************************************************************** -// Field: [31:28] B2_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 - -// Field: [27:24] B2_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 - -// Field: [23:0] B2_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 -#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B3_START -// -//***************************************************************************** -// Field: [31:28] B3_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 - -// Field: [27:24] B3_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 - -// Field: [23:0] B3_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 -#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B4_START -// -//***************************************************************************** -// Field: [31:28] B4_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 - -// Field: [27:24] B4_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 - -// Field: [23:0] B4_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 -#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B5_START -// -//***************************************************************************** -// Field: [31:28] B5_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 - -// Field: [27:24] B5_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 - -// Field: [23:0] B5_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 -#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B6_START -// -//***************************************************************************** -// Field: [31:28] B6_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 - -// Field: [27:24] B6_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 - -// Field: [23:0] B6_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 -#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B7_START -// -//***************************************************************************** -// Field: [31:28] B7_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 - -// Field: [27:24] B7_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 - -// Field: [23:0] B7_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 -#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B0_SSIZE0 -// -//***************************************************************************** -// Field: [27:16] B0_NUM_SECTORS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 - -// Field: [3:0] B0_SECT_SIZE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 - - -#endif // __FLASH__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_gpio.h b/third_party/ti/devices/cc26x0/inc/hw_gpio.h deleted file mode 100644 index 51f375b97..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_gpio.h +++ /dev/null @@ -1,2247 +0,0 @@ -/****************************************************************************** -* Filename: hw_gpio_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// GPIO component -// -//***************************************************************************** -// Data Out 0 to 3 -#define GPIO_O_DOUT3_0 0x00000000 - -// Data Out 4 to 7 -#define GPIO_O_DOUT7_4 0x00000004 - -// Data Out 8 to 11 -#define GPIO_O_DOUT11_8 0x00000008 - -// Data Out 12 to 15 -#define GPIO_O_DOUT15_12 0x0000000C - -// Data Out 16 to 19 -#define GPIO_O_DOUT19_16 0x00000010 - -// Data Out 20 to 23 -#define GPIO_O_DOUT23_20 0x00000014 - -// Data Out 24 to 27 -#define GPIO_O_DOUT27_24 0x00000018 - -// Data Out 28 to 31 -#define GPIO_O_DOUT31_28 0x0000001C - -// Data Output for DIO 0 to 31 -#define GPIO_O_DOUT31_0 0x00000080 - -// Data Out Set -#define GPIO_O_DOUTSET31_0 0x00000090 - -// Data Out Clear -#define GPIO_O_DOUTCLR31_0 0x000000A0 - -// Data Out Toggle -#define GPIO_O_DOUTTGL31_0 0x000000B0 - -// Data Input from DIO 0 to 31 -#define GPIO_O_DIN31_0 0x000000C0 - -// Data Output Enable for DIO 0 to 31 -#define GPIO_O_DOE31_0 0x000000D0 - -// Event Register for DIO 0 to 31 -#define GPIO_O_EVFLAGS31_0 0x000000E0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT3_0 -// -//***************************************************************************** -// Field: [24] DIO3 -// -// Sets the state of the pin that is configured as DIO#3, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO3 0x01000000 -#define GPIO_DOUT3_0_DIO3_BITN 24 -#define GPIO_DOUT3_0_DIO3_M 0x01000000 -#define GPIO_DOUT3_0_DIO3_S 24 - -// Field: [16] DIO2 -// -// Sets the state of the pin that is configured as DIO#2, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO2 0x00010000 -#define GPIO_DOUT3_0_DIO2_BITN 16 -#define GPIO_DOUT3_0_DIO2_M 0x00010000 -#define GPIO_DOUT3_0_DIO2_S 16 - -// Field: [8] DIO1 -// -// Sets the state of the pin that is configured as DIO#1, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO1 0x00000100 -#define GPIO_DOUT3_0_DIO1_BITN 8 -#define GPIO_DOUT3_0_DIO1_M 0x00000100 -#define GPIO_DOUT3_0_DIO1_S 8 - -// Field: [0] DIO0 -// -// Sets the state of the pin that is configured as DIO#0, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO0 0x00000001 -#define GPIO_DOUT3_0_DIO0_BITN 0 -#define GPIO_DOUT3_0_DIO0_M 0x00000001 -#define GPIO_DOUT3_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT7_4 -// -//***************************************************************************** -// Field: [24] DIO7 -// -// Sets the state of the pin that is configured as DIO#7, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO7 0x01000000 -#define GPIO_DOUT7_4_DIO7_BITN 24 -#define GPIO_DOUT7_4_DIO7_M 0x01000000 -#define GPIO_DOUT7_4_DIO7_S 24 - -// Field: [16] DIO6 -// -// Sets the state of the pin that is configured as DIO#6, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO6 0x00010000 -#define GPIO_DOUT7_4_DIO6_BITN 16 -#define GPIO_DOUT7_4_DIO6_M 0x00010000 -#define GPIO_DOUT7_4_DIO6_S 16 - -// Field: [8] DIO5 -// -// Sets the state of the pin that is configured as DIO#5, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO5 0x00000100 -#define GPIO_DOUT7_4_DIO5_BITN 8 -#define GPIO_DOUT7_4_DIO5_M 0x00000100 -#define GPIO_DOUT7_4_DIO5_S 8 - -// Field: [0] DIO4 -// -// Sets the state of the pin that is configured as DIO#4, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO4 0x00000001 -#define GPIO_DOUT7_4_DIO4_BITN 0 -#define GPIO_DOUT7_4_DIO4_M 0x00000001 -#define GPIO_DOUT7_4_DIO4_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT11_8 -// -//***************************************************************************** -// Field: [24] DIO11 -// -// Sets the state of the pin that is configured as DIO#11, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO11 0x01000000 -#define GPIO_DOUT11_8_DIO11_BITN 24 -#define GPIO_DOUT11_8_DIO11_M 0x01000000 -#define GPIO_DOUT11_8_DIO11_S 24 - -// Field: [16] DIO10 -// -// Sets the state of the pin that is configured as DIO#10, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO10 0x00010000 -#define GPIO_DOUT11_8_DIO10_BITN 16 -#define GPIO_DOUT11_8_DIO10_M 0x00010000 -#define GPIO_DOUT11_8_DIO10_S 16 - -// Field: [8] DIO9 -// -// Sets the state of the pin that is configured as DIO#9, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO9 0x00000100 -#define GPIO_DOUT11_8_DIO9_BITN 8 -#define GPIO_DOUT11_8_DIO9_M 0x00000100 -#define GPIO_DOUT11_8_DIO9_S 8 - -// Field: [0] DIO8 -// -// Sets the state of the pin that is configured as DIO#8, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO8 0x00000001 -#define GPIO_DOUT11_8_DIO8_BITN 0 -#define GPIO_DOUT11_8_DIO8_M 0x00000001 -#define GPIO_DOUT11_8_DIO8_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT15_12 -// -//***************************************************************************** -// Field: [24] DIO15 -// -// Sets the state of the pin that is configured as DIO#15, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO15 0x01000000 -#define GPIO_DOUT15_12_DIO15_BITN 24 -#define GPIO_DOUT15_12_DIO15_M 0x01000000 -#define GPIO_DOUT15_12_DIO15_S 24 - -// Field: [16] DIO14 -// -// Sets the state of the pin that is configured as DIO#14, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO14 0x00010000 -#define GPIO_DOUT15_12_DIO14_BITN 16 -#define GPIO_DOUT15_12_DIO14_M 0x00010000 -#define GPIO_DOUT15_12_DIO14_S 16 - -// Field: [8] DIO13 -// -// Sets the state of the pin that is configured as DIO#13, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO13 0x00000100 -#define GPIO_DOUT15_12_DIO13_BITN 8 -#define GPIO_DOUT15_12_DIO13_M 0x00000100 -#define GPIO_DOUT15_12_DIO13_S 8 - -// Field: [0] DIO12 -// -// Sets the state of the pin that is configured as DIO#12, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO12 0x00000001 -#define GPIO_DOUT15_12_DIO12_BITN 0 -#define GPIO_DOUT15_12_DIO12_M 0x00000001 -#define GPIO_DOUT15_12_DIO12_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT19_16 -// -//***************************************************************************** -// Field: [24] DIO19 -// -// Sets the state of the pin that is configured as DIO#19, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO19 0x01000000 -#define GPIO_DOUT19_16_DIO19_BITN 24 -#define GPIO_DOUT19_16_DIO19_M 0x01000000 -#define GPIO_DOUT19_16_DIO19_S 24 - -// Field: [16] DIO18 -// -// Sets the state of the pin that is configured as DIO#18, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO18 0x00010000 -#define GPIO_DOUT19_16_DIO18_BITN 16 -#define GPIO_DOUT19_16_DIO18_M 0x00010000 -#define GPIO_DOUT19_16_DIO18_S 16 - -// Field: [8] DIO17 -// -// Sets the state of the pin that is configured as DIO#17, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO17 0x00000100 -#define GPIO_DOUT19_16_DIO17_BITN 8 -#define GPIO_DOUT19_16_DIO17_M 0x00000100 -#define GPIO_DOUT19_16_DIO17_S 8 - -// Field: [0] DIO16 -// -// Sets the state of the pin that is configured as DIO#16, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO16 0x00000001 -#define GPIO_DOUT19_16_DIO16_BITN 0 -#define GPIO_DOUT19_16_DIO16_M 0x00000001 -#define GPIO_DOUT19_16_DIO16_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT23_20 -// -//***************************************************************************** -// Field: [24] DIO23 -// -// Sets the state of the pin that is configured as DIO#23, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO23 0x01000000 -#define GPIO_DOUT23_20_DIO23_BITN 24 -#define GPIO_DOUT23_20_DIO23_M 0x01000000 -#define GPIO_DOUT23_20_DIO23_S 24 - -// Field: [16] DIO22 -// -// Sets the state of the pin that is configured as DIO#22, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO22 0x00010000 -#define GPIO_DOUT23_20_DIO22_BITN 16 -#define GPIO_DOUT23_20_DIO22_M 0x00010000 -#define GPIO_DOUT23_20_DIO22_S 16 - -// Field: [8] DIO21 -// -// Sets the state of the pin that is configured as DIO#21, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO21 0x00000100 -#define GPIO_DOUT23_20_DIO21_BITN 8 -#define GPIO_DOUT23_20_DIO21_M 0x00000100 -#define GPIO_DOUT23_20_DIO21_S 8 - -// Field: [0] DIO20 -// -// Sets the state of the pin that is configured as DIO#20, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO20 0x00000001 -#define GPIO_DOUT23_20_DIO20_BITN 0 -#define GPIO_DOUT23_20_DIO20_M 0x00000001 -#define GPIO_DOUT23_20_DIO20_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT27_24 -// -//***************************************************************************** -// Field: [24] DIO27 -// -// Sets the state of the pin that is configured as DIO#27, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO27 0x01000000 -#define GPIO_DOUT27_24_DIO27_BITN 24 -#define GPIO_DOUT27_24_DIO27_M 0x01000000 -#define GPIO_DOUT27_24_DIO27_S 24 - -// Field: [16] DIO26 -// -// Sets the state of the pin that is configured as DIO#26, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO26 0x00010000 -#define GPIO_DOUT27_24_DIO26_BITN 16 -#define GPIO_DOUT27_24_DIO26_M 0x00010000 -#define GPIO_DOUT27_24_DIO26_S 16 - -// Field: [8] DIO25 -// -// Sets the state of the pin that is configured as DIO#25, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO25 0x00000100 -#define GPIO_DOUT27_24_DIO25_BITN 8 -#define GPIO_DOUT27_24_DIO25_M 0x00000100 -#define GPIO_DOUT27_24_DIO25_S 8 - -// Field: [0] DIO24 -// -// Sets the state of the pin that is configured as DIO#24, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO24 0x00000001 -#define GPIO_DOUT27_24_DIO24_BITN 0 -#define GPIO_DOUT27_24_DIO24_M 0x00000001 -#define GPIO_DOUT27_24_DIO24_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT31_28 -// -//***************************************************************************** -// Field: [24] DIO31 -// -// Sets the state of the pin that is configured as DIO#31, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO31 0x01000000 -#define GPIO_DOUT31_28_DIO31_BITN 24 -#define GPIO_DOUT31_28_DIO31_M 0x01000000 -#define GPIO_DOUT31_28_DIO31_S 24 - -// Field: [16] DIO30 -// -// Sets the state of the pin that is configured as DIO#30, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO30 0x00010000 -#define GPIO_DOUT31_28_DIO30_BITN 16 -#define GPIO_DOUT31_28_DIO30_M 0x00010000 -#define GPIO_DOUT31_28_DIO30_S 16 - -// Field: [8] DIO29 -// -// Sets the state of the pin that is configured as DIO#29, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO29 0x00000100 -#define GPIO_DOUT31_28_DIO29_BITN 8 -#define GPIO_DOUT31_28_DIO29_M 0x00000100 -#define GPIO_DOUT31_28_DIO29_S 8 - -// Field: [0] DIO28 -// -// Sets the state of the pin that is configured as DIO#28, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO28 0x00000001 -#define GPIO_DOUT31_28_DIO28_BITN 0 -#define GPIO_DOUT31_28_DIO28_M 0x00000001 -#define GPIO_DOUT31_28_DIO28_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Data output for DIO 31 -#define GPIO_DOUT31_0_DIO31 0x80000000 -#define GPIO_DOUT31_0_DIO31_BITN 31 -#define GPIO_DOUT31_0_DIO31_M 0x80000000 -#define GPIO_DOUT31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Data output for DIO 30 -#define GPIO_DOUT31_0_DIO30 0x40000000 -#define GPIO_DOUT31_0_DIO30_BITN 30 -#define GPIO_DOUT31_0_DIO30_M 0x40000000 -#define GPIO_DOUT31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Data output for DIO 29 -#define GPIO_DOUT31_0_DIO29 0x20000000 -#define GPIO_DOUT31_0_DIO29_BITN 29 -#define GPIO_DOUT31_0_DIO29_M 0x20000000 -#define GPIO_DOUT31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Data output for DIO 28 -#define GPIO_DOUT31_0_DIO28 0x10000000 -#define GPIO_DOUT31_0_DIO28_BITN 28 -#define GPIO_DOUT31_0_DIO28_M 0x10000000 -#define GPIO_DOUT31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Data output for DIO 27 -#define GPIO_DOUT31_0_DIO27 0x08000000 -#define GPIO_DOUT31_0_DIO27_BITN 27 -#define GPIO_DOUT31_0_DIO27_M 0x08000000 -#define GPIO_DOUT31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Data output for DIO 26 -#define GPIO_DOUT31_0_DIO26 0x04000000 -#define GPIO_DOUT31_0_DIO26_BITN 26 -#define GPIO_DOUT31_0_DIO26_M 0x04000000 -#define GPIO_DOUT31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Data output for DIO 25 -#define GPIO_DOUT31_0_DIO25 0x02000000 -#define GPIO_DOUT31_0_DIO25_BITN 25 -#define GPIO_DOUT31_0_DIO25_M 0x02000000 -#define GPIO_DOUT31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Data output for DIO 24 -#define GPIO_DOUT31_0_DIO24 0x01000000 -#define GPIO_DOUT31_0_DIO24_BITN 24 -#define GPIO_DOUT31_0_DIO24_M 0x01000000 -#define GPIO_DOUT31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Data output for DIO 23 -#define GPIO_DOUT31_0_DIO23 0x00800000 -#define GPIO_DOUT31_0_DIO23_BITN 23 -#define GPIO_DOUT31_0_DIO23_M 0x00800000 -#define GPIO_DOUT31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Data output for DIO 22 -#define GPIO_DOUT31_0_DIO22 0x00400000 -#define GPIO_DOUT31_0_DIO22_BITN 22 -#define GPIO_DOUT31_0_DIO22_M 0x00400000 -#define GPIO_DOUT31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Data output for DIO 21 -#define GPIO_DOUT31_0_DIO21 0x00200000 -#define GPIO_DOUT31_0_DIO21_BITN 21 -#define GPIO_DOUT31_0_DIO21_M 0x00200000 -#define GPIO_DOUT31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Data output for DIO 20 -#define GPIO_DOUT31_0_DIO20 0x00100000 -#define GPIO_DOUT31_0_DIO20_BITN 20 -#define GPIO_DOUT31_0_DIO20_M 0x00100000 -#define GPIO_DOUT31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Data output for DIO 19 -#define GPIO_DOUT31_0_DIO19 0x00080000 -#define GPIO_DOUT31_0_DIO19_BITN 19 -#define GPIO_DOUT31_0_DIO19_M 0x00080000 -#define GPIO_DOUT31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Data output for DIO 18 -#define GPIO_DOUT31_0_DIO18 0x00040000 -#define GPIO_DOUT31_0_DIO18_BITN 18 -#define GPIO_DOUT31_0_DIO18_M 0x00040000 -#define GPIO_DOUT31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Data output for DIO 17 -#define GPIO_DOUT31_0_DIO17 0x00020000 -#define GPIO_DOUT31_0_DIO17_BITN 17 -#define GPIO_DOUT31_0_DIO17_M 0x00020000 -#define GPIO_DOUT31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Data output for DIO 16 -#define GPIO_DOUT31_0_DIO16 0x00010000 -#define GPIO_DOUT31_0_DIO16_BITN 16 -#define GPIO_DOUT31_0_DIO16_M 0x00010000 -#define GPIO_DOUT31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Data output for DIO 15 -#define GPIO_DOUT31_0_DIO15 0x00008000 -#define GPIO_DOUT31_0_DIO15_BITN 15 -#define GPIO_DOUT31_0_DIO15_M 0x00008000 -#define GPIO_DOUT31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Data output for DIO 14 -#define GPIO_DOUT31_0_DIO14 0x00004000 -#define GPIO_DOUT31_0_DIO14_BITN 14 -#define GPIO_DOUT31_0_DIO14_M 0x00004000 -#define GPIO_DOUT31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Data output for DIO 13 -#define GPIO_DOUT31_0_DIO13 0x00002000 -#define GPIO_DOUT31_0_DIO13_BITN 13 -#define GPIO_DOUT31_0_DIO13_M 0x00002000 -#define GPIO_DOUT31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Data output for DIO 12 -#define GPIO_DOUT31_0_DIO12 0x00001000 -#define GPIO_DOUT31_0_DIO12_BITN 12 -#define GPIO_DOUT31_0_DIO12_M 0x00001000 -#define GPIO_DOUT31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Data output for DIO 11 -#define GPIO_DOUT31_0_DIO11 0x00000800 -#define GPIO_DOUT31_0_DIO11_BITN 11 -#define GPIO_DOUT31_0_DIO11_M 0x00000800 -#define GPIO_DOUT31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Data output for DIO 10 -#define GPIO_DOUT31_0_DIO10 0x00000400 -#define GPIO_DOUT31_0_DIO10_BITN 10 -#define GPIO_DOUT31_0_DIO10_M 0x00000400 -#define GPIO_DOUT31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Data output for DIO 9 -#define GPIO_DOUT31_0_DIO9 0x00000200 -#define GPIO_DOUT31_0_DIO9_BITN 9 -#define GPIO_DOUT31_0_DIO9_M 0x00000200 -#define GPIO_DOUT31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Data output for DIO 8 -#define GPIO_DOUT31_0_DIO8 0x00000100 -#define GPIO_DOUT31_0_DIO8_BITN 8 -#define GPIO_DOUT31_0_DIO8_M 0x00000100 -#define GPIO_DOUT31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Data output for DIO 7 -#define GPIO_DOUT31_0_DIO7 0x00000080 -#define GPIO_DOUT31_0_DIO7_BITN 7 -#define GPIO_DOUT31_0_DIO7_M 0x00000080 -#define GPIO_DOUT31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Data output for DIO 6 -#define GPIO_DOUT31_0_DIO6 0x00000040 -#define GPIO_DOUT31_0_DIO6_BITN 6 -#define GPIO_DOUT31_0_DIO6_M 0x00000040 -#define GPIO_DOUT31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Data output for DIO 5 -#define GPIO_DOUT31_0_DIO5 0x00000020 -#define GPIO_DOUT31_0_DIO5_BITN 5 -#define GPIO_DOUT31_0_DIO5_M 0x00000020 -#define GPIO_DOUT31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Data output for DIO 4 -#define GPIO_DOUT31_0_DIO4 0x00000010 -#define GPIO_DOUT31_0_DIO4_BITN 4 -#define GPIO_DOUT31_0_DIO4_M 0x00000010 -#define GPIO_DOUT31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Data output for DIO 3 -#define GPIO_DOUT31_0_DIO3 0x00000008 -#define GPIO_DOUT31_0_DIO3_BITN 3 -#define GPIO_DOUT31_0_DIO3_M 0x00000008 -#define GPIO_DOUT31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Data output for DIO 2 -#define GPIO_DOUT31_0_DIO2 0x00000004 -#define GPIO_DOUT31_0_DIO2_BITN 2 -#define GPIO_DOUT31_0_DIO2_M 0x00000004 -#define GPIO_DOUT31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Data output for DIO 1 -#define GPIO_DOUT31_0_DIO1 0x00000002 -#define GPIO_DOUT31_0_DIO1_BITN 1 -#define GPIO_DOUT31_0_DIO1_M 0x00000002 -#define GPIO_DOUT31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Data output for DIO 0 -#define GPIO_DOUT31_0_DIO0 0x00000001 -#define GPIO_DOUT31_0_DIO0_BITN 0 -#define GPIO_DOUT31_0_DIO0_M 0x00000001 -#define GPIO_DOUT31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUTSET31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Set bit 31 -#define GPIO_DOUTSET31_0_DIO31 0x80000000 -#define GPIO_DOUTSET31_0_DIO31_BITN 31 -#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 -#define GPIO_DOUTSET31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Set bit 30 -#define GPIO_DOUTSET31_0_DIO30 0x40000000 -#define GPIO_DOUTSET31_0_DIO30_BITN 30 -#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 -#define GPIO_DOUTSET31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Set bit 29 -#define GPIO_DOUTSET31_0_DIO29 0x20000000 -#define GPIO_DOUTSET31_0_DIO29_BITN 29 -#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 -#define GPIO_DOUTSET31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Set bit 28 -#define GPIO_DOUTSET31_0_DIO28 0x10000000 -#define GPIO_DOUTSET31_0_DIO28_BITN 28 -#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 -#define GPIO_DOUTSET31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Set bit 27 -#define GPIO_DOUTSET31_0_DIO27 0x08000000 -#define GPIO_DOUTSET31_0_DIO27_BITN 27 -#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 -#define GPIO_DOUTSET31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Set bit 26 -#define GPIO_DOUTSET31_0_DIO26 0x04000000 -#define GPIO_DOUTSET31_0_DIO26_BITN 26 -#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 -#define GPIO_DOUTSET31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Set bit 25 -#define GPIO_DOUTSET31_0_DIO25 0x02000000 -#define GPIO_DOUTSET31_0_DIO25_BITN 25 -#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 -#define GPIO_DOUTSET31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Set bit 24 -#define GPIO_DOUTSET31_0_DIO24 0x01000000 -#define GPIO_DOUTSET31_0_DIO24_BITN 24 -#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 -#define GPIO_DOUTSET31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Set bit 23 -#define GPIO_DOUTSET31_0_DIO23 0x00800000 -#define GPIO_DOUTSET31_0_DIO23_BITN 23 -#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 -#define GPIO_DOUTSET31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Set bit 22 -#define GPIO_DOUTSET31_0_DIO22 0x00400000 -#define GPIO_DOUTSET31_0_DIO22_BITN 22 -#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 -#define GPIO_DOUTSET31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Set bit 21 -#define GPIO_DOUTSET31_0_DIO21 0x00200000 -#define GPIO_DOUTSET31_0_DIO21_BITN 21 -#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 -#define GPIO_DOUTSET31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Set bit 20 -#define GPIO_DOUTSET31_0_DIO20 0x00100000 -#define GPIO_DOUTSET31_0_DIO20_BITN 20 -#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 -#define GPIO_DOUTSET31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Set bit 19 -#define GPIO_DOUTSET31_0_DIO19 0x00080000 -#define GPIO_DOUTSET31_0_DIO19_BITN 19 -#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 -#define GPIO_DOUTSET31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Set bit 18 -#define GPIO_DOUTSET31_0_DIO18 0x00040000 -#define GPIO_DOUTSET31_0_DIO18_BITN 18 -#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 -#define GPIO_DOUTSET31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Set bit 17 -#define GPIO_DOUTSET31_0_DIO17 0x00020000 -#define GPIO_DOUTSET31_0_DIO17_BITN 17 -#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 -#define GPIO_DOUTSET31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Set bit 16 -#define GPIO_DOUTSET31_0_DIO16 0x00010000 -#define GPIO_DOUTSET31_0_DIO16_BITN 16 -#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 -#define GPIO_DOUTSET31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Set bit 15 -#define GPIO_DOUTSET31_0_DIO15 0x00008000 -#define GPIO_DOUTSET31_0_DIO15_BITN 15 -#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 -#define GPIO_DOUTSET31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Set bit 14 -#define GPIO_DOUTSET31_0_DIO14 0x00004000 -#define GPIO_DOUTSET31_0_DIO14_BITN 14 -#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 -#define GPIO_DOUTSET31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Set bit 13 -#define GPIO_DOUTSET31_0_DIO13 0x00002000 -#define GPIO_DOUTSET31_0_DIO13_BITN 13 -#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 -#define GPIO_DOUTSET31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Set bit 12 -#define GPIO_DOUTSET31_0_DIO12 0x00001000 -#define GPIO_DOUTSET31_0_DIO12_BITN 12 -#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 -#define GPIO_DOUTSET31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Set bit 11 -#define GPIO_DOUTSET31_0_DIO11 0x00000800 -#define GPIO_DOUTSET31_0_DIO11_BITN 11 -#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 -#define GPIO_DOUTSET31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Set bit 10 -#define GPIO_DOUTSET31_0_DIO10 0x00000400 -#define GPIO_DOUTSET31_0_DIO10_BITN 10 -#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 -#define GPIO_DOUTSET31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Set bit 9 -#define GPIO_DOUTSET31_0_DIO9 0x00000200 -#define GPIO_DOUTSET31_0_DIO9_BITN 9 -#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 -#define GPIO_DOUTSET31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Set bit 8 -#define GPIO_DOUTSET31_0_DIO8 0x00000100 -#define GPIO_DOUTSET31_0_DIO8_BITN 8 -#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 -#define GPIO_DOUTSET31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Set bit 7 -#define GPIO_DOUTSET31_0_DIO7 0x00000080 -#define GPIO_DOUTSET31_0_DIO7_BITN 7 -#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 -#define GPIO_DOUTSET31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Set bit 6 -#define GPIO_DOUTSET31_0_DIO6 0x00000040 -#define GPIO_DOUTSET31_0_DIO6_BITN 6 -#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 -#define GPIO_DOUTSET31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Set bit 5 -#define GPIO_DOUTSET31_0_DIO5 0x00000020 -#define GPIO_DOUTSET31_0_DIO5_BITN 5 -#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 -#define GPIO_DOUTSET31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Set bit 4 -#define GPIO_DOUTSET31_0_DIO4 0x00000010 -#define GPIO_DOUTSET31_0_DIO4_BITN 4 -#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 -#define GPIO_DOUTSET31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Set bit 3 -#define GPIO_DOUTSET31_0_DIO3 0x00000008 -#define GPIO_DOUTSET31_0_DIO3_BITN 3 -#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 -#define GPIO_DOUTSET31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Set bit 2 -#define GPIO_DOUTSET31_0_DIO2 0x00000004 -#define GPIO_DOUTSET31_0_DIO2_BITN 2 -#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 -#define GPIO_DOUTSET31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Set bit 1 -#define GPIO_DOUTSET31_0_DIO1 0x00000002 -#define GPIO_DOUTSET31_0_DIO1_BITN 1 -#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 -#define GPIO_DOUTSET31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Set bit 0 -#define GPIO_DOUTSET31_0_DIO0 0x00000001 -#define GPIO_DOUTSET31_0_DIO0_BITN 0 -#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 -#define GPIO_DOUTSET31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUTCLR31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Clears bit 31 -#define GPIO_DOUTCLR31_0_DIO31 0x80000000 -#define GPIO_DOUTCLR31_0_DIO31_BITN 31 -#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 -#define GPIO_DOUTCLR31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Clears bit 30 -#define GPIO_DOUTCLR31_0_DIO30 0x40000000 -#define GPIO_DOUTCLR31_0_DIO30_BITN 30 -#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 -#define GPIO_DOUTCLR31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Clears bit 29 -#define GPIO_DOUTCLR31_0_DIO29 0x20000000 -#define GPIO_DOUTCLR31_0_DIO29_BITN 29 -#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 -#define GPIO_DOUTCLR31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Clears bit 28 -#define GPIO_DOUTCLR31_0_DIO28 0x10000000 -#define GPIO_DOUTCLR31_0_DIO28_BITN 28 -#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 -#define GPIO_DOUTCLR31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Clears bit 27 -#define GPIO_DOUTCLR31_0_DIO27 0x08000000 -#define GPIO_DOUTCLR31_0_DIO27_BITN 27 -#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 -#define GPIO_DOUTCLR31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Clears bit 26 -#define GPIO_DOUTCLR31_0_DIO26 0x04000000 -#define GPIO_DOUTCLR31_0_DIO26_BITN 26 -#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 -#define GPIO_DOUTCLR31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Clears bit 25 -#define GPIO_DOUTCLR31_0_DIO25 0x02000000 -#define GPIO_DOUTCLR31_0_DIO25_BITN 25 -#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 -#define GPIO_DOUTCLR31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Clears bit 24 -#define GPIO_DOUTCLR31_0_DIO24 0x01000000 -#define GPIO_DOUTCLR31_0_DIO24_BITN 24 -#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 -#define GPIO_DOUTCLR31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Clears bit 23 -#define GPIO_DOUTCLR31_0_DIO23 0x00800000 -#define GPIO_DOUTCLR31_0_DIO23_BITN 23 -#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 -#define GPIO_DOUTCLR31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Clears bit 22 -#define GPIO_DOUTCLR31_0_DIO22 0x00400000 -#define GPIO_DOUTCLR31_0_DIO22_BITN 22 -#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 -#define GPIO_DOUTCLR31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Clears bit 21 -#define GPIO_DOUTCLR31_0_DIO21 0x00200000 -#define GPIO_DOUTCLR31_0_DIO21_BITN 21 -#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 -#define GPIO_DOUTCLR31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Clears bit 20 -#define GPIO_DOUTCLR31_0_DIO20 0x00100000 -#define GPIO_DOUTCLR31_0_DIO20_BITN 20 -#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 -#define GPIO_DOUTCLR31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Clears bit 19 -#define GPIO_DOUTCLR31_0_DIO19 0x00080000 -#define GPIO_DOUTCLR31_0_DIO19_BITN 19 -#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 -#define GPIO_DOUTCLR31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Clears bit 18 -#define GPIO_DOUTCLR31_0_DIO18 0x00040000 -#define GPIO_DOUTCLR31_0_DIO18_BITN 18 -#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 -#define GPIO_DOUTCLR31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Clears bit 17 -#define GPIO_DOUTCLR31_0_DIO17 0x00020000 -#define GPIO_DOUTCLR31_0_DIO17_BITN 17 -#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 -#define GPIO_DOUTCLR31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Clears bit 16 -#define GPIO_DOUTCLR31_0_DIO16 0x00010000 -#define GPIO_DOUTCLR31_0_DIO16_BITN 16 -#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 -#define GPIO_DOUTCLR31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Clears bit 15 -#define GPIO_DOUTCLR31_0_DIO15 0x00008000 -#define GPIO_DOUTCLR31_0_DIO15_BITN 15 -#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 -#define GPIO_DOUTCLR31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Clears bit 14 -#define GPIO_DOUTCLR31_0_DIO14 0x00004000 -#define GPIO_DOUTCLR31_0_DIO14_BITN 14 -#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 -#define GPIO_DOUTCLR31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Clears bit 13 -#define GPIO_DOUTCLR31_0_DIO13 0x00002000 -#define GPIO_DOUTCLR31_0_DIO13_BITN 13 -#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 -#define GPIO_DOUTCLR31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Clears bit 12 -#define GPIO_DOUTCLR31_0_DIO12 0x00001000 -#define GPIO_DOUTCLR31_0_DIO12_BITN 12 -#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 -#define GPIO_DOUTCLR31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Clears bit 11 -#define GPIO_DOUTCLR31_0_DIO11 0x00000800 -#define GPIO_DOUTCLR31_0_DIO11_BITN 11 -#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 -#define GPIO_DOUTCLR31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Clears bit 10 -#define GPIO_DOUTCLR31_0_DIO10 0x00000400 -#define GPIO_DOUTCLR31_0_DIO10_BITN 10 -#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 -#define GPIO_DOUTCLR31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Clears bit 9 -#define GPIO_DOUTCLR31_0_DIO9 0x00000200 -#define GPIO_DOUTCLR31_0_DIO9_BITN 9 -#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 -#define GPIO_DOUTCLR31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Clears bit 8 -#define GPIO_DOUTCLR31_0_DIO8 0x00000100 -#define GPIO_DOUTCLR31_0_DIO8_BITN 8 -#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 -#define GPIO_DOUTCLR31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Clears bit 7 -#define GPIO_DOUTCLR31_0_DIO7 0x00000080 -#define GPIO_DOUTCLR31_0_DIO7_BITN 7 -#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 -#define GPIO_DOUTCLR31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Clears bit 6 -#define GPIO_DOUTCLR31_0_DIO6 0x00000040 -#define GPIO_DOUTCLR31_0_DIO6_BITN 6 -#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 -#define GPIO_DOUTCLR31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Clears bit 5 -#define GPIO_DOUTCLR31_0_DIO5 0x00000020 -#define GPIO_DOUTCLR31_0_DIO5_BITN 5 -#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 -#define GPIO_DOUTCLR31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Clears bit 4 -#define GPIO_DOUTCLR31_0_DIO4 0x00000010 -#define GPIO_DOUTCLR31_0_DIO4_BITN 4 -#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 -#define GPIO_DOUTCLR31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Clears bit 3 -#define GPIO_DOUTCLR31_0_DIO3 0x00000008 -#define GPIO_DOUTCLR31_0_DIO3_BITN 3 -#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 -#define GPIO_DOUTCLR31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Clears bit 2 -#define GPIO_DOUTCLR31_0_DIO2 0x00000004 -#define GPIO_DOUTCLR31_0_DIO2_BITN 2 -#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 -#define GPIO_DOUTCLR31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Clears bit 1 -#define GPIO_DOUTCLR31_0_DIO1 0x00000002 -#define GPIO_DOUTCLR31_0_DIO1_BITN 1 -#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 -#define GPIO_DOUTCLR31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Clears bit 0 -#define GPIO_DOUTCLR31_0_DIO0 0x00000001 -#define GPIO_DOUTCLR31_0_DIO0_BITN 0 -#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 -#define GPIO_DOUTCLR31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUTTGL31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Toggles bit 31 -#define GPIO_DOUTTGL31_0_DIO31 0x80000000 -#define GPIO_DOUTTGL31_0_DIO31_BITN 31 -#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 -#define GPIO_DOUTTGL31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Toggles bit 30 -#define GPIO_DOUTTGL31_0_DIO30 0x40000000 -#define GPIO_DOUTTGL31_0_DIO30_BITN 30 -#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 -#define GPIO_DOUTTGL31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Toggles bit 29 -#define GPIO_DOUTTGL31_0_DIO29 0x20000000 -#define GPIO_DOUTTGL31_0_DIO29_BITN 29 -#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 -#define GPIO_DOUTTGL31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Toggles bit 28 -#define GPIO_DOUTTGL31_0_DIO28 0x10000000 -#define GPIO_DOUTTGL31_0_DIO28_BITN 28 -#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 -#define GPIO_DOUTTGL31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Toggles bit 27 -#define GPIO_DOUTTGL31_0_DIO27 0x08000000 -#define GPIO_DOUTTGL31_0_DIO27_BITN 27 -#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 -#define GPIO_DOUTTGL31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Toggles bit 26 -#define GPIO_DOUTTGL31_0_DIO26 0x04000000 -#define GPIO_DOUTTGL31_0_DIO26_BITN 26 -#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 -#define GPIO_DOUTTGL31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Toggles bit 25 -#define GPIO_DOUTTGL31_0_DIO25 0x02000000 -#define GPIO_DOUTTGL31_0_DIO25_BITN 25 -#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 -#define GPIO_DOUTTGL31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Toggles bit 24 -#define GPIO_DOUTTGL31_0_DIO24 0x01000000 -#define GPIO_DOUTTGL31_0_DIO24_BITN 24 -#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 -#define GPIO_DOUTTGL31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Toggles bit 23 -#define GPIO_DOUTTGL31_0_DIO23 0x00800000 -#define GPIO_DOUTTGL31_0_DIO23_BITN 23 -#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 -#define GPIO_DOUTTGL31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Toggles bit 22 -#define GPIO_DOUTTGL31_0_DIO22 0x00400000 -#define GPIO_DOUTTGL31_0_DIO22_BITN 22 -#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 -#define GPIO_DOUTTGL31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Toggles bit 21 -#define GPIO_DOUTTGL31_0_DIO21 0x00200000 -#define GPIO_DOUTTGL31_0_DIO21_BITN 21 -#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 -#define GPIO_DOUTTGL31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Toggles bit 20 -#define GPIO_DOUTTGL31_0_DIO20 0x00100000 -#define GPIO_DOUTTGL31_0_DIO20_BITN 20 -#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 -#define GPIO_DOUTTGL31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Toggles bit 19 -#define GPIO_DOUTTGL31_0_DIO19 0x00080000 -#define GPIO_DOUTTGL31_0_DIO19_BITN 19 -#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 -#define GPIO_DOUTTGL31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Toggles bit 18 -#define GPIO_DOUTTGL31_0_DIO18 0x00040000 -#define GPIO_DOUTTGL31_0_DIO18_BITN 18 -#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 -#define GPIO_DOUTTGL31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Toggles bit 17 -#define GPIO_DOUTTGL31_0_DIO17 0x00020000 -#define GPIO_DOUTTGL31_0_DIO17_BITN 17 -#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 -#define GPIO_DOUTTGL31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Toggles bit 16 -#define GPIO_DOUTTGL31_0_DIO16 0x00010000 -#define GPIO_DOUTTGL31_0_DIO16_BITN 16 -#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 -#define GPIO_DOUTTGL31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Toggles bit 15 -#define GPIO_DOUTTGL31_0_DIO15 0x00008000 -#define GPIO_DOUTTGL31_0_DIO15_BITN 15 -#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 -#define GPIO_DOUTTGL31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Toggles bit 14 -#define GPIO_DOUTTGL31_0_DIO14 0x00004000 -#define GPIO_DOUTTGL31_0_DIO14_BITN 14 -#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 -#define GPIO_DOUTTGL31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Toggles bit 13 -#define GPIO_DOUTTGL31_0_DIO13 0x00002000 -#define GPIO_DOUTTGL31_0_DIO13_BITN 13 -#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 -#define GPIO_DOUTTGL31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Toggles bit 12 -#define GPIO_DOUTTGL31_0_DIO12 0x00001000 -#define GPIO_DOUTTGL31_0_DIO12_BITN 12 -#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 -#define GPIO_DOUTTGL31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Toggles bit 11 -#define GPIO_DOUTTGL31_0_DIO11 0x00000800 -#define GPIO_DOUTTGL31_0_DIO11_BITN 11 -#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 -#define GPIO_DOUTTGL31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Toggles bit 10 -#define GPIO_DOUTTGL31_0_DIO10 0x00000400 -#define GPIO_DOUTTGL31_0_DIO10_BITN 10 -#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 -#define GPIO_DOUTTGL31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Toggles bit 9 -#define GPIO_DOUTTGL31_0_DIO9 0x00000200 -#define GPIO_DOUTTGL31_0_DIO9_BITN 9 -#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 -#define GPIO_DOUTTGL31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Toggles bit 8 -#define GPIO_DOUTTGL31_0_DIO8 0x00000100 -#define GPIO_DOUTTGL31_0_DIO8_BITN 8 -#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 -#define GPIO_DOUTTGL31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Toggles bit 7 -#define GPIO_DOUTTGL31_0_DIO7 0x00000080 -#define GPIO_DOUTTGL31_0_DIO7_BITN 7 -#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 -#define GPIO_DOUTTGL31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Toggles bit 6 -#define GPIO_DOUTTGL31_0_DIO6 0x00000040 -#define GPIO_DOUTTGL31_0_DIO6_BITN 6 -#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 -#define GPIO_DOUTTGL31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Toggles bit 5 -#define GPIO_DOUTTGL31_0_DIO5 0x00000020 -#define GPIO_DOUTTGL31_0_DIO5_BITN 5 -#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 -#define GPIO_DOUTTGL31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Toggles bit 4 -#define GPIO_DOUTTGL31_0_DIO4 0x00000010 -#define GPIO_DOUTTGL31_0_DIO4_BITN 4 -#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 -#define GPIO_DOUTTGL31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Toggles bit 3 -#define GPIO_DOUTTGL31_0_DIO3 0x00000008 -#define GPIO_DOUTTGL31_0_DIO3_BITN 3 -#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 -#define GPIO_DOUTTGL31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Toggles bit 2 -#define GPIO_DOUTTGL31_0_DIO2 0x00000004 -#define GPIO_DOUTTGL31_0_DIO2_BITN 2 -#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 -#define GPIO_DOUTTGL31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Toggles bit 1 -#define GPIO_DOUTTGL31_0_DIO1 0x00000002 -#define GPIO_DOUTTGL31_0_DIO1_BITN 1 -#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 -#define GPIO_DOUTTGL31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Toggles bit 0 -#define GPIO_DOUTTGL31_0_DIO0 0x00000001 -#define GPIO_DOUTTGL31_0_DIO0_BITN 0 -#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 -#define GPIO_DOUTTGL31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DIN31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Data input from DIO 31 -#define GPIO_DIN31_0_DIO31 0x80000000 -#define GPIO_DIN31_0_DIO31_BITN 31 -#define GPIO_DIN31_0_DIO31_M 0x80000000 -#define GPIO_DIN31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Data input from DIO 30 -#define GPIO_DIN31_0_DIO30 0x40000000 -#define GPIO_DIN31_0_DIO30_BITN 30 -#define GPIO_DIN31_0_DIO30_M 0x40000000 -#define GPIO_DIN31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Data input from DIO 29 -#define GPIO_DIN31_0_DIO29 0x20000000 -#define GPIO_DIN31_0_DIO29_BITN 29 -#define GPIO_DIN31_0_DIO29_M 0x20000000 -#define GPIO_DIN31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Data input from DIO 28 -#define GPIO_DIN31_0_DIO28 0x10000000 -#define GPIO_DIN31_0_DIO28_BITN 28 -#define GPIO_DIN31_0_DIO28_M 0x10000000 -#define GPIO_DIN31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Data input from DIO 27 -#define GPIO_DIN31_0_DIO27 0x08000000 -#define GPIO_DIN31_0_DIO27_BITN 27 -#define GPIO_DIN31_0_DIO27_M 0x08000000 -#define GPIO_DIN31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Data input from DIO 26 -#define GPIO_DIN31_0_DIO26 0x04000000 -#define GPIO_DIN31_0_DIO26_BITN 26 -#define GPIO_DIN31_0_DIO26_M 0x04000000 -#define GPIO_DIN31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Data input from DIO 25 -#define GPIO_DIN31_0_DIO25 0x02000000 -#define GPIO_DIN31_0_DIO25_BITN 25 -#define GPIO_DIN31_0_DIO25_M 0x02000000 -#define GPIO_DIN31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Data input from DIO 24 -#define GPIO_DIN31_0_DIO24 0x01000000 -#define GPIO_DIN31_0_DIO24_BITN 24 -#define GPIO_DIN31_0_DIO24_M 0x01000000 -#define GPIO_DIN31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Data input from DIO 23 -#define GPIO_DIN31_0_DIO23 0x00800000 -#define GPIO_DIN31_0_DIO23_BITN 23 -#define GPIO_DIN31_0_DIO23_M 0x00800000 -#define GPIO_DIN31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Data input from DIO 22 -#define GPIO_DIN31_0_DIO22 0x00400000 -#define GPIO_DIN31_0_DIO22_BITN 22 -#define GPIO_DIN31_0_DIO22_M 0x00400000 -#define GPIO_DIN31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Data input from DIO 21 -#define GPIO_DIN31_0_DIO21 0x00200000 -#define GPIO_DIN31_0_DIO21_BITN 21 -#define GPIO_DIN31_0_DIO21_M 0x00200000 -#define GPIO_DIN31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Data input from DIO 20 -#define GPIO_DIN31_0_DIO20 0x00100000 -#define GPIO_DIN31_0_DIO20_BITN 20 -#define GPIO_DIN31_0_DIO20_M 0x00100000 -#define GPIO_DIN31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Data input from DIO 19 -#define GPIO_DIN31_0_DIO19 0x00080000 -#define GPIO_DIN31_0_DIO19_BITN 19 -#define GPIO_DIN31_0_DIO19_M 0x00080000 -#define GPIO_DIN31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Data input from DIO 18 -#define GPIO_DIN31_0_DIO18 0x00040000 -#define GPIO_DIN31_0_DIO18_BITN 18 -#define GPIO_DIN31_0_DIO18_M 0x00040000 -#define GPIO_DIN31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Data input from DIO 17 -#define GPIO_DIN31_0_DIO17 0x00020000 -#define GPIO_DIN31_0_DIO17_BITN 17 -#define GPIO_DIN31_0_DIO17_M 0x00020000 -#define GPIO_DIN31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Data input from DIO 16 -#define GPIO_DIN31_0_DIO16 0x00010000 -#define GPIO_DIN31_0_DIO16_BITN 16 -#define GPIO_DIN31_0_DIO16_M 0x00010000 -#define GPIO_DIN31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Data input from DIO 15 -#define GPIO_DIN31_0_DIO15 0x00008000 -#define GPIO_DIN31_0_DIO15_BITN 15 -#define GPIO_DIN31_0_DIO15_M 0x00008000 -#define GPIO_DIN31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Data input from DIO 14 -#define GPIO_DIN31_0_DIO14 0x00004000 -#define GPIO_DIN31_0_DIO14_BITN 14 -#define GPIO_DIN31_0_DIO14_M 0x00004000 -#define GPIO_DIN31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Data input from DIO 13 -#define GPIO_DIN31_0_DIO13 0x00002000 -#define GPIO_DIN31_0_DIO13_BITN 13 -#define GPIO_DIN31_0_DIO13_M 0x00002000 -#define GPIO_DIN31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Data input from DIO 12 -#define GPIO_DIN31_0_DIO12 0x00001000 -#define GPIO_DIN31_0_DIO12_BITN 12 -#define GPIO_DIN31_0_DIO12_M 0x00001000 -#define GPIO_DIN31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Data input from DIO 11 -#define GPIO_DIN31_0_DIO11 0x00000800 -#define GPIO_DIN31_0_DIO11_BITN 11 -#define GPIO_DIN31_0_DIO11_M 0x00000800 -#define GPIO_DIN31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Data input from DIO 10 -#define GPIO_DIN31_0_DIO10 0x00000400 -#define GPIO_DIN31_0_DIO10_BITN 10 -#define GPIO_DIN31_0_DIO10_M 0x00000400 -#define GPIO_DIN31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Data input from DIO 9 -#define GPIO_DIN31_0_DIO9 0x00000200 -#define GPIO_DIN31_0_DIO9_BITN 9 -#define GPIO_DIN31_0_DIO9_M 0x00000200 -#define GPIO_DIN31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Data input from DIO 8 -#define GPIO_DIN31_0_DIO8 0x00000100 -#define GPIO_DIN31_0_DIO8_BITN 8 -#define GPIO_DIN31_0_DIO8_M 0x00000100 -#define GPIO_DIN31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Data input from DIO 7 -#define GPIO_DIN31_0_DIO7 0x00000080 -#define GPIO_DIN31_0_DIO7_BITN 7 -#define GPIO_DIN31_0_DIO7_M 0x00000080 -#define GPIO_DIN31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Data input from DIO 6 -#define GPIO_DIN31_0_DIO6 0x00000040 -#define GPIO_DIN31_0_DIO6_BITN 6 -#define GPIO_DIN31_0_DIO6_M 0x00000040 -#define GPIO_DIN31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Data input from DIO 5 -#define GPIO_DIN31_0_DIO5 0x00000020 -#define GPIO_DIN31_0_DIO5_BITN 5 -#define GPIO_DIN31_0_DIO5_M 0x00000020 -#define GPIO_DIN31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Data input from DIO 4 -#define GPIO_DIN31_0_DIO4 0x00000010 -#define GPIO_DIN31_0_DIO4_BITN 4 -#define GPIO_DIN31_0_DIO4_M 0x00000010 -#define GPIO_DIN31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Data input from DIO 3 -#define GPIO_DIN31_0_DIO3 0x00000008 -#define GPIO_DIN31_0_DIO3_BITN 3 -#define GPIO_DIN31_0_DIO3_M 0x00000008 -#define GPIO_DIN31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Data input from DIO 2 -#define GPIO_DIN31_0_DIO2 0x00000004 -#define GPIO_DIN31_0_DIO2_BITN 2 -#define GPIO_DIN31_0_DIO2_M 0x00000004 -#define GPIO_DIN31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Data input from DIO 1 -#define GPIO_DIN31_0_DIO1 0x00000002 -#define GPIO_DIN31_0_DIO1_BITN 1 -#define GPIO_DIN31_0_DIO1_M 0x00000002 -#define GPIO_DIN31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Data input from DIO 0 -#define GPIO_DIN31_0_DIO0 0x00000001 -#define GPIO_DIN31_0_DIO0_BITN 0 -#define GPIO_DIN31_0_DIO0_M 0x00000001 -#define GPIO_DIN31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOE31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Data output enable for DIO 31 -#define GPIO_DOE31_0_DIO31 0x80000000 -#define GPIO_DOE31_0_DIO31_BITN 31 -#define GPIO_DOE31_0_DIO31_M 0x80000000 -#define GPIO_DOE31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Data output enable for DIO 30 -#define GPIO_DOE31_0_DIO30 0x40000000 -#define GPIO_DOE31_0_DIO30_BITN 30 -#define GPIO_DOE31_0_DIO30_M 0x40000000 -#define GPIO_DOE31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Data output enable for DIO 29 -#define GPIO_DOE31_0_DIO29 0x20000000 -#define GPIO_DOE31_0_DIO29_BITN 29 -#define GPIO_DOE31_0_DIO29_M 0x20000000 -#define GPIO_DOE31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Data output enable for DIO 28 -#define GPIO_DOE31_0_DIO28 0x10000000 -#define GPIO_DOE31_0_DIO28_BITN 28 -#define GPIO_DOE31_0_DIO28_M 0x10000000 -#define GPIO_DOE31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Data output enable for DIO 27 -#define GPIO_DOE31_0_DIO27 0x08000000 -#define GPIO_DOE31_0_DIO27_BITN 27 -#define GPIO_DOE31_0_DIO27_M 0x08000000 -#define GPIO_DOE31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Data output enable for DIO 26 -#define GPIO_DOE31_0_DIO26 0x04000000 -#define GPIO_DOE31_0_DIO26_BITN 26 -#define GPIO_DOE31_0_DIO26_M 0x04000000 -#define GPIO_DOE31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Data output enable for DIO 25 -#define GPIO_DOE31_0_DIO25 0x02000000 -#define GPIO_DOE31_0_DIO25_BITN 25 -#define GPIO_DOE31_0_DIO25_M 0x02000000 -#define GPIO_DOE31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Data output enable for DIO 24 -#define GPIO_DOE31_0_DIO24 0x01000000 -#define GPIO_DOE31_0_DIO24_BITN 24 -#define GPIO_DOE31_0_DIO24_M 0x01000000 -#define GPIO_DOE31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Data output enable for DIO 23 -#define GPIO_DOE31_0_DIO23 0x00800000 -#define GPIO_DOE31_0_DIO23_BITN 23 -#define GPIO_DOE31_0_DIO23_M 0x00800000 -#define GPIO_DOE31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Data output enable for DIO 22 -#define GPIO_DOE31_0_DIO22 0x00400000 -#define GPIO_DOE31_0_DIO22_BITN 22 -#define GPIO_DOE31_0_DIO22_M 0x00400000 -#define GPIO_DOE31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Data output enable for DIO 21 -#define GPIO_DOE31_0_DIO21 0x00200000 -#define GPIO_DOE31_0_DIO21_BITN 21 -#define GPIO_DOE31_0_DIO21_M 0x00200000 -#define GPIO_DOE31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Data output enable for DIO 20 -#define GPIO_DOE31_0_DIO20 0x00100000 -#define GPIO_DOE31_0_DIO20_BITN 20 -#define GPIO_DOE31_0_DIO20_M 0x00100000 -#define GPIO_DOE31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Data output enable for DIO 19 -#define GPIO_DOE31_0_DIO19 0x00080000 -#define GPIO_DOE31_0_DIO19_BITN 19 -#define GPIO_DOE31_0_DIO19_M 0x00080000 -#define GPIO_DOE31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Data output enable for DIO 18 -#define GPIO_DOE31_0_DIO18 0x00040000 -#define GPIO_DOE31_0_DIO18_BITN 18 -#define GPIO_DOE31_0_DIO18_M 0x00040000 -#define GPIO_DOE31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Data output enable for DIO 17 -#define GPIO_DOE31_0_DIO17 0x00020000 -#define GPIO_DOE31_0_DIO17_BITN 17 -#define GPIO_DOE31_0_DIO17_M 0x00020000 -#define GPIO_DOE31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Data output enable for DIO 16 -#define GPIO_DOE31_0_DIO16 0x00010000 -#define GPIO_DOE31_0_DIO16_BITN 16 -#define GPIO_DOE31_0_DIO16_M 0x00010000 -#define GPIO_DOE31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Data output enable for DIO 15 -#define GPIO_DOE31_0_DIO15 0x00008000 -#define GPIO_DOE31_0_DIO15_BITN 15 -#define GPIO_DOE31_0_DIO15_M 0x00008000 -#define GPIO_DOE31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Data output enable for DIO 14 -#define GPIO_DOE31_0_DIO14 0x00004000 -#define GPIO_DOE31_0_DIO14_BITN 14 -#define GPIO_DOE31_0_DIO14_M 0x00004000 -#define GPIO_DOE31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Data output enable for DIO 13 -#define GPIO_DOE31_0_DIO13 0x00002000 -#define GPIO_DOE31_0_DIO13_BITN 13 -#define GPIO_DOE31_0_DIO13_M 0x00002000 -#define GPIO_DOE31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Data output enable for DIO 12 -#define GPIO_DOE31_0_DIO12 0x00001000 -#define GPIO_DOE31_0_DIO12_BITN 12 -#define GPIO_DOE31_0_DIO12_M 0x00001000 -#define GPIO_DOE31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Data output enable for DIO 11 -#define GPIO_DOE31_0_DIO11 0x00000800 -#define GPIO_DOE31_0_DIO11_BITN 11 -#define GPIO_DOE31_0_DIO11_M 0x00000800 -#define GPIO_DOE31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Data output enable for DIO 10 -#define GPIO_DOE31_0_DIO10 0x00000400 -#define GPIO_DOE31_0_DIO10_BITN 10 -#define GPIO_DOE31_0_DIO10_M 0x00000400 -#define GPIO_DOE31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Data output enable for DIO 9 -#define GPIO_DOE31_0_DIO9 0x00000200 -#define GPIO_DOE31_0_DIO9_BITN 9 -#define GPIO_DOE31_0_DIO9_M 0x00000200 -#define GPIO_DOE31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Data output enable for DIO 8 -#define GPIO_DOE31_0_DIO8 0x00000100 -#define GPIO_DOE31_0_DIO8_BITN 8 -#define GPIO_DOE31_0_DIO8_M 0x00000100 -#define GPIO_DOE31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Data output enable for DIO 7 -#define GPIO_DOE31_0_DIO7 0x00000080 -#define GPIO_DOE31_0_DIO7_BITN 7 -#define GPIO_DOE31_0_DIO7_M 0x00000080 -#define GPIO_DOE31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Data output enable for DIO 6 -#define GPIO_DOE31_0_DIO6 0x00000040 -#define GPIO_DOE31_0_DIO6_BITN 6 -#define GPIO_DOE31_0_DIO6_M 0x00000040 -#define GPIO_DOE31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Data output enable for DIO 5 -#define GPIO_DOE31_0_DIO5 0x00000020 -#define GPIO_DOE31_0_DIO5_BITN 5 -#define GPIO_DOE31_0_DIO5_M 0x00000020 -#define GPIO_DOE31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Data output enable for DIO 4 -#define GPIO_DOE31_0_DIO4 0x00000010 -#define GPIO_DOE31_0_DIO4_BITN 4 -#define GPIO_DOE31_0_DIO4_M 0x00000010 -#define GPIO_DOE31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Data output enable for DIO 3 -#define GPIO_DOE31_0_DIO3 0x00000008 -#define GPIO_DOE31_0_DIO3_BITN 3 -#define GPIO_DOE31_0_DIO3_M 0x00000008 -#define GPIO_DOE31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Data output enable for DIO 2 -#define GPIO_DOE31_0_DIO2 0x00000004 -#define GPIO_DOE31_0_DIO2_BITN 2 -#define GPIO_DOE31_0_DIO2_M 0x00000004 -#define GPIO_DOE31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Data output enable for DIO 1 -#define GPIO_DOE31_0_DIO1 0x00000002 -#define GPIO_DOE31_0_DIO1_BITN 1 -#define GPIO_DOE31_0_DIO1_M 0x00000002 -#define GPIO_DOE31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Data output enable for DIO 0 -#define GPIO_DOE31_0_DIO0 0x00000001 -#define GPIO_DOE31_0_DIO0_BITN 0 -#define GPIO_DOE31_0_DIO0_M 0x00000001 -#define GPIO_DOE31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_EVFLAGS31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Event for DIO 31 -#define GPIO_EVFLAGS31_0_DIO31 0x80000000 -#define GPIO_EVFLAGS31_0_DIO31_BITN 31 -#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 -#define GPIO_EVFLAGS31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Event for DIO 30 -#define GPIO_EVFLAGS31_0_DIO30 0x40000000 -#define GPIO_EVFLAGS31_0_DIO30_BITN 30 -#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 -#define GPIO_EVFLAGS31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Event for DIO 29 -#define GPIO_EVFLAGS31_0_DIO29 0x20000000 -#define GPIO_EVFLAGS31_0_DIO29_BITN 29 -#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 -#define GPIO_EVFLAGS31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Event for DIO 28 -#define GPIO_EVFLAGS31_0_DIO28 0x10000000 -#define GPIO_EVFLAGS31_0_DIO28_BITN 28 -#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 -#define GPIO_EVFLAGS31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Event for DIO 27 -#define GPIO_EVFLAGS31_0_DIO27 0x08000000 -#define GPIO_EVFLAGS31_0_DIO27_BITN 27 -#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 -#define GPIO_EVFLAGS31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Event for DIO 26 -#define GPIO_EVFLAGS31_0_DIO26 0x04000000 -#define GPIO_EVFLAGS31_0_DIO26_BITN 26 -#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 -#define GPIO_EVFLAGS31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Event for DIO 25 -#define GPIO_EVFLAGS31_0_DIO25 0x02000000 -#define GPIO_EVFLAGS31_0_DIO25_BITN 25 -#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 -#define GPIO_EVFLAGS31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Event for DIO 24 -#define GPIO_EVFLAGS31_0_DIO24 0x01000000 -#define GPIO_EVFLAGS31_0_DIO24_BITN 24 -#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 -#define GPIO_EVFLAGS31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Event for DIO 23 -#define GPIO_EVFLAGS31_0_DIO23 0x00800000 -#define GPIO_EVFLAGS31_0_DIO23_BITN 23 -#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 -#define GPIO_EVFLAGS31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Event for DIO 22 -#define GPIO_EVFLAGS31_0_DIO22 0x00400000 -#define GPIO_EVFLAGS31_0_DIO22_BITN 22 -#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 -#define GPIO_EVFLAGS31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Event for DIO 21 -#define GPIO_EVFLAGS31_0_DIO21 0x00200000 -#define GPIO_EVFLAGS31_0_DIO21_BITN 21 -#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 -#define GPIO_EVFLAGS31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Event for DIO 20 -#define GPIO_EVFLAGS31_0_DIO20 0x00100000 -#define GPIO_EVFLAGS31_0_DIO20_BITN 20 -#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 -#define GPIO_EVFLAGS31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Event for DIO 19 -#define GPIO_EVFLAGS31_0_DIO19 0x00080000 -#define GPIO_EVFLAGS31_0_DIO19_BITN 19 -#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 -#define GPIO_EVFLAGS31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Event for DIO 18 -#define GPIO_EVFLAGS31_0_DIO18 0x00040000 -#define GPIO_EVFLAGS31_0_DIO18_BITN 18 -#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 -#define GPIO_EVFLAGS31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Event for DIO 17 -#define GPIO_EVFLAGS31_0_DIO17 0x00020000 -#define GPIO_EVFLAGS31_0_DIO17_BITN 17 -#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 -#define GPIO_EVFLAGS31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Event for DIO 16 -#define GPIO_EVFLAGS31_0_DIO16 0x00010000 -#define GPIO_EVFLAGS31_0_DIO16_BITN 16 -#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 -#define GPIO_EVFLAGS31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Event for DIO 15 -#define GPIO_EVFLAGS31_0_DIO15 0x00008000 -#define GPIO_EVFLAGS31_0_DIO15_BITN 15 -#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 -#define GPIO_EVFLAGS31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Event for DIO 14 -#define GPIO_EVFLAGS31_0_DIO14 0x00004000 -#define GPIO_EVFLAGS31_0_DIO14_BITN 14 -#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 -#define GPIO_EVFLAGS31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Event for DIO 13 -#define GPIO_EVFLAGS31_0_DIO13 0x00002000 -#define GPIO_EVFLAGS31_0_DIO13_BITN 13 -#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 -#define GPIO_EVFLAGS31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Event for DIO 12 -#define GPIO_EVFLAGS31_0_DIO12 0x00001000 -#define GPIO_EVFLAGS31_0_DIO12_BITN 12 -#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 -#define GPIO_EVFLAGS31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Event for DIO 11 -#define GPIO_EVFLAGS31_0_DIO11 0x00000800 -#define GPIO_EVFLAGS31_0_DIO11_BITN 11 -#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 -#define GPIO_EVFLAGS31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Event for DIO 10 -#define GPIO_EVFLAGS31_0_DIO10 0x00000400 -#define GPIO_EVFLAGS31_0_DIO10_BITN 10 -#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 -#define GPIO_EVFLAGS31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Event for DIO 9 -#define GPIO_EVFLAGS31_0_DIO9 0x00000200 -#define GPIO_EVFLAGS31_0_DIO9_BITN 9 -#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 -#define GPIO_EVFLAGS31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Event for DIO 8 -#define GPIO_EVFLAGS31_0_DIO8 0x00000100 -#define GPIO_EVFLAGS31_0_DIO8_BITN 8 -#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 -#define GPIO_EVFLAGS31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Event for DIO 7 -#define GPIO_EVFLAGS31_0_DIO7 0x00000080 -#define GPIO_EVFLAGS31_0_DIO7_BITN 7 -#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 -#define GPIO_EVFLAGS31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Event for DIO 6 -#define GPIO_EVFLAGS31_0_DIO6 0x00000040 -#define GPIO_EVFLAGS31_0_DIO6_BITN 6 -#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 -#define GPIO_EVFLAGS31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Event for DIO 5 -#define GPIO_EVFLAGS31_0_DIO5 0x00000020 -#define GPIO_EVFLAGS31_0_DIO5_BITN 5 -#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 -#define GPIO_EVFLAGS31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Event for DIO 4 -#define GPIO_EVFLAGS31_0_DIO4 0x00000010 -#define GPIO_EVFLAGS31_0_DIO4_BITN 4 -#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 -#define GPIO_EVFLAGS31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Event for DIO 3 -#define GPIO_EVFLAGS31_0_DIO3 0x00000008 -#define GPIO_EVFLAGS31_0_DIO3_BITN 3 -#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 -#define GPIO_EVFLAGS31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Event for DIO 2 -#define GPIO_EVFLAGS31_0_DIO2 0x00000004 -#define GPIO_EVFLAGS31_0_DIO2_BITN 2 -#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 -#define GPIO_EVFLAGS31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Event for DIO 1 -#define GPIO_EVFLAGS31_0_DIO1 0x00000002 -#define GPIO_EVFLAGS31_0_DIO1_BITN 1 -#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 -#define GPIO_EVFLAGS31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Event for DIO 0 -#define GPIO_EVFLAGS31_0_DIO0 0x00000001 -#define GPIO_EVFLAGS31_0_DIO0_BITN 0 -#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 -#define GPIO_EVFLAGS31_0_DIO0_S 0 - - -#endif // __GPIO__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_gpt.h b/third_party/ti/devices/cc26x0/inc/hw_gpt.h deleted file mode 100644 index aa116e716..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_gpt.h +++ /dev/null @@ -1,1686 +0,0 @@ -/****************************************************************************** -* Filename: hw_gpt_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_GPT_H__ -#define __HW_GPT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// GPT component -// -//***************************************************************************** -// Configuration -#define GPT_O_CFG 0x00000000 - -// Timer A Mode -#define GPT_O_TAMR 0x00000004 - -// Timer B Mode -#define GPT_O_TBMR 0x00000008 - -// Control -#define GPT_O_CTL 0x0000000C - -// Synch Register -#define GPT_O_SYNC 0x00000010 - -// Interrupt Mask -#define GPT_O_IMR 0x00000018 - -// Raw Interrupt Status -#define GPT_O_RIS 0x0000001C - -// Masked Interrupt Status -#define GPT_O_MIS 0x00000020 - -// Interrupt Clear -#define GPT_O_ICLR 0x00000024 - -// Timer A Interval Load Register -#define GPT_O_TAILR 0x00000028 - -// Timer B Interval Load Register -#define GPT_O_TBILR 0x0000002C - -// Timer A Match Register -#define GPT_O_TAMATCHR 0x00000030 - -// Timer B Match Register -#define GPT_O_TBMATCHR 0x00000034 - -// Timer A Pre-scale -#define GPT_O_TAPR 0x00000038 - -// Timer B Pre-scale -#define GPT_O_TBPR 0x0000003C - -// Timer A Pre-scale Match -#define GPT_O_TAPMR 0x00000040 - -// Timer B Pre-scale Match -#define GPT_O_TBPMR 0x00000044 - -// Timer A Register -#define GPT_O_TAR 0x00000048 - -// Timer B Register -#define GPT_O_TBR 0x0000004C - -// Timer A Value -#define GPT_O_TAV 0x00000050 - -// Timer B Value -#define GPT_O_TBV 0x00000054 - -// Timer A Pre-scale Snap-shot -#define GPT_O_TAPS 0x0000005C - -// Timer B Pre-scale Snap-shot -#define GPT_O_TBPS 0x00000060 - -// Timer A Pre-scale Value -#define GPT_O_TAPV 0x00000064 - -// Timer B Pre-scale Value -#define GPT_O_TBPV 0x00000068 - -// DMA Event -#define GPT_O_DMAEV 0x0000006C - -// Peripheral Version -#define GPT_O_VERSION 0x00000FB0 - -// Combined CCP Output -#define GPT_O_ANDCCP 0x00000FB4 - -//***************************************************************************** -// -// Register: GPT_O_CFG -// -//***************************************************************************** -// Field: [2:0] CFG -// -// GPT Configuration -// 0x2- 0x3 - Reserved -// 0x5- 0x7 - Reserved -// ENUMs: -// 16BIT_TIMER 16-bit timer configuration. -// Configure for two 16-bit -// timers. -// Also see TAMR.TAMR and -// TBMR.TBMR. -// 32BIT_TIMER 32-bit timer configuration -#define GPT_CFG_CFG_W 3 -#define GPT_CFG_CFG_M 0x00000007 -#define GPT_CFG_CFG_S 0 -#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 -#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 - -//***************************************************************************** -// -// Register: GPT_O_TAMR -// -//***************************************************************************** -// Field: [15:13] TCACT -// -// Timer Compare Action Select -// ENUMs: -// CLRSET_ON_TO Clear CCP output pin immediately and set on -// Time-Out -// SETCLR_ON_TO Set CCP output pin immediately and clear on -// Time-Out -// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on -// Time-Out -// SETTOG_ON_TO Set CCP output pin immediately and toggle on -// Time-Out -// SET_ON_TO Set CCP output pin on Time-Out -// CLR_ON_TO Clear CCP output pin on Time-Out -// TOG_ON_TO Toggle State on Time-Out -// DIS_CMP Disable compare operations -#define GPT_TAMR_TCACT_W 3 -#define GPT_TAMR_TCACT_M 0x0000E000 -#define GPT_TAMR_TCACT_S 13 -#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 -#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 -#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 -#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 -#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 -#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 -#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 -#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 - -// Field: [12] TACINTD -// -// One-Shot/Periodic Interrupt Disable -// ENUMs: -// DIS_TO_INTR Time-out interrupt are disabled -// EN_TO_INTR Time-out interrupt function as normal -#define GPT_TAMR_TACINTD 0x00001000 -#define GPT_TAMR_TACINTD_BITN 12 -#define GPT_TAMR_TACINTD_M 0x00001000 -#define GPT_TAMR_TACINTD_S 12 -#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 -#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 - -// Field: [11] TAPLO -// -// GPTM Timer A PWM Legacy Operation -// -// 0 Legacy operation with CCP pin driven Low when the TAILR -// register is reloaded after the timer reaches 0. -// -// 1 CCP is driven High when the TAILR register is reloaded after the timer -// reaches 0. -// -// This bit is only valid in PWM mode. -// ENUMs: -// CCP_ON_TO CCP output pin is set to 1 on time-out -// LEGACY Legacy operation -#define GPT_TAMR_TAPLO 0x00000800 -#define GPT_TAMR_TAPLO_BITN 11 -#define GPT_TAMR_TAPLO_M 0x00000800 -#define GPT_TAMR_TAPLO_S 11 -#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 -#define GPT_TAMR_TAPLO_LEGACY 0x00000000 - -// Field: [10] TAMRSU -// -// Timer A Match Register Update mode -// -// This bit defines when the TAMATCHR and TAPR registers are updated. -// -// If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and -// TAPR are updated when the timer is enabled. -// If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and -// TAPR are updated according to the configuration of this bit. -// ENUMs: -// TOUPDATE Update TAMATCHR and TAPR, if used, on the next -// time-out. -// CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next -// cycle. -#define GPT_TAMR_TAMRSU 0x00000400 -#define GPT_TAMR_TAMRSU_BITN 10 -#define GPT_TAMR_TAMRSU_M 0x00000400 -#define GPT_TAMR_TAMRSU_S 10 -#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 -#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 - -// Field: [9] TAPWMIE -// -// GPTM Timer A PWM Interrupt Enable -// This bit enables interrupts in PWM mode on rising, falling, or both edges of -// the CCP output, as defined by the CTL.TAEVENT -// In addition, when this bit is set and a capture event occurs, Timer A -// automatically generates triggers to the DMA if the trigger capability is -// enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit -// respectively. -// -// 0 Capture event interrupt is disabled. -// 1 Capture event interrupt is enabled. -// This bit is only valid in PWM mode. -// ENUMs: -// EN Interrupt is enabled. This bit is only valid in -// PWM mode. -// DIS Interrupt is disabled. -#define GPT_TAMR_TAPWMIE 0x00000200 -#define GPT_TAMR_TAPWMIE_BITN 9 -#define GPT_TAMR_TAPWMIE_M 0x00000200 -#define GPT_TAMR_TAPWMIE_S 9 -#define GPT_TAMR_TAPWMIE_EN 0x00000200 -#define GPT_TAMR_TAPWMIE_DIS 0x00000000 - -// Field: [8] TAILD -// -// GPT Timer A PWM Interval Load Write -// ENUMs: -// TOUPDATE Update the TAR register with the value in the -// TAILR register on the next timeout. If the -// prescaler is used, update the TAPS register -// with the value in the TAPR register on the next -// timeout. -// CYCLEUPDATE Update the TAR register with the value in the -// TAILR register on the next clock cycle. If the -// pre-scaler is used, update the TAPS register -// with the value in the TAPR register on the next -// clock cycle. -#define GPT_TAMR_TAILD 0x00000100 -#define GPT_TAMR_TAILD_BITN 8 -#define GPT_TAMR_TAILD_M 0x00000100 -#define GPT_TAMR_TAILD_S 8 -#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 -#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 - -// Field: [7] TASNAPS -// -// GPT Timer A Snap-Shot Mode -// ENUMs: -// EN If Timer A is configured in the periodic mode, the -// actual free-running value of Timer A is loaded -// at the time-out event into the GPT Timer A -// (TAR) register. -// DIS Snap-shot mode is disabled. -#define GPT_TAMR_TASNAPS 0x00000080 -#define GPT_TAMR_TASNAPS_BITN 7 -#define GPT_TAMR_TASNAPS_M 0x00000080 -#define GPT_TAMR_TASNAPS_S 7 -#define GPT_TAMR_TASNAPS_EN 0x00000080 -#define GPT_TAMR_TASNAPS_DIS 0x00000000 - -// Field: [6] TAWOT -// -// GPT Timer A Wait-On-Trigger -// ENUMs: -// WAIT If Timer A is enabled (CTL.TAEN = 1), Timer A does -// not begin counting until it receives a trigger -// from the timer in the previous position in the -// daisy chain. This bit must be clear for GPT -// Module 0, Timer A. This function is valid for -// one-shot, periodic, and PWM modes -// NOWAIT Timer A begins counting as soon as it is enabled. -#define GPT_TAMR_TAWOT 0x00000040 -#define GPT_TAMR_TAWOT_BITN 6 -#define GPT_TAMR_TAWOT_M 0x00000040 -#define GPT_TAMR_TAWOT_S 6 -#define GPT_TAMR_TAWOT_WAIT 0x00000040 -#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 - -// Field: [5] TAMIE -// -// GPT Timer A Match Interrupt Enable -// ENUMs: -// EN An interrupt is generated when the match value in -// TAMATCHR is reached in the one-shot and -// periodic modes. -// DIS The match interrupt is disabled for match events. -// Additionally, output triggers on match events -// are prevented. -#define GPT_TAMR_TAMIE 0x00000020 -#define GPT_TAMR_TAMIE_BITN 5 -#define GPT_TAMR_TAMIE_M 0x00000020 -#define GPT_TAMR_TAMIE_S 5 -#define GPT_TAMR_TAMIE_EN 0x00000020 -#define GPT_TAMR_TAMIE_DIS 0x00000000 - -// Field: [4] TACDIR -// -// GPT Timer A Count Direction -// ENUMs: -// UP The timer counts up. When counting up, the timer -// starts from a value of 0x0. -// DOWN The timer counts down. -#define GPT_TAMR_TACDIR 0x00000010 -#define GPT_TAMR_TACDIR_BITN 4 -#define GPT_TAMR_TACDIR_M 0x00000010 -#define GPT_TAMR_TACDIR_S 4 -#define GPT_TAMR_TACDIR_UP 0x00000010 -#define GPT_TAMR_TACDIR_DOWN 0x00000000 - -// Field: [3] TAAMS -// -// GPT Timer A Alternate Mode -// -// Note: To enable PWM mode, you must also clear TACM and then configure TAMR -// field to 0x2. -// ENUMs: -// PWM PWM mode is enabled -// CAP_COMP Capture/Compare mode is enabled. -#define GPT_TAMR_TAAMS 0x00000008 -#define GPT_TAMR_TAAMS_BITN 3 -#define GPT_TAMR_TAAMS_M 0x00000008 -#define GPT_TAMR_TAAMS_S 3 -#define GPT_TAMR_TAAMS_PWM 0x00000008 -#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 - -// Field: [2] TACM -// -// GPT Timer A Capture Mode -// ENUMs: -// EDGTIME Edge-Time mode -// EDGCNT Edge-Count mode -#define GPT_TAMR_TACM 0x00000004 -#define GPT_TAMR_TACM_BITN 2 -#define GPT_TAMR_TACM_M 0x00000004 -#define GPT_TAMR_TACM_S 2 -#define GPT_TAMR_TACM_EDGTIME 0x00000004 -#define GPT_TAMR_TACM_EDGCNT 0x00000000 - -// Field: [1:0] TAMR -// -// GPT Timer A Mode -// -// 0x0 Reserved -// 0x1 One-Shot Timer mode -// 0x2 Periodic Timer mode -// 0x3 Capture mode -// The Timer mode is based on the timer configuration defined by bits 2:0 in -// the CFG register -// ENUMs: -// CAPTURE Capture mode -// PERIODIC Periodic Timer mode -// ONE_SHOT One-Shot Timer mode -#define GPT_TAMR_TAMR_W 2 -#define GPT_TAMR_TAMR_M 0x00000003 -#define GPT_TAMR_TAMR_S 0 -#define GPT_TAMR_TAMR_CAPTURE 0x00000003 -#define GPT_TAMR_TAMR_PERIODIC 0x00000002 -#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 - -//***************************************************************************** -// -// Register: GPT_O_TBMR -// -//***************************************************************************** -// Field: [15:13] TCACT -// -// Timer Compare Action Select -// ENUMs: -// CLRSET_ON_TO Clear CCP output pin immediately and set on -// Time-Out -// SETCLR_ON_TO Set CCP output pin immediately and clear on -// Time-Out -// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on -// Time-Out -// SETTOG_ON_TO Set CCP output pin immediately and toggle on -// Time-Out -// SET_ON_TO Set CCP output pin on Time-Out -// CLR_ON_TO Clear CCP output pin on Time-Out -// TOG_ON_TO Toggle State on Time-Out -// DIS_CMP Disable compare operations -#define GPT_TBMR_TCACT_W 3 -#define GPT_TBMR_TCACT_M 0x0000E000 -#define GPT_TBMR_TCACT_S 13 -#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 -#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 -#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 -#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 -#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 -#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 -#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 -#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 - -// Field: [12] TBCINTD -// -// One-Shot/Periodic Interrupt Mode -// ENUMs: -// DIS_TO_INTR Mask Time-Out Interrupt -// EN_TO_INTR Normal Time-Out Interrupt -#define GPT_TBMR_TBCINTD 0x00001000 -#define GPT_TBMR_TBCINTD_BITN 12 -#define GPT_TBMR_TBCINTD_M 0x00001000 -#define GPT_TBMR_TBCINTD_S 12 -#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 -#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 - -// Field: [11] TBPLO -// -// GPTM Timer B PWM Legacy Operation -// -// 0 Legacy operation with CCP pin driven Low when the TBILR -// register is reloaded after the timer reaches 0. -// -// 1 CCP is driven High when the TBILR register is reloaded after the timer -// reaches 0. -// -// This bit is only valid in PWM mode. -// ENUMs: -// CCP_ON_TO CCP output pin is set to 1 on time-out -// LEGACY Legacy operation -#define GPT_TBMR_TBPLO 0x00000800 -#define GPT_TBMR_TBPLO_BITN 11 -#define GPT_TBMR_TBPLO_M 0x00000800 -#define GPT_TBMR_TBPLO_S 11 -#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 -#define GPT_TBMR_TBPLO_LEGACY 0x00000000 - -// Field: [10] TBMRSU -// -// Timer B Match Register Update mode -// -// This bit defines when the TBMATCHR and TBPR registers are updated -// -// If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR -// and TBPR are updated when the timer is enabled. -// If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR -// and TBPR are updated according to the configuration of this bit. -// ENUMs: -// TOUPDATE Update TBMATCHR and TBPR, if used, on the next -// time-out. -// CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next -// cycle. -#define GPT_TBMR_TBMRSU 0x00000400 -#define GPT_TBMR_TBMRSU_BITN 10 -#define GPT_TBMR_TBMRSU_M 0x00000400 -#define GPT_TBMR_TBMRSU_S 10 -#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 -#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 - -// Field: [9] TBPWMIE -// -// GPTM Timer B PWM Interrupt Enable -// This bit enables interrupts in PWM mode on rising, falling, or both edges of -// the CCP output, as defined by the CTL.TBEVENT -// In addition, when this bit is set and a capture event occurs, Timer A -// automatically generates triggers to the DMA if the trigger capability is -// enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit -// respectively. -// -// 0 Capture event interrupt is disabled. -// 1 Capture event interrupt is enabled. -// This bit is only valid in PWM mode. -// ENUMs: -// EN Interrupt is enabled. This bit is only valid in -// PWM mode. -// DIS Interrupt is disabled. -#define GPT_TBMR_TBPWMIE 0x00000200 -#define GPT_TBMR_TBPWMIE_BITN 9 -#define GPT_TBMR_TBPWMIE_M 0x00000200 -#define GPT_TBMR_TBPWMIE_S 9 -#define GPT_TBMR_TBPWMIE_EN 0x00000200 -#define GPT_TBMR_TBPWMIE_DIS 0x00000000 - -// Field: [8] TBILD -// -// GPT Timer B PWM Interval Load Write -// ENUMs: -// TOUPDATE Update the TBR register with the value in the -// TBILR register on the next timeout. If the -// prescaler is used, update the TBPS register -// with the value in the TBPR register on the next -// timeout. -// CYCLEUPDATE Update the TBR register with the value in the -// TBILR register on the next clock cycle. If the -// pre-scaler is used, update the TBPS register -// with the value in the TBPR register on the next -// clock cycle. -#define GPT_TBMR_TBILD 0x00000100 -#define GPT_TBMR_TBILD_BITN 8 -#define GPT_TBMR_TBILD_M 0x00000100 -#define GPT_TBMR_TBILD_S 8 -#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 -#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 - -// Field: [7] TBSNAPS -// -// GPT Timer B Snap-Shot Mode -// ENUMs: -// EN If Timer B is configured in the periodic mode -// DIS Snap-shot mode is disabled. -#define GPT_TBMR_TBSNAPS 0x00000080 -#define GPT_TBMR_TBSNAPS_BITN 7 -#define GPT_TBMR_TBSNAPS_M 0x00000080 -#define GPT_TBMR_TBSNAPS_S 7 -#define GPT_TBMR_TBSNAPS_EN 0x00000080 -#define GPT_TBMR_TBSNAPS_DIS 0x00000000 - -// Field: [6] TBWOT -// -// GPT Timer B Wait-On-Trigger -// ENUMs: -// WAIT If Timer B is enabled (CTL.TBEN is set), Timer B -// does not begin counting until it receives a -// trigger from the timer in the previous position -// in the daisy chain. This function is valid for -// one-shot, periodic, and PWM modes -// NOWAIT Timer B begins counting as soon as it is enabled. -#define GPT_TBMR_TBWOT 0x00000040 -#define GPT_TBMR_TBWOT_BITN 6 -#define GPT_TBMR_TBWOT_M 0x00000040 -#define GPT_TBMR_TBWOT_S 6 -#define GPT_TBMR_TBWOT_WAIT 0x00000040 -#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 - -// Field: [5] TBMIE -// -// GPT Timer B Match Interrupt Enable. -// ENUMs: -// EN An interrupt is generated when the match value in -// the TBMATCHR register is reached in the -// one-shot and periodic modes. -// DIS The match interrupt is disabled for match events. -// Additionally, output triggers on match events -// are prevented. -#define GPT_TBMR_TBMIE 0x00000020 -#define GPT_TBMR_TBMIE_BITN 5 -#define GPT_TBMR_TBMIE_M 0x00000020 -#define GPT_TBMR_TBMIE_S 5 -#define GPT_TBMR_TBMIE_EN 0x00000020 -#define GPT_TBMR_TBMIE_DIS 0x00000000 - -// Field: [4] TBCDIR -// -// GPT Timer B Count Direction -// ENUMs: -// UP The timer counts up. When counting up, the timer -// starts from a value of 0x0. -// DOWN The timer counts down. -#define GPT_TBMR_TBCDIR 0x00000010 -#define GPT_TBMR_TBCDIR_BITN 4 -#define GPT_TBMR_TBCDIR_M 0x00000010 -#define GPT_TBMR_TBCDIR_S 4 -#define GPT_TBMR_TBCDIR_UP 0x00000010 -#define GPT_TBMR_TBCDIR_DOWN 0x00000000 - -// Field: [3] TBAMS -// -// GPT Timer B Alternate Mode -// -// Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR -// field to 0x2. -// ENUMs: -// PWM PWM mode is enabled -// CAP_COMP Capture/Compare mode is enabled. -#define GPT_TBMR_TBAMS 0x00000008 -#define GPT_TBMR_TBAMS_BITN 3 -#define GPT_TBMR_TBAMS_M 0x00000008 -#define GPT_TBMR_TBAMS_S 3 -#define GPT_TBMR_TBAMS_PWM 0x00000008 -#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 - -// Field: [2] TBCM -// -// GPT Timer B Capture Mode -// ENUMs: -// EDGTIME Edge-Time mode -// EDGCNT Edge-Count mode -#define GPT_TBMR_TBCM 0x00000004 -#define GPT_TBMR_TBCM_BITN 2 -#define GPT_TBMR_TBCM_M 0x00000004 -#define GPT_TBMR_TBCM_S 2 -#define GPT_TBMR_TBCM_EDGTIME 0x00000004 -#define GPT_TBMR_TBCM_EDGCNT 0x00000000 - -// Field: [1:0] TBMR -// -// GPT Timer B Mode -// -// 0x0 Reserved -// 0x1 One-Shot Timer mode -// 0x2 Periodic Timer mode -// 0x3 Capture mode -// The Timer mode is based on the timer configuration defined by bits 2:0 in -// the CFG register -// ENUMs: -// CAPTURE Capture mode -// PERIODIC Periodic Timer mode -// ONE_SHOT One-Shot Timer mode -#define GPT_TBMR_TBMR_W 2 -#define GPT_TBMR_TBMR_M 0x00000003 -#define GPT_TBMR_TBMR_S 0 -#define GPT_TBMR_TBMR_CAPTURE 0x00000003 -#define GPT_TBMR_TBMR_PERIODIC 0x00000002 -#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 - -//***************************************************************************** -// -// Register: GPT_O_CTL -// -//***************************************************************************** -// Field: [14] TBPWML -// -// GPT Timer B PWM Output Level -// -// 0: Output is unaffected. -// 1: Output is inverted. -// ENUMs: -// INVERTED Inverted -// NORMAL Not inverted -#define GPT_CTL_TBPWML 0x00004000 -#define GPT_CTL_TBPWML_BITN 14 -#define GPT_CTL_TBPWML_M 0x00004000 -#define GPT_CTL_TBPWML_S 14 -#define GPT_CTL_TBPWML_INVERTED 0x00004000 -#define GPT_CTL_TBPWML_NORMAL 0x00000000 - -// Field: [11:10] TBEVENT -// -// GPT Timer B Event Mode -// -// The values in this register are defined as follows: -// Value Description -// 0x0 Positive edge -// 0x1 Negative edge -// 0x2 Reserved -// 0x3 Both edges -// Note: If PWM output inversion is enabled, edge detection interrupt -// behavior is reversed. Thus, if a positive-edge interrupt trigger -// has been set and the PWM inversion generates a postive -// edge, no event-trigger interrupt asserts. Instead, the interrupt -// is generated on the negative edge of the PWM signal. -// ENUMs: -// BOTH Both edges -// NEG Negative edge -// POS Positive edge -#define GPT_CTL_TBEVENT_W 2 -#define GPT_CTL_TBEVENT_M 0x00000C00 -#define GPT_CTL_TBEVENT_S 10 -#define GPT_CTL_TBEVENT_BOTH 0x00000C00 -#define GPT_CTL_TBEVENT_NEG 0x00000400 -#define GPT_CTL_TBEVENT_POS 0x00000000 - -// Field: [9] TBSTALL -// -// GPT Timer B Stall Enable -// ENUMs: -// EN Timer B freezes counting while the processor is -// halted by the debugger. -// DIS Timer B continues counting while the processor is -// halted by the debugger. -#define GPT_CTL_TBSTALL 0x00000200 -#define GPT_CTL_TBSTALL_BITN 9 -#define GPT_CTL_TBSTALL_M 0x00000200 -#define GPT_CTL_TBSTALL_S 9 -#define GPT_CTL_TBSTALL_EN 0x00000200 -#define GPT_CTL_TBSTALL_DIS 0x00000000 - -// Field: [8] TBEN -// -// GPT Timer B Enable -// ENUMs: -// EN Timer B is enabled and begins counting or the -// capture logic is enabled based on CFG register. -// DIS Timer B is disabled. -#define GPT_CTL_TBEN 0x00000100 -#define GPT_CTL_TBEN_BITN 8 -#define GPT_CTL_TBEN_M 0x00000100 -#define GPT_CTL_TBEN_S 8 -#define GPT_CTL_TBEN_EN 0x00000100 -#define GPT_CTL_TBEN_DIS 0x00000000 - -// Field: [6] TAPWML -// -// GPT Timer A PWM Output Level -// ENUMs: -// INVERTED Inverted -// NORMAL Not inverted -#define GPT_CTL_TAPWML 0x00000040 -#define GPT_CTL_TAPWML_BITN 6 -#define GPT_CTL_TAPWML_M 0x00000040 -#define GPT_CTL_TAPWML_S 6 -#define GPT_CTL_TAPWML_INVERTED 0x00000040 -#define GPT_CTL_TAPWML_NORMAL 0x00000000 - -// Field: [3:2] TAEVENT -// -// GPT Timer A Event Mode -// -// The values in this register are defined as follows: -// Value Description -// 0x0 Positive edge -// 0x1 Negative edge -// 0x2 Reserved -// 0x3 Both edges -// Note: If PWM output inversion is enabled, edge detection interrupt -// behavior is reversed. Thus, if a positive-edge interrupt trigger -// has been set and the PWM inversion generates a postive -// edge, no event-trigger interrupt asserts. Instead, the interrupt -// is generated on the negative edge of the PWM signal. -// ENUMs: -// BOTH Both edges -// NEG Negative edge -// POS Positive edge -#define GPT_CTL_TAEVENT_W 2 -#define GPT_CTL_TAEVENT_M 0x0000000C -#define GPT_CTL_TAEVENT_S 2 -#define GPT_CTL_TAEVENT_BOTH 0x0000000C -#define GPT_CTL_TAEVENT_NEG 0x00000004 -#define GPT_CTL_TAEVENT_POS 0x00000000 - -// Field: [1] TASTALL -// -// GPT Timer A Stall Enable -// ENUMs: -// EN Timer A freezes counting while the processor is -// halted by the debugger. -// DIS Timer A continues counting while the processor is -// halted by the debugger. -#define GPT_CTL_TASTALL 0x00000002 -#define GPT_CTL_TASTALL_BITN 1 -#define GPT_CTL_TASTALL_M 0x00000002 -#define GPT_CTL_TASTALL_S 1 -#define GPT_CTL_TASTALL_EN 0x00000002 -#define GPT_CTL_TASTALL_DIS 0x00000000 - -// Field: [0] TAEN -// -// GPT Timer A Enable -// ENUMs: -// EN Timer A is enabled and begins counting or the -// capture logic is enabled based on the CFG -// register. -// DIS Timer A is disabled. -#define GPT_CTL_TAEN 0x00000001 -#define GPT_CTL_TAEN_BITN 0 -#define GPT_CTL_TAEN_M 0x00000001 -#define GPT_CTL_TAEN_S 0 -#define GPT_CTL_TAEN_EN 0x00000001 -#define GPT_CTL_TAEN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: GPT_O_SYNC -// -//***************************************************************************** -// Field: [7:6] SYNC3 -// -// Synchronize GPT Timer 3. -// ENUMs: -// BOTH A timeout event for both Timer A and Timer B of -// GPT3 is triggered -// TIMERB A timeout event for Timer B of GPT3 is triggered -// TIMERA A timeout event for Timer A of GPT3 is triggered -// NOSYNC No Sync. GPT3 is not affected. -#define GPT_SYNC_SYNC3_W 2 -#define GPT_SYNC_SYNC3_M 0x000000C0 -#define GPT_SYNC_SYNC3_S 6 -#define GPT_SYNC_SYNC3_BOTH 0x000000C0 -#define GPT_SYNC_SYNC3_TIMERB 0x00000080 -#define GPT_SYNC_SYNC3_TIMERA 0x00000040 -#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 - -// Field: [5:4] SYNC2 -// -// Synchronize GPT Timer 2. -// ENUMs: -// BOTH A timeout event for both Timer A and Timer B of -// GPT2 is triggered -// TIMERB A timeout event for Timer B of GPT2 is triggered -// TIMERA A timeout event for Timer A of GPT2 is triggered -// NOSYNC No Sync. GPT2 is not affected. -#define GPT_SYNC_SYNC2_W 2 -#define GPT_SYNC_SYNC2_M 0x00000030 -#define GPT_SYNC_SYNC2_S 4 -#define GPT_SYNC_SYNC2_BOTH 0x00000030 -#define GPT_SYNC_SYNC2_TIMERB 0x00000020 -#define GPT_SYNC_SYNC2_TIMERA 0x00000010 -#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 - -// Field: [3:2] SYNC1 -// -// Synchronize GPT Timer 1 -// ENUMs: -// BOTH A timeout event for both Timer A and Timer B of -// GPT1 is triggered -// TIMERB A timeout event for Timer B of GPT1 is triggered -// TIMERA A timeout event for Timer A of GPT1 is triggered -// NOSYNC No Sync. GPT1 is not affected. -#define GPT_SYNC_SYNC1_W 2 -#define GPT_SYNC_SYNC1_M 0x0000000C -#define GPT_SYNC_SYNC1_S 2 -#define GPT_SYNC_SYNC1_BOTH 0x0000000C -#define GPT_SYNC_SYNC1_TIMERB 0x00000008 -#define GPT_SYNC_SYNC1_TIMERA 0x00000004 -#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 - -// Field: [1:0] SYNC0 -// -// Synchronize GPT Timer 0 -// ENUMs: -// BOTH A timeout event for both Timer A and Timer B of -// GPT0 is triggered -// TIMERB A timeout event for Timer B of GPT0 is triggered -// TIMERA A timeout event for Timer A of GPT0 is triggered -// NOSYNC No Sync. GPT0 is not affected. -#define GPT_SYNC_SYNC0_W 2 -#define GPT_SYNC_SYNC0_M 0x00000003 -#define GPT_SYNC_SYNC0_S 0 -#define GPT_SYNC_SYNC0_BOTH 0x00000003 -#define GPT_SYNC_SYNC0_TIMERB 0x00000002 -#define GPT_SYNC_SYNC0_TIMERA 0x00000001 -#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 - -//***************************************************************************** -// -// Register: GPT_O_IMR -// -//***************************************************************************** -// Field: [13] DMABIM -// -// Enabling this bit will make the RIS.DMABRIS interrupt propagate to -// MIS.DMABMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_DMABIM 0x00002000 -#define GPT_IMR_DMABIM_BITN 13 -#define GPT_IMR_DMABIM_M 0x00002000 -#define GPT_IMR_DMABIM_S 13 -#define GPT_IMR_DMABIM_EN 0x00002000 -#define GPT_IMR_DMABIM_DIS 0x00000000 - -// Field: [11] TBMIM -// -// Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_TBMIM 0x00000800 -#define GPT_IMR_TBMIM_BITN 11 -#define GPT_IMR_TBMIM_M 0x00000800 -#define GPT_IMR_TBMIM_S 11 -#define GPT_IMR_TBMIM_EN 0x00000800 -#define GPT_IMR_TBMIM_DIS 0x00000000 - -// Field: [10] CBEIM -// -// Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_CBEIM 0x00000400 -#define GPT_IMR_CBEIM_BITN 10 -#define GPT_IMR_CBEIM_M 0x00000400 -#define GPT_IMR_CBEIM_S 10 -#define GPT_IMR_CBEIM_EN 0x00000400 -#define GPT_IMR_CBEIM_DIS 0x00000000 - -// Field: [9] CBMIM -// -// Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_CBMIM 0x00000200 -#define GPT_IMR_CBMIM_BITN 9 -#define GPT_IMR_CBMIM_M 0x00000200 -#define GPT_IMR_CBMIM_S 9 -#define GPT_IMR_CBMIM_EN 0x00000200 -#define GPT_IMR_CBMIM_DIS 0x00000000 - -// Field: [8] TBTOIM -// -// Enabling this bit will make the RIS.TBTORIS interrupt propagate to -// MIS.TBTOMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_TBTOIM 0x00000100 -#define GPT_IMR_TBTOIM_BITN 8 -#define GPT_IMR_TBTOIM_M 0x00000100 -#define GPT_IMR_TBTOIM_S 8 -#define GPT_IMR_TBTOIM_EN 0x00000100 -#define GPT_IMR_TBTOIM_DIS 0x00000000 - -// Field: [5] DMAAIM -// -// Enabling this bit will make the RIS.DMAARIS interrupt propagate to -// MIS.DMAAMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_DMAAIM 0x00000020 -#define GPT_IMR_DMAAIM_BITN 5 -#define GPT_IMR_DMAAIM_M 0x00000020 -#define GPT_IMR_DMAAIM_S 5 -#define GPT_IMR_DMAAIM_EN 0x00000020 -#define GPT_IMR_DMAAIM_DIS 0x00000000 - -// Field: [4] TAMIM -// -// Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_TAMIM 0x00000010 -#define GPT_IMR_TAMIM_BITN 4 -#define GPT_IMR_TAMIM_M 0x00000010 -#define GPT_IMR_TAMIM_S 4 -#define GPT_IMR_TAMIM_EN 0x00000010 -#define GPT_IMR_TAMIM_DIS 0x00000000 - -// Field: [2] CAEIM -// -// Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_CAEIM 0x00000004 -#define GPT_IMR_CAEIM_BITN 2 -#define GPT_IMR_CAEIM_M 0x00000004 -#define GPT_IMR_CAEIM_S 2 -#define GPT_IMR_CAEIM_EN 0x00000004 -#define GPT_IMR_CAEIM_DIS 0x00000000 - -// Field: [1] CAMIM -// -// Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_CAMIM 0x00000002 -#define GPT_IMR_CAMIM_BITN 1 -#define GPT_IMR_CAMIM_M 0x00000002 -#define GPT_IMR_CAMIM_S 1 -#define GPT_IMR_CAMIM_EN 0x00000002 -#define GPT_IMR_CAMIM_DIS 0x00000000 - -// Field: [0] TATOIM -// -// Enabling this bit will make the RIS.TATORIS interrupt propagate to -// MIS.TATOMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_TATOIM 0x00000001 -#define GPT_IMR_TATOIM_BITN 0 -#define GPT_IMR_TATOIM_M 0x00000001 -#define GPT_IMR_TATOIM_S 0 -#define GPT_IMR_TATOIM_EN 0x00000001 -#define GPT_IMR_TATOIM_DIS 0x00000000 - -//***************************************************************************** -// -// Register: GPT_O_RIS -// -//***************************************************************************** -// Field: [13] DMABRIS -// -// GPT Timer B DMA Done Raw Interrupt Status -// -// 0: Transfer has not completed -// 1: Transfer has completed -#define GPT_RIS_DMABRIS 0x00002000 -#define GPT_RIS_DMABRIS_BITN 13 -#define GPT_RIS_DMABRIS_M 0x00002000 -#define GPT_RIS_DMABRIS_S 13 - -// Field: [11] TBMRIS -// -// GPT Timer B Match Raw Interrupt -// -// 0: The match value has not been reached -// 1: The match value is reached. -// -// TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR -// have been reached when configured in one-shot or periodic mode. -#define GPT_RIS_TBMRIS 0x00000800 -#define GPT_RIS_TBMRIS_BITN 11 -#define GPT_RIS_TBMRIS_M 0x00000800 -#define GPT_RIS_TBMRIS_S 11 - -// Field: [10] CBERIS -// -// GPT Timer B Capture Mode Event Raw Interrupt -// -// 0: The event has not occured. -// 1: The event has occured. -// -// This interrupt asserts when the subtimer is configured in Input Edge-Time -// mode -#define GPT_RIS_CBERIS 0x00000400 -#define GPT_RIS_CBERIS_BITN 10 -#define GPT_RIS_CBERIS_M 0x00000400 -#define GPT_RIS_CBERIS_S 10 - -// Field: [9] CBMRIS -// -// GPT Timer B Capture Mode Match Raw Interrupt -// -// 0: The capture mode match for Timer B has not occurred. -// 1: A capture mode match has occurred for Timer B. This interrupt -// asserts when the values in the TBR and TBPR -// match the values in the TBMATCHR and TBPMR -// when configured in Input Edge-Time mode. -// -// This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. -#define GPT_RIS_CBMRIS 0x00000200 -#define GPT_RIS_CBMRIS_BITN 9 -#define GPT_RIS_CBMRIS_M 0x00000200 -#define GPT_RIS_CBMRIS_S 9 - -// Field: [8] TBTORIS -// -// GPT Timer B Time-out Raw Interrupt -// -// 0: Timer B has not timed out -// 1: Timer B has timed out. -// -// This interrupt is asserted when a one-shot or periodic mode timer reaches -// its count limit. The count limit is 0 or the value loaded into TBILR, -// depending on the count direction. -#define GPT_RIS_TBTORIS 0x00000100 -#define GPT_RIS_TBTORIS_BITN 8 -#define GPT_RIS_TBTORIS_M 0x00000100 -#define GPT_RIS_TBTORIS_S 8 - -// Field: [5] DMAARIS -// -// GPT Timer A DMA Done Raw Interrupt Status -// -// 0: Transfer has not completed -// 1: Transfer has completed -#define GPT_RIS_DMAARIS 0x00000020 -#define GPT_RIS_DMAARIS_BITN 5 -#define GPT_RIS_DMAARIS_M 0x00000020 -#define GPT_RIS_DMAARIS_S 5 - -// Field: [4] TAMRIS -// -// GPT Timer A Match Raw Interrupt -// -// 0: The match value has not been reached -// 1: The match value is reached. -// -// TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR -// have been reached when configured in one-shot or periodic mode. -#define GPT_RIS_TAMRIS 0x00000010 -#define GPT_RIS_TAMRIS_BITN 4 -#define GPT_RIS_TAMRIS_M 0x00000010 -#define GPT_RIS_TAMRIS_S 4 - -// Field: [2] CAERIS -// -// GPT Timer A Capture Mode Event Raw Interrupt -// -// 0: The event has not occured. -// 1: The event has occured. -// -// This interrupt asserts when the subtimer is configured in Input Edge-Time -// mode -#define GPT_RIS_CAERIS 0x00000004 -#define GPT_RIS_CAERIS_BITN 2 -#define GPT_RIS_CAERIS_M 0x00000004 -#define GPT_RIS_CAERIS_S 2 - -// Field: [1] CAMRIS -// -// GPT Timer A Capture Mode Match Raw Interrupt -// -// 0: The capture mode match for Timer A has not occurred. -// 1: A capture mode match has occurred for Timer A. This interrupt -// asserts when the values in the TAR and TAPR -// match the values in the TAMATCHR and TAPMR -// when configured in Input Edge-Time mode. -// -// This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. -#define GPT_RIS_CAMRIS 0x00000002 -#define GPT_RIS_CAMRIS_BITN 1 -#define GPT_RIS_CAMRIS_M 0x00000002 -#define GPT_RIS_CAMRIS_S 1 - -// Field: [0] TATORIS -// -// GPT Timer A Time-out Raw Interrupt -// -// 0: Timer A has not timed out -// 1: Timer A has timed out. -// -// This interrupt is asserted when a one-shot or periodic mode timer reaches -// its count limit. The count limit is 0 or the value loaded into TAILR, -// depending on the count direction. -#define GPT_RIS_TATORIS 0x00000001 -#define GPT_RIS_TATORIS_BITN 0 -#define GPT_RIS_TATORIS_M 0x00000001 -#define GPT_RIS_TATORIS_S 0 - -//***************************************************************************** -// -// Register: GPT_O_MIS -// -//***************************************************************************** -// Field: [13] DMABMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 -#define GPT_MIS_DMABMIS 0x00002000 -#define GPT_MIS_DMABMIS_BITN 13 -#define GPT_MIS_DMABMIS_M 0x00002000 -#define GPT_MIS_DMABMIS_S 13 - -// Field: [11] TBMMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 -#define GPT_MIS_TBMMIS 0x00000800 -#define GPT_MIS_TBMMIS_BITN 11 -#define GPT_MIS_TBMMIS_M 0x00000800 -#define GPT_MIS_TBMMIS_S 11 - -// Field: [10] CBEMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 -#define GPT_MIS_CBEMIS 0x00000400 -#define GPT_MIS_CBEMIS_BITN 10 -#define GPT_MIS_CBEMIS_M 0x00000400 -#define GPT_MIS_CBEMIS_S 10 - -// Field: [9] CBMMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 -#define GPT_MIS_CBMMIS 0x00000200 -#define GPT_MIS_CBMMIS_BITN 9 -#define GPT_MIS_CBMMIS_M 0x00000200 -#define GPT_MIS_CBMMIS_S 9 - -// Field: [8] TBTOMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 -#define GPT_MIS_TBTOMIS 0x00000100 -#define GPT_MIS_TBTOMIS_BITN 8 -#define GPT_MIS_TBTOMIS_M 0x00000100 -#define GPT_MIS_TBTOMIS_S 8 - -// Field: [5] DMAAMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 -#define GPT_MIS_DMAAMIS 0x00000020 -#define GPT_MIS_DMAAMIS_BITN 5 -#define GPT_MIS_DMAAMIS_M 0x00000020 -#define GPT_MIS_DMAAMIS_S 5 - -// Field: [4] TAMMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 -#define GPT_MIS_TAMMIS 0x00000010 -#define GPT_MIS_TAMMIS_BITN 4 -#define GPT_MIS_TAMMIS_M 0x00000010 -#define GPT_MIS_TAMMIS_S 4 - -// Field: [2] CAEMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 -#define GPT_MIS_CAEMIS 0x00000004 -#define GPT_MIS_CAEMIS_BITN 2 -#define GPT_MIS_CAEMIS_M 0x00000004 -#define GPT_MIS_CAEMIS_S 2 - -// Field: [1] CAMMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 -#define GPT_MIS_CAMMIS 0x00000002 -#define GPT_MIS_CAMMIS_BITN 1 -#define GPT_MIS_CAMMIS_M 0x00000002 -#define GPT_MIS_CAMMIS_S 1 - -// Field: [0] TATOMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 -#define GPT_MIS_TATOMIS 0x00000001 -#define GPT_MIS_TATOMIS_BITN 0 -#define GPT_MIS_TATOMIS_M 0x00000001 -#define GPT_MIS_TATOMIS_S 0 - -//***************************************************************************** -// -// Register: GPT_O_ICLR -// -//***************************************************************************** -// Field: [13] DMABINT -// -// 0: Do nothing. -// 1: Clear RIS.DMABRIS and MIS.DMABMIS -#define GPT_ICLR_DMABINT 0x00002000 -#define GPT_ICLR_DMABINT_BITN 13 -#define GPT_ICLR_DMABINT_M 0x00002000 -#define GPT_ICLR_DMABINT_S 13 - -// Field: [11] TBMCINT -// -// 0: Do nothing. -// 1: Clear RIS.TBMRIS and MIS.TBMMIS -#define GPT_ICLR_TBMCINT 0x00000800 -#define GPT_ICLR_TBMCINT_BITN 11 -#define GPT_ICLR_TBMCINT_M 0x00000800 -#define GPT_ICLR_TBMCINT_S 11 - -// Field: [10] CBECINT -// -// 0: Do nothing. -// 1: Clear RIS.CBERIS and MIS.CBEMIS -#define GPT_ICLR_CBECINT 0x00000400 -#define GPT_ICLR_CBECINT_BITN 10 -#define GPT_ICLR_CBECINT_M 0x00000400 -#define GPT_ICLR_CBECINT_S 10 - -// Field: [9] CBMCINT -// -// 0: Do nothing. -// 1: Clear RIS.CBMRIS and MIS.CBMMIS -#define GPT_ICLR_CBMCINT 0x00000200 -#define GPT_ICLR_CBMCINT_BITN 9 -#define GPT_ICLR_CBMCINT_M 0x00000200 -#define GPT_ICLR_CBMCINT_S 9 - -// Field: [8] TBTOCINT -// -// 0: Do nothing. -// 1: Clear RIS.TBTORIS and MIS.TBTOMIS -#define GPT_ICLR_TBTOCINT 0x00000100 -#define GPT_ICLR_TBTOCINT_BITN 8 -#define GPT_ICLR_TBTOCINT_M 0x00000100 -#define GPT_ICLR_TBTOCINT_S 8 - -// Field: [5] DMAAINT -// -// 0: Do nothing. -// 1: Clear RIS.DMAARIS and MIS.DMAAMIS -#define GPT_ICLR_DMAAINT 0x00000020 -#define GPT_ICLR_DMAAINT_BITN 5 -#define GPT_ICLR_DMAAINT_M 0x00000020 -#define GPT_ICLR_DMAAINT_S 5 - -// Field: [4] TAMCINT -// -// 0: Do nothing. -// 1: Clear RIS.TAMRIS and MIS.TAMMIS -#define GPT_ICLR_TAMCINT 0x00000010 -#define GPT_ICLR_TAMCINT_BITN 4 -#define GPT_ICLR_TAMCINT_M 0x00000010 -#define GPT_ICLR_TAMCINT_S 4 - -// Field: [2] CAECINT -// -// 0: Do nothing. -// 1: Clear RIS.CAERIS and MIS.CAEMIS -#define GPT_ICLR_CAECINT 0x00000004 -#define GPT_ICLR_CAECINT_BITN 2 -#define GPT_ICLR_CAECINT_M 0x00000004 -#define GPT_ICLR_CAECINT_S 2 - -// Field: [1] CAMCINT -// -// 0: Do nothing. -// 1: Clear RIS.CAMRIS and MIS.CAMMIS -#define GPT_ICLR_CAMCINT 0x00000002 -#define GPT_ICLR_CAMCINT_BITN 1 -#define GPT_ICLR_CAMCINT_M 0x00000002 -#define GPT_ICLR_CAMCINT_S 1 - -// Field: [0] TATOCINT -// -// 0: Do nothing. -// 1: Clear RIS.TATORIS and MIS.TATOMIS -#define GPT_ICLR_TATOCINT 0x00000001 -#define GPT_ICLR_TATOCINT_BITN 0 -#define GPT_ICLR_TATOCINT_M 0x00000001 -#define GPT_ICLR_TATOCINT_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAILR -// -//***************************************************************************** -// Field: [31:0] TAILR -// -// GPT Timer A Interval Load Register -// -// Writing this field loads the counter for Timer A. A read returns the current -// value of TAILR. -#define GPT_TAILR_TAILR_W 32 -#define GPT_TAILR_TAILR_M 0xFFFFFFFF -#define GPT_TAILR_TAILR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBILR -// -//***************************************************************************** -// Field: [31:0] TBILR -// -// GPT Timer B Interval Load Register -// -// Writing this field loads the counter for Timer B. A read returns the current -// value of TBILR. -#define GPT_TBILR_TBILR_W 32 -#define GPT_TBILR_TBILR_M 0xFFFFFFFF -#define GPT_TBILR_TBILR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAMATCHR -// -//***************************************************************************** -// Field: [31:0] TAMATCHR -// -// GPT Timer A Match Register -#define GPT_TAMATCHR_TAMATCHR_W 32 -#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF -#define GPT_TAMATCHR_TAMATCHR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBMATCHR -// -//***************************************************************************** -// Field: [15:0] TBMATCHR -// -// GPT Timer B Match Register -#define GPT_TBMATCHR_TBMATCHR_W 16 -#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF -#define GPT_TBMATCHR_TBMATCHR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAPR -// -//***************************************************************************** -// Field: [7:0] TAPSR -// -// Timer A Pre-scale. -// -// Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: -// -// 0: Prescaler ratio = 1 -// 1: Prescaler ratio = 2 -// 2: Prescaler ratio = 3 -// ... -// 255: Prescaler ratio = 256 -#define GPT_TAPR_TAPSR_W 8 -#define GPT_TAPR_TAPSR_M 0x000000FF -#define GPT_TAPR_TAPSR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBPR -// -//***************************************************************************** -// Field: [7:0] TBPSR -// -// Timer B Pre-scale. -// -// Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: -// -// 0: Prescaler ratio = 1 -// 1: Prescaler ratio = 2 -// 2: Prescaler ratio = 3 -// ... -// 255: Prescaler ratio = 256 -#define GPT_TBPR_TBPSR_W 8 -#define GPT_TBPR_TBPSR_M 0x000000FF -#define GPT_TBPR_TBPSR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAPMR -// -//***************************************************************************** -// Field: [7:0] TAPSMR -// -// GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. -#define GPT_TAPMR_TAPSMR_W 8 -#define GPT_TAPMR_TAPSMR_M 0x000000FF -#define GPT_TAPMR_TAPSMR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBPMR -// -//***************************************************************************** -// Field: [7:0] TBPSMR -// -// GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits -// 23 to 16. -#define GPT_TBPMR_TBPSMR_W 8 -#define GPT_TBPMR_TBPSMR_M 0x000000FF -#define GPT_TBPMR_TBPSMR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAR -// -//***************************************************************************** -// Field: [31:0] TAR -// -// GPT Timer A Register -// -// Based on the value in the register field TAMR.TAILD, this register is -// updated with the value from TAILR register either on the next cycle or on -// the next timeout. -// -// A read returns the current value of the Timer A Count Register, in all cases -// except for Input Edge count and Timer modes. -// In the Input Edge Count Mode, this register contains the number of edges -// that have occurred. In the Input Edge Time mode, this register contains the -// time at which the last edge event took place. -#define GPT_TAR_TAR_W 32 -#define GPT_TAR_TAR_M 0xFFFFFFFF -#define GPT_TAR_TAR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBR -// -//***************************************************************************** -// Field: [31:0] TBR -// -// GPT Timer B Register -// -// Based on the value in the register field TBMR.TBILD, this register is -// updated with the value from TBILR register either on the next cycle or on -// the next timeout. -// -// A read returns the current value of the Timer B Count Register, in all cases -// except for Input Edge count and Timer modes. -// In the Input Edge Count Mode, this register contains the number of edges -// that have occurred. In the Input Edge Time mode, this register contains the -// time at which the last edge event took place. -#define GPT_TBR_TBR_W 32 -#define GPT_TBR_TBR_M 0xFFFFFFFF -#define GPT_TBR_TBR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAV -// -//***************************************************************************** -// Field: [31:0] TAV -// -// GPT Timer A Register -// A read returns the current, free-running value of Timer A in all modes. -// When written, the value written into this register is loaded into the -// TAR register on the next clock cycle. -// Note: In 16-bit mode, only the lower 16-bits of this -// register can be written with a new value. Writes to the prescaler bits have -// no effect -#define GPT_TAV_TAV_W 32 -#define GPT_TAV_TAV_M 0xFFFFFFFF -#define GPT_TAV_TAV_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBV -// -//***************************************************************************** -// Field: [31:0] TBV -// -// GPT Timer B Register -// A read returns the current, free-running value of Timer B in all modes. -// When written, the value written into this register is loaded into the -// TBR register on the next clock cycle. -// Note: In 16-bit mode, only the lower 16-bits of this -// register can be written with a new value. Writes to the prescaler bits have -// no effect -#define GPT_TBV_TBV_W 32 -#define GPT_TBV_TBV_M 0xFFFFFFFF -#define GPT_TBV_TBV_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAPS -// -//***************************************************************************** -// Field: [7:0] PSS -// -// GPT Timer A Pre-scaler -#define GPT_TAPS_PSS_W 8 -#define GPT_TAPS_PSS_M 0x000000FF -#define GPT_TAPS_PSS_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBPS -// -//***************************************************************************** -// Field: [7:0] PSS -// -// GPT Timer B Pre-scaler -#define GPT_TBPS_PSS_W 8 -#define GPT_TBPS_PSS_M 0x000000FF -#define GPT_TBPS_PSS_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAPV -// -//***************************************************************************** -// Field: [7:0] PSV -// -// GPT Timer A Pre-scaler Value -#define GPT_TAPV_PSV_W 8 -#define GPT_TAPV_PSV_M 0x000000FF -#define GPT_TAPV_PSV_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBPV -// -//***************************************************************************** -// Field: [7:0] PSV -// -// GPT Timer B Pre-scaler Value -#define GPT_TBPV_PSV_W 8 -#define GPT_TBPV_PSV_M 0x000000FF -#define GPT_TBPV_PSV_S 0 - -//***************************************************************************** -// -// Register: GPT_O_DMAEV -// -//***************************************************************************** -// Field: [11] TBMDMAEN -// -// GPT Timer B Match DMA Trigger Enable -#define GPT_DMAEV_TBMDMAEN 0x00000800 -#define GPT_DMAEV_TBMDMAEN_BITN 11 -#define GPT_DMAEV_TBMDMAEN_M 0x00000800 -#define GPT_DMAEV_TBMDMAEN_S 11 - -// Field: [10] CBEDMAEN -// -// GPT Timer B Capture Event DMA Trigger Enable -#define GPT_DMAEV_CBEDMAEN 0x00000400 -#define GPT_DMAEV_CBEDMAEN_BITN 10 -#define GPT_DMAEV_CBEDMAEN_M 0x00000400 -#define GPT_DMAEV_CBEDMAEN_S 10 - -// Field: [9] CBMDMAEN -// -// GPT Timer B Capture Match DMA Trigger Enable -#define GPT_DMAEV_CBMDMAEN 0x00000200 -#define GPT_DMAEV_CBMDMAEN_BITN 9 -#define GPT_DMAEV_CBMDMAEN_M 0x00000200 -#define GPT_DMAEV_CBMDMAEN_S 9 - -// Field: [8] TBTODMAEN -// -// GPT Timer B Time-Out DMA Trigger Enable -#define GPT_DMAEV_TBTODMAEN 0x00000100 -#define GPT_DMAEV_TBTODMAEN_BITN 8 -#define GPT_DMAEV_TBTODMAEN_M 0x00000100 -#define GPT_DMAEV_TBTODMAEN_S 8 - -// Field: [4] TAMDMAEN -// -// GPT Timer A Match DMA Trigger Enable -#define GPT_DMAEV_TAMDMAEN 0x00000010 -#define GPT_DMAEV_TAMDMAEN_BITN 4 -#define GPT_DMAEV_TAMDMAEN_M 0x00000010 -#define GPT_DMAEV_TAMDMAEN_S 4 - -// Field: [2] CAEDMAEN -// -// GPT Timer A Capture Event DMA Trigger Enable -#define GPT_DMAEV_CAEDMAEN 0x00000004 -#define GPT_DMAEV_CAEDMAEN_BITN 2 -#define GPT_DMAEV_CAEDMAEN_M 0x00000004 -#define GPT_DMAEV_CAEDMAEN_S 2 - -// Field: [1] CAMDMAEN -// -// GPT Timer A Capture Match DMA Trigger Enable -#define GPT_DMAEV_CAMDMAEN 0x00000002 -#define GPT_DMAEV_CAMDMAEN_BITN 1 -#define GPT_DMAEV_CAMDMAEN_M 0x00000002 -#define GPT_DMAEV_CAMDMAEN_S 1 - -// Field: [0] TATODMAEN -// -// GPT Timer A Time-Out DMA Trigger Enable -#define GPT_DMAEV_TATODMAEN 0x00000001 -#define GPT_DMAEV_TATODMAEN_BITN 0 -#define GPT_DMAEV_TATODMAEN_M 0x00000001 -#define GPT_DMAEV_TATODMAEN_S 0 - -//***************************************************************************** -// -// Register: GPT_O_VERSION -// -//***************************************************************************** -// Field: [31:0] VERSION -// -// Timer Revision. -#define GPT_VERSION_VERSION_W 32 -#define GPT_VERSION_VERSION_M 0xFFFFFFFF -#define GPT_VERSION_VERSION_S 0 - -//***************************************************************************** -// -// Register: GPT_O_ANDCCP -// -//***************************************************************************** -// Field: [0] CCP_AND_EN -// -// Enables AND operation of the CCP outputs for timers A and B. -// -// 0 : PWM outputs of Timer A and Timer B are the internal generated PWM -// signals of the respective timers. -// 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM -// signals and Timer B PWM ouput is Timer B PWM signal only. -#define GPT_ANDCCP_CCP_AND_EN 0x00000001 -#define GPT_ANDCCP_CCP_AND_EN_BITN 0 -#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 -#define GPT_ANDCCP_CCP_AND_EN_S 0 - - -#endif // __GPT__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_i2c.h b/third_party/ti/devices/cc26x0/inc/hw_i2c.h deleted file mode 100644 index 0857ae41a..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_i2c.h +++ /dev/null @@ -1,728 +0,0 @@ -/****************************************************************************** -* Filename: hw_i2c_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// I2C component -// -//***************************************************************************** -// Slave Own Address -#define I2C_O_SOAR 0x00000000 - -// Slave Status -#define I2C_O_SSTAT 0x00000004 - -// Slave Control -#define I2C_O_SCTL 0x00000004 - -// Slave Data -#define I2C_O_SDR 0x00000008 - -// Slave Interrupt Mask -#define I2C_O_SIMR 0x0000000C - -// Slave Raw Interrupt Status -#define I2C_O_SRIS 0x00000010 - -// Slave Masked Interrupt Status -#define I2C_O_SMIS 0x00000014 - -// Slave Interrupt Clear -#define I2C_O_SICR 0x00000018 - -// Master Salve Address -#define I2C_O_MSA 0x00000800 - -// Master Status -#define I2C_O_MSTAT 0x00000804 - -// Master Control -#define I2C_O_MCTRL 0x00000804 - -// Master Data -#define I2C_O_MDR 0x00000808 - -// I2C Master Timer Period -#define I2C_O_MTPR 0x0000080C - -// Master Interrupt Mask -#define I2C_O_MIMR 0x00000810 - -// Master Raw Interrupt Status -#define I2C_O_MRIS 0x00000814 - -// Master Masked Interrupt Status -#define I2C_O_MMIS 0x00000818 - -// Master Interrupt Clear -#define I2C_O_MICR 0x0000081C - -// Master Configuration -#define I2C_O_MCR 0x00000820 - -//***************************************************************************** -// -// Register: I2C_O_SOAR -// -//***************************************************************************** -// Field: [6:0] OAR -// -// I2C slave own address -// This field specifies bits a6 through a0 of the slave address. -#define I2C_SOAR_OAR_W 7 -#define I2C_SOAR_OAR_M 0x0000007F -#define I2C_SOAR_OAR_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SSTAT -// -//***************************************************************************** -// Field: [2] FBR -// -// First byte received -// -// 0: The first byte has not been received. -// 1: The first byte following the slave's own address has been received. -// -// This bit is only valid when the RREQ bit is set and is automatically cleared -// when data has been read from the SDR register. -// Note: This bit is not used for slave transmit operations. -#define I2C_SSTAT_FBR 0x00000004 -#define I2C_SSTAT_FBR_BITN 2 -#define I2C_SSTAT_FBR_M 0x00000004 -#define I2C_SSTAT_FBR_S 2 - -// Field: [1] TREQ -// -// Transmit request -// -// 0: No outstanding transmit request. -// 1: The I2C controller has been addressed as a slave transmitter and is using -// clock stretching to delay the master until data has been written to the SDR -// register. -#define I2C_SSTAT_TREQ 0x00000002 -#define I2C_SSTAT_TREQ_BITN 1 -#define I2C_SSTAT_TREQ_M 0x00000002 -#define I2C_SSTAT_TREQ_S 1 - -// Field: [0] RREQ -// -// Receive request -// -// 0: No outstanding receive data -// 1: The I2C controller has outstanding receive data from the I2C master and -// is using clock stretching to delay the master until data has been read from -// the SDR register. -#define I2C_SSTAT_RREQ 0x00000001 -#define I2C_SSTAT_RREQ_BITN 0 -#define I2C_SSTAT_RREQ_M 0x00000001 -#define I2C_SSTAT_RREQ_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SCTL -// -//***************************************************************************** -// Field: [0] DA -// -// Device active -// -// 0: Disables the I2C slave operation -// 1: Enables the I2C slave operation -#define I2C_SCTL_DA 0x00000001 -#define I2C_SCTL_DA_BITN 0 -#define I2C_SCTL_DA_M 0x00000001 -#define I2C_SCTL_DA_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SDR -// -//***************************************************************************** -// Field: [7:0] DATA -// -// Data for transfer -// This field contains the data for transfer during a slave receive or transmit -// operation. When written the register data is used as transmit data. When -// read, this register returns the last data received. -// Data is stored until next update, either by a system write for transmit or -// by an external master for receive. -#define I2C_SDR_DATA_W 8 -#define I2C_SDR_DATA_M 0x000000FF -#define I2C_SDR_DATA_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SIMR -// -//***************************************************************************** -// Field: [2] STOPIM -// -// Stop condition interrupt mask -// -// 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt -// controller. -// 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt -// controller. -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define I2C_SIMR_STOPIM 0x00000004 -#define I2C_SIMR_STOPIM_BITN 2 -#define I2C_SIMR_STOPIM_M 0x00000004 -#define I2C_SIMR_STOPIM_S 2 -#define I2C_SIMR_STOPIM_EN 0x00000004 -#define I2C_SIMR_STOPIM_DIS 0x00000000 - -// Field: [1] STARTIM -// -// Start condition interrupt mask -// -// 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt -// controller. -// 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt -// controller. -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define I2C_SIMR_STARTIM 0x00000002 -#define I2C_SIMR_STARTIM_BITN 1 -#define I2C_SIMR_STARTIM_M 0x00000002 -#define I2C_SIMR_STARTIM_S 1 -#define I2C_SIMR_STARTIM_EN 0x00000002 -#define I2C_SIMR_STARTIM_DIS 0x00000000 - -// Field: [0] DATAIM -// -// Data interrupt mask -// -// 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt -// controller. -// 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt -// controller. -#define I2C_SIMR_DATAIM 0x00000001 -#define I2C_SIMR_DATAIM_BITN 0 -#define I2C_SIMR_DATAIM_M 0x00000001 -#define I2C_SIMR_DATAIM_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SRIS -// -//***************************************************************************** -// Field: [2] STOPRIS -// -// Stop condition raw interrupt status -// -// 0: No interrupt -// 1: A Stop condition interrupt is pending. -// -// This bit is cleared by writing a 1 to SICR.STOPIC. -#define I2C_SRIS_STOPRIS 0x00000004 -#define I2C_SRIS_STOPRIS_BITN 2 -#define I2C_SRIS_STOPRIS_M 0x00000004 -#define I2C_SRIS_STOPRIS_S 2 - -// Field: [1] STARTRIS -// -// Start condition raw interrupt status -// -// 0: No interrupt -// 1: A Start condition interrupt is pending. -// -// This bit is cleared by writing a 1 to SICR.STARTIC. -#define I2C_SRIS_STARTRIS 0x00000002 -#define I2C_SRIS_STARTRIS_BITN 1 -#define I2C_SRIS_STARTRIS_M 0x00000002 -#define I2C_SRIS_STARTRIS_S 1 - -// Field: [0] DATARIS -// -// Data raw interrupt status -// -// 0: No interrupt -// 1: A data received or data requested interrupt is pending. -// -// This bit is cleared by writing a 1 to the SICR.DATAIC. -#define I2C_SRIS_DATARIS 0x00000001 -#define I2C_SRIS_DATARIS_BITN 0 -#define I2C_SRIS_DATARIS_M 0x00000001 -#define I2C_SRIS_DATARIS_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SMIS -// -//***************************************************************************** -// Field: [2] STOPMIS -// -// Stop condition masked interrupt status -// -// 0: An interrupt has not occurred or is masked/disabled. -// 1: An unmasked Stop condition interrupt is pending. -// -// This bit is cleared by writing a 1 to the SICR.STOPIC. -#define I2C_SMIS_STOPMIS 0x00000004 -#define I2C_SMIS_STOPMIS_BITN 2 -#define I2C_SMIS_STOPMIS_M 0x00000004 -#define I2C_SMIS_STOPMIS_S 2 - -// Field: [1] STARTMIS -// -// Start condition masked interrupt status -// -// 0: An interrupt has not occurred or is masked/disabled. -// 1: An unmasked Start condition interrupt is pending. -// -// This bit is cleared by writing a 1 to the SICR.STARTIC. -#define I2C_SMIS_STARTMIS 0x00000002 -#define I2C_SMIS_STARTMIS_BITN 1 -#define I2C_SMIS_STARTMIS_M 0x00000002 -#define I2C_SMIS_STARTMIS_S 1 - -// Field: [0] DATAMIS -// -// Data masked interrupt status -// -// 0: An interrupt has not occurred or is masked/disabled. -// 1: An unmasked data received or data requested interrupt is pending. -// -// This bit is cleared by writing a 1 to the SICR.DATAIC. -#define I2C_SMIS_DATAMIS 0x00000001 -#define I2C_SMIS_DATAMIS_BITN 0 -#define I2C_SMIS_DATAMIS_M 0x00000001 -#define I2C_SMIS_DATAMIS_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SICR -// -//***************************************************************************** -// Field: [2] STOPIC -// -// Stop condition interrupt clear -// -// Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. -#define I2C_SICR_STOPIC 0x00000004 -#define I2C_SICR_STOPIC_BITN 2 -#define I2C_SICR_STOPIC_M 0x00000004 -#define I2C_SICR_STOPIC_S 2 - -// Field: [1] STARTIC -// -// Start condition interrupt clear -// -// Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. -#define I2C_SICR_STARTIC 0x00000002 -#define I2C_SICR_STARTIC_BITN 1 -#define I2C_SICR_STARTIC_M 0x00000002 -#define I2C_SICR_STARTIC_S 1 - -// Field: [0] DATAIC -// -// Data interrupt clear -// -// Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. -#define I2C_SICR_DATAIC 0x00000001 -#define I2C_SICR_DATAIC_BITN 0 -#define I2C_SICR_DATAIC_M 0x00000001 -#define I2C_SICR_DATAIC_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MSA -// -//***************************************************************************** -// Field: [7:1] SA -// -// I2C master slave address -// Defines which slave is addressed for the transaction in master mode -#define I2C_MSA_SA_W 7 -#define I2C_MSA_SA_M 0x000000FE -#define I2C_MSA_SA_S 1 - -// Field: [0] RS -// -// Receive or Send -// This bit-field specifies if the next operation is a receive (high) or a -// transmit/send (low) from the addressed slave SA. -// ENUMs: -// RX Receive data from slave -// TX Transmit/send data to slave -#define I2C_MSA_RS 0x00000001 -#define I2C_MSA_RS_BITN 0 -#define I2C_MSA_RS_M 0x00000001 -#define I2C_MSA_RS_S 0 -#define I2C_MSA_RS_RX 0x00000001 -#define I2C_MSA_RS_TX 0x00000000 - -//***************************************************************************** -// -// Register: I2C_O_MSTAT -// -//***************************************************************************** -// Field: [6] BUSBSY -// -// Bus busy -// -// 0: The I2C bus is idle. -// 1: The I2C bus is busy. -// -// The bit changes based on the MCTRL.START and MCTRL.STOP conditions. -#define I2C_MSTAT_BUSBSY 0x00000040 -#define I2C_MSTAT_BUSBSY_BITN 6 -#define I2C_MSTAT_BUSBSY_M 0x00000040 -#define I2C_MSTAT_BUSBSY_S 6 - -// Field: [5] IDLE -// -// I2C idle -// -// 0: The I2C controller is not idle. -// 1: The I2C controller is idle. -#define I2C_MSTAT_IDLE 0x00000020 -#define I2C_MSTAT_IDLE_BITN 5 -#define I2C_MSTAT_IDLE_M 0x00000020 -#define I2C_MSTAT_IDLE_S 5 - -// Field: [4] ARBLST -// -// Arbitration lost -// -// 0: The I2C controller won arbitration. -// 1: The I2C controller lost arbitration. -#define I2C_MSTAT_ARBLST 0x00000010 -#define I2C_MSTAT_ARBLST_BITN 4 -#define I2C_MSTAT_ARBLST_M 0x00000010 -#define I2C_MSTAT_ARBLST_S 4 - -// Field: [3] DATACK_N -// -// Data Was Not Acknowledge -// -// 0: The transmitted data was acknowledged. -// 1: The transmitted data was not acknowledged. -#define I2C_MSTAT_DATACK_N 0x00000008 -#define I2C_MSTAT_DATACK_N_BITN 3 -#define I2C_MSTAT_DATACK_N_M 0x00000008 -#define I2C_MSTAT_DATACK_N_S 3 - -// Field: [2] ADRACK_N -// -// Address Was Not Acknowledge -// -// 0: The transmitted address was acknowledged. -// 1: The transmitted address was not acknowledged. -#define I2C_MSTAT_ADRACK_N 0x00000004 -#define I2C_MSTAT_ADRACK_N_BITN 2 -#define I2C_MSTAT_ADRACK_N_M 0x00000004 -#define I2C_MSTAT_ADRACK_N_S 2 - -// Field: [1] ERR -// -// Error -// -// 0: No error was detected on the last operation. -// 1: An error occurred on the last operation. -#define I2C_MSTAT_ERR 0x00000002 -#define I2C_MSTAT_ERR_BITN 1 -#define I2C_MSTAT_ERR_M 0x00000002 -#define I2C_MSTAT_ERR_S 1 - -// Field: [0] BUSY -// -// I2C busy -// -// 0: The controller is idle. -// 1: The controller is busy. -// -// When this bit-field is set, the other status bits are not valid. -// -// Note: The I2C controller requires four SYSBUS clock cycles to assert the -// BUSY status after I2C master operation has been initiated through MCTRL -// register. -// Hence after programming MCTRL register, application is requested to wait for -// four SYSBUS clock cycles before issuing a controller status inquiry through -// MSTAT register. -// Any prior inquiry would result in wrong status being reported. -#define I2C_MSTAT_BUSY 0x00000001 -#define I2C_MSTAT_BUSY_BITN 0 -#define I2C_MSTAT_BUSY_M 0x00000001 -#define I2C_MSTAT_BUSY_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MCTRL -// -//***************************************************************************** -// Field: [3] ACK -// -// Data acknowledge enable -// -// 0: The received data byte is not acknowledged automatically by the master. -// 1: The received data byte is acknowledged automatically by the master. -// -// This bit-field must be cleared when the I2C bus controller requires no -// further data to be transmitted from the slave transmitter. -// ENUMs: -// EN Enable acknowledge -// DIS Disable acknowledge -#define I2C_MCTRL_ACK 0x00000008 -#define I2C_MCTRL_ACK_BITN 3 -#define I2C_MCTRL_ACK_M 0x00000008 -#define I2C_MCTRL_ACK_S 3 -#define I2C_MCTRL_ACK_EN 0x00000008 -#define I2C_MCTRL_ACK_DIS 0x00000000 - -// Field: [2] STOP -// -// This bit-field determines if the cycle stops at the end of the data cycle or -// continues on to a repeated START condition. -// -// 0: The controller does not generate the Stop condition. -// 1: The controller generates the Stop condition. -// ENUMs: -// EN Enable STOP -// DIS Disable STOP -#define I2C_MCTRL_STOP 0x00000004 -#define I2C_MCTRL_STOP_BITN 2 -#define I2C_MCTRL_STOP_M 0x00000004 -#define I2C_MCTRL_STOP_S 2 -#define I2C_MCTRL_STOP_EN 0x00000004 -#define I2C_MCTRL_STOP_DIS 0x00000000 - -// Field: [1] START -// -// This bit-field generates the Start or Repeated Start condition. -// -// 0: The controller does not generate the Start condition. -// 1: The controller generates the Start condition. -// ENUMs: -// EN Enable START -// DIS Disable START -#define I2C_MCTRL_START 0x00000002 -#define I2C_MCTRL_START_BITN 1 -#define I2C_MCTRL_START_M 0x00000002 -#define I2C_MCTRL_START_S 1 -#define I2C_MCTRL_START_EN 0x00000002 -#define I2C_MCTRL_START_DIS 0x00000000 - -// Field: [0] RUN -// -// I2C master enable -// -// 0: The master is disabled. -// 1: The master is enabled to transmit or receive data. -// ENUMs: -// EN Enable Master -// DIS Disable Master -#define I2C_MCTRL_RUN 0x00000001 -#define I2C_MCTRL_RUN_BITN 0 -#define I2C_MCTRL_RUN_M 0x00000001 -#define I2C_MCTRL_RUN_S 0 -#define I2C_MCTRL_RUN_EN 0x00000001 -#define I2C_MCTRL_RUN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: I2C_O_MDR -// -//***************************************************************************** -// Field: [7:0] DATA -// -// When Read: Last RX Data is returned -// When Written: Data is transferred during TX transaction -#define I2C_MDR_DATA_W 8 -#define I2C_MDR_DATA_M 0x000000FF -#define I2C_MDR_DATA_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MTPR -// -//***************************************************************************** -// Field: [7] TPR_7 -// -// Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. -#define I2C_MTPR_TPR_7 0x00000080 -#define I2C_MTPR_TPR_7_BITN 7 -#define I2C_MTPR_TPR_7_M 0x00000080 -#define I2C_MTPR_TPR_7_S 7 - -// Field: [6:0] TPR -// -// SCL clock period -// This field specifies the period of the SCL clock. -// SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD -// where: -// SCL_PRD is the SCL line period (I2C clock). -// TPR is the timer period register value (range of 1 to 127) -// SCL_LP is the SCL low period (fixed at 6). -// SCL_HP is the SCL high period (fixed at 4). -// CLK_PRD is the system clock period in ns. -#define I2C_MTPR_TPR_W 7 -#define I2C_MTPR_TPR_M 0x0000007F -#define I2C_MTPR_TPR_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MIMR -// -//***************************************************************************** -// Field: [0] IM -// -// Interrupt mask -// -// 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt -// controller. -// 1: The master interrupt is sent to the interrupt controller when the -// MRIS.RIS is set. -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define I2C_MIMR_IM 0x00000001 -#define I2C_MIMR_IM_BITN 0 -#define I2C_MIMR_IM_M 0x00000001 -#define I2C_MIMR_IM_S 0 -#define I2C_MIMR_IM_EN 0x00000001 -#define I2C_MIMR_IM_DIS 0x00000000 - -//***************************************************************************** -// -// Register: I2C_O_MRIS -// -//***************************************************************************** -// Field: [0] RIS -// -// Raw interrupt status -// -// 0: No interrupt -// 1: A master interrupt is pending. -// -// This bit is cleared by writing 1 to the MICR.IC bit . -#define I2C_MRIS_RIS 0x00000001 -#define I2C_MRIS_RIS_BITN 0 -#define I2C_MRIS_RIS_M 0x00000001 -#define I2C_MRIS_RIS_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MMIS -// -//***************************************************************************** -// Field: [0] MIS -// -// Masked interrupt status -// -// 0: An interrupt has not occurred or is masked. -// 1: A master interrupt is pending. -// -// This bit is cleared by writing 1 to the MICR.IC bit . -#define I2C_MMIS_MIS 0x00000001 -#define I2C_MMIS_MIS_BITN 0 -#define I2C_MMIS_MIS_M 0x00000001 -#define I2C_MMIS_MIS_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MICR -// -//***************************************************************************** -// Field: [0] IC -// -// Interrupt clear -// Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . -// -// Reading this register returns no meaningful data. -#define I2C_MICR_IC 0x00000001 -#define I2C_MICR_IC_BITN 0 -#define I2C_MICR_IC_M 0x00000001 -#define I2C_MICR_IC_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MCR -// -//***************************************************************************** -// Field: [5] SFE -// -// I2C slave function enable -// ENUMs: -// EN Slave mode is enabled. -// DIS Slave mode is disabled. -#define I2C_MCR_SFE 0x00000020 -#define I2C_MCR_SFE_BITN 5 -#define I2C_MCR_SFE_M 0x00000020 -#define I2C_MCR_SFE_S 5 -#define I2C_MCR_SFE_EN 0x00000020 -#define I2C_MCR_SFE_DIS 0x00000000 - -// Field: [4] MFE -// -// I2C master function enable -// ENUMs: -// EN Master mode is enabled. -// DIS Master mode is disabled. -#define I2C_MCR_MFE 0x00000010 -#define I2C_MCR_MFE_BITN 4 -#define I2C_MCR_MFE_M 0x00000010 -#define I2C_MCR_MFE_S 4 -#define I2C_MCR_MFE_EN 0x00000010 -#define I2C_MCR_MFE_DIS 0x00000000 - -// Field: [0] LPBK -// -// I2C loopback -// -// 0: Normal operation -// 1: Loopback operation (test mode) -// ENUMs: -// EN Enable Test Mode -// DIS Disable Test Mode -#define I2C_MCR_LPBK 0x00000001 -#define I2C_MCR_LPBK_BITN 0 -#define I2C_MCR_LPBK_M 0x00000001 -#define I2C_MCR_LPBK_S 0 -#define I2C_MCR_LPBK_EN 0x00000001 -#define I2C_MCR_LPBK_DIS 0x00000000 - - -#endif // __I2C__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_i2s.h b/third_party/ti/devices/cc26x0/inc/hw_i2s.h deleted file mode 100644 index 1750b69ac..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_i2s.h +++ /dev/null @@ -1,984 +0,0 @@ -/****************************************************************************** -* Filename: hw_i2s_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_I2S_H__ -#define __HW_I2S_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// I2S component -// -//***************************************************************************** -// WCLK Source Selection -#define I2S_O_AIFWCLKSRC 0x00000000 - -// DMA Buffer Size Configuration -#define I2S_O_AIFDMACFG 0x00000004 - -// Pin Direction -#define I2S_O_AIFDIRCFG 0x00000008 - -// Serial Interface Format Configuration -#define I2S_O_AIFFMTCFG 0x0000000C - -// Word Selection Bit Mask for Pin 0 -#define I2S_O_AIFWMASK0 0x00000010 - -// Word Selection Bit Mask for Pin 1 -#define I2S_O_AIFWMASK1 0x00000014 - -// Audio Interface PWM Debug Value -#define I2S_O_AIFPWMVALUE 0x0000001C - -// DMA Input Buffer Next Pointer -#define I2S_O_AIFINPTRNEXT 0x00000020 - -// DMA Input Buffer Current Pointer -#define I2S_O_AIFINPTR 0x00000024 - -// DMA Output Buffer Next Pointer -#define I2S_O_AIFOUTPTRNEXT 0x00000028 - -// DMA Output Buffer Current Pointer -#define I2S_O_AIFOUTPTR 0x0000002C - -// Samplestamp Generator Control Register -#define I2S_O_STMPCTL 0x00000034 - -// Captured XOSC Counter Value, Capture Channel 0 -#define I2S_O_STMPXCNTCAPT0 0x00000038 - -// XOSC Period Value -#define I2S_O_STMPXPER 0x0000003C - -// Captured WCLK Counter Value, Capture Channel 0 -#define I2S_O_STMPWCNTCAPT0 0x00000040 - -// WCLK Counter Period Value -#define I2S_O_STMPWPER 0x00000044 - -// WCLK Counter Trigger Value for Input Pins -#define I2S_O_STMPINTRIG 0x00000048 - -// WCLK Counter Trigger Value for Output Pins -#define I2S_O_STMPOUTTRIG 0x0000004C - -// WCLK Counter Set Operation -#define I2S_O_STMPWSET 0x00000050 - -// WCLK Counter Add Operation -#define I2S_O_STMPWADD 0x00000054 - -// XOSC Minimum Period Value -#define I2S_O_STMPXPERMIN 0x00000058 - -// Current Value of WCNT -#define I2S_O_STMPWCNT 0x0000005C - -// Current Value of XCNT -#define I2S_O_STMPXCNT 0x00000060 - -// Internal -#define I2S_O_STMPXCNTCAPT1 0x00000064 - -// Captured WCLK Counter Value, Capture Channel 1 -#define I2S_O_STMPWCNTCAPT1 0x00000068 - -// Interrupt Mask Register -#define I2S_O_IRQMASK 0x00000070 - -// Raw Interrupt Status Register -#define I2S_O_IRQFLAGS 0x00000074 - -// Interrupt Set Register -#define I2S_O_IRQSET 0x00000078 - -// Interrupt Clear Register -#define I2S_O_IRQCLR 0x0000007C - -//***************************************************************************** -// -// Register: I2S_O_AIFWCLKSRC -// -//***************************************************************************** -// Field: [2] WCLK_INV -// -// Inverts WCLK source (pad or internal) when set. -// -// 0: Not inverted -// 1: Inverted -#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 -#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 -#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 -#define I2S_AIFWCLKSRC_WCLK_INV_S 2 - -// Field: [1:0] WCLK_SRC -// -// Selects WCLK source for AIF (should be the same as the BCLK source). The -// BCLK source is defined in the PRCM:I2SBCLKSEL.SRC -// ENUMs: -// RESERVED Not supported. Will give same WCLK as 'NONE' -// ('00') -// INT Internal WCLK generator, from module PRCM -// EXT External WCLK generator, from pad -// NONE None ('0') -#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 -#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 -#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 -#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 -#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 -#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 -#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 - -//***************************************************************************** -// -// Register: I2S_O_AIFDMACFG -// -//***************************************************************************** -// Field: [7:0] END_FRAME_IDX -// -// Defines the length of the DMA buffer. Writing a non-zero value to this -// register field enables and initializes AIF. Note that before doing so, all -// other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must -// have been loaded. -#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 -#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF -#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFDIRCFG -// -//***************************************************************************** -// Field: [9:8] AD2 -// -// Configures the AD2 audio data pin usage -// -// 0x3: Reserved -// ENUMs: -// OUT Output mode -// IN Input mode -// DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD2_W 2 -#define I2S_AIFDIRCFG_AD2_M 0x00000300 -#define I2S_AIFDIRCFG_AD2_S 8 -#define I2S_AIFDIRCFG_AD2_OUT 0x00000200 -#define I2S_AIFDIRCFG_AD2_IN 0x00000100 -#define I2S_AIFDIRCFG_AD2_DIS 0x00000000 - -// Field: [5:4] AD1 -// -// Configures the AD1 audio data pin usage: -// -// 0x3: Reserved -// ENUMs: -// OUT Output mode -// IN Input mode -// DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD1_W 2 -#define I2S_AIFDIRCFG_AD1_M 0x00000030 -#define I2S_AIFDIRCFG_AD1_S 4 -#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 -#define I2S_AIFDIRCFG_AD1_IN 0x00000010 -#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 - -// Field: [1:0] AD0 -// -// Configures the AD0 audio data pin usage: -// -// 0x3: Reserved -// ENUMs: -// OUT Output mode -// IN Input mode -// DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD0_W 2 -#define I2S_AIFDIRCFG_AD0_M 0x00000003 -#define I2S_AIFDIRCFG_AD0_S 0 -#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 -#define I2S_AIFDIRCFG_AD0_IN 0x00000001 -#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 - -//***************************************************************************** -// -// Register: I2S_O_AIFFMTCFG -// -//***************************************************************************** -// Field: [15:8] DATA_DELAY -// -// The number of BCLK periods between a WCLK edge and MSB of the first word in -// a phase: -// -// 0x00: LJF format -// 0x01: I2S and DSP format -// 0x02: RJF format -// ... -// 0xFF: RJF format -// -// Note: When 0, MSB of the next word will be output in the idle period between -// LSB of the previous word and the start of the next word. Otherwise logical 0 -// will be output until the data delay has expired. -#define I2S_AIFFMTCFG_DATA_DELAY_W 8 -#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 -#define I2S_AIFFMTCFG_DATA_DELAY_S 8 - -// Field: [7] MEM_LEN_24 -// -// The size of each word stored to or loaded from memory: -// ENUMs: -// 24BIT 24-bit (one 8 bit and one 16 bit locked access per -// sample) -// 16BIT 16-bit (one 16 bit access per sample) -#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 -#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 -#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 - -// Field: [6] SMPL_EDGE -// -// On the serial audio interface, data (and wclk) is sampled and clocked out on -// opposite edges of BCLK. -// ENUMs: -// POS Data is sampled on the positive edge and clocked -// out on the negative edge. -// NEG Data is sampled on the negative edge and clocked -// out on the positive edge. -#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 -#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 -#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 - -// Field: [5] DUAL_PHASE -// -// Selects dual- or single-phase format. -// -// 0: Single-phase: DSP format -// 1: Dual-phase: I2S, LJF and RJF formats -#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 -#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 -#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 -#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 - -// Field: [4:0] WORD_LEN -// -// Number of bits per word (8-24): -// In single-phase format, this is the exact number of bits per word. -// In dual-phase format, this is the maximum number of bits per word. -// -// Values below 8 and above 24 give undefined behavior. Data written to memory -// is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that -// differ from this alignment will either be truncated or zero padded. -#define I2S_AIFFMTCFG_WORD_LEN_W 5 -#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F -#define I2S_AIFFMTCFG_WORD_LEN_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFWMASK0 -// -//***************************************************************************** -// Field: [7:0] MASK -// -// Bit-mask indicating valid channels in a frame on AD0. -// -// In single-phase mode, each bit represents one channel, starting with LSB for -// the first word in the frame. A frame can contain up to 8 channels. Channels -// that are not included in the mask will not be sampled and stored in memory, -// and clocked out as '0'. -// -// In dual-phase mode, only the two LSBs are considered. For a stereo -// configuration, set both bits. For a mono configuration, set bit 0 only. In -// mono mode, only channel 0 will be sampled and stored to memory, and channel -// 0 will be repeated when clocked out. -// -// In mono mode, only channel 0 will be sampled and stored to memory, and -// channel 0 will be repeated in the second phase when clocked out. -// -// If all bits are zero, no input words will be stored to memory, and the -// output data lines will be constant '0'. This can be utilized when PWM debug -// output is desired without any actively used output pins. -#define I2S_AIFWMASK0_MASK_W 8 -#define I2S_AIFWMASK0_MASK_M 0x000000FF -#define I2S_AIFWMASK0_MASK_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFWMASK1 -// -//***************************************************************************** -// Field: [7:0] MASK -// -// Bit-mask indicating valid channels in a frame on AD1. -// -// In single-phase mode, each bit represents one channel, starting with LSB for -// the first word in the frame. A frame can contain up to 8 channels. Channels -// that are not included in the mask will not be sampled and stored in memory, -// and clocked out as '0'. -// -// In dual-phase mode, only the two LSBs are considered. For a stereo -// configuration, set both bits. For a mono configuration, set bit 0 only. In -// mono mode, only channel 0 will be sampled and stored to memory, and channel -// 0 will be repeated when clocked out. -// -// In mono mode, only channel 0 will be sampled and stored to memory, and -// channel 0 will be repeated in the second phase when clocked out. -// -// If all bits are zero, no input words will be stored to memory, and the -// output data lines will be constant '0'. This can be utilized when PWM debug -// output is desired without any actively used output pins. -#define I2S_AIFWMASK1_MASK_W 8 -#define I2S_AIFWMASK1_MASK_M 0x000000FF -#define I2S_AIFWMASK1_MASK_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFPWMVALUE -// -//***************************************************************************** -// Field: [15:0] PULSE_WIDTH -// -// The value written to this register determines the width of the active high -// PWM pulse (pwm_debug), which starts together with MSB of the first output -// word in a DMA buffer: -// -// 0x0000: Constant low -// 0x0001: Width of the pulse (number of BCLK cycles, here 1). -// ... -// 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). -// 0xFFFF: Constant high -#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 -#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF -#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFINPTRNEXT -// -//***************************************************************************** -// Field: [31:0] PTR -// -// Pointer to the first byte in the next DMA input buffer. -// -// The read value equals the last written value until the currently used DMA -// input buffer is completed, and then becomes null when the last written value -// is transferred to the DMA controller to start on the next buffer. This event -// is signalized by IRQFLAGS.AIF_DMA_IN. -// -// At startup, the value must be written once before and once after configuring -// the DMA buffer size in AIFDMACFG. -// -// The next pointer must be written to this register while the DMA function -// uses the previously written pointer. If not written in time, -// IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. -#define I2S_AIFINPTRNEXT_PTR_W 32 -#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF -#define I2S_AIFINPTRNEXT_PTR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFINPTR -// -//***************************************************************************** -// Field: [31:0] PTR -// -// Value of the DMA input buffer pointer currently used by the DMA controller. -// Incremented by 1 (byte) or 2 (word) for each AHB access. -#define I2S_AIFINPTR_PTR_W 32 -#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF -#define I2S_AIFINPTR_PTR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFOUTPTRNEXT -// -//***************************************************************************** -// Field: [31:0] PTR -// -// Pointer to the first byte in the next DMA output buffer. -// -// The read value equals the last written value until the currently used DMA -// output buffer is completed, and then becomes null when the last written -// value is transferred to the DMA controller to start on the next buffer. This -// event is signalized by IRQFLAGS.AIF_DMA_OUT. -// -// At startup, the value must be written once before and once after configuring -// the DMA buffer size in AIFDMACFG. At this time, the first two samples will -// be fetched from memory. -// -// The next pointer must be written to this register while the DMA function -// uses the previously written pointer. If not written in time, -// IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. -#define I2S_AIFOUTPTRNEXT_PTR_W 32 -#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF -#define I2S_AIFOUTPTRNEXT_PTR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFOUTPTR -// -//***************************************************************************** -// Field: [31:0] PTR -// -// Value of the DMA output buffer pointer currently used by the DMA controller -// Incremented by 1 (byte) or 2 (word) for each AHB access. -#define I2S_AIFOUTPTR_PTR_W 32 -#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF -#define I2S_AIFOUTPTR_PTR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPCTL -// -//***************************************************************************** -// Field: [2] OUT_RDY -// -// Low until the output pins are ready to be started by the samplestamp -// generator. When started (that is STMPOUTTRIG equals the WCLK counter) the -// bit goes back low. -#define I2S_STMPCTL_OUT_RDY 0x00000004 -#define I2S_STMPCTL_OUT_RDY_BITN 2 -#define I2S_STMPCTL_OUT_RDY_M 0x00000004 -#define I2S_STMPCTL_OUT_RDY_S 2 - -// Field: [1] IN_RDY -// -// Low until the input pins are ready to be started by the samplestamp -// generator. When started (that is STMPINTRIG equals the WCLK counter) the bit -// goes back low. -#define I2S_STMPCTL_IN_RDY 0x00000002 -#define I2S_STMPCTL_IN_RDY_BITN 1 -#define I2S_STMPCTL_IN_RDY_M 0x00000002 -#define I2S_STMPCTL_IN_RDY_S 1 - -// Field: [0] STMP_EN -// -// Enables the samplestamp generator. The samplestamp generator must only be -// enabled after it has been properly configured. -// When cleared, all samplestamp generator counters and capture values are -// cleared. -#define I2S_STMPCTL_STMP_EN 0x00000001 -#define I2S_STMPCTL_STMP_EN_BITN 0 -#define I2S_STMPCTL_STMP_EN_M 0x00000001 -#define I2S_STMPCTL_STMP_EN_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPXCNTCAPT0 -// -//***************************************************************************** -// Field: [15:0] CAPT_VALUE -// -// The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an -// event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for -// channel 0). This number corresponds to the number of 24 MHz clock cycles -// since the last positive edge of the selected WCLK. -// The value is cleared when STMPCTL.STMP_EN = 0. -// Note: Due to buffering and synchronization, WCLK is delayed by a small -// number of BCLK periods and clk periods. -// Note: When calculating the fractional part of the sample stamp, STMPXPER may -// be less than this bit field. -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPXPER -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// The number of 24 MHz clock cycles in the previous WCLK period (that is - -// the next value of the XOSC counter at the positive WCLK edge, had it not -// been reset to 0). -// The value is cleared when STMPCTL.STMP_EN = 0. -#define I2S_STMPXPER_VALUE_W 16 -#define I2S_STMPXPER_VALUE_M 0x0000FFFF -#define I2S_STMPXPER_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWCNTCAPT0 -// -//***************************************************************************** -// Field: [15:0] CAPT_VALUE -// -// The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an -// event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel -// 0). This number corresponds to the number of positive WCLK edges since the -// samplestamp generator was enabled (not taking modification through -// STMPWADD/STMPWSET into account). -// The value is cleared when STMPCTL.STMP_EN = 0. -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWPER -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Used to define when STMPWCNT is to be reset so number of WCLK edges are -// found for the size of the sample buffer. This is thus a modulo value for the -// WCLK counter. This number must correspond to the size of the sample buffer -// used by the system (that is the index of the last sample plus 1). -#define I2S_STMPWPER_VALUE_W 16 -#define I2S_STMPWPER_VALUE_M 0x0000FFFF -#define I2S_STMPWPER_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPINTRIG -// -//***************************************************************************** -// Field: [15:0] IN_START_WCNT -// -// Compare value used to start the incoming audio streams. -// This bit field shall equal the WCLK counter value during the WCLK period in -// which the first input word(s) are sampled and stored to memory (that is the -// sample at the start of the very first DMA input buffer). -// -// The value of this register takes effect when the following conditions are -// met: -// - One or more pins are configured as inputs in AIFDIRCFG. -// - AIFDMACFG has been configured for the correct buffer size, and at least 32 -// BCLK cycle ticks have happened. -// -// Note: To avoid false triggers, this bit field should be set higher than -// STMPWPER.VALUE. -#define I2S_STMPINTRIG_IN_START_WCNT_W 16 -#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF -#define I2S_STMPINTRIG_IN_START_WCNT_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPOUTTRIG -// -//***************************************************************************** -// Field: [15:0] OUT_START_WCNT -// -// Compare value used to start the outgoing audio streams. -// -// This bit field must equal the WCLK counter value during the WCLK period in -// which the first output word(s) read from memory are clocked out (that is the -// sample at the start of the very first DMA output buffer). -// -// The value of this register takes effect when the following conditions are -// met: -// - One or more pins are configured as outputs in AIFDIRCFG. -// - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK -// cycle ticks have happened. -// - 2 samples have been preloaded from memory (examine the AIFOUTPTR register -// if necessary). -// Note: The memory read access is only performed when required, that is -// channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. -// -// Note: To avoid false triggers, this bit field should be set higher than -// STMPWPER.VALUE. -#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 -#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF -#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWSET -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// WCLK counter modification: Sets the running WCLK counter equal to the -// written value. -#define I2S_STMPWSET_VALUE_W 16 -#define I2S_STMPWSET_VALUE_M 0x0000FFFF -#define I2S_STMPWSET_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWADD -// -//***************************************************************************** -// Field: [15:0] VALUE_INC -// -// WCLK counter modification: Adds the written value to the running WCLK -// counter. If a positive edge of WCLK occurs at the same time as the -// operation, this will be taken into account. -// To add a negative value, write "STMPWPER.VALUE - value". -// -#define I2S_STMPWADD_VALUE_INC_W 16 -#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF -#define I2S_STMPWADD_VALUE_INC_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPXPERMIN -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Each time STMPXPER is updated, the value is also loaded into this register, -// provided that the value is smaller than the current value in this register. -// When written, the register is reset to 0xFFFF (65535), regardless of the -// value written. -// The minimum value can be used to detect extra WCLK pulses (this registers -// value will be significantly smaller than STMPXPER.VALUE). -#define I2S_STMPXPERMIN_VALUE_W 16 -#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF -#define I2S_STMPXPERMIN_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWCNT -// -//***************************************************************************** -// Field: [15:0] CURR_VALUE -// -// Current value of the WCLK counter -#define I2S_STMPWCNT_CURR_VALUE_W 16 -#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF -#define I2S_STMPWCNT_CURR_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPXCNT -// -//***************************************************************************** -// Field: [15:0] CURR_VALUE -// -// Current value of the XOSC counter, latched when reading STMPWCNT. -#define I2S_STMPXCNT_CURR_VALUE_W 16 -#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF -#define I2S_STMPXCNT_CURR_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPXCNTCAPT1 -// -//***************************************************************************** -// Field: [15:0] CAPT_VALUE -// -// Internal. Only to be used through TI provided API. -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWCNTCAPT1 -// -//***************************************************************************** -// Field: [15:0] CAPT_VALUE -// -// Channel 1 is idle and can not be sampled from an external event as with -// Channel 0 STMPWCNTCAPT0 -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_IRQMASK -// -//***************************************************************************** -// Field: [5] AIF_DMA_IN -// -// IRQFLAGS.AIF_DMA_IN interrupt mask -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 -#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 -#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQMASK_AIF_DMA_IN_S 5 - -// Field: [4] AIF_DMA_OUT -// -// IRQFLAGS.AIF_DMA_OUT interrupt mask -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 -#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 -#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQMASK_AIF_DMA_OUT_S 4 - -// Field: [3] WCLK_TIMEOUT -// -// IRQFLAGS.WCLK_TIMEOUT interrupt mask -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 - -// Field: [2] BUS_ERR -// -// IRQFLAGS.BUS_ERR interrupt mask -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_BUS_ERR 0x00000004 -#define I2S_IRQMASK_BUS_ERR_BITN 2 -#define I2S_IRQMASK_BUS_ERR_M 0x00000004 -#define I2S_IRQMASK_BUS_ERR_S 2 - -// Field: [1] WCLK_ERR -// -// IRQFLAGS.WCLK_ERR interrupt mask -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_WCLK_ERR 0x00000002 -#define I2S_IRQMASK_WCLK_ERR_BITN 1 -#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 -#define I2S_IRQMASK_WCLK_ERR_S 1 - -// Field: [0] PTR_ERR -// -// IRQFLAGS.PTR_ERR interrupt mask. -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_PTR_ERR 0x00000001 -#define I2S_IRQMASK_PTR_ERR_BITN 0 -#define I2S_IRQMASK_PTR_ERR_M 0x00000001 -#define I2S_IRQMASK_PTR_ERR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_IRQFLAGS -// -//***************************************************************************** -// Field: [5] AIF_DMA_IN -// -// Set when condition for this bit field event occurs (auto cleared when input -// pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register -// for details. -#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 -#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 -#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 - -// Field: [4] AIF_DMA_OUT -// -// Set when condition for this bit field event occurs (auto cleared when output -// pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT -// register for details -#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 -#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 -#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 - -// Field: [3] WCLK_TIMEOUT -// -// Set when the sample stamp generator does not detect a positive WCLK edge for -// 65535 clk periods. This signalizes that the internal or external BCLK and -// WCLK generator source has been disabled. -// -// The bit is sticky and may only be cleared by software (by writing '1' to -// IRQCLR.WCLK_TIMEOUT). -#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 - -// Field: [2] BUS_ERR -// -// Set when a DMA operation is not completed in time (that is audio output -// buffer underflow, or audio input buffer overflow). -// This error requires a complete restart since word synchronization has been -// lost. The bit is sticky and may only be cleared by software (by writing '1' -// to IRQCLR.BUS_ERR). -// -// Note that DMA initiated transactions to illegal addresses will not trigger -// an interrupt. The response to such transactions is undefined. -#define I2S_IRQFLAGS_BUS_ERR 0x00000004 -#define I2S_IRQFLAGS_BUS_ERR_BITN 2 -#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 -#define I2S_IRQFLAGS_BUS_ERR_S 2 - -// Field: [1] WCLK_ERR -// -// Set when: -// - An unexpected WCLK edge occurs during the data delay period of a phase. -// Note unexpected WCLK edges during the word and idle periods of the phase are -// not detected. -// - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles -// apart. -// - In single-phase mode, when a WCLK pulse occurs before the last channel. -// This error requires a complete restart since word synchronization has been -// lost. The bit is sticky and may only be cleared by software (by writing '1' -// to IRQCLR.WCLK_ERR). -#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 -#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 -#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 -#define I2S_IRQFLAGS_WCLK_ERR_S 1 - -// Field: [0] PTR_ERR -// -// Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next -// block address in time. -// This error requires a complete restart since word synchronization has been -// lost. The bit is sticky and may only be cleared by software (by writing '1' -// to IRQCLR.PTR_ERR). -#define I2S_IRQFLAGS_PTR_ERR 0x00000001 -#define I2S_IRQFLAGS_PTR_ERR_BITN 0 -#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 -#define I2S_IRQFLAGS_PTR_ERR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_IRQSET -// -//***************************************************************************** -// Field: [5] AIF_DMA_IN -// -// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria -// was given at the same time, in which the set will be ignored) -#define I2S_IRQSET_AIF_DMA_IN 0x00000020 -#define I2S_IRQSET_AIF_DMA_IN_BITN 5 -#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQSET_AIF_DMA_IN_S 5 - -// Field: [4] AIF_DMA_OUT -// -// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria -// was given at the same time, in which the set will be ignored) -#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 -#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 -#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQSET_AIF_DMA_OUT_S 4 - -// Field: [3] WCLK_TIMEOUT -// -// 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT -#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQSET_WCLK_TIMEOUT_S 3 - -// Field: [2] BUS_ERR -// -// 1: Sets the interrupt of IRQFLAGS.BUS_ERR -#define I2S_IRQSET_BUS_ERR 0x00000004 -#define I2S_IRQSET_BUS_ERR_BITN 2 -#define I2S_IRQSET_BUS_ERR_M 0x00000004 -#define I2S_IRQSET_BUS_ERR_S 2 - -// Field: [1] WCLK_ERR -// -// 1: Sets the interrupt of IRQFLAGS.WCLK_ERR -#define I2S_IRQSET_WCLK_ERR 0x00000002 -#define I2S_IRQSET_WCLK_ERR_BITN 1 -#define I2S_IRQSET_WCLK_ERR_M 0x00000002 -#define I2S_IRQSET_WCLK_ERR_S 1 - -// Field: [0] PTR_ERR -// -// 1: Sets the interrupt of IRQFLAGS.PTR_ERR -#define I2S_IRQSET_PTR_ERR 0x00000001 -#define I2S_IRQSET_PTR_ERR_BITN 0 -#define I2S_IRQSET_PTR_ERR_M 0x00000001 -#define I2S_IRQSET_PTR_ERR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_IRQCLR -// -//***************************************************************************** -// Field: [5] AIF_DMA_IN -// -// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was -// given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 -#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 -#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQCLR_AIF_DMA_IN_S 5 - -// Field: [4] AIF_DMA_OUT -// -// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was -// given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 -#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 -#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQCLR_AIF_DMA_OUT_S 4 - -// Field: [3] WCLK_TIMEOUT -// -// 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was -// given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 - -// Field: [2] BUS_ERR -// -// 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given -// at the same time in which the clear will be ignored) -#define I2S_IRQCLR_BUS_ERR 0x00000004 -#define I2S_IRQCLR_BUS_ERR_BITN 2 -#define I2S_IRQCLR_BUS_ERR_M 0x00000004 -#define I2S_IRQCLR_BUS_ERR_S 2 - -// Field: [1] WCLK_ERR -// -// 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was -// given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_WCLK_ERR 0x00000002 -#define I2S_IRQCLR_WCLK_ERR_BITN 1 -#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 -#define I2S_IRQCLR_WCLK_ERR_S 1 - -// Field: [0] PTR_ERR -// -// 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given -// at the same time in which the clear will be ignored) -#define I2S_IRQCLR_PTR_ERR 0x00000001 -#define I2S_IRQCLR_PTR_ERR_BITN 0 -#define I2S_IRQCLR_PTR_ERR_M 0x00000001 -#define I2S_IRQCLR_PTR_ERR_S 0 - - -#endif // __I2S__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_ints.h b/third_party/ti/devices/cc26x0/inc/hw_ints.h deleted file mode 100644 index e693e57a5..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_ints.h +++ /dev/null @@ -1,113 +0,0 @@ -/****************************************************************************** -* Filename: hw_ints_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following are defines for the interrupt assignments. -// -//***************************************************************************** -#define INT_NMI_FAULT 2 // NMI Fault -#define INT_HARD_FAULT 3 // Hard Fault -#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) - // Fault -#define INT_BUS_FAULT 5 // Bus Fault -#define INT_USAGE_FAULT 6 // Usage Fault -#define INT_SVCALL 11 // Supervisor Call (SVCall) -#define INT_DEBUG 12 // Debug Monitor -#define INT_PENDSV 14 // Pending Service Call (PendSV) -#define INT_SYSTICK 15 // SysTick Interrupt from the - // System Timer in NVIC. -#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC -#define INT_I2C_IRQ 17 // Interrupt event from I2C -#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE - // Generated events -#define INT_AON_RTC_COMB 20 // Event from AON_RTC -#define INT_UART0_COMB 21 // UART0 combined interrupt -#define INT_AUX_SWEV0 22 // AUX software event 0 -#define INT_SSI0_COMB 23 // SSI0 combined interrupt -#define INT_SSI1_COMB 24 // SSI1 combined interrupt -#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE - // Generated events -#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt -#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command - // Acknowledgement Interrupt -#define INT_I2S_IRQ 28 // Interrupt event from I2S -#define INT_AUX_SWEV1 29 // AUX software event 1 -#define INT_WDT_IRQ 30 // Watchdog interrupt event -#define INT_GPT0A 31 // GPT0A interrupt event -#define INT_GPT0B 32 // GPT0B interrupt event -#define INT_GPT1A 33 // GPT1A interrupt event -#define INT_GPT1B 34 // GPT1B interrupt event -#define INT_GPT2A 35 // GPT2A interrupt event -#define INT_GPT2B 36 // GPT2B interrupt event -#define INT_GPT3A 37 // GPT3A interrupt event -#define INT_GPT3B 38 // GPT3B interrupt event -#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt - // event -#define INT_DMA_DONE_COMB 40 // Combined DMA done -#define INT_DMA_ERR 41 // DMA bus error -#define INT_FLASH 42 // FLASH controller error event -#define INT_SWEV0 43 // Software event 0 -#define INT_AUX_COMB 44 // AUX combined event -#define INT_AON_PROG0 45 // AON programmable event 0 -#define INT_PROG0 46 // Programmable Interrupt 0 -#define INT_AUX_COMPA 47 // AUX Compare A event -#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event -#define INT_TRNG_IRQ 49 // TRNG Interrupt event - -//***************************************************************************** -// -// The following are defines for number of interrupts and priority levels. -// -//***************************************************************************** -#define NUM_INTERRUPTS 50 // Number of interrupts -#define NUM_PRIORITY_BITS 3 // Number of Priority bits -#define NUM_PRIORITY 8 // Number of priority levels - - -//***************************************************************************** -// -// Aliases for backwards compatibility with Sensor Controller Studio 1.1.0 -// -//***************************************************************************** - -#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 -#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 - -#endif diff --git a/third_party/ti/devices/cc26x0/inc/hw_ioc.h b/third_party/ti/devices/cc26x0/inc/hw_ioc.h deleted file mode 100644 index 05a99ac0e..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_ioc.h +++ /dev/null @@ -1,9839 +0,0 @@ -/****************************************************************************** -* Filename: hw_ioc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_IOC_H__ -#define __HW_IOC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// IOC component -// -//***************************************************************************** -// Configuration of DIO0 -#define IOC_O_IOCFG0 0x00000000 - -// Configuration of DIO1 -#define IOC_O_IOCFG1 0x00000004 - -// Configuration of DIO2 -#define IOC_O_IOCFG2 0x00000008 - -// Configuration of DIO3 -#define IOC_O_IOCFG3 0x0000000C - -// Configuration of DIO4 -#define IOC_O_IOCFG4 0x00000010 - -// Configuration of DIO5 -#define IOC_O_IOCFG5 0x00000014 - -// Configuration of DIO6 -#define IOC_O_IOCFG6 0x00000018 - -// Configuration of DIO7 -#define IOC_O_IOCFG7 0x0000001C - -// Configuration of DIO8 -#define IOC_O_IOCFG8 0x00000020 - -// Configuration of DIO9 -#define IOC_O_IOCFG9 0x00000024 - -// Configuration of DIO10 -#define IOC_O_IOCFG10 0x00000028 - -// Configuration of DIO11 -#define IOC_O_IOCFG11 0x0000002C - -// Configuration of DIO12 -#define IOC_O_IOCFG12 0x00000030 - -// Configuration of DIO13 -#define IOC_O_IOCFG13 0x00000034 - -// Configuration of DIO14 -#define IOC_O_IOCFG14 0x00000038 - -// Configuration of DIO15 -#define IOC_O_IOCFG15 0x0000003C - -// Configuration of DIO16 -#define IOC_O_IOCFG16 0x00000040 - -// Configuration of DIO17 -#define IOC_O_IOCFG17 0x00000044 - -// Configuration of DIO18 -#define IOC_O_IOCFG18 0x00000048 - -// Configuration of DIO19 -#define IOC_O_IOCFG19 0x0000004C - -// Configuration of DIO20 -#define IOC_O_IOCFG20 0x00000050 - -// Configuration of DIO21 -#define IOC_O_IOCFG21 0x00000054 - -// Configuration of DIO22 -#define IOC_O_IOCFG22 0x00000058 - -// Configuration of DIO23 -#define IOC_O_IOCFG23 0x0000005C - -// Configuration of DIO24 -#define IOC_O_IOCFG24 0x00000060 - -// Configuration of DIO25 -#define IOC_O_IOCFG25 0x00000064 - -// Configuration of DIO26 -#define IOC_O_IOCFG26 0x00000068 - -// Configuration of DIO27 -#define IOC_O_IOCFG27 0x0000006C - -// Configuration of DIO28 -#define IOC_O_IOCFG28 0x00000070 - -// Configuration of DIO29 -#define IOC_O_IOCFG29 0x00000074 - -// Configuration of DIO30 -#define IOC_O_IOCFG30 0x00000078 - -// Configuration of DIO31 -#define IOC_O_IOCFG31 0x0000007C - -//***************************************************************************** -// -// Register: IOC_O_IOCFG0 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG0_HYST_EN 0x40000000 -#define IOC_IOCFG0_HYST_EN_BITN 30 -#define IOC_IOCFG0_HYST_EN_M 0x40000000 -#define IOC_IOCFG0_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG0_IE 0x20000000 -#define IOC_IOCFG0_IE_BITN 29 -#define IOC_IOCFG0_IE_M 0x20000000 -#define IOC_IOCFG0_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG0_WU_CFG_W 2 -#define IOC_IOCFG0_WU_CFG_M 0x18000000 -#define IOC_IOCFG0_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input/output -// OPENSRC Open Source -// Normal input / outut -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG0_IOMODE_W 3 -#define IOC_IOCFG0_IOMODE_M 0x07000000 -#define IOC_IOCFG0_IOMODE_S 24 -#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG0_IOMODE_INV 0x01000000 -#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG0_EDGE_DET_W 2 -#define IOC_IOCFG0_EDGE_DET_M 0x00030000 -#define IOC_IOCFG0_EDGE_DET_S 16 -#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG0_PULL_CTL_W 2 -#define IOC_IOCFG0_PULL_CTL_M 0x00006000 -#define IOC_IOCFG0_PULL_CTL_S 13 -#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG0_SLEW_RED 0x00001000 -#define IOC_IOCFG0_SLEW_RED_BITN 12 -#define IOC_IOCFG0_SLEW_RED_M 0x00001000 -#define IOC_IOCFG0_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG0_IOCURR_W 2 -#define IOC_IOCFG0_IOCURR_M 0x00000C00 -#define IOC_IOCFG0_IOCURR_S 10 -#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG0_IOCURR_4MA 0x00000400 -#define IOC_IOCFG0_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG0_IOSTR_W 2 -#define IOC_IOCFG0_IOSTR_M 0x00000300 -#define IOC_IOCFG0_IOSTR_S 8 -#define IOC_IOCFG0_IOSTR_MAX 0x00000300 -#define IOC_IOCFG0_IOSTR_MED 0x00000200 -#define IOC_IOCFG0_IOSTR_MIN 0x00000100 -#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO0 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG0_PORT_ID_W 6 -#define IOC_IOCFG0_PORT_ID_M 0x0000003F -#define IOC_IOCFG0_PORT_ID_S 0 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG1 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG1_HYST_EN 0x40000000 -#define IOC_IOCFG1_HYST_EN_BITN 30 -#define IOC_IOCFG1_HYST_EN_M 0x40000000 -#define IOC_IOCFG1_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG1_IE 0x20000000 -#define IOC_IOCFG1_IE_BITN 29 -#define IOC_IOCFG1_IE_M 0x20000000 -#define IOC_IOCFG1_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG1_WU_CFG_W 2 -#define IOC_IOCFG1_WU_CFG_M 0x18000000 -#define IOC_IOCFG1_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG1_IOMODE_W 3 -#define IOC_IOCFG1_IOMODE_M 0x07000000 -#define IOC_IOCFG1_IOMODE_S 24 -#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG1_IOMODE_INV 0x01000000 -#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG1_EDGE_DET_W 2 -#define IOC_IOCFG1_EDGE_DET_M 0x00030000 -#define IOC_IOCFG1_EDGE_DET_S 16 -#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG1_PULL_CTL_W 2 -#define IOC_IOCFG1_PULL_CTL_M 0x00006000 -#define IOC_IOCFG1_PULL_CTL_S 13 -#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG1_SLEW_RED 0x00001000 -#define IOC_IOCFG1_SLEW_RED_BITN 12 -#define IOC_IOCFG1_SLEW_RED_M 0x00001000 -#define IOC_IOCFG1_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG1_IOCURR_W 2 -#define IOC_IOCFG1_IOCURR_M 0x00000C00 -#define IOC_IOCFG1_IOCURR_S 10 -#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG1_IOCURR_4MA 0x00000400 -#define IOC_IOCFG1_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG1_IOSTR_W 2 -#define IOC_IOCFG1_IOSTR_M 0x00000300 -#define IOC_IOCFG1_IOSTR_S 8 -#define IOC_IOCFG1_IOSTR_MAX 0x00000300 -#define IOC_IOCFG1_IOSTR_MED 0x00000200 -#define IOC_IOCFG1_IOSTR_MIN 0x00000100 -#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO1 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG1_PORT_ID_W 6 -#define IOC_IOCFG1_PORT_ID_M 0x0000003F -#define IOC_IOCFG1_PORT_ID_S 0 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG2 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG2_HYST_EN 0x40000000 -#define IOC_IOCFG2_HYST_EN_BITN 30 -#define IOC_IOCFG2_HYST_EN_M 0x40000000 -#define IOC_IOCFG2_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG2_IE 0x20000000 -#define IOC_IOCFG2_IE_BITN 29 -#define IOC_IOCFG2_IE_M 0x20000000 -#define IOC_IOCFG2_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG2_WU_CFG_W 2 -#define IOC_IOCFG2_WU_CFG_M 0x18000000 -#define IOC_IOCFG2_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG2_IOMODE_W 3 -#define IOC_IOCFG2_IOMODE_M 0x07000000 -#define IOC_IOCFG2_IOMODE_S 24 -#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG2_IOMODE_INV 0x01000000 -#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG2_EDGE_DET_W 2 -#define IOC_IOCFG2_EDGE_DET_M 0x00030000 -#define IOC_IOCFG2_EDGE_DET_S 16 -#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG2_PULL_CTL_W 2 -#define IOC_IOCFG2_PULL_CTL_M 0x00006000 -#define IOC_IOCFG2_PULL_CTL_S 13 -#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG2_SLEW_RED 0x00001000 -#define IOC_IOCFG2_SLEW_RED_BITN 12 -#define IOC_IOCFG2_SLEW_RED_M 0x00001000 -#define IOC_IOCFG2_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG2_IOCURR_W 2 -#define IOC_IOCFG2_IOCURR_M 0x00000C00 -#define IOC_IOCFG2_IOCURR_S 10 -#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG2_IOCURR_4MA 0x00000400 -#define IOC_IOCFG2_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG2_IOSTR_W 2 -#define IOC_IOCFG2_IOSTR_M 0x00000300 -#define IOC_IOCFG2_IOSTR_S 8 -#define IOC_IOCFG2_IOSTR_MAX 0x00000300 -#define IOC_IOCFG2_IOSTR_MED 0x00000200 -#define IOC_IOCFG2_IOSTR_MIN 0x00000100 -#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO2 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG2_PORT_ID_W 6 -#define IOC_IOCFG2_PORT_ID_M 0x0000003F -#define IOC_IOCFG2_PORT_ID_S 0 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG3 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG3_HYST_EN 0x40000000 -#define IOC_IOCFG3_HYST_EN_BITN 30 -#define IOC_IOCFG3_HYST_EN_M 0x40000000 -#define IOC_IOCFG3_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG3_IE 0x20000000 -#define IOC_IOCFG3_IE_BITN 29 -#define IOC_IOCFG3_IE_M 0x20000000 -#define IOC_IOCFG3_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG3_WU_CFG_W 2 -#define IOC_IOCFG3_WU_CFG_M 0x18000000 -#define IOC_IOCFG3_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG3_IOMODE_W 3 -#define IOC_IOCFG3_IOMODE_M 0x07000000 -#define IOC_IOCFG3_IOMODE_S 24 -#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG3_IOMODE_INV 0x01000000 -#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG3_EDGE_DET_W 2 -#define IOC_IOCFG3_EDGE_DET_M 0x00030000 -#define IOC_IOCFG3_EDGE_DET_S 16 -#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG3_PULL_CTL_W 2 -#define IOC_IOCFG3_PULL_CTL_M 0x00006000 -#define IOC_IOCFG3_PULL_CTL_S 13 -#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG3_SLEW_RED 0x00001000 -#define IOC_IOCFG3_SLEW_RED_BITN 12 -#define IOC_IOCFG3_SLEW_RED_M 0x00001000 -#define IOC_IOCFG3_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG3_IOCURR_W 2 -#define IOC_IOCFG3_IOCURR_M 0x00000C00 -#define IOC_IOCFG3_IOCURR_S 10 -#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG3_IOCURR_4MA 0x00000400 -#define IOC_IOCFG3_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG3_IOSTR_W 2 -#define IOC_IOCFG3_IOSTR_M 0x00000300 -#define IOC_IOCFG3_IOSTR_S 8 -#define IOC_IOCFG3_IOSTR_MAX 0x00000300 -#define IOC_IOCFG3_IOSTR_MED 0x00000200 -#define IOC_IOCFG3_IOSTR_MIN 0x00000100 -#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO3 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG3_PORT_ID_W 6 -#define IOC_IOCFG3_PORT_ID_M 0x0000003F -#define IOC_IOCFG3_PORT_ID_S 0 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG4 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG4_HYST_EN 0x40000000 -#define IOC_IOCFG4_HYST_EN_BITN 30 -#define IOC_IOCFG4_HYST_EN_M 0x40000000 -#define IOC_IOCFG4_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG4_IE 0x20000000 -#define IOC_IOCFG4_IE_BITN 29 -#define IOC_IOCFG4_IE_M 0x20000000 -#define IOC_IOCFG4_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG4_WU_CFG_W 2 -#define IOC_IOCFG4_WU_CFG_M 0x18000000 -#define IOC_IOCFG4_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG4_IOMODE_W 3 -#define IOC_IOCFG4_IOMODE_M 0x07000000 -#define IOC_IOCFG4_IOMODE_S 24 -#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG4_IOMODE_INV 0x01000000 -#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG4_EDGE_DET_W 2 -#define IOC_IOCFG4_EDGE_DET_M 0x00030000 -#define IOC_IOCFG4_EDGE_DET_S 16 -#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG4_PULL_CTL_W 2 -#define IOC_IOCFG4_PULL_CTL_M 0x00006000 -#define IOC_IOCFG4_PULL_CTL_S 13 -#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG4_SLEW_RED 0x00001000 -#define IOC_IOCFG4_SLEW_RED_BITN 12 -#define IOC_IOCFG4_SLEW_RED_M 0x00001000 -#define IOC_IOCFG4_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG4_IOCURR_W 2 -#define IOC_IOCFG4_IOCURR_M 0x00000C00 -#define IOC_IOCFG4_IOCURR_S 10 -#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG4_IOCURR_4MA 0x00000400 -#define IOC_IOCFG4_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG4_IOSTR_W 2 -#define IOC_IOCFG4_IOSTR_M 0x00000300 -#define IOC_IOCFG4_IOSTR_S 8 -#define IOC_IOCFG4_IOSTR_MAX 0x00000300 -#define IOC_IOCFG4_IOSTR_MED 0x00000200 -#define IOC_IOCFG4_IOSTR_MIN 0x00000100 -#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO4 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG4_PORT_ID_W 6 -#define IOC_IOCFG4_PORT_ID_M 0x0000003F -#define IOC_IOCFG4_PORT_ID_S 0 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG5 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG5_HYST_EN 0x40000000 -#define IOC_IOCFG5_HYST_EN_BITN 30 -#define IOC_IOCFG5_HYST_EN_M 0x40000000 -#define IOC_IOCFG5_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG5_IE 0x20000000 -#define IOC_IOCFG5_IE_BITN 29 -#define IOC_IOCFG5_IE_M 0x20000000 -#define IOC_IOCFG5_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG5_WU_CFG_W 2 -#define IOC_IOCFG5_WU_CFG_M 0x18000000 -#define IOC_IOCFG5_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG5_IOMODE_W 3 -#define IOC_IOCFG5_IOMODE_M 0x07000000 -#define IOC_IOCFG5_IOMODE_S 24 -#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG5_IOMODE_INV 0x01000000 -#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG5_EDGE_DET_W 2 -#define IOC_IOCFG5_EDGE_DET_M 0x00030000 -#define IOC_IOCFG5_EDGE_DET_S 16 -#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG5_PULL_CTL_W 2 -#define IOC_IOCFG5_PULL_CTL_M 0x00006000 -#define IOC_IOCFG5_PULL_CTL_S 13 -#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG5_SLEW_RED 0x00001000 -#define IOC_IOCFG5_SLEW_RED_BITN 12 -#define IOC_IOCFG5_SLEW_RED_M 0x00001000 -#define IOC_IOCFG5_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG5_IOCURR_W 2 -#define IOC_IOCFG5_IOCURR_M 0x00000C00 -#define IOC_IOCFG5_IOCURR_S 10 -#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG5_IOCURR_4MA 0x00000400 -#define IOC_IOCFG5_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG5_IOSTR_W 2 -#define IOC_IOCFG5_IOSTR_M 0x00000300 -#define IOC_IOCFG5_IOSTR_S 8 -#define IOC_IOCFG5_IOSTR_MAX 0x00000300 -#define IOC_IOCFG5_IOSTR_MED 0x00000200 -#define IOC_IOCFG5_IOSTR_MIN 0x00000100 -#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO5 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG5_PORT_ID_W 6 -#define IOC_IOCFG5_PORT_ID_M 0x0000003F -#define IOC_IOCFG5_PORT_ID_S 0 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG6 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG6_HYST_EN 0x40000000 -#define IOC_IOCFG6_HYST_EN_BITN 30 -#define IOC_IOCFG6_HYST_EN_M 0x40000000 -#define IOC_IOCFG6_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG6_IE 0x20000000 -#define IOC_IOCFG6_IE_BITN 29 -#define IOC_IOCFG6_IE_M 0x20000000 -#define IOC_IOCFG6_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG6_WU_CFG_W 2 -#define IOC_IOCFG6_WU_CFG_M 0x18000000 -#define IOC_IOCFG6_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG6_IOMODE_W 3 -#define IOC_IOCFG6_IOMODE_M 0x07000000 -#define IOC_IOCFG6_IOMODE_S 24 -#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG6_IOMODE_INV 0x01000000 -#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG6_EDGE_DET_W 2 -#define IOC_IOCFG6_EDGE_DET_M 0x00030000 -#define IOC_IOCFG6_EDGE_DET_S 16 -#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG6_PULL_CTL_W 2 -#define IOC_IOCFG6_PULL_CTL_M 0x00006000 -#define IOC_IOCFG6_PULL_CTL_S 13 -#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG6_SLEW_RED 0x00001000 -#define IOC_IOCFG6_SLEW_RED_BITN 12 -#define IOC_IOCFG6_SLEW_RED_M 0x00001000 -#define IOC_IOCFG6_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG6_IOCURR_W 2 -#define IOC_IOCFG6_IOCURR_M 0x00000C00 -#define IOC_IOCFG6_IOCURR_S 10 -#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG6_IOCURR_4MA 0x00000400 -#define IOC_IOCFG6_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG6_IOSTR_W 2 -#define IOC_IOCFG6_IOSTR_M 0x00000300 -#define IOC_IOCFG6_IOSTR_S 8 -#define IOC_IOCFG6_IOSTR_MAX 0x00000300 -#define IOC_IOCFG6_IOSTR_MED 0x00000200 -#define IOC_IOCFG6_IOSTR_MIN 0x00000100 -#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO6 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG6_PORT_ID_W 6 -#define IOC_IOCFG6_PORT_ID_M 0x0000003F -#define IOC_IOCFG6_PORT_ID_S 0 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG7 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG7_HYST_EN 0x40000000 -#define IOC_IOCFG7_HYST_EN_BITN 30 -#define IOC_IOCFG7_HYST_EN_M 0x40000000 -#define IOC_IOCFG7_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG7_IE 0x20000000 -#define IOC_IOCFG7_IE_BITN 29 -#define IOC_IOCFG7_IE_M 0x20000000 -#define IOC_IOCFG7_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG7_WU_CFG_W 2 -#define IOC_IOCFG7_WU_CFG_M 0x18000000 -#define IOC_IOCFG7_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG7_IOMODE_W 3 -#define IOC_IOCFG7_IOMODE_M 0x07000000 -#define IOC_IOCFG7_IOMODE_S 24 -#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG7_IOMODE_INV 0x01000000 -#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG7_EDGE_DET_W 2 -#define IOC_IOCFG7_EDGE_DET_M 0x00030000 -#define IOC_IOCFG7_EDGE_DET_S 16 -#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG7_PULL_CTL_W 2 -#define IOC_IOCFG7_PULL_CTL_M 0x00006000 -#define IOC_IOCFG7_PULL_CTL_S 13 -#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG7_SLEW_RED 0x00001000 -#define IOC_IOCFG7_SLEW_RED_BITN 12 -#define IOC_IOCFG7_SLEW_RED_M 0x00001000 -#define IOC_IOCFG7_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG7_IOCURR_W 2 -#define IOC_IOCFG7_IOCURR_M 0x00000C00 -#define IOC_IOCFG7_IOCURR_S 10 -#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG7_IOCURR_4MA 0x00000400 -#define IOC_IOCFG7_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG7_IOSTR_W 2 -#define IOC_IOCFG7_IOSTR_M 0x00000300 -#define IOC_IOCFG7_IOSTR_S 8 -#define IOC_IOCFG7_IOSTR_MAX 0x00000300 -#define IOC_IOCFG7_IOSTR_MED 0x00000200 -#define IOC_IOCFG7_IOSTR_MIN 0x00000100 -#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO7 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG7_PORT_ID_W 6 -#define IOC_IOCFG7_PORT_ID_M 0x0000003F -#define IOC_IOCFG7_PORT_ID_S 0 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG8 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG8_HYST_EN 0x40000000 -#define IOC_IOCFG8_HYST_EN_BITN 30 -#define IOC_IOCFG8_HYST_EN_M 0x40000000 -#define IOC_IOCFG8_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG8_IE 0x20000000 -#define IOC_IOCFG8_IE_BITN 29 -#define IOC_IOCFG8_IE_M 0x20000000 -#define IOC_IOCFG8_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG8_WU_CFG_W 2 -#define IOC_IOCFG8_WU_CFG_M 0x18000000 -#define IOC_IOCFG8_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG8_IOMODE_W 3 -#define IOC_IOCFG8_IOMODE_M 0x07000000 -#define IOC_IOCFG8_IOMODE_S 24 -#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG8_IOMODE_INV 0x01000000 -#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG8_EDGE_DET_W 2 -#define IOC_IOCFG8_EDGE_DET_M 0x00030000 -#define IOC_IOCFG8_EDGE_DET_S 16 -#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG8_PULL_CTL_W 2 -#define IOC_IOCFG8_PULL_CTL_M 0x00006000 -#define IOC_IOCFG8_PULL_CTL_S 13 -#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG8_SLEW_RED 0x00001000 -#define IOC_IOCFG8_SLEW_RED_BITN 12 -#define IOC_IOCFG8_SLEW_RED_M 0x00001000 -#define IOC_IOCFG8_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG8_IOCURR_W 2 -#define IOC_IOCFG8_IOCURR_M 0x00000C00 -#define IOC_IOCFG8_IOCURR_S 10 -#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG8_IOCURR_4MA 0x00000400 -#define IOC_IOCFG8_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG8_IOSTR_W 2 -#define IOC_IOCFG8_IOSTR_M 0x00000300 -#define IOC_IOCFG8_IOSTR_S 8 -#define IOC_IOCFG8_IOSTR_MAX 0x00000300 -#define IOC_IOCFG8_IOSTR_MED 0x00000200 -#define IOC_IOCFG8_IOSTR_MIN 0x00000100 -#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO8 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG8_PORT_ID_W 6 -#define IOC_IOCFG8_PORT_ID_M 0x0000003F -#define IOC_IOCFG8_PORT_ID_S 0 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG9 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG9_HYST_EN 0x40000000 -#define IOC_IOCFG9_HYST_EN_BITN 30 -#define IOC_IOCFG9_HYST_EN_M 0x40000000 -#define IOC_IOCFG9_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG9_IE 0x20000000 -#define IOC_IOCFG9_IE_BITN 29 -#define IOC_IOCFG9_IE_M 0x20000000 -#define IOC_IOCFG9_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG9_WU_CFG_W 2 -#define IOC_IOCFG9_WU_CFG_M 0x18000000 -#define IOC_IOCFG9_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG9_IOMODE_W 3 -#define IOC_IOCFG9_IOMODE_M 0x07000000 -#define IOC_IOCFG9_IOMODE_S 24 -#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG9_IOMODE_INV 0x01000000 -#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG9_EDGE_DET_W 2 -#define IOC_IOCFG9_EDGE_DET_M 0x00030000 -#define IOC_IOCFG9_EDGE_DET_S 16 -#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG9_PULL_CTL_W 2 -#define IOC_IOCFG9_PULL_CTL_M 0x00006000 -#define IOC_IOCFG9_PULL_CTL_S 13 -#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG9_SLEW_RED 0x00001000 -#define IOC_IOCFG9_SLEW_RED_BITN 12 -#define IOC_IOCFG9_SLEW_RED_M 0x00001000 -#define IOC_IOCFG9_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG9_IOCURR_W 2 -#define IOC_IOCFG9_IOCURR_M 0x00000C00 -#define IOC_IOCFG9_IOCURR_S 10 -#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG9_IOCURR_4MA 0x00000400 -#define IOC_IOCFG9_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG9_IOSTR_W 2 -#define IOC_IOCFG9_IOSTR_M 0x00000300 -#define IOC_IOCFG9_IOSTR_S 8 -#define IOC_IOCFG9_IOSTR_MAX 0x00000300 -#define IOC_IOCFG9_IOSTR_MED 0x00000200 -#define IOC_IOCFG9_IOSTR_MIN 0x00000100 -#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO9 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG9_PORT_ID_W 6 -#define IOC_IOCFG9_PORT_ID_M 0x0000003F -#define IOC_IOCFG9_PORT_ID_S 0 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG10 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG10_HYST_EN 0x40000000 -#define IOC_IOCFG10_HYST_EN_BITN 30 -#define IOC_IOCFG10_HYST_EN_M 0x40000000 -#define IOC_IOCFG10_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG10_IE 0x20000000 -#define IOC_IOCFG10_IE_BITN 29 -#define IOC_IOCFG10_IE_M 0x20000000 -#define IOC_IOCFG10_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG10_WU_CFG_W 2 -#define IOC_IOCFG10_WU_CFG_M 0x18000000 -#define IOC_IOCFG10_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG10_IOMODE_W 3 -#define IOC_IOCFG10_IOMODE_M 0x07000000 -#define IOC_IOCFG10_IOMODE_S 24 -#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG10_IOMODE_INV 0x01000000 -#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG10_EDGE_DET_W 2 -#define IOC_IOCFG10_EDGE_DET_M 0x00030000 -#define IOC_IOCFG10_EDGE_DET_S 16 -#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG10_PULL_CTL_W 2 -#define IOC_IOCFG10_PULL_CTL_M 0x00006000 -#define IOC_IOCFG10_PULL_CTL_S 13 -#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG10_SLEW_RED 0x00001000 -#define IOC_IOCFG10_SLEW_RED_BITN 12 -#define IOC_IOCFG10_SLEW_RED_M 0x00001000 -#define IOC_IOCFG10_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG10_IOCURR_W 2 -#define IOC_IOCFG10_IOCURR_M 0x00000C00 -#define IOC_IOCFG10_IOCURR_S 10 -#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG10_IOCURR_4MA 0x00000400 -#define IOC_IOCFG10_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG10_IOSTR_W 2 -#define IOC_IOCFG10_IOSTR_M 0x00000300 -#define IOC_IOCFG10_IOSTR_S 8 -#define IOC_IOCFG10_IOSTR_MAX 0x00000300 -#define IOC_IOCFG10_IOSTR_MED 0x00000200 -#define IOC_IOCFG10_IOSTR_MIN 0x00000100 -#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO10 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG10_PORT_ID_W 6 -#define IOC_IOCFG10_PORT_ID_M 0x0000003F -#define IOC_IOCFG10_PORT_ID_S 0 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG11 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG11_HYST_EN 0x40000000 -#define IOC_IOCFG11_HYST_EN_BITN 30 -#define IOC_IOCFG11_HYST_EN_M 0x40000000 -#define IOC_IOCFG11_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG11_IE 0x20000000 -#define IOC_IOCFG11_IE_BITN 29 -#define IOC_IOCFG11_IE_M 0x20000000 -#define IOC_IOCFG11_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG11_WU_CFG_W 2 -#define IOC_IOCFG11_WU_CFG_M 0x18000000 -#define IOC_IOCFG11_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG11_IOMODE_W 3 -#define IOC_IOCFG11_IOMODE_M 0x07000000 -#define IOC_IOCFG11_IOMODE_S 24 -#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG11_IOMODE_INV 0x01000000 -#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG11_EDGE_DET_W 2 -#define IOC_IOCFG11_EDGE_DET_M 0x00030000 -#define IOC_IOCFG11_EDGE_DET_S 16 -#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG11_PULL_CTL_W 2 -#define IOC_IOCFG11_PULL_CTL_M 0x00006000 -#define IOC_IOCFG11_PULL_CTL_S 13 -#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG11_SLEW_RED 0x00001000 -#define IOC_IOCFG11_SLEW_RED_BITN 12 -#define IOC_IOCFG11_SLEW_RED_M 0x00001000 -#define IOC_IOCFG11_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG11_IOCURR_W 2 -#define IOC_IOCFG11_IOCURR_M 0x00000C00 -#define IOC_IOCFG11_IOCURR_S 10 -#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG11_IOCURR_4MA 0x00000400 -#define IOC_IOCFG11_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG11_IOSTR_W 2 -#define IOC_IOCFG11_IOSTR_M 0x00000300 -#define IOC_IOCFG11_IOSTR_S 8 -#define IOC_IOCFG11_IOSTR_MAX 0x00000300 -#define IOC_IOCFG11_IOSTR_MED 0x00000200 -#define IOC_IOCFG11_IOSTR_MIN 0x00000100 -#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO11 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG11_PORT_ID_W 6 -#define IOC_IOCFG11_PORT_ID_M 0x0000003F -#define IOC_IOCFG11_PORT_ID_S 0 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG12 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG12_HYST_EN 0x40000000 -#define IOC_IOCFG12_HYST_EN_BITN 30 -#define IOC_IOCFG12_HYST_EN_M 0x40000000 -#define IOC_IOCFG12_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG12_IE 0x20000000 -#define IOC_IOCFG12_IE_BITN 29 -#define IOC_IOCFG12_IE_M 0x20000000 -#define IOC_IOCFG12_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG12_WU_CFG_W 2 -#define IOC_IOCFG12_WU_CFG_M 0x18000000 -#define IOC_IOCFG12_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG12_IOMODE_W 3 -#define IOC_IOCFG12_IOMODE_M 0x07000000 -#define IOC_IOCFG12_IOMODE_S 24 -#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG12_IOMODE_INV 0x01000000 -#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG12_EDGE_DET_W 2 -#define IOC_IOCFG12_EDGE_DET_M 0x00030000 -#define IOC_IOCFG12_EDGE_DET_S 16 -#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG12_PULL_CTL_W 2 -#define IOC_IOCFG12_PULL_CTL_M 0x00006000 -#define IOC_IOCFG12_PULL_CTL_S 13 -#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG12_SLEW_RED 0x00001000 -#define IOC_IOCFG12_SLEW_RED_BITN 12 -#define IOC_IOCFG12_SLEW_RED_M 0x00001000 -#define IOC_IOCFG12_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG12_IOCURR_W 2 -#define IOC_IOCFG12_IOCURR_M 0x00000C00 -#define IOC_IOCFG12_IOCURR_S 10 -#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG12_IOCURR_4MA 0x00000400 -#define IOC_IOCFG12_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG12_IOSTR_W 2 -#define IOC_IOCFG12_IOSTR_M 0x00000300 -#define IOC_IOCFG12_IOSTR_S 8 -#define IOC_IOCFG12_IOSTR_MAX 0x00000300 -#define IOC_IOCFG12_IOSTR_MED 0x00000200 -#define IOC_IOCFG12_IOSTR_MIN 0x00000100 -#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO12 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG12_PORT_ID_W 6 -#define IOC_IOCFG12_PORT_ID_M 0x0000003F -#define IOC_IOCFG12_PORT_ID_S 0 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG13 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG13_HYST_EN 0x40000000 -#define IOC_IOCFG13_HYST_EN_BITN 30 -#define IOC_IOCFG13_HYST_EN_M 0x40000000 -#define IOC_IOCFG13_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG13_IE 0x20000000 -#define IOC_IOCFG13_IE_BITN 29 -#define IOC_IOCFG13_IE_M 0x20000000 -#define IOC_IOCFG13_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG13_WU_CFG_W 2 -#define IOC_IOCFG13_WU_CFG_M 0x18000000 -#define IOC_IOCFG13_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG13_IOMODE_W 3 -#define IOC_IOCFG13_IOMODE_M 0x07000000 -#define IOC_IOCFG13_IOMODE_S 24 -#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG13_IOMODE_INV 0x01000000 -#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG13_EDGE_DET_W 2 -#define IOC_IOCFG13_EDGE_DET_M 0x00030000 -#define IOC_IOCFG13_EDGE_DET_S 16 -#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG13_PULL_CTL_W 2 -#define IOC_IOCFG13_PULL_CTL_M 0x00006000 -#define IOC_IOCFG13_PULL_CTL_S 13 -#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG13_SLEW_RED 0x00001000 -#define IOC_IOCFG13_SLEW_RED_BITN 12 -#define IOC_IOCFG13_SLEW_RED_M 0x00001000 -#define IOC_IOCFG13_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG13_IOCURR_W 2 -#define IOC_IOCFG13_IOCURR_M 0x00000C00 -#define IOC_IOCFG13_IOCURR_S 10 -#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG13_IOCURR_4MA 0x00000400 -#define IOC_IOCFG13_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG13_IOSTR_W 2 -#define IOC_IOCFG13_IOSTR_M 0x00000300 -#define IOC_IOCFG13_IOSTR_S 8 -#define IOC_IOCFG13_IOSTR_MAX 0x00000300 -#define IOC_IOCFG13_IOSTR_MED 0x00000200 -#define IOC_IOCFG13_IOSTR_MIN 0x00000100 -#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO13 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG13_PORT_ID_W 6 -#define IOC_IOCFG13_PORT_ID_M 0x0000003F -#define IOC_IOCFG13_PORT_ID_S 0 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG14 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG14_HYST_EN 0x40000000 -#define IOC_IOCFG14_HYST_EN_BITN 30 -#define IOC_IOCFG14_HYST_EN_M 0x40000000 -#define IOC_IOCFG14_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG14_IE 0x20000000 -#define IOC_IOCFG14_IE_BITN 29 -#define IOC_IOCFG14_IE_M 0x20000000 -#define IOC_IOCFG14_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG14_WU_CFG_W 2 -#define IOC_IOCFG14_WU_CFG_M 0x18000000 -#define IOC_IOCFG14_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG14_IOMODE_W 3 -#define IOC_IOCFG14_IOMODE_M 0x07000000 -#define IOC_IOCFG14_IOMODE_S 24 -#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG14_IOMODE_INV 0x01000000 -#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG14_EDGE_DET_W 2 -#define IOC_IOCFG14_EDGE_DET_M 0x00030000 -#define IOC_IOCFG14_EDGE_DET_S 16 -#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG14_PULL_CTL_W 2 -#define IOC_IOCFG14_PULL_CTL_M 0x00006000 -#define IOC_IOCFG14_PULL_CTL_S 13 -#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG14_SLEW_RED 0x00001000 -#define IOC_IOCFG14_SLEW_RED_BITN 12 -#define IOC_IOCFG14_SLEW_RED_M 0x00001000 -#define IOC_IOCFG14_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG14_IOCURR_W 2 -#define IOC_IOCFG14_IOCURR_M 0x00000C00 -#define IOC_IOCFG14_IOCURR_S 10 -#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG14_IOCURR_4MA 0x00000400 -#define IOC_IOCFG14_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG14_IOSTR_W 2 -#define IOC_IOCFG14_IOSTR_M 0x00000300 -#define IOC_IOCFG14_IOSTR_S 8 -#define IOC_IOCFG14_IOSTR_MAX 0x00000300 -#define IOC_IOCFG14_IOSTR_MED 0x00000200 -#define IOC_IOCFG14_IOSTR_MIN 0x00000100 -#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO14 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG14_PORT_ID_W 6 -#define IOC_IOCFG14_PORT_ID_M 0x0000003F -#define IOC_IOCFG14_PORT_ID_S 0 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG15 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG15_HYST_EN 0x40000000 -#define IOC_IOCFG15_HYST_EN_BITN 30 -#define IOC_IOCFG15_HYST_EN_M 0x40000000 -#define IOC_IOCFG15_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG15_IE 0x20000000 -#define IOC_IOCFG15_IE_BITN 29 -#define IOC_IOCFG15_IE_M 0x20000000 -#define IOC_IOCFG15_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG15_WU_CFG_W 2 -#define IOC_IOCFG15_WU_CFG_M 0x18000000 -#define IOC_IOCFG15_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG15_IOMODE_W 3 -#define IOC_IOCFG15_IOMODE_M 0x07000000 -#define IOC_IOCFG15_IOMODE_S 24 -#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG15_IOMODE_INV 0x01000000 -#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG15_EDGE_DET_W 2 -#define IOC_IOCFG15_EDGE_DET_M 0x00030000 -#define IOC_IOCFG15_EDGE_DET_S 16 -#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG15_PULL_CTL_W 2 -#define IOC_IOCFG15_PULL_CTL_M 0x00006000 -#define IOC_IOCFG15_PULL_CTL_S 13 -#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG15_SLEW_RED 0x00001000 -#define IOC_IOCFG15_SLEW_RED_BITN 12 -#define IOC_IOCFG15_SLEW_RED_M 0x00001000 -#define IOC_IOCFG15_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG15_IOCURR_W 2 -#define IOC_IOCFG15_IOCURR_M 0x00000C00 -#define IOC_IOCFG15_IOCURR_S 10 -#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG15_IOCURR_4MA 0x00000400 -#define IOC_IOCFG15_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG15_IOSTR_W 2 -#define IOC_IOCFG15_IOSTR_M 0x00000300 -#define IOC_IOCFG15_IOSTR_S 8 -#define IOC_IOCFG15_IOSTR_MAX 0x00000300 -#define IOC_IOCFG15_IOSTR_MED 0x00000200 -#define IOC_IOCFG15_IOSTR_MIN 0x00000100 -#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO15 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG15_PORT_ID_W 6 -#define IOC_IOCFG15_PORT_ID_M 0x0000003F -#define IOC_IOCFG15_PORT_ID_S 0 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG16 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG16_HYST_EN 0x40000000 -#define IOC_IOCFG16_HYST_EN_BITN 30 -#define IOC_IOCFG16_HYST_EN_M 0x40000000 -#define IOC_IOCFG16_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG16_IE 0x20000000 -#define IOC_IOCFG16_IE_BITN 29 -#define IOC_IOCFG16_IE_M 0x20000000 -#define IOC_IOCFG16_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG16_WU_CFG_W 2 -#define IOC_IOCFG16_WU_CFG_M 0x18000000 -#define IOC_IOCFG16_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG16_IOMODE_W 3 -#define IOC_IOCFG16_IOMODE_M 0x07000000 -#define IOC_IOCFG16_IOMODE_S 24 -#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG16_IOMODE_INV 0x01000000 -#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG16_EDGE_DET_W 2 -#define IOC_IOCFG16_EDGE_DET_M 0x00030000 -#define IOC_IOCFG16_EDGE_DET_S 16 -#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG16_PULL_CTL_W 2 -#define IOC_IOCFG16_PULL_CTL_M 0x00006000 -#define IOC_IOCFG16_PULL_CTL_S 13 -#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG16_SLEW_RED 0x00001000 -#define IOC_IOCFG16_SLEW_RED_BITN 12 -#define IOC_IOCFG16_SLEW_RED_M 0x00001000 -#define IOC_IOCFG16_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG16_IOCURR_W 2 -#define IOC_IOCFG16_IOCURR_M 0x00000C00 -#define IOC_IOCFG16_IOCURR_S 10 -#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG16_IOCURR_4MA 0x00000400 -#define IOC_IOCFG16_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG16_IOSTR_W 2 -#define IOC_IOCFG16_IOSTR_M 0x00000300 -#define IOC_IOCFG16_IOSTR_S 8 -#define IOC_IOCFG16_IOSTR_MAX 0x00000300 -#define IOC_IOCFG16_IOSTR_MED 0x00000200 -#define IOC_IOCFG16_IOSTR_MIN 0x00000100 -#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO16 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG16_PORT_ID_W 6 -#define IOC_IOCFG16_PORT_ID_M 0x0000003F -#define IOC_IOCFG16_PORT_ID_S 0 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG17 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG17_HYST_EN 0x40000000 -#define IOC_IOCFG17_HYST_EN_BITN 30 -#define IOC_IOCFG17_HYST_EN_M 0x40000000 -#define IOC_IOCFG17_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG17_IE 0x20000000 -#define IOC_IOCFG17_IE_BITN 29 -#define IOC_IOCFG17_IE_M 0x20000000 -#define IOC_IOCFG17_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG17_WU_CFG_W 2 -#define IOC_IOCFG17_WU_CFG_M 0x18000000 -#define IOC_IOCFG17_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG17_IOMODE_W 3 -#define IOC_IOCFG17_IOMODE_M 0x07000000 -#define IOC_IOCFG17_IOMODE_S 24 -#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG17_IOMODE_INV 0x01000000 -#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG17_EDGE_DET_W 2 -#define IOC_IOCFG17_EDGE_DET_M 0x00030000 -#define IOC_IOCFG17_EDGE_DET_S 16 -#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG17_PULL_CTL_W 2 -#define IOC_IOCFG17_PULL_CTL_M 0x00006000 -#define IOC_IOCFG17_PULL_CTL_S 13 -#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG17_SLEW_RED 0x00001000 -#define IOC_IOCFG17_SLEW_RED_BITN 12 -#define IOC_IOCFG17_SLEW_RED_M 0x00001000 -#define IOC_IOCFG17_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG17_IOCURR_W 2 -#define IOC_IOCFG17_IOCURR_M 0x00000C00 -#define IOC_IOCFG17_IOCURR_S 10 -#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG17_IOCURR_4MA 0x00000400 -#define IOC_IOCFG17_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG17_IOSTR_W 2 -#define IOC_IOCFG17_IOSTR_M 0x00000300 -#define IOC_IOCFG17_IOSTR_S 8 -#define IOC_IOCFG17_IOSTR_MAX 0x00000300 -#define IOC_IOCFG17_IOSTR_MED 0x00000200 -#define IOC_IOCFG17_IOSTR_MIN 0x00000100 -#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO17 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG17_PORT_ID_W 6 -#define IOC_IOCFG17_PORT_ID_M 0x0000003F -#define IOC_IOCFG17_PORT_ID_S 0 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG18 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG18_HYST_EN 0x40000000 -#define IOC_IOCFG18_HYST_EN_BITN 30 -#define IOC_IOCFG18_HYST_EN_M 0x40000000 -#define IOC_IOCFG18_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG18_IE 0x20000000 -#define IOC_IOCFG18_IE_BITN 29 -#define IOC_IOCFG18_IE_M 0x20000000 -#define IOC_IOCFG18_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG18_WU_CFG_W 2 -#define IOC_IOCFG18_WU_CFG_M 0x18000000 -#define IOC_IOCFG18_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG18_IOMODE_W 3 -#define IOC_IOCFG18_IOMODE_M 0x07000000 -#define IOC_IOCFG18_IOMODE_S 24 -#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG18_IOMODE_INV 0x01000000 -#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG18_EDGE_DET_W 2 -#define IOC_IOCFG18_EDGE_DET_M 0x00030000 -#define IOC_IOCFG18_EDGE_DET_S 16 -#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG18_PULL_CTL_W 2 -#define IOC_IOCFG18_PULL_CTL_M 0x00006000 -#define IOC_IOCFG18_PULL_CTL_S 13 -#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG18_SLEW_RED 0x00001000 -#define IOC_IOCFG18_SLEW_RED_BITN 12 -#define IOC_IOCFG18_SLEW_RED_M 0x00001000 -#define IOC_IOCFG18_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG18_IOCURR_W 2 -#define IOC_IOCFG18_IOCURR_M 0x00000C00 -#define IOC_IOCFG18_IOCURR_S 10 -#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG18_IOCURR_4MA 0x00000400 -#define IOC_IOCFG18_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG18_IOSTR_W 2 -#define IOC_IOCFG18_IOSTR_M 0x00000300 -#define IOC_IOCFG18_IOSTR_S 8 -#define IOC_IOCFG18_IOSTR_MAX 0x00000300 -#define IOC_IOCFG18_IOSTR_MED 0x00000200 -#define IOC_IOCFG18_IOSTR_MIN 0x00000100 -#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO18 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG18_PORT_ID_W 6 -#define IOC_IOCFG18_PORT_ID_M 0x0000003F -#define IOC_IOCFG18_PORT_ID_S 0 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG19 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG19_HYST_EN 0x40000000 -#define IOC_IOCFG19_HYST_EN_BITN 30 -#define IOC_IOCFG19_HYST_EN_M 0x40000000 -#define IOC_IOCFG19_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG19_IE 0x20000000 -#define IOC_IOCFG19_IE_BITN 29 -#define IOC_IOCFG19_IE_M 0x20000000 -#define IOC_IOCFG19_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG19_WU_CFG_W 2 -#define IOC_IOCFG19_WU_CFG_M 0x18000000 -#define IOC_IOCFG19_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG19_IOMODE_W 3 -#define IOC_IOCFG19_IOMODE_M 0x07000000 -#define IOC_IOCFG19_IOMODE_S 24 -#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG19_IOMODE_INV 0x01000000 -#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG19_EDGE_DET_W 2 -#define IOC_IOCFG19_EDGE_DET_M 0x00030000 -#define IOC_IOCFG19_EDGE_DET_S 16 -#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG19_PULL_CTL_W 2 -#define IOC_IOCFG19_PULL_CTL_M 0x00006000 -#define IOC_IOCFG19_PULL_CTL_S 13 -#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG19_SLEW_RED 0x00001000 -#define IOC_IOCFG19_SLEW_RED_BITN 12 -#define IOC_IOCFG19_SLEW_RED_M 0x00001000 -#define IOC_IOCFG19_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG19_IOCURR_W 2 -#define IOC_IOCFG19_IOCURR_M 0x00000C00 -#define IOC_IOCFG19_IOCURR_S 10 -#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG19_IOCURR_4MA 0x00000400 -#define IOC_IOCFG19_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG19_IOSTR_W 2 -#define IOC_IOCFG19_IOSTR_M 0x00000300 -#define IOC_IOCFG19_IOSTR_S 8 -#define IOC_IOCFG19_IOSTR_MAX 0x00000300 -#define IOC_IOCFG19_IOSTR_MED 0x00000200 -#define IOC_IOCFG19_IOSTR_MIN 0x00000100 -#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO19 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG19_PORT_ID_W 6 -#define IOC_IOCFG19_PORT_ID_M 0x0000003F -#define IOC_IOCFG19_PORT_ID_S 0 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG20 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG20_HYST_EN 0x40000000 -#define IOC_IOCFG20_HYST_EN_BITN 30 -#define IOC_IOCFG20_HYST_EN_M 0x40000000 -#define IOC_IOCFG20_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG20_IE 0x20000000 -#define IOC_IOCFG20_IE_BITN 29 -#define IOC_IOCFG20_IE_M 0x20000000 -#define IOC_IOCFG20_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG20_WU_CFG_W 2 -#define IOC_IOCFG20_WU_CFG_M 0x18000000 -#define IOC_IOCFG20_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG20_IOMODE_W 3 -#define IOC_IOCFG20_IOMODE_M 0x07000000 -#define IOC_IOCFG20_IOMODE_S 24 -#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG20_IOMODE_INV 0x01000000 -#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG20_EDGE_DET_W 2 -#define IOC_IOCFG20_EDGE_DET_M 0x00030000 -#define IOC_IOCFG20_EDGE_DET_S 16 -#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG20_PULL_CTL_W 2 -#define IOC_IOCFG20_PULL_CTL_M 0x00006000 -#define IOC_IOCFG20_PULL_CTL_S 13 -#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG20_SLEW_RED 0x00001000 -#define IOC_IOCFG20_SLEW_RED_BITN 12 -#define IOC_IOCFG20_SLEW_RED_M 0x00001000 -#define IOC_IOCFG20_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG20_IOCURR_W 2 -#define IOC_IOCFG20_IOCURR_M 0x00000C00 -#define IOC_IOCFG20_IOCURR_S 10 -#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG20_IOCURR_4MA 0x00000400 -#define IOC_IOCFG20_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG20_IOSTR_W 2 -#define IOC_IOCFG20_IOSTR_M 0x00000300 -#define IOC_IOCFG20_IOSTR_S 8 -#define IOC_IOCFG20_IOSTR_MAX 0x00000300 -#define IOC_IOCFG20_IOSTR_MED 0x00000200 -#define IOC_IOCFG20_IOSTR_MIN 0x00000100 -#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO20 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG20_PORT_ID_W 6 -#define IOC_IOCFG20_PORT_ID_M 0x0000003F -#define IOC_IOCFG20_PORT_ID_S 0 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG21 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG21_HYST_EN 0x40000000 -#define IOC_IOCFG21_HYST_EN_BITN 30 -#define IOC_IOCFG21_HYST_EN_M 0x40000000 -#define IOC_IOCFG21_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG21_IE 0x20000000 -#define IOC_IOCFG21_IE_BITN 29 -#define IOC_IOCFG21_IE_M 0x20000000 -#define IOC_IOCFG21_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG21_WU_CFG_W 2 -#define IOC_IOCFG21_WU_CFG_M 0x18000000 -#define IOC_IOCFG21_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG21_IOMODE_W 3 -#define IOC_IOCFG21_IOMODE_M 0x07000000 -#define IOC_IOCFG21_IOMODE_S 24 -#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG21_IOMODE_INV 0x01000000 -#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG21_EDGE_DET_W 2 -#define IOC_IOCFG21_EDGE_DET_M 0x00030000 -#define IOC_IOCFG21_EDGE_DET_S 16 -#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG21_PULL_CTL_W 2 -#define IOC_IOCFG21_PULL_CTL_M 0x00006000 -#define IOC_IOCFG21_PULL_CTL_S 13 -#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG21_SLEW_RED 0x00001000 -#define IOC_IOCFG21_SLEW_RED_BITN 12 -#define IOC_IOCFG21_SLEW_RED_M 0x00001000 -#define IOC_IOCFG21_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG21_IOCURR_W 2 -#define IOC_IOCFG21_IOCURR_M 0x00000C00 -#define IOC_IOCFG21_IOCURR_S 10 -#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG21_IOCURR_4MA 0x00000400 -#define IOC_IOCFG21_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG21_IOSTR_W 2 -#define IOC_IOCFG21_IOSTR_M 0x00000300 -#define IOC_IOCFG21_IOSTR_S 8 -#define IOC_IOCFG21_IOSTR_MAX 0x00000300 -#define IOC_IOCFG21_IOSTR_MED 0x00000200 -#define IOC_IOCFG21_IOSTR_MIN 0x00000100 -#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO21 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG21_PORT_ID_W 6 -#define IOC_IOCFG21_PORT_ID_M 0x0000003F -#define IOC_IOCFG21_PORT_ID_S 0 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG22 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG22_HYST_EN 0x40000000 -#define IOC_IOCFG22_HYST_EN_BITN 30 -#define IOC_IOCFG22_HYST_EN_M 0x40000000 -#define IOC_IOCFG22_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG22_IE 0x20000000 -#define IOC_IOCFG22_IE_BITN 29 -#define IOC_IOCFG22_IE_M 0x20000000 -#define IOC_IOCFG22_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG22_WU_CFG_W 2 -#define IOC_IOCFG22_WU_CFG_M 0x18000000 -#define IOC_IOCFG22_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG22_IOMODE_W 3 -#define IOC_IOCFG22_IOMODE_M 0x07000000 -#define IOC_IOCFG22_IOMODE_S 24 -#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG22_IOMODE_INV 0x01000000 -#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG22_EDGE_DET_W 2 -#define IOC_IOCFG22_EDGE_DET_M 0x00030000 -#define IOC_IOCFG22_EDGE_DET_S 16 -#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG22_PULL_CTL_W 2 -#define IOC_IOCFG22_PULL_CTL_M 0x00006000 -#define IOC_IOCFG22_PULL_CTL_S 13 -#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG22_SLEW_RED 0x00001000 -#define IOC_IOCFG22_SLEW_RED_BITN 12 -#define IOC_IOCFG22_SLEW_RED_M 0x00001000 -#define IOC_IOCFG22_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG22_IOCURR_W 2 -#define IOC_IOCFG22_IOCURR_M 0x00000C00 -#define IOC_IOCFG22_IOCURR_S 10 -#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG22_IOCURR_4MA 0x00000400 -#define IOC_IOCFG22_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG22_IOSTR_W 2 -#define IOC_IOCFG22_IOSTR_M 0x00000300 -#define IOC_IOCFG22_IOSTR_S 8 -#define IOC_IOCFG22_IOSTR_MAX 0x00000300 -#define IOC_IOCFG22_IOSTR_MED 0x00000200 -#define IOC_IOCFG22_IOSTR_MIN 0x00000100 -#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO22 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG22_PORT_ID_W 6 -#define IOC_IOCFG22_PORT_ID_M 0x0000003F -#define IOC_IOCFG22_PORT_ID_S 0 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG23 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG23_HYST_EN 0x40000000 -#define IOC_IOCFG23_HYST_EN_BITN 30 -#define IOC_IOCFG23_HYST_EN_M 0x40000000 -#define IOC_IOCFG23_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG23_IE 0x20000000 -#define IOC_IOCFG23_IE_BITN 29 -#define IOC_IOCFG23_IE_M 0x20000000 -#define IOC_IOCFG23_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG23_WU_CFG_W 2 -#define IOC_IOCFG23_WU_CFG_M 0x18000000 -#define IOC_IOCFG23_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG23_IOMODE_W 3 -#define IOC_IOCFG23_IOMODE_M 0x07000000 -#define IOC_IOCFG23_IOMODE_S 24 -#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG23_IOMODE_INV 0x01000000 -#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG23_EDGE_DET_W 2 -#define IOC_IOCFG23_EDGE_DET_M 0x00030000 -#define IOC_IOCFG23_EDGE_DET_S 16 -#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG23_PULL_CTL_W 2 -#define IOC_IOCFG23_PULL_CTL_M 0x00006000 -#define IOC_IOCFG23_PULL_CTL_S 13 -#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG23_SLEW_RED 0x00001000 -#define IOC_IOCFG23_SLEW_RED_BITN 12 -#define IOC_IOCFG23_SLEW_RED_M 0x00001000 -#define IOC_IOCFG23_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG23_IOCURR_W 2 -#define IOC_IOCFG23_IOCURR_M 0x00000C00 -#define IOC_IOCFG23_IOCURR_S 10 -#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG23_IOCURR_4MA 0x00000400 -#define IOC_IOCFG23_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG23_IOSTR_W 2 -#define IOC_IOCFG23_IOSTR_M 0x00000300 -#define IOC_IOCFG23_IOSTR_S 8 -#define IOC_IOCFG23_IOSTR_MAX 0x00000300 -#define IOC_IOCFG23_IOSTR_MED 0x00000200 -#define IOC_IOCFG23_IOSTR_MIN 0x00000100 -#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO23 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG23_PORT_ID_W 6 -#define IOC_IOCFG23_PORT_ID_M 0x0000003F -#define IOC_IOCFG23_PORT_ID_S 0 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG24 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG24_HYST_EN 0x40000000 -#define IOC_IOCFG24_HYST_EN_BITN 30 -#define IOC_IOCFG24_HYST_EN_M 0x40000000 -#define IOC_IOCFG24_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG24_IE 0x20000000 -#define IOC_IOCFG24_IE_BITN 29 -#define IOC_IOCFG24_IE_M 0x20000000 -#define IOC_IOCFG24_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG24_WU_CFG_W 2 -#define IOC_IOCFG24_WU_CFG_M 0x18000000 -#define IOC_IOCFG24_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG24_IOMODE_W 3 -#define IOC_IOCFG24_IOMODE_M 0x07000000 -#define IOC_IOCFG24_IOMODE_S 24 -#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG24_IOMODE_INV 0x01000000 -#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG24_EDGE_DET_W 2 -#define IOC_IOCFG24_EDGE_DET_M 0x00030000 -#define IOC_IOCFG24_EDGE_DET_S 16 -#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG24_PULL_CTL_W 2 -#define IOC_IOCFG24_PULL_CTL_M 0x00006000 -#define IOC_IOCFG24_PULL_CTL_S 13 -#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG24_SLEW_RED 0x00001000 -#define IOC_IOCFG24_SLEW_RED_BITN 12 -#define IOC_IOCFG24_SLEW_RED_M 0x00001000 -#define IOC_IOCFG24_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG24_IOCURR_W 2 -#define IOC_IOCFG24_IOCURR_M 0x00000C00 -#define IOC_IOCFG24_IOCURR_S 10 -#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG24_IOCURR_4MA 0x00000400 -#define IOC_IOCFG24_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG24_IOSTR_W 2 -#define IOC_IOCFG24_IOSTR_M 0x00000300 -#define IOC_IOCFG24_IOSTR_S 8 -#define IOC_IOCFG24_IOSTR_MAX 0x00000300 -#define IOC_IOCFG24_IOSTR_MED 0x00000200 -#define IOC_IOCFG24_IOSTR_MIN 0x00000100 -#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO24 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG24_PORT_ID_W 6 -#define IOC_IOCFG24_PORT_ID_M 0x0000003F -#define IOC_IOCFG24_PORT_ID_S 0 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG25 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG25_HYST_EN 0x40000000 -#define IOC_IOCFG25_HYST_EN_BITN 30 -#define IOC_IOCFG25_HYST_EN_M 0x40000000 -#define IOC_IOCFG25_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG25_IE 0x20000000 -#define IOC_IOCFG25_IE_BITN 29 -#define IOC_IOCFG25_IE_M 0x20000000 -#define IOC_IOCFG25_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG25_WU_CFG_W 2 -#define IOC_IOCFG25_WU_CFG_M 0x18000000 -#define IOC_IOCFG25_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG25_IOMODE_W 3 -#define IOC_IOCFG25_IOMODE_M 0x07000000 -#define IOC_IOCFG25_IOMODE_S 24 -#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG25_IOMODE_INV 0x01000000 -#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG25_EDGE_DET_W 2 -#define IOC_IOCFG25_EDGE_DET_M 0x00030000 -#define IOC_IOCFG25_EDGE_DET_S 16 -#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG25_PULL_CTL_W 2 -#define IOC_IOCFG25_PULL_CTL_M 0x00006000 -#define IOC_IOCFG25_PULL_CTL_S 13 -#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG25_SLEW_RED 0x00001000 -#define IOC_IOCFG25_SLEW_RED_BITN 12 -#define IOC_IOCFG25_SLEW_RED_M 0x00001000 -#define IOC_IOCFG25_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG25_IOCURR_W 2 -#define IOC_IOCFG25_IOCURR_M 0x00000C00 -#define IOC_IOCFG25_IOCURR_S 10 -#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG25_IOCURR_4MA 0x00000400 -#define IOC_IOCFG25_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG25_IOSTR_W 2 -#define IOC_IOCFG25_IOSTR_M 0x00000300 -#define IOC_IOCFG25_IOSTR_S 8 -#define IOC_IOCFG25_IOSTR_MAX 0x00000300 -#define IOC_IOCFG25_IOSTR_MED 0x00000200 -#define IOC_IOCFG25_IOSTR_MIN 0x00000100 -#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO25 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG25_PORT_ID_W 6 -#define IOC_IOCFG25_PORT_ID_M 0x0000003F -#define IOC_IOCFG25_PORT_ID_S 0 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG26 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG26_HYST_EN 0x40000000 -#define IOC_IOCFG26_HYST_EN_BITN 30 -#define IOC_IOCFG26_HYST_EN_M 0x40000000 -#define IOC_IOCFG26_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG26_IE 0x20000000 -#define IOC_IOCFG26_IE_BITN 29 -#define IOC_IOCFG26_IE_M 0x20000000 -#define IOC_IOCFG26_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG26_WU_CFG_W 2 -#define IOC_IOCFG26_WU_CFG_M 0x18000000 -#define IOC_IOCFG26_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG26_IOMODE_W 3 -#define IOC_IOCFG26_IOMODE_M 0x07000000 -#define IOC_IOCFG26_IOMODE_S 24 -#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG26_IOMODE_INV 0x01000000 -#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG26_EDGE_DET_W 2 -#define IOC_IOCFG26_EDGE_DET_M 0x00030000 -#define IOC_IOCFG26_EDGE_DET_S 16 -#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG26_PULL_CTL_W 2 -#define IOC_IOCFG26_PULL_CTL_M 0x00006000 -#define IOC_IOCFG26_PULL_CTL_S 13 -#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG26_SLEW_RED 0x00001000 -#define IOC_IOCFG26_SLEW_RED_BITN 12 -#define IOC_IOCFG26_SLEW_RED_M 0x00001000 -#define IOC_IOCFG26_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG26_IOCURR_W 2 -#define IOC_IOCFG26_IOCURR_M 0x00000C00 -#define IOC_IOCFG26_IOCURR_S 10 -#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG26_IOCURR_4MA 0x00000400 -#define IOC_IOCFG26_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG26_IOSTR_W 2 -#define IOC_IOCFG26_IOSTR_M 0x00000300 -#define IOC_IOCFG26_IOSTR_S 8 -#define IOC_IOCFG26_IOSTR_MAX 0x00000300 -#define IOC_IOCFG26_IOSTR_MED 0x00000200 -#define IOC_IOCFG26_IOSTR_MIN 0x00000100 -#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO26 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG26_PORT_ID_W 6 -#define IOC_IOCFG26_PORT_ID_M 0x0000003F -#define IOC_IOCFG26_PORT_ID_S 0 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG27 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG27_HYST_EN 0x40000000 -#define IOC_IOCFG27_HYST_EN_BITN 30 -#define IOC_IOCFG27_HYST_EN_M 0x40000000 -#define IOC_IOCFG27_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG27_IE 0x20000000 -#define IOC_IOCFG27_IE_BITN 29 -#define IOC_IOCFG27_IE_M 0x20000000 -#define IOC_IOCFG27_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG27_WU_CFG_W 2 -#define IOC_IOCFG27_WU_CFG_M 0x18000000 -#define IOC_IOCFG27_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG27_IOMODE_W 3 -#define IOC_IOCFG27_IOMODE_M 0x07000000 -#define IOC_IOCFG27_IOMODE_S 24 -#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG27_IOMODE_INV 0x01000000 -#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG27_EDGE_DET_W 2 -#define IOC_IOCFG27_EDGE_DET_M 0x00030000 -#define IOC_IOCFG27_EDGE_DET_S 16 -#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG27_PULL_CTL_W 2 -#define IOC_IOCFG27_PULL_CTL_M 0x00006000 -#define IOC_IOCFG27_PULL_CTL_S 13 -#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG27_SLEW_RED 0x00001000 -#define IOC_IOCFG27_SLEW_RED_BITN 12 -#define IOC_IOCFG27_SLEW_RED_M 0x00001000 -#define IOC_IOCFG27_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG27_IOCURR_W 2 -#define IOC_IOCFG27_IOCURR_M 0x00000C00 -#define IOC_IOCFG27_IOCURR_S 10 -#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG27_IOCURR_4MA 0x00000400 -#define IOC_IOCFG27_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG27_IOSTR_W 2 -#define IOC_IOCFG27_IOSTR_M 0x00000300 -#define IOC_IOCFG27_IOSTR_S 8 -#define IOC_IOCFG27_IOSTR_MAX 0x00000300 -#define IOC_IOCFG27_IOSTR_MED 0x00000200 -#define IOC_IOCFG27_IOSTR_MIN 0x00000100 -#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO27 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG27_PORT_ID_W 6 -#define IOC_IOCFG27_PORT_ID_M 0x0000003F -#define IOC_IOCFG27_PORT_ID_S 0 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG28 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG28_HYST_EN 0x40000000 -#define IOC_IOCFG28_HYST_EN_BITN 30 -#define IOC_IOCFG28_HYST_EN_M 0x40000000 -#define IOC_IOCFG28_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG28_IE 0x20000000 -#define IOC_IOCFG28_IE_BITN 29 -#define IOC_IOCFG28_IE_M 0x20000000 -#define IOC_IOCFG28_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG28_WU_CFG_W 2 -#define IOC_IOCFG28_WU_CFG_M 0x18000000 -#define IOC_IOCFG28_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG28_IOMODE_W 3 -#define IOC_IOCFG28_IOMODE_M 0x07000000 -#define IOC_IOCFG28_IOMODE_S 24 -#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG28_IOMODE_INV 0x01000000 -#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG28_EDGE_DET_W 2 -#define IOC_IOCFG28_EDGE_DET_M 0x00030000 -#define IOC_IOCFG28_EDGE_DET_S 16 -#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG28_PULL_CTL_W 2 -#define IOC_IOCFG28_PULL_CTL_M 0x00006000 -#define IOC_IOCFG28_PULL_CTL_S 13 -#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG28_SLEW_RED 0x00001000 -#define IOC_IOCFG28_SLEW_RED_BITN 12 -#define IOC_IOCFG28_SLEW_RED_M 0x00001000 -#define IOC_IOCFG28_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG28_IOCURR_W 2 -#define IOC_IOCFG28_IOCURR_M 0x00000C00 -#define IOC_IOCFG28_IOCURR_S 10 -#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG28_IOCURR_4MA 0x00000400 -#define IOC_IOCFG28_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG28_IOSTR_W 2 -#define IOC_IOCFG28_IOSTR_M 0x00000300 -#define IOC_IOCFG28_IOSTR_S 8 -#define IOC_IOCFG28_IOSTR_MAX 0x00000300 -#define IOC_IOCFG28_IOSTR_MED 0x00000200 -#define IOC_IOCFG28_IOSTR_MIN 0x00000100 -#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO28 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG28_PORT_ID_W 6 -#define IOC_IOCFG28_PORT_ID_M 0x0000003F -#define IOC_IOCFG28_PORT_ID_S 0 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG29 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG29_HYST_EN 0x40000000 -#define IOC_IOCFG29_HYST_EN_BITN 30 -#define IOC_IOCFG29_HYST_EN_M 0x40000000 -#define IOC_IOCFG29_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG29_IE 0x20000000 -#define IOC_IOCFG29_IE_BITN 29 -#define IOC_IOCFG29_IE_M 0x20000000 -#define IOC_IOCFG29_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG29_WU_CFG_W 2 -#define IOC_IOCFG29_WU_CFG_M 0x18000000 -#define IOC_IOCFG29_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG29_IOMODE_W 3 -#define IOC_IOCFG29_IOMODE_M 0x07000000 -#define IOC_IOCFG29_IOMODE_S 24 -#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG29_IOMODE_INV 0x01000000 -#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG29_EDGE_DET_W 2 -#define IOC_IOCFG29_EDGE_DET_M 0x00030000 -#define IOC_IOCFG29_EDGE_DET_S 16 -#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG29_PULL_CTL_W 2 -#define IOC_IOCFG29_PULL_CTL_M 0x00006000 -#define IOC_IOCFG29_PULL_CTL_S 13 -#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG29_SLEW_RED 0x00001000 -#define IOC_IOCFG29_SLEW_RED_BITN 12 -#define IOC_IOCFG29_SLEW_RED_M 0x00001000 -#define IOC_IOCFG29_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG29_IOCURR_W 2 -#define IOC_IOCFG29_IOCURR_M 0x00000C00 -#define IOC_IOCFG29_IOCURR_S 10 -#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG29_IOCURR_4MA 0x00000400 -#define IOC_IOCFG29_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG29_IOSTR_W 2 -#define IOC_IOCFG29_IOSTR_M 0x00000300 -#define IOC_IOCFG29_IOSTR_S 8 -#define IOC_IOCFG29_IOSTR_MAX 0x00000300 -#define IOC_IOCFG29_IOSTR_MED 0x00000200 -#define IOC_IOCFG29_IOSTR_MIN 0x00000100 -#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO29 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG29_PORT_ID_W 6 -#define IOC_IOCFG29_PORT_ID_M 0x0000003F -#define IOC_IOCFG29_PORT_ID_S 0 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG30 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG30_HYST_EN 0x40000000 -#define IOC_IOCFG30_HYST_EN_BITN 30 -#define IOC_IOCFG30_HYST_EN_M 0x40000000 -#define IOC_IOCFG30_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG30_IE 0x20000000 -#define IOC_IOCFG30_IE_BITN 29 -#define IOC_IOCFG30_IE_M 0x20000000 -#define IOC_IOCFG30_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG30_WU_CFG_W 2 -#define IOC_IOCFG30_WU_CFG_M 0x18000000 -#define IOC_IOCFG30_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG30_IOMODE_W 3 -#define IOC_IOCFG30_IOMODE_M 0x07000000 -#define IOC_IOCFG30_IOMODE_S 24 -#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG30_IOMODE_INV 0x01000000 -#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG30_EDGE_DET_W 2 -#define IOC_IOCFG30_EDGE_DET_M 0x00030000 -#define IOC_IOCFG30_EDGE_DET_S 16 -#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG30_PULL_CTL_W 2 -#define IOC_IOCFG30_PULL_CTL_M 0x00006000 -#define IOC_IOCFG30_PULL_CTL_S 13 -#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG30_SLEW_RED 0x00001000 -#define IOC_IOCFG30_SLEW_RED_BITN 12 -#define IOC_IOCFG30_SLEW_RED_M 0x00001000 -#define IOC_IOCFG30_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG30_IOCURR_W 2 -#define IOC_IOCFG30_IOCURR_M 0x00000C00 -#define IOC_IOCFG30_IOCURR_S 10 -#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG30_IOCURR_4MA 0x00000400 -#define IOC_IOCFG30_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG30_IOSTR_W 2 -#define IOC_IOCFG30_IOSTR_M 0x00000300 -#define IOC_IOCFG30_IOSTR_S 8 -#define IOC_IOCFG30_IOSTR_MAX 0x00000300 -#define IOC_IOCFG30_IOSTR_MED 0x00000200 -#define IOC_IOCFG30_IOSTR_MIN 0x00000100 -#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO30 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG30_PORT_ID_W 6 -#define IOC_IOCFG30_PORT_ID_M 0x0000003F -#define IOC_IOCFG30_PORT_ID_S 0 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG31 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG31_HYST_EN 0x40000000 -#define IOC_IOCFG31_HYST_EN_BITN 30 -#define IOC_IOCFG31_HYST_EN_M 0x40000000 -#define IOC_IOCFG31_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG31_IE 0x20000000 -#define IOC_IOCFG31_IE_BITN 29 -#define IOC_IOCFG31_IE_M 0x20000000 -#define IOC_IOCFG31_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, i.e. PORT_ID 0x00 -// or >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX ie. PORT_ID -// 0x01-0x08, this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG31_WU_CFG_W 2 -#define IOC_IOCFG31_WU_CFG_M 0x18000000 -#define IOC_IOCFG31_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// N/A for IO configured for AON periph. signals and AUX ie. PORT_ID 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG31_IOMODE_W 3 -#define IOC_IOCFG31_IOMODE_M 0x07000000 -#define IOC_IOCFG31_IOMODE_S 24 -#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG31_IOMODE_INV 0x01000000 -#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG31_EDGE_DET_W 2 -#define IOC_IOCFG31_EDGE_DET_M 0x00030000 -#define IOC_IOCFG31_EDGE_DET_S 16 -#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG31_PULL_CTL_W 2 -#define IOC_IOCFG31_PULL_CTL_M 0x00006000 -#define IOC_IOCFG31_PULL_CTL_S 13 -#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG31_SLEW_RED 0x00001000 -#define IOC_IOCFG31_SLEW_RED_BITN 12 -#define IOC_IOCFG31_SLEW_RED_M 0x00001000 -#define IOC_IOCFG31_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG31_IOCURR_W 2 -#define IOC_IOCFG31_IOCURR_M 0x00000C00 -#define IOC_IOCFG31_IOCURR_S 10 -#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG31_IOCURR_4MA 0x00000400 -#define IOC_IOCFG31_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG31_IOSTR_W 2 -#define IOC_IOCFG31_IOSTR_M 0x00000300 -#define IOC_IOCFG31_IOSTR_S 8 -#define IOC_IOCFG31_IOSTR_MAX 0x00000300 -#define IOC_IOCFG31_IOSTR_MED 0x00000200 -#define IOC_IOCFG31_IOSTR_MIN 0x00000100 -#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO31 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it via registers -// in the EVENT module, e.g. -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// etc -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG31_PORT_ID_W 6 -#define IOC_IOCFG31_PORT_ID_M 0x0000003F -#define IOC_IOCFG31_PORT_ID_S 0 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 - - -#endif // __IOC__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_memmap.h b/third_party/ti/devices/cc26x0/inc/hw_memmap.h deleted file mode 100644 index 7f1b194fe..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_memmap.h +++ /dev/null @@ -1,158 +0,0 @@ -/****************************************************************************** -* Filename: hw_memmap_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following are defines for the base address of the memories and -// peripherals on the CPU_MMAP interface -// -//***************************************************************************** -#define FLASHMEM_BASE 0x00000000 // FLASHMEM -#define BROM_BASE 0x10000000 // BROM -#define GPRAM_BASE 0x11000000 // GPRAM -#define SRAM_BASE 0x20000000 // SRAM -#define RFC_RAM_BASE 0x21000000 // RFC_RAM -#define SSI0_BASE 0x40000000 // SSI -#define UART0_BASE 0x40001000 // UART -#define I2C0_BASE 0x40002000 // I2C -#define SSI1_BASE 0x40008000 // SSI -#define GPT0_BASE 0x40010000 // GPT -#define GPT1_BASE 0x40011000 // GPT -#define GPT2_BASE 0x40012000 // GPT -#define GPT3_BASE 0x40013000 // GPT -#define UDMA0_BASE 0x40020000 // UDMA -#define I2S0_BASE 0x40021000 // I2S -#define GPIO_BASE 0x40022000 // GPIO -#define CRYPTO_BASE 0x40024000 // CRYPTO -#define TRNG_BASE 0x40028000 // TRNG -#define FLASH_BASE 0x40030000 // FLASH -#define VIMS_BASE 0x40034000 // VIMS -#define RFC_PWR_BASE 0x40040000 // RFC_PWR -#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL -#define RFC_RAT_BASE 0x40043000 // RFC_RAT -#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA -#define WDT_BASE 0x40080000 // WDT -#define IOC_BASE 0x40081000 // IOC -#define PRCM_BASE 0x40082000 // PRCM -#define EVENT_BASE 0x40083000 // EVENT -#define SMPH_BASE 0x40084000 // SMPH -#define ADI2_BASE 0x40086000 // ADI -#define ADI3_BASE 0x40086200 // ADI -#define AON_SYSCTL_BASE 0x40090000 // AON_SYSCTL -#define AON_WUC_BASE 0x40091000 // AON_WUC -#define AON_RTC_BASE 0x40092000 // AON_RTC -#define AON_EVENT_BASE 0x40093000 // AON_EVENT -#define AON_IOC_BASE 0x40094000 // AON_IOC -#define AON_BATMON_BASE 0x40095000 // AON_BATMON -#define AUX_AIODIO0_BASE 0x400C1000 // AUX_AIODIO -#define AUX_AIODIO1_BASE 0x400C2000 // AUX_AIODIO -#define AUX_TDC_BASE 0x400C4000 // AUX_TDC -#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL -#define AUX_WUC_BASE 0x400C6000 // AUX_WUC -#define AUX_TIMER_BASE 0x400C7000 // AUX_TIMER -#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH -#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF -#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI -#define AUX_ADI4_BASE 0x400CB000 // ADI -#define AUX_RAM_BASE 0x400E0000 // AUX_RAM -#define AUX_SCE_BASE 0x400E1000 // AUX_SCE -#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP -#define FCFG1_BASE 0x50001000 // FCFG1 -#define FCFG2_BASE 0x50002000 // FCFG2 -#ifndef CCFG_BASE -#define CCFG_BASE 0x50003000 // CCFG -#endif -#define CCFG_BASE_DEFAULT 0x50003000 // CCFG -#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base -#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base -#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base -#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base -#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base -#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base -#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base -#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base -#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base -#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base -#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base -#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base -#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base -#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base -#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base -#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base -#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base -#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base -#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base -#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base -#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base -#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base -#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base -#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base -#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base -#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base -#define AON_SYSCTL_NONBUF_BASE 0x60090000 // AON_SYSCTL CPU nonbuf base -#define AON_WUC_NONBUF_BASE 0x60091000 // AON_WUC CPU nonbuf base -#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base -#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base -#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base -#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base -#define AUX_AIODIO0_NONBUF_BASE \ - 0x600C1000 // AUX_AIODIO CPU nonbuf base -#define AUX_AIODIO1_NONBUF_BASE \ - 0x600C2000 // AUX_AIODIO CPU nonbuf base -#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base -#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base -#define AUX_WUC_NONBUF_BASE 0x600C6000 // AUX_WUC CPU nonbuf base -#define AUX_TIMER_NONBUF_BASE 0x600C7000 // AUX_TIMER CPU nonbuf base -#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base -#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base -#define AUX_DDI0_OSC_NONBUF_BASE \ - 0x600CA000 // DDI CPU nonbuf base -#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base -#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base -#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base -#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base -#define CPU_ITM_BASE 0xE0000000 // CPU_ITM -#define CPU_DWT_BASE 0xE0001000 // CPU_DWT -#define CPU_FPB_BASE 0xE0002000 // CPU_FPB -#define CPU_SCS_BASE 0xE000E000 // CPU_SCS -#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU -#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP -#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE - -#endif // __HW_MEMMAP__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_nvic.h b/third_party/ti/devices/cc26x0/inc/hw_nvic.h deleted file mode 100644 index 15c522472..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_nvic.h +++ /dev/null @@ -1,1026 +0,0 @@ -/****************************************************************************** -* Filename: hw_nvic.h -* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) -* Revision: 42365 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following are defines for the NVIC register addresses. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg -#define NVIC_ACTLR 0xE000E008 // Auxiliary Control -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status - // Register -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg -#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable -#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable -#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable -#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable -#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending -#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending -#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending -#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending -#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit -#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit -#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority -#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority -#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority -#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority -#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority -#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority -#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority -#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority -#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority -#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority -#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority -#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority -#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority -#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority -#define NVIC_CPUID 0xE000ED00 // CPU ID Base -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset -#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset - // Control -#define NVIC_SYS_CTRL 0xE000ED10 // System Control -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control -#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 -#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 -#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size -#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 -#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size - // Alias 1 -#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 -#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size - // Alias 2 -#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 -#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size - // Alias 3 -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTLR register. -// -//***************************************************************************** -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple - // Cycle Instructions - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CURRENT -// register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI11 register. -// -//***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI12 register. -// -//***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI13 register. -// -//***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number -#undef NVIC_INT_CTRL_VEC_PEN_M -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI -#define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault -#define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault -#define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault -#define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault -#define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall -#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV -#define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number -#undef NVIC_INT_CTRL_VEC_ACT_M -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset -#undef NVIC_VTABLE_OFFSET_M -#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset -#define NVIC_VTABLE_OFFSET_S 9 -#undef NVIC_VTABLE_OFFSET_S -#define NVIC_VTABLE_OFFSET_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception - // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and - // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL -// register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending -#define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage - // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy - // State Preservation -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address - // Register Valid -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on - // Floating-Point Lazy State - // Preservation -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_HFAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DEBUG_STAT -// register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_ADDR -// register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read -#define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction - // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available -#define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_prcm.h b/third_party/ti/devices/cc26x0/inc/hw_prcm.h deleted file mode 100644 index fe6e00d67..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_prcm.h +++ /dev/null @@ -1,1636 +0,0 @@ -/****************************************************************************** -* Filename: hw_prcm_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_PRCM_H__ -#define __HW_PRCM_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// PRCM component -// -//***************************************************************************** -// Infrastructure Clock Division Factor For Run Mode -#define PRCM_O_INFRCLKDIVR 0x00000000 - -// Infrastructure Clock Division Factor For Sleep Mode -#define PRCM_O_INFRCLKDIVS 0x00000004 - -// Infrastructure Clock Division Factor For DeepSleep Mode -#define PRCM_O_INFRCLKDIVDS 0x00000008 - -// MCU Voltage Domain Control -#define PRCM_O_VDCTL 0x0000000C - -// Load PRCM Settings To CLKCTRL Power Domain -#define PRCM_O_CLKLOADCTL 0x00000028 - -// RFC Clock Gate -#define PRCM_O_RFCCLKG 0x0000002C - -// VIMS Clock Gate -#define PRCM_O_VIMSCLKG 0x00000030 - -// TRNG, CRYPTO And UDMA Clock Gate For Run Mode -#define PRCM_O_SECDMACLKGR 0x0000003C - -// TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode -#define PRCM_O_SECDMACLKGS 0x00000040 - -// TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode -#define PRCM_O_SECDMACLKGDS 0x00000044 - -// GPIO Clock Gate For Run Mode -#define PRCM_O_GPIOCLKGR 0x00000048 - -// GPIO Clock Gate For Sleep Mode -#define PRCM_O_GPIOCLKGS 0x0000004C - -// GPIO Clock Gate For Deep Sleep Mode -#define PRCM_O_GPIOCLKGDS 0x00000050 - -// GPT Clock Gate For Run Mode -#define PRCM_O_GPTCLKGR 0x00000054 - -// GPT Clock Gate For Sleep Mode -#define PRCM_O_GPTCLKGS 0x00000058 - -// GPT Clock Gate For Deep Sleep Mode -#define PRCM_O_GPTCLKGDS 0x0000005C - -// I2C Clock Gate For Run Mode -#define PRCM_O_I2CCLKGR 0x00000060 - -// I2C Clock Gate For Sleep Mode -#define PRCM_O_I2CCLKGS 0x00000064 - -// I2C Clock Gate For Deep Sleep Mode -#define PRCM_O_I2CCLKGDS 0x00000068 - -// UART Clock Gate For Run Mode -#define PRCM_O_UARTCLKGR 0x0000006C - -// UART Clock Gate For Sleep Mode -#define PRCM_O_UARTCLKGS 0x00000070 - -// UART Clock Gate For Deep Sleep Mode -#define PRCM_O_UARTCLKGDS 0x00000074 - -// SSI Clock Gate For Run Mode -#define PRCM_O_SSICLKGR 0x00000078 - -// SSI Clock Gate For Sleep Mode -#define PRCM_O_SSICLKGS 0x0000007C - -// SSI Clock Gate For Deep Sleep Mode -#define PRCM_O_SSICLKGDS 0x00000080 - -// I2S Clock Gate For Run Mode -#define PRCM_O_I2SCLKGR 0x00000084 - -// I2S Clock Gate For Sleep Mode -#define PRCM_O_I2SCLKGS 0x00000088 - -// I2S Clock Gate For Deep Sleep Mode -#define PRCM_O_I2SCLKGDS 0x0000008C - -// Internal -#define PRCM_O_CPUCLKDIV 0x000000B8 - -// I2S Clock Control -#define PRCM_O_I2SBCLKSEL 0x000000C8 - -// GPT Scalar -#define PRCM_O_GPTCLKDIV 0x000000CC - -// I2S Clock Control -#define PRCM_O_I2SCLKCTL 0x000000D0 - -// MCLK Division Ratio -#define PRCM_O_I2SMCLKDIV 0x000000D4 - -// BCLK Division Ratio -#define PRCM_O_I2SBCLKDIV 0x000000D8 - -// WCLK Division Ratio -#define PRCM_O_I2SWCLKDIV 0x000000DC - -// SW Initiated Resets -#define PRCM_O_SWRESET 0x0000010C - -// WARM Reset Control And Status -#define PRCM_O_WARMRESET 0x00000110 - -// Power Domain Control -#define PRCM_O_PDCTL0 0x0000012C - -// RFC Power Domain Control -#define PRCM_O_PDCTL0RFC 0x00000130 - -// SERIAL Power Domain Control -#define PRCM_O_PDCTL0SERIAL 0x00000134 - -// PERIPH Power Domain Control -#define PRCM_O_PDCTL0PERIPH 0x00000138 - -// Power Domain Status -#define PRCM_O_PDSTAT0 0x00000140 - -// RFC Power Domain Status -#define PRCM_O_PDSTAT0RFC 0x00000144 - -// SERIAL Power Domain Status -#define PRCM_O_PDSTAT0SERIAL 0x00000148 - -// PERIPH Power Domain Status -#define PRCM_O_PDSTAT0PERIPH 0x0000014C - -// Power Domain Control -#define PRCM_O_PDCTL1 0x0000017C - -// CPU Power Domain Direct Control -#define PRCM_O_PDCTL1CPU 0x00000184 - -// RFC Power Domain Direct Control -#define PRCM_O_PDCTL1RFC 0x00000188 - -// VIMS Mode Direct Control -#define PRCM_O_PDCTL1VIMS 0x0000018C - -// Power Manager Status -#define PRCM_O_PDSTAT1 0x00000194 - -// BUS Power Domain Direct Read Status -#define PRCM_O_PDSTAT1BUS 0x00000198 - -// RFC Power Domain Direct Read Status -#define PRCM_O_PDSTAT1RFC 0x0000019C - -// CPU Power Domain Direct Read Status -#define PRCM_O_PDSTAT1CPU 0x000001A0 - -// VIMS Mode Direct Read Status -#define PRCM_O_PDSTAT1VIMS 0x000001A4 - -// Control To RFC -#define PRCM_O_RFCBITS 0x000001CC - -// Selected RFC Mode -#define PRCM_O_RFCMODESEL 0x000001D0 - -// Allowed RFC Modes -#define PRCM_O_RFCMODEHWOPT 0x000001D4 - -// Power Profiler Register -#define PRCM_O_PWRPROFSTAT 0x000001E0 - -// Memory Retention Control -#define PRCM_O_RAMRETEN 0x00000224 - -//***************************************************************************** -// -// Register: PRCM_O_INFRCLKDIVR -// -//***************************************************************************** -// Field: [1:0] RATIO -// -// Division rate for clocks driving modules in the MCU_AON domain when system -// CPU is in run mode. Division ratio affects both infrastructure clock and -// perbusull clock. -// ENUMs: -// DIV32 Divide by 32 -// DIV8 Divide by 8 -// DIV2 Divide by 2 -// DIV1 Divide by 1 -#define PRCM_INFRCLKDIVR_RATIO_W 2 -#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVR_RATIO_S 0 -#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_INFRCLKDIVS -// -//***************************************************************************** -// Field: [1:0] RATIO -// -// Division rate for clocks driving modules in the MCU_AON domain when system -// CPU is in sleep mode. Division ratio affects both infrastructure clock and -// perbusull clock. -// ENUMs: -// DIV32 Divide by 32 -// DIV8 Divide by 8 -// DIV2 Divide by 2 -// DIV1 Divide by 1 -#define PRCM_INFRCLKDIVS_RATIO_W 2 -#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVS_RATIO_S 0 -#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_INFRCLKDIVDS -// -//***************************************************************************** -// Field: [1:0] RATIO -// -// Division rate for clocks driving modules in the MCU_AON domain when system -// CPU is in seepsleep mode. Division ratio affects both infrastructure clock -// and perbusull clock. -// ENUMs: -// DIV32 Divide by 32 -// DIV8 Divide by 8 -// DIV2 Divide by 2 -// DIV1 Divide by 1 -#define PRCM_INFRCLKDIVDS_RATIO_W 2 -#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVDS_RATIO_S 0 -#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_VDCTL -// -//***************************************************************************** -// Field: [2] MCU_VD -// -// Request WUC to power down the MCU voltage domain -// -// 0: No request -// 1: Assert request when possible. An asserted power down request will result -// in a boot of the MCU system when powered up again. -// -// The bit will have no effect before the following requirements are met: -// 1. PDCTL1.CPU_ON = 0 -// 2. PDCTL1.VIMS_MODE = 0 -// 3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with -// CLKLOADCTL.LOAD) -// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with -// CLKLOADCTL.LOAD) -// 5. RFC do no request access to BUS -// 6. System CPU in deepsleep -#define PRCM_VDCTL_MCU_VD 0x00000004 -#define PRCM_VDCTL_MCU_VD_BITN 2 -#define PRCM_VDCTL_MCU_VD_M 0x00000004 -#define PRCM_VDCTL_MCU_VD_S 2 - -// Field: [0] ULDO -// -// Request WUC to switch to uLDO. -// -// 0: No request -// 1: Assert request when possible -// -// The bit will have no effect before the following requirements are met: -// 1. PDCTL1.CPU_ON = 0 -// 2. PDCTL1.VIMS_MODE = 0 -// 3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with -// CLKLOADCTL.LOAD) -// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with -// CLKLOADCTL.LOAD) -// 5. RFC do no request access to BUS -// 6. System CPU in deepsleep -#define PRCM_VDCTL_ULDO 0x00000001 -#define PRCM_VDCTL_ULDO_BITN 0 -#define PRCM_VDCTL_ULDO_M 0x00000001 -#define PRCM_VDCTL_ULDO_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_CLKLOADCTL -// -//***************************************************************************** -// Field: [1] LOAD_DONE -// -// Status of LOAD. -// Will be cleared to 0 when any of the registers requiring a LOAD is written -// to, and be set to 1 when a LOAD is done. -// Note that writing no change to a register will result in the LOAD_DONE being -// cleared. -// -// 0 : One or more registers have been write accessed after last LOAD -// 1 : No registers are write accessed after last LOAD -#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 -#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 -#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 -#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 - -// Field: [0] LOAD -// -// 0: No action -// 1: Load settings to CLKCTRL. Bit is HW cleared. -// -// Multiple changes to settings may be done before LOAD is written once so all -// changes takes place at the same time. LOAD can also be done after single -// setting updates. -// -// Registers that needs to be followed by LOAD before settings being applied -// are: -// - RFCCLKG -// - VIMSCLKG -// - SECDMACLKGR -// - SECDMACLKGS -// - SECDMACLKGDS -// - GPIOCLKGR -// - GPIOCLKGS -// - GPIOCLKGDS -// - GPTCLKGR -// - GPTCLKGS -// - GPTCLKGDS -// - GPTCLKDIV -// - I2CCLKGR -// - I2CCLKGS -// - I2CCLKGDS -// - SSICLKGR -// - SSICLKGS -// - SSICLKGDS -// - UARTCLKGR -// - UARTCLKGS -// - UARTCLKGDS -// - I2SCLKGR -// - I2SCLKGS -// - I2SCLKGDS -// - I2SBCLKSEL -// - I2SCLKCTL -// - I2SMCLKDIV -// - I2SBCLKDIV -// - I2SWCLKDIV -#define PRCM_CLKLOADCTL_LOAD 0x00000001 -#define PRCM_CLKLOADCTL_LOAD_BITN 0 -#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 -#define PRCM_CLKLOADCTL_LOAD_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RFCCLKG -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock if RFC power domain is on -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_RFCCLKG_CLK_EN 0x00000001 -#define PRCM_RFCCLKG_CLK_EN_BITN 0 -#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 -#define PRCM_RFCCLKG_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_VIMSCLKG -// -//***************************************************************************** -// Field: [1:0] CLK_EN -// -// -// 00: Disable clock -// 01: Disable clock when system CPU is in DeepSleep -// 11: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_VIMSCLKG_CLK_EN_W 2 -#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 -#define PRCM_VIMSCLKG_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_SECDMACLKGR -// -//***************************************************************************** -// Field: [8] DMA_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 - -// Field: [1] TRNG_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 - -// Field: [0] CRYPTO_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_SECDMACLKGS -// -//***************************************************************************** -// Field: [8] DMA_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 - -// Field: [1] TRNG_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 - -// Field: [0] CRYPTO_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_SECDMACLKGDS -// -//***************************************************************************** -// Field: [8] DMA_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 - -// Field: [1] TRNG_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 - -// Field: [0] CRYPTO_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_GPIOCLKGR -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGR_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_GPIOCLKGS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_GPIOCLKGDS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGDS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_GPTCLKGR -// -//***************************************************************************** -// Field: [3:0] CLK_EN -// -// Each bit below has the following meaning: -// -// 0: Disable clock -// 1: Enable clock -// -// ENUMs can be combined -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// GPT3 Enable clock for GPT3 -// GPT2 Enable clock for GPT2 -// GPT1 Enable clock for GPT1 -// GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGR_CLK_EN_W 4 -#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGR_CLK_EN_S 0 -#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_GPTCLKGS -// -//***************************************************************************** -// Field: [3:0] CLK_EN -// -// Each bit below has the following meaning: -// -// 0: Disable clock -// 1: Enable clock -// -// ENUMs can be combined -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// GPT3 Enable clock for GPT3 -// GPT2 Enable clock for GPT2 -// GPT1 Enable clock for GPT1 -// GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGS_CLK_EN_W 4 -#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGS_CLK_EN_S 0 -#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_GPTCLKGDS -// -//***************************************************************************** -// Field: [3:0] CLK_EN -// -// Each bit below has the following meaning: -// -// 0: Disable clock -// 1: Enable clock -// -// ENUMs can be combined -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// GPT3 Enable clock for GPT3 -// GPT2 Enable clock for GPT2 -// GPT1 Enable clock for GPT1 -// GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGDS_CLK_EN_W 4 -#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGDS_CLK_EN_S 0 -#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_I2CCLKGR -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGR_CLK_EN 0x00000001 -#define PRCM_I2CCLKGR_CLK_EN_BITN 0 -#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGR_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2CCLKGS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGS_CLK_EN 0x00000001 -#define PRCM_I2CCLKGS_CLK_EN_BITN 0 -#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2CCLKGDS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 -#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 -#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGDS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_UARTCLKGR -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_UARTCLKGR_CLK_EN 0x00000001 -#define PRCM_UARTCLKGR_CLK_EN_BITN 0 -#define PRCM_UARTCLKGR_CLK_EN_M 0x00000001 -#define PRCM_UARTCLKGR_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_UARTCLKGS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_UARTCLKGS_CLK_EN 0x00000001 -#define PRCM_UARTCLKGS_CLK_EN_BITN 0 -#define PRCM_UARTCLKGS_CLK_EN_M 0x00000001 -#define PRCM_UARTCLKGS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_UARTCLKGDS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_UARTCLKGDS_CLK_EN 0x00000001 -#define PRCM_UARTCLKGDS_CLK_EN_BITN 0 -#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_UARTCLKGDS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_SSICLKGR -// -//***************************************************************************** -// Field: [1:0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// SSI1 Enable clock for SSI1 -// SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGR_CLK_EN_W 2 -#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGR_CLK_EN_S 0 -#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_SSICLKGS -// -//***************************************************************************** -// Field: [1:0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// SSI1 Enable clock for SSI1 -// SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGS_CLK_EN_W 2 -#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGS_CLK_EN_S 0 -#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_SSICLKGDS -// -//***************************************************************************** -// Field: [1:0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// SSI1 Enable clock for SSI1 -// SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGDS_CLK_EN_W 2 -#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGDS_CLK_EN_S 0 -#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_I2SCLKGR -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGR_CLK_EN 0x00000001 -#define PRCM_I2SCLKGR_CLK_EN_BITN 0 -#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGR_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2SCLKGS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGS_CLK_EN 0x00000001 -#define PRCM_I2SCLKGS_CLK_EN_BITN 0 -#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2SCLKGDS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 -#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 -#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGDS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_CPUCLKDIV -// -//***************************************************************************** -// Field: [0] RATIO -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// DIV2 Internal. Only to be used through TI provided API. -// DIV1 Internal. Only to be used through TI provided API. -#define PRCM_CPUCLKDIV_RATIO 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_BITN 0 -#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_S 0 -#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_I2SBCLKSEL -// -//***************************************************************************** -// Field: [0] SRC -// -// BCLK source selector -// -// 0: Use external BCLK -// 1: Use internally generated clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SBCLKSEL_SRC 0x00000001 -#define PRCM_I2SBCLKSEL_SRC_BITN 0 -#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 -#define PRCM_I2SBCLKSEL_SRC_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_GPTCLKDIV -// -//***************************************************************************** -// Field: [3:0] RATIO -// -// Scalar used for GPTs. The division rate will be constant and ungated for Run -// / Sleep / DeepSleep mode. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// Other values are not supported. -// ENUMs: -// DIV256 Divide by 256 -// DIV128 Divide by 128 -// DIV64 Divide by 64 -// DIV32 Divide by 32 -// DIV16 Divide by 16 -// DIV8 Divide by 8 -// DIV4 Divide by 4 -// DIV2 Divide by 2 -// DIV1 Divide by 1 -#define PRCM_GPTCLKDIV_RATIO_W 4 -#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F -#define PRCM_GPTCLKDIV_RATIO_S 0 -#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 -#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 -#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 -#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 -#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 -#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 -#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 -#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_I2SCLKCTL -// -//***************************************************************************** -// Field: [3] SMPL_ON_POSEDGE -// -// On the I2S serial interface, data and WCLK is sampled and clocked out on -// opposite edges of BCLK. -// -// 0 - data and WCLK are sampled on the negative edge and clocked out on the -// positive edge. -// 1 - data and WCLK are sampled on the positive edge and clocked out on the -// negative edge. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 - -// Field: [2:1] WCLK_PHASE -// -// Decides how the WCLK division ratio is calculated and used to generate -// different duty cycles (See I2SWCLKDIV.WDIV). -// -// 0: Single phase -// 1: Dual phase -// 2: User Defined -// 3: Reserved/Undefined -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 -#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 -#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 - -// Field: [0] EN -// -// -// 0: MCLK, BCLK and **WCLK** will be static low -// 1: Enables the generation of MCLK, BCLK and WCLK -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_EN 0x00000001 -#define PRCM_I2SCLKCTL_EN_BITN 0 -#define PRCM_I2SCLKCTL_EN_M 0x00000001 -#define PRCM_I2SCLKCTL_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2SMCLKDIV -// -//***************************************************************************** -// Field: [9:0] MDIV -// -// An unsigned factor of the division ratio used to generate MCLK [2-1024]: -// -// MCLK = MCUCLK/MDIV[Hz] -// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined -// by AON_WUC:MCUCLK.PWR_DWN_SRC -// -// A value of 0 is interpreted as 1024. -// A value of 1 is invalid. -// If MDIV is odd the low phase of the clock is one MCUCLK period longer than -// the high phase. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SMCLKDIV_MDIV_W 10 -#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF -#define PRCM_I2SMCLKDIV_MDIV_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2SBCLKDIV -// -//***************************************************************************** -// Field: [9:0] BDIV -// -// An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: -// -// BCLK = MCUCLK/BDIV[Hz] -// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined -// by AON_WUC:MCUCLK.PWR_DWN_SRC -// -// A value of 0 is interpreted as 1024. -// A value of 1 is invalid. -// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock -// is one MCUCLK period longer than the high phase. -// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the -// clock is one MCUCLK period longer than the low phase. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SBCLKDIV_BDIV_W 10 -#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF -#define PRCM_I2SBCLKDIV_BDIV_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2SWCLKDIV -// -//***************************************************************************** -// Field: [15:0] WDIV -// -// If I2SCLKCTL.WCLK_PHASE = 0, Single phase. -// WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK -// periods. -// -// WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] -// MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined -// by AON_WUC:MCUCLK.PWR_DWN_SRC -// -// If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. -// Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK -// periods. -// -// WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] -// -// If I2SCLKCTL.WCLK_PHASE = 2, User defined. -// WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] -// (unsigned, [1-255]) BCLK periods. -// -// WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SWCLKDIV_WDIV_W 16 -#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF -#define PRCM_I2SWCLKDIV_WDIV_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_SWRESET -// -//***************************************************************************** -// Field: [2] MCU -// -// Internal. Only to be used through TI provided API. -#define PRCM_SWRESET_MCU 0x00000004 -#define PRCM_SWRESET_MCU_BITN 2 -#define PRCM_SWRESET_MCU_M 0x00000004 -#define PRCM_SWRESET_MCU_S 2 - -//***************************************************************************** -// -// Register: PRCM_O_WARMRESET -// -//***************************************************************************** -// Field: [2] WR_TO_PINRESET -// -// 0: No action -// 1: A warm system reset event triggered by the below listed sources will -// result in an emulated pin reset. -// -// Warm reset sources included: -// ICEPick sysreset -// System CPU reset request, CPU_SCS:AIRCR.SYSRESETREQ -// System CPU Lockup -// WDT timeout -// -// An active ICEPick block system reset will gate all sources except ICEPick -// sysreset -// -// SW can read AON_SYSCTL:RESETCTL.RESET_SRC to find the source of the last -// reset resulting in a full power up sequence. WARMRESET in this register is -// set in the scenario that WR_TO_PINRESET=1 and one of the above listed -// sources is triggered. -#define PRCM_WARMRESET_WR_TO_PINRESET 0x00000004 -#define PRCM_WARMRESET_WR_TO_PINRESET_BITN 2 -#define PRCM_WARMRESET_WR_TO_PINRESET_M 0x00000004 -#define PRCM_WARMRESET_WR_TO_PINRESET_S 2 - -// Field: [1] LOCKUP_STAT -// -// -// 0: No registred event -// 1: A system CPU LOCKUP event has occured since last SW clear of the -// register. -// -// A read of this register clears both WDT_STAT and LOCKUP_STAT. -#define PRCM_WARMRESET_LOCKUP_STAT 0x00000002 -#define PRCM_WARMRESET_LOCKUP_STAT_BITN 1 -#define PRCM_WARMRESET_LOCKUP_STAT_M 0x00000002 -#define PRCM_WARMRESET_LOCKUP_STAT_S 1 - -// Field: [0] WDT_STAT -// -// -// 0: No registered event -// 1: A WDT event has occured since last SW clear of the register. -// -// A read of this register clears both WDT_STAT and LOCKUP_STAT. -#define PRCM_WARMRESET_WDT_STAT 0x00000001 -#define PRCM_WARMRESET_WDT_STAT_BITN 0 -#define PRCM_WARMRESET_WDT_STAT_M 0x00000001 -#define PRCM_WARMRESET_WDT_STAT_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL0 -// -//***************************************************************************** -// Field: [2] PERIPH_ON -// -// PERIPH Power domain. -// -// 0: PERIPH power domain is powered down -// 1: PERIPH power domain is powered up -#define PRCM_PDCTL0_PERIPH_ON 0x00000004 -#define PRCM_PDCTL0_PERIPH_ON_BITN 2 -#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 -#define PRCM_PDCTL0_PERIPH_ON_S 2 - -// Field: [1] SERIAL_ON -// -// SERIAL Power domain. -// -// 0: SERIAL power domain is powered down -// 1: SERIAL power domain is powered up -#define PRCM_PDCTL0_SERIAL_ON 0x00000002 -#define PRCM_PDCTL0_SERIAL_ON_BITN 1 -#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 -#define PRCM_PDCTL0_SERIAL_ON_S 1 - -// Field: [0] RFC_ON -// -// -// 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 -// 1: RFC power domain powered on -#define PRCM_PDCTL0_RFC_ON 0x00000001 -#define PRCM_PDCTL0_RFC_ON_BITN 0 -#define PRCM_PDCTL0_RFC_ON_M 0x00000001 -#define PRCM_PDCTL0_RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL0RFC -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDCTL0.RFC_ON -#define PRCM_PDCTL0RFC_ON 0x00000001 -#define PRCM_PDCTL0RFC_ON_BITN 0 -#define PRCM_PDCTL0RFC_ON_M 0x00000001 -#define PRCM_PDCTL0RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL0SERIAL -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDCTL0.SERIAL_ON -#define PRCM_PDCTL0SERIAL_ON 0x00000001 -#define PRCM_PDCTL0SERIAL_ON_BITN 0 -#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 -#define PRCM_PDCTL0SERIAL_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL0PERIPH -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDCTL0.PERIPH_ON -#define PRCM_PDCTL0PERIPH_ON 0x00000001 -#define PRCM_PDCTL0PERIPH_ON_BITN 0 -#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 -#define PRCM_PDCTL0PERIPH_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT0 -// -//***************************************************************************** -// Field: [2] PERIPH_ON -// -// PERIPH Power domain. -// -// 0: Domain may be powered down -// 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 -#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 -#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 -#define PRCM_PDSTAT0_PERIPH_ON_S 2 - -// Field: [1] SERIAL_ON -// -// SERIAL Power domain. -// -// 0: Domain may be powered down -// 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 -#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 -#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 -#define PRCM_PDSTAT0_SERIAL_ON_S 1 - -// Field: [0] RFC_ON -// -// RFC Power domain -// -// 0: Domain may be powered down -// 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_RFC_ON 0x00000001 -#define PRCM_PDSTAT0_RFC_ON_BITN 0 -#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 -#define PRCM_PDSTAT0_RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT0RFC -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDSTAT0.RFC_ON -#define PRCM_PDSTAT0RFC_ON 0x00000001 -#define PRCM_PDSTAT0RFC_ON_BITN 0 -#define PRCM_PDSTAT0RFC_ON_M 0x00000001 -#define PRCM_PDSTAT0RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT0SERIAL -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDSTAT0.SERIAL_ON -#define PRCM_PDSTAT0SERIAL_ON 0x00000001 -#define PRCM_PDSTAT0SERIAL_ON_BITN 0 -#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 -#define PRCM_PDSTAT0SERIAL_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT0PERIPH -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDSTAT0.PERIPH_ON -#define PRCM_PDSTAT0PERIPH_ON 0x00000001 -#define PRCM_PDSTAT0PERIPH_ON_BITN 0 -#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 -#define PRCM_PDSTAT0PERIPH_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL1 -// -//***************************************************************************** -// Field: [3] VIMS_MODE -// -// -// 0: VIMS power domain is only powered when CPU power domain is powered. -// 1: VIMS power domain is powered whenever the BUS power domain is powered. -#define PRCM_PDCTL1_VIMS_MODE 0x00000008 -#define PRCM_PDCTL1_VIMS_MODE_BITN 3 -#define PRCM_PDCTL1_VIMS_MODE_M 0x00000008 -#define PRCM_PDCTL1_VIMS_MODE_S 3 - -// Field: [2] RFC_ON -// -// -// 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 -// 1: RFC power domain powered on -// -// Bit shall be used by RFC in autonomus mode but there is no HW restrictions -// fom system CPU to access the bit. -#define PRCM_PDCTL1_RFC_ON 0x00000004 -#define PRCM_PDCTL1_RFC_ON_BITN 2 -#define PRCM_PDCTL1_RFC_ON_M 0x00000004 -#define PRCM_PDCTL1_RFC_ON_S 2 - -// Field: [1] CPU_ON -// -// -// 0: Causes a power down of the CPU power domain when system CPU indicates it -// is idle. -// 1: Initiates power-on of the CPU power domain. -// -// This bit is automatically set by a WIC power-on event. -#define PRCM_PDCTL1_CPU_ON 0x00000002 -#define PRCM_PDCTL1_CPU_ON_BITN 1 -#define PRCM_PDCTL1_CPU_ON_M 0x00000002 -#define PRCM_PDCTL1_CPU_ON_S 1 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL1CPU -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDCTL1.CPU_ON -#define PRCM_PDCTL1CPU_ON 0x00000001 -#define PRCM_PDCTL1CPU_ON_BITN 0 -#define PRCM_PDCTL1CPU_ON_M 0x00000001 -#define PRCM_PDCTL1CPU_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL1RFC -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDCTL1.RFC_ON -#define PRCM_PDCTL1RFC_ON 0x00000001 -#define PRCM_PDCTL1RFC_ON_BITN 0 -#define PRCM_PDCTL1RFC_ON_M 0x00000001 -#define PRCM_PDCTL1RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL1VIMS -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDCTL1.VIMS_MODE -#define PRCM_PDCTL1VIMS_ON 0x00000001 -#define PRCM_PDCTL1VIMS_ON_BITN 0 -#define PRCM_PDCTL1VIMS_ON_M 0x00000001 -#define PRCM_PDCTL1VIMS_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT1 -// -//***************************************************************************** -// Field: [4] BUS_ON -// -// -// 0: BUS domain not accessible -// 1: BUS domain is currently accessible -#define PRCM_PDSTAT1_BUS_ON 0x00000010 -#define PRCM_PDSTAT1_BUS_ON_BITN 4 -#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 -#define PRCM_PDSTAT1_BUS_ON_S 4 - -// Field: [3] VIMS_MODE -// -// -// 0: VIMS domain not accessible -// 1: VIMS domain is currently accessible -#define PRCM_PDSTAT1_VIMS_MODE 0x00000008 -#define PRCM_PDSTAT1_VIMS_MODE_BITN 3 -#define PRCM_PDSTAT1_VIMS_MODE_M 0x00000008 -#define PRCM_PDSTAT1_VIMS_MODE_S 3 - -// Field: [2] RFC_ON -// -// -// 0: RFC domain not accessible -// 1: RFC domain is currently accessible -#define PRCM_PDSTAT1_RFC_ON 0x00000004 -#define PRCM_PDSTAT1_RFC_ON_BITN 2 -#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 -#define PRCM_PDSTAT1_RFC_ON_S 2 - -// Field: [1] CPU_ON -// -// -// 0: CPU and BUS domain not accessible -// 1: CPU and BUS domains are both currently accessible -#define PRCM_PDSTAT1_CPU_ON 0x00000002 -#define PRCM_PDSTAT1_CPU_ON_BITN 1 -#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 -#define PRCM_PDSTAT1_CPU_ON_S 1 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT1BUS -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDSTAT1.BUS_ON -#define PRCM_PDSTAT1BUS_ON 0x00000001 -#define PRCM_PDSTAT1BUS_ON_BITN 0 -#define PRCM_PDSTAT1BUS_ON_M 0x00000001 -#define PRCM_PDSTAT1BUS_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT1RFC -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDSTAT1.RFC_ON -#define PRCM_PDSTAT1RFC_ON 0x00000001 -#define PRCM_PDSTAT1RFC_ON_BITN 0 -#define PRCM_PDSTAT1RFC_ON_M 0x00000001 -#define PRCM_PDSTAT1RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT1CPU -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDSTAT1.CPU_ON -#define PRCM_PDSTAT1CPU_ON 0x00000001 -#define PRCM_PDSTAT1CPU_ON_BITN 0 -#define PRCM_PDSTAT1CPU_ON_M 0x00000001 -#define PRCM_PDSTAT1CPU_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT1VIMS -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDSTAT1.VIMS_MODE -#define PRCM_PDSTAT1VIMS_ON 0x00000001 -#define PRCM_PDSTAT1VIMS_ON_BITN 0 -#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 -#define PRCM_PDSTAT1VIMS_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RFCBITS -// -//***************************************************************************** -// Field: [31:0] READ -// -// Control bits for RFC. The RF core CPE processor will automatically check -// this register when it boots, and it can be used to immediately instruct CPE -// to perform some tasks at its start-up. The supported functionality is -// ROM-defined and may vary. See the technical reference manual for more -// details. -#define PRCM_RFCBITS_READ_W 32 -#define PRCM_RFCBITS_READ_M 0xFFFFFFFF -#define PRCM_RFCBITS_READ_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RFCMODESEL -// -//***************************************************************************** -// Field: [2:0] CURR -// -// Selects the set of commands that the RFC will accept. Only modes permitted -// by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for -// details. -// ENUMs: -// MODE7 Select Mode 7 -// MODE6 Select Mode 6 -// MODE5 Select Mode 5 -// MODE4 Select Mode 4 -// MODE3 Select Mode 3 -// MODE2 Select Mode 2 -// MODE1 Select Mode 1 -// MODE0 Select Mode 0 -#define PRCM_RFCMODESEL_CURR_W 3 -#define PRCM_RFCMODESEL_CURR_M 0x00000007 -#define PRCM_RFCMODESEL_CURR_S 0 -#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 -#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 -#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 -#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 -#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 -#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 -#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 -#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_RFCMODEHWOPT -// -//***************************************************************************** -// Field: [7:0] AVAIL -// -// Permitted RFC modes. More than one mode can be permitted. -// ENUMs: -// MODE7 Mode 7 permitted -// MODE6 Mode 6 permitted -// MODE5 Mode 5 permitted -// MODE4 Mode 4 permitted -// MODE3 Mode 3 permitted -// MODE2 Mode 2 permitted -// MODE1 Mode 1 permitted -// MODE0 Mode 0 permitted -#define PRCM_RFCMODEHWOPT_AVAIL_W 8 -#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF -#define PRCM_RFCMODEHWOPT_AVAIL_S 0 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_PWRPROFSTAT -// -//***************************************************************************** -// Field: [7:0] VALUE -// -// SW can use these bits to timestamp the application. These bits are also -// available through the testtap and can thus be used by the emulator to -// profile in real time. -#define PRCM_PWRPROFSTAT_VALUE_W 8 -#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF -#define PRCM_PWRPROFSTAT_VALUE_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RAMRETEN -// -//***************************************************************************** -// Field: [2] RFC -// -// -// 0: Retention for RFC SRAM disabled -// 1: Retention for RFC SRAM enabled -// -// Memories controlled: CPERAM MCERAM RFERAM -#define PRCM_RAMRETEN_RFC 0x00000004 -#define PRCM_RAMRETEN_RFC_BITN 2 -#define PRCM_RAMRETEN_RFC_M 0x00000004 -#define PRCM_RAMRETEN_RFC_S 2 - -// Field: [1:0] VIMS -// -// -// 0: Memory retention disabled -// 1: Memory retention enabled -// -// Bit 0: VIMS_TRAM -// Bit 1: VIMS_CRAM -// -// Legal modes depend on settings in VIMS:CTL.MODE -// -// 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to -// CACHE or SPLIT mode after waking up again -// 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in -// GPRAM mode after wake up, alternatively select OFF mode first and then CACHE -// or SPILT mode. -// 10: Illegal mode -// 11: No restrictions -#define PRCM_RAMRETEN_VIMS_W 2 -#define PRCM_RAMRETEN_VIMS_M 0x00000003 -#define PRCM_RAMRETEN_VIMS_S 0 - - -#endif // __PRCM__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_rfc_dbell.h b/third_party/ti/devices/cc26x0/inc/hw_rfc_dbell.h deleted file mode 100644 index 0cb01e35d..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_rfc_dbell.h +++ /dev/null @@ -1,1671 +0,0 @@ -/****************************************************************************** -* Filename: hw_rfc_dbell_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_RFC_DBELL_H__ -#define __HW_RFC_DBELL_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// RFC_DBELL component -// -//***************************************************************************** -// Doorbell Command Register -#define RFC_DBELL_O_CMDR 0x00000000 - -// Doorbell Command Status Register -#define RFC_DBELL_O_CMDSTA 0x00000004 - -// Interrupt Flags From RF Hardware Modules -#define RFC_DBELL_O_RFHWIFG 0x00000008 - -// Interrupt Enable For RF Hardware Modules -#define RFC_DBELL_O_RFHWIEN 0x0000000C - -// Interrupt Flags For Command and Packet Engine Generated Interrupts -#define RFC_DBELL_O_RFCPEIFG 0x00000010 - -// Interrupt Enable For Command and Packet Engine Generated Interrupts -#define RFC_DBELL_O_RFCPEIEN 0x00000014 - -// Interrupt Vector Selection For Command and Packet Engine Generated -// Interrupts -#define RFC_DBELL_O_RFCPEISL 0x00000018 - -// Doorbell Command Acknowledgement Interrupt Flag -#define RFC_DBELL_O_RFACKIFG 0x0000001C - -// RF Core General Purpose Output Control -#define RFC_DBELL_O_SYSGPOCTL 0x00000020 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_CMDR -// -//***************************************************************************** -// Field: [31:0] CMD -// -// Command register. Raises an interrupt to the Command and packet engine (CPE) -// upon write. -#define RFC_DBELL_CMDR_CMD_W 32 -#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF -#define RFC_DBELL_CMDR_CMD_S 0 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_CMDSTA -// -//***************************************************************************** -// Field: [31:0] STAT -// -// Status of the last command used -#define RFC_DBELL_CMDSTA_STAT_W 32 -#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF -#define RFC_DBELL_CMDSTA_STAT_S 0 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFHWIFG -// -//***************************************************************************** -// Field: [19] RATCH7 -// -// Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 -#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 -#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 -#define RFC_DBELL_RFHWIFG_RATCH7_S 19 - -// Field: [18] RATCH6 -// -// Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 -#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 -#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 -#define RFC_DBELL_RFHWIFG_RATCH6_S 18 - -// Field: [17] RATCH5 -// -// Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 -#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 -#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 -#define RFC_DBELL_RFHWIFG_RATCH5_S 17 - -// Field: [16] RATCH4 -// -// Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 -#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 -#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 -#define RFC_DBELL_RFHWIFG_RATCH4_S 16 - -// Field: [15] RATCH3 -// -// Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 -#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 -#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 -#define RFC_DBELL_RFHWIFG_RATCH3_S 15 - -// Field: [14] RATCH2 -// -// Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 -#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 -#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 -#define RFC_DBELL_RFHWIFG_RATCH2_S 14 - -// Field: [13] RATCH1 -// -// Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 -#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 -#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 -#define RFC_DBELL_RFHWIFG_RATCH1_S 13 - -// Field: [12] RATCH0 -// -// Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 -#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 -#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 -#define RFC_DBELL_RFHWIFG_RATCH0_S 12 - -// Field: [11] RFESOFT2 -// -// RF engine software defined interrupt 2 flag. Write zero to clear flag. Write -// to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 -#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 -#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 -#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 - -// Field: [10] RFESOFT1 -// -// RF engine software defined interrupt 1 flag. Write zero to clear flag. Write -// to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 -#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 -#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 -#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 - -// Field: [9] RFESOFT0 -// -// RF engine software defined interrupt 0 flag. Write zero to clear flag. Write -// to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 -#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 -#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 -#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 - -// Field: [8] RFEDONE -// -// RF engine command done interrupt flag. Write zero to clear flag. Write to -// one has no effect. -#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 -#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 -#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 -#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 - -// Field: [6] TRCTK -// -// Debug tracer system tick interrupt flag. Write zero to clear flag. Write to -// one has no effect. -#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 -#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 -#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 -#define RFC_DBELL_RFHWIFG_TRCTK_S 6 - -// Field: [5] MDMSOFT -// -// Modem synchronization word detection interrupt flag. This interrupt will be -// raised by modem when the synchronization word is received. The CPE may -// decide to reject the packet based on its header (protocol specific). Write -// zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 -#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 -#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 -#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 - -// Field: [4] MDMOUT -// -// Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has -// no effect. -#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 -#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 -#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 -#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 - -// Field: [3] MDMIN -// -// Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has -// no effect. -#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 -#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 -#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 -#define RFC_DBELL_RFHWIFG_MDMIN_S 3 - -// Field: [2] MDMDONE -// -// Modem command done interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 -#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 -#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 -#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 - -// Field: [1] FSCA -// -// Frequency synthesizer calibration accelerator interrupt flag. Write zero to -// clear flag. Write to one has no effect. -#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 -#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 -#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 -#define RFC_DBELL_RFHWIFG_FSCA_S 1 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFHWIEN -// -//***************************************************************************** -// Field: [19] RATCH7 -// -// Interrupt enable for RFHWIFG.RATCH7. -#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 -#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 -#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 -#define RFC_DBELL_RFHWIEN_RATCH7_S 19 - -// Field: [18] RATCH6 -// -// Interrupt enable for RFHWIFG.RATCH6. -#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 -#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 -#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 -#define RFC_DBELL_RFHWIEN_RATCH6_S 18 - -// Field: [17] RATCH5 -// -// Interrupt enable for RFHWIFG.RATCH5. -#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 -#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 -#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 -#define RFC_DBELL_RFHWIEN_RATCH5_S 17 - -// Field: [16] RATCH4 -// -// Interrupt enable for RFHWIFG.RATCH4. -#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 -#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 -#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 -#define RFC_DBELL_RFHWIEN_RATCH4_S 16 - -// Field: [15] RATCH3 -// -// Interrupt enable for RFHWIFG.RATCH3. -#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 -#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 -#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 -#define RFC_DBELL_RFHWIEN_RATCH3_S 15 - -// Field: [14] RATCH2 -// -// Interrupt enable for RFHWIFG.RATCH2. -#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 -#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 -#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 -#define RFC_DBELL_RFHWIEN_RATCH2_S 14 - -// Field: [13] RATCH1 -// -// Interrupt enable for RFHWIFG.RATCH1. -#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 -#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 -#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 -#define RFC_DBELL_RFHWIEN_RATCH1_S 13 - -// Field: [12] RATCH0 -// -// Interrupt enable for RFHWIFG.RATCH0. -#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 -#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 -#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 -#define RFC_DBELL_RFHWIEN_RATCH0_S 12 - -// Field: [11] RFESOFT2 -// -// Interrupt enable for RFHWIFG.RFESOFT2. -#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 -#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 -#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 -#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 - -// Field: [10] RFESOFT1 -// -// Interrupt enable for RFHWIFG.RFESOFT1. -#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 -#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 -#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 -#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 - -// Field: [9] RFESOFT0 -// -// Interrupt enable for RFHWIFG.RFESOFT0. -#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 -#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 -#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 -#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 - -// Field: [8] RFEDONE -// -// Interrupt enable for RFHWIFG.RFEDONE. -#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 -#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 -#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 -#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 - -// Field: [6] TRCTK -// -// Interrupt enable for RFHWIFG.TRCTK. -#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 -#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 -#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 -#define RFC_DBELL_RFHWIEN_TRCTK_S 6 - -// Field: [5] MDMSOFT -// -// Interrupt enable for RFHWIFG.MDMSOFT. -#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 -#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 -#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 -#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 - -// Field: [4] MDMOUT -// -// Interrupt enable for RFHWIFG.MDMOUT. -#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 -#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 -#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 -#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 - -// Field: [3] MDMIN -// -// Interrupt enable for RFHWIFG.MDMIN. -#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 -#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 -#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 -#define RFC_DBELL_RFHWIEN_MDMIN_S 3 - -// Field: [2] MDMDONE -// -// Interrupt enable for RFHWIFG.MDMDONE. -#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 -#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 -#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 -#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 - -// Field: [1] FSCA -// -// Interrupt enable for RFHWIFG.FSCA. -#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 -#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 -#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 -#define RFC_DBELL_RFHWIEN_FSCA_S 1 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFCPEIFG -// -//***************************************************************************** -// Field: [31] INTERNAL_ERROR -// -// Interrupt flag 31. The command and packet engine (CPE) has observed an -// unexpected error. A reset of the CPE is needed. This can be done by -// switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero -// to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 - -// Field: [30] BOOT_DONE -// -// Interrupt flag 30. The command and packet engine (CPE) boot is finished. -// Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 - -// Field: [29] MODULES_UNLOCKED -// -// Interrupt flag 29. As part of command and packet engine (CPE) boot process, -// it has opened access to RF Core modules and memories. Write zero to clear -// flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 - -// Field: [28] SYNTH_NO_LOCK -// -// Interrupt flag 28. The phase-locked loop in frequency synthesizer has -// reported loss of lock. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 - -// Field: [27] IRQ27 -// -// Interrupt flag 27. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 - -// Field: [26] RX_ABORTED -// -// Interrupt flag 26. Packet reception stopped before packet was done. Write -// zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 - -// Field: [25] RX_N_DATA_WRITTEN -// -// Interrupt flag 25. Specified number of bytes written to partial read Rx -// buffer. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 - -// Field: [24] RX_DATA_WRITTEN -// -// Interrupt flag 24. Data written to partial read Rx buffer. Write zero to -// clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 - -// Field: [23] RX_ENTRY_DONE -// -// Interrupt flag 23. Rx queue data entry changing state to finished. Write -// zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 - -// Field: [22] RX_BUF_FULL -// -// Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode: -// Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame -// received that did not fit in the Rx queue. Write zero to clear flag. Write -// to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 - -// Field: [21] RX_CTRL_ACK -// -// Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, -// not to be ignored, then acknowledgement sent. Write zero to clear flag. -// Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 - -// Field: [20] RX_CTRL -// -// Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, -// not to be ignored. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 - -// Field: [19] RX_EMPTY -// -// Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be -// ignored, no payload. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 - -// Field: [18] RX_IGNORED -// -// Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet -// received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received -// with ignore flag set. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 - -// Field: [17] RX_NOK -// -// Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received -// with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write -// zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 - -// Field: [16] RX_OK -// -// Interrupt flag 16. Packet received correctly. BLE mode: Packet received with -// CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received -// with CRC OK. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 - -// Field: [15] IRQ15 -// -// Interrupt flag 15. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 - -// Field: [14] IRQ14 -// -// Interrupt flag 14. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 - -// Field: [13] IRQ13 -// -// Interrupt flag 13. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ13 0x00002000 -#define RFC_DBELL_RFCPEIFG_IRQ13_BITN 13 -#define RFC_DBELL_RFCPEIFG_IRQ13_M 0x00002000 -#define RFC_DBELL_RFCPEIFG_IRQ13_S 13 - -// Field: [12] IRQ12 -// -// Interrupt flag 12. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ12 0x00001000 -#define RFC_DBELL_RFCPEIFG_IRQ12_BITN 12 -#define RFC_DBELL_RFCPEIFG_IRQ12_M 0x00001000 -#define RFC_DBELL_RFCPEIFG_IRQ12_S 12 - -// Field: [11] TX_BUFFER_CHANGED -// -// Interrupt flag 11. BLE mode only: A buffer change is complete after -// CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 - -// Field: [10] TX_ENTRY_DONE -// -// Interrupt flag 10. Tx queue data entry state changed to finished. Write zero -// to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 - -// Field: [9] TX_RETRANS -// -// Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear -// flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 - -// Field: [8] TX_CTRL_ACK_ACK -// -// Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted -// LL control packet, and acknowledgement transmitted for that packet. Write -// zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 - -// Field: [7] TX_CTRL_ACK -// -// Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL -// control packet. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 - -// Field: [6] TX_CTRL -// -// Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to -// clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 - -// Field: [5] TX_ACK -// -// Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted -// packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to -// clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 - -// Field: [4] TX_DONE -// -// Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been -// transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero -// to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 - -// Field: [3] LAST_FG_COMMAND_DONE -// -// Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio -// operation command in a chain of commands has finished. Write zero to clear -// flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 - -// Field: [2] FG_COMMAND_DONE -// -// Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation -// command has finished. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 - -// Field: [1] LAST_COMMAND_DONE -// -// Interrupt flag 1. The last radio operation command in a chain of commands -// has finished. (IEEE 802.15.4 mode: The last background level radio operation -// command in a chain of commands has finished.) Write zero to clear flag. -// Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 - -// Field: [0] COMMAND_DONE -// -// Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A -// background level radio operation command has finished.) Write zero to clear -// flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFCPEIEN -// -//***************************************************************************** -// Field: [31] INTERNAL_ERROR -// -// Interrupt enable for RFCPEIFG.INTERNAL_ERROR. -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 - -// Field: [30] BOOT_DONE -// -// Interrupt enable for RFCPEIFG.BOOT_DONE. -#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 - -// Field: [29] MODULES_UNLOCKED -// -// Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 - -// Field: [28] SYNTH_NO_LOCK -// -// Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 - -// Field: [27] IRQ27 -// -// Interrupt enable for RFCPEIFG.IRQ27. -#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 - -// Field: [26] RX_ABORTED -// -// Interrupt enable for RFCPEIFG.RX_ABORTED. -#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 - -// Field: [25] RX_N_DATA_WRITTEN -// -// Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 - -// Field: [24] RX_DATA_WRITTEN -// -// Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 - -// Field: [23] RX_ENTRY_DONE -// -// Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 - -// Field: [22] RX_BUF_FULL -// -// Interrupt enable for RFCPEIFG.RX_BUF_FULL. -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 - -// Field: [21] RX_CTRL_ACK -// -// Interrupt enable for RFCPEIFG.RX_CTRL_ACK. -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 - -// Field: [20] RX_CTRL -// -// Interrupt enable for RFCPEIFG.RX_CTRL. -#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 - -// Field: [19] RX_EMPTY -// -// Interrupt enable for RFCPEIFG.RX_EMPTY. -#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 - -// Field: [18] RX_IGNORED -// -// Interrupt enable for RFCPEIFG.RX_IGNORED. -#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 - -// Field: [17] RX_NOK -// -// Interrupt enable for RFCPEIFG.RX_NOK. -#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 - -// Field: [16] RX_OK -// -// Interrupt enable for RFCPEIFG.RX_OK. -#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 - -// Field: [15] IRQ15 -// -// Interrupt enable for RFCPEIFG.IRQ15. -#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 - -// Field: [14] IRQ14 -// -// Interrupt enable for RFCPEIFG.IRQ14. -#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 - -// Field: [13] IRQ13 -// -// Interrupt enable for RFCPEIFG.IRQ13. -#define RFC_DBELL_RFCPEIEN_IRQ13 0x00002000 -#define RFC_DBELL_RFCPEIEN_IRQ13_BITN 13 -#define RFC_DBELL_RFCPEIEN_IRQ13_M 0x00002000 -#define RFC_DBELL_RFCPEIEN_IRQ13_S 13 - -// Field: [12] IRQ12 -// -// Interrupt enable for RFCPEIFG.IRQ12. -#define RFC_DBELL_RFCPEIEN_IRQ12 0x00001000 -#define RFC_DBELL_RFCPEIEN_IRQ12_BITN 12 -#define RFC_DBELL_RFCPEIEN_IRQ12_M 0x00001000 -#define RFC_DBELL_RFCPEIEN_IRQ12_S 12 - -// Field: [11] TX_BUFFER_CHANGED -// -// Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 - -// Field: [10] TX_ENTRY_DONE -// -// Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 - -// Field: [9] TX_RETRANS -// -// Interrupt enable for RFCPEIFG.TX_RETRANS. -#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 - -// Field: [8] TX_CTRL_ACK_ACK -// -// Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 - -// Field: [7] TX_CTRL_ACK -// -// Interrupt enable for RFCPEIFG.TX_CTRL_ACK. -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 - -// Field: [6] TX_CTRL -// -// Interrupt enable for RFCPEIFG.TX_CTRL. -#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 - -// Field: [5] TX_ACK -// -// Interrupt enable for RFCPEIFG.TX_ACK. -#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 - -// Field: [4] TX_DONE -// -// Interrupt enable for RFCPEIFG.TX_DONE. -#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 - -// Field: [3] LAST_FG_COMMAND_DONE -// -// Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 - -// Field: [2] FG_COMMAND_DONE -// -// Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 - -// Field: [1] LAST_COMMAND_DONE -// -// Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 - -// Field: [0] COMMAND_DONE -// -// Interrupt enable for RFCPEIFG.COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFCPEISL -// -//***************************************************************************** -// Field: [31] INTERNAL_ERROR -// -// Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 - -// Field: [30] BOOT_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 - -// Field: [29] MODULES_UNLOCKED -// -// Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 - -// Field: [28] SYNTH_NO_LOCK -// -// Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 - -// Field: [27] IRQ27 -// -// Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_S 27 -#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 - -// Field: [26] RX_ABORTED -// -// Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 - -// Field: [25] RX_N_DATA_WRITTEN -// -// Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 - -// Field: [24] RX_DATA_WRITTEN -// -// Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 - -// Field: [23] RX_ENTRY_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 - -// Field: [22] RX_BUF_FULL -// -// Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 - -// Field: [21] RX_CTRL_ACK -// -// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 - -// Field: [20] RX_CTRL -// -// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 -#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 - -// Field: [19] RX_EMPTY -// -// Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 - -// Field: [18] RX_IGNORED -// -// Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 - -// Field: [17] RX_NOK -// -// Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 -#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 - -// Field: [16] RX_OK -// -// Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_S 16 -#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 - -// Field: [15] IRQ15 -// -// Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_S 15 -#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 - -// Field: [14] IRQ14 -// -// Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_S 14 -#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 - -// Field: [13] IRQ13 -// -// Select which CPU interrupt vector the RFCPEIFG.IRQ13 interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ13 0x00002000 -#define RFC_DBELL_RFCPEISL_IRQ13_BITN 13 -#define RFC_DBELL_RFCPEISL_IRQ13_M 0x00002000 -#define RFC_DBELL_RFCPEISL_IRQ13_S 13 -#define RFC_DBELL_RFCPEISL_IRQ13_CPE1 0x00002000 -#define RFC_DBELL_RFCPEISL_IRQ13_CPE0 0x00000000 - -// Field: [12] IRQ12 -// -// Select which CPU interrupt vector the RFCPEIFG.IRQ12 interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ12 0x00001000 -#define RFC_DBELL_RFCPEISL_IRQ12_BITN 12 -#define RFC_DBELL_RFCPEISL_IRQ12_M 0x00001000 -#define RFC_DBELL_RFCPEISL_IRQ12_S 12 -#define RFC_DBELL_RFCPEISL_IRQ12_CPE1 0x00001000 -#define RFC_DBELL_RFCPEISL_IRQ12_CPE0 0x00000000 - -// Field: [11] TX_BUFFER_CHANGED -// -// Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 - -// Field: [10] TX_ENTRY_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 - -// Field: [9] TX_RETRANS -// -// Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 - -// Field: [8] TX_CTRL_ACK_ACK -// -// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 - -// Field: [7] TX_CTRL_ACK -// -// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 - -// Field: [6] TX_CTRL -// -// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 -#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 - -// Field: [5] TX_ACK -// -// Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 -#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 - -// Field: [4] TX_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 -#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 - -// Field: [3] LAST_FG_COMMAND_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE -// interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 - -// Field: [2] FG_COMMAND_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 - -// Field: [1] LAST_COMMAND_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 - -// Field: [0] COMMAND_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFACKIFG -// -//***************************************************************************** -// Field: [0] ACKFLAG -// -// Interrupt flag for Command ACK -#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 -#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 -#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 -#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_SYSGPOCTL -// -//***************************************************************************** -// Field: [15:12] GPOCTL3 -// -// RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO -// line 3. -// ENUMs: -// RATGPO3 RAT GPO line 3 -// RATGPO2 RAT GPO line 2 -// RATGPO1 RAT GPO line 1 -// RATGPO0 RAT GPO line 0 -// RFEGPO3 RFE GPO line 3 -// RFEGPO2 RFE GPO line 2 -// RFEGPO1 RFE GPO line 1 -// RFEGPO0 RFE GPO line 0 -// MCEGPO3 MCE GPO line 3 -// MCEGPO2 MCE GPO line 2 -// MCEGPO1 MCE GPO line 1 -// MCEGPO0 MCE GPO line 0 -// CPEGPO3 CPE GPO line 3 -// CPEGPO2 CPE GPO line 2 -// CPEGPO1 CPE GPO line 1 -// CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 - -// Field: [11:8] GPOCTL2 -// -// RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO -// line 2. -// ENUMs: -// RATGPO3 RAT GPO line 3 -// RATGPO2 RAT GPO line 2 -// RATGPO1 RAT GPO line 1 -// RATGPO0 RAT GPO line 0 -// RFEGPO3 RFE GPO line 3 -// RFEGPO2 RFE GPO line 2 -// RFEGPO1 RFE GPO line 1 -// RFEGPO0 RFE GPO line 0 -// MCEGPO3 MCE GPO line 3 -// MCEGPO2 MCE GPO line 2 -// MCEGPO1 MCE GPO line 1 -// MCEGPO0 MCE GPO line 0 -// CPEGPO3 CPE GPO line 3 -// CPEGPO2 CPE GPO line 2 -// CPEGPO1 CPE GPO line 1 -// CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 - -// Field: [7:4] GPOCTL1 -// -// RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO -// line 1. -// ENUMs: -// RATGPO3 RAT GPO line 3 -// RATGPO2 RAT GPO line 2 -// RATGPO1 RAT GPO line 1 -// RATGPO0 RAT GPO line 0 -// RFEGPO3 RFE GPO line 3 -// RFEGPO2 RFE GPO line 2 -// RFEGPO1 RFE GPO line 1 -// RFEGPO0 RFE GPO line 0 -// MCEGPO3 MCE GPO line 3 -// MCEGPO2 MCE GPO line 2 -// MCEGPO1 MCE GPO line 1 -// MCEGPO0 MCE GPO line 0 -// CPEGPO3 CPE GPO line 3 -// CPEGPO2 CPE GPO line 2 -// CPEGPO1 CPE GPO line 1 -// CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 - -// Field: [3:0] GPOCTL0 -// -// RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO -// line 0. -// ENUMs: -// RATGPO3 RAT GPO line 3 -// RATGPO2 RAT GPO line 2 -// RATGPO1 RAT GPO line 1 -// RATGPO0 RAT GPO line 0 -// RFEGPO3 RFE GPO line 3 -// RFEGPO2 RFE GPO line 2 -// RFEGPO1 RFE GPO line 1 -// RFEGPO0 RFE GPO line 0 -// MCEGPO3 MCE GPO line 3 -// MCEGPO2 MCE GPO line 2 -// MCEGPO1 MCE GPO line 1 -// MCEGPO0 MCE GPO line 0 -// CPEGPO3 CPE GPO line 3 -// CPEGPO2 CPE GPO line 2 -// CPEGPO1 CPE GPO line 1 -// CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 - - -#endif // __RFC_DBELL__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_rfc_pwr.h b/third_party/ti/devices/cc26x0/inc/hw_rfc_pwr.h deleted file mode 100644 index 8266fd3d4..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_rfc_pwr.h +++ /dev/null @@ -1,153 +0,0 @@ -/****************************************************************************** -* Filename: hw_rfc_pwr_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_RFC_PWR_H__ -#define __HW_RFC_PWR_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// RFC_PWR component -// -//***************************************************************************** -// RF Core Power Management and Clock Enable -#define RFC_PWR_O_PWMCLKEN 0x00000000 - -//***************************************************************************** -// -// Register: RFC_PWR_O_PWMCLKEN -// -//***************************************************************************** -// Field: [10] RFCTRC -// -// Enable clock to the RF Core Tracer (RFCTRC) module. -#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 -#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 -#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 -#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 - -// Field: [9] FSCA -// -// Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) -// module. -#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 -#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 -#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 -#define RFC_PWR_PWMCLKEN_FSCA_S 9 - -// Field: [8] PHA -// -// Enable clock to the Packet Handling Accelerator (PHA) module. -#define RFC_PWR_PWMCLKEN_PHA 0x00000100 -#define RFC_PWR_PWMCLKEN_PHA_BITN 8 -#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 -#define RFC_PWR_PWMCLKEN_PHA_S 8 - -// Field: [7] RAT -// -// Enable clock to the Radio Timer (RAT) module. -#define RFC_PWR_PWMCLKEN_RAT 0x00000080 -#define RFC_PWR_PWMCLKEN_RAT_BITN 7 -#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 -#define RFC_PWR_PWMCLKEN_RAT_S 7 - -// Field: [6] RFERAM -// -// Enable clock to the RF Engine RAM module. -#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 -#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 -#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 -#define RFC_PWR_PWMCLKEN_RFERAM_S 6 - -// Field: [5] RFE -// -// Enable clock to the RF Engine (RFE) module. -#define RFC_PWR_PWMCLKEN_RFE 0x00000020 -#define RFC_PWR_PWMCLKEN_RFE_BITN 5 -#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 -#define RFC_PWR_PWMCLKEN_RFE_S 5 - -// Field: [4] MDMRAM -// -// Enable clock to the Modem RAM module. -#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 -#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 -#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 -#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 - -// Field: [3] MDM -// -// Enable clock to the Modem (MDM) module. -#define RFC_PWR_PWMCLKEN_MDM 0x00000008 -#define RFC_PWR_PWMCLKEN_MDM_BITN 3 -#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 -#define RFC_PWR_PWMCLKEN_MDM_S 3 - -// Field: [2] CPERAM -// -// Enable clock to the Command and Packet Engine (CPE) RAM module. As part of -// RF Core initialization, set this bit together with CPE bit to enable CPE to -// boot. -#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 -#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 -#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 -#define RFC_PWR_PWMCLKEN_CPERAM_S 2 - -// Field: [1] CPE -// -// Enable processor clock (hclk) to the Command and Packet Engine (CPE). As -// part of RF Core initialization, set this bit together with CPERAM bit to -// enable CPE to boot. -#define RFC_PWR_PWMCLKEN_CPE 0x00000002 -#define RFC_PWR_PWMCLKEN_CPE_BITN 1 -#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 -#define RFC_PWR_PWMCLKEN_CPE_S 1 - -// Field: [0] RFC -// -// Enable essential clocks for the RF Core interface. This includes the -// interconnect, the radio doorbell DBELL command interface, the power -// management (PWR) clock control module, and bus clock (sclk) for the CPE. To -// remove possibility of locking yourself out from the RF Core, this bit can -// not be cleared. If you need to disable all clocks to the RF Core, see the -// PRCM:RFCCLKG.CLK_EN register. -#define RFC_PWR_PWMCLKEN_RFC 0x00000001 -#define RFC_PWR_PWMCLKEN_RFC_BITN 0 -#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 -#define RFC_PWR_PWMCLKEN_RFC_S 0 - - -#endif // __RFC_PWR__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_rfc_rat.h b/third_party/ti/devices/cc26x0/inc/hw_rfc_rat.h deleted file mode 100644 index 73afbcc10..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_rfc_rat.h +++ /dev/null @@ -1,190 +0,0 @@ -/****************************************************************************** -* Filename: hw_rfc_rat_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_RFC_RAT_H__ -#define __HW_RFC_RAT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// RFC_RAT component -// -//***************************************************************************** -// Radio Timer Counter Value -#define RFC_RAT_O_RATCNT 0x00000004 - -// Timer Channel 0 Capture/Compare Register -#define RFC_RAT_O_RATCH0VAL 0x00000080 - -// Timer Channel 1 Capture/Compare Register -#define RFC_RAT_O_RATCH1VAL 0x00000084 - -// Timer Channel 2 Capture/Compare Register -#define RFC_RAT_O_RATCH2VAL 0x00000088 - -// Timer Channel 3 Capture/Compare Register -#define RFC_RAT_O_RATCH3VAL 0x0000008C - -// Timer Channel 4 Capture/Compare Register -#define RFC_RAT_O_RATCH4VAL 0x00000090 - -// Timer Channel 5 Capture/Compare Register -#define RFC_RAT_O_RATCH5VAL 0x00000094 - -// Timer Channel 6 Capture/Compare Register -#define RFC_RAT_O_RATCH6VAL 0x00000098 - -// Timer Channel 7 Capture/Compare Register -#define RFC_RAT_O_RATCH7VAL 0x0000009C - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCNT -// -//***************************************************************************** -// Field: [31:0] CNT -// -// Counter value. This is not writable while radio timer counter is enabled. -#define RFC_RAT_RATCNT_CNT_W 32 -#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF -#define RFC_RAT_RATCNT_CNT_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH0VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. The system CPU can safely read this register, but it -// is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH0VAL_VAL_W 32 -#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH0VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH1VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. The system CPU can safely read this register, but it -// is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH1VAL_VAL_W 32 -#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH1VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH2VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. The system CPU can safely read this register, but it -// is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH2VAL_VAL_W 32 -#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH2VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH3VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. The system CPU can safely read this register, but it -// is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH3VAL_VAL_W 32 -#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH3VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH4VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. The system CPU can safely read this register, but it -// is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH4VAL_VAL_W 32 -#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH4VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH5VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. The system CPU can safely read this register, but it -// is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH5VAL_VAL_W 32 -#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH5VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH6VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. The system CPU can safely read this register, but it -// is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH6VAL_VAL_W 32 -#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH6VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH7VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. The system CPU can safely read this register, but it -// is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH7VAL_VAL_W 32 -#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH7VAL_VAL_S 0 - - -#endif // __RFC_RAT__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_smph.h b/third_party/ti/devices/cc26x0/inc/hw_smph.h deleted file mode 100644 index 85dc8b27f..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_smph.h +++ /dev/null @@ -1,1455 +0,0 @@ -/****************************************************************************** -* Filename: hw_smph_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_SMPH_H__ -#define __HW_SMPH_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// SMPH component -// -//***************************************************************************** -// MCU SEMAPHORE 0 -#define SMPH_O_SMPH0 0x00000000 - -// MCU SEMAPHORE 1 -#define SMPH_O_SMPH1 0x00000004 - -// MCU SEMAPHORE 2 -#define SMPH_O_SMPH2 0x00000008 - -// MCU SEMAPHORE 3 -#define SMPH_O_SMPH3 0x0000000C - -// MCU SEMAPHORE 4 -#define SMPH_O_SMPH4 0x00000010 - -// MCU SEMAPHORE 5 -#define SMPH_O_SMPH5 0x00000014 - -// MCU SEMAPHORE 6 -#define SMPH_O_SMPH6 0x00000018 - -// MCU SEMAPHORE 7 -#define SMPH_O_SMPH7 0x0000001C - -// MCU SEMAPHORE 8 -#define SMPH_O_SMPH8 0x00000020 - -// MCU SEMAPHORE 9 -#define SMPH_O_SMPH9 0x00000024 - -// MCU SEMAPHORE 10 -#define SMPH_O_SMPH10 0x00000028 - -// MCU SEMAPHORE 11 -#define SMPH_O_SMPH11 0x0000002C - -// MCU SEMAPHORE 12 -#define SMPH_O_SMPH12 0x00000030 - -// MCU SEMAPHORE 13 -#define SMPH_O_SMPH13 0x00000034 - -// MCU SEMAPHORE 14 -#define SMPH_O_SMPH14 0x00000038 - -// MCU SEMAPHORE 15 -#define SMPH_O_SMPH15 0x0000003C - -// MCU SEMAPHORE 16 -#define SMPH_O_SMPH16 0x00000040 - -// MCU SEMAPHORE 17 -#define SMPH_O_SMPH17 0x00000044 - -// MCU SEMAPHORE 18 -#define SMPH_O_SMPH18 0x00000048 - -// MCU SEMAPHORE 19 -#define SMPH_O_SMPH19 0x0000004C - -// MCU SEMAPHORE 20 -#define SMPH_O_SMPH20 0x00000050 - -// MCU SEMAPHORE 21 -#define SMPH_O_SMPH21 0x00000054 - -// MCU SEMAPHORE 22 -#define SMPH_O_SMPH22 0x00000058 - -// MCU SEMAPHORE 23 -#define SMPH_O_SMPH23 0x0000005C - -// MCU SEMAPHORE 24 -#define SMPH_O_SMPH24 0x00000060 - -// MCU SEMAPHORE 25 -#define SMPH_O_SMPH25 0x00000064 - -// MCU SEMAPHORE 26 -#define SMPH_O_SMPH26 0x00000068 - -// MCU SEMAPHORE 27 -#define SMPH_O_SMPH27 0x0000006C - -// MCU SEMAPHORE 28 -#define SMPH_O_SMPH28 0x00000070 - -// MCU SEMAPHORE 29 -#define SMPH_O_SMPH29 0x00000074 - -// MCU SEMAPHORE 30 -#define SMPH_O_SMPH30 0x00000078 - -// MCU SEMAPHORE 31 -#define SMPH_O_SMPH31 0x0000007C - -// MCU SEMAPHORE 0 ALIAS -#define SMPH_O_PEEK0 0x00000800 - -// MCU SEMAPHORE 1 ALIAS -#define SMPH_O_PEEK1 0x00000804 - -// MCU SEMAPHORE 2 ALIAS -#define SMPH_O_PEEK2 0x00000808 - -// MCU SEMAPHORE 3 ALIAS -#define SMPH_O_PEEK3 0x0000080C - -// MCU SEMAPHORE 4 ALIAS -#define SMPH_O_PEEK4 0x00000810 - -// MCU SEMAPHORE 5 ALIAS -#define SMPH_O_PEEK5 0x00000814 - -// MCU SEMAPHORE 6 ALIAS -#define SMPH_O_PEEK6 0x00000818 - -// MCU SEMAPHORE 7 ALIAS -#define SMPH_O_PEEK7 0x0000081C - -// MCU SEMAPHORE 8 ALIAS -#define SMPH_O_PEEK8 0x00000820 - -// MCU SEMAPHORE 9 ALIAS -#define SMPH_O_PEEK9 0x00000824 - -// MCU SEMAPHORE 10 ALIAS -#define SMPH_O_PEEK10 0x00000828 - -// MCU SEMAPHORE 11 ALIAS -#define SMPH_O_PEEK11 0x0000082C - -// MCU SEMAPHORE 12 ALIAS -#define SMPH_O_PEEK12 0x00000830 - -// MCU SEMAPHORE 13 ALIAS -#define SMPH_O_PEEK13 0x00000834 - -// MCU SEMAPHORE 14 ALIAS -#define SMPH_O_PEEK14 0x00000838 - -// MCU SEMAPHORE 15 ALIAS -#define SMPH_O_PEEK15 0x0000083C - -// MCU SEMAPHORE 16 ALIAS -#define SMPH_O_PEEK16 0x00000840 - -// MCU SEMAPHORE 17 ALIAS -#define SMPH_O_PEEK17 0x00000844 - -// MCU SEMAPHORE 18 ALIAS -#define SMPH_O_PEEK18 0x00000848 - -// MCU SEMAPHORE 19 ALIAS -#define SMPH_O_PEEK19 0x0000084C - -// MCU SEMAPHORE 20 ALIAS -#define SMPH_O_PEEK20 0x00000850 - -// MCU SEMAPHORE 21 ALIAS -#define SMPH_O_PEEK21 0x00000854 - -// MCU SEMAPHORE 22 ALIAS -#define SMPH_O_PEEK22 0x00000858 - -// MCU SEMAPHORE 23 ALIAS -#define SMPH_O_PEEK23 0x0000085C - -// MCU SEMAPHORE 24 ALIAS -#define SMPH_O_PEEK24 0x00000860 - -// MCU SEMAPHORE 25 ALIAS -#define SMPH_O_PEEK25 0x00000864 - -// MCU SEMAPHORE 26 ALIAS -#define SMPH_O_PEEK26 0x00000868 - -// MCU SEMAPHORE 27 ALIAS -#define SMPH_O_PEEK27 0x0000086C - -// MCU SEMAPHORE 28 ALIAS -#define SMPH_O_PEEK28 0x00000870 - -// MCU SEMAPHORE 29 ALIAS -#define SMPH_O_PEEK29 0x00000874 - -// MCU SEMAPHORE 30 ALIAS -#define SMPH_O_PEEK30 0x00000878 - -// MCU SEMAPHORE 31 ALIAS -#define SMPH_O_PEEK31 0x0000087C - -//***************************************************************************** -// -// Register: SMPH_O_SMPH0 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH0_STAT 0x00000001 -#define SMPH_SMPH0_STAT_BITN 0 -#define SMPH_SMPH0_STAT_M 0x00000001 -#define SMPH_SMPH0_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH1 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH1_STAT 0x00000001 -#define SMPH_SMPH1_STAT_BITN 0 -#define SMPH_SMPH1_STAT_M 0x00000001 -#define SMPH_SMPH1_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH2 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH2_STAT 0x00000001 -#define SMPH_SMPH2_STAT_BITN 0 -#define SMPH_SMPH2_STAT_M 0x00000001 -#define SMPH_SMPH2_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH3 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH3_STAT 0x00000001 -#define SMPH_SMPH3_STAT_BITN 0 -#define SMPH_SMPH3_STAT_M 0x00000001 -#define SMPH_SMPH3_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH4 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH4_STAT 0x00000001 -#define SMPH_SMPH4_STAT_BITN 0 -#define SMPH_SMPH4_STAT_M 0x00000001 -#define SMPH_SMPH4_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH5 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH5_STAT 0x00000001 -#define SMPH_SMPH5_STAT_BITN 0 -#define SMPH_SMPH5_STAT_M 0x00000001 -#define SMPH_SMPH5_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH6 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH6_STAT 0x00000001 -#define SMPH_SMPH6_STAT_BITN 0 -#define SMPH_SMPH6_STAT_M 0x00000001 -#define SMPH_SMPH6_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH7 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH7_STAT 0x00000001 -#define SMPH_SMPH7_STAT_BITN 0 -#define SMPH_SMPH7_STAT_M 0x00000001 -#define SMPH_SMPH7_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH8 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH8_STAT 0x00000001 -#define SMPH_SMPH8_STAT_BITN 0 -#define SMPH_SMPH8_STAT_M 0x00000001 -#define SMPH_SMPH8_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH9 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH9_STAT 0x00000001 -#define SMPH_SMPH9_STAT_BITN 0 -#define SMPH_SMPH9_STAT_M 0x00000001 -#define SMPH_SMPH9_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH10 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH10_STAT 0x00000001 -#define SMPH_SMPH10_STAT_BITN 0 -#define SMPH_SMPH10_STAT_M 0x00000001 -#define SMPH_SMPH10_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH11 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH11_STAT 0x00000001 -#define SMPH_SMPH11_STAT_BITN 0 -#define SMPH_SMPH11_STAT_M 0x00000001 -#define SMPH_SMPH11_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH12 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH12_STAT 0x00000001 -#define SMPH_SMPH12_STAT_BITN 0 -#define SMPH_SMPH12_STAT_M 0x00000001 -#define SMPH_SMPH12_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH13 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH13_STAT 0x00000001 -#define SMPH_SMPH13_STAT_BITN 0 -#define SMPH_SMPH13_STAT_M 0x00000001 -#define SMPH_SMPH13_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH14 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH14_STAT 0x00000001 -#define SMPH_SMPH14_STAT_BITN 0 -#define SMPH_SMPH14_STAT_M 0x00000001 -#define SMPH_SMPH14_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH15 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH15_STAT 0x00000001 -#define SMPH_SMPH15_STAT_BITN 0 -#define SMPH_SMPH15_STAT_M 0x00000001 -#define SMPH_SMPH15_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH16 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH16_STAT 0x00000001 -#define SMPH_SMPH16_STAT_BITN 0 -#define SMPH_SMPH16_STAT_M 0x00000001 -#define SMPH_SMPH16_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH17 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH17_STAT 0x00000001 -#define SMPH_SMPH17_STAT_BITN 0 -#define SMPH_SMPH17_STAT_M 0x00000001 -#define SMPH_SMPH17_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH18 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH18_STAT 0x00000001 -#define SMPH_SMPH18_STAT_BITN 0 -#define SMPH_SMPH18_STAT_M 0x00000001 -#define SMPH_SMPH18_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH19 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH19_STAT 0x00000001 -#define SMPH_SMPH19_STAT_BITN 0 -#define SMPH_SMPH19_STAT_M 0x00000001 -#define SMPH_SMPH19_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH20 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH20_STAT 0x00000001 -#define SMPH_SMPH20_STAT_BITN 0 -#define SMPH_SMPH20_STAT_M 0x00000001 -#define SMPH_SMPH20_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH21 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH21_STAT 0x00000001 -#define SMPH_SMPH21_STAT_BITN 0 -#define SMPH_SMPH21_STAT_M 0x00000001 -#define SMPH_SMPH21_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH22 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH22_STAT 0x00000001 -#define SMPH_SMPH22_STAT_BITN 0 -#define SMPH_SMPH22_STAT_M 0x00000001 -#define SMPH_SMPH22_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH23 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH23_STAT 0x00000001 -#define SMPH_SMPH23_STAT_BITN 0 -#define SMPH_SMPH23_STAT_M 0x00000001 -#define SMPH_SMPH23_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH24 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH24_STAT 0x00000001 -#define SMPH_SMPH24_STAT_BITN 0 -#define SMPH_SMPH24_STAT_M 0x00000001 -#define SMPH_SMPH24_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH25 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH25_STAT 0x00000001 -#define SMPH_SMPH25_STAT_BITN 0 -#define SMPH_SMPH25_STAT_M 0x00000001 -#define SMPH_SMPH25_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH26 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH26_STAT 0x00000001 -#define SMPH_SMPH26_STAT_BITN 0 -#define SMPH_SMPH26_STAT_M 0x00000001 -#define SMPH_SMPH26_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH27 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH27_STAT 0x00000001 -#define SMPH_SMPH27_STAT_BITN 0 -#define SMPH_SMPH27_STAT_M 0x00000001 -#define SMPH_SMPH27_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH28 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH28_STAT 0x00000001 -#define SMPH_SMPH28_STAT_BITN 0 -#define SMPH_SMPH28_STAT_M 0x00000001 -#define SMPH_SMPH28_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH29 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH29_STAT 0x00000001 -#define SMPH_SMPH29_STAT_BITN 0 -#define SMPH_SMPH29_STAT_M 0x00000001 -#define SMPH_SMPH29_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH30 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH30_STAT 0x00000001 -#define SMPH_SMPH30_STAT_BITN 0 -#define SMPH_SMPH30_STAT_M 0x00000001 -#define SMPH_SMPH30_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH31 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH31_STAT 0x00000001 -#define SMPH_SMPH31_STAT_BITN 0 -#define SMPH_SMPH31_STAT_M 0x00000001 -#define SMPH_SMPH31_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK0 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK0_STAT 0x00000001 -#define SMPH_PEEK0_STAT_BITN 0 -#define SMPH_PEEK0_STAT_M 0x00000001 -#define SMPH_PEEK0_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK1 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK1_STAT 0x00000001 -#define SMPH_PEEK1_STAT_BITN 0 -#define SMPH_PEEK1_STAT_M 0x00000001 -#define SMPH_PEEK1_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK2 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK2_STAT 0x00000001 -#define SMPH_PEEK2_STAT_BITN 0 -#define SMPH_PEEK2_STAT_M 0x00000001 -#define SMPH_PEEK2_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK3 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK3_STAT 0x00000001 -#define SMPH_PEEK3_STAT_BITN 0 -#define SMPH_PEEK3_STAT_M 0x00000001 -#define SMPH_PEEK3_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK4 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK4_STAT 0x00000001 -#define SMPH_PEEK4_STAT_BITN 0 -#define SMPH_PEEK4_STAT_M 0x00000001 -#define SMPH_PEEK4_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK5 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK5_STAT 0x00000001 -#define SMPH_PEEK5_STAT_BITN 0 -#define SMPH_PEEK5_STAT_M 0x00000001 -#define SMPH_PEEK5_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK6 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK6_STAT 0x00000001 -#define SMPH_PEEK6_STAT_BITN 0 -#define SMPH_PEEK6_STAT_M 0x00000001 -#define SMPH_PEEK6_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK7 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK7_STAT 0x00000001 -#define SMPH_PEEK7_STAT_BITN 0 -#define SMPH_PEEK7_STAT_M 0x00000001 -#define SMPH_PEEK7_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK8 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK8_STAT 0x00000001 -#define SMPH_PEEK8_STAT_BITN 0 -#define SMPH_PEEK8_STAT_M 0x00000001 -#define SMPH_PEEK8_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK9 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK9_STAT 0x00000001 -#define SMPH_PEEK9_STAT_BITN 0 -#define SMPH_PEEK9_STAT_M 0x00000001 -#define SMPH_PEEK9_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK10 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK10_STAT 0x00000001 -#define SMPH_PEEK10_STAT_BITN 0 -#define SMPH_PEEK10_STAT_M 0x00000001 -#define SMPH_PEEK10_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK11 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK11_STAT 0x00000001 -#define SMPH_PEEK11_STAT_BITN 0 -#define SMPH_PEEK11_STAT_M 0x00000001 -#define SMPH_PEEK11_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK12 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK12_STAT 0x00000001 -#define SMPH_PEEK12_STAT_BITN 0 -#define SMPH_PEEK12_STAT_M 0x00000001 -#define SMPH_PEEK12_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK13 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK13_STAT 0x00000001 -#define SMPH_PEEK13_STAT_BITN 0 -#define SMPH_PEEK13_STAT_M 0x00000001 -#define SMPH_PEEK13_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK14 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK14_STAT 0x00000001 -#define SMPH_PEEK14_STAT_BITN 0 -#define SMPH_PEEK14_STAT_M 0x00000001 -#define SMPH_PEEK14_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK15 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK15_STAT 0x00000001 -#define SMPH_PEEK15_STAT_BITN 0 -#define SMPH_PEEK15_STAT_M 0x00000001 -#define SMPH_PEEK15_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK16 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK16_STAT 0x00000001 -#define SMPH_PEEK16_STAT_BITN 0 -#define SMPH_PEEK16_STAT_M 0x00000001 -#define SMPH_PEEK16_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK17 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK17_STAT 0x00000001 -#define SMPH_PEEK17_STAT_BITN 0 -#define SMPH_PEEK17_STAT_M 0x00000001 -#define SMPH_PEEK17_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK18 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK18_STAT 0x00000001 -#define SMPH_PEEK18_STAT_BITN 0 -#define SMPH_PEEK18_STAT_M 0x00000001 -#define SMPH_PEEK18_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK19 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK19_STAT 0x00000001 -#define SMPH_PEEK19_STAT_BITN 0 -#define SMPH_PEEK19_STAT_M 0x00000001 -#define SMPH_PEEK19_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK20 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK20_STAT 0x00000001 -#define SMPH_PEEK20_STAT_BITN 0 -#define SMPH_PEEK20_STAT_M 0x00000001 -#define SMPH_PEEK20_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK21 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK21_STAT 0x00000001 -#define SMPH_PEEK21_STAT_BITN 0 -#define SMPH_PEEK21_STAT_M 0x00000001 -#define SMPH_PEEK21_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK22 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK22_STAT 0x00000001 -#define SMPH_PEEK22_STAT_BITN 0 -#define SMPH_PEEK22_STAT_M 0x00000001 -#define SMPH_PEEK22_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK23 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK23_STAT 0x00000001 -#define SMPH_PEEK23_STAT_BITN 0 -#define SMPH_PEEK23_STAT_M 0x00000001 -#define SMPH_PEEK23_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK24 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK24_STAT 0x00000001 -#define SMPH_PEEK24_STAT_BITN 0 -#define SMPH_PEEK24_STAT_M 0x00000001 -#define SMPH_PEEK24_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK25 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK25_STAT 0x00000001 -#define SMPH_PEEK25_STAT_BITN 0 -#define SMPH_PEEK25_STAT_M 0x00000001 -#define SMPH_PEEK25_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK26 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK26_STAT 0x00000001 -#define SMPH_PEEK26_STAT_BITN 0 -#define SMPH_PEEK26_STAT_M 0x00000001 -#define SMPH_PEEK26_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK27 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK27_STAT 0x00000001 -#define SMPH_PEEK27_STAT_BITN 0 -#define SMPH_PEEK27_STAT_M 0x00000001 -#define SMPH_PEEK27_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK28 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK28_STAT 0x00000001 -#define SMPH_PEEK28_STAT_BITN 0 -#define SMPH_PEEK28_STAT_M 0x00000001 -#define SMPH_PEEK28_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK29 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK29_STAT 0x00000001 -#define SMPH_PEEK29_STAT_BITN 0 -#define SMPH_PEEK29_STAT_M 0x00000001 -#define SMPH_PEEK29_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK30 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK30_STAT 0x00000001 -#define SMPH_PEEK30_STAT_BITN 0 -#define SMPH_PEEK30_STAT_M 0x00000001 -#define SMPH_PEEK30_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK31 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK31_STAT 0x00000001 -#define SMPH_PEEK31_STAT_BITN 0 -#define SMPH_PEEK31_STAT_M 0x00000001 -#define SMPH_PEEK31_STAT_S 0 - - -#endif // __SMPH__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_ssi.h b/third_party/ti/devices/cc26x0/inc/hw_ssi.h deleted file mode 100644 index 6855f2b74..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_ssi.h +++ /dev/null @@ -1,544 +0,0 @@ -/****************************************************************************** -* Filename: hw_ssi_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// SSI component -// -//***************************************************************************** -// Control 0 -#define SSI_O_CR0 0x00000000 - -// Control 1 -#define SSI_O_CR1 0x00000004 - -// Data -#define SSI_O_DR 0x00000008 - -// Status -#define SSI_O_SR 0x0000000C - -// Clock Prescale -#define SSI_O_CPSR 0x00000010 - -// Interrupt Mask Set and Clear -#define SSI_O_IMSC 0x00000014 - -// Raw Interrupt Status -#define SSI_O_RIS 0x00000018 - -// Masked Interrupt Status -#define SSI_O_MIS 0x0000001C - -// Interrupt Clear -#define SSI_O_ICR 0x00000020 - -// DMA Control -#define SSI_O_DMACR 0x00000024 - -//***************************************************************************** -// -// Register: SSI_O_CR0 -// -//***************************************************************************** -// Field: [15:8] SCR -// -// Serial clock rate: -// This is used to generate the transmit and receive bit rate of the SSI. The -// bit rate is -// (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). -// SCR is a value from 0-255. -#define SSI_CR0_SCR_W 8 -#define SSI_CR0_SCR_M 0x0000FF00 -#define SSI_CR0_SCR_S 8 - -// Field: [7] SPH -// -// CLKOUT phase (Motorola SPI frame format only) -// This bit selects the clock edge that captures data and enables it to change -// state. It -// has the most impact on the first bit transmitted by either permitting or not -// permitting a clock transition before the first data capture edge. -// ENUMs: -// 2ND_CLK_EDGE Data is captured on the second clock edge -// transition. -// 1ST_CLK_EDGE Data is captured on the first clock edge -// transition. -#define SSI_CR0_SPH 0x00000080 -#define SSI_CR0_SPH_BITN 7 -#define SSI_CR0_SPH_M 0x00000080 -#define SSI_CR0_SPH_S 7 -#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 -#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 - -// Field: [6] SPO -// -// CLKOUT polarity (Motorola SPI frame format only) -// ENUMs: -// HIGH SSI produces a steady state HIGH value on the -// CLKOUT pin when data is not being transferred. -// LOW SSI produces a steady state LOW value on the -// CLKOUT pin when data is -// not being transferred. -#define SSI_CR0_SPO 0x00000040 -#define SSI_CR0_SPO_BITN 6 -#define SSI_CR0_SPO_M 0x00000040 -#define SSI_CR0_SPO_S 6 -#define SSI_CR0_SPO_HIGH 0x00000040 -#define SSI_CR0_SPO_LOW 0x00000000 - -// Field: [5:4] FRF -// -// Frame format. -// The supported frame formats are Motorola SPI, TI synchronous serial and -// National Microwire. -// Value 0'b11 is reserved and shall not be used. -// ENUMs: -// NATIONAL_MICROWIRE National Microwire frame format -// TI_SYNC_SERIAL TI synchronous serial frame format -// MOTOROLA_SPI Motorola SPI frame format -#define SSI_CR0_FRF_W 2 -#define SSI_CR0_FRF_M 0x00000030 -#define SSI_CR0_FRF_S 4 -#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 -#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 -#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 - -// Field: [3:0] DSS -// -// Data Size Select. -// Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. -// ENUMs: -// 16_BIT 16-bit data -// 15_BIT 15-bit data -// 14_BIT 14-bit data -// 13_BIT 13-bit data -// 12_BIT 12-bit data -// 11_BIT 11-bit data -// 10_BIT 10-bit data -// 9_BIT 9-bit data -// 8_BIT 8-bit data -// 7_BIT 7-bit data -// 6_BIT 6-bit data -// 5_BIT 5-bit data -// 4_BIT 4-bit data -#define SSI_CR0_DSS_W 4 -#define SSI_CR0_DSS_M 0x0000000F -#define SSI_CR0_DSS_S 0 -#define SSI_CR0_DSS_16_BIT 0x0000000F -#define SSI_CR0_DSS_15_BIT 0x0000000E -#define SSI_CR0_DSS_14_BIT 0x0000000D -#define SSI_CR0_DSS_13_BIT 0x0000000C -#define SSI_CR0_DSS_12_BIT 0x0000000B -#define SSI_CR0_DSS_11_BIT 0x0000000A -#define SSI_CR0_DSS_10_BIT 0x00000009 -#define SSI_CR0_DSS_9_BIT 0x00000008 -#define SSI_CR0_DSS_8_BIT 0x00000007 -#define SSI_CR0_DSS_7_BIT 0x00000006 -#define SSI_CR0_DSS_6_BIT 0x00000005 -#define SSI_CR0_DSS_5_BIT 0x00000004 -#define SSI_CR0_DSS_4_BIT 0x00000003 - -//***************************************************************************** -// -// Register: SSI_O_CR1 -// -//***************************************************************************** -// Field: [3] SOD -// -// Slave-mode output disabled -// This bit is relevant only in the slave mode, MS=1. In multiple-slave -// systems, it is possible for an SSI master to broadcast a message to all -// slaves in the system while ensuring that only one slave drives data onto its -// serial output line. In such systems the RXD lines from multiple slaves could -// be tied together. To operate in such systems, this bitfield can be set if -// the SSI slave is not supposed to drive the TXD line: -// -// 0: SSI can drive the TXD output in slave mode. -// 1: SSI cannot drive the TXD output in slave mode. -#define SSI_CR1_SOD 0x00000008 -#define SSI_CR1_SOD_BITN 3 -#define SSI_CR1_SOD_M 0x00000008 -#define SSI_CR1_SOD_S 3 - -// Field: [2] MS -// -// Master or slave mode select. This bit can be modified only when SSI is -// disabled, SSE=0. -// ENUMs: -// SLAVE Device configured as slave -// MASTER Device configured as master -#define SSI_CR1_MS 0x00000004 -#define SSI_CR1_MS_BITN 2 -#define SSI_CR1_MS_M 0x00000004 -#define SSI_CR1_MS_S 2 -#define SSI_CR1_MS_SLAVE 0x00000004 -#define SSI_CR1_MS_MASTER 0x00000000 - -// Field: [1] SSE -// -// Synchronous serial interface enable. -// ENUMs: -// SSI_ENABLED Operation enabled -// SSI_DISABLED Operation disabled -#define SSI_CR1_SSE 0x00000002 -#define SSI_CR1_SSE_BITN 1 -#define SSI_CR1_SSE_M 0x00000002 -#define SSI_CR1_SSE_S 1 -#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 -#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 - -// Field: [0] LBM -// -// Loop back mode: -// -// 0: Normal serial port operation enabled. -// 1: Output of transmit serial shifter is connected to input of receive serial -// shifter internally. -#define SSI_CR1_LBM 0x00000001 -#define SSI_CR1_LBM_BITN 0 -#define SSI_CR1_LBM_M 0x00000001 -#define SSI_CR1_LBM_S 0 - -//***************************************************************************** -// -// Register: SSI_O_DR -// -//***************************************************************************** -// Field: [15:0] DATA -// -// Transmit/receive data -// The values read from this field or written to this field must be -// right-justified when SSI is programmed for a data size that is less than 16 -// bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit -// logic. The receive logic automatically right-justifies. -#define SSI_DR_DATA_W 16 -#define SSI_DR_DATA_M 0x0000FFFF -#define SSI_DR_DATA_S 0 - -//***************************************************************************** -// -// Register: SSI_O_SR -// -//***************************************************************************** -// Field: [4] BSY -// -// Serial interface busy: -// -// 0: SSI is idle -// 1: SSI is currently transmitting and/or receiving a frame or the transmit -// FIFO is not empty. -#define SSI_SR_BSY 0x00000010 -#define SSI_SR_BSY_BITN 4 -#define SSI_SR_BSY_M 0x00000010 -#define SSI_SR_BSY_S 4 - -// Field: [3] RFF -// -// Receive FIFO full: -// -// 0: Receive FIFO is not full. -// 1: Receive FIFO is full. -#define SSI_SR_RFF 0x00000008 -#define SSI_SR_RFF_BITN 3 -#define SSI_SR_RFF_M 0x00000008 -#define SSI_SR_RFF_S 3 - -// Field: [2] RNE -// -// Receive FIFO not empty -// -// 0: Receive FIFO is empty. -// 1: Receive FIFO is not empty. -#define SSI_SR_RNE 0x00000004 -#define SSI_SR_RNE_BITN 2 -#define SSI_SR_RNE_M 0x00000004 -#define SSI_SR_RNE_S 2 - -// Field: [1] TNF -// -// Transmit FIFO not full: -// -// 0: Transmit FIFO is full. -// 1: Transmit FIFO is not full. -#define SSI_SR_TNF 0x00000002 -#define SSI_SR_TNF_BITN 1 -#define SSI_SR_TNF_M 0x00000002 -#define SSI_SR_TNF_S 1 - -// Field: [0] TFE -// -// Transmit FIFO empty: -// -// 0: Transmit FIFO is not empty. -// 1: Transmit FIFO is empty. -#define SSI_SR_TFE 0x00000001 -#define SSI_SR_TFE_BITN 0 -#define SSI_SR_TFE_M 0x00000001 -#define SSI_SR_TFE_S 0 - -//***************************************************************************** -// -// Register: SSI_O_CPSR -// -//***************************************************************************** -// Field: [7:0] CPSDVSR -// -// Clock prescale divisor: -// This field specifies the division factor by which the input system clock to -// SSI must be internally divided before further use. -// The value programmed into this field must be an even non-zero number -// (2-254). The least significant bit of the programmed number is hard-coded to -// zero. If an odd number is written to this register, data read back from -// this register has the least significant bit as zero. -#define SSI_CPSR_CPSDVSR_W 8 -#define SSI_CPSR_CPSDVSR_M 0x000000FF -#define SSI_CPSR_CPSDVSR_S 0 - -//***************************************************************************** -// -// Register: SSI_O_IMSC -// -//***************************************************************************** -// Field: [3] TXIM -// -// Transmit FIFO interrupt mask: -// A read returns the current mask for transmit FIFO interrupt. On a write of -// 1, the mask for transmit FIFO interrupt is set which means the interrupt -// state will be reflected in MIS.TXMIS. A write of 0 clears the mask which -// means MIS.TXMIS will not reflect the interrupt. -#define SSI_IMSC_TXIM 0x00000008 -#define SSI_IMSC_TXIM_BITN 3 -#define SSI_IMSC_TXIM_M 0x00000008 -#define SSI_IMSC_TXIM_S 3 - -// Field: [2] RXIM -// -// Receive FIFO interrupt mask: -// A read returns the current mask for receive FIFO interrupt. On a write of 1, -// the mask for receive FIFO interrupt is set which means the interrupt state -// will be reflected in MIS.RXMIS. A write of 0 clears the mask which means -// MIS.RXMIS will not reflect the interrupt. -#define SSI_IMSC_RXIM 0x00000004 -#define SSI_IMSC_RXIM_BITN 2 -#define SSI_IMSC_RXIM_M 0x00000004 -#define SSI_IMSC_RXIM_S 2 - -// Field: [1] RTIM -// -// Receive timeout interrupt mask: -// A read returns the current mask for receive timeout interrupt. On a write of -// 1, the mask for receive timeout interrupt is set which means the interrupt -// state will be reflected in MIS.RTMIS. A write of 0 clears the mask which -// means MIS.RTMIS will not reflect the interrupt. -#define SSI_IMSC_RTIM 0x00000002 -#define SSI_IMSC_RTIM_BITN 1 -#define SSI_IMSC_RTIM_M 0x00000002 -#define SSI_IMSC_RTIM_S 1 - -// Field: [0] RORIM -// -// Receive overrun interrupt mask: -// A read returns the current mask for receive overrun interrupt. On a write of -// 1, the mask for receive overrun interrupt is set which means the interrupt -// state will be reflected in MIS.RORMIS. A write of 0 clears the mask which -// means MIS.RORMIS will not reflect the interrupt. -#define SSI_IMSC_RORIM 0x00000001 -#define SSI_IMSC_RORIM_BITN 0 -#define SSI_IMSC_RORIM_M 0x00000001 -#define SSI_IMSC_RORIM_S 0 - -//***************************************************************************** -// -// Register: SSI_O_RIS -// -//***************************************************************************** -// Field: [3] TXRIS -// -// Raw transmit FIFO interrupt status: -// The transmit interrupt is asserted when there are four or fewer valid -// entries in the transmit FIFO. The transmit interrupt is not qualified with -// the SSI enable signal. Therefore one of the following ways can be used: -// - data can be written to the transmit FIFO prior to enabling the SSI and -// the -// interrupts. -// - SSI and interrupts can be enabled so that data can be written to the -// transmit FIFO by an interrupt service routine. -#define SSI_RIS_TXRIS 0x00000008 -#define SSI_RIS_TXRIS_BITN 3 -#define SSI_RIS_TXRIS_M 0x00000008 -#define SSI_RIS_TXRIS_S 3 - -// Field: [2] RXRIS -// -// Raw interrupt state of receive FIFO interrupt: -// The receive interrupt is asserted when there are four or more valid entries -// in the receive FIFO. -#define SSI_RIS_RXRIS 0x00000004 -#define SSI_RIS_RXRIS_BITN 2 -#define SSI_RIS_RXRIS_M 0x00000004 -#define SSI_RIS_RXRIS_S 2 - -// Field: [1] RTRIS -// -// Raw interrupt state of receive timeout interrupt: -// The receive timeout interrupt is asserted when the receive FIFO is not empty -// and SSI has remained idle for a fixed 32 bit period. This mechanism can be -// used to notify the user that data is still present in the receive FIFO and -// requires servicing. This interrupt is deasserted if the receive FIFO becomes -// empty by subsequent reads, or if new data is received on RXD. -// It can also be cleared by writing to ICR.RTIC. -#define SSI_RIS_RTRIS 0x00000002 -#define SSI_RIS_RTRIS_BITN 1 -#define SSI_RIS_RTRIS_M 0x00000002 -#define SSI_RIS_RTRIS_S 1 - -// Field: [0] RORRIS -// -// Raw interrupt state of receive overrun interrupt: -// The receive overrun interrupt is asserted when the FIFO is already full and -// an additional data frame is received, causing an overrun of the FIFO. Data -// is over-written in the -// receive shift register, but not the FIFO so the FIFO contents stay valid. -// It can also be cleared by writing to ICR.RORIC. -#define SSI_RIS_RORRIS 0x00000001 -#define SSI_RIS_RORRIS_BITN 0 -#define SSI_RIS_RORRIS_M 0x00000001 -#define SSI_RIS_RORRIS_S 0 - -//***************************************************************************** -// -// Register: SSI_O_MIS -// -//***************************************************************************** -// Field: [3] TXMIS -// -// Masked interrupt state of transmit FIFO interrupt: -// This field returns the masked interrupt state of transmit FIFO interrupt -// which is the AND product of raw interrupt state RIS.TXRIS and the mask -// setting IMSC.TXIM. -#define SSI_MIS_TXMIS 0x00000008 -#define SSI_MIS_TXMIS_BITN 3 -#define SSI_MIS_TXMIS_M 0x00000008 -#define SSI_MIS_TXMIS_S 3 - -// Field: [2] RXMIS -// -// Masked interrupt state of receive FIFO interrupt: -// This field returns the masked interrupt state of receive FIFO interrupt -// which is the AND product of raw interrupt state RIS.RXRIS and the mask -// setting IMSC.RXIM. -#define SSI_MIS_RXMIS 0x00000004 -#define SSI_MIS_RXMIS_BITN 2 -#define SSI_MIS_RXMIS_M 0x00000004 -#define SSI_MIS_RXMIS_S 2 - -// Field: [1] RTMIS -// -// Masked interrupt state of receive timeout interrupt: -// This field returns the masked interrupt state of receive timeout interrupt -// which is the AND product of raw interrupt state RIS.RTRIS and the mask -// setting IMSC.RTIM. -#define SSI_MIS_RTMIS 0x00000002 -#define SSI_MIS_RTMIS_BITN 1 -#define SSI_MIS_RTMIS_M 0x00000002 -#define SSI_MIS_RTMIS_S 1 - -// Field: [0] RORMIS -// -// Masked interrupt state of receive overrun interrupt: -// This field returns the masked interrupt state of receive overrun interrupt -// which is the AND product of raw interrupt state RIS.RORRIS and the mask -// setting IMSC.RORIM. -#define SSI_MIS_RORMIS 0x00000001 -#define SSI_MIS_RORMIS_BITN 0 -#define SSI_MIS_RORMIS_M 0x00000001 -#define SSI_MIS_RORMIS_S 0 - -//***************************************************************************** -// -// Register: SSI_O_ICR -// -//***************************************************************************** -// Field: [1] RTIC -// -// Clear the receive timeout interrupt: -// Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 -// has no effect. -#define SSI_ICR_RTIC 0x00000002 -#define SSI_ICR_RTIC_BITN 1 -#define SSI_ICR_RTIC_M 0x00000002 -#define SSI_ICR_RTIC_S 1 - -// Field: [0] RORIC -// -// Clear the receive overrun interrupt: -// Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). -// Writing 0 has no effect. -#define SSI_ICR_RORIC 0x00000001 -#define SSI_ICR_RORIC_BITN 0 -#define SSI_ICR_RORIC_M 0x00000001 -#define SSI_ICR_RORIC_S 0 - -//***************************************************************************** -// -// Register: SSI_O_DMACR -// -//***************************************************************************** -// Field: [1] TXDMAE -// -// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is -// enabled. -#define SSI_DMACR_TXDMAE 0x00000002 -#define SSI_DMACR_TXDMAE_BITN 1 -#define SSI_DMACR_TXDMAE_M 0x00000002 -#define SSI_DMACR_TXDMAE_S 1 - -// Field: [0] RXDMAE -// -// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is -// enabled. -#define SSI_DMACR_RXDMAE 0x00000001 -#define SSI_DMACR_RXDMAE_BITN 0 -#define SSI_DMACR_RXDMAE_M 0x00000001 -#define SSI_DMACR_RXDMAE_S 0 - - -#endif // __SSI__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_sysctl.h b/third_party/ti/devices/cc26x0/inc/hw_sysctl.h deleted file mode 100644 index 3fdb02f3c..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_sysctl.h +++ /dev/null @@ -1,49 +0,0 @@ -/****************************************************************************** -* Filename: hw_sysctl.h -* Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) -* Revision: 42989 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - - -//***************************************************************************** -// -// The following are initial defines for the MCU clock -// -//***************************************************************************** -#define GET_MCU_CLOCK 48000000 - - -#endif // __HW_SYSCTL_H__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_trng.h b/third_party/ti/devices/cc26x0/inc/hw_trng.h deleted file mode 100644 index 27ea3c2d5..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_trng.h +++ /dev/null @@ -1,609 +0,0 @@ -/****************************************************************************** -* Filename: hw_trng_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_TRNG_H__ -#define __HW_TRNG_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// TRNG component -// -//***************************************************************************** -// Random Number Lower Word Readout Value -#define TRNG_O_OUT0 0x00000000 - -// Random Number Upper Word Readout Value -#define TRNG_O_OUT1 0x00000004 - -// Interrupt Status -#define TRNG_O_IRQFLAGSTAT 0x00000008 - -// Interrupt Mask -#define TRNG_O_IRQFLAGMASK 0x0000000C - -// Interrupt Flag Clear -#define TRNG_O_IRQFLAGCLR 0x00000010 - -// Control -#define TRNG_O_CTL 0x00000014 - -// Configuration 0 -#define TRNG_O_CFG0 0x00000018 - -// Alarm Control -#define TRNG_O_ALARMCNT 0x0000001C - -// FRO Enable -#define TRNG_O_FROEN 0x00000020 - -// FRO De-tune Bit -#define TRNG_O_FRODETUNE 0x00000024 - -// Alarm Event -#define TRNG_O_ALARMMASK 0x00000028 - -// Alarm Shutdown -#define TRNG_O_ALARMSTOP 0x0000002C - -// LFSR Readout Value -#define TRNG_O_LFSR0 0x00000030 - -// LFSR Readout Value -#define TRNG_O_LFSR1 0x00000034 - -// LFSR Readout Value -#define TRNG_O_LFSR2 0x00000038 - -// TRNG Engine Options Information -#define TRNG_O_HWOPT 0x00000078 - -// HW Version 0 -#define TRNG_O_HWVER0 0x0000007C - -// Interrupt Status After Masking -#define TRNG_O_IRQSTATMASK 0x00001FD8 - -// HW Version 1 -#define TRNG_O_HWVER1 0x00001FE0 - -// Interrupt Set -#define TRNG_O_IRQSET 0x00001FEC - -// SW Reset Control -#define TRNG_O_SWRESET 0x00001FF0 - -// Interrupt Status -#define TRNG_O_IRQSTAT 0x00001FF8 - -//***************************************************************************** -// -// Register: TRNG_O_OUT0 -// -//***************************************************************************** -// Field: [31:0] VALUE_31_0 -// -// LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. -#define TRNG_OUT0_VALUE_31_0_W 32 -#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF -#define TRNG_OUT0_VALUE_31_0_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_OUT1 -// -//***************************************************************************** -// Field: [31:0] VALUE_63_32 -// -// MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. -#define TRNG_OUT1_VALUE_63_32_W 32 -#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF -#define TRNG_OUT1_VALUE_63_32_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQFLAGSTAT -// -//***************************************************************************** -// Field: [31] NEED_CLOCK -// -// 1: Indicates that the TRNG is busy generating entropy or is in one of its -// test modes - clocks may not be turned off and the power supply voltage must -// be kept stable. -// 0: TRNG is idle and can be shut down -#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 - -// Field: [1] SHUTDOWN_OVF -// -// 1: The number of FROs shut down (i.e. the number of '1' bits in the -// ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR -// -// Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 - -// Field: [0] RDY -// -// 1: Data are available in OUT0 and OUT1. -// -// Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to -// '0'. -// If a new number is already available in the internal register of the TRNG, -// the number is directly clocked into the result register. In this case the -// status bit is asserted again, after one clock cycle. -#define TRNG_IRQFLAGSTAT_RDY 0x00000001 -#define TRNG_IRQFLAGSTAT_RDY_BITN 0 -#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 -#define TRNG_IRQFLAGSTAT_RDY_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQFLAGMASK -// -//***************************************************************************** -// Field: [1] SHUTDOWN_OVF -// -// 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this -// module. -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 - -// Field: [0] RDY -// -// 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. -#define TRNG_IRQFLAGMASK_RDY 0x00000001 -#define TRNG_IRQFLAGMASK_RDY_BITN 0 -#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 -#define TRNG_IRQFLAGMASK_RDY_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQFLAGCLR -// -//***************************************************************************** -// Field: [1] SHUTDOWN_OVF -// -// 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 - -// Field: [0] RDY -// -// 1: Clear IRQFLAGSTAT.RDY. -#define TRNG_IRQFLAGCLR_RDY 0x00000001 -#define TRNG_IRQFLAGCLR_RDY_BITN 0 -#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 -#define TRNG_IRQFLAGCLR_RDY_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_CTL -// -//***************************************************************************** -// Field: [31:16] STARTUP_CYCLES -// -// This field determines the number of samples (between 2^8 and 2^24) taken to -// gather entropy from the FROs during startup. If the written value of this -// field is zero, the number of samples is 2^24, otherwise the number of -// samples equals the written value times 2^8. -// -// 0x0000: 2^24 samples -// 0x0001: 1*2^8 samples -// 0x0002: 2*2^8 samples -// 0x0003: 3*2^8 samples -// ... -// 0x8000: 32768*2^8 samples -// 0xC000: 49152*2^8 samples -// ... -// 0xFFFF: 65535*2^8 samples -// -// This field can only be modified while TRNG_EN is 0. If 1 an update will be -// ignored. -#define TRNG_CTL_STARTUP_CYCLES_W 16 -#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 -#define TRNG_CTL_STARTUP_CYCLES_S 16 - -// Field: [10] TRNG_EN -// -// 0: Forces all TRNG logic back into the idle state immediately. -// 1: Starts TRNG, gathering entropy from the FROs for the number of samples -// determined by STARTUP_CYCLES. -#define TRNG_CTL_TRNG_EN 0x00000400 -#define TRNG_CTL_TRNG_EN_BITN 10 -#define TRNG_CTL_TRNG_EN_M 0x00000400 -#define TRNG_CTL_TRNG_EN_S 10 - -// Field: [2] NO_LFSR_FB -// -// 1: Remove XNOR feedback from the main LFSR, converting it into a normal -// shift register for the XOR-ed outputs of the FROs (shifting data in on the -// LSB side). A '1' also forces the LFSR to sample continuously. -// -// This bit can only be set to '1' when TEST_MODE is also set to '1' and should -// not be used for other than test purposes -#define TRNG_CTL_NO_LFSR_FB 0x00000004 -#define TRNG_CTL_NO_LFSR_FB_BITN 2 -#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 -#define TRNG_CTL_NO_LFSR_FB_S 2 - -// Field: [1] TEST_MODE -// -// 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter -// are automatically cleared before enabling access) and keeps -// IRQFLAGSTAT.NEED_CLOCK at '1'. -// -// This bit shall not be used unless you need to change the LFSR seed prior to -// creating a new random value. All other testing is done external to register -// control. -#define TRNG_CTL_TEST_MODE 0x00000002 -#define TRNG_CTL_TEST_MODE_BITN 1 -#define TRNG_CTL_TEST_MODE_M 0x00000002 -#define TRNG_CTL_TEST_MODE_S 1 - -//***************************************************************************** -// -// Register: TRNG_O_CFG0 -// -//***************************************************************************** -// Field: [31:16] MAX_REFILL_CYCLES -// -// This field determines the maximum number of samples (between 2^8 and 2^24) -// taken to re-generate entropy from the FROs after reading out a 64 bits -// random number. If the written value of this field is zero, the number of -// samples is 2^24, otherwise the number of samples equals the written value -// times 2^8. -// -// 0x0000: 2^24 samples -// 0x0001: 1*2^8 samples -// 0x0002: 2*2^8 samples -// 0x0003: 3*2^8 samples -// ... -// 0x8000: 32768*2^8 samples -// 0xC000: 49152*2^8 samples -// ... -// 0xFFFF: 65535*2^8 samples -// -// This field can only be modified while CTL.TRNG_EN is 0. -#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 -#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 -#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 - -// Field: [11:8] SMPL_DIV -// -// This field directly controls the number of clock cycles between samples -// taken from the FROs. Default value 0 indicates that samples are taken every -// clock cycle, -// maximum value 0xF takes one sample every 16 clock cycles. -// This field must be set to a value such that the slowest FRO (even under -// worst-case -// conditions) has a cycle time less than twice the sample period. -// -// This field can only be modified while CTL.TRNG_EN is '0'. -#define TRNG_CFG0_SMPL_DIV_W 4 -#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 -#define TRNG_CFG0_SMPL_DIV_S 8 - -// Field: [7:0] MIN_REFILL_CYCLES -// -// This field determines the minimum number of samples (between 2^6 and 2^14) -// taken to re-generate entropy from the FROs after reading out a 64 bits -// random number. If the value of this field is zero, the number of samples is -// fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the -// minimum number of samples equals the written value times 64 (which can be up -// to 2^14). To ensure same entropy in all generated random numbers the value 0 -// should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. -// The number of samples defined here cannot be higher than the number defined -// by the 'max_refill_cycles' field (i.e. that field takes precedence). No -// random value will be created if min refill > max refill. -// -// This field can only be modified while CTL.TRNG_EN = 0. -// -// 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) -// 0x01: 1*2^6 samples -// 0x02: 2*2^6 samples -// ... -// 0xFF: 255*2^6 samples -#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 -#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF -#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_ALARMCNT -// -//***************************************************************************** -// Field: [29:24] SHUTDOWN_CNT -// -// Read-only, indicates the number of '1' bits in ALARMSTOP register. -// The maximum value equals the number of FROs. -#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 -#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 -#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 - -// Field: [20:16] SHUTDOWN_THR -// -// Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The -// interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. -#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 -#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 -#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 - -// Field: [7:0] ALARM_THR -// -// Alarm detection threshold for the repeating pattern detectors on each FRO. -// An FRO 'alarm event' is declared when a repeating pattern (of up to four -// samples length) is detected continuously for the number of samples defined -// by this field's value. Reset value 0xFF should keep the number of 'alarm -// events' to a manageable level. -#define TRNG_ALARMCNT_ALARM_THR_W 8 -#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF -#define TRNG_ALARMCNT_ALARM_THR_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_FROEN -// -//***************************************************************************** -// Field: [23:0] FRO_MASK -// -// Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. -// Default state is all '1's to enable all FROs after power-up. Note that they -// are not actually started up before the CTL.TRNG_EN bit is set to '1'. -// -// Bits are automatically forced to '0' here (and cannot be written to '1') -// while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. -#define TRNG_FROEN_FRO_MASK_W 24 -#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF -#define TRNG_FROEN_FRO_MASK_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_FRODETUNE -// -//***************************************************************************** -// Field: [23:0] FRO_MASK -// -// De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run -// approximately 5% faster. The value of one of these bits may only be changed -// while the corresponding FRO is turned off (by temporarily writing a '0' in -// the corresponding -// bit of the FROEN.FRO_MASK register). -#define TRNG_FRODETUNE_FRO_MASK_W 24 -#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF -#define TRNG_FRODETUNE_FRO_MASK_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_ALARMMASK -// -//***************************************************************************** -// Field: [23:0] FRO_MASK -// -// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] -// indicates FRO 'n' experienced an 'alarm event'. -#define TRNG_ALARMMASK_FRO_MASK_W 24 -#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF -#define TRNG_ALARMMASK_FRO_MASK_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_ALARMSTOP -// -//***************************************************************************** -// Field: [23:0] FRO_FLAGS -// -// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] -// indicates FRO 'n' experienced more than one 'alarm event' in quick -// succession and has been turned off. A '1' in this field forces the -// corresponding bit in FROEN.FRO_MASK to '0'. -#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 -#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF -#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_LFSR0 -// -//***************************************************************************** -// Field: [31:0] LFSR_31_0 -// -// Bits [31:0] of the main entropy accumulation LFSR. Register can only be -// accessed when CTL.TEST_MODE = 1. -// Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR0_LFSR_31_0_W 32 -#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF -#define TRNG_LFSR0_LFSR_31_0_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_LFSR1 -// -//***************************************************************************** -// Field: [31:0] LFSR_63_32 -// -// Bits [63:32] of the main entropy accumulation LFSR. Register can only be -// accessed when CTL.TEST_MODE = 1. -// Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR1_LFSR_63_32_W 32 -#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF -#define TRNG_LFSR1_LFSR_63_32_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_LFSR2 -// -//***************************************************************************** -// Field: [16:0] LFSR_80_64 -// -// Bits [80:64] of the main entropy accumulation LFSR. Register can only be -// accessed when CTL.TEST_MODE = 1. -// Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR2_LFSR_80_64_W 17 -#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF -#define TRNG_LFSR2_LFSR_80_64_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_HWOPT -// -//***************************************************************************** -// Field: [11:6] NR_OF_FROS -// -// Number of FROs implemented in this TRNG, value 24 (decimal). -#define TRNG_HWOPT_NR_OF_FROS_W 6 -#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 -#define TRNG_HWOPT_NR_OF_FROS_S 6 - -//***************************************************************************** -// -// Register: TRNG_O_HWVER0 -// -//***************************************************************************** -// Field: [27:24] HW_MAJOR_VER -// -// 4 bits binary encoding of the major hardware revision number. -#define TRNG_HWVER0_HW_MAJOR_VER_W 4 -#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 -#define TRNG_HWVER0_HW_MAJOR_VER_S 24 - -// Field: [23:20] HW_MINOR_VER -// -// 4 bits binary encoding of the minor hardware revision number. -#define TRNG_HWVER0_HW_MINOR_VER_W 4 -#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 -#define TRNG_HWVER0_HW_MINOR_VER_S 20 - -// Field: [19:16] HW_PATCH_LVL -// -// 4 bits binary encoding of the hardware patch level, initial release will -// carry value zero. -#define TRNG_HWVER0_HW_PATCH_LVL_W 4 -#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 -#define TRNG_HWVER0_HW_PATCH_LVL_S 16 - -// Field: [15:8] EIP_NUM_COMPL -// -// Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. -#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 -#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 -#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 - -// Field: [7:0] EIP_NUM -// -// 8 bits binary encoding of the module number. This TRNG gives 0x4B. -#define TRNG_HWVER0_EIP_NUM_W 8 -#define TRNG_HWVER0_EIP_NUM_M 0x000000FF -#define TRNG_HWVER0_EIP_NUM_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQSTATMASK -// -//***************************************************************************** -// Field: [1] SHUTDOWN_OVF -// -// Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with -// IRQFLAGMASK.SHUTDOWN_OVF) -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 - -// Field: [0] RDY -// -// New random value available (result of IRQFLAGSTAT.RDY AND'ed with -// IRQFLAGMASK.RDY) -#define TRNG_IRQSTATMASK_RDY 0x00000001 -#define TRNG_IRQSTATMASK_RDY_BITN 0 -#define TRNG_IRQSTATMASK_RDY_M 0x00000001 -#define TRNG_IRQSTATMASK_RDY_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_HWVER1 -// -//***************************************************************************** -// Field: [7:0] REV -// -// The revision number of this module is Rev 2.0. -#define TRNG_HWVER1_REV_W 8 -#define TRNG_HWVER1_REV_M 0x000000FF -#define TRNG_HWVER1_REV_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQSET -// -//***************************************************************************** -//***************************************************************************** -// -// Register: TRNG_O_SWRESET -// -//***************************************************************************** -// Field: [0] RESET -// -// Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 -// for reset to be completed. -#define TRNG_SWRESET_RESET 0x00000001 -#define TRNG_SWRESET_RESET_BITN 0 -#define TRNG_SWRESET_RESET_M 0x00000001 -#define TRNG_SWRESET_RESET_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQSTAT -// -//***************************************************************************** -// Field: [0] STAT -// -// TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and -// IRQFLAGSTAT.RDY -#define TRNG_IRQSTAT_STAT 0x00000001 -#define TRNG_IRQSTAT_STAT_BITN 0 -#define TRNG_IRQSTAT_STAT_M 0x00000001 -#define TRNG_IRQSTAT_STAT_S 0 - - -#endif // __TRNG__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_types.h b/third_party/ti/devices/cc26x0/inc/hw_types.h deleted file mode 100644 index 3f6fe1422..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_types.h +++ /dev/null @@ -1,123 +0,0 @@ -/****************************************************************************** -* Filename: hw_types.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 -* -* Description: Common types and macros. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -#include -#include -#include "../inc/hw_chip_def.h" - -//***************************************************************************** -// -// Common driverlib types -// -//***************************************************************************** -typedef void (* FPTR_VOID_VOID_T) (void); -typedef void (* FPTR_VOID_UINT8_T) (uint8_t); - -//***************************************************************************** -// -// This symbol forces simple driverlib functions to be inlined in the code -// instead of using function calls. -// -//***************************************************************************** -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif - -//***************************************************************************** -// -// C99 types only allows bitfield defintions on certain datatypes. -// -//***************************************************************************** -typedef unsigned int __UINT32; - -//***************************************************************************** -// -// Macros for direct hardware access. -// -// If using these macros the programmer should be aware of any limitations to -// the address accessed i.e. if it supports word and/or byte access. -// -//***************************************************************************** -// Word (32 bit) access to address x -// Read example : my32BitVar = HWREG(base_addr + offset) ; -// Write example : HWREG(base_addr + offset) = my32BitVar ; -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) - -// Half word (16 bit) access to address x -// Read example : my16BitVar = HWREGH(base_addr + offset) ; -// Write example : HWREGH(base_addr + offset) = my16BitVar ; -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) - -// Byte (8 bit) access to address x -// Read example : my8BitVar = HWREGB(base_addr + offset) ; -// Write example : HWREGB(base_addr + offset) = my8BitVar ; -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) - -//***************************************************************************** -// -// Macros for hardware access to bit-band supported addresses via the bit-band region. -// -// Macros calculate the corresponding address to access in the bit-band region -// based on the actual address of the memory/register and the bit number. -// -// Do NOT use these macros to access the bit-band region directly! -// -//***************************************************************************** -// Bit-band access to address x bit number b using word access (32 bit) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -// Bit-band access to address x bit number b using half word access (16 bit) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -// Bit-band access to address x bit number b using byte access (8 bit) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - - -#endif // __HW_TYPES_H__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_uart.h b/third_party/ti/devices/cc26x0/inc/hw_uart.h deleted file mode 100644 index 7fd5a670e..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_uart.h +++ /dev/null @@ -1,1044 +0,0 @@ -/****************************************************************************** -* Filename: hw_uart_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// UART component -// -//***************************************************************************** -// Data -#define UART_O_DR 0x00000000 - -// Status -#define UART_O_RSR 0x00000004 - -// Error Clear -#define UART_O_ECR 0x00000004 - -// Flag -#define UART_O_FR 0x00000018 - -// Integer Baud-Rate Divisor -#define UART_O_IBRD 0x00000024 - -// Fractional Baud-Rate Divisor -#define UART_O_FBRD 0x00000028 - -// Line Control -#define UART_O_LCRH 0x0000002C - -// Control -#define UART_O_CTL 0x00000030 - -// Interrupt FIFO Level Select -#define UART_O_IFLS 0x00000034 - -// Interrupt Mask Set/Clear -#define UART_O_IMSC 0x00000038 - -// Raw Interrupt Status -#define UART_O_RIS 0x0000003C - -// Masked Interrupt Status -#define UART_O_MIS 0x00000040 - -// Interrupt Clear -#define UART_O_ICR 0x00000044 - -// DMA Control -#define UART_O_DMACTL 0x00000048 - -//***************************************************************************** -// -// Register: UART_O_DR -// -//***************************************************************************** -// Field: [11] OE -// -// UART Overrun Error: -// This bit is set to 1 if data is received and the receive FIFO is already -// full. The FIFO contents remain valid because no more data is written when -// the FIFO is full, , only the contents of the shift register are overwritten. -// This is cleared to 0 once there is an empty space in the FIFO and a new -// character can be written to it. -#define UART_DR_OE 0x00000800 -#define UART_DR_OE_BITN 11 -#define UART_DR_OE_M 0x00000800 -#define UART_DR_OE_S 11 - -// Field: [10] BE -// -// UART Break Error: -// This bit is set to 1 if a break condition was detected, indicating that the -// received data input (UARTRXD input pin) was held LOW for longer than a -// full-word transmission time (defined as start, data, parity and stop bits). -// In FIFO mode, this error is associated with the character at the top of the -// FIFO (i.e., the oldest received data character since last read). When a -// break occurs, a 0 character is loaded into the FIFO. The next character is -// enabled after the receive data input (UARTRXD input pin) goes to a 1 -// (marking state), and the next valid start bit is received. -#define UART_DR_BE 0x00000400 -#define UART_DR_BE_BITN 10 -#define UART_DR_BE_M 0x00000400 -#define UART_DR_BE_S 10 - -// Field: [9] PE -// -// UART Parity Error: -// When set to 1, it indicates that the parity of the received data character -// does not match the parity that the LCRH.EPS and LCRH.SPS select. -// In FIFO mode, this error is associated with the character at the top of the -// FIFO (i.e., the oldest received data character since last read). -#define UART_DR_PE 0x00000200 -#define UART_DR_PE_BITN 9 -#define UART_DR_PE_M 0x00000200 -#define UART_DR_PE_S 9 - -// Field: [8] FE -// -// UART Framing Error: -// When set to 1, it indicates that the received character did not have a valid -// stop bit (a valid stop bit is 1). -// In FIFO mode, this error is associated with the character at the top of the -// FIFO (i.e., the oldest received data character since last read). -#define UART_DR_FE 0x00000100 -#define UART_DR_FE_BITN 8 -#define UART_DR_FE_M 0x00000100 -#define UART_DR_FE_S 8 - -// Field: [7:0] DATA -// -// Data transmitted or received: -// On writes, the transmit data character is pushed into the FIFO. -// On reads, the oldest received data character since the last read is -// returned. -#define UART_DR_DATA_W 8 -#define UART_DR_DATA_M 0x000000FF -#define UART_DR_DATA_S 0 - -//***************************************************************************** -// -// Register: UART_O_RSR -// -//***************************************************************************** -// Field: [3] OE -// -// UART Overrun Error: -// This bit is set to 1 if data is received and the receive FIFO is already -// full. The FIFO contents remain valid because no more data is written when -// the FIFO is full, , only the contents of the shift register are overwritten. -// This is cleared to 0 once there is an empty space in the FIFO and a new -// character can be written to it. -#define UART_RSR_OE 0x00000008 -#define UART_RSR_OE_BITN 3 -#define UART_RSR_OE_M 0x00000008 -#define UART_RSR_OE_S 3 - -// Field: [2] BE -// -// UART Break Error: -// This bit is set to 1 if a break condition was detected, indicating that the -// received data input (UARTRXD input pin) was held LOW for longer than a -// full-word transmission time (defined as start, data, parity and stop bits). -// When a break occurs, a 0 character is loaded into the FIFO. The next -// character is enabled after the receive data input (UARTRXD input pin) goes -// to a 1 (marking state), and the next valid start bit is received. -#define UART_RSR_BE 0x00000004 -#define UART_RSR_BE_BITN 2 -#define UART_RSR_BE_M 0x00000004 -#define UART_RSR_BE_S 2 - -// Field: [1] PE -// -// UART Parity Error: -// When set to 1, it indicates that the parity of the received data character -// does not match the parity that the LCRH.EPS and LCRH.SPS select. -#define UART_RSR_PE 0x00000002 -#define UART_RSR_PE_BITN 1 -#define UART_RSR_PE_M 0x00000002 -#define UART_RSR_PE_S 1 - -// Field: [0] FE -// -// UART Framing Error: -// When set to 1, it indicates that the received character did not have a valid -// stop bit (a valid stop bit is 1). -#define UART_RSR_FE 0x00000001 -#define UART_RSR_FE_BITN 0 -#define UART_RSR_FE_M 0x00000001 -#define UART_RSR_FE_S 0 - -//***************************************************************************** -// -// Register: UART_O_ECR -// -//***************************************************************************** -// Field: [3] OE -// -// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are -// cleared to 0 by any write to this register. -#define UART_ECR_OE 0x00000008 -#define UART_ECR_OE_BITN 3 -#define UART_ECR_OE_M 0x00000008 -#define UART_ECR_OE_S 3 - -// Field: [2] BE -// -// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are -// cleared to 0 by any write to this register. -#define UART_ECR_BE 0x00000004 -#define UART_ECR_BE_BITN 2 -#define UART_ECR_BE_M 0x00000004 -#define UART_ECR_BE_S 2 - -// Field: [1] PE -// -// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are -// cleared to 0 by any write to this register. -#define UART_ECR_PE 0x00000002 -#define UART_ECR_PE_BITN 1 -#define UART_ECR_PE_M 0x00000002 -#define UART_ECR_PE_S 1 - -// Field: [0] FE -// -// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are -// cleared to 0 by any write to this register. -#define UART_ECR_FE 0x00000001 -#define UART_ECR_FE_BITN 0 -#define UART_ECR_FE_M 0x00000001 -#define UART_ECR_FE_S 0 - -//***************************************************************************** -// -// Register: UART_O_FR -// -//***************************************************************************** -// Field: [7] TXFE -// -// UART Transmit FIFO Empty: -// The meaning of this bit depends on the state of LCRH.FEN . -// - If the FIFO is disabled, this bit is set when the transmit holding -// register is empty. -// - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. -// This bit does not indicate if there is data in the transmit shift register. -#define UART_FR_TXFE 0x00000080 -#define UART_FR_TXFE_BITN 7 -#define UART_FR_TXFE_M 0x00000080 -#define UART_FR_TXFE_S 7 - -// Field: [6] RXFF -// -// UART Receive FIFO Full: -// The meaning of this bit depends on the state of LCRH.FEN. -// - If the FIFO is disabled, this bit is set when the receive holding -// register is full. -// - If the FIFO is enabled, this bit is set when the receive FIFO is full. -#define UART_FR_RXFF 0x00000040 -#define UART_FR_RXFF_BITN 6 -#define UART_FR_RXFF_M 0x00000040 -#define UART_FR_RXFF_S 6 - -// Field: [5] TXFF -// -// UART Transmit FIFO Full: -// Transmit FIFO full. The meaning of this bit depends on the state of -// LCRH.FEN. -// - If the FIFO is disabled, this bit is set when the transmit holding -// register is full. -// - If the FIFO is enabled, this bit is set when the transmit FIFO is full. -#define UART_FR_TXFF 0x00000020 -#define UART_FR_TXFF_BITN 5 -#define UART_FR_TXFF_M 0x00000020 -#define UART_FR_TXFF_S 5 - -// Field: [4] RXFE -// -// UART Receive FIFO Empty: -// Receive FIFO empty. The meaning of this bit depends on the state of -// LCRH.FEN. -// - If the FIFO is disabled, this bit is set when the receive holding -// register is empty. -// - If the FIFO is enabled, this bit is set when the receive FIFO is empty. -#define UART_FR_RXFE 0x00000010 -#define UART_FR_RXFE_BITN 4 -#define UART_FR_RXFE_M 0x00000010 -#define UART_FR_RXFE_S 4 - -// Field: [3] BUSY -// -// UART Busy: -// If this bit is set to 1, the UART is busy transmitting data. This bit -// remains set until the complete byte, including all the stop bits, has been -// sent from the shift register. -// This bit is set as soon as the transmit FIFO becomes non-empty, regardless -// of whether the UART is enabled or not. -#define UART_FR_BUSY 0x00000008 -#define UART_FR_BUSY_BITN 3 -#define UART_FR_BUSY_M 0x00000008 -#define UART_FR_BUSY_S 3 - -// Field: [0] CTS -// -// Clear To Send: -// This bit is the complement of the active-low UART CTS input pin. -// That is, the bit is 1 when CTS input pin is LOW. -#define UART_FR_CTS 0x00000001 -#define UART_FR_CTS_BITN 0 -#define UART_FR_CTS_M 0x00000001 -#define UART_FR_CTS_S 0 - -//***************************************************************************** -// -// Register: UART_O_IBRD -// -//***************************************************************************** -// Field: [15:0] DIVINT -// -// The integer baud rate divisor: -// The baud rate divisor is calculated using the formula below: -// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) -// Baud rate divisor must be minimum 1 and maximum 65535. -// That is, DIVINT=0 does not give a valid baud rate. -// Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be -// illegal. -// A valid value must be written to this field before the UART can be used for -// RX or TX operations. -#define UART_IBRD_DIVINT_W 16 -#define UART_IBRD_DIVINT_M 0x0000FFFF -#define UART_IBRD_DIVINT_S 0 - -//***************************************************************************** -// -// Register: UART_O_FBRD -// -//***************************************************************************** -// Field: [5:0] DIVFRAC -// -// Fractional Baud-Rate Divisor: -// The baud rate divisor is calculated using the formula below: -// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) -// Baud rate divisor must be minimum 1 and maximum 65535. -// That is, IBRD.DIVINT=0 does not give a valid baud rate. -// Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be -// illegal. -// A valid value must be written to this field before the UART can be used for -// RX or TX operations. -#define UART_FBRD_DIVFRAC_W 6 -#define UART_FBRD_DIVFRAC_M 0x0000003F -#define UART_FBRD_DIVFRAC_S 0 - -//***************************************************************************** -// -// Register: UART_O_LCRH -// -//***************************************************************************** -// Field: [7] SPS -// -// UART Stick Parity Select: -// -// 0: Stick parity is disabled -// 1: The parity bit is transmitted and checked as invert of EPS field (i.e. -// the parity bit is transmitted and checked as 1 when EPS = 0). -// -// This bit has no effect when PEN disables parity checking and generation. -#define UART_LCRH_SPS 0x00000080 -#define UART_LCRH_SPS_BITN 7 -#define UART_LCRH_SPS_M 0x00000080 -#define UART_LCRH_SPS_S 7 - -// Field: [6:5] WLEN -// -// UART Word Length: -// These bits indicate the number of data bits transmitted or received in a -// frame. -// ENUMs: -// 8 Word Length 8 bits -// 7 Word Length 7 bits -// 6 Word Length 6 bits -// 5 Word Length 5 bits -#define UART_LCRH_WLEN_W 2 -#define UART_LCRH_WLEN_M 0x00000060 -#define UART_LCRH_WLEN_S 5 -#define UART_LCRH_WLEN_8 0x00000060 -#define UART_LCRH_WLEN_7 0x00000040 -#define UART_LCRH_WLEN_6 0x00000020 -#define UART_LCRH_WLEN_5 0x00000000 - -// Field: [4] FEN -// -// UART Enable FIFOs -// ENUMs: -// EN Transmit and receive FIFO buffers are enabled -// (FIFO mode) -// DIS FIFOs are disabled (character mode) that is, the -// FIFOs become 1-byte-deep holding registers. -#define UART_LCRH_FEN 0x00000010 -#define UART_LCRH_FEN_BITN 4 -#define UART_LCRH_FEN_M 0x00000010 -#define UART_LCRH_FEN_S 4 -#define UART_LCRH_FEN_EN 0x00000010 -#define UART_LCRH_FEN_DIS 0x00000000 - -// Field: [3] STP2 -// -// UART Two Stop Bits Select: -// If this bit is set to 1, two stop bits are transmitted at the end of the -// frame. The receive logic does not check for two stop bits being received. -#define UART_LCRH_STP2 0x00000008 -#define UART_LCRH_STP2_BITN 3 -#define UART_LCRH_STP2_M 0x00000008 -#define UART_LCRH_STP2_S 3 - -// Field: [2] EPS -// -// UART Even Parity Select -// ENUMs: -// EVEN Even parity: The UART generates or checks for an -// even number of 1s in the data and parity bits. -// ODD Odd parity: The UART generates or checks for an -// odd number of 1s in the data and parity bits. -#define UART_LCRH_EPS 0x00000004 -#define UART_LCRH_EPS_BITN 2 -#define UART_LCRH_EPS_M 0x00000004 -#define UART_LCRH_EPS_S 2 -#define UART_LCRH_EPS_EVEN 0x00000004 -#define UART_LCRH_EPS_ODD 0x00000000 - -// Field: [1] PEN -// -// UART Parity Enable -// This bit controls generation and checking of parity bit. -// ENUMs: -// EN Parity checking and generation is enabled. -// DIS Parity is disabled and no parity bit is added to -// the data frame -#define UART_LCRH_PEN 0x00000002 -#define UART_LCRH_PEN_BITN 1 -#define UART_LCRH_PEN_M 0x00000002 -#define UART_LCRH_PEN_S 1 -#define UART_LCRH_PEN_EN 0x00000002 -#define UART_LCRH_PEN_DIS 0x00000000 - -// Field: [0] BRK -// -// UART Send Break -// If this bit is set to 1, a low-level is continually output on the UARTTXD -// output pin, after completing transmission of the current character. For the -// proper execution of the break command, the -// software must set this bit for at least two complete frames. For normal use, -// this bit must be cleared to 0. -#define UART_LCRH_BRK 0x00000001 -#define UART_LCRH_BRK_BITN 0 -#define UART_LCRH_BRK_M 0x00000001 -#define UART_LCRH_BRK_S 0 - -//***************************************************************************** -// -// Register: UART_O_CTL -// -//***************************************************************************** -// Field: [15] CTSEN -// -// CTS hardware flow control enable -// ENUMs: -// EN CTS hardware flow control enabled -// DIS CTS hardware flow control disabled -#define UART_CTL_CTSEN 0x00008000 -#define UART_CTL_CTSEN_BITN 15 -#define UART_CTL_CTSEN_M 0x00008000 -#define UART_CTL_CTSEN_S 15 -#define UART_CTL_CTSEN_EN 0x00008000 -#define UART_CTL_CTSEN_DIS 0x00000000 - -// Field: [14] RTSEN -// -// RTS hardware flow control enable -// ENUMs: -// EN RTS hardware flow control enabled -// DIS RTS hardware flow control disabled -#define UART_CTL_RTSEN 0x00004000 -#define UART_CTL_RTSEN_BITN 14 -#define UART_CTL_RTSEN_M 0x00004000 -#define UART_CTL_RTSEN_S 14 -#define UART_CTL_RTSEN_EN 0x00004000 -#define UART_CTL_RTSEN_DIS 0x00000000 - -// Field: [11] RTS -// -// Request to Send -// This bit is the complement of the active-low UART RTS output. That is, when -// the bit is programmed to a 1 then RTS output on the pins is LOW. -#define UART_CTL_RTS 0x00000800 -#define UART_CTL_RTS_BITN 11 -#define UART_CTL_RTS_M 0x00000800 -#define UART_CTL_RTS_S 11 - -// Field: [9] RXE -// -// UART Receive Enable -// If the UART is disabled in the middle of reception, it completes the current -// character before stopping. -// ENUMs: -// EN UART Receive enabled -// DIS UART Receive disabled -#define UART_CTL_RXE 0x00000200 -#define UART_CTL_RXE_BITN 9 -#define UART_CTL_RXE_M 0x00000200 -#define UART_CTL_RXE_S 9 -#define UART_CTL_RXE_EN 0x00000200 -#define UART_CTL_RXE_DIS 0x00000000 - -// Field: [8] TXE -// -// UART Transmit Enable -// If the UART is disabled in the middle of transmission, it completes the -// current character before stopping. -// ENUMs: -// EN UART Transmit enabled -// DIS UART Transmit disabled -#define UART_CTL_TXE 0x00000100 -#define UART_CTL_TXE_BITN 8 -#define UART_CTL_TXE_M 0x00000100 -#define UART_CTL_TXE_S 8 -#define UART_CTL_TXE_EN 0x00000100 -#define UART_CTL_TXE_DIS 0x00000000 - -// Field: [7] LBE -// -// UART Loop Back Enable: -// Enabling the loop-back mode connects the UARTTXD output from the UART to -// UARTRXD input of the UART. -// ENUMs: -// EN Loop Back enabled -// DIS Loop Back disabled -#define UART_CTL_LBE 0x00000080 -#define UART_CTL_LBE_BITN 7 -#define UART_CTL_LBE_M 0x00000080 -#define UART_CTL_LBE_S 7 -#define UART_CTL_LBE_EN 0x00000080 -#define UART_CTL_LBE_DIS 0x00000000 - -// Field: [0] UARTEN -// -// UART Enable -// ENUMs: -// EN UART enabled -// DIS UART disabled -#define UART_CTL_UARTEN 0x00000001 -#define UART_CTL_UARTEN_BITN 0 -#define UART_CTL_UARTEN_M 0x00000001 -#define UART_CTL_UARTEN_S 0 -#define UART_CTL_UARTEN_EN 0x00000001 -#define UART_CTL_UARTEN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: UART_O_IFLS -// -//***************************************************************************** -// Field: [5:3] RXSEL -// -// Receive interrupt FIFO level select: -// This field sets the trigger points for the receive interrupt. Values -// 0b101-0b111 are reserved. -// ENUMs: -// 7_8 Receive FIFO becomes >= 7/8 full -// 6_8 Receive FIFO becomes >= 3/4 full -// 4_8 Receive FIFO becomes >= 1/2 full -// 2_8 Receive FIFO becomes >= 1/4 full -// 1_8 Receive FIFO becomes >= 1/8 full -#define UART_IFLS_RXSEL_W 3 -#define UART_IFLS_RXSEL_M 0x00000038 -#define UART_IFLS_RXSEL_S 3 -#define UART_IFLS_RXSEL_7_8 0x00000020 -#define UART_IFLS_RXSEL_6_8 0x00000018 -#define UART_IFLS_RXSEL_4_8 0x00000010 -#define UART_IFLS_RXSEL_2_8 0x00000008 -#define UART_IFLS_RXSEL_1_8 0x00000000 - -// Field: [2:0] TXSEL -// -// Transmit interrupt FIFO level select: -// This field sets the trigger points for the transmit interrupt. Values -// 0b101-0b111 are reserved. -// ENUMs: -// 7_8 Transmit FIFO becomes <= 7/8 full -// 6_8 Transmit FIFO becomes <= 3/4 full -// 4_8 Transmit FIFO becomes <= 1/2 full -// 2_8 Transmit FIFO becomes <= 1/4 full -// 1_8 Transmit FIFO becomes <= 1/8 full -#define UART_IFLS_TXSEL_W 3 -#define UART_IFLS_TXSEL_M 0x00000007 -#define UART_IFLS_TXSEL_S 0 -#define UART_IFLS_TXSEL_7_8 0x00000004 -#define UART_IFLS_TXSEL_6_8 0x00000003 -#define UART_IFLS_TXSEL_4_8 0x00000002 -#define UART_IFLS_TXSEL_2_8 0x00000001 -#define UART_IFLS_TXSEL_1_8 0x00000000 - -//***************************************************************************** -// -// Register: UART_O_IMSC -// -//***************************************************************************** -// Field: [10] OEIM -// -// Overrun error interrupt mask. A read returns the current mask for UART's -// overrun error interrupt. On a write of 1, the mask of the overrun error -// interrupt is set which means the interrupt state will be reflected in -// MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not -// reflect the interrupt. -#define UART_IMSC_OEIM 0x00000400 -#define UART_IMSC_OEIM_BITN 10 -#define UART_IMSC_OEIM_M 0x00000400 -#define UART_IMSC_OEIM_S 10 - -// Field: [9] BEIM -// -// Break error interrupt mask. A read returns the current mask for UART's break -// error interrupt. On a write of 1, the mask of the overrun error interrupt is -// set which means the interrupt state will be reflected in MIS.BEMIS. A write -// of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. -#define UART_IMSC_BEIM 0x00000200 -#define UART_IMSC_BEIM_BITN 9 -#define UART_IMSC_BEIM_M 0x00000200 -#define UART_IMSC_BEIM_S 9 - -// Field: [8] PEIM -// -// Parity error interrupt mask. A read returns the current mask for UART's -// parity error interrupt. On a write of 1, the mask of the overrun error -// interrupt is set which means the interrupt state will be reflected in -// MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not -// reflect the interrupt. -#define UART_IMSC_PEIM 0x00000100 -#define UART_IMSC_PEIM_BITN 8 -#define UART_IMSC_PEIM_M 0x00000100 -#define UART_IMSC_PEIM_S 8 - -// Field: [7] FEIM -// -// Framing error interrupt mask. A read returns the current mask for UART's -// framing error interrupt. On a write of 1, the mask of the overrun error -// interrupt is set which means the interrupt state will be reflected in -// MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not -// reflect the interrupt. -#define UART_IMSC_FEIM 0x00000080 -#define UART_IMSC_FEIM_BITN 7 -#define UART_IMSC_FEIM_M 0x00000080 -#define UART_IMSC_FEIM_S 7 - -// Field: [6] RTIM -// -// Receive timeout interrupt mask. A read returns the current mask for UART's -// receive timeout interrupt. On a write of 1, the mask of the overrun error -// interrupt is set which means the interrupt state will be reflected in -// MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not -// reflect the interrupt. -// The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the -// mask is set (RTIM = 1). This is because the mask acts as an enable for power -// saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. -#define UART_IMSC_RTIM 0x00000040 -#define UART_IMSC_RTIM_BITN 6 -#define UART_IMSC_RTIM_M 0x00000040 -#define UART_IMSC_RTIM_S 6 - -// Field: [5] TXIM -// -// Transmit interrupt mask. A read returns the current mask for UART's transmit -// interrupt. On a write of 1, the mask of the overrun error interrupt is set -// which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 -// clears the mask which means MIS.TXMIS will not reflect the interrupt. -#define UART_IMSC_TXIM 0x00000020 -#define UART_IMSC_TXIM_BITN 5 -#define UART_IMSC_TXIM_M 0x00000020 -#define UART_IMSC_TXIM_S 5 - -// Field: [4] RXIM -// -// Receive interrupt mask. A read returns the current mask for UART's receive -// interrupt. On a write of 1, the mask of the overrun error interrupt is set -// which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 -// clears the mask which means MIS.RXMIS will not reflect the interrupt. -#define UART_IMSC_RXIM 0x00000010 -#define UART_IMSC_RXIM_BITN 4 -#define UART_IMSC_RXIM_M 0x00000010 -#define UART_IMSC_RXIM_S 4 - -// Field: [1] CTSMIM -// -// Clear to Send (CTS) modem interrupt mask. A read returns the current mask -// for UART's clear to send interrupt. On a write of 1, the mask of the overrun -// error interrupt is set which means the interrupt state will be reflected in -// MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not -// reflect the interrupt. -#define UART_IMSC_CTSMIM 0x00000002 -#define UART_IMSC_CTSMIM_BITN 1 -#define UART_IMSC_CTSMIM_M 0x00000002 -#define UART_IMSC_CTSMIM_S 1 - -//***************************************************************************** -// -// Register: UART_O_RIS -// -//***************************************************************************** -// Field: [10] OERIS -// -// Overrun error interrupt status: -// This field returns the raw interrupt state of UART's overrun error -// interrupt. Overrun error occurs if data is received and the receive FIFO is -// full. -#define UART_RIS_OERIS 0x00000400 -#define UART_RIS_OERIS_BITN 10 -#define UART_RIS_OERIS_M 0x00000400 -#define UART_RIS_OERIS_S 10 - -// Field: [9] BERIS -// -// Break error interrupt status: -// This field returns the raw interrupt state of UART's break error interrupt. -// Break error is set when a break condition is detected, indicating that the -// received data input (UARTRXD input pin) was held LOW for longer than a -// full-word transmission time (defined as start, data, parity and stop bits). -#define UART_RIS_BERIS 0x00000200 -#define UART_RIS_BERIS_BITN 9 -#define UART_RIS_BERIS_M 0x00000200 -#define UART_RIS_BERIS_S 9 - -// Field: [8] PERIS -// -// Parity error interrupt status: -// This field returns the raw interrupt state of UART's parity error interrupt. -// Parity error is set if the parity of the received data character does not -// match the parity that the LCRH.EPS and LCRH.SPS select. -#define UART_RIS_PERIS 0x00000100 -#define UART_RIS_PERIS_BITN 8 -#define UART_RIS_PERIS_M 0x00000100 -#define UART_RIS_PERIS_S 8 - -// Field: [7] FERIS -// -// Framing error interrupt status: -// This field returns the raw interrupt state of UART's framing error -// interrupt. Framing error is set if the received character does not have a -// valid stop bit (a valid stop bit is 1). -#define UART_RIS_FERIS 0x00000080 -#define UART_RIS_FERIS_BITN 7 -#define UART_RIS_FERIS_M 0x00000080 -#define UART_RIS_FERIS_S 7 - -// Field: [6] RTRIS -// -// Receive timeout interrupt status: -// This field returns the raw interrupt state of UART's receive timeout -// interrupt. The receive timeout interrupt is asserted when the receive FIFO -// is not empty, and no more data is received during a 32-bit period. The -// receive timeout interrupt is cleared either when the FIFO becomes empty -// through reading all the data, or when a 1 is written to ICR.RTIC. -// The raw interrupt for receive timeout cannot be set unless the mask is set -// (IMSC.RTIM = 1). This is because the mask acts as an enable for power -// saving. That is, the same status can be read from MIS.RTMIS and RTRIS. -#define UART_RIS_RTRIS 0x00000040 -#define UART_RIS_RTRIS_BITN 6 -#define UART_RIS_RTRIS_M 0x00000040 -#define UART_RIS_RTRIS_S 6 - -// Field: [5] TXRIS -// -// Transmit interrupt status: -// This field returns the raw interrupt state of UART's transmit interrupt. -// When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if -// the number of bytes in transmit FIFO is equal to or lower than the -// programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by -// writing data to the transmit FIFO until it becomes greater than the trigger -// level, or by clearing the interrupt through ICR.TXIC. -// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one -// location, the transmit interrupt is asserted if there is no data present in -// the transmitters single location. It is cleared by performing a single write -// to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. -#define UART_RIS_TXRIS 0x00000020 -#define UART_RIS_TXRIS_BITN 5 -#define UART_RIS_TXRIS_M 0x00000020 -#define UART_RIS_TXRIS_S 5 - -// Field: [4] RXRIS -// -// Receive interrupt status: -// This field returns the raw interrupt state of UART's receive interrupt. -// When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if -// the receive FIFO reaches the programmed trigger -// level (IFLS.RXSEL). The receive interrupt is cleared by reading data from -// the receive FIFO until it becomes less than the trigger level, or by -// clearing the interrupt through ICR.RXIC. -// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one -// location, the receive interrupt is asserted if data is received -// thereby filling the location. The receive interrupt is cleared by performing -// a single read of the receive FIFO, or by clearing the interrupt through -// ICR.RXIC. -#define UART_RIS_RXRIS 0x00000010 -#define UART_RIS_RXRIS_BITN 4 -#define UART_RIS_RXRIS_M 0x00000010 -#define UART_RIS_RXRIS_S 4 - -// Field: [1] CTSRMIS -// -// Clear to Send (CTS) modem interrupt status: -// This field returns the raw interrupt state of UART's clear to send -// interrupt. -#define UART_RIS_CTSRMIS 0x00000002 -#define UART_RIS_CTSRMIS_BITN 1 -#define UART_RIS_CTSRMIS_M 0x00000002 -#define UART_RIS_CTSRMIS_S 1 - -//***************************************************************************** -// -// Register: UART_O_MIS -// -//***************************************************************************** -// Field: [10] OEMIS -// -// Overrun error masked interrupt status: -// This field returns the masked interrupt state of the overrun interrupt which -// is the AND product of raw interrupt state RIS.OERIS and the mask setting -// IMSC.OEIM. -#define UART_MIS_OEMIS 0x00000400 -#define UART_MIS_OEMIS_BITN 10 -#define UART_MIS_OEMIS_M 0x00000400 -#define UART_MIS_OEMIS_S 10 - -// Field: [9] BEMIS -// -// Break error masked interrupt status: -// This field returns the masked interrupt state of the break error interrupt -// which is the AND product of raw interrupt state RIS.BERIS and the mask -// setting IMSC.BEIM. -#define UART_MIS_BEMIS 0x00000200 -#define UART_MIS_BEMIS_BITN 9 -#define UART_MIS_BEMIS_M 0x00000200 -#define UART_MIS_BEMIS_S 9 - -// Field: [8] PEMIS -// -// Parity error masked interrupt status: -// This field returns the masked interrupt state of the parity error interrupt -// which is the AND product of raw interrupt state RIS.PERIS and the mask -// setting IMSC.PEIM. -#define UART_MIS_PEMIS 0x00000100 -#define UART_MIS_PEMIS_BITN 8 -#define UART_MIS_PEMIS_M 0x00000100 -#define UART_MIS_PEMIS_S 8 - -// Field: [7] FEMIS -// -// Framing error masked interrupt status: Returns the masked interrupt state of -// the framing error interrupt which is the AND product of raw interrupt state -// RIS.FERIS and the mask setting IMSC.FEIM. -#define UART_MIS_FEMIS 0x00000080 -#define UART_MIS_FEMIS_BITN 7 -#define UART_MIS_FEMIS_M 0x00000080 -#define UART_MIS_FEMIS_S 7 - -// Field: [6] RTMIS -// -// Receive timeout masked interrupt status: -// Returns the masked interrupt state of the receive timeout interrupt. -// The raw interrupt for receive timeout cannot be set unless the mask is set -// (IMSC.RTIM = 1). This is because the mask acts as an enable for power -// saving. That is, the same status can be read from RTMIS and RIS.RTRIS. -#define UART_MIS_RTMIS 0x00000040 -#define UART_MIS_RTMIS_BITN 6 -#define UART_MIS_RTMIS_M 0x00000040 -#define UART_MIS_RTMIS_S 6 - -// Field: [5] TXMIS -// -// Transmit masked interrupt status: -// This field returns the masked interrupt state of the transmit interrupt -// which is the AND product of raw interrupt state RIS.TXRIS and the mask -// setting IMSC.TXIM. -#define UART_MIS_TXMIS 0x00000020 -#define UART_MIS_TXMIS_BITN 5 -#define UART_MIS_TXMIS_M 0x00000020 -#define UART_MIS_TXMIS_S 5 - -// Field: [4] RXMIS -// -// Receive masked interrupt status: -// This field returns the masked interrupt state of the receive interrupt -// which is the AND product of raw interrupt state RIS.RXRIS and the mask -// setting IMSC.RXIM. -#define UART_MIS_RXMIS 0x00000010 -#define UART_MIS_RXMIS_BITN 4 -#define UART_MIS_RXMIS_M 0x00000010 -#define UART_MIS_RXMIS_S 4 - -// Field: [1] CTSMMIS -// -// Clear to Send (CTS) modem masked interrupt status: -// This field returns the masked interrupt state of the clear to send interrupt -// which is the AND product of raw interrupt state RIS.CTSRMIS and the mask -// setting IMSC.CTSMIM. -#define UART_MIS_CTSMMIS 0x00000002 -#define UART_MIS_CTSMMIS_BITN 1 -#define UART_MIS_CTSMMIS_M 0x00000002 -#define UART_MIS_CTSMMIS_S 1 - -//***************************************************************************** -// -// Register: UART_O_ICR -// -//***************************************************************************** -// Field: [10] OEIC -// -// Overrun error interrupt clear: -// Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). -// Writing 0 has no effect. -#define UART_ICR_OEIC 0x00000400 -#define UART_ICR_OEIC_BITN 10 -#define UART_ICR_OEIC_M 0x00000400 -#define UART_ICR_OEIC_S 10 - -// Field: [9] BEIC -// -// Break error interrupt clear: -// Writing 1 to this field clears the break error interrupt (RIS.BERIS). -// Writing 0 has no effect. -#define UART_ICR_BEIC 0x00000200 -#define UART_ICR_BEIC_BITN 9 -#define UART_ICR_BEIC_M 0x00000200 -#define UART_ICR_BEIC_S 9 - -// Field: [8] PEIC -// -// Parity error interrupt clear: -// Writing 1 to this field clears the parity error interrupt (RIS.PERIS). -// Writing 0 has no effect. -#define UART_ICR_PEIC 0x00000100 -#define UART_ICR_PEIC_BITN 8 -#define UART_ICR_PEIC_M 0x00000100 -#define UART_ICR_PEIC_S 8 - -// Field: [7] FEIC -// -// Framing error interrupt clear: -// Writing 1 to this field clears the framing error interrupt (RIS.FERIS). -// Writing 0 has no effect. -#define UART_ICR_FEIC 0x00000080 -#define UART_ICR_FEIC_BITN 7 -#define UART_ICR_FEIC_M 0x00000080 -#define UART_ICR_FEIC_S 7 - -// Field: [6] RTIC -// -// Receive timeout interrupt clear: -// Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). -// Writing 0 has no effect. -#define UART_ICR_RTIC 0x00000040 -#define UART_ICR_RTIC_BITN 6 -#define UART_ICR_RTIC_M 0x00000040 -#define UART_ICR_RTIC_S 6 - -// Field: [5] TXIC -// -// Transmit interrupt clear: -// Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 -// has no effect. -#define UART_ICR_TXIC 0x00000020 -#define UART_ICR_TXIC_BITN 5 -#define UART_ICR_TXIC_M 0x00000020 -#define UART_ICR_TXIC_S 5 - -// Field: [4] RXIC -// -// Receive interrupt clear: -// Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 -// has no effect. -#define UART_ICR_RXIC 0x00000010 -#define UART_ICR_RXIC_BITN 4 -#define UART_ICR_RXIC_M 0x00000010 -#define UART_ICR_RXIC_S 4 - -// Field: [1] CTSMIC -// -// Clear to Send (CTS) modem interrupt clear: -// Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). -// Writing 0 has no effect. -#define UART_ICR_CTSMIC 0x00000002 -#define UART_ICR_CTSMIC_BITN 1 -#define UART_ICR_CTSMIC_M 0x00000002 -#define UART_ICR_CTSMIC_S 1 - -//***************************************************************************** -// -// Register: UART_O_DMACTL -// -//***************************************************************************** -// Field: [2] DMAONERR -// -// DMA on error. If this bit is set to 1, the DMA receive request outputs (for -// single and burst requests) are disabled when the UART error interrupt is -// asserted (more specifically if any of the error interrupts RIS.PERIS, -// RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). -#define UART_DMACTL_DMAONERR 0x00000004 -#define UART_DMACTL_DMAONERR_BITN 2 -#define UART_DMACTL_DMAONERR_M 0x00000004 -#define UART_DMACTL_DMAONERR_S 2 - -// Field: [1] TXDMAE -// -// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is -// enabled. -#define UART_DMACTL_TXDMAE 0x00000002 -#define UART_DMACTL_TXDMAE_BITN 1 -#define UART_DMACTL_TXDMAE_M 0x00000002 -#define UART_DMACTL_TXDMAE_S 1 - -// Field: [0] RXDMAE -// -// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is -// enabled. -#define UART_DMACTL_RXDMAE 0x00000001 -#define UART_DMACTL_RXDMAE_BITN 0 -#define UART_DMACTL_RXDMAE_M 0x00000001 -#define UART_DMACTL_RXDMAE_S 0 - - -#endif // __UART__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_udma.h b/third_party/ti/devices/cc26x0/inc/hw_udma.h deleted file mode 100644 index 747382c5e..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_udma.h +++ /dev/null @@ -1,575 +0,0 @@ -/****************************************************************************** -* Filename: hw_udma_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_UDMA_H__ -#define __HW_UDMA_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// UDMA component -// -//***************************************************************************** -// Status -#define UDMA_O_STATUS 0x00000000 - -// Configuration -#define UDMA_O_CFG 0x00000004 - -// Channel Control Data Base Pointer -#define UDMA_O_CTRL 0x00000008 - -// Channel Alternate Control Data Base Pointer -#define UDMA_O_ALTCTRL 0x0000000C - -// Channel Wait On Request Status -#define UDMA_O_WAITONREQ 0x00000010 - -// Channel Software Request -#define UDMA_O_SOFTREQ 0x00000014 - -// Channel Set UseBurst -#define UDMA_O_SETBURST 0x00000018 - -// Channel Clear UseBurst -#define UDMA_O_CLEARBURST 0x0000001C - -// Channel Set Request Mask -#define UDMA_O_SETREQMASK 0x00000020 - -// Clear Channel Request Mask -#define UDMA_O_CLEARREQMASK 0x00000024 - -// Set Channel Enable -#define UDMA_O_SETCHANNELEN 0x00000028 - -// Clear Channel Enable -#define UDMA_O_CLEARCHANNELEN 0x0000002C - -// Channel Set Primary-Alternate -#define UDMA_O_SETCHNLPRIALT 0x00000030 - -// Channel Clear Primary-Alternate -#define UDMA_O_CLEARCHNLPRIALT 0x00000034 - -// Set Channel Priority -#define UDMA_O_SETCHNLPRIORITY 0x00000038 - -// Clear Channel Priority -#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C - -// Error Status and Clear -#define UDMA_O_ERROR 0x0000004C - -// Channel Request Done -#define UDMA_O_REQDONE 0x00000504 - -// Channel Request Done Mask -#define UDMA_O_DONEMASK 0x00000520 - -//***************************************************************************** -// -// Register: UDMA_O_STATUS -// -//***************************************************************************** -// Field: [31:28] TEST -// -// -// 0x0: Controller does not include the integration test logic -// 0x1: Controller includes the integration test logic -// 0x2: Undefined -// ... -// 0xF: Undefined -#define UDMA_STATUS_TEST_W 4 -#define UDMA_STATUS_TEST_M 0xF0000000 -#define UDMA_STATUS_TEST_S 28 - -// Field: [20:16] TOTALCHANNELS -// -// Register value returns number of available uDMA channels minus one. For -// example a read out value of: -// -// 0x00: Show that the controller is configured to use 1 uDMA channel -// 0x01: Shows that the controller is configured to use 2 uDMA channels -// ... -// 0x1F: Shows that the controller is configured to use 32 uDMA channels -// (32-1=31=0x1F) -#define UDMA_STATUS_TOTALCHANNELS_W 5 -#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 -#define UDMA_STATUS_TOTALCHANNELS_S 16 - -// Field: [7:4] STATE -// -// Current state of the control state machine. State can be one of the -// following: -// -// 0x0: Idle -// 0x1: Reading channel controller data -// 0x2: Reading source data end pointer -// 0x3: Reading destination data end pointer -// 0x4: Reading source data -// 0x5: Writing destination data -// 0x6: Waiting for uDMA request to clear -// 0x7: Writing channel controller data -// 0x8: Stalled -// 0x9: Done -// 0xA: Peripheral scatter-gather transition -// 0xB: Undefined -// ... -// 0xF: Undefined. -#define UDMA_STATUS_STATE_W 4 -#define UDMA_STATUS_STATE_M 0x000000F0 -#define UDMA_STATUS_STATE_S 4 - -// Field: [0] MASTERENABLE -// -// Shows the enable status of the controller as configured by CFG.MASTERENABLE: -// -// 0: Controller is disabled -// 1: Controller is enabled -#define UDMA_STATUS_MASTERENABLE 0x00000001 -#define UDMA_STATUS_MASTERENABLE_BITN 0 -#define UDMA_STATUS_MASTERENABLE_M 0x00000001 -#define UDMA_STATUS_MASTERENABLE_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CFG -// -//***************************************************************************** -// Field: [7:5] PRTOCTRL -// -// Sets the AHB-Lite bus protocol protection state by controlling the AHB -// signal HProt[3:1] as follows: -// -// Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. -// Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. -// Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. -// -// When bit [n] = 1 then the corresponding HProt bit is high. -// When bit [n] = 0 then the corresponding HProt bit is low. -// -// This field controls HProt[3:1] signal for all transactions initiated by uDMA -// except two transactions below: -// - the read from the address indicated by source address pointer -// - the write to the address indicated by destination address pointer -// HProt[3:1] for these two exceptions can be controlled by dedicated fields in -// the channel configutation descriptor. -#define UDMA_CFG_PRTOCTRL_W 3 -#define UDMA_CFG_PRTOCTRL_M 0x000000E0 -#define UDMA_CFG_PRTOCTRL_S 5 - -// Field: [0] MASTERENABLE -// -// Enables the controller: -// -// 0: Disables the controller -// 1: Enables the controller -#define UDMA_CFG_MASTERENABLE 0x00000001 -#define UDMA_CFG_MASTERENABLE_BITN 0 -#define UDMA_CFG_MASTERENABLE_M 0x00000001 -#define UDMA_CFG_MASTERENABLE_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CTRL -// -//***************************************************************************** -// Field: [31:10] BASEPTR -// -// This register point to the base address for the primary data structures of -// each DMA channel. This is not stored in module, but in system memory, thus -// space must be allocated for this usage when DMA is in usage -#define UDMA_CTRL_BASEPTR_W 22 -#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 -#define UDMA_CTRL_BASEPTR_S 10 - -//***************************************************************************** -// -// Register: UDMA_O_ALTCTRL -// -//***************************************************************************** -// Field: [31:0] BASEPTR -// -// This register shows the base address for the alternate data structures and -// is calculated by module, thus read only -#define UDMA_ALTCTRL_BASEPTR_W 32 -#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF -#define UDMA_ALTCTRL_BASEPTR_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_WAITONREQ -// -//***************************************************************************** -// Field: [31:0] CHNLSTATUS -// -// Channel wait on request status: -// -// Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, -// this channel may come out of active state even if request is still present. -// Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it -// keeps channel Ch in active state until the requests are deasserted. This -// handshake is necessary for channels where the requester is in an -// asynchronous domain or can run at slower clock speed than uDMA -#define UDMA_WAITONREQ_CHNLSTATUS_W 32 -#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF -#define UDMA_WAITONREQ_CHNLSTATUS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SOFTREQ -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Set the appropriate bit to generate a software uDMA request on the -// corresponding uDMA channel -// -// Bit [Ch] = 0: Does not create a uDMA request for channel Ch -// Bit [Ch] = 1: Creates a uDMA request for channel Ch -// -// Writing to a bit where a uDMA channel is not implemented does not create a -// uDMA request for that channel -#define UDMA_SOFTREQ_CHNLS_W 32 -#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF -#define UDMA_SOFTREQ_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SETBURST -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Returns the useburst status, or disables individual channels from generating -// single uDMA requests. The value R is the arbitration rate and stored in the -// controller data structure. -// -// Read as: -// -// Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on -// channel C. The controller performs 2^R, or single, bus transfers. -// -// Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. -// The controller only responds to burst transfer requests and performs 2^R -// transfers. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. -// Bit [Ch] = 1: Disables single transfer requests on channel Ch. The -// controller performs 2^R transfers for burst requests. -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETBURST_CHNLS_W 32 -#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF -#define UDMA_SETBURST_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CLEARBURST -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Set the appropriate bit to enable single transfer requests. -// -// Write as: -// -// Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer -// requests. -// -// Bit [Ch] = 1: Enables single transfer requests on channel Ch. -// -// Writing to a bit where a DMA channel is not implemented has no effect. -#define UDMA_CLEARBURST_CHNLS_W 32 -#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARBURST_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SETREQMASK -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Returns the burst and single request mask status, or disables the -// corresponding channel from generating uDMA requests. -// -// Read as: -// Bit [Ch] = 0: External requests are enabled for channel Ch. -// Bit [Ch] = 1: External requests are disabled for channel Ch. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. -// Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single -// request channel [C] input from generating uDMA requests. -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETREQMASK_CHNLS_W 32 -#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_SETREQMASK_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CLEARREQMASK -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Set the appropriate bit to enable DMA request for the channel. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from -// generating requests. -// Bit [Ch] = 1: Enables channel [C] to generate DMA requests. -// -// Writing to a bit where a DMA channel is not implemented has no effect. -#define UDMA_CLEARREQMASK_CHNLS_W 32 -#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARREQMASK_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SETCHANNELEN -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Returns the enable status of the channels, or enables the corresponding -// channels. -// -// Read as: -// Bit [Ch] = 0: Channel Ch is disabled. -// Bit [Ch] = 1: Channel Ch is enabled. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel -// Bit [Ch] = 1: Enables channel Ch -// -// Writing to a bit where a DMA channel is not implemented has no effect -#define UDMA_SETCHANNELEN_CHNLS_W 32 -#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHANNELEN_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CLEARCHANNELEN -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Set the appropriate bit to disable the corresponding uDMA channel. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. -// Bit [Ch] = 1: Disables channel Ch -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHANNELEN_CHNLS_W 32 -#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHANNELEN_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SETCHNLPRIALT -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Returns the channel control data structure status, or selects the alternate -// data structure for the corresponding uDMA channel. -// -// Read as: -// Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. -// Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel -// Bit [Ch] = 1: Selects the alternate data structure for channel Ch -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETCHNLPRIALT_CHNLS_W 32 -#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHNLPRIALT_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CLEARCHNLPRIALT -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Clears the appropriate bit to select the primary data structure for the -// corresponding uDMA channel. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate -// data structure. -// Bit [Ch] = 1: Selects the primary data structure for channel Ch. -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 -#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SETCHNLPRIORITY -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Returns the channel priority mask status, or sets the channel priority to -// high. -// -// Read as: -// Bit [Ch] = 0: uDMA channel Ch is using the default priority level. -// Bit [Ch] = 1: uDMA channel Ch is using a high priority level. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch -// to the default priority level. -// Bit [Ch] = 1: Channel Ch uses the high priority level. -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 -#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CLEARCHNLPRIORITY -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Clear the appropriate bit to select the default priority level for the -// specified uDMA channel. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to -// the high priority level. -// Bit [Ch] = 1: Channel Ch uses the default priority level. -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 -#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_ERROR -// -//***************************************************************************** -// Field: [0] STATUS -// -// Returns the status of bus error flag in uDMA, or clears this bit -// -// Read as: -// -// 0: No bus error detected -// 1: Bus error detected -// -// Write as: -// -// 0: No effect, status of bus error flag is unchanged. -// 1: Clears the bus error flag. -#define UDMA_ERROR_STATUS 0x00000001 -#define UDMA_ERROR_STATUS_BITN 0 -#define UDMA_ERROR_STATUS_M 0x00000001 -#define UDMA_ERROR_STATUS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_REQDONE -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Reflects the uDMA done status for the given channel, channel [Ch]. It's a -// sticky done bit. Unless cleared by writing a 1, it holds the value of 1. -// -// Read as: -// Bit [Ch] = 0: Request has not completed for channel Ch -// Bit [Ch] = 1: Request has completed for the channel Ch -// -// Writing a 1 to individual bits would clear the corresponding bit. -// -// Write as: -// Bit [Ch] = 0: No effect. -// Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 -#define UDMA_REQDONE_CHNLS_W 32 -#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF -#define UDMA_REQDONE_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_DONEMASK -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Controls the propagation of the uDMA done and active state to the assigned -// peripheral. Specifically used for software channels. -// -// Read as: -// Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from -// reaching to the peripherals. -// Note that the uDMA done state for channel [Ch] is blocked from contributing -// to generation of combined uDMA done signal -// -// Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from -// reaching to the peripherals. -// Note that the uDMA done state for channel [Ch] is not blocked from -// contributing to generation of combined uDMA done signal -// -// Write as: -// Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the -// peripherals. -// Note that this disables uDMA done state for channel [Ch] from contributing -// to generation of combined uDMA done signal -// -// Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the -// peripherals. -// Note that this enables uDMA done for channel [Ch] to contribute to -// generation of combined uDMA done signal. -#define UDMA_DONEMASK_CHNLS_W 32 -#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_DONEMASK_CHNLS_S 0 - - -#endif // __UDMA__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_vims.h b/third_party/ti/devices/cc26x0/inc/hw_vims.h deleted file mode 100644 index f750d4883..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_vims.h +++ /dev/null @@ -1,206 +0,0 @@ -/****************************************************************************** -* Filename: hw_vims_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_VIMS_H__ -#define __HW_VIMS_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// VIMS component -// -//***************************************************************************** -// Status -#define VIMS_O_STAT 0x00000000 - -// Control -#define VIMS_O_CTL 0x00000004 - -//***************************************************************************** -// -// Register: VIMS_O_STAT -// -//***************************************************************************** -// Field: [5] IDCODE_LB_DIS -// -// Icode/Dcode flash line buffer status -// -// 0: Enabled or in transition to disabled -// 1: Disabled and flushed -#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 -#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 -#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 -#define VIMS_STAT_IDCODE_LB_DIS_S 5 - -// Field: [4] SYSBUS_LB_DIS -// -// Sysbus flash line buffer control -// -// 0: Enabled or in transition to disabled -// 1: Disabled and flushed -#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 -#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 -#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 -#define VIMS_STAT_SYSBUS_LB_DIS_S 4 - -// Field: [3] MODE_CHANGING -// -// VIMS mode change status -// -// 0: VIMS is in the mode defined by MODE -// 1: VIMS is in the process of changing to the mode given in CTL.MODE -#define VIMS_STAT_MODE_CHANGING 0x00000008 -#define VIMS_STAT_MODE_CHANGING_BITN 3 -#define VIMS_STAT_MODE_CHANGING_M 0x00000008 -#define VIMS_STAT_MODE_CHANGING_S 3 - -// Field: [2] INV -// -// This bit is set when invalidation of the cache memory is active / ongoing -#define VIMS_STAT_INV 0x00000004 -#define VIMS_STAT_INV_BITN 2 -#define VIMS_STAT_INV_M 0x00000004 -#define VIMS_STAT_INV_S 2 - -// Field: [1:0] MODE -// -// Current VIMS mode -// ENUMs: -// OFF VIMS Off mode -// CACHE VIMS Cache mode -// GPRAM VIMS GPRAM mode -#define VIMS_STAT_MODE_W 2 -#define VIMS_STAT_MODE_M 0x00000003 -#define VIMS_STAT_MODE_S 0 -#define VIMS_STAT_MODE_OFF 0x00000003 -#define VIMS_STAT_MODE_CACHE 0x00000001 -#define VIMS_STAT_MODE_GPRAM 0x00000000 - -//***************************************************************************** -// -// Register: VIMS_O_CTL -// -//***************************************************************************** -// Field: [31] STATS_CLR -// -// Set this bit to clear statistic counters. -#define VIMS_CTL_STATS_CLR 0x80000000 -#define VIMS_CTL_STATS_CLR_BITN 31 -#define VIMS_CTL_STATS_CLR_M 0x80000000 -#define VIMS_CTL_STATS_CLR_S 31 - -// Field: [30] STATS_EN -// -// Set this bit to enable statistic counters. -#define VIMS_CTL_STATS_EN 0x40000000 -#define VIMS_CTL_STATS_EN_BITN 30 -#define VIMS_CTL_STATS_EN_M 0x40000000 -#define VIMS_CTL_STATS_EN_S 30 - -// Field: [29] DYN_CG_EN -// -// 0: The in-built clock gate functionality is bypassed. -// 1: The in-built clock gate functionality is enabled, automatically gating -// the clock when not needed. -#define VIMS_CTL_DYN_CG_EN 0x20000000 -#define VIMS_CTL_DYN_CG_EN_BITN 29 -#define VIMS_CTL_DYN_CG_EN_M 0x20000000 -#define VIMS_CTL_DYN_CG_EN_S 29 - -// Field: [5] IDCODE_LB_DIS -// -// Icode/Dcode flash line buffer control -// -// 0: Enable -// 1: Disable -#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 -#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 -#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 -#define VIMS_CTL_IDCODE_LB_DIS_S 5 - -// Field: [4] SYSBUS_LB_DIS -// -// Sysbus flash line buffer control -// -// 0: Enable -// 1: Disable -#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 -#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 -#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 -#define VIMS_CTL_SYSBUS_LB_DIS_S 4 - -// Field: [3] ARB_CFG -// -// Icode/Dcode and sysbus arbitation scheme -// -// 0: Static arbitration (icode/docde > sysbus) -// 1: Round-robin arbitration -#define VIMS_CTL_ARB_CFG 0x00000008 -#define VIMS_CTL_ARB_CFG_BITN 3 -#define VIMS_CTL_ARB_CFG_M 0x00000008 -#define VIMS_CTL_ARB_CFG_S 3 - -// Field: [2] PREF_EN -// -// Tag prefetch control -// -// 0: Disabled -// 1: Enabled -#define VIMS_CTL_PREF_EN 0x00000004 -#define VIMS_CTL_PREF_EN_BITN 2 -#define VIMS_CTL_PREF_EN_M 0x00000004 -#define VIMS_CTL_PREF_EN_S 2 - -// Field: [1:0] MODE -// -// VIMS mode request. -// Write accesses to this field will be blocked while STAT.MODE_CHANGING is set -// to 1. -// Note: Transaction from CACHE mode to GPRAM mode should be done through OFF -// mode to minimize flash block delay. -// ENUMs: -// OFF VIMS Off mode -// CACHE VIMS Cache mode -// GPRAM VIMS GPRAM mode -#define VIMS_CTL_MODE_W 2 -#define VIMS_CTL_MODE_M 0x00000003 -#define VIMS_CTL_MODE_S 0 -#define VIMS_CTL_MODE_OFF 0x00000003 -#define VIMS_CTL_MODE_CACHE 0x00000001 -#define VIMS_CTL_MODE_GPRAM 0x00000000 - - -#endif // __VIMS__ diff --git a/third_party/ti/devices/cc26x0/inc/hw_wdt.h b/third_party/ti/devices/cc26x0/inc/hw_wdt.h deleted file mode 100644 index 11e7ca2e2..000000000 --- a/third_party/ti/devices/cc26x0/inc/hw_wdt.h +++ /dev/null @@ -1,290 +0,0 @@ -/****************************************************************************** -* Filename: hw_wdt_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_WDT_H__ -#define __HW_WDT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// WDT component -// -//***************************************************************************** -// Configuration -#define WDT_O_LOAD 0x00000000 - -// Current Count Value -#define WDT_O_VALUE 0x00000004 - -// Control -#define WDT_O_CTL 0x00000008 - -// Interrupt Clear -#define WDT_O_ICR 0x0000000C - -// Raw Interrupt Status -#define WDT_O_RIS 0x00000010 - -// Masked Interrupt Status -#define WDT_O_MIS 0x00000014 - -// Test Mode -#define WDT_O_TEST 0x00000418 - -// Interrupt Cause Test Mode -#define WDT_O_INT_CAUS 0x0000041C - -// Lock -#define WDT_O_LOCK 0x00000C00 - -//***************************************************************************** -// -// Register: WDT_O_LOAD -// -//***************************************************************************** -// Field: [31:0] WDTLOAD -// -// This register is the 32-bit interval value used by the 32-bit counter. When -// this register is written, the value is immediately loaded and the counter is -// restarted to count down from the new value. If this register is loaded with -// 0x0000.0000, an interrupt is immediately generated. -#define WDT_LOAD_WDTLOAD_W 32 -#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF -#define WDT_LOAD_WDTLOAD_S 0 - -//***************************************************************************** -// -// Register: WDT_O_VALUE -// -//***************************************************************************** -// Field: [31:0] WDTVALUE -// -// This register contains the current count value of the timer. -#define WDT_VALUE_WDTVALUE_W 32 -#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF -#define WDT_VALUE_WDTVALUE_S 0 - -//***************************************************************************** -// -// Register: WDT_O_CTL -// -//***************************************************************************** -// Field: [2] INTTYPE -// -// WDT Interrupt Type -// -// 0: WDT interrupt is a standard interrupt. -// 1: WDT interrupt is a non-maskable interrupt. -// ENUMs: -// NONMASKABLE Non-maskable interrupt -// MASKABLE Maskable interrupt -#define WDT_CTL_INTTYPE 0x00000004 -#define WDT_CTL_INTTYPE_BITN 2 -#define WDT_CTL_INTTYPE_M 0x00000004 -#define WDT_CTL_INTTYPE_S 2 -#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 -#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 - -// Field: [1] RESEN -// -// WDT Reset Enable. Defines the function of the WDT reset source (see -// PRCM:WARMRESET.WDT_STAT if enabled) -// -// 0: Disabled. -// 1: Enable the Watchdog reset output. -// ENUMs: -// EN Reset output Enabled -// DIS Reset output Disabled -#define WDT_CTL_RESEN 0x00000002 -#define WDT_CTL_RESEN_BITN 1 -#define WDT_CTL_RESEN_M 0x00000002 -#define WDT_CTL_RESEN_S 1 -#define WDT_CTL_RESEN_EN 0x00000002 -#define WDT_CTL_RESEN_DIS 0x00000000 - -// Field: [0] INTEN -// -// WDT Interrupt Enable -// -// 0: Interrupt event disabled. -// 1: Interrupt event enabled. Once set, this bit can only be cleared by a -// hardware reset. -// ENUMs: -// EN Interrupt Enabled -// DIS Interrupt Disabled -#define WDT_CTL_INTEN 0x00000001 -#define WDT_CTL_INTEN_BITN 0 -#define WDT_CTL_INTEN_M 0x00000001 -#define WDT_CTL_INTEN_S 0 -#define WDT_CTL_INTEN_EN 0x00000001 -#define WDT_CTL_INTEN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: WDT_O_ICR -// -//***************************************************************************** -// Field: [31:0] WDTICR -// -// This register is the interrupt clear register. A write of any value to this -// register clears the WDT interrupt and reloads the 32-bit counter from the -// LOAD register. -#define WDT_ICR_WDTICR_W 32 -#define WDT_ICR_WDTICR_M 0xFFFFFFFF -#define WDT_ICR_WDTICR_S 0 - -//***************************************************************************** -// -// Register: WDT_O_RIS -// -//***************************************************************************** -// Field: [0] WDTRIS -// -// This register is the raw interrupt status register. WDT interrupt events can -// be monitored via this register if the controller interrupt is masked. -// -// Value Description -// -// 0: The WDT has not timed out -// 1: A WDT time-out event has occurred -// -#define WDT_RIS_WDTRIS 0x00000001 -#define WDT_RIS_WDTRIS_BITN 0 -#define WDT_RIS_WDTRIS_M 0x00000001 -#define WDT_RIS_WDTRIS_S 0 - -//***************************************************************************** -// -// Register: WDT_O_MIS -// -//***************************************************************************** -// Field: [0] WDTMIS -// -// This register is the masked interrupt status register. The value of this -// register is the logical AND of the raw interrupt bit and the WDT interrupt -// enable bit CTL.INTEN. -// -// Value Description -// -// 0: The WDT has not timed out or is masked. -// 1: An unmasked WDT time-out event has occurred. -#define WDT_MIS_WDTMIS 0x00000001 -#define WDT_MIS_WDTMIS_BITN 0 -#define WDT_MIS_WDTMIS_M 0x00000001 -#define WDT_MIS_WDTMIS_S 0 - -//***************************************************************************** -// -// Register: WDT_O_TEST -// -//***************************************************************************** -// Field: [8] STALL -// -// WDT Stall Enable -// -// 0: The WDT timer continues counting if the CPU is stopped with a debugger. -// 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the -// CPU is restarted, the WDT resumes counting. -// ENUMs: -// EN Enable STALL -// DIS Disable STALL -#define WDT_TEST_STALL 0x00000100 -#define WDT_TEST_STALL_BITN 8 -#define WDT_TEST_STALL_M 0x00000100 -#define WDT_TEST_STALL_S 8 -#define WDT_TEST_STALL_EN 0x00000100 -#define WDT_TEST_STALL_DIS 0x00000000 - -// Field: [0] TEST_EN -// -// The test enable bit -// -// 0: Enable external reset -// 1: Disables the generation of an external reset. Instead bit 1 of the -// INT_CAUS register is set and an interrupt is generated -// ENUMs: -// EN Test mode Enabled -// DIS Test mode Disabled -#define WDT_TEST_TEST_EN 0x00000001 -#define WDT_TEST_TEST_EN_BITN 0 -#define WDT_TEST_TEST_EN_M 0x00000001 -#define WDT_TEST_TEST_EN_S 0 -#define WDT_TEST_TEST_EN_EN 0x00000001 -#define WDT_TEST_TEST_EN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: WDT_O_INT_CAUS -// -//***************************************************************************** -// Field: [1] CAUSE_RESET -// -// Indicates that the cause of an interrupt was a reset generated but blocked -// due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). -#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 -#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 -#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 -#define WDT_INT_CAUS_CAUSE_RESET_S 1 - -// Field: [0] CAUSE_INTR -// -// Replica of RIS.WDTRIS -#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 -#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 -#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 -#define WDT_INT_CAUS_CAUSE_INTR_S 0 - -//***************************************************************************** -// -// Register: WDT_O_LOCK -// -//***************************************************************************** -// Field: [31:0] WDTLOCK -// -// WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers -// for write access. A write of any other value reapplies the lock, preventing -// any register updates (NOTE: TEST.TEST_EN bit is not lockable). -// -// A read of this register returns the following values: -// -// 0x0000.0000: Unlocked -// 0x0000.0001: Locked -#define WDT_LOCK_WDTLOCK_W 32 -#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF -#define WDT_LOCK_WDTLOCK_S 0 - - -#endif // __WDT__ diff --git a/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.cmd b/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.cmd deleted file mode 100644 index 66dd063e6..000000000 --- a/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.cmd +++ /dev/null @@ -1,124 +0,0 @@ -//***************************************************************************** -//! @file cc26x0f128.cmd -//! @brief CC26x0F128 rev2 linker file for Code Composer Studio. -//! -//! Revised $Date: 2017-03-28 15:32:09 +0200 (Tue, 28 Mar 2017) $ -//! Revision $Revision: 17730 $ -// -// This file is auto-generated. -// -// Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ -// -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//****************************************************************************/ - -/* Retain interrupt vector table variable */ ---retain=g_pfnVectors -/* Override default entry point. */ ---entry_point ResetISR -/* Allow main() to take args */ ---args 0x8 -/* Suppress warnings and errors: */ -/* - 10063: Warning about entry point not being _c_int00 */ -/* - 16011, 16012: 8-byte alignment errors. Observed when linking in object */ -/* files compiled using Keil (ARM compiler) */ ---diag_suppress=10063,16011,16012 - -/* The following command line options are set as part of the CCS project. */ -/* If you are building using the command line, or for some reason want to */ -/* define them here, you can uncomment and modify these lines as needed. */ -/* If you are using CCS for building, it is probably better to make any such */ -/* modifications in your CCS project and leave this file alone. */ -/* */ -/* --heap_size=0 */ -/* --stack_size=256 */ -/* --library=rtsv7M3_T_le_eabi.lib */ - -/* The starting address of the application. Normally the interrupt vectors */ -/* must be located at the beginning of the application. */ -#define FLASH_BASE 0x0 -#define FLASH_SIZE 0x20000 -#define RAM_BASE 0x20000000 -#define RAM_SIZE 0x5000 -#define GPRAM_BASE 0x11000000 -#define GPRAM_SIZE 0x2000 - - -/* System memory map */ - -MEMORY -{ - /* Application stored in and executes from internal flash */ - FLASH (RX) : origin = FLASH_BASE, length = FLASH_SIZE - /* Application uses internal RAM for data */ - SRAM (RWX) : origin = RAM_BASE, length = RAM_SIZE - /* Application can use GPRAM region as RAM if cache is disabled in the CCFG - (DEFAULT_CCFG_SIZE_AND_DIS_FLAGS.SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM = 0) */ - GPRAM (RWX): origin = GPRAM_BASE, length = GPRAM_SIZE -} - -/* Section allocation in memory */ - -SECTIONS -{ - .intvecs : > FLASH_BASE - .text : > FLASH - .const : > FLASH - .constdata : > FLASH - .rodata : > FLASH - .binit : > FLASH - .cinit : > FLASH - .pinit : > FLASH - .init_array : > FLASH - .emb_text : > FLASH - .ccfg : > FLASH (HIGH) - - .vtable : > SRAM - .vtable_ram : > SRAM - vtable_ram : > SRAM - .data : > SRAM - .bss : > SRAM - .sysmem : > SRAM - .stack : > SRAM (HIGH) - .nonretenvar : > SRAM - .TI.noinit : > SRAM - .gpram : > GPRAM - -#ifdef __TI_COMPILER_VERSION__ -#if __TI_COMPILER_VERSION__ >= 15009000 -/* Hide section from older compilers not supporting the "ramfunc" attribute. - See http://processors.wiki.ti.com/index.php/Placing_functions_in_RAM */ - .TI.ramfunc : {} load=FLASH, run=SRAM, table(BINIT) -#endif -#endif -} - -/* Create global constant that points to top of stack */ -/* CCS: Change stack size under Project Properties */ -__STACK_TOP = __stack + __STACK_SIZE; diff --git a/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.icf b/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.icf deleted file mode 100644 index 6e2652646..000000000 --- a/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.icf +++ /dev/null @@ -1,143 +0,0 @@ -//***************************************************************************** -//! @file cc26x0f128.icf -//! @brief CC26x0F128 rev2 linker file for IAR EWARM. -//! -//! Revised $Date: 2017-02-03 19:14:38 +0100 (Fri, 03 Feb 2017) $ -//! Revision $Revision: 17632 $ -// -// This file is auto-generated. -// -// Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ -// -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//****************************************************************************/ - - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x1000; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __GPRAM_START__ = 0x11000000; -define symbol __GPRAM_END__ = 0x11001FFF; - -// -// Define a memory region that covers the entire 4 GB addressable space of the -// processor. -// -define memory mem with size = 4G; - -// -// Define a region for the on-chip flash. -// -define region FLASH_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -// -// Define a region for the on-chip SRAM. -// -define region SRAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -// -// Place the interrupt vectors at the start of flash. -// -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -keep { section .intvec }; - -// -// Place the CCFG area at the end of flash -// -place at end of FLASH_region { readonly section .ccfg }; -keep { section .ccfg }; - -// -// Place remaining 'read only' in Flash -// -place in FLASH_region { readonly }; - - -// -// Place .vtable_ram in start of RAM -// -place at start of SRAM_region { section .vtable_ram }; - -// -// Define CSTACK block to contain .stack section. This enables the IAR IDE -// to properly show the stack content during debug. Place stack at end of -// retention RAM, do not initialize (initializing the stack will destroy the -// return address from the initialization code, causing the processor to branch -// to zero and fault) -// -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { section .stack }; -place at end of SRAM_region { block CSTACK }; -do not initialize { section .stack, section .noinit}; - -// -// Export stack top symbol. Used by startup file. -// -define exported symbol STACK_TOP = __ICFEDIT_region_RAM_end__ + 1; - -// -// Define a block for the heap. The size should be set to something other -// than zero if things in the C library that require the heap are used. -// -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -place in SRAM_region { block HEAP }; - -// -// Place all read/write items into RAM. -// -place in SRAM_region { readwrite }; -initialize by copy { readwrite }; - -// -// The USE_TIRTOS_ROM symbol is defined internally in the build flow (using -// --config_def USE_TIRTOS_ROM=1) for TI-RTOS applications whose app.cfg file -// specifies to use the ROM. -// -if (isdefinedsymbol(USE_TIRTOS_ROM)) { - include "TIRTOS_ROM.icf"; -} - -// -// Define a region for the on-chip GPRAM/cache. -// Application can use this region as RAM if cache is disabled in the CCFG -// (DEFAULT_CCFG_SIZE_AND_DIS_FLAGS.SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM = 0) -// -define region GPRAM_region = mem:[from __GPRAM_START__ to __GPRAM_END__]; -place in GPRAM_region {section .gpram}; diff --git a/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.lds b/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.lds deleted file mode 100644 index 7e9fa6367..000000000 --- a/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.lds +++ /dev/null @@ -1,138 +0,0 @@ -/* - @file cc26x0f128.lds - @brief CC26x0F128 linker configuration file for GNU compiler. - - Revised $Date: 2017-02-03 19:14:38 +0100 (Fri, 03 Feb 2017) $ - Revision $Revision: 17632 $ - - This file is auto-generated. - - Copyright (C) 2017 Texas Instruments Incorporated - http:www.ti.com/ - - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of Texas Instruments Incorporated nor the names of - its contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/* Entry Point */ -ENTRY( ResetISR ) - -/* System memory map */ -MEMORY -{ - /* Application is stored in and executes from internal flash */ - FLASH (RX) : ORIGIN = 0x0, LENGTH = 0x1FFA8 - /* Customer Configuration Area (CCFG) */ - FLASH_CCFG (RX) : ORIGIN = 0x1FFA8, LENGTH = 88 - /* Application uses internal RAM for data */ - SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x5000 - /* Application can use GPRAM region as RAM if cache is disabled in the CCFG - (DEFAULT_CCFG_SIZE_AND_DIS_FLAGS.SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM = 0) */ - GPRAM (RWX) : ORIGIN = 0x11000000, LENGTH = 0x2000 -} - -/*. Highest address of the stack. Used in startup file .*/ -_estack = ORIGIN(SRAM) + LENGTH(SRAM); /*end of SRAM .*/ - -/*. Generate a link error if heap and stack does not fit into RAM .*/ -_Min_Heap_Size = 0; -_Min_Stack_Size = 0x100; - - -/* Section allocation in memory */ -SECTIONS -{ - .text : - { - _text = .; - KEEP(*(.vectors)) - *(.text*) - *(.rodata*) - *(.init) - *(.fini*) - *(.eh_frame*) - _etext = .; - } > FLASH = 0 - - .ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - .init_array : - { - _init_array = .; - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array*)) - _einit_array = .; - } > FLASH - - .data : - { - _data = .; - *(vtable) - *(.data*) - _edata = .; - } > SRAM AT > FLASH - _ldata = LOADADDR(.data); - - .bss : - { - __bss_start__ = .; - _bss = .; - *(.bss*) - *(COMMON) - _ebss = .; - __bss_end__ = .; - } > SRAM - - .ccfg : - { - KEEP(*(.ccfg)); - } > FLASH_CCFG - - /* User_heap_stack section, used to check that there is enough SRAM left */ - ._user_heap_stack : - { - . = ALIGN(4); - end = .; - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } > SRAM - - .gpram : - { - } > GPRAM -} diff --git a/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.sct b/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.sct deleted file mode 100644 index 07edc0eaa..000000000 --- a/third_party/ti/devices/cc26x0/linker_files/cc26x0f128.sct +++ /dev/null @@ -1,68 +0,0 @@ -; /**************************************************************************** -; * @file cc26x0f128.sct -; * @brief CC26x0F128 rev2 scatter loading file for ARM linker. -; * -; * Revised $Date: 2017-02-03 19:14:38 +0100 (Fri, 03 Feb 2017) $ -; * Revision $Revision: 17632 $ -; * -; * This file is auto-generated. -; * -; * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ -; * -; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions -; * are met: -; * -; * Redistributions of source code must retain the above copyright -; * notice, this list of conditions and the following disclaimer. -; * -; * Redistributions in binary form must reproduce the above copyright -; * notice, this list of conditions and the following disclaimer in the -; * documentation and/or other materials provided with the distribution. -; * -; * Neither the name of Texas Instruments Incorporated nor the names of -; * its contributors may be used to endorse or promote products derived -; * from this software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -; * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -; * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -; * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -; * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -; * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; ****************************************************************************/ - -LR_IROM1 0x00000000 0x20000 { ; load region size_region - ER_IROM1 0x00000000 0x20000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 0x20000000 0x5000 { ; RW data - .ANY (+RW +ZI) - } - - ; Define a region for the on-chip GPRAM/cache. - ; Application can use this region as RAM if cache is disabled in the CCFG - ; (DEFAULT_CCFG_SIZE_AND_DIS_FLAGS.SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM = 0) - ;RW_IRAM2 0x11000000 0x00002000 { - ; *(.gpram) - ;} -} - -; Customer configuration area (CCFG) placed at end of device flash. -; Make sure the entry in this linker file is aligned with your application's -; CCFG area. -LR_CCFG (0x20000-88) { ; load region size_region - ER_CCFG ImageBase(LR_CCFG) { ; load address = execution address - *(.ccfg, +First) - } -} diff --git a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble.h b/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble.h deleted file mode 100644 index efe23e946..000000000 --- a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble.h +++ /dev/null @@ -1,235 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_cpe_ble.h -* Revised: $Date: 2016-12-07 13:37:33 +0100 (Wed, 07 Dec 2016) $ -* Revision: $Revision: 17556 $ -* -* Description: RF Core patch file for CC26x0 -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_CPE_BLE_H -#define _RF_PATCH_CPE_BLE_H - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#ifndef CPE_PATCH_TYPE -#define CPE_PATCH_TYPE static const uint32_t -#endif - -#ifndef SYS_PATCH_TYPE -#define SYS_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef _APPLY_PATCH_TAB -#define _APPLY_PATCH_TAB -#endif - - -CPE_PATCH_TYPE patchImageBle[] = { - 0x21000499, - 0x21000519, - 0x21000479, - 0x4c17b5f0, - 0x18612140, - 0x280278c8, - 0x4809d005, - 0x60012100, - 0x47884908, - 0x6e25bdf0, - 0x60354e07, - 0x43280760, - 0x68276620, - 0x480e6024, - 0x60274780, - 0xbdf06035, - 0x4004112c, - 0x000065a5, - 0x40044028, - 0x4c07b510, - 0x29007da1, - 0x2101d105, - 0x024875a1, - 0x393e4904, - 0x68204788, - 0xd0002800, - 0xbd104780, - 0x21000254, - 0x0000398b, - 0x4905b510, - 0xb6724a05, - 0x280178c8, - 0x2001dc02, - 0x1d127048, - 0x4710b662, - 0x21000294, - 0x0000476d, - 0x4e1ab5f8, - 0x6b314605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6334, - 0x07c00a40, - 0x2001d00c, - 0x6af10380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x490762f1, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x21000296, - 0x00003cdf, - 0x40044040, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, -}; -#define _NWORD_PATCHIMAGE_BLE 79 - -#define _NWORD_PATCHSYS_BLE 0 - -#define _IRQ_PATCH_0 0x21000411 -#define _IRQ_PATCH_1 0x21000451 - - -#ifndef _BLE_SYSRAM_START -#define _BLE_SYSRAM_START 0x20000000 -#endif - -#ifndef _BLE_CPERAM_START -#define _BLE_CPERAM_START 0x21000000 -#endif - -#define _BLE_SYS_PATCH_FIXED_ADDR 0x20000000 - -#define _BLE_PARSER_PATCH_TAB_OFFSET 0x0334 -#define _BLE_PATCH_TAB_OFFSET 0x033C -#define _BLE_IRQPATCH_OFFSET 0x03AC -#define _BLE_PATCH_VEC_OFFSET 0x0404 - -PATCH_FUN_SPEC void enterBleCpePatch(void) -{ - uint32_t *pPatchVec = (uint32_t *) (_BLE_CPERAM_START + _BLE_PATCH_VEC_OFFSET); - -#if (_NWORD_PATCHIMAGE_BLE > 0) - memcpy(pPatchVec, patchImageBle, sizeof(patchImageBle)); -#endif -} - -PATCH_FUN_SPEC void enterBleSysPatch(void) -{ -} - -PATCH_FUN_SPEC void configureBlePatch(void) -{ - uint8_t *pPatchTab = (uint8_t *) (_BLE_CPERAM_START + _BLE_PATCH_TAB_OFFSET); - uint32_t *pIrqPatch = (uint32_t *) (_BLE_CPERAM_START + _BLE_IRQPATCH_OFFSET); - - - pPatchTab[103] = 0; - pPatchTab[60] = 1; - pPatchTab[48] = 2; - - pIrqPatch[1] = _IRQ_PATCH_0; - pIrqPatch[9] = _IRQ_PATCH_1; -} - -PATCH_FUN_SPEC void applyBlePatch(void) -{ - enterBleSysPatch(); - enterBleCpePatch(); - configureBlePatch(); -} - -PATCH_FUN_SPEC void refreshBlePatch(void) -{ - enterBleCpePatch(); - configureBlePatch(); -} - -PATCH_FUN_SPEC void rf_patch_cpe_ble(void) -{ - applyBlePatch(); -} - -#undef _IRQ_PATCH_0 -#undef _IRQ_PATCH_1 - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // _RF_PATCH_CPE_BLE_H - diff --git a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h b/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h deleted file mode 100644 index ccba0aba7..000000000 --- a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h +++ /dev/null @@ -1,330 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_cpe_ble_priv_1_2.h -* Revised: $Date: 2016-12-07 13:37:33 +0100 (Wed, 07 Dec 2016) $ -* Revision: $Revision: 17556 $ -* -* Description: RF Core patch file for CC26x0 Bluetooth Low Energy with privacy 1.2 support -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_CPE_BLE_PRIV_1_2_H -#define _RF_PATCH_CPE_BLE_PRIV_1_2_H - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#ifndef CPE_PATCH_TYPE -#define CPE_PATCH_TYPE static const uint32_t -#endif - -#ifndef SYS_PATCH_TYPE -#define SYS_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef _APPLY_PATCH_TAB -#define _APPLY_PATCH_TAB -#endif - - -CPE_PATCH_TYPE patchImageBlePriv12[] = { - 0x210005c5, - 0x21000611, - 0x21000691, - 0x2100047d, - 0x4c17b5f0, - 0x18612140, - 0x280278c8, - 0x4809d005, - 0x60012100, - 0x47884908, - 0x6e25bdf0, - 0x60354e07, - 0x43280760, - 0x68276620, - 0x480e6024, - 0x60274780, - 0xbdf06035, - 0x4004112c, - 0x000065a5, - 0x40044028, - 0x4c07b510, - 0x29007da1, - 0x2101d105, - 0x024875a1, - 0x393e4904, - 0x68204788, - 0xd0002800, - 0xbd104780, - 0x21000254, - 0x0000398b, - 0x4905b510, - 0xb6724a05, - 0x280178c8, - 0x2001dc02, - 0x1d127048, - 0x4710b662, - 0x21000294, - 0x0000476d, - 0x4d53b5fe, - 0x462c4628, - 0x90003040, - 0x7e014627, - 0x78383760, - 0xd0022900, - 0xd10707c0, - 0x09c1e050, - 0x07c0d04e, - 0x7d20d14c, - 0xd5490640, - 0x31724629, - 0x20064a48, - 0x98004790, - 0x28007e00, - 0x7d20d007, - 0xd5010640, - 0xe0002003, - 0x26132001, - 0x6f68e008, - 0x28010f80, - 0x2006d002, - 0xe0014606, - 0x26072003, - 0x02312201, - 0x1a890412, - 0x02008a7a, - 0x43020412, - 0x35806f6b, - 0x68a89501, - 0x47a84d37, - 0x2e062201, - 0x2e07d002, - 0xe007d002, - 0xe00543c0, - 0x70797839, - 0x70394311, - 0x61089901, - 0xda012800, - 0x55022039, - 0x7e809800, - 0xd0022800, - 0x201e2106, - 0x6a61e002, - 0x201f1f89, - 0x6ca162a1, - 0x64e04788, - 0xbdfe2000, - 0x47804826, - 0x4822bdfe, - 0x78413060, - 0xd0022900, - 0x21007001, - 0x48217041, - 0x470038b0, - 0x4e1cb5f8, - 0x4635481f, - 0x7fec3540, - 0x09e14637, - 0x6db1d01a, - 0xd0172901, - 0x29007f69, - 0x07a1d002, - 0xe011d502, - 0xd10f07e1, - 0x06497d39, - 0x2103d50c, - 0x77e94321, - 0x6f314780, - 0x29010f89, - 0x2100d002, - 0x76793720, - 0xbdf877ec, - 0xbdf84780, - 0x31404909, - 0x28157508, - 0x281bd008, - 0x281dd008, - 0x490ad008, - 0x18400080, - 0x47706980, - 0x47704808, - 0x47704808, - 0x47704808, - 0x21000144, - 0x0000b8af, - 0x0000a001, - 0x0000be03, - 0x0000b98d, - 0x0000ccc0, - 0x21000579, - 0x21000563, - 0x2100049d, - 0x4e1ab5f8, - 0x6b314605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6334, - 0x07c00a40, - 0x2001d00c, - 0x6af10380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x490762f1, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x21000296, - 0x00003cdf, - 0x40044040, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, -}; -#define _NWORD_PATCHIMAGE_BLE_PRIV_1_2 173 - -#define _NWORD_PATCHSYS_BLE_PRIV_1_2 0 - -#define _IRQ_PATCH_0 0x21000415 -#define _IRQ_PATCH_1 0x21000455 - - -#ifndef _BLE_PRIV_1_2_SYSRAM_START -#define _BLE_PRIV_1_2_SYSRAM_START 0x20000000 -#endif - -#ifndef _BLE_PRIV_1_2_CPERAM_START -#define _BLE_PRIV_1_2_CPERAM_START 0x21000000 -#endif - -#define _BLE_PRIV_1_2_SYS_PATCH_FIXED_ADDR 0x20000000 - -#define _BLE_PRIV_1_2_PARSER_PATCH_TAB_OFFSET 0x0334 -#define _BLE_PRIV_1_2_PATCH_TAB_OFFSET 0x033C -#define _BLE_PRIV_1_2_IRQPATCH_OFFSET 0x03AC -#define _BLE_PRIV_1_2_PATCH_VEC_OFFSET 0x0404 - -PATCH_FUN_SPEC void enterBlePriv12CpePatch(void) -{ - uint32_t *pPatchVec = (uint32_t *) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_VEC_OFFSET); - -#if (_NWORD_PATCHIMAGE_BLE_PRIV_1_2 > 0) - memcpy(pPatchVec, patchImageBlePriv12, sizeof(patchImageBlePriv12)); -#endif -} - -PATCH_FUN_SPEC void enterBlePriv12SysPatch(void) -{ -} - -PATCH_FUN_SPEC void configureBlePriv12Patch(void) -{ - uint8_t *pPatchTab = (uint8_t *) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_TAB_OFFSET); - uint32_t *pIrqPatch = (uint32_t *) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_IRQPATCH_OFFSET); - - - pPatchTab[1] = 0; - pPatchTab[103] = 1; - pPatchTab[60] = 2; - pPatchTab[48] = 3; - - pIrqPatch[1] = _IRQ_PATCH_0; - pIrqPatch[9] = _IRQ_PATCH_1; -} - -PATCH_FUN_SPEC void applyBlePriv12Patch(void) -{ - enterBlePriv12SysPatch(); - enterBlePriv12CpePatch(); - configureBlePriv12Patch(); -} - -PATCH_FUN_SPEC void refreshBlePriv12Patch(void) -{ - enterBlePriv12CpePatch(); - configureBlePriv12Patch(); -} - -PATCH_FUN_SPEC void rf_patch_cpe_ble_priv_1_2(void) -{ - applyBlePriv12Patch(); -} - -#undef _IRQ_PATCH_0 -#undef _IRQ_PATCH_1 - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // _RF_PATCH_CPE_BLE_PRIV_1_2_H - diff --git a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_genfsk.h b/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_genfsk.h deleted file mode 100644 index a0efda4cc..000000000 --- a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_genfsk.h +++ /dev/null @@ -1,225 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_cpe_genfsk.h -* Revised: $Date: 2017-01-30 18:00:26 +0100 (Mon, 30 Jan 2017) $ -* Revision: $Revision: 17599 $ -* -* Description: RF core patch for CC26x0 Generic FSK -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_CPE_GENFSK_H -#define _RF_PATCH_CPE_GENFSK_H - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#ifndef CPE_PATCH_TYPE -#define CPE_PATCH_TYPE static const uint32_t -#endif - -#ifndef SYS_PATCH_TYPE -#define SYS_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef _APPLY_PATCH_TAB -#define _APPLY_PATCH_TAB -#endif - - -CPE_PATCH_TYPE patchImageGenfsk[] = { - 0x21000475, - 0x210004f5, - 0x4c17b5f0, - 0x18612140, - 0x280278c8, - 0x4809d005, - 0x60012100, - 0x47884908, - 0x6e25bdf0, - 0x60354e07, - 0x43280760, - 0x68276620, - 0x480e6024, - 0x60274780, - 0xbdf06035, - 0x4004112c, - 0x000065a5, - 0x40044028, - 0x4c07b510, - 0x29007da1, - 0x2101d105, - 0x024875a1, - 0x393e4904, - 0x68204788, - 0xd0002800, - 0xbd104780, - 0x21000254, - 0x0000398b, - 0x4e1ab5f8, - 0x6b314605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6334, - 0x07c00a40, - 0x2001d00c, - 0x6af10380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x490762f1, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x21000296, - 0x00003cdf, - 0x40044040, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, -}; -#define _NWORD_PATCHIMAGE_GENFSK 70 - -#define _NWORD_PATCHSYS_GENFSK 0 - -#define _IRQ_PATCH_0 0x2100040d -#define _IRQ_PATCH_1 0x2100044d - - -#ifndef _GENFSK_SYSRAM_START -#define _GENFSK_SYSRAM_START 0x20000000 -#endif - -#ifndef _GENFSK_CPERAM_START -#define _GENFSK_CPERAM_START 0x21000000 -#endif - -#define _GENFSK_SYS_PATCH_FIXED_ADDR 0x20000000 - -#define _GENFSK_PARSER_PATCH_TAB_OFFSET 0x0334 -#define _GENFSK_PATCH_TAB_OFFSET 0x033C -#define _GENFSK_IRQPATCH_OFFSET 0x03AC -#define _GENFSK_PATCH_VEC_OFFSET 0x0404 - -PATCH_FUN_SPEC void enterGenfskCpePatch(void) -{ - uint32_t *pPatchVec = (uint32_t *) (_GENFSK_CPERAM_START + _GENFSK_PATCH_VEC_OFFSET); - -#if (_NWORD_PATCHIMAGE_GENFSK > 0) - memcpy(pPatchVec, patchImageGenfsk, sizeof(patchImageGenfsk)); -#endif -} - -PATCH_FUN_SPEC void enterGenfskSysPatch(void) -{ -} - -PATCH_FUN_SPEC void configureGenfskPatch(void) -{ - uint8_t *pPatchTab = (uint8_t *) (_GENFSK_CPERAM_START + _GENFSK_PATCH_TAB_OFFSET); - uint32_t *pIrqPatch = (uint32_t *) (_GENFSK_CPERAM_START + _GENFSK_IRQPATCH_OFFSET); - - - pPatchTab[103] = 0; - pPatchTab[60] = 1; - - pIrqPatch[1] = _IRQ_PATCH_0; - pIrqPatch[9] = _IRQ_PATCH_1; -} - -PATCH_FUN_SPEC void applyGenfskPatch(void) -{ - enterGenfskSysPatch(); - enterGenfskCpePatch(); - configureGenfskPatch(); -} - -PATCH_FUN_SPEC void refreshGenfskPatch(void) -{ - enterGenfskCpePatch(); - configureGenfskPatch(); -} - -PATCH_FUN_SPEC void rf_patch_cpe_genfsk(void) -{ - applyGenfskPatch(); -} - -#undef _IRQ_PATCH_0 -#undef _IRQ_PATCH_1 - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // _RF_PATCH_CPE_GENFSK_H - diff --git a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ieee.h b/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ieee.h deleted file mode 100644 index 0a818d850..000000000 --- a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ieee.h +++ /dev/null @@ -1,269 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_cpe_ieee.h -* Revised: $Date: 2017-08-24 11:43:33 +0200 (Thu, 24 Aug 2017) $ -* Revision: $Revision: 17889 $ -* -* Description: RF Core patch file for CC26xx IEEE 802.15.4 PHY -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_CPE_IEEE_H -#define _RF_PATCH_CPE_IEEE_H - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#ifndef CPE_PATCH_TYPE -#define CPE_PATCH_TYPE static const uint32_t -#endif - -#ifndef SYS_PATCH_TYPE -#define SYS_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef _APPLY_PATCH_TAB -#define _APPLY_PATCH_TAB -#endif - - -CPE_PATCH_TYPE patchImageIeee[] = { - 0x210004ef, - 0x21000419, - 0x21000519, - 0x21000599, - 0x210004b1, - 0x22024823, - 0x421a7dc3, - 0xd0034472, - 0x1dc04678, - 0xb5f84686, - 0x4c1f4710, - 0x200834ae, - 0x490347a0, - 0x60082008, - 0x3cec6008, - 0xbdf847a0, - 0x40045004, - 0x4c17b5f0, - 0x18612140, - 0x280278c8, - 0x4809d005, - 0x60012100, - 0x47884908, - 0x6e25bdf0, - 0x60354e07, - 0x43280760, - 0x68276620, - 0x480e6024, - 0x60274780, - 0xbdf06035, - 0x4004112c, - 0x000065a5, - 0x40044028, - 0x4c07b510, - 0x29007da1, - 0x2101d105, - 0x024875a1, - 0x393e4904, - 0x68204788, - 0xd0002800, - 0xbd104780, - 0x21000254, - 0x0000398b, - 0x6a034807, - 0x46784907, - 0x46861dc0, - 0x4788b5f8, - 0x009b089b, - 0x6a014802, - 0xd10007c9, - 0xbdf86203, - 0x40045040, - 0x0000f1ab, - 0x6a00480b, - 0xd00407c0, - 0x2201480a, - 0x43117801, - 0x48097001, - 0x72c84700, - 0xd006280d, - 0x00802285, - 0x18800252, - 0x60486840, - 0x48044770, - 0x0000e7fb, - 0x40045040, - 0x21000268, - 0x0000ff39, - 0x210004d9, - 0x4e1ab5f8, - 0x6b314605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6334, - 0x07c00a40, - 0x2001d00c, - 0x6af10380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x490762f1, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x21000296, - 0x00003cdf, - 0x40044040, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, -}; -#define _NWORD_PATCHIMAGE_IEEE 111 - -#define _NWORD_PATCHSYS_IEEE 0 - -#define _IRQ_PATCH_0 0x21000449 -#define _IRQ_PATCH_1 0x21000489 - - -#ifndef _IEEE_SYSRAM_START -#define _IEEE_SYSRAM_START 0x20000000 -#endif - -#ifndef _IEEE_CPERAM_START -#define _IEEE_CPERAM_START 0x21000000 -#endif - -#define _IEEE_SYS_PATCH_FIXED_ADDR 0x20000000 - -#define _IEEE_PARSER_PATCH_TAB_OFFSET 0x0334 -#define _IEEE_PATCH_TAB_OFFSET 0x033C -#define _IEEE_IRQPATCH_OFFSET 0x03AC -#define _IEEE_PATCH_VEC_OFFSET 0x0404 - -PATCH_FUN_SPEC void enterIeeeCpePatch(void) -{ - uint32_t *pPatchVec = (uint32_t *) (_IEEE_CPERAM_START + _IEEE_PATCH_VEC_OFFSET); - -#if (_NWORD_PATCHIMAGE_IEEE > 0) - memcpy(pPatchVec, patchImageIeee, sizeof(patchImageIeee)); -#endif -} - -PATCH_FUN_SPEC void enterIeeeSysPatch(void) -{ -} - -PATCH_FUN_SPEC void configureIeeePatch(void) -{ - uint8_t *pPatchTab = (uint8_t *) (_IEEE_CPERAM_START + _IEEE_PATCH_TAB_OFFSET); - uint32_t *pIrqPatch = (uint32_t *) (_IEEE_CPERAM_START + _IEEE_IRQPATCH_OFFSET); - - - pPatchTab[5] = 0; - pPatchTab[52] = 1; - pPatchTab[103] = 2; - pPatchTab[60] = 3; - pPatchTab[38] = 4; - - pIrqPatch[1] = _IRQ_PATCH_0; - pIrqPatch[9] = _IRQ_PATCH_1; -} - -PATCH_FUN_SPEC void applyIeeePatch(void) -{ - enterIeeeSysPatch(); - enterIeeeCpePatch(); - configureIeeePatch(); -} - -PATCH_FUN_SPEC void refreshIeeePatch(void) -{ - enterIeeeCpePatch(); - configureIeeePatch(); -} - -PATCH_FUN_SPEC void rf_patch_cpe_ieee(void) -{ - applyIeeePatch(); -} - -#undef _IRQ_PATCH_0 -#undef _IRQ_PATCH_1 - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // _RF_PATCH_CPE_IEEE_H - diff --git a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_mce_genfsk.h b/third_party/ti/devices/cc26x0/rf_patches/rf_patch_mce_genfsk.h deleted file mode 100644 index 472c3b630..000000000 --- a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_mce_genfsk.h +++ /dev/null @@ -1,567 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_mce_genfsk.h -* Revised: $Date: 2017-05-04 12:39:32 +0200 (Thu, 04 May 2017) $ -* Revision: $Revision: 17776 $ -* -* Description: RF core patch for CC26x0 Generic FSK -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_MCE_GENFSK_H -#define _RF_PATCH_MCE_GENFSK_H - -#include -#include "../inc/hw_types.h" - -#ifndef MCE_PATCH_TYPE -#define MCE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_MCERAM_BASE -#define RFC_MCERAM_BASE 0x21008000 -#endif - -#ifndef MCE_PATCH_MODE -#define MCE_PATCH_MODE 0 -#endif - -MCE_PATCH_TYPE patchGenfskMce[460] = { - 0x2fcf603c, - 0x030c3f9d, - 0x070c680a, - 0x003f0387, - 0x00fffff0, - 0x0000ff00, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00070003, - 0x00003d1f, - 0x04000000, - 0x0000000f, - 0x000b0387, - 0x004340f4, - 0x80828000, - 0x00000670, - 0x0510091e, - 0x00050054, - 0x3e100200, - 0x00000061, - 0x3030002f, - 0x0000027f, - 0x00000000, - 0x0000aa00, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72487220, - 0x7303a32d, - 0x72037305, - 0x73067304, - 0x73767204, - 0xc7c07276, - 0x00018001, - 0x90109001, - 0x90010801, - 0x720d720c, - 0xb0c0720e, - 0xb0f07100, - 0x7218a0c0, - 0x10208132, - 0x06703952, - 0x16300020, - 0x14011101, - 0x60796c01, - 0x60ec607b, - 0x60796352, - 0x60796079, - 0x6079607a, - 0x60ec607b, - 0x60796352, - 0x60796079, - 0x1210607a, - 0x730f7220, - 0x73117310, - 0x00108181, - 0xb0709180, - 0x606f6051, - 0xc030606f, - 0xc1416791, - 0xc470c282, - 0x6f131820, - 0x16116e23, - 0x68811612, - 0x9ab07830, - 0x9ac07840, - 0x9ad07850, - 0x9ae07860, - 0xc5a0c482, - 0x40961820, - 0x6e231203, - 0x68931612, - 0x8160606f, - 0x81409490, - 0x2a703980, - 0x16111001, - 0x84448432, - 0xc0f5c0f3, - 0x1c01c200, - 0xc10040bb, - 0x40b11c10, - 0x10134cb3, - 0x18301803, - 0x1a101a13, - 0x68ae3912, - 0x13f360bb, - 0x13f360bb, - 0xc1001015, - 0x1a151850, - 0x39141a10, - 0xb0d868b9, - 0xb1087100, - 0xb200a0d8, - 0xb003b480, - 0xb002b013, - 0x7229b012, - 0x7100b0d0, - 0x8140b100, - 0x71009290, - 0x8140b100, - 0x44cb22f0, - 0x1c0313f0, - 0x929340d7, - 0x71009492, - 0x9295b100, - 0x71009494, - 0xb0d0b100, - 0x7000a480, - 0xc030a0d1, - 0xc0409760, - 0xb0f19780, - 0x7100b0c1, - 0xa0c1b0f1, - 0xa0037276, - 0x7000a002, - 0x7310730f, - 0x6791c040, - 0x91c0c100, - 0xb4836497, - 0xb0c3b0f3, - 0xa0c37100, - 0x606f64de, - 0xb016b006, - 0xb014b004, - 0xb012b002, - 0x78728400, - 0x81430420, - 0x2a733983, - 0xc1f29473, - 0x31621832, - 0x31511021, - 0x00200012, - 0x10309400, - 0x10011610, - 0x39303121, - 0x41172210, - 0x31501220, - 0x31801003, - 0x16300010, - 0x12029350, - 0x22731204, - 0x8430412a, - 0x87d297c0, - 0x84501a82, - 0x87d497c0, - 0x612c1a84, - 0x41372263, - 0x97c08440, - 0x1a8087d0, - 0x84601402, - 0x87d097c0, - 0x14041a80, - 0x84406143, - 0x041078a1, - 0x87d297c0, - 0x84601a42, - 0x041078a1, - 0x87d497c0, - 0x31521a44, - 0x39633154, - 0x16130633, - 0x38343832, - 0x39823182, - 0x00423184, - 0x78109572, - 0x90509030, - 0x90407820, - 0xb2059060, - 0x83038ae2, - 0xc00c9302, - 0x8140c00b, - 0x39803180, - 0x81413940, - 0x0431c0f3, - 0x1441c014, - 0x1412c002, - 0x31226965, - 0xc010847d, - 0x312d140d, - 0x8ace142d, - 0x311e318e, - 0x8ac9397e, - 0x39793149, - 0x31293949, - 0xb072109a, - 0xb06ea04e, - 0xb06cb011, - 0x7276978a, - 0xa764b764, - 0x9762c662, - 0x66d3c04f, - 0x22f18ab1, - 0x8ad1458b, - 0x458b22f1, - 0x71006231, - 0xb760b073, - 0x220780b7, - 0xa76045c2, - 0x22f18ab1, - 0x2237419c, - 0xb113419c, - 0x223080b0, - 0x61aa4597, - 0x41af22e1, - 0x22508090, - 0xb0f541af, - 0x22208210, - 0x9789418b, - 0xa764b764, - 0x618bb0f6, - 0xb764978d, - 0xb0f6a764, - 0x8ad0618b, - 0x41bb22f0, - 0x41bb2237, - 0xb113b075, - 0x223080b0, - 0xb08745b5, - 0x22d1618b, - 0x80904316, - 0x43162220, - 0x618b6699, - 0xc7f3978f, - 0x31808410, - 0x31833980, - 0x94100030, - 0xa0e3b087, - 0xa0c2b0f2, - 0xa0c5b0f5, - 0xb0c1b0f1, - 0xb110a0c6, - 0x80b0b113, - 0x45d32200, - 0x45d32230, - 0x12607100, - 0xb0f19780, - 0x8961b88f, - 0x18018570, - 0x8a609551, - 0xa4888a71, - 0xc022a487, - 0x1c211801, - 0x14124df3, - 0x61f449f1, - 0x41f41c01, - 0xb4874df3, - 0xb48861f4, - 0xb061b041, - 0x22e08ad0, - 0x821041fc, - 0x45772220, - 0xb04e7100, - 0x80b1b06e, - 0x468b2201, - 0x468b2231, - 0xb0f67276, - 0x31218471, - 0x1410c260, - 0xc7e09780, - 0xc6f09760, - 0xb0f69760, - 0xa0c1b0c6, - 0x8a63b7b0, - 0x8a838a74, - 0x71008a94, - 0x220180b1, - 0x2231468b, - 0x8ab0468b, - 0x462322c0, - 0x22018991, - 0x81c14177, - 0x91c0c000, - 0x81a28470, - 0x91c16a27, - 0x9070c300, - 0xa0e0b201, - 0xa044a0e3, - 0x71007000, - 0xb760b073, - 0x220780b7, - 0x22374650, - 0xa760466e, - 0x22e18ab1, - 0x80904249, - 0x42492250, - 0x8210b0f5, - 0x42312220, - 0xb764978d, - 0xb0f6a764, - 0x22d16231, - 0x80904316, - 0x43162220, - 0x62316699, - 0xb0f2978f, - 0xb0f5a0c2, - 0xb0f1a0c5, - 0xa0c6b0c1, - 0xb113b110, - 0x220080b0, - 0x22304658, - 0x71004658, - 0x97801260, - 0xb88fb0f1, - 0x85708961, - 0x3d803180, - 0x95511801, - 0x8a718a60, - 0x61e5a182, - 0xb0f2978f, - 0xb0f5a0c2, - 0xb0f1a0c5, - 0xa0c6b0c1, - 0xb113b110, - 0x220080b0, - 0x22304676, - 0x71004676, - 0x97801260, - 0xb88fb0f1, - 0x85708961, - 0x18013d80, - 0x8a809551, - 0xb1828a91, - 0xb07361e5, - 0xb760a760, - 0xb072a7b0, - 0xb06ea04e, - 0x8ab0b011, - 0x45c222f0, - 0x46502201, - 0x8ab0626e, - 0x469f22b0, - 0x46d11e3b, - 0x1e7b62a1, - 0xc00b46d1, - 0x8940b889, - 0x3d803180, - 0x3d301610, - 0x80b0140c, - 0x42ad2200, - 0x8ab37000, - 0x06f33983, - 0xcff08ab1, - 0x30310401, - 0x4ec91c1c, - 0x18101200, - 0x4acb1c0c, - 0x220080b0, - 0x700042be, - 0x161210c2, - 0x8ae13c32, - 0x22108320, - 0x62cf42cd, - 0xb0f29301, - 0x101c7000, - 0x100c62ba, - 0x182162ba, - 0x142162c6, - 0x161b62c6, - 0xb0f662c7, - 0xb110b0f1, - 0xb0f5b113, - 0x720cb0f2, - 0x720e720d, - 0xb0e3b0e0, - 0x22f28ab2, - 0xb0c642e4, - 0x62e7b763, - 0x22f08ad0, - 0xb4054307, - 0xb428a404, - 0xcaa0a429, - 0xcaa13180, - 0x94510001, - 0x8ad39461, - 0x39833183, - 0x31808410, - 0x31833980, - 0x94100030, - 0x31508400, - 0x8ad33950, - 0x06f33983, - 0x1834c1f4, - 0x31343184, - 0x94000040, - 0x22e2b089, - 0x8aca4311, - 0x398a394a, - 0x978a312a, - 0xb0c6b0c5, - 0x8ab2b763, - 0x431522d2, - 0x7000b0c2, - 0xa0e0b20f, - 0x978ea0e3, - 0xa764b764, - 0xb110b0f6, - 0x8210b113, - 0x431f22f0, - 0x8002b0f5, - 0xa006a004, - 0x7203a001, - 0xc0507204, - 0x71006791, - 0xb0f6b764, - 0xa20fb0c5, - 0xb0f57100, - 0x7810a0c5, - 0x90029030, - 0x90407820, - 0xb0729060, - 0x66d3a20f, - 0xa764978a, - 0x6184b0f6, - 0x8180b88c, - 0x392489a4, - 0x00043184, - 0xc0609184, - 0x73766791, - 0x72487276, - 0x72027206, - 0x73057204, - 0x606f7306, - 0x91b01300, - 0xc070b32d, - 0xb0f86791, - 0x120064fa, - 0x97801a10, - 0x9760c380, - 0x9760c280, - 0xb0c6a0c1, - 0x22008090, - 0x81544451, - 0x43621e04, - 0xb0f69784, - 0xd0808552, - 0x67919862, - 0x22118991, - 0x8a824378, - 0xe0908a93, - 0x98739862, - 0x637e6791, - 0x8a738a62, - 0x9862e0a0, - 0x67919873, - 0x87818790, - 0x4b8e1c01, - 0x1ef11801, - 0x87814b8c, - 0x97811af1, - 0xb0f67100, - 0x978116f1, - 0x7100a205, - 0xa0c6b0f6, - 0x98506340, - 0x22008840, - 0xb8304792, - 0x00007000 -}; - -PATCH_FUN_SPEC void rf_patch_mce_genfsk(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 460; i++) { - HWREG(RFC_MCERAM_BASE + 4 * i) = patchGenfskMce[i]; - } -#else - const uint32_t *pS = patchGenfskMce; - volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 57; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; -#endif -} - -#endif diff --git a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_mce_ieee_s.h b/third_party/ti/devices/cc26x0/rf_patches/rf_patch_mce_ieee_s.h deleted file mode 100644 index 34731f159..000000000 --- a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_mce_ieee_s.h +++ /dev/null @@ -1,354 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_mce_ieee_s.h -* Revised: $Date: 2017-08-24 11:43:33 +0200 (Thu, 24 Aug 2017) $ -* Revision: $Revision: 17889 $ -* -* Description: RF core patch for CC26x0 IEEE 802.15.4 Single Ended Output -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_MCE_IEEE_S_H -#define _RF_PATCH_MCE_IEEE_S_H - -#include -#include "../inc/hw_types.h" - -#ifndef MCE_PATCH_TYPE -#define MCE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_MCERAM_BASE -#define RFC_MCERAM_BASE 0x21008000 -#endif - -#ifndef MCE_PATCH_MODE -#define MCE_PATCH_MODE 0 -#endif - -MCE_PATCH_TYPE patchZigbeeXsIsMce[256] = { - 0xf703605f, - 0x70399b3a, - 0x039bb3af, - 0x39b33af7, - 0x9b3aaf70, - 0xb3aff703, - 0x3af77039, - 0xaf70039b, - 0x08fcb9b3, - 0x8fc664c5, - 0xfc644c50, - 0xc64cc508, - 0x64c5508f, - 0x4c5008fc, - 0xc5088fc6, - 0x508ffc64, - 0x0fcfc64c, - 0x7f7f079c, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000003, - 0x0000001f, - 0x80000000, - 0x0004000c, - 0x000114c4, - 0x00000009, - 0x00008000, - 0x002b0670, - 0x0a11121d, - 0x0b600000, - 0x40100000, - 0x00000040, - 0x1e1e0006, - 0x0000001e, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72200000, - 0x720d720c, - 0x7248720e, - 0x7203a32d, - 0x73057204, - 0x73767306, - 0xc7c07276, - 0xb0c09010, - 0xa0c07100, - 0x7218b0f0, - 0x10208132, - 0x06703952, - 0x16300020, - 0x14011101, - 0x609b6c01, - 0x60c860a9, - 0x6147612c, - 0x609b609b, - 0x609b609c, - 0x609b609b, - 0x609b609b, - 0x609b609b, - 0x609b609c, - 0x609b609b, - 0x609b609b, - 0x609b609b, - 0x609b609c, - 0x609b609b, - 0x609b609b, - 0x609b609b, - 0x60a0609c, - 0x60a0664e, - 0x60a11220, - 0x730f1210, - 0x73117310, - 0x00108181, - 0xb0709180, - 0xc301606d, - 0xc420c282, - 0x6f131820, - 0x16116e23, - 0x68ad1612, - 0xc810c482, - 0x40ba1820, - 0x6e231203, - 0x68b71612, - 0x60a072ab, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xc1307276, - 0xb0f391c0, - 0xb0d8b108, - 0xb1087100, - 0xb200a0d8, - 0x1e008ab0, - 0xb76040da, - 0xb0f19780, - 0x7100b0c1, - 0xb013b483, - 0xb012b003, - 0xb0f1b002, - 0x7276a0c1, - 0x7100b0c3, - 0xa0c3b0f3, - 0xc0301000, - 0xc0209760, - 0xb0c19780, - 0xb0f17100, - 0x7276a0c1, - 0xa0037248, - 0x7248a002, - 0x73067305, - 0x72767376, - 0x9010c7c0, - 0x000060a0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xc0307276, - 0xb00291b0, - 0xb006b004, - 0x90507a10, - 0x7a209030, - 0x90409060, - 0x94507810, - 0x94607820, - 0xc0f18160, - 0xc0120410, - 0x14023110, - 0x94306f20, - 0x6f201612, - 0x84209440, - 0x84213180, - 0x39813181, - 0x94100010, - 0xb2051200, - 0x31858165, - 0x39853145, - 0x120e3945, - 0x12061217, - 0x940012f0, - 0x9400c190, - 0xb119b011, - 0xa0ecb0e9, - 0x7100b089, - 0xa0e9b119, - 0xb0ecb11c, - 0x7100a404, - 0x659bb11c, - 0x417e1e76, - 0x45471eaf, - 0x1c90c140, - 0x12054d47, - 0x12761202, - 0x9070c300, - 0xc070b200, - 0xc0c065fa, - 0x7a309400, - 0x61859410, - 0x919f1647, - 0x1e008150, - 0x1c704185, - 0x7100498a, - 0x22008090, - 0x61684470, - 0x7276a205, - 0x72047203, - 0x73067305, - 0xa004a002, - 0x7248a006, - 0x73067305, - 0x72767376, - 0x9010c7c0, - 0x120960a0, - 0xc0cc120a, - 0xb88e120d, - 0x1c898928, - 0x1c8a49a6, - 0x61b34dac, - 0x12001089, - 0x100a1880, - 0x61b310db, - 0x1200108a, - 0x10091880, - 0x168b10db, - 0x161d61b3, - 0x41b81e8d, - 0x619f908c, - 0x1e8210bf, - 0x149541c3, - 0x1e821612, - 0x312545c3, - 0x00058180, - 0x1e8b9185, - 0x1a8b49c6, - 0x18b0c070, - 0x11011630, - 0x6c011401, - 0x908c908c, - 0x908c908c, - 0x908c908c, - 0x908c908c, - 0x1000b082, - 0x8923b88e, - 0xb083b083, - 0xb88e1000, - 0x1e8f8924, - 0x1ca349e4, - 0x1ca449e9, - 0x700049eb, - 0x4de91c93, - 0x4deb1c94, - 0x1a1e7000, - 0x161e61ed, - 0xc04061ed, - 0x49f41ce0, - 0x164010e0, - 0x700049f7, - 0xb085c00e, - 0xc00e7000, - 0x7000b084, - 0x88409850, - 0x45fb2200, - 0x7000b830 -}; - -PATCH_FUN_SPEC void rf_patch_mce_ieee_s(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 256; i++) { - HWREG(RFC_MCERAM_BASE + 4 * i) = patchZigbeeXsIsMce[i]; - } -#else - const uint32_t *pS = patchZigbeeXsIsMce; - volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 32; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); -#endif -} - -#endif diff --git a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ble.h b/third_party/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ble.h deleted file mode 100644 index 78be2d049..000000000 --- a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ble.h +++ /dev/null @@ -1,421 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_rfe_ble.h -* Revised: $Date: 2017-05-04 12:39:32 +0200 (Thu, 04 May 2017) $ -* Revision: $Revision: 17776 $ -* -* Description: RF core patch for CC26x0 BLE -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - - -#ifndef _RF_PATCH_RFE_BLE_H -#define _RF_PATCH_RFE_BLE_H - -#include -#include "../inc/hw_types.h" - -#ifndef RFE_PATCH_TYPE -#define RFE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_RFERAM_BASE -#define RFC_RFERAM_BASE 0x2100C000 -#endif - -#ifndef RFE_PATCH_MODE -#define RFE_PATCH_MODE 0 -#endif - -RFE_PATCH_TYPE patchBleRfe[315] = { - 0x00006154, - 0x0002147f, - 0x00050006, - 0x0008000f, - 0x00520048, - 0x003fff80, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x00000000, - 0x000f0000, - 0x00000008, - 0x0000003f, - 0x003f0040, - 0x00040000, - 0x000e0068, - 0x000600dc, - 0x001a0043, - 0x00000005, - 0x00020000, - 0x00000000, - 0x00000000, - 0x00c00004, - 0x00040000, - 0x000000c0, - 0x00000007, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x40632241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x686f1614, - 0x10257000, - 0x9100c050, - 0xc140c3f4, - 0x6f031420, - 0x04411031, - 0x22f08250, - 0x26514084, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x64537000, - 0x1031c052, - 0x31610631, - 0x645602c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006456, - 0x9101c051, - 0xc0e2cc01, - 0x64536456, - 0xc0c2c111, - 0xb0546456, - 0xa0547100, - 0x80f0b064, - 0x40b52200, - 0x90b01240, - 0xc2f0b032, - 0xc11168c0, - 0x6456c122, - 0x68c5c0b0, - 0x9101c051, - 0x3182c0e2, - 0x00028260, - 0xb1109132, - 0x39538253, - 0x649d3953, - 0x68d3c050, - 0x12800000, - 0xb03290b0, - 0x64537000, - 0xc122c101, - 0xc1016456, - 0x6456c0c2, - 0x649d8253, - 0x90b012c0, - 0x7000b032, - 0xc2726453, - 0x6456c081, - 0xc111c122, - 0xc0026456, - 0x6456c111, - 0xc331c062, - 0xc3626456, - 0x6456c111, - 0xc111c302, - 0x82536456, - 0x649d3953, - 0x645bc3e2, - 0x40fc2211, - 0xc881c242, - 0xc2526456, - 0x6456c111, - 0xcee1c272, - 0xc2026456, - 0x6456c881, - 0xc801c202, - 0xc0b06456, - 0x70006910, - 0xc2426453, - 0x6456c801, - 0xc011c252, - 0xc2726456, - 0x6456c0e1, - 0xc101c002, - 0xc0626456, - 0x6456c301, - 0xc101c122, - 0xc3626456, - 0x6456c101, - 0xc101c302, - 0x82536456, - 0x7000649d, - 0x3162c102, - 0x80a0c001, - 0x41361e00, - 0x61381a10, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006938, - 0x82d092e0, - 0x453f2200, - 0x7000b2c0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xb0608081, - 0x8092a050, - 0x92f1eff0, - 0x653e9302, - 0x45782241, - 0xc1f18080, - 0x16300410, - 0x14011101, - 0x618b6c01, - 0x618d618c, - 0x618f618e, - 0x61916190, - 0x61956193, - 0x61996197, - 0x62736270, - 0xc0f28091, - 0x31210421, - 0x2a428082, - 0x16321412, - 0x14211101, - 0x61a66c01, - 0x61ac61c7, - 0x61a66273, - 0x61ac61c7, - 0x619b6273, - 0x619b619b, - 0x619b619b, - 0x64ac619b, - 0x64d9619b, - 0x64e6619b, - 0x6512619b, - 0x652e619b, - 0x8082619b, - 0x92f2dfe0, - 0xb0b0653e, - 0xb0b161a2, - 0x72057306, - 0x6158b030, - 0x653ecfd0, - 0xc003c284, - 0x6468c3c0, - 0x91507890, - 0x31107860, - 0x14107861, - 0x78509200, - 0x78613140, - 0x31400010, - 0x00107871, - 0x78b09210, - 0x78819260, - 0x78309221, - 0x78413140, - 0x92300010, - 0x91f0c010, - 0xa054619b, - 0x225080f0, - 0x804045cf, - 0x46662200, - 0xc80061c7, - 0x81599160, - 0x8091b050, - 0x462e2241, - 0x653ecfc0, - 0x31828212, - 0x39423982, - 0x64771028, - 0x12f18212, - 0x102f0412, - 0x142f311f, - 0x1420c140, - 0x396d6f0d, - 0xc3f410de, - 0xc082044e, - 0x002e3182, - 0xc0a2396d, - 0x002d3182, - 0x398a821a, - 0x31808220, - 0xc00b3980, - 0x78ac180b, - 0x39408230, - 0xc0111002, - 0xc0103001, - 0x18021801, - 0x00213182, - 0x919126c1, - 0xb013b003, - 0xb053b063, - 0x14398203, - 0x22018041, - 0x81b44666, - 0x81d591c4, - 0x1cb51895, - 0x1cc54e1c, - 0x91654a54, - 0x221080f0, - 0x622c420c, - 0xb110913d, - 0xb110913e, - 0x920f9165, - 0x14f98159, - 0x10bc18ab, - 0x225080f0, - 0x221041c7, - 0x620c462c, - 0x653ecfb0, - 0x8230b063, - 0xc0f21000, - 0x10020420, - 0x3001c011, - 0x1801c010, - 0x31821802, - 0x26c10021, - 0x91919191, - 0xb003b013, - 0xb053b063, - 0xb054b064, - 0x80417100, - 0x46662201, - 0xb064b063, - 0x225080f0, - 0x81b141c7, - 0x81d191c1, - 0x91611891, - 0x6244b031, - 0x31828212, - 0x39423982, - 0x64771028, - 0x82058159, - 0x82201459, - 0x180bc00b, - 0xc08078ac, - 0xb0637100, - 0x620c6a62, - 0x81628201, - 0x3d823182, - 0x92f1efa0, - 0x653e9302, - 0x619ba003, - 0x647780a2, - 0xb050619b, - 0x619b7100 -}; - -PATCH_FUN_SPEC void rf_patch_rfe_ble(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 315; i++) { - HWREG(RFC_RFERAM_BASE + 4 * i) = patchBleRfe[i]; - } -#else - const uint32_t *pS = patchBleRfe; - volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 39; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; -#endif -} - -#endif diff --git a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_rfe_genfsk.h b/third_party/ti/devices/cc26x0/rf_patches/rf_patch_rfe_genfsk.h deleted file mode 100644 index 7b3c6b4dc..000000000 --- a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_rfe_genfsk.h +++ /dev/null @@ -1,545 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_rfe_genfsk.h -* Revised: $Date: 2017-05-04 12:39:32 +0200 (Thu, 04 May 2017) $ -* Revision: $Revision: 17776 $ -* -* Description: RF core patch for CC26x0 Generic FSK -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - - -#ifndef _RF_PATCH_RFE_GENFSK_H -#define _RF_PATCH_RFE_GENFSK_H - -#include -#include "../inc/hw_types.h" - -#ifndef RFE_PATCH_TYPE -#define RFE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_RFERAM_BASE -#define RFC_RFERAM_BASE 0x2100C000 -#endif - -#ifndef RFE_PATCH_MODE -#define RFE_PATCH_MODE 0 -#endif - -RFE_PATCH_TYPE patchGenfskRfe[431] = { - 0x000061a9, - 0x1307147f, - 0x00080053, - 0x1f2e24f1, - 0x0ab03f13, - 0xff07003f, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x0008000f, - 0x003f0000, - 0x00400000, - 0x0000003f, - 0x00680004, - 0x00dc000e, - 0x00430006, - 0x0005001a, - 0x00000000, - 0x00000002, - 0x0000003f, - 0x00040000, - 0x000000c0, - 0x00c00004, - 0x00070000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x404f2241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x685b1614, - 0x10257000, - 0x9100c050, - 0xc0c0c3f4, - 0x6f031420, - 0x04411031, - 0x22f08250, - 0x26514070, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x643f7000, - 0x1031c052, - 0x31610631, - 0x644202c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006442, - 0x659d658e, - 0x8220c088, - 0x39803950, - 0x40a31e00, - 0x3001c041, - 0x1a181418, - 0x8230c089, - 0x39803960, - 0x40ad1e00, - 0x3001c041, - 0x1a191419, - 0x9136643c, - 0x9134b110, - 0xb054b110, - 0xa0547100, - 0x80f0b064, - 0x40b32200, - 0x90b01240, - 0x8253b032, - 0x39533953, - 0x643f6489, - 0xc122c111, - 0xc1706442, - 0xc11168c6, - 0x6442c0c2, - 0x68cbc170, - 0x9100c050, - 0x92987227, - 0x16141615, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0xb270b051, - 0x72276576, - 0xb2709299, - 0x10731062, - 0x8231c3f0, - 0x39213121, - 0x101b3981, - 0xc0e26576, - 0x82603182, - 0x39803180, - 0xb0610002, - 0x91327100, - 0xa051b110, - 0x7227b061, - 0x68f7c230, - 0x12800000, - 0xb03290b0, - 0xc0507000, - 0x72279100, - 0x10629299, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0xb270b051, - 0x72276582, - 0xb2709298, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0x6582101a, - 0xb061a051, - 0xc0b07227, - 0x643f691c, - 0xc122c101, - 0xc1016442, - 0x6442c0c2, - 0x643c1a15, - 0xb1109135, - 0x64898253, - 0x90b012c0, - 0x7000b032, - 0xc272643f, - 0x6442c081, - 0xc111c122, - 0xc0026442, - 0x6442c111, - 0xc331c062, - 0xc3626442, - 0x6442c111, - 0xc111c302, - 0x82536442, - 0x64893953, - 0x6447c3e2, - 0x41442211, - 0xc881c242, - 0xc2526442, - 0x6442c111, - 0xcee1c272, - 0xc2026442, - 0x6442c881, - 0xc801c202, - 0xc0b06442, - 0x70006958, - 0xc242643f, - 0x6442c801, - 0xc011c252, - 0xc2726442, - 0x6442c0e1, - 0xc101c002, - 0xc0626442, - 0x6442c301, - 0xc101c122, - 0xc3626442, - 0x6442c101, - 0xc101c302, - 0x82536442, - 0x70006489, - 0x7100b061, - 0x1c231412, - 0x91334d7e, - 0x7000b110, - 0xb1109132, - 0x70006976, - 0x7100b061, - 0x1c321813, - 0x9132498a, - 0x7000b110, - 0xb1109133, - 0x70006982, - 0x6447c0c2, - 0xc0c21015, - 0x64471612, - 0x14153141, - 0x3180c0c0, - 0x10541405, - 0x040478b0, - 0xc0e67000, - 0x82613186, - 0x0401cc00, - 0x10671416, - 0xc3f08261, - 0x14170401, - 0x73067000, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0x22418092, - 0x808045c9, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61dd61dc, - 0x61df61de, - 0x61e161e0, - 0x61e461e2, - 0x61e861e6, - 0x633961ea, - 0x8091633c, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x621161f3, - 0x633c61f9, - 0x621161f3, - 0x633c61f9, - 0x61eb61eb, - 0x61eb61eb, - 0x61eb61eb, - 0x61eb6498, - 0x61eb64fd, - 0x61eb652e, - 0x61eb655a, - 0x121061eb, - 0x720e90b0, - 0x72057306, - 0x90301210, - 0xcff061ad, - 0xc1d4673f, - 0xc3c0c003, - 0x78406454, - 0x78609150, - 0x78709210, - 0x78809220, - 0x78909230, - 0x78a09240, - 0x78509260, - 0x783091f0, - 0x82109190, - 0x06f03940, - 0x31101001, - 0x92001410, - 0xa0bc61eb, - 0xa054a0e2, - 0x225080f0, - 0x8040461b, - 0x472e2200, - 0xa0406213, - 0x318d822d, - 0x8210398d, - 0x0410c0f1, - 0x821a1009, - 0x041a394a, - 0x39808210, - 0x100e0410, - 0x10bc10ab, - 0x646310c2, - 0xcfe07229, - 0xb013673f, - 0x66cdb003, - 0xb050b053, - 0xb064b054, - 0x66abb013, - 0x22e08210, - 0x66b4463e, - 0x80417100, - 0x472e2201, - 0x221080f0, - 0x22f04651, - 0xb064471b, - 0x423e2231, - 0x66d3b063, - 0x22e08210, - 0x6676463e, - 0xb064623e, - 0x318f816f, - 0xdfd03d8f, - 0x673f92ff, - 0x80417100, - 0x472e2201, - 0x80f0b064, - 0x426b2250, - 0x8211b063, - 0x466622c1, - 0x670866d3, - 0x22d18211, - 0x66764658, - 0x81616258, - 0x31818172, - 0x31823d81, - 0xefc03d82, - 0x930292f1, - 0x6211673f, - 0x91c081b0, - 0x829781d3, - 0x18d3a290, - 0x0bf34e85, - 0x1ce31613, - 0x91c34aaa, - 0x143b81e3, - 0x1cba6296, - 0x1e234691, - 0x1ce34a91, - 0xb2904e91, - 0x42912207, - 0x1a1ba290, - 0x1ce3629c, - 0x91c34aaa, - 0x183b81e3, - 0x4ea61cab, - 0x4aa81c9b, - 0x42aa1cbc, - 0x821010b2, - 0x42a322d0, - 0x221080f0, - 0x646346aa, - 0x62aa66ab, - 0x629a10ab, - 0x629a109b, - 0x82307000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6aae, - 0x7000b0e0, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4ac41c12, - 0xb032b0e2, - 0x673fcfb0, - 0x1421c7f1, - 0xc8124ec8, - 0x91729162, - 0xb0e1b031, - 0x12087000, - 0xc800c006, - 0x91709160, - 0x82017000, - 0x91c081b0, - 0x181081d0, - 0x18108151, - 0x80e11406, - 0x31828242, - 0x1c203d82, - 0xb0e24ae7, - 0x46eb2221, - 0xcfa0b032, - 0x2221673f, - 0xa0e242eb, - 0x8231b032, - 0xc0f03941, - 0x1e010401, - 0x161842f9, - 0x3010c010, - 0x47071c08, - 0x3c101060, - 0xc7f11006, - 0x4efd1461, - 0x9166c816, - 0x31818171, - 0x1c163d81, - 0x91764b04, - 0xc006b031, - 0x70001208, - 0x31818161, - 0x82403d81, - 0x18013980, - 0x4b1a1cf1, - 0x80b01401, - 0x471a22c0, - 0xb033b0bc, - 0x92f1ef90, - 0x673f930f, - 0xa0037000, - 0xb064b063, - 0x655ab0ef, - 0x80407100, - 0x472e2200, - 0x652eb064, - 0x7100a0ef, - 0x22008040, - 0xb064472e, - 0x623eb003, - 0x81628201, - 0x3d823182, - 0x92f1ef80, - 0x673f9302, - 0x655aa003, - 0x80a261eb, - 0x61eb6463, - 0x7100b050, - 0x92e061eb, - 0x220082d0, - 0xb2c04740, - 0x80a07000, - 0x435c22f0, - 0xc102b030, - 0xc0013162, - 0x1e0080a0, - 0x22f04355, - 0xf5d04356, - 0x39603160, - 0x10206356, - 0x6f131a10, - 0x16116e23, - 0x6b571612, - 0x00007000 -}; - -PATCH_FUN_SPEC void rf_patch_rfe_genfsk(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 431; i++) { - HWREG(RFC_RFERAM_BASE + 4 * i) = patchGenfskRfe[i]; - } -#else - const uint32_t *pS = patchGenfskRfe; - volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 53; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; -#endif -} - -#endif diff --git a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee_s.h b/third_party/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee_s.h deleted file mode 100644 index 7a012bc60..000000000 --- a/third_party/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee_s.h +++ /dev/null @@ -1,403 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_rfe_ieee_s.h -* Revised: $Date: 2017-08-24 11:43:33 +0200 (Thu, 24 Aug 2017) $ -* Revision: $Revision: 17889 $ -* -* Description: RF core patch for CC26x0 IEEE 802.15.4 Single Ended Output -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - - -#ifndef _RF_PATCH_RFE_IEEE_S_H -#define _RF_PATCH_RFE_IEEE_S_H - -#include -#include "../inc/hw_types.h" - -#ifndef RFE_PATCH_TYPE -#define RFE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_RFERAM_BASE -#define RFC_RFERAM_BASE 0x2100C000 -#endif - -#ifndef RFE_PATCH_MODE -#define RFE_PATCH_MODE 0 -#endif - -RFE_PATCH_TYPE patchZigbeeXsIsRfe[304] = { - 0x00006154, - 0x07f7177f, - 0x004507ff, - 0x0000000f, - 0x002e0004, - 0x0000003f, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x00000000, - 0x000f0000, - 0x00000008, - 0x0000003f, - 0x003f0040, - 0x00040000, - 0x000e0068, - 0x000600dc, - 0x001a0043, - 0x00000005, - 0x00020000, - 0x00000000, - 0x00000000, - 0x00c00004, - 0x00040000, - 0x000000c0, - 0x00000007, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x40632241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x686f1614, - 0x10257000, - 0x9100c050, - 0xc140c3f4, - 0x6f031420, - 0x04411031, - 0x22f08250, - 0x26514084, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x64537000, - 0x1031c052, - 0x31610631, - 0x645602c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006456, - 0x9101c051, - 0xc0e2cc01, - 0x64536456, - 0xc0c2c111, - 0xb0546456, - 0xa0547100, - 0x80f0b064, - 0x40b52200, - 0xc122c111, - 0xc0516456, - 0xc0e29101, - 0x82603182, - 0x91320002, - 0xc300b110, - 0x645368c8, - 0x90b01240, - 0xc300b032, - 0xc24068ce, - 0x128068d0, - 0xb03290b0, - 0x64537000, - 0xc122c101, - 0xc1016456, - 0x6456c0c2, - 0x649d8253, - 0x90b012c0, - 0x7000b032, - 0xc2726453, - 0x6456c081, - 0xc111c122, - 0xc0026456, - 0x6456c111, - 0xc331c062, - 0xc3626456, - 0x6456c111, - 0xc111c302, - 0x82536456, - 0x649d3953, - 0x645bc3e2, - 0x40f82211, - 0xc881c242, - 0xc2526456, - 0x6456c111, - 0xcee1c272, - 0xc2026456, - 0x6456c881, - 0xc801c202, - 0xc0b06456, - 0x7000690c, - 0xc2426453, - 0x6456c801, - 0xc011c252, - 0xc2726456, - 0x6456c0e1, - 0xc101c002, - 0xc0626456, - 0x6456c301, - 0xc101c122, - 0xc3626456, - 0x6456c101, - 0xc101c302, - 0x82536456, - 0x7000649d, - 0x3162c102, - 0x80a0c001, - 0x41321e00, - 0x61341a10, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006934, - 0x82d092e0, - 0x453b2200, - 0x7000b2c0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xb0608081, - 0x8092a050, - 0x92f1ef90, - 0x653a9302, - 0x45782241, - 0xc1f18080, - 0x16300410, - 0x14011101, - 0x61896c01, - 0x618b618a, - 0x618d618c, - 0x618f618e, - 0x61936191, - 0x61976195, - 0x625d625a, - 0x31218091, - 0x2a428082, - 0x16321412, - 0x14211101, - 0x61a76c01, - 0x61ad61c1, - 0x61a7625d, - 0x61ad61c1, - 0x6199625d, - 0x61996199, - 0x61996199, - 0x64ac6199, - 0x64d56199, - 0x64e26199, - 0x650e6199, - 0x652a6199, - 0x80826199, - 0x92f2df80, - 0x1210653a, - 0x61a290b0, - 0x90b01220, - 0x72057306, - 0x90301210, - 0xcf706158, - 0xc284653a, - 0xc3c0c003, - 0x78506468, - 0x78609150, - 0x78613110, - 0x92001410, - 0x31407880, - 0x00107861, - 0x78713140, - 0x92100010, - 0x92207890, - 0x926078a0, - 0xa0546199, - 0x225080f0, - 0x804045c9, - 0x46502200, - 0xcf6061c1, - 0x821e653a, - 0x06f910e9, - 0x10ea394e, - 0x10ac06fa, - 0x06fe394e, - 0x647710c2, - 0x10cb822d, - 0x91907820, - 0xb013661b, - 0xb063b053, - 0xb054b050, - 0xb003b064, - 0x225080f0, - 0x710041c1, - 0x22018041, - 0x22414650, - 0xb06441ec, - 0x81b0b063, - 0x81df91c0, - 0x220080f0, - 0x8090464e, - 0x464e2240, - 0x18d310f3, - 0x0bf34e01, - 0x1ce31613, - 0x91c34a4e, - 0x143b81e3, - 0x1ce36206, - 0x91c34a4e, - 0x183b81e3, - 0x4e171cab, - 0x4a191c9b, - 0x424e1cbc, - 0x10b210bc, - 0x662b6477, - 0xb063662b, - 0xb0637100, - 0xb0637100, - 0x10ab61e2, - 0x109b620a, - 0x7837620a, - 0x18707840, - 0xc0011a10, - 0x16176e71, - 0x78376a20, - 0xc0061208, - 0x9160c800, - 0x10007000, - 0x10f01000, - 0x18108201, - 0x6d716d71, - 0x14061816, - 0x16176e70, - 0x1c177841, - 0x78374638, - 0x1e881618, - 0x1060464b, - 0x81513930, - 0x80f11810, - 0x41c12251, - 0x81719160, - 0x3d813181, - 0x4a491c10, - 0xb0319170, - 0x70001278, - 0x10001000, - 0x61e2662b, - 0x81628201, - 0x3d823182, - 0x92f1ef50, - 0x653a9302, - 0x6199a003, - 0x647780a2, - 0xb0506199, - 0x61997100 -}; - -PATCH_FUN_SPEC void rf_patch_rfe_ieee_s(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 304; i++) { - HWREG(RFC_RFERAM_BASE + 4 * i) = patchZigbeeXsIsRfe[i]; - } -#else - const uint32_t *pS = patchZigbeeXsIsRfe; - volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 38; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); -#endif -} - -#endif diff --git a/third_party/ti/devices/cc26x0/rom/driverlib.c b/third_party/ti/devices/cc26x0/rom/driverlib.c deleted file mode 100644 index e8bebee39..000000000 --- a/third_party/ti/devices/cc26x0/rom/driverlib.c +++ /dev/null @@ -1,7823 +0,0 @@ -//##### AUTO GENERATED FILE...DO NOT EDIT ##### -// -// This file is autogenerated from the project definition -// and module includes defined in the 'APITable.xls' -// -//##### AUTO GENERATED FILE...DO NOT EDIT ##### -#undef DEBUG -#include "lib_src/hw_ioc.h" -#include "lib_src/hw_nvic.h" -#include "lib_src/hw_gpio.h" -#include "lib_src/hw_flash.h" -#include "lib_src/hw_device.h" -#include "lib_src/hw_aux_tdc.h" -#include "lib_src/hw_ints.h" -#include "lib_src/hw_i2c.h" -#include "lib_src/hw_trng.h" -#include "lib_src/hw_gpt.h" -#include "lib_src/hw_uart.h" -#include "lib_src/hw_smph.h" -#include "lib_src/hw_aon_rtc.h" -#include "lib_src/hw_aon_wuc.h" -#include "lib_src/hw_vims.h" -#include "lib_src/hw_aon_event.h" -#include "lib_src/hw_memmap.h" -#include "lib_src/hw_aon_ioc.h" -#include "lib_src/hw_aux_wuc.h" -#include "lib_src/hw_sysctl.h" -#include "lib_src/hw_udma.h" -#include "lib_src/hw_ssi.h" -#include "lib_src/hw_aux_sce.h" -#include "lib_src/hw_aon_sysctl.h" -#include "lib_src/hw_factory_cfg.h" -#include "lib_src/hw_types.h" -#include "lib_src/hw_ddi.h" -#include "lib_src/hw_aux_timer.h" -#include "lib_src/hw_spis.h" -#include "lib_src/hw_prcm.h" -#include "lib_src/aon_event.h" -#include "lib_src/aon_ioc.h" -#include "lib_src/aon_rtc.h" -#include "lib_src/aon_wuc.h" -#include "lib_src/aux_ctrl.h" -#include "lib_src/aux_tdc.h" -#include "lib_src/aux_timer.h" -#include "lib_src/aux_wuc.h" -#include "lib_src/ddi.h" -#include "lib_src/flash.h" -#include "lib_src/i2c.h" -#include "lib_src/interrupt.h" -#include "lib_src/ioc.h" -#include "lib_src/prcm.h" -#include "lib_src/smph.h" -#include "lib_src/spis.h" -#include "lib_src/ssi.h" -#include "lib_src/timer.h" -#include "lib_src/trng.h" -#include "lib_src/uart.h" -#include "lib_src/udma.h" -#include "lib_src/vims.h" -#include "lib_src/cpu.h" -#include "lib_src/gpio.h" -#include "lib_src/debug.h" -// -// Include interrupt functions for based ROM code -// -//***************************************************************************** -// -//! Disable all external interrupts -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) -uint32_t __attribute__((naked)) -CPUcpsid(void) -{ - uint32_t ui32Ret; - - // - // Read PRIMASK and disable interrupts - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " bx lr\n" - : "=r"(ui32Ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ui32Ret); -} -#endif -#if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN) -uint32_t -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - mrs r0, PRIMASK; - cpsid i; - bx lr -} -#endif -#if defined(__TI_COMPILER_VERSION__) -uint32_t -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -//! Enable all external interrupts -// -//***************************************************************************** -#if defined(codered) || defined(gcc) || defined(sourcerygxx) - uint32_t __attribute__((naked)) -CPUcpsie(void) -{ - uint32_t ui32Ret; - - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " bx lr\n" - : "=r"(ui32Ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ui32Ret); -} -#endif -#if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN) - uint32_t -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - mrs r0, PRIMASK; - cpsie i; - bx lr -} -#endif -#if defined(__TI_COMPILER_VERSION__) - uint32_t -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif -//! \\addtogroup aon_event_api -//! @{ -//***************************************************************************** -// -//! Select event source for the specified MCU wakeup programmable event -// -//***************************************************************************** -void -AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) -{ - uint32_t ui32Ctrl; - - // - // Check the arguments. - // - ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); - ASSERT(ui32EventSrc <= AON_EVENT_NULL); - - ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); - - if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) - { - ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU0_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU0_EV_S; - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) - { - ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU1_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU1_EV_S; - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) - { - ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU2_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU2_EV_S; - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) - { - ui32Ctrl &= ~(AON_EVENT_MCUWUSEL_WU3_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_MCUWUSEL_WU3_EV_S; - } - - HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = ui32Ctrl; -} -//***************************************************************************** -// -//! Get event source for the specified MCU wakeup programmable event -// -//***************************************************************************** -uint32_t -AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) -{ - uint32_t ui32EventSrc; - - // - // Check the arguments. - // - ASSERT((ui32MCUWUEvent == AON_EVENT_MCU_WU0) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU1) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU2) || - (ui32MCUWUEvent == AON_EVENT_MCU_WU3)); - - ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL); - - if(ui32MCUWUEvent == AON_EVENT_MCU_WU0) - { - return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU0_EV_M) >> - AON_EVENT_MCUWUSEL_WU0_EV_S); - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU1) - { - return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU1_EV_M) >> - AON_EVENT_MCUWUSEL_WU1_EV_S); - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU2) - { - return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU2_EV_M) >> - AON_EVENT_MCUWUSEL_WU2_EV_S); - } - else if(ui32MCUWUEvent == AON_EVENT_MCU_WU3) - { - return((ui32EventSrc & AON_EVENT_MCUWUSEL_WU3_EV_M) >> - AON_EVENT_MCUWUSEL_WU3_EV_S); - } - - // - // Should never get to this statement, but suppress warning. - // - ASSERT(0); - return(0); -} -//***************************************************************************** -// -//! Select event source for the specified AUX wakeup programmable event -// -//***************************************************************************** -void -AONEventAuxWakeUpSet(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc) -{ - uint32_t ui32Ctrl; - - // - // Check the arguments. - // - ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || - (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || - (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); - ASSERT(ui32EventSrc <= AON_EVENT_NULL); - - ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); - - if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) - { - ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU0_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU0_EV_S; - } - else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) - { - ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU1_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU1_EV_S; - } - else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) - { - ui32Ctrl &= ~(AON_EVENT_AUXWUSEL_WU2_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_AUXWUSEL_WU2_EV_S; - } - - HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL) = ui32Ctrl; -} -//***************************************************************************** -// -//! Get event source for the specified AUX wakeup programmable event -// -//***************************************************************************** -uint32_t -AONEventAuxWakeUpGet(uint32_t ui32AUXWUEvent) -{ - uint32_t ui32EventSrc; - - // - // Check the arguments. - // - ASSERT((ui32AUXWUEvent == AON_EVENT_AUX_WU0) || - (ui32AUXWUEvent == AON_EVENT_AUX_WU1) || - (ui32AUXWUEvent == AON_EVENT_AUX_WU2)); - - ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL); - - if(ui32AUXWUEvent == AON_EVENT_AUX_WU0) - { - return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU0_EV_M) >> - AON_EVENT_AUXWUSEL_WU0_EV_S); - } - else if(ui32AUXWUEvent == AON_EVENT_AUX_WU1) - { - return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU1_EV_M) >> - AON_EVENT_AUXWUSEL_WU1_EV_S); - } - else if(ui32AUXWUEvent == AON_EVENT_AUX_WU2) - { - return((ui32EventSrc & AON_EVENT_AUXWUSEL_WU2_EV_M) >> - AON_EVENT_AUXWUSEL_WU2_EV_S); - } - - // - // Should never get to this statement, but suppress warning. - // - ASSERT(0); - return(0); -} -//***************************************************************************** -// -//! Select event source for the specified programmable event forwarded to the -//! MCU event fabric -// -//***************************************************************************** -void -AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) -{ - uint32_t ui32Ctrl; - - // - // Check the arguments. - // - ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); - ASSERT(ui32EventSrc <= AON_EVENT_NULL); - - ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); - - if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) - { - ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) - { - ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) - { - ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; - } - - HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; -} -//***************************************************************************** -// -//! Get source for the specified programmable event forwarded to the MCU event -//! fabric. -// -//***************************************************************************** -uint32_t -AONEventMcuGet(uint32_t ui32MCUEvent) -{ - uint32_t ui32EventSrc; - - // - // Check the arguments. - // - ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); - - ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); - - if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) - { - return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> - AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) - { - return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> - AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) - { - return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> - AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); - } - - // - // Should never get to this statement, but supress warning. - // - ASSERT(0); - return(0); -} -//! @} -//! \\addtogroup aon_ioc_api -//! @{ -//***************************************************************************** -// -//! Setup the drive strength for all IOs on the chip -// -//***************************************************************************** -void -AONIOCDriveStrengthSet(uint32_t ui32LowDrvStr, uint32_t ui32MedDrvStr, - uint32_t ui32MaxDrvStr) -{ - ASSERT((ui32LowDrvStr == AONIOC_DRV_STR5_7_14) || - (ui32LowDrvStr == AONIOC_DRV_STR5_10_20) || - (ui32LowDrvStr == AONIOC_DRV_STR7_14_28) || - (ui32LowDrvStr == AONIOC_DRV_STR10_20_40) || - (ui32LowDrvStr == AONIOC_DRV_STR14_28_56) || - (ui32LowDrvStr == AONIOC_DRV_STR20_40_80) || - (ui32LowDrvStr == AONIOC_DRV_STR28_56_112) || - (ui32LowDrvStr == AONIOC_DRV_STR40_80_112)); - ASSERT((ui32MedDrvStr == AONIOC_DRV_STR5_7_14) || - (ui32MedDrvStr == AONIOC_DRV_STR5_10_20) || - (ui32MedDrvStr == AONIOC_DRV_STR7_14_28) || - (ui32MedDrvStr == AONIOC_DRV_STR10_20_40) || - (ui32MedDrvStr == AONIOC_DRV_STR14_28_56) || - (ui32MedDrvStr == AONIOC_DRV_STR20_40_80) || - (ui32MedDrvStr == AONIOC_DRV_STR28_56_112) || - (ui32MedDrvStr == AONIOC_DRV_STR40_80_112)); - ASSERT((ui32MaxDrvStr == AONIOC_DRV_STR5_7_14) || - (ui32MaxDrvStr == AONIOC_DRV_STR5_10_20) || - (ui32MaxDrvStr == AONIOC_DRV_STR7_14_28) || - (ui32MaxDrvStr == AONIOC_DRV_STR10_20_40) || - (ui32MaxDrvStr == AONIOC_DRV_STR14_28_56) || - (ui32MaxDrvStr == AONIOC_DRV_STR20_40_80) || - (ui32MaxDrvStr == AONIOC_DRV_STR28_56_112) || - (ui32MaxDrvStr == AONIOC_DRV_STR40_80_112)); - - // - // Set the minimum drive strength. - // - HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMIN) = ui32LowDrvStr & - AON_IOC_IOSTRMIN_GRAY_CODE_M; - // - // Set the medium drive strength. - // - HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMED) = ui32MedDrvStr & - AON_IOC_IOSTRMED_GRAY_CODE_M; - // - // Set the maximum drive strength. - // - HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMAX) = ui32MaxDrvStr & - AON_IOC_IOSTRMAX_GRAY_CODE_M; - -} -//***************************************************************************** -// -//! Get a specific drive level setting for all IOs -// -//***************************************************************************** -uint32_t -AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) -{ - uint32_t ui32DrvStr; - - // - // Check the arguments. - // - ASSERT((ui32DriveLevel == AONIOC_MAX_DRIVE) || - (ui32DriveLevel == AONIOC_MED_DRIVE) || - (ui32DriveLevel == AONIOC_MIN_DRIVE)); - - // - // Get the specified drive strength level. - // - if(ui32DriveLevel == AONIOC_MAX_DRIVE) - { - ui32DrvStr = HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMAX); - } - else if(ui32DriveLevel == AONIOC_MED_DRIVE) - { - ui32DrvStr = HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMED); - } - else - { - ui32DrvStr = HWREG(AON_IOC_BASE + AON_IOC_O_IOSTRMIN); - } - - // - // Return the drive strength value. - // - return(ui32DrvStr); -} -//! @} -//! \\addtogroup aon_rtc_api -//! @{ -//***************************************************************************** -// -//! Check if the AON Real Time Clock is running. -// -//***************************************************************************** -uint32_t -AONRTCStatus(void) -{ - uint32_t ui32ChannelStatus; - uint32_t ui32RtcStatus; - - // - // Read out the status' - // - ui32ChannelStatus = HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL); - ui32RtcStatus = HWREG(AON_RTC_BASE + AON_RTC_O_CTL) & - AON_RTC_CTL_EN ? AON_RTC_ACTIVE : 0; - - // - // Return the status - // - ui32RtcStatus |= (ui32ChannelStatus & AON_RTC_CHCTL_CH2_EN ? - AON_RTC_CH2 : 0) | - (ui32ChannelStatus & AON_RTC_CHCTL_CH1_EN ? - AON_RTC_CH1 : 0) | - (ui32ChannelStatus & AON_RTC_CHCTL_CH0_EN ? - AON_RTC_CH0 : 0); - return ui32RtcStatus; -} -//***************************************************************************** -// -//! Clear event from a specified channel -// -//***************************************************************************** -void -AONRTCEventClear(uint32_t ui32Channel) -{ - // - // Check the arguments. - // - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0; - } - else if(ui32Channel & AON_RTC_CH1) - { - HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1; - } - else if(ui32Channel & AON_RTC_CH2) - { - HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH2; - } -} -//***************************************************************************** -// -//! Get event status for a specified channel -// -//***************************************************************************** -bool -AONRTCEventGet(uint32_t ui32Channel) -{ - // - // Check the arguments. - // - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - return ((HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) & - AON_RTC_EVFLAGS_CH0) ? true : false); - } - else if(ui32Channel & AON_RTC_CH1) - { - return ((HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) & - AON_RTC_EVFLAGS_CH1) ? true : false); - } - else if(ui32Channel & AON_RTC_CH2) - { - return ((HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) & - AON_RTC_EVFLAGS_CH2) ? true : false); - } - - return(false); -} -//***************************************************************************** -// -//! Set operational mode of channel 1 -// -//***************************************************************************** -void -AONRTCModeCh1Set(uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) || - (ui32Mode == AON_RTC_MODE_CH1_COMPARE)); - - if(ui32Mode == AON_RTC_MODE_CH1_CAPTURE) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH1_CAPT_EN; - } - else if(ui32Mode == AON_RTC_MODE_CH1_COMPARE) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH1_CAPT_EN); - } -} -//***************************************************************************** -// -//! Get operational mode of channel 1 -// -//***************************************************************************** -uint32_t -AONRTCModeCh1Get(void) -{ - if(HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) & AON_RTC_CHCTL_CH1_CAPT_EN) - { - return(AON_RTC_MODE_CH1_CAPTURE); - } - else - { - return(AON_RTC_MODE_CH1_COMPARE); - } -} -//***************************************************************************** -// -//! Set operational mode of channel 2 -// -//***************************************************************************** -void -AONRTCModeCh2Set(uint32_t ui32Mode) -{ - // - // Check the arguments. - // - ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) || - (ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE)); - - if(ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH2_CONT_EN; - } - else if(ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH2_CONT_EN); - } -} -//***************************************************************************** -// -//! Get operational mode of channel 2 -// -//***************************************************************************** -uint32_t -AONRTCModeCh2Get(void) -{ - if(HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) & AON_RTC_CHCTL_CH2_CONT_EN) - { - return(AON_RTC_MODE_CH2_CONTINUOUS); - } - else - { - return(AON_RTC_MODE_CH2_NORMALCOMPARE); - } -} -//***************************************************************************** -// -//! Enable event operation for the specified channel -// -//***************************************************************************** -void -AONRTCChannelEnable(uint32_t ui32Channel) -{ - // - // Check the arguments. - // - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH0_EN; - } - else if(ui32Channel & AON_RTC_CH1) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH1_EN; - } - else if(ui32Channel & AON_RTC_CH2) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) |= AON_RTC_CHCTL_CH2_EN; - } -} -//***************************************************************************** -// -//! Disable event operation for the specified channel -// -//***************************************************************************** -void -AONRTCChannelDisable(uint32_t ui32Channel) -{ - // - // Check the arguments. - // - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH0_EN); - } - else if(ui32Channel & AON_RTC_CH1) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH1_EN); - } - else if(ui32Channel & AON_RTC_CH2) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) &= ~(AON_RTC_CHCTL_CH2_EN); - } -} -//***************************************************************************** -// -//! Set the compare value for the given channel -// -//***************************************************************************** -void -AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue) -{ - // - // Check the arguments. - // - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP) = ui32CompValue; - } - else if(ui32Channel & AON_RTC_CH1) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP) = ui32CompValue; - } - else if(ui32Channel & AON_RTC_CH2) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP) = ui32CompValue; - } -} -//***************************************************************************** -// -//! Get the compare value for the given channel -// -//***************************************************************************** -uint32_t -AONRTCCompareValueGet(uint32_t ui32Channel) -{ - // - // Check the arguments - // - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - return(HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP)); - } - else if(ui32Channel & AON_RTC_CH1) - { - return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP)); - } - else if(ui32Channel & AON_RTC_CH2) - { - return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP)); - } - // - // Should never return from here! - // - return(0); -} -//***************************************************************************** -// -//! Get the current value of the RTC counter in a format compatible to the -//! compare registers. -// -//***************************************************************************** -uint32_t -AONRTCCurrentCompareValueGet(void) -{ - uint32_t ui32CurrentSec0; - uint32_t ui32CurrentSec1; - uint32_t ui32CurrentSubSec; - - // - // Read the integer part of the RTC counter - // - ui32CurrentSec0 = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); - - // - // Read the fractional part of the RTC counter. Make sure the fractional - // part has not rolled over and incremented the integer part. - // - do { - ui32CurrentSubSec = HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC); - ui32CurrentSec1 = ui32CurrentSec0; - ui32CurrentSec0 = HWREG(AON_RTC_BASE + AON_RTC_O_SEC); - } while(ui32CurrentSec0 != ui32CurrentSec1); - - // - // Return the RTC value in the correct format - // - return ((ui32CurrentSec0 << 16) | (ui32CurrentSubSec >> 16)); -} -//! @} -//! \\addtogroup aon_wuc_api -//! @{ -//***************************************************************************** -// -//! Set the clock source for the AUX domain -// -//***************************************************************************** -void -AONWUCAuxClockConfigSet(uint32_t ui32ClkSrc, uint32_t ui32ClkDiv) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT((ui32ClkSrc == AONWUC_CLOCK_SRC_HF) || - (ui32ClkSrc == AONWUC_CLOCK_SRC_MF) || - (ui32ClkSrc == AONWUC_CLOCK_SRC_LF)); - ASSERT((ui32ClkDiv == AUX_CLOCK_DIV_2) || - (ui32ClkDiv == AUX_CLOCK_DIV_4) || - (ui32ClkDiv == AUX_CLOCK_DIV_8) || - (ui32ClkDiv == AUX_CLOCK_DIV_16) || - (ui32ClkDiv == AUX_CLOCK_DIV_32) || - (ui32ClkDiv == AUX_CLOCK_DIV_64) || - (ui32ClkDiv == AUX_CLOCK_DIV_128) || - (ui32ClkDiv == AUX_CLOCK_DIV_256) || - (ui32ClkDiv == AUX_CLOCK_DIV_UNUSED)); - - // - // Configure the clock for the AUX domain. - // - ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK); - - // - // Check if we need to update the clock division factor - // - if(ui32ClkDiv != AUX_CLOCK_DIV_UNUSED) - { - ui32Reg = (ui32Reg & ~AON_WUC_AUXCLK_SCLK_HF_DIV_M) | ui32ClkDiv; - HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg; - - // If switching to a HF clocks source for AUX it is necessary to - // synchronize the write on the AON RTC to ensure the clock division is - // updated before requesting the clock source - // - if(ui32ClkSrc == AONWUC_CLOCK_SRC_HF) - { - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); - } - } - - // - // Configure the clock for the AUX domain. - // - ui32Reg &= ~AON_WUC_AUXCLK_SRC_M; - if(ui32ClkSrc == AONWUC_CLOCK_SRC_HF) - { - ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_HF; - } - else if(ui32ClkSrc == AONWUC_CLOCK_SRC_MF) - { - ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_MF; - } - else if(ui32ClkSrc == AONWUC_CLOCK_SRC_LF) - { - ui32Reg |= AON_WUC_AUXCLK_SRC_SCLK_LF; - } - HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg; -} -//***************************************************************************** -// -//! Configure the rentention on the AUX SRAM -// -//***************************************************************************** -void -AONWUCAuxSRamConfig(uint32_t ui32Retention) -{ - - // - // Enable/disable the retention. - // - if(ui32Retention) - { - HWREG(AON_WUC_BASE + AON_WUC_O_AUXCFG) |= AON_WUC_AUXCFG_SRAM_RET_EN; - } - else - { - HWREG(AON_WUC_BASE + AON_WUC_O_AUXCFG) &= ~AON_WUC_AUXCFG_SRAM_RET_EN; - } -} -//***************************************************************************** -// -//! Control the wake up procedure of the AUX domain -// -//***************************************************************************** -void -AONWUCAuxWakeupEvent(uint32_t ui32Mode) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT((ui32Mode == AONWUC_AUX_WAKEUP_SWEVT) || - (ui32Mode == AONWUC_AUX_WAKEUP) || - (ui32Mode == AONWUC_AUX_ALLOW_SLEEP)); - - // - // Wake up the AUX domain. - // - ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL); - - if(ui32Mode == AONWUC_AUX_ALLOW_SLEEP) - { - ui32Reg &= ~AON_WUC_AUXCTL_AUX_FORCE_ON; - } - else - { - ui32Reg |= ui32Mode; - } - - HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) = ui32Reg; -} -//***************************************************************************** -// -//! Reset the AUX domain -// -//***************************************************************************** -void -AONWUCAuxReset(void) -{ - // - // Reset the AUX domain. - // - HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) |= AON_WUC_AUXCTL_RESET_REQ; - - // - // Wait for AON interface to be in sync. - // - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); - - // - // De-assert reset on the AUX domain. - // - HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) &= ~AON_WUC_AUXCTL_RESET_REQ; - - // - // Wait for AON interface to be in sync. - // - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); -} -//***************************************************************************** -// -//! Configure the recharge controller -// -//***************************************************************************** -void -AONWUCRechargeCtrlConfigSet(bool bAdaptEnable, uint32_t ui32AdaptRate, - uint32_t ui32Period, uint32_t ui32MaxPeriod) -{ - uint32_t ui32Shift; - uint32_t ui32C1; - uint32_t ui32C2; - uint32_t ui32Reg; - uint32_t ui32Exponent; - uint32_t ui32MaxExponent; - uint32_t ui32Mantissa; - uint32_t ui32MaxMantissa; - - // - // Check the arguments. - // - ASSERT((ui32AdaptRate >= RC_RATE_MIN) || - (ui32AdaptRate <= RC_RATE_MAX)); - - ui32C1 = 0; - ui32C2 = 0; - ui32Shift = 9; - - // - // Clear the previous values. - // - ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); - ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M | - AON_WUC_RECHARGECFG_ADAPTIVE_EN_M | AON_WUC_RECHARGECFG_PER_M_M | - AON_WUC_RECHARGECFG_PER_E_M | AON_WUC_RECHARGECFG_C1_M | - AON_WUC_RECHARGECFG_C2_M); - - // - // Check if the recharge controller adaption algorithm should be active. - // - if(bAdaptEnable) - { - // - // Calculate adaption parameters. - // - while(ui32AdaptRate) - { - if(ui32AdaptRate & (1 << ui32Shift)) - { - if(!ui32C1) - { - ui32C1 = ui32Shift; - } - else if(!ui32C2) - { - if((2 * ui32AdaptRate) > ((uint32_t)(3 << ui32Shift))) - { - ui32C2 = ui32Shift + 1; - } - else - { - ui32C2 = ui32Shift; - } - } - else - { - break; - } - ui32AdaptRate &= ~(1 << ui32Shift); - } - ui32Shift--; - } - if(!ui32C2) - { - ui32C2 = ui32C1 = ui32C1 - 1; - } - - ui32C1 = 10 - ui32C1; - ui32C2 = 10 - ui32C2; - - // - // Update the recharge rate parameters. - // - ui32Reg &= ~(AON_WUC_RECHARGECFG_C1_M | AON_WUC_RECHARGECFG_C2_M); - ui32Reg |= (ui32C1 << AON_WUC_RECHARGECFG_C1_S) | - (ui32C2 << AON_WUC_RECHARGECFG_C2_S) | - AON_WUC_RECHARGECFG_ADAPTIVE_EN_M; - } - - // - // Resolve the period into an exponent and mantissa. - // - ui32Period = (ui32Period >> 4); - ui32Exponent = 0; - while(ui32Period > (AON_WUC_RECHARGECFG_PER_M_M >> AON_WUC_RECHARGECFG_PER_M_S)) - { - ui32Period >>= 1; - ui32Exponent++; - } - ui32Mantissa = ui32Period; - - // - // Resolve the max period into an exponent and mantissa. - // - ui32MaxPeriod = (ui32MaxPeriod >> 4); - ui32MaxExponent = 0; - while(ui32MaxPeriod > (AON_WUC_RECHARGECFG_MAX_PER_M_M >> AON_WUC_RECHARGECFG_MAX_PER_M_S)) - { - ui32MaxPeriod >>= 1; - ui32MaxExponent++; - } - ui32MaxMantissa = ui32MaxPeriod; - - - // - // Configure the controller. - // - ui32Reg |= ((ui32MaxMantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | - (ui32MaxExponent << AON_WUC_RECHARGECFG_MAX_PER_E_S) | - (ui32Mantissa << AON_WUC_RECHARGECFG_PER_M_S) | - (ui32Exponent << AON_WUC_RECHARGECFG_PER_E_S)); - HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; - -} -//***************************************************************************** -// -//! Configure the interval for oscillator amplitude calibration -// -//***************************************************************************** -void -AONWUCOscConfig(uint32_t ui32Period) -{ - uint32_t ui32Mantissa; - uint32_t ui32Exponent; - uint32_t ui32Reg; - - // - // Resolve the period into a exponent and mantissa. - // - ui32Period = (ui32Period >> 4); - ui32Exponent = 0; - while(ui32Period > (AON_WUC_OSCCFG_PER_M_M >> AON_WUC_OSCCFG_PER_M_S)) - { - ui32Period >>= 1; - ui32Exponent++; - } - ui32Mantissa = ui32Period; - - // - // Update the period for the oscillator amplitude calibration. - // - HWREG(AON_WUC_BASE + AON_WUC_O_OSCCFG) = - (ui32Mantissa << AON_WUC_OSCCFG_PER_M_S) | - (ui32Exponent << AON_WUC_OSCCFG_PER_E_S); - - // - // Set the maximum reacharge period equal to the oscillator amplitude - // calibration period. - // - ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG); - ui32Reg &= ~(AON_WUC_RECHARGECFG_MAX_PER_M_M | AON_WUC_RECHARGECFG_MAX_PER_E_M); - ui32Reg |= ((ui32Mantissa << AON_WUC_RECHARGECFG_MAX_PER_M_S) | - (ui32Exponent << AON_WUC_RECHARGECFG_MAX_PER_E_S)); - - // - // Write the configuration. - // - HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG) = ui32Reg; -} -//! @} -//! \\addtogroup aux_ctrl_api -//! @{ -//***************************************************************************** -// -//! Load AUX controller Firmware into dedicated RAM -// -//***************************************************************************** -void -AUXCTRLImageLoad(uint16_t *pui16Image, uint32_t ui32StartAddr, - uint32_t ui32Size) -{ - uint16_t* pui16Src16; - uint16_t* pui16Dst16; - uint32_t ui32WordCnt; - - // - // Check the arguments. - // - ASSERT(ui32StartAddr < 512); - ASSERT(ui32Size <= 1024); - ASSERT((ui32Size / 2 + ui32StartAddr) <= 512); - - // - // Copy image to AUX RAM. - // - ui32WordCnt = (ui32Size >> 1); - pui16Src16 = pui16Image; - pui16Dst16 = (uint16_t*)(AUX_RAM_BASE + (ui32StartAddr << 1)); - - while(ui32WordCnt--) - { - *pui16Dst16++ = *pui16Src16++; - } -} -//! @} -//! \\addtogroup aux_tdc_api -//! @{ -//***************************************************************************** -// -//! Configure the operation of the AUX TDC -// -//***************************************************************************** -void -AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, - uint32_t ui32StopCondition) -{ - // - // Check the arguments. - // - ASSERT(AUXTDCBaseValid(ui32Base)); - - // - // Make sure the AUX TDC is in the idle state before changing the - // configuration. - // - while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) - { - } - - // - // Clear previous results. - // - HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; - - // - // Change the configuration. - // - HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; -} -//***************************************************************************** -// -//! Check if the AUX TDC is done measuring -// -//***************************************************************************** -uint32_t -AUXTDCMeasurementDone(uint32_t ui32Base) -{ - uint32_t ui32Reg; - uint32_t ui32Status; - - // - // Check the arguments. - // - ASSERT(AUXTDCBaseValid(ui32Base)); - - // - // Check if the AUX TDC is done measuring. - // - ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); - if(ui32Reg & AUX_TDC_STAT_DONE) - { - ui32Status = AUX_TDC_DONE; - } - else if(ui32Reg & AUX_TDC_STAT_SAT) - { - ui32Status = AUX_TDC_TIMEOUT; - } - else - { - ui32Status = AUX_TDC_BUSY; - } - - // - // Return the status. - // - return (ui32Status); -} -//! @} -//! \\addtogroup aux_timer_api -//! @{ -//***************************************************************************** -// -//! Configure AUX timer -// -//***************************************************************************** -void -AUXTimerConfigure(uint32_t ui32Timer, uint32_t ui32Config) -{ - uint32_t ui32Val; - - // - // Check the arguments. - // - ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || - (ui32Timer == AUX_TIMER_BOTH)); - ASSERT(((ui32Config & 0x0000000F) == AUX_TIMER_CFG_ONE_SHOT) || - ((ui32Config & 0x0000000F) == AUX_TIMER_CFG_PERIODIC) || - ((ui32Config & 0x0000000F) == AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT) || - ((ui32Config & 0x0000000F) == AUX_TIMER_CFG_PERIODIC_EDGE_COUNT) || - ((ui32Config & 0x000000F0) == AUX_TIMER_CFG_RISING_EDGE) || - ((ui32Config & 0x000000F0) == AUX_TIMER_CFG_FALLING_EDGE) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_RTC_EVENT) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_CMP_A) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_CMP_B) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_TDCDONE) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_ADC_DONE) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO0) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO1) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO2) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO3) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO4) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO5) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO6) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO7) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO8) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO9) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO10) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO11) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO12) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO13) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO14) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_AIO15) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_ACLK_REF) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_MCU_EVENT) || - ((ui32Config & 0x00000F00) == AUX_TIMER_CFG_TICK_SRC_ADC_IRQ)); - - // - // Configure Timer 0. - // - if(ui32Timer & AUX_TIMER_0) - { - // - // Stop timer 0. - // - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; - - // - // Set mode. - // - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); - ui32Val &= ~(AUX_TIMER_T0CFG_MODE_M | AUX_TIMER_T0CFG_RELOAD_M); - ui32Val |= (ui32Config & (AUX_TIMER_T0CFG_MODE_M | - AUX_TIMER_T0CFG_RELOAD_M)); - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; - - // - // If edge counter, set rising/falling edge and tick source. - // - if(ui32Config & AUX_TIMER_T0CFG_MODE_M) - { - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); - ui32Val &= ~(AUX_TIMER_T0CFG_TICK_SRC_POL_M | - AUX_TIMER_T0CFG_TICK_SRC_M); - - // - // Set edge polarity. - // - if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) - { - ui32Val |= AUX_TIMER_T0CFG_TICK_SRC_POL; - } - - // - // Set tick source. - // - ui32Val |= ((ui32Config & 0x00000F00) >> 8) << - AUX_TIMER_T0CFG_TICK_SRC_S; - - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; - } - } - - // - // Configure Timer 1. - // - if(ui32Timer & AUX_TIMER_1) - { - // - // Stop timer 1. - // - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; - - // - // Set mode. - // - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); - ui32Val &= ~(AUX_TIMER_T1CFG_MODE_M | AUX_TIMER_T1CFG_RELOAD_M); - ui32Val |= ((ui32Config) & (AUX_TIMER_T1CFG_MODE_M | - AUX_TIMER_T1CFG_RELOAD_M)); - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; - - // - // If edge counter, set rising/falling edge and tick source. - // - if(ui32Config & AUX_TIMER_T1CFG_MODE) - { - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); - ui32Val &= ~(AUX_TIMER_T1CFG_TICK_SRC_POL_M | - AUX_TIMER_T1CFG_TICK_SRC_M); - - // - // Set edge polarity. - // - if(ui32Config & AUX_TIMER_CFG_FALLING_EDGE) - { - ui32Val |= AUX_TIMER_T1CFG_TICK_SRC_POL; - } - - // - // Set tick source. - // - ui32Val |= ((ui32Config & 0x00000F00) >> 8) << - AUX_TIMER_T1CFG_TICK_SRC_S; - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; - } - } -} -//***************************************************************************** -// -//! Start AUX timer -// -//***************************************************************************** -void -AUXTimerStart(uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT((ui32Timer == AUX_TIMER_0) || - (ui32Timer == AUX_TIMER_1) || - (ui32Timer == AUX_TIMER_BOTH)); - - if(ui32Timer & AUX_TIMER_0) - { - // - // Start timer 0. - // - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = AUX_TIMER_T0CTL_EN; - } - if(ui32Timer & AUX_TIMER_1) - { - // - // Start timer 1. - // - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = AUX_TIMER_T1CTL_EN; - } -} -//***************************************************************************** -// -//! Stop AUX timer -// -//***************************************************************************** -void -AUXTimerStop(uint32_t ui32Timer) -{ - // - // Check the arguments. - // - ASSERT((ui32Timer == AUX_TIMER_0) || - (ui32Timer == AUX_TIMER_1) || - (ui32Timer == AUX_TIMER_BOTH)); - - if(ui32Timer & AUX_TIMER_0) - { - // - // Stop timer 0. - // - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CTL) = 0; - } - if(ui32Timer & AUX_TIMER_1) - { - // - // Stop timer 1. - // - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CTL) = 0; - } -} -//***************************************************************************** -// -//! Set AUX timer prescale value -// -//***************************************************************************** -void -AUXTimerPrescaleSet(uint32_t ui32Timer, uint32_t ui32PrescaleDiv) -{ - uint32_t ui32Val; - - // - // Check the arguments. - // - ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1) || - (ui32Timer == AUX_TIMER_BOTH)); - ASSERT(ui32PrescaleDiv <= AUX_TIMER_PRESCALE_DIV_32768); - - if(ui32Timer & AUX_TIMER_0) - { - // - // Set timer 0 prescale value. - // - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG); - ui32Val &= ~AUX_TIMER_T0CFG_PRE_M; - ui32Val |= ui32PrescaleDiv << AUX_TIMER_T0CFG_PRE_S; - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG) = ui32Val; - } - if(ui32Timer & AUX_TIMER_1) - { - // - // Set timer 1 prescale value. - // - ui32Val = HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG); - ui32Val &= ~AUX_TIMER_T1CFG_PRE_M; - ui32Val |= ui32PrescaleDiv << AUX_TIMER_T1CFG_PRE_S; - HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T1CFG) = ui32Val; - } -} -//***************************************************************************** -// -//! Get AUX timer prescale value -// -//***************************************************************************** -uint32_t -AUXTimerPrescaleGet(uint32_t ui32Timer) -{ - uint32_t ui32Val; - uint32_t ui32PrescaleDiv; - - // - // Check the arguments. - // - ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); - - ui32Val = (HWREG(AUX_TIMER_BASE + AUX_TIMER_O_T0CFG)); - if(ui32Timer & AUX_TIMER_0) - { - // - // Get timer 0 prescale value. - // - ui32PrescaleDiv = - (ui32Val & AUX_TIMER_T0CFG_PRE_M) >> AUX_TIMER_T0CFG_PRE_S; - } - else - { - // - // Get timer 1 prescale value. - // - ui32PrescaleDiv = - (ui32Val & AUX_TIMER_T1CFG_PRE_M) >> AUX_TIMER_T1CFG_PRE_S; - } - - return(ui32PrescaleDiv); -} -//! @} -//! \\addtogroup aux_wuc_api -//! @{ -//**************************************************************************** -// -//! Enable clocks for peripherals in the AUX domain -// -//**************************************************************************** -void -AUXWUCClockEnable(uint32_t ui32Clocks) -{ - // - // Check the arguments. - // - ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || - (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || - (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || - (ui32Clocks & AUX_WUC_SOC_CLOCK) || - (ui32Clocks & AUX_WUC_TIMER_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || - (ui32Clocks & AUX_WUC_SMPH_CLOCK) || - (ui32Clocks & AUX_WUC_TDC_CLOCK) || - (ui32Clocks & AUX_WUC_ADC_CLOCK) || - (ui32Clocks & AUX_WUC_REF_CLOCK)); - - // - // Enable some of the clocks in the clock register. - // - HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) |= (ui32Clocks & - AUX_WUC_MODCLK_MASK); - - // - // Check the rest. - // - if(ui32Clocks & AUX_WUC_ADC_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) = - AUX_WUC_ADCCLKCTL_REQ; - } - if(ui32Clocks & AUX_WUC_TDC_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) = - AUX_WUC_TDCCLKCTL_REQ; - } - if(ui32Clocks & AUX_WUC_REF_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = - AUX_WUC_REFCLKCTL_REQ; - } -} -//**************************************************************************** -// -//! Disable clocks for peripherals in the AUX domain -// -//**************************************************************************** -void -AUXWUCClockDisable(uint32_t ui32Clocks) -{ - // - // Check the arguments. - // - ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || - (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || - (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || - (ui32Clocks & AUX_WUC_SOC_CLOCK) || - (ui32Clocks & AUX_WUC_TIMER_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || - (ui32Clocks & AUX_WUC_SMPH_CLOCK) || - (ui32Clocks & AUX_WUC_TDC_CLOCK) || - (ui32Clocks & AUX_WUC_ADC_CLOCK) || - (ui32Clocks & AUX_WUC_REF_CLOCK)); - - // - // Disable some of the clocks in the clock register. - // - HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0) &= ~(ui32Clocks & - AUX_WUC_MODCLK_MASK); - - // - // Check the rest. - // - if(ui32Clocks & AUX_WUC_ADC_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL) &= - ~AUX_WUC_ADCCLKCTL_REQ; - } - if(ui32Clocks & AUX_WUC_TDC_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) &= - ~AUX_WUC_TDCCLKCTL_REQ; - } - if(ui32Clocks & AUX_WUC_REF_CLOCK) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) &= - ~AUX_WUC_REFCLKCTL_REQ; - } -} -//**************************************************************************** -// -//! Get the status of a clock -// -//**************************************************************************** -uint32_t -AUXWUCClockStatus(uint32_t ui32Clocks) -{ - bool bClockStatus; - uint32_t ui32ClockRegister; - - // - // Check the arguments. - // - ASSERT((ui32Clocks & AUX_WUC_ADI_CLOCK) || - (ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) || - (ui32Clocks & AUX_WUC_TDCIF_CLOCK) || - (ui32Clocks & AUX_WUC_SOC_CLOCK) || - (ui32Clocks & AUX_WUC_TIMER_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO0_CLOCK) || - (ui32Clocks & AUX_WUC_AIODIO1_CLOCK) || - (ui32Clocks & AUX_WUC_SMPH_CLOCK) || - (ui32Clocks & AUX_WUC_TDC_CLOCK) || - (ui32Clocks & AUX_WUC_ADC_CLOCK) || - (ui32Clocks & AUX_WUC_REF_CLOCK)); - - bClockStatus = true; - - // - // Read the status registers. - // - ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN0); - - // - // Check all requested clocks - // - if(ui32Clocks & AUX_WUC_ADI_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_AUX_ADI ? - true : false); - } - if(ui32Clocks & AUX_WUC_OSCCTRL_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_OSCCTL ? - true : false); - } - if(ui32Clocks & AUX_WUC_TDCIF_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_TDC ? - true : false); - } - if(ui32Clocks & AUX_WUC_SOC_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_SOC ? - true : false); - } - if(ui32Clocks & AUX_WUC_TIMER_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_TIMER ? - true : false); - } - if(ui32Clocks & AUX_WUC_AIODIO0_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_AIODIO0 ? - true : false); - } - if(ui32Clocks & AUX_WUC_AIODIO1_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_AIODIO1 ? - true : false); - } - if(ui32Clocks & AUX_WUC_SMPH_CLOCK) - { - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_MODCLKEN0_SMPH ? - true : false); - } - if(ui32Clocks & AUX_WUC_ADC_CLOCK) - { - ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_ADCCLKCTL); - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_ADCCLKCTL_ACK ? - true : false); - } - if(ui32Clocks & AUX_WUC_TDC_CLOCK) - { - ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL); - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_TDCCLKCTL_ACK ? - true : false); - } - if(ui32Clocks & AUX_WUC_REF_CLOCK) - { - ui32ClockRegister = HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL); - bClockStatus = bClockStatus && (ui32ClockRegister & - AUX_WUC_REFCLKCTL_ACK ? - true : false); - } - - // - // Return the clock status. - // - return bClockStatus ? AUX_WUC_CLOCK_READY : AUX_WUC_CLOCK_OFF; -} -//**************************************************************************** -// -//! Control the power to the AUX domain -// -//**************************************************************************** -void -AUXWUCPowerCtrl(uint32_t ui32PowerMode) -{ - // - // Check the arguments. - // - ASSERT((ui32PowerMode == AUX_WUC_POWER_OFF) || - (ui32PowerMode == AUX_WUC_POWER_DOWN) || - (ui32PowerMode == AUX_WUC_POWER_ACTIVE)); - - // - // Power on/off. - // - if(ui32PowerMode == AUX_WUC_POWER_OFF) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = AUX_WUC_PWROFFREQ_REQ; - HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; - return; - } - else - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_PWROFFREQ) = 0x0; - } - - // - // Power down/active. - // - if(ui32PowerMode == AUX_WUC_POWER_DOWN) - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = - AUX_WUC_PWRDWNREQ_REQ; - HWREG(AUX_WUC_BASE + AUX_WUC_O_MCUBUSCTL) = AUX_WUC_MCUBUSCTL_DISCONNECT_REQ; - } - else - { - HWREG(AUX_WUC_BASE + AUX_WUC_O_PWRDWNREQ) = 0x0; - } -} -//! @} -//! \\addtogroup ddi_api -//! @{ -//***************************************************************************** -// -//! Write a single bit using a 16-bit maskable write -// -//***************************************************************************** -void -DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Mask, uint32_t ui32WrData) -{ - uint32_t ui32RegAddr; - uint32_t ui32Data; - - // - // Check the arguments. - // - ASSERT(DDIBaseValid(ui32Base)); - ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF))); - ASSERT(!(ui32WrData & 0xFFFF0000)); - - // - // DDI 16-bit target is on 32-bit boundary so double offset - // - ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; - - // - // Adjust for target bit in high half of the word. - // - if(ui32Mask & 0xFFFF0000) - { - ui32RegAddr += 4; - ui32Mask >>= 16; - } - - // - // Write mask if data is not zero (to set mask bit), else write '0'. - // - ui32Data = ui32WrData ? ui32Mask : 0x0; - - // - // Update the register. - // - HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32Data; -} -//***************************************************************************** -// -//! Write a bitfield via the DDI using 16-bit maskable write -// -//***************************************************************************** -void -DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Mask, uint32_t ui32Shift, - uint16_t ui32Data) -{ - uint32_t ui32RegAddr; - uint32_t ui32WrData; - - // - // Check the arguments. - // - ASSERT(DDIBaseValid(ui32Base)); - - // - // 16-bit target is on 32-bit boundary so double offset. - // - ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; - - // - // Adjust for target bit in high half of the word. - // - if(ui32Shift >= 16) - { - ui32Shift = ui32Shift - 16; - ui32RegAddr += 4; - ui32Mask = ui32Mask >> 16; - } - - // - // Shift data in to position. - // - ui32WrData = ui32Data << ui32Shift; - - // - // Write data. - // - HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32WrData; -} -//***************************************************************************** -// -//! Read a bit via the DDI using 16-bit READ. -// -//***************************************************************************** -uint16_t -DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask) -{ - uint32_t ui32RegAddr; - uint16_t ui16Data; - - // - // Check the arguments. - // - ASSERT(DDIBaseValid(ui32Base)); - - // - // Calculate the address of the register. - // - ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; - - // - // Adjust for target bit in high half of the word. - // - if(ui32Mask & 0xFFFF0000) - { - ui32RegAddr += 2; - ui32Mask = ui32Mask >> 16; - } - - // - // Read a halfword on the DDI interface. - // - ui16Data = HWREGH(ui32RegAddr); - - // - // Mask data. - // - ui16Data = ui16Data & ui32Mask; - - // - // Return masked data. - // - return(ui16Data); -} -//***************************************************************************** -// -//! Read a bitfield via the DDI using 16-bit read. -// -//***************************************************************************** -uint16_t -DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Mask, uint32_t ui32Shift) -{ - uint32_t ui32RegAddr; - uint16_t ui16Data; - - // - // Check the arguments. - // - ASSERT(DDIBaseValid(ui32Base)); - - // - // Calculate the register address. - // - ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; - - // - // Adjust for target bit in high half of the word. - // - if(ui32Shift >= 16) - { - ui32Shift = ui32Shift - 16; - ui32RegAddr += 2; - ui32Mask = ui32Mask >> 16; - } - - // - // Read the register. - // - ui16Data = HWREGH(ui32RegAddr); - - // - // Mask data and shift into place. - // - ui16Data &= ui32Mask; - ui16Data >>= ui32Shift; - - // - // Return data. - // - return(ui16Data); -} -//! @} -//! \\addtogroup flash_api -//! @{ -//***************************************************************************** -// -// Default values for security control in customer configuration area in flash -// top sector. TBD! It must be asured that layout corresponds with CCFG. -// -//***************************************************************************** -const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xC5, 0xFF, 0xFF, 0xFF, - 0xC5, 0xC5, 0xC5, 0xFF, - 0xC5, 0xC5, 0xC5, 0xFF - }; - -//***************************************************************************** -// -// Function prototypes for static functions -// -//***************************************************************************** -static void IssueFsmCommand(tFlashStateCommandsType eCommand); -static void EnableSectorsForWrite(void); -static uint32_t ScaleCycleValues(uint32_t ui32SpecifiedTiming, - uint32_t ui32ScaleValue); -static void SetWriteMode(void); -static void SetReadMode(void); -static void TrimForWrite(void); -//***************************************************************************** -// -//! \internal -//! Issues a command to the Flash State Machine. -//! -//! \param eCommand specifies the FSM command. -//! -//! Issues a command to the Flash State Machine. -//! -//! \return None -// -//***************************************************************************** -static void -IssueFsmCommand(tFlashStateCommandsType eCommand) -{ - // - // Check the arguments. - // - ASSERT( - eCommand == FAPI_ERASE_SECTOR || eCommand == FAPI_ERASE_BANK || - eCommand == FAPI_VALIDATE_SECTOR || eCommand == FAPI_CLEAR_STATUS || - eCommand == FAPI_PROGRAM_RESUME || eCommand == FAPI_ERASE_RESUME || - eCommand == FAPI_CLEAR_MORE || eCommand == FAPI_PROGRAM_SECTOR || - eCommand == FAPI_PROGRAM_DATA || eCommand == FAPI_ERASE_OTP); - - // - // Enable write to FSM register. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - - // - // Issue FSM command. - // - HWREG(FLASH_BASE + FLASH_O_FSM_CMD) = eCommand; - - // - // Start command execute. - // - HWREG(FLASH_BASE + FLASH_O_FSM_EXECUTE) = FLASH_CMD_EXEC; - - // - // Disable write to FSM register. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; -} - -//***************************************************************************** -// -//! \internal -//! Enables all sectors for erase and programming on the active bank. -//! -//! This function disables the idle reading power reduction mode, selects the -//! flash bank and enables all sectors for erase and programming on the active -//! bank. -//! Sectores may be protected from programming depending on the value of the -//! FLASH_O_FSM_BSLPx registers. -//! Sectores may be protected from erase depending on the value of the -//! FLASH_O_FSM_BSLEx registers. Additional sector erase protection is set by -//! the FLASH_O_FSM_SECTOR1 register. -//! -//! \return None -// -//***************************************************************************** -static void -EnableSectorsForWrite(void) -{ - // - // Trim flash module for program/erase operation. - // - TrimForWrite(); - - // - // Configure flash to write mode - // - SetWriteMode(); - - // - // Select flash bank. - // - HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; - - // - // Disable Level 1 Protection. - // - HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; - - // - // Enable all sectors for erase and programming. - // - HWREG(FLASH_BASE + FLASH_O_FBSE) = 0xFFFF; - - // - // Enable Level 1 Protection - // - HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; -} - -//***************************************************************************** -// -//! \internal -//! Trims the Flash Bank and Flash Pump for program/erase functionality -//! -//! This trimming will make it possible to perform erase and program operations -//! of the flash. Trim values are loaded from factory configuration area -//! (referred to as FCGF1). The trimming done by this function is valid until -//! reset of the flash module. -//! -//! Some registers shall be written with a value that is a number of FCLK -//! cycles. The trim values controlling these registers have a value of -//! number of half us. FCLK = SysClk / ((RWAIT+1) x 2). -//! In order to calculate the register value for these registers the -//! following calculation must be done: -//! -//! OtpValue SysClkMHz -//! -------- us OtpValue x --------- -//! 2 (RWAIT+1) -//! RegValue_in_no_of_clk_cycles = ----------------- = --------------------- -//! 1 4 -//! -------------- -//! SysClkMHz -//! ------------ -//! (RWAIT+1)x 2 -//! -//! This is equevivalent to: -//! -//! 16 x SysClkMHz -//! OtpValue x --------------- -//! (RWAIT+1) -//! RegValue_in_no_of_clk_cycles = ---------------------------- -//! 64 -//! -//! 16 x SysClkMHz -//! A scaling factor is set equal to: ui32FclkScale = -------------- -//! (RWAIT+1) -//! -//! which gives: -//! OtpValue x ui32FclkScale -//! RegValue_in_no_of_clk_cycles = ------------------------ -//! 64 -//! -//! \return None. -// -//***************************************************************************** -static void -TrimForWrite(void) -{ - uint32_t ui32Value; - uint32_t ui32TempVal; - uint32_t ui32FclkScale; - uint32_t ui32RWait; - - // - // Return if flash is already trimmed for program/erase operations. - // - if(HWREG(FLASH_BASE + FLASH_O_FWFLAG) & FW_WRT_TRIMMED) - { - return; - } - - //***********************************************************************// - // // - // Configure the FSM registers // - // // - //***********************************************************************// - - // - // Enable access to the FSM registers. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - - // - // Determine the scaling value to be used on timing related trim values. - // The scaling value is based on the flash module clock frequency and RWAIT - // - ui32RWait = (HWREG(FLASH_BASE + FLASH_O_FRDCTL) & - FLASH_FRDCTL_RWAIT_M) >> FLASH_FRDCTL_RWAIT_S; - ui32FclkScale = (16 * FLASH_MODULE_CLK_FREQ) / (ui32RWait + 1); - - // - // Configure Program puls width bits 15:0. - // (FCFG1 offset 0x188 bits 15:0). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_PROG_EP) & - FACTORY_CFG_FLASH_PROG_EP_PROGRAM_PW_M) >> - FACTORY_CFG_FLASH_PROG_EP_PROGRAM_PW_S; - - ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); - - HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) = - (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) & - ~FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M) | - ((ui32Value << FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S) & - FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M); - - // - // Configure Erase puls width bits 31:0. - // (FCFG1 offset 0x18C bits 31:0). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_ERA_PW) & - FACTORY_CFG_FLASH_ERA_PW_ERASE_PW_M) >> - FACTORY_CFG_FLASH_ERA_PW_ERASE_PW_S; - - ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); - - HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) = - (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) & - ~FLASH_FSM_ERA_PW_FSM_ERA_PW_M) | - ((ui32Value << FLASH_FSM_ERA_PW_FSM_ERA_PW_S) & - FLASH_FSM_ERA_PW_FSM_ERA_PW_M); - - - // - // Configure no of flash clock cycles from EXECUTEZ going low to the the - // verify data can be read in the program verify mode bits 7:0. - // (FCFG1 offset 0x174 bits 23:16). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_C_E_P_R) & - FACTORY_CFG_FLASH_C_E_P_R_PV_ACCESS_M) >> - FACTORY_CFG_FLASH_C_E_P_R_PV_ACCESS_S; - - ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); - - HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = - (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & - ~FLASH_FSM_EX_VAL_EXE_VALD_M) | - ((ui32Value << FLASH_FSM_EX_VAL_EXE_VALD_S) & - FLASH_FSM_EX_VAL_EXE_VALD_M); - - // - // Configure the number of flash clocks from the start of the Read mode at - // the end of the operations until the FSM clears the BUSY bit in FMSTAT. - // (FCFG1 offset 0x178 bits 23:16). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_P_R_PV) & - FACTORY_CFG_FLASH_P_R_PV_RH_M) >> - FACTORY_CFG_FLASH_P_R_PV_RH_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) = - (HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) & - ~FLASH_FSM_RD_H_RD_H_M) | - ((ui32Value << FLASH_FSM_RD_H_RD_H_S) & - FLASH_FSM_RD_H_RD_H_M); - - // - // Configure Program hold time - // (FCFG1 offset 0x178 bits 31:24). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_P_R_PV) & - FACTORY_CFG_FLASH_P_R_PV_PH_M) >> - FACTORY_CFG_FLASH_P_R_PV_PH_S; - - ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); - - HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) = - (HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) & - ~FLASH_FSM_P_OH_PGM_OH_M) | - ((ui32Value << FLASH_FSM_P_OH_PGM_OH_S) & - FLASH_FSM_P_OH_PGM_OH_M); - - // - // Configure Erase hold time - // (FCFG1 offset 0x17C bits 31:24). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_EH_SEQ) & - FACTORY_CFG_FLASH_EH_SEQ_EH_M) >> - FACTORY_CFG_FLASH_EH_SEQ_EH_S; - - ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); - - HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) = - (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) & - ~FLASH_FSM_ERA_OH_ERA_OH_M) | - ((ui32Value << FLASH_FSM_ERA_OH_ERA_OH_S) & - FLASH_FSM_ERA_OH_ERA_OH_M); - - // - // Configure Program verify row switch time - // (FCFG1 offset0x178 bits 15:8). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_P_R_PV) & - FACTORY_CFG_FLASH_P_R_PV_PVH_M) >> - FACTORY_CFG_FLASH_P_R_PV_PVH_S; - - ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); - - HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) = - (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) & - ~FLASH_FSM_PE_VH_PGM_VH_M) | - ((ui32Value << FLASH_FSM_PE_VH_PGM_VH_S) & - FLASH_FSM_PE_VH_PGM_VH_M); - - // - // Configure Program Operation Setup time - // (FCFG1 offset 0x170 bits 31:24). - // - ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & - FACTORY_CFG_FLASH_E_P_PSU_M) >> - FACTORY_CFG_FLASH_E_P_PSU_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = - (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & - ~FLASH_FSM_PE_OSU_PGM_OSU_M) | - ((ui32Value << FLASH_FSM_PE_OSU_PGM_OSU_S) & - FLASH_FSM_PE_OSU_PGM_OSU_M); - - // - // Configure Erase Operation Setup time - // (FCGF1 offset 0x170 bits 23:16). - // - ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & - FACTORY_CFG_FLASH_E_P_ESU_M) >> - FACTORY_CFG_FLASH_E_P_ESU_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = - (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & - ~FLASH_FSM_PE_OSU_ERA_OSU_M) | - ((ui32Value << FLASH_FSM_PE_OSU_ERA_OSU_S) & - FLASH_FSM_PE_OSU_ERA_OSU_M); - - // - // Confgure Program Verify Setup time - // (FCFG1 offset 0x170 bits 15:8). - // - ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & - FACTORY_CFG_FLASH_E_P_PVSU_M) >> - FACTORY_CFG_FLASH_E_P_PVSU_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = - (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & - ~FLASH_FSM_PE_VSU_PGM_VSU_M) | - ((ui32Value << FLASH_FSM_PE_VSU_PGM_VSU_S) & - FLASH_FSM_PE_VSU_PGM_VSU_M); - - // - // Configure Erase Verify Setup time - // (FCFG1 offset 0x170 bits 7:0). - // - ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_E_P) & - FACTORY_CFG_FLASH_E_P_EVSU_M) >> - FACTORY_CFG_FLASH_E_P_EVSU_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = - (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & - ~FLASH_FSM_PE_VSU_ERA_VSU_M) | - ((ui32Value << FLASH_FSM_PE_VSU_ERA_VSU_S) & - FLASH_FSM_PE_VSU_ERA_VSU_M); - - // - // Configure Addr to EXECUTEZ low setup time - // (FCFG1 offset 0x174 bits 15:12). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_C_E_P_R) & - FACTORY_CFG_FLASH_C_E_P_R_A_EXEZ_SETUP_M) >> - FACTORY_CFG_FLASH_C_E_P_R_A_EXEZ_SETUP_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) = - (HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) & - ~FLASH_FSM_CMP_VSU_ADD_EXZ_M) | - ((ui32Value << FLASH_FSM_CMP_VSU_ADD_EXZ_S) & - FLASH_FSM_CMP_VSU_ADD_EXZ_M); - - // - // Configure Voltage Status Count - // (FCFG1 offset 0x17C bits 15:12). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_EH_SEQ) & - FACTORY_CFG_FLASH_EH_SEQ_VSTAT_M) >> - FACTORY_CFG_FLASH_EH_SEQ_VSTAT_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) = - (HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) & - ~FLASH_FSM_VSTAT_VSTAT_CNT_M) | - ((ui32Value << FLASH_FSM_VSTAT_VSTAT_CNT_S) & - FLASH_FSM_VSTAT_VSTAT_CNT_M); - - // - // Configure Repeat Verify action setup - // (FCFG1 offset 0x174 bits 31:24). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_C_E_P_R) & - FACTORY_CFG_FLASH_C_E_P_R_RVSU_M) >> - FACTORY_CFG_FLASH_C_E_P_R_RVSU_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = - (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & - ~FLASH_FSM_EX_VAL_REP_VSU_M) | - ((ui32Value << FLASH_FSM_EX_VAL_REP_VSU_S) & - FLASH_FSM_EX_VAL_REP_VSU_M); - - // - // Configure Maximum Programming Pulses - // (FCFG1 offset 0x184 bits 15:0). - // - ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_PP) & - FACTORY_CFG_FLASH_PP_MAX_PP_M) >> - FACTORY_CFG_FLASH_PP_MAX_PP_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = - (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & - ~FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M) | - ((ui32Value << FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S) & - FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M); - - // - // Configure Beginning level for VHVCT used during erase modes - // (FCFG1 offset 0x180 bits 31:16). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_E) & - FACTORY_CFG_FLASH_VHV_E_VHV_E_START_M) >> - FACTORY_CFG_FLASH_VHV_E_VHV_E_START_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = - (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & - ~FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M) | - ((ui32Value << FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S) & - FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M); - - // - // Configure Maximum EC Level - // (FCFG1 offset 0x2B0 bits 21:18). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & - FACTORY_CFG_FLASH_OTP_DATA3_MAX_EC_LEVEL_M) >> - FACTORY_CFG_FLASH_OTP_DATA3_MAX_EC_LEVEL_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = - (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & - ~FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M) | - ((ui32Value << FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S) & - FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M); - - // - // Configure Maximum Erase Pulses - // (FCFG1 offset 0x188 bits 31:16). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_PROG_EP) & - FACTORY_CFG_FLASH_PROG_EP_MAX_EP_M) >> - FACTORY_CFG_FLASH_PROG_EP_MAX_EP_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = - (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & - ~FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M) | - ((ui32Value << FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S) & - FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M); - - // - // Configure the VHVCT Step Size. This is the number of erase pulses that - // must be completed for each level before the FSM increments the - // CUR_EC_LEVEL to the next higher level. Actual erase pulses per level - // equals (EC_STEP_SIZE +1). The stepping is only needed for the VHVCT - // voltage. - // (FCFG1 offset 0x2B0 bits 31:23). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & - FACTORY_CFG_FLASH_OTP_DATA3_EC_STEP_SIZE_M) >> - FACTORY_CFG_FLASH_OTP_DATA3_EC_STEP_SIZE_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) = - (HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) & - ~FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M) | - ((ui32Value << FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S) & - FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M); - - // - // Configure the hight of each EC step. This is the number of counts that - // the CUR_EC_LEVEL will increment when going to a new level. Actual count - // size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the VHVCT - // voltage. - // The read trim value is decremented by 1 before written to the register - // since actual counts equals (register value + 1). - // (FCFG1 offset 0x180 bits 15:0). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_E) & - FACTORY_CFG_FLASH_VHV_E_VHV_E_STEP_HIGHT_M) >> - FACTORY_CFG_FLASH_VHV_E_VHV_E_STEP_HIGHT_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_EC_STEP_HEIGHT) = ((ui32Value - 1) & - FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M); - - // - // Configure Precondition used in erase operations - // (FCFG1 offset 0x2B0 bit 22). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & - FACTORY_CFG_FLASH_OTP_DATA3_DO_PRECOND_M) >> - FACTORY_CFG_FLASH_OTP_DATA3_DO_PRECOND_S; - - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) = - (HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) & - ~FLASH_FSM_ST_MACHINE_DO_PRECOND_M) | - ((ui32Value << FLASH_FSM_ST_MACHINE_DO_PRECOND_S) & - FLASH_FSM_ST_MACHINE_DO_PRECOND_M); - - // - // Enable the recommended Good Time function. - // - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= - FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD; - - // - // Disable write access to FSM registers. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - - - //***********************************************************************// - // // - // Configure the voltage registers // - // // - //***********************************************************************// - - // - // Unlock voltage registers (0x2080 - 0x2098). - // - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - - // - // Configure voltage level for the specified pump voltage of high - // voltage supply input during erase operation VHVCT_E and the TRIM13_E - // (FCFG1 offset 0x190 bits[3:0] and bits[11:8]). - // - ui32TempVal = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV); - - ui32Value = ((ui32TempVal & FACTORY_CFG_FLASH_VHV_TRIM13_E_M)>> - FACTORY_CFG_FLASH_VHV_TRIM13_E_S) << FLASH_FVHVCT1_TRIM13_E_S; - ui32Value |= ((ui32TempVal & FACTORY_CFG_FLASH_VHV_VHV_E_M)>> - FACTORY_CFG_FLASH_VHV_VHV_E_S) << FLASH_FVHVCT1_VHVCT_E_S; - - HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & - ~(FLASH_FVHVCT1_TRIM13_E_M | FLASH_FVHVCT1_VHVCT_E_M)) | ui32Value; - - // - // Configure voltage level for the specified pump voltage of high voltage - // supply input during program verify operation VHVCT_PV and the TRIM13_PV - // (OTP offset 0x194 bits[19:16] and bits[27:24]). - // - ui32TempVal = - HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_PV); - - ui32Value = ((ui32TempVal & FACTORY_CFG_FLASH_VHV_PV_TRIM13_PV_M)>> - FACTORY_CFG_FLASH_VHV_PV_TRIM13_PV_S) << - FLASH_FVHVCT1_TRIM13_PV_S; - ui32Value |= ((ui32TempVal & FACTORY_CFG_FLASH_VHV_PV_VHV_PV_M)>> - FACTORY_CFG_FLASH_VHV_PV_VHV_PV_S) << - FLASH_FVHVCT1_VHVCT_PV_S; - - HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & - ~(FLASH_FVHVCT1_TRIM13_PV_M | FLASH_FVHVCT1_VHVCT_PV_M)) | ui32Value; - - // - // Configure voltage level for the specified pump voltage of high voltage - // supply input during program operation VHVCT_P and TRIM13_P - // (FCFG1 offset 0x190 bits[19:16] and bits[27:24]). - // - ui32TempVal = - HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV); - - ui32Value = ((ui32TempVal & FACTORY_CFG_FLASH_VHV_TRIM13_P_M)>> - FACTORY_CFG_FLASH_VHV_TRIM13_P_S) << FLASH_FVHVCT2_TRIM13_P_S; - ui32Value |= ((ui32TempVal & FACTORY_CFG_FLASH_VHV_VHV_P_M)>> - FACTORY_CFG_FLASH_VHV_VHV_P_S) << FLASH_FVHVCT2_VHVCT_P_S; - - HWREG(FLASH_BASE + FLASH_O_FVHVCT2) = - (HWREG(FLASH_BASE + FLASH_O_FVHVCT2) & - ~(FLASH_FVHVCT2_TRIM13_P_M | FLASH_FVHVCT2_VHVCT_P_M)) | ui32Value; - - // - // Configure voltage level for the specified pump voltage of wordline power - // supply for read mode - // (FCFG1 offset 0x198 Bits 15:8). - // - ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_V) & - FACTORY_CFG_FLASH_V_V_READ_M) >> - FACTORY_CFG_FLASH_V_V_READ_S; - - HWREG(FLASH_BASE + FLASH_O_FVREADCT) = - (HWREG(FLASH_BASE + FLASH_O_FVREADCT) & - ~FLASH_FVREADCT_VREADCT_M) | - ((ui32Value << FLASH_FVREADCT_VREADCT_S) & - FLASH_FVREADCT_VREADCT_M); - - // - // Configure the voltage level for the VCG 2.5 CT pump voltage - // (FCFG1 offset 0x194 bits 15:8). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_VHV_PV) & - FACTORY_CFG_FLASH_VHV_PV_VCG2P5_M) >> - FACTORY_CFG_FLASH_VHV_PV_VCG2P5_S; - - HWREG(FLASH_BASE + FLASH_O_FVNVCT) = - (HWREG(FLASH_BASE + FLASH_O_FVNVCT) & - ~FLASH_FVNVCT_VCG2P5CT_M) | - ((ui32Value << FLASH_FVNVCT_VCG2P5CT_S) & - FLASH_FVNVCT_VCG2P5CT_M); - - // - // Configure the voltage level for the specified pump voltage of high - // current power input during program operation - // (FCFG1 offset 0x198 bits 31:24). - // - ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_V) & - FACTORY_CFG_FLASH_V_VSL_P_M) >> - FACTORY_CFG_FLASH_V_VSL_P_S; - - HWREG(FLASH_BASE + FLASH_O_FVSLP) = - (HWREG(FLASH_BASE + FLASH_O_FVSLP) & - ~FLASH_FVSLP_VSL_P_M) | - ((ui32Value << FLASH_FVSLP_VSL_P_S) & - FLASH_FVSLP_VSL_P_M); - - // - // Configure the voltage level for the specified pump voltage of wordline - // power supply during programming operations - // (OTP offset 0x198 bits 23:16). - // - ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_V) & - FACTORY_CFG_FLASH_V_VWL_P_M) >> - FACTORY_CFG_FLASH_V_VWL_P_S; - - HWREG(FLASH_BASE + FLASH_O_FVWLCT) = - (HWREG(FLASH_BASE + FLASH_O_FVWLCT) & - ~FLASH_FVWLCT_VWLCT_P_M) | - ((ui32Value << FLASH_FVWLCT_VWLCT_P_S) & - FLASH_FVWLCT_VWLCT_P_M); - - // - // Configure the pump's TRIM_1P7 port pins. - // (FCFG1 offset 0x2B0 bits 17:16). - // - ui32Value = - (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA3) & - FACTORY_CFG_FLASH_OTP_DATA3_TRIM_1P7_M) >> - FACTORY_CFG_FLASH_OTP_DATA3_TRIM_1P7_S; - - HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = - (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & - ~FLASH_FSEQPMP_TRIM_1P7_M) | - ((ui32Value << FLASH_FSEQPMP_TRIM_1P7_S) & - FLASH_FSEQPMP_TRIM_1P7_M); - - // - // Lock the voltage registers. - // - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - - // - // Set trimmed flag. - // - HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; - HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_WRT_TRIMMED; - HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; -} - -//***************************************************************************** -// -//! \internal -//! Used to scale the TI OTP values based on the FClk scaling value. -//! -//! \param ui32SpecifiedTiming -//! \param ui32ScaleValue -//! -//! Used to scale the TI OTP values based on the FClk scaling value. -//! -//! \return Returns the scaled value -// -//***************************************************************************** -static uint32_t -ScaleCycleValues(uint32_t ui32SpecifiedTiming, uint32_t ui32ScaleValue) -{ - return((ui32SpecifiedTiming * ui32ScaleValue) >> 6); -} - -//***************************************************************************** -// -//! \internal -//! Used to set flash in read mode. -//! -//! Flash is configured with values loaded from OTP dependent on the current -//! regulator mode. -//! -//! \return None. -// -//***************************************************************************** -static void -SetReadMode(void) -{ - uint32_t ui32TrimValue; - uint32_t ui32Value; - - // - // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, - // VIN_AT_X and VIN_BY_PASS for read mode - // - if(HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) & - AON_SYSCTL_PWRCTL_EXT_REG_MODE) - { - // Select trim values for external regulator mode: - // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) - // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) - // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 - HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; - - ui32TrimValue = - HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); - - ui32Value = ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << - FLASH_CFG_STANDBY_MODE_SEL_S; - - ui32Value |= ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << - FLASH_CFG_STANDBY_PW_SEL_S; - - // Configure DIS_STANDBY (OTP offset 0x308 bit 4). - // Configure DIS_IDLE (OTP offset 0x308 bit 3). - ui32Value |= ((ui32TrimValue & - (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M | - FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >> - FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) << - FLASH_CFG_DIS_IDLE_S; - - HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & - ~(FLASH_CFG_STANDBY_MODE_SEL_M | - FLASH_CFG_STANDBY_PW_SEL_M | - FLASH_CFG_DIS_STANDBY_M | - FLASH_CFG_DIS_IDLE_M)) | ui32Value; - - // Check if sample and hold functionality is disabled. - if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) - { - // - // Wait for disabled sample and hold functionality to be stable. - // - while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) - { - } - } - - // Configure VIN_AT_X (OTP offset 0x308 bits 2:0) - ui32Value = ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << - FLASH_FSEQPMP_VIN_AT_X_S; - - // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. - // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise - // VIN_BY_PASS should be 1 - if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> - FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) - { - ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; - } - - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = - (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & - ~(FLASH_FSEQPMP_VIN_BY_PASS_M | - FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - } - else - { - // Select trim values for internal regulator mode: - // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) - // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) - // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 - HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; - - ui32TrimValue = - HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); - - ui32Value = ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << - FLASH_CFG_STANDBY_MODE_SEL_S; - - ui32Value |= ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << - FLASH_CFG_STANDBY_PW_SEL_S; - - // Configure DIS_STANDBY (OTP offset 0x308 bit 12). - // Configure DIS_IDLE (OTP offset 0x308 bit 11). - ui32Value |= ((ui32TrimValue & - (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M | - FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >> - FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) << - FLASH_CFG_DIS_IDLE_S; - - HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & - ~(FLASH_CFG_STANDBY_MODE_SEL_M | - FLASH_CFG_STANDBY_PW_SEL_M | - FLASH_CFG_DIS_STANDBY_M | - FLASH_CFG_DIS_IDLE_M)) | ui32Value; - - // Check if sample and hold functionality is disabled. - if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) - { - // - // Wait for disabled sample and hold functionality to be stable. - // - while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) - { - } - } - - // Configure VIN_AT_X (OTP offset 0x308 bits 10:8) - ui32Value = (((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << - FLASH_FSEQPMP_VIN_AT_X_S); - - // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. - // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise - // VIN_BY_PASS should be 1 - if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> - FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) - { - ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; - } - - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = - (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & - ~(FLASH_FSEQPMP_VIN_BY_PASS_M | - FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - } -} - -//***************************************************************************** -// -//! \internal -//! Used to set flash in write mode. -//! -//! Flash is configured with values loaded from OTP dependent on the current -//! regulator mode. -//! -//! \return None. -// -//***************************************************************************** -static void -SetWriteMode(void) -{ - uint32_t ui32TrimValue; - uint32_t ui32Value; - - // - // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, - // VIN_AT_X and VIN_BY_PASS for program/erase mode - // - if(HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) & - AON_SYSCTL_PWRCTL_EXT_REG_MODE) - { - // Select trim values for external regulator mode: - // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 23) - // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 22:21) - // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 - HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; - - ui32TrimValue = - HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); - - ui32Value = ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S) << - FLASH_CFG_STANDBY_MODE_SEL_S; - - ui32Value |= ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S) << - FLASH_CFG_STANDBY_PW_SEL_S; - - // Configure DIS_STANDBY (OTP offset 0x308 bit 20). - // Configure DIS_IDLE (OTP offset 0x308 bit 19). - ui32Value |= ((ui32TrimValue & - (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M | - FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M)) >> - FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S) << - FLASH_CFG_DIS_IDLE_S; - - HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & - ~(FLASH_CFG_STANDBY_MODE_SEL_M | - FLASH_CFG_STANDBY_PW_SEL_M | - FLASH_CFG_DIS_STANDBY_M | - FLASH_CFG_DIS_IDLE_M)) | ui32Value; - - // Check if sample and hold functionality is disabled. - if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) - { - // - // Wait for disabled sample and hold functionality to be stable. - // - while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) - { - } - } - - // Configure VIN_AT_X (OTP offset 0x308 bits 18:16) - ui32Value = ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S) << - FLASH_FSEQPMP_VIN_AT_X_S; - - // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. - // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise - // VIN_BY_PASS should be 1 - if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> - FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) - { - ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; - } - - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = - (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & - ~(FLASH_FSEQPMP_VIN_BY_PASS_M | - FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - } - else - { - // Select trim values for internal regulator mode: - // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 31) - // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 30:29) - // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 - HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; - - ui32TrimValue = - HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FACTORY_CFG_O_FLASH_OTP_DATA4); - - ui32Value = ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S) << - FLASH_CFG_STANDBY_MODE_SEL_S; - - ui32Value |= ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S) << - FLASH_CFG_STANDBY_PW_SEL_S; - - // Configure DIS_STANDBY (OTP offset 0x308 bit 28). - // Configure DIS_IDLE (OTP offset 0x308 bit 27). - ui32Value |= ((ui32TrimValue & - (FACTORY_CFG_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M | - FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M)) >> - FACTORY_CFG_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S) << - FLASH_CFG_DIS_IDLE_S; - - - HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & - ~(FLASH_CFG_STANDBY_MODE_SEL_M | - FLASH_CFG_STANDBY_PW_SEL_M | - FLASH_CFG_DIS_STANDBY_M | - FLASH_CFG_DIS_IDLE_M)) | ui32Value; - - // Check if sample and hold functionality is disabled. - if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) - { - // - // Wait for disabled sample and hold functionality to be stable. - // - while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) - { - } - } - - // Configure VIN_AT_X (OTP offset 0x308 bits 26:24) - ui32Value = ((ui32TrimValue & - FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M) >> - FACTORY_CFG_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S) << - FLASH_FSEQPMP_VIN_AT_X_S; - - // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. - // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise - // VIN_BY_PASS should be 1 - if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> - FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) - { - ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; - } - - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = - (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & - ~(FLASH_FSEQPMP_VIN_BY_PASS_M | - FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - } -} -//***************************************************************************** -// -//! Set power mode -// -//***************************************************************************** -void -FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriode, - uint32_t ui32PumpGracePeriode) -{ - // - // Check the arguments. - // - ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || - ui32PowerMode == FLASH_PWR_OFF_MODE || - ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); - ASSERT(ui32BankGracePeriode <= 0xFF); - ASSERT(ui32PumpGracePeriode <= 0xFFFF); - - switch(ui32PowerMode) - { - case FLASH_PWR_ACTIVE_MODE: - // - // Set bank power mode to ACTIVE. - // - HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= - (~FLASH_FBFALLBACK_BANKPWR0_M | FBFALLBACK_ACTIVE); - - // - // Set charge pump power mode to ACTIVE mode. - // - HWREG(FLASH_BASE + FLASH_O_FPAC1) |= 1 << FLASH_FPAC1_PUMPPWR_S; - break; - - case FLASH_PWR_OFF_MODE: - // - // Set bank grace periode. - // - HWREG(FLASH_BASE + FLASH_O_FBAC) = - (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | - ((ui32BankGracePeriode << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); - - // - // Set pump grace periode. - // - HWREG(FLASH_BASE + FLASH_O_FPAC2) = - (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | - ((ui32PumpGracePeriode << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); - - // - // Set bank power mode to SLEEP. - // - HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= - (~FLASH_FBFALLBACK_BANKPWR0_M | FBFALLBACK_SLEEP); - - // - // Set charge pump power mode to SLEEP mode. - // - HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; - break; - - case FLASH_PWR_DEEP_STDBY_MODE: - // - // Set bank grace periode. - // - HWREG(FLASH_BASE + FLASH_O_FBAC) = - (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | - ((ui32BankGracePeriode << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); - - // - // Set pump grace periode. - // - HWREG(FLASH_BASE + FLASH_O_FPAC2) = - (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | - ((ui32PumpGracePeriode << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); - - // - // Set bank power mode to DEEP STANDBY mode. - // - HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= - (~FLASH_FBFALLBACK_BANKPWR0_M | FBFALLBACK_DEEP_STDBY); - - // - // Set charge pump power mode to SLEEP mode. - // - HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; - break; - } -} -//***************************************************************************** -// -//! Get current configured power mode -// -//***************************************************************************** -uint32_t -FlashPowerModeGet(void) -{ - uint32_t ui32PowerMode; - uint32_t ui32BankPwrMode; - - ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & - FLASH_FBFALLBACK_BANKPWR0_M; - - if(ui32BankPwrMode == FBFALLBACK_SLEEP) - { - ui32PowerMode = FLASH_PWR_OFF_MODE; - } - else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY) - { - ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE; - } - else - { - ui32PowerMode = FLASH_PWR_ACTIVE_MODE; - } - - // - // Return power mode. - // - return(ui32PowerMode); -} -//***************************************************************************** -// -//! Set sector protection -// -//***************************************************************************** -void -FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode) -{ - uint32_t ui32SectorNumber; - - // - // Check the arguments. - // - ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - - FlashSectorSizeGet())); - ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); - - if(ui32ProtectMode == FLASH_WRITE_PROTECT) - { - ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / - FlashSectorSizeGet(); - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - - if(ui32SectorNumber <= 31) - { - HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); - HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); - } - else if(ui32SectorNumber <= 63) - { - HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= - (1 << (ui32SectorNumber & 0x1F)); - HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= - (1 << (ui32SectorNumber & 0x1F)); - } - - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - } -} -//***************************************************************************** -// -//! Get sector protection -// -//***************************************************************************** -uint32_t -FlashProtectionGet(uint32_t ui32SectorAddress) -{ - uint32_t ui32SectorProtect; - uint32_t ui32SectorNumber; - - // - // Check the arguments. - // - ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - - FlashSectorSizeGet())); - ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); - - ui32SectorProtect = FLASH_NO_PROTECT; - ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); - - if(ui32SectorNumber <= 31) - { - if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && - (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) - { - ui32SectorProtect = FLASH_WRITE_PROTECT; - } - } - else if(ui32SectorNumber <= 63) - { - if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & - (1 << (ui32SectorNumber & 0x1F))) && - (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & - (1 << (ui32SectorNumber & 0x1F)))) - { - ui32SectorProtect = FLASH_WRITE_PROTECT; - } - } - - return(ui32SectorProtect); -} -//***************************************************************************** -// -//! Save sector protection to make it permanent -// -//***************************************************************************** -uint32_t -FlashProtectionSave(uint32_t ui32SectorAddress) -{ - uint32_t ui32ErrorReturn; - uint32_t ui32SectorNumber; - uint32_t ui32CcfgSectorAddr; - uint8_t pui8ProgBuf[4]; - - ui32ErrorReturn = FAPI_STATUS_SUCCESS; - - // - // Check the arguments. - // - ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - - FlashSectorSizeGet())); - ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); - - if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT) - { - // - // Find sector number for specified sector. - // - ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); - ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); - - // - // Adjust CCFG address to the 32-bit CCFG word holding the - // protect-bit for the specified sector. - // - ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT); - - // - // Find value to program by setting the protect-bit which - // corresponds to specified sector number, to 0. - // Leave other protect-bits unchanged. - // - *(uint32_t *)pui8ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) & - *(uint32_t *)ui32CcfgSectorAddr; - - ui32ErrorReturn = FlashProgram(pui8ProgBuf, ui32CcfgSectorAddr, - CCFG_SIZE_SECT_PROT); - } - - // - // Return status. - // - return(ui32ErrorReturn); -} -//***************************************************************************** -// -//! Erase a flash sector -// -//***************************************************************************** -uint32_t -FlashSectorErase(uint32_t ui32SectorAddress) -{ - uint32_t ui32ErrorReturn; - uint32_t ui32Error; - uint32_t ui32SectorBit; - uint32_t ui32SectorNumber; - - // - // Check the arguments. - // - ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - - FlashSectorSizeGet())); - ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); - - // - // Enable all sectors for erase. - // - EnableSectorsForWrite(); - - // - // Check the arguments. - // - if((ui32SectorAddress > - (FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet())) || - ((ui32SectorAddress & (FlashSectorSizeGet() - 1)) != 00)) - { - // - // Invalid arguments. Exit function! - // - FlashDisableSectorsForWrite(); - return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); - } - - // - // Clear the Status register. - // - IssueFsmCommand(FAPI_CLEAR_STATUS); - - // - // Unprotect sector to be erased. - // - ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); - ui32SectorBit = 1 << (ui32SectorNumber & 0x1F); - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - if(ui32SectorNumber < 0x20) - { - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = ~ui32SectorBit; - } - else - { - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = ~ui32SectorBit; - } - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - - // - // Write the address to the FSM. - // - HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32SectorAddress + ADDR_OFFSET; - - // - // Issue the sector erase command to the FSM. - // - IssueFsmCommand(FAPI_ERASE_SECTOR); - - // - // Wait for erase to finish. - // - while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) - { - } - - // - // Update status. - // - ui32ErrorReturn = FlashCheckFsmForError(); - - // - // Disable sectors for erase. - // - FlashDisableSectorsForWrite(); - - // - // Check if flash top sector was erased. - // - if(ui32SectorAddress == (FLASHMEM_BASE + FlashSizeGet() - - FlashSectorSizeGet())) - { - // - // Program security data to default values in the customer configuration - // area within the flash top sector. - // - ui32Error = FlashProgram((uint8_t *)g_pui8CcfgDefaultSec, - (ui32SectorAddress + CCFG_OFFSET_SECURITY), - CCFG_SIZE_SECURITY); - - if((ui32Error != FAPI_STATUS_SUCCESS) && - (ui32ErrorReturn == FAPI_STATUS_SUCCESS)) - { - ui32ErrorReturn = ui32Error; - } - } - - // - // Return status of operation. - // - return(ui32ErrorReturn); -} -//***************************************************************************** -// -//! Programs unprotected main bank flash sectors -// -//***************************************************************************** -uint32_t -FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) -{ - uint32_t ui32StartIndex; - uint32_t ui32StopIndex; - uint32_t ui32Index; - uint8_t ui8BankWidth; - uint8_t ui8NoOfBytes; - tFwpWriteByte *oFwpWriteByte; - uint32_t ui32ErrorReturn; - - // - // Check the arguments. - // - ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet())); - - // - // Enable sectors for programming. - // - EnableSectorsForWrite(); - oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; - - // - // Check the arguments. - // - if((ui32Address + ui32Count) > (FLASHMEM_BASE + FlashSizeGet())) - { - // - // Invalid arguments. Exit function! - // - FlashDisableSectorsForWrite(); - return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); - } - - // - // Set the status to indicate success. - // - ui32ErrorReturn = FAPI_STATUS_SUCCESS; - - // - // Find flash bank width in number of bytes. - // - ui8BankWidth = - (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & - FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> - FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); - - // - // Loop over the bytes to be programmed. - // - while(ui32Count) - { - // - // Setup the start position within the write data registers. - // - ui32StartIndex = ui32Address & (uint32_t)(ui8BankWidth - 1); - - // - // Setup number of bytes to program. - // - ui8NoOfBytes = ui8BankWidth - ui32StartIndex; - if(ui8NoOfBytes > ui32Count) - { - ui8NoOfBytes = ui32Count; - } - - // - // Clear the Status register. - // - IssueFsmCommand(FAPI_CLEAR_STATUS); - - // - // Write address to FADDR register. - // - HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32Address + ADDR_OFFSET; - - // - // Setup the stop position within the write data registers. - // - ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); - - // - // Write each byte to the FWPWrite registers. - // - for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) - { - oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); - } - - // - // Issue the Program command to the FSM. - // - IssueFsmCommand(FAPI_PROGRAM_DATA); - - // - // Wait until the word has been programmed. - // - while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) - { - } - - // - // Exit if an access violation occurred. - // - ui32ErrorReturn = FlashCheckFsmForError(); - if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) - { - break; - } - - // - // Prepare for next data burst. - // - ui32Count -= ((ui32StopIndex - ui32StartIndex) + 1); - ui32Address += ((ui32StopIndex - ui32StartIndex) + 1); - } - - // - // Disable sectors for programming. - // - FlashDisableSectorsForWrite(); - - // - // Return status of operation. - // - return(ui32ErrorReturn); -} -//***************************************************************************** -// -//! Starts programming within unprotected main bank flash sector and returns -// -//***************************************************************************** -uint32_t -FlashProgramNowait(uint32_t ui32StartAddress, uint8_t *pui8DataBuffer, - uint8_t ui8NoOfBytes) -{ - uint32_t ui32StartIndex; - uint32_t ui32StopIndex; - uint32_t ui32Index; - uint32_t ui32BankWidth; - uint32_t ui32ErrorReturn; - tFwpWriteByte *oFwpWriteByte; - - // - // Check the arguments. - // - ASSERT((ui32StartAddress + ui8NoOfBytes) <= (FLASHMEM_BASE + FlashSizeGet())); - - // - // Enable sectors for programming. - // - EnableSectorsForWrite(); - oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; - - // - // Check the arguments. - // - if((ui32StartAddress + ui8NoOfBytes) > (FLASHMEM_BASE + FlashSizeGet())) - { - // - // Invalid arguments. Exit function! - // - FlashDisableSectorsForWrite(); - return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); - } - - // - // Set status to indicate success - // - ui32ErrorReturn = FAPI_STATUS_SUCCESS; - - // - // Find flash bank width in number of bytes. - // - ui32BankWidth = (((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & - FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> - FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); - - // - // Setup the start position within the write data registers. - // - ui32StartIndex = ui32StartAddress & (ui32BankWidth - 1); - - // - // Check to see if there is more data in the buffer than the register. - // width. - // - if((ui8NoOfBytes == 0) || ((ui32StartIndex + ui8NoOfBytes) > ui32BankWidth)) - { - ui32ErrorReturn = FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH; - } - - if(ui32ErrorReturn == FAPI_STATUS_SUCCESS) - { - // - // Clear the Status register. - // - IssueFsmCommand(FAPI_CLEAR_STATUS); - - // - // Write address to FADDR register. - // - HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32StartAddress + ADDR_OFFSET; - - // - // Setup the stop position within the write data registers. - // - ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); - - // - // Write each byte to the FWPWrite registers. - // - for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) - { - oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); - } - - // - // Issue the Program command to the FSM. - // - IssueFsmCommand(FAPI_PROGRAM_DATA); - } - - // - // Return the function status. - // - return(ui32ErrorReturn); -} -//***************************************************************************** -// -//! Reads efuse data from specified row -// -//***************************************************************************** -bool -FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress) -{ - bool bStatus; - - // - // Make sure the clock for the efuse is enabled - // - HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK; - - // - // Set timing for EFUSE read operations. - // - HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) & - FLASH_EFUSEREAD_READCLOCK_M); - - // - // Clear status register. - // - HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0; - - // - // Select the FuseROM block 0. - // - HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000; - - // - // Start the read operation. - // - HWREG(FLASH_BASE + FLASH_O_EFUSE) = - (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) | - (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M); - - // - // Wait for operation to finish. - // - while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE)) - { - } - - // - // Check if error reported. - // - if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M) - { - // - // Set error status. - // - bStatus = 1; - - // - // Clear data. - // - *pui32EfuseData = 0; - } - else - { - // - // Set ok status. - // - bStatus = 0; - - // - // No error. Get data from data register. - // - *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER); - } - - // - // Disable the efuse clock to conserve power - // - HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK; - - // - // Return the data. - // - return(bStatus); -} -//***************************************************************************** -// -//! Disables all sectors for erase and programming on the active bank -// -//***************************************************************************** -void -FlashDisableSectorsForWrite(void) -{ - // - // Configure flash back to read mode - // - SetReadMode(); - - // - // Disable Level 1 Protection. - // - HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; - - // - // Disable all sectors for erase and programming. - // - HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; - - // - // Enable Level 1 Protection. - // - HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; - - // - // Protect sectors from sector erase. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; -} -//***************************************************************************** -// -//! Erase all unprotected sectors in the flash main bank -// -//***************************************************************************** -uint32_t -FlashBankErase(bool bForcePrecondition) -{ - uint32_t ui32ErrorReturn; - uint32_t ui32Error; - uint32_t ui32SectorAddress; - uint32_t ui32RegVal; - - // - // Enable all sectors for erase. - // - EnableSectorsForWrite(); - - // - // Clear the Status register. - // - IssueFsmCommand(FAPI_CLEAR_STATUS); - - // - // Enable erase of all sectors and enable precondition if required. - // - ui32RegVal = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000; - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000; - if(bForcePrecondition) - { - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= - FLASH_FSM_ST_MACHINE_DO_PRECOND; - } - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - - // - // Issue the bank erase command to the FSM. - // - IssueFsmCommand(FAPI_ERASE_BANK); - - // - // Wait for erase to finish. - // - while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) - { - } - - // - // Update status. - // - ui32ErrorReturn = FlashCheckFsmForError(); - - // - // Disable sectors for erase. - // - FlashDisableSectorsForWrite(); - - // - // Set configured precondition mode since it may have been forced on. - // - if(!(ui32RegVal & FLASH_FSM_ST_MACHINE_DO_PRECOND)) - { - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= - ~FLASH_FSM_ST_MACHINE_DO_PRECOND; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - } - - // - // Program security data to default values in the customer configuration - // area within the flash top sector. - // - ui32SectorAddress = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); - ui32Error = FlashProgram((uint8_t *)g_pui8CcfgDefaultSec, - (ui32SectorAddress + CCFG_OFFSET_SECURITY), - CCFG_SIZE_SECURITY); - - if((ui32Error != FAPI_STATUS_SUCCESS) && - (ui32ErrorReturn == FAPI_STATUS_SUCCESS)) - { - ui32ErrorReturn = ui32Error; - } - - // - // Return status of operation. - // - return(ui32ErrorReturn); -} -//***************************************************************************** -// -//! Erase flash OTP/ENGR areas. -// -//***************************************************************************** -uint32_t -FlashhOtpEngrErase(void) -{ - uint32_t ui32ErrorReturn; - uint32_t ui32RegVal; - - // - // Enable all sectors for erase. - // - EnableSectorsForWrite(); - - // - // Clear the Status register. - // - IssueFsmCommand(FAPI_CLEAR_STATUS); - - // - // Disable OTP protection. - // - HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; - HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; - HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; - - // - // Enable test commands. - // - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - - // - // Set address to OTP. - // - HWREG(FLASH_BASE + FLASH_O_FADDR) = 0xF0000000; - - // - // Enable for FSM test commands and erase precondition. - // - ui32RegVal = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= - (FLASH_FSM_ST_MACHINE_CMD_EN | FLASH_FSM_ST_MACHINE_DO_PRECOND); - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - - // - // Issue the erase command to the FSM. - // - IssueFsmCommand(FAPI_ERASE_OTP); - - // - // Wait for erase to finish. - // - while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) - { - } - - // - // Update status. - // - ui32ErrorReturn = FlashCheckFsmForError(); - - // - // Disable sectors for erase. - // - FlashDisableSectorsForWrite(); - - // - // Disable test commands. - // - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - - // - // Renable OTP protection. - // - HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; - HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; - HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; - - // - // Disable FSM test command mode. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; - - // - // Set configured precondition mode since it may have been changed. - // - if(!(ui32RegVal & FLASH_FSM_ST_MACHINE_DO_PRECOND)) - { - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= - ~FLASH_FSM_ST_MACHINE_DO_PRECOND; - } - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - - // - // Return status of operation. - // - return(ui32ErrorReturn); -} -//***************************************************************************** -// -//! Programs a data pattern in a main bank flash sector. -// -//***************************************************************************** -uint32_t -FlashProgramPattern(uint32_t ui32SectorAddress, uint32_t ui32DataPattern, - bool bInvertData) -{ - uint8_t ui8Index; - uint8_t ui8BankWidth; - tFwpWriteByte *oFwpWriteByte; - uint32_t ui32ErrorReturn; - - // - // Check the arguments. - // - ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - - FlashSectorSizeGet())); - ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); - - // - // Enable sectors for programming. - // - EnableSectorsForWrite(); - oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; - - // - // Check the arguments. - // - if((ui32SectorAddress > - (FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet())) || - ((ui32SectorAddress & (FlashSectorSizeGet() - 1)) != 00)) - { - // - // Invalid arguments. Exit function! - // - FlashDisableSectorsForWrite(); - return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); - } - - // - // Find flash bank width in number of bytes. - // - ui8BankWidth = - (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & - FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> - FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); - - // - // Clear the Status register. - // - IssueFsmCommand(FAPI_CLEAR_STATUS); - - // - // Write address to FADDR register. - // - HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32SectorAddress + ADDR_OFFSET; - - // - // Write each byte of the pattern to the FWPWrite registers. - // - for(ui8Index = 0; ui8Index < ui8BankWidth; ui8Index++) - { - oFwpWriteByte[ui8Index] = ui32DataPattern >> ((ui8Index * 8) & - (PATTERN_BITS - 1)); - } - - // - // Enable for FSM test command and enable the Invert Data option if - // required. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; - if(bInvertData) - { - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_INV_DATA; - } - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - - // - // Issue the Program command to the FSM. - // - IssueFsmCommand(FAPI_PROGRAM_SECTOR); - - // - // Wait until the sector has been programmed. - // - while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) - { - } - - // - // Update status of the program operation. - // - ui32ErrorReturn = FlashCheckFsmForError(); - - // - // Disable sectors for programming. - // - FlashDisableSectorsForWrite(); - - // - // Disable FSM test command mode and the Invert Data option. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_INV_DATA; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - - // - // Return status of operation. - // - return(ui32ErrorReturn); -} -//***************************************************************************** -// -//! Programs flash ENGR area -// -//***************************************************************************** -uint32_t -FlashProgramEngr(uint8_t *pui8DataBuffer, uint32_t ui32AddressOffset, - uint32_t ui32Count) -{ - uint32_t ui32StartIndex; - uint32_t ui32StopIndex; - uint32_t ui32Index; - uint8_t ui8BankWidth; - uint8_t ui8NoOfBytes; - tFwpWriteByte *oFwpWriteByte; - uint32_t ui32ErrorReturn; - - // - // Check the arguments. - // - ASSERT((ui32AddressOffset + ui32Count) <= 1024); - - // - // Enable sectors for programming. - // - EnableSectorsForWrite(); - oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; - - // - // Check the arguments. - // - if((ui32AddressOffset + ui32Count) > 1024) - { - // - // Invalid arguments. Exit function! - // - FlashDisableSectorsForWrite(); - return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); - } - - // - // Set the status to indicate success. - // - ui32ErrorReturn = FAPI_STATUS_SUCCESS; - - // - // Find flash bank width in number of bytes. - // - ui8BankWidth = - (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & - FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> - FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); - - // - // Disable OTP protection. - // - // - HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; - HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; - HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; - - // - // Enable test commands. - // - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - - // - // Enable for FSM test command. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - - // - // Loop over the bytes to be programmed. - // - while(ui32Count) - { - // - // Setup the start position within the write data registers. - // - ui32StartIndex = ui32AddressOffset & (uint32_t)(ui8BankWidth - 1); - - // - // Setup number of bytes to program. - // - ui8NoOfBytes = ui8BankWidth - ui32StartIndex; - if(ui8NoOfBytes > ui32Count) - { - ui8NoOfBytes = ui32Count; - } - - // - // Clear the Status register. - // - IssueFsmCommand(FAPI_CLEAR_STATUS); - - // - // Write address to FADDR register. - // - HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32AddressOffset + 0xF0080000; - - // - // Setup the stop position within the write data registers. - // - ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); - - // - // Write each byte to the FWPWrite registers. - // - for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) - { - oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); - } - - // - // Issue programming command. - // - IssueFsmCommand(FAPI_PROGRAM_DATA); - - // - // Wait until the word has been programmed. - // - while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) - { - } - - // - // Update error status and exit if an error occurred. - // - ui32ErrorReturn = FlashCheckFsmForError(); - if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) - { - break; - } - - // - // Prepare for next data burst. - // - ui32Count -= ((ui32StopIndex - ui32StartIndex) + 1); - ui32AddressOffset += ((ui32StopIndex - ui32StartIndex) + 1); - } - - // - // Disable sectors for programming. - // - FlashDisableSectorsForWrite(); - - // - // Reenable OTP protection. - // - HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; - HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; - HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; - - // - // Disable test commands. - // - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - - // - // Disable FSM test command mode. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - - // - // Return status of operation. - // - return(ui32ErrorReturn); -} -//***************************************************************************** -// -//! FlashOtpProgramEraseSetup prepares program and erase of the OTP/ENGR -//! sector. -// -//***************************************************************************** -void -FlashOtpProgramEraseSetup(void) -{ - // - // Disable OTP protection. - // - HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; - HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS; - HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; - - // - // Enable test commands by performing the following steps: - // - Enable SW Interface mode - // - Enable for test commands - // - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x0000AAAA; - HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x000055AA; - - // - // Enable for FSM test commands. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; -} -//***************************************************************************** -// -//! FlashOtpProgramEraseCleanup restores to default program and erase -//! protection. -// -//***************************************************************************** -void -FlashOtpProgramEraseCleanup(void) -{ - // - // Reenable OTP protection. - // - HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; - HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; - HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; - - // - // Disable test commands and turn off SW interface mode. - // - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x0000AAAA; - HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - - // - // Disable FSM test command mode. - // - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; -} -//! @} -//! \\addtogroup i2c_api -//! @{ -//***************************************************************************** -// -//! Initializes the I2C Master block -// -//***************************************************************************** -void -I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast) -{ - uint32_t ui32SCLFreq; - uint32_t ui32TPR; - - // - // Check the arguments. - // - ASSERT(I2CBaseValid(ui32Base)); - - // - // Must enable the device before doing anything else. - // - I2CMasterEnable(ui32Base); - - // - // Get the desired SCL speed. - // - if(bFast == true) - { - ui32SCLFreq = 400000; - } - else - { - ui32SCLFreq = 100000; - } - - // - // Compute the clock divider that achieves the fastest speed less than or - // equal to the desired speed. The numerator is biased to favor a larger - // clock divider so that the resulting clock is always less than or equal - // to the desired clock, never greater. - // - ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1; - HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; -} -//***************************************************************************** -// -//! Gets the error status of the I2C Master module -// -//***************************************************************************** -uint32_t -I2CMasterErr(uint32_t ui32Base) -{ - uint32_t ui32Err; - - // - // Check the arguments. - // - ASSERT(I2CBaseValid(ui32Base)); - - // - // Get the raw error state. - // - ui32Err = HWREG(ui32Base + I2C_O_MSTAT); - - // - // If the I2C master is busy, then all the other status bits are invalid, - // and there is no error to report. - // - if(ui32Err & I2C_MSTAT_BUSY) - { - return(I2C_MASTER_ERR_NONE); - } - - // - // Check for errors. - // - if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) - { - return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK | I2C_MSTAT_ADRACK)); - } - else - { - return(I2C_MASTER_ERR_NONE); - } -} -//! @} -//! \\addtogroup interrupt_api -//! @{ -//***************************************************************************** -// -//! This is a mapping between priority grouping encodings and the number of -//! preemption priority bits. -// -//***************************************************************************** -static const uint32_t g_pui32Priority[] = -{ - NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, - NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, - NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 -}; - -//***************************************************************************** -// -//! This is a mapping between interrupt number and the register that contains -//! the priority encoding for that interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32Regs[] = -{ - 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, - NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, - NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 -}; -//***************************************************************************** -// -//! Sets the priority grouping of the interrupt controller. -// -//***************************************************************************** -void -IntPriorityGroupingSet(uint32_t ui32Bits) -{ - // - // Check the arguments. - // - ASSERT(ui32Bits < NUM_PRIORITY); - - // - // Set the priority grouping. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; -} -//***************************************************************************** -// -//! Gets the priority grouping of the interrupt controller -// -//***************************************************************************** -uint32_t -IntPriorityGroupingGet(void) -{ - uint32_t ui32Loop, ui32Value; - - // - // Read the priority grouping. - // - ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; - - // - // Loop through the priority grouping values. - // - for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) - { - // - // Stop looping if this value matches. - // - if(ui32Value == g_pui32Priority[ui32Loop]) - { - break; - } - } - - // - // Return the number of priority bits. - // - return(ui32Loop); -} -//***************************************************************************** -// -//! Sets the priority of an interrupt -// -//***************************************************************************** -void -IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); - ASSERT(ui8Priority <= INT_PRI_LEVEL7); - - // - // Set the interrupt priority. - // - ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); - ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); - ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); - HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; -} -//***************************************************************************** -// -//! Gets the priority of an interrupt -// -//***************************************************************************** -int32_t -IntPriorityGet(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); - - // - // Return the interrupt priority. - // - return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & - 0xFF); -} -//***************************************************************************** -// -//! Enables an interrupt -// -//***************************************************************************** -void -IntEnable(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to enable. - // - if(ui32Interrupt == FAULT_MPU) - { - // - // Enable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; - } - else if(ui32Interrupt == FAULT_BUS) - { - // - // Enable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; - } - else if(ui32Interrupt == FAULT_USAGE) - { - // - // Enable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Enable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; - } - else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) - { - // - // Enable the general interrupt. - // - HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); - } - else if(ui32Interrupt >= 48) - { - // - // Enable the general interrupt. - // - HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); - } -} -//***************************************************************************** -// -//! Disables an interrupt -// -//***************************************************************************** -void -IntDisable(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to disable. - // - if(ui32Interrupt == FAULT_MPU) - { - // - // Disable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); - } - else if(ui32Interrupt == FAULT_BUS) - { - // - // Disable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); - } - else if(ui32Interrupt == FAULT_USAGE) - { - // - // Disable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Disable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - } - else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) - { - // - // Disable the general interrupt. - // - HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); - } - else if(ui32Interrupt >= 48) - { - // - // Disable the general interrupt. - // - HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48); - } -} -//***************************************************************************** -// -//! Pends an interrupt -// -//***************************************************************************** -void -IntPendSet(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to pend. - // - if(ui32Interrupt == FAULT_NMI) - { - // - // Pend the NMI interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; - } - else if(ui32Interrupt == FAULT_PENDSV) - { - // - // Pend the PendSV interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Pend the SysTick interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; - } - else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) - { - // - // Pend the general interrupt. - // - HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16); - } - else if(ui32Interrupt >= 48) - { - // - // Pend the general interrupt. - // - HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48); - } -} -//***************************************************************************** -// -//! Query whether an interrupt is pending -// -//***************************************************************************** -bool -IntPendGet(uint32_t ui32Interrupt) -{ - uint32_t ui32IntPending; - - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Assume no interrupts are pending. - // - ui32IntPending = 0; - - // - // The lower 16 IRQ vectors are unsupported by this function - // - if (ui32Interrupt < 16) - { - - return 0; - } - - // - // Subtract lower 16 irq vectors - // - ui32Interrupt -= 16; - - // - // Check if the interrupt is pending - // - ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32)); - ui32IntPending &= (1 << (ui32Interrupt & 31)); - - return ui32IntPending ? true : false; -} -//***************************************************************************** -// -//! Unpends an interrupt -// -//***************************************************************************** -void -IntPendClear(uint32_t ui32Interrupt) -{ - // - // Check the arguments. - // - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to unpend. - // - if(ui32Interrupt == FAULT_PENDSV) - { - // - // Unpend the PendSV interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; - } - else if(ui32Interrupt == FAULT_SYSTICK) - { - // - // Unpend the SysTick interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; - } - else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) - { - // - // Unpend the general interrupt. - // - HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16); - } - else if(ui32Interrupt >= 48) - { - // - // Unpend the general interrupt. - // - HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48); - } -} -//! @} -//! \\addtogroup ioc_api -//! @{ -//***************************************************************************** -// -// This is the mapping between an IO and the corresponding configuration -// register. -// -//***************************************************************************** -static const uint32_t g_pui32IOCfgReg[] = -{ - IOC_O_IOCFG0, IOC_O_IOCFG1, IOC_O_IOCFG2, IOC_O_IOCFG3, IOC_O_IOCFG4, - IOC_O_IOCFG5, IOC_O_IOCFG6, IOC_O_IOCFG7, IOC_O_IOCFG8, IOC_O_IOCFG9, - IOC_O_IOCFG10, IOC_O_IOCFG11, IOC_O_IOCFG12, IOC_O_IOCFG13, IOC_O_IOCFG14, - IOC_O_IOCFG15, IOC_O_IOCFG16, IOC_O_IOCFG17, IOC_O_IOCFG18, IOC_O_IOCFG19, - IOC_O_IOCFG20, IOC_O_IOCFG21, IOC_O_IOCFG22, IOC_O_IOCFG23, IOC_O_IOCFG24, - IOC_O_IOCFG25, IOC_O_IOCFG26, IOC_O_IOCFG27, IOC_O_IOCFG28, IOC_O_IOCFG29, - IOC_O_IOCFG30, IOC_O_IOCFG31 -}; -//***************************************************************************** -// -//! Set the configuration of an IO port -// -//***************************************************************************** -void -IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, - uint32_t ui32IOConfig) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT(ui32PortId <= IOC_PORT_RFC_SMI_CL_IN); - - // - // Get the register address. - // - ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the port. - // - HWREG(ui32Reg) = ui32IOConfig | ui32PortId; -} -//***************************************************************************** -// -//! Get the configuration of an IO port -// -//***************************************************************************** -uint32_t -IOCPortConfigureGet(uint32_t ui32IOId) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - - // - // Get the register address. - // - ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Return the IO configuration. - // - return HWREG(ui32Reg); -} -//***************************************************************************** -// -//! Set wake-up on an IO port -// -//***************************************************************************** -void -IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown) -{ - uint32_t ui32Reg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || - (ui32IOShutdown == IOC_WAKE_ON_LOW) || - (ui32IOShutdown == IOC_WAKE_ON_HIGH)); - - // - // Get the register address. - // - ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the IO. - // - ui32Config = HWREG(ui32Reg); - ui32Config &= ~IOC_IOCFG0_WU_CFG_M; - HWREG(ui32Reg) = ui32Config | ui32IOShutdown; -} -//***************************************************************************** -// -//! Set wake-up on an IO port -// -//***************************************************************************** -void -IOCIOJTagSet(uint32_t ui32IOId, uint32_t ui32IOJTag) -{ - uint32_t ui32Reg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32IOJTag == IOC_JTAG_TDO_ENABLE) || - (ui32IOJTag == IOC_JTAG_TDI_ENABLE) || - (ui32IOJTag == IOC_JTAG_DISABLE)); - - // - // Get the register address. - // - ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the IO. - // - ui32Config = HWREG(ui32Reg); - ui32Config &= ~(IOC_IOCFG0_TDI | IOC_IOCFG0_TDO); - HWREG(ui32Reg) = ui32Config | ui32IOJTag; -} -//***************************************************************************** -// -//! Set the IO Mode of an IO Port -// -//***************************************************************************** -void -IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode) -{ - uint32_t ui32Reg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || - (ui32IOMode == IOC_IOMODE_INV) || - (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) || - (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) || - (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) || - (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV)); - - // - // Get the register address. - // - ui32Reg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the IO. - // - ui32Config = HWREG(ui32Reg); - ui32Config &= ~IOC_IOCFG0_IOMODE_M; - HWREG(ui32Reg) = ui32Config | ui32IOMode; -} -//***************************************************************************** -// -//! Setup interrupt detection on an IO Port -// -//***************************************************************************** -void -IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32Int == IOC_INT_ENABLE) || - (ui32Int == IOC_INT_DISABLE)); - ASSERT((ui32EdgeDet == IOC_NO_EDGE) || - (ui32EdgeDet == IOC_FALLING_EDGE) || - (ui32EdgeDet == IOC_RISING_EDGE) || - (ui32EdgeDet == IOC_BOTH_EDGES)); - - // - // Get the register address. - // - ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the IO. - // - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M); - HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet); -} -//***************************************************************************** -// -//! Set the pull on an IO port -// -//***************************************************************************** -void -IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // - // Check the argument. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32Pull == IOC_NO_IOPULL) || - (ui32Pull == IOC_IOPULL_UP) || - (ui32Pull == IOC_IOPULL_DOWN)); - - // - // Get the register address. - // - ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the IO. - // - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_PULL_CTL_M; - HWREG(ui32IOReg) = ui32Config | ui32Pull; -} -//***************************************************************************** -// -//! Configure hysteresis on and IO port -// -//***************************************************************************** -void -IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) || - (ui32Hysteresis == IOC_HYST_DISABLE)); - - // - // Get the register address. - // - ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the IO. - // - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_HYST_EN; - HWREG(ui32IOReg) = ui32Config | ui32Hysteresis; -} -//***************************************************************************** -// -//! Enable/disable IO port as input -// -//***************************************************************************** -void -IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32Input == IOC_INPUT_ENABLE) || - (ui32Input == IOC_INPUT_DISABLE)); - - // - // Get the register address. - // - ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the IO. - // - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_IE; - HWREG(ui32IOReg) = ui32Config | ui32Input; -} -//***************************************************************************** -// -//! Enable/disable the slew control on an IO port -// -//***************************************************************************** -void -IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) || - (ui32SlewEnable == IOC_SLEW_DISABLE)); - - // - // Get the register address. - // - ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the IO. - // - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_SLEW_RED; - HWREG(ui32IOReg) = ui32Config | ui32SlewEnable; -} -//***************************************************************************** -// -//! Configure the drive strength and maxium current of an IO port -// -//***************************************************************************** -void -IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, - uint32_t ui32DrvStrength) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) || - (ui32IOCurrent == IOC_CURRENT_4MA) || - (ui32IOCurrent == IOC_CURRENT_8MA) || - (ui32IOCurrent == IOC_CURRENT_16MA)); - ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) || - (ui32DrvStrength == IOC_STRENGTH_MAX) || - (ui32DrvStrength == IOC_STRENGTH_MED) || - (ui32DrvStrength == IOC_STRENGTH_AUTO)); - - // - // Get the register address. - // - ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the IO. - // - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M); - HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength); -} -//***************************************************************************** -// -//! Setup the Port ID for this IO -// -//***************************************************************************** -void -IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - ASSERT(ui32PortId <= IOC_PORT_RFC_SMI_CL_IN); - - // - // Get the register address. - // - ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Configure the IO. - // - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_PORT_ID_M; - HWREG(ui32IOReg) = ui32Config | ui32PortId; -} -//***************************************************************************** -// -//! Enables individual IO edge detect interrupt -//! -//! \param ui32IOId is the IO to enable edge detect interrupt for. -//! -//! This function enables the indicated IO edge interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \return None -// -//***************************************************************************** -void -IOCIntEnable(uint32_t ui32IOId) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - - // - // Get the register address. - // - ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Enable the specified interrupt. - // - ui32Config = HWREG(ui32IOReg); - ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN; - HWREG(ui32IOReg) = ui32Config; -} -//***************************************************************************** -// -//! Disables individual IO edge interrupt sources -// -//***************************************************************************** -void -IOCIntDisable(uint32_t ui32IOId) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - - // - // Get the register address. - // - ui32IOReg = IOC_BASE + g_pui32IOCfgReg[ui32IOId]; - - // - // Disable the specified interrupt. - // - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN; - HWREG(ui32IOReg) = ui32Config; -} -//***************************************************************************** -// -//! Setup an IO for standard GPIO input -// -//***************************************************************************** -void -IOCPinTypeGpioInput(uint32_t ui32IOId) -{ - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - - // - // Setup the IO for standard input. - // - IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT); - - // - // Enable input mode in the GPIO module. - // - GPIODirModeSet(1 << ui32IOId, GPIO_DIR_MODE_IN); -} -//***************************************************************************** -// -//! Setup an IO for standard GPIO output -// -//***************************************************************************** -void -IOCPinTypeGpioOutput(uint32_t ui32IOId) -{ - // - // Check the arguments. - // - ASSERT(ui32IOId <= IOID_31); - - // - // Setup the IO for standard input. - // - IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT); - - // - // Enable output mode in the GPIO module. - // - GPIODirModeSet(1 << ui32IOId, GPIO_DIR_MODE_OUT); -} -//***************************************************************************** -// -//! Configure a set of IOs for standard UART peripheral control -// -//***************************************************************************** -void -IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, - uint32_t ui32Cts, uint32_t ui32Rts) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == UART0_BASE); - ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); - ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); - ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED)); - ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED)); - - // - // Setup the IOs in the desired configuration. - // - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT); - } - if(ui32Cts != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT); - } - if(ui32Rts != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT); - } -} -//***************************************************************************** -// -//! Configure a set of IOs for standard SSI peripheral master control -// -//***************************************************************************** -void -IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, - uint32_t ui32Tx, uint32_t ui32Fss, - uint32_t ui32Clk) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); - ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); - ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); - ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); - ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); - - // - // Setup the IOs in the desired configuration. - // - if(ui32Base == SSI0_BASE) - { - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); - } - if(ui32Fss != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT); - } - if(ui32Clk != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT); - } - } - else - { - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); - } - if(ui32Fss != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT); - } - if(ui32Clk != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT); - } - } -} -//***************************************************************************** -// -//! Configure a set of IOs for standard SSI peripheral slave control -// -//***************************************************************************** -void -IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, - uint32_t ui32Tx, uint32_t ui32Fss, - uint32_t ui32Clk) -{ - // - // Check the arguments. - // - ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); - ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); - ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); - ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); - ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); - - // - // Setup the IOs in the desired configuration. - // - if(ui32Base == SSI0_BASE) - { - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); - } - if(ui32Fss != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT); - } - if(ui32Clk != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT); - } - } - else - { - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); - } - if(ui32Fss != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT); - } - if(ui32Clk != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT); - } - } -} -//***************************************************************************** -// -//! Configure a set of IOs for standard I2C peripheral control -// -//***************************************************************************** -void -IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk) -{ - uint32_t ui32IOConfig; - - // - // Check the arguments. - // - ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED)); - ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); - - // - // Define the IO configuration parameters. - // - ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP | - IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | - IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL | - IOC_NO_WAKE_UP | IOC_INPUT_ENABLE; - - // - // Setup the IOs in the desired configuration. - // - IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig); - IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig); -} -//***************************************************************************** -// -//! Configure a set of IOs for standard SPIS peripheral control -// -//***************************************************************************** -void -IOCPinTypeSpis(uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, - uint32_t ui32Clk) -{ - // - // Check the arguments. - // - ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); - ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); - ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); - ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); - - // - // Setup the IOs in the desired configuration. - // - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_AON_SDI, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_AON_SDO, IOC_STD_OUTPUT); - } - if(ui32Fss != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Fss, IOC_PORT_AON_SCS, IOC_STD_INPUT); - } - if(ui32Clk != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Clk, IOC_PORT_AON_SCK, IOC_STD_INPUT); - } -} -//***************************************************************************** -// -//! Configure an IO for AUX control -// -//***************************************************************************** -void -IOCPinTypeAux(uint32_t ui32IOId) -{ - // - // Check the arguments. - // - ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED)); - - // - // Setup the IO. - // - IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT); -} -//! @} -//! \\addtogroup prcm_api -//! @{ - -//***************************************************************************** -// -// Arrays that maps the "peripheral set" number (which is stored in the -// third nibble of the PRCM_PERIPH_* defines) to the PRCM register that -// contains the relevant bit for that peripheral. -// -//***************************************************************************** - -// Run mode registers -static const uint32_t g_pui32RCGCRegs[] = -{ - PRCM_O_GPTCLKGR, - PRCM_O_SSICLKGR, - PRCM_O_UARTCLKGR, - PRCM_O_I2CCLKGR, - PRCM_O_SECDMACLKGR, - PRCM_O_GPIOCLKGR, - PRCM_O_I2SCLKGR -}; - -// Sleep mode registers -static const uint32_t g_pui32SCGCRegs[] = -{ - PRCM_O_GPTCLKGS, - PRCM_O_SSICLKGS, - PRCM_O_UARTCLKGS, - PRCM_O_I2CCLKGS, - PRCM_O_SECDMASCLKG, - PRCM_O_GPIOCLKGS, - PRCM_O_I2SCLKGS -}; - -// Deep sleep mode registers -static const uint32_t g_pui32DCGCRegs[] = -{ - PRCM_O_GPTCLKGDS, - PRCM_O_SSICLKGDS, - PRCM_O_UARTCLKGDS, - PRCM_O_I2CCLKGDS, - PRCM_O_SECDMACLKGDS, - PRCM_O_GPIOCLKGDS, - PRCM_O_I2SCLKGDS -}; - -//***************************************************************************** -// -// This macro extracts the array index out of the peripheral number -// -//***************************************************************************** -#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf) - -//***************************************************************************** -// -// This macro extracts the peripheral instance number and generates bit mask -// -//***************************************************************************** -#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0xf)) - -//***************************************************************************** -// -//! Configure the infrastructure clock. -// -//***************************************************************************** -void -PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode) -{ - uint32_t ui32Divisor; - - // - // Check the arguments. - // - ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || - (ui32ClkDiv == PRCM_CLOCK_DIV_2) || - (ui32ClkDiv == PRCM_CLOCK_DIV_8) || - (ui32ClkDiv == PRCM_CLOCK_DIV_32)); - ASSERT((ui32PowerMode == PRCM_RUN_MODE) || - (ui32PowerMode == PRCM_SLEEP_MODE) || - (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); - - ui32Divisor = 0; - - // - // Find the correct division factor. - // - if(ui32ClkDiv == PRCM_CLOCK_DIV_1) - { - ui32Divisor = 0x0; - } - else if(ui32ClkDiv == PRCM_CLOCK_DIV_2) - { - ui32Divisor = 0x1; - } - else if(ui32ClkDiv == PRCM_CLOCK_DIV_8) - { - ui32Divisor = 0x2; - } - else if(ui32ClkDiv == PRCM_CLOCK_DIV_32) - { - ui32Divisor = 0x3; - } - - // - // Determine the correct power mode set the division factor accordingly. - // - if(ui32PowerMode == PRCM_RUN_MODE) - { - HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; - } - else if(ui32PowerMode == PRCM_SLEEP_MODE) - { - HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; - } - else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) - { - HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; - } -} -//***************************************************************************** -// -//! Use this function to retreive the set infrastructure clock configuration -// -//***************************************************************************** -uint32_t -PRCMInfClockConfigureGet(uint32_t ui32PowerMode) -{ - uint32_t ui32ClkDiv; - uint32_t ui32Divisor; - - // - // Check the arguments. - // - ASSERT((ui32PowerMode == PRCM_RUN_MODE) || - (ui32PowerMode == PRCM_SLEEP_MODE) || - (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); - - ui32ClkDiv = 0; - ui32Divisor = 0; - - // - // Determine the correct power mode. - // - if(ui32PowerMode == PRCM_RUN_MODE) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); - } - else if(ui32PowerMode == PRCM_SLEEP_MODE) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); - } - else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); - } - - // - // Find the correct division factor. - // - if(ui32ClkDiv == 0x0) - { - ui32Divisor = PRCM_CLOCK_DIV_1; - } - else if(ui32ClkDiv == 0x1) - { - ui32Divisor = PRCM_CLOCK_DIV_2; - } - else if(ui32ClkDiv == 0x2) - { - ui32Divisor = PRCM_CLOCK_DIV_8; - } - else if(ui32ClkDiv == 0x3) - { - ui32Divisor = PRCM_CLOCK_DIV_32; - } - - // - // Return the clock divison factor. - // - return ui32Divisor; -} -//***************************************************************************** -// -//! Setup the clock division factor for a subsystem in the MCU voltage -//! domain. -// -//***************************************************************************** -void -PRCMClockConfigureSet(uint32_t ui32Domains, uint32_t ui32ClkDiv) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT((ui32Domains & PRCM_DOMAIN_SYSBUS) || - (ui32Domains & PRCM_DOMAIN_CPU) || - (ui32Domains & PRCM_DOMAIN_PERIPH) || - (ui32Domains & PRCM_DOMAIN_TIMER) || - (ui32Domains & PRCM_DOMAIN_SERIAL)); - ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || - (ui32ClkDiv == PRCM_CLOCK_DIV_2) || - (ui32ClkDiv == PRCM_CLOCK_DIV_4) || - (ui32ClkDiv == PRCM_CLOCK_DIV_8) || - (ui32ClkDiv == PRCM_CLOCK_DIV_16) || - (ui32ClkDiv == PRCM_CLOCK_DIV_32) || - (ui32ClkDiv == PRCM_CLOCK_DIV_64) || - (ui32ClkDiv == PRCM_CLOCK_DIV_128) || - (ui32ClkDiv == PRCM_CLOCK_DIV_256)); - - // - // Configure the selected clock dividers. - // - if(ui32Domains & PRCM_DOMAIN_SYSBUS) - { - ui32Reg = PRCM_O_SYSBUSCLKDIV; - HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; - } - if(ui32Domains & PRCM_DOMAIN_CPU) - { - ui32Reg = PRCM_O_CPUCLKDIV; - HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; - } - if(ui32Domains & PRCM_DOMAIN_PERIPH) - { - ui32Reg = PRCM_O_PERBUSCPUCLKDIV; - HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; - } - if(ui32Domains & PRCM_DOMAIN_SERIAL) - { - ui32Reg = PRCM_O_PERDMACLKDIV; - HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; - } - if(ui32Domains & PRCM_DOMAIN_TIMER) - { - ui32Reg = PRCM_O_GPTCLKDIV; - HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; - } -} -//***************************************************************************** -// -//! Get the clock configuration for a specific sub system in the MCU Voltage -//! Domain. -// -//***************************************************************************** -uint32_t -PRCMClockConfigureGet(uint32_t ui32Domain) -{ - uint32_t ui32ClkDiv; - - // - // Check the arguments. - // - ASSERT((ui32Domain == PRCM_DOMAIN_SYSBUS) || - (ui32Domain == PRCM_DOMAIN_CPU) || - (ui32Domain == PRCM_DOMAIN_PERIPH) || - (ui32Domain == PRCM_DOMAIN_TIMER) || - (ui32Domain == PRCM_DOMAIN_SERIAL)); - - ui32ClkDiv = 0; - - // - // Find the correct sub system. - // - if(ui32Domain == PRCM_DOMAIN_SYSBUS) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_SYSBUSCLKDIV); - } - else if(ui32Domain == PRCM_DOMAIN_CPU) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_CPUCLKDIV); - } - else if(ui32Domain == PRCM_DOMAIN_PERIPH) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERBUSCPUCLKDIV); - } - else if(ui32Domain == PRCM_DOMAIN_SERIAL) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERDMACLKDIV); - } - else if(ui32Domain == PRCM_DOMAIN_TIMER) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV); - } - - // - // Return the clock configuration. - // - return(ui32ClkDiv); -} -//***************************************************************************** -// -//! Configure the audio clock generation -// -//***************************************************************************** -void -PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate) -{ - uint32_t ui32Reg; - uint32_t ui32MstDiv; - uint32_t ui32BitDiv; - uint32_t ui32WordDiv; - - // - // Check the arguments. - // - ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); - ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) || - (ui32SampleRate == I2S_SAMPLE_RATE_24K) || - (ui32SampleRate == I2S_SAMPLE_RATE_32K) || - (ui32SampleRate == I2S_SAMPLE_RATE_48K)); - - ui32MstDiv = 0; - ui32BitDiv = 0; - ui32WordDiv = 0; - - // - // Make sure the audio clock generation is disabled before reconfiguring. - // - PRCMAudioClockDisable(); - - // - // Define the clock division factors for the audio interface. - // - switch(ui32SampleRate) - { - case I2S_SAMPLE_RATE_16K : - ui32MstDiv = 6; - ui32BitDiv = 60; - ui32WordDiv = 25; - break; - case I2S_SAMPLE_RATE_24K : - ui32MstDiv = 4; - ui32BitDiv = 40; - ui32WordDiv = 25; - break; - case I2S_SAMPLE_RATE_32K : - ui32MstDiv = 3; - ui32BitDiv = 30; - ui32WordDiv = 25; - break; - case I2S_SAMPLE_RATE_48K : - ui32MstDiv = 2; - ui32BitDiv = 20; - ui32WordDiv = 25; - break; - } - - // - // Make sure to compensate the Frame clock division factor if using single - // phase format. - // - if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) - { - ui32WordDiv -= 1; - } - - // - // Write the clock divison factors. - // - HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; - HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; - HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; - - // - // Configure the Word clock format and polarity. - // - ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | - PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); - HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; -} -//***************************************************************************** -// -//! Turn power on in power domains in the MCU domain -// -//***************************************************************************** -void -PRCMPowerDomainOn(uint32_t ui32Domains) -{ - // - // Check the arguments. - // - ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || - (ui32Domains & PRCM_DOMAIN_SERIAL) || - (ui32Domains & PRCM_DOMAIN_PERIPH) || - (ui32Domains & PRCM_DOMAIN_CPU) || - (ui32Domains & PRCM_DOMAIN_VIMS)); - - // - // Assert the request to power on the right domains. - // - if(ui32Domains & PRCM_DOMAIN_RFCORE) - { - HWREG(PRCM_BASE + - PRCM_O_PDCTL0RFC) |= PRCM_PDCTL0RFC_ON; - HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC) |= PRCM_PDCTL1RFC_ON; - } - if(ui32Domains & PRCM_DOMAIN_SERIAL) - { - HWREG(PRCM_BASE + - PRCM_O_PDCTL0SERIAL) |= PRCM_PDCTL0SERIAL_ON; - } - if(ui32Domains & PRCM_DOMAIN_PERIPH) - { - HWREG(PRCM_BASE + - PRCM_O_PDCTL0PERIPH) |= PRCM_PDCTL0PERIPH_ON; - } - if(ui32Domains & PRCM_DOMAIN_VIMS) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) |= - PRCM_PDCTL1VIMS_ON; - } - if(ui32Domains & PRCM_DOMAIN_CPU) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU) |= PRCM_PDCTL1CPU_ON; - } -} -//***************************************************************************** -// -//! Turn off a specific power domain -// -//***************************************************************************** -void -PRCMPowerDomainOff(uint32_t ui32Domains) -{ - // - // Check the arguments. - // - ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || - (ui32Domains & PRCM_DOMAIN_SERIAL) || - (ui32Domains & PRCM_DOMAIN_PERIPH) || - (ui32Domains & PRCM_DOMAIN_CPU) || - (ui32Domains & PRCM_DOMAIN_VIMS)); - - // - // Assert the request to power off the right domains. - // - if(ui32Domains & PRCM_DOMAIN_RFCORE) - { - HWREG(PRCM_BASE + - PRCM_O_PDCTL0RFC) &= ~PRCM_PDCTL0RFC_ON; - HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC) &= ~PRCM_PDCTL1RFC_ON; - } - if(ui32Domains & PRCM_DOMAIN_SERIAL) - { - HWREG(PRCM_BASE + - PRCM_O_PDCTL0SERIAL) &= ~PRCM_PDCTL0SERIAL_ON; - } - if(ui32Domains & PRCM_DOMAIN_PERIPH) - { - HWREG(PRCM_BASE + - PRCM_O_PDCTL0PERIPH) &= ~PRCM_PDCTL0PERIPH_ON; - } - if(ui32Domains & PRCM_DOMAIN_VIMS) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) &= - ~PRCM_PDCTL1VIMS_ON; - } - if(ui32Domains & PRCM_DOMAIN_CPU) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU) &= ~PRCM_PDCTL1CPU_ON; - } -} -//***************************************************************************** -// -//! Enables a peripheral in Run mode -// -//***************************************************************************** -void -PRCMPeripheralRunEnable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // - // Enable module in Run Mode. - // - HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= - PRCM_PERIPH_MASKBIT(ui32Peripheral); -} -//***************************************************************************** -// -//! Disables a peripheral in Run mode -// -//***************************************************************************** -void -PRCMPeripheralRunDisable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // - // Disable module in Run Mode. - // - HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= - ~PRCM_PERIPH_MASKBIT(ui32Peripheral); -} -//***************************************************************************** -// -//! Enables a peripheral in sleep mode -// -//***************************************************************************** -void -PRCMPeripheralSleepEnable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // - // Enable this peripheral in sleep mode. - // - HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= - PRCM_PERIPH_MASKBIT(ui32Peripheral); -} -//***************************************************************************** -// -//! Disables a peripheral in sleep mode -// -//***************************************************************************** -void -PRCMPeripheralSleepDisable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // - // Disable this peripheral in sleep mode - // - HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= - ~PRCM_PERIPH_MASKBIT(ui32Peripheral); -} -//***************************************************************************** -// -//! Enables a peripheral in deep-sleep mode -// -//***************************************************************************** -void -PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // - // Enable this peripheral in deep-sleep mode. - // - HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= - PRCM_PERIPH_MASKBIT(ui32Peripheral); -} -//***************************************************************************** -// -//! Disables a peripheral in deep-sleep mode -// -//***************************************************************************** -void -PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral) -{ - // - // Check the arguments. - // - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // - // Disable this peripheral in Deep Sleep mode. - // - HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= - ~PRCM_PERIPH_MASKBIT(ui32Peripheral); -} -//***************************************************************************** -// -//! Get the status for a specific power domain -// -//***************************************************************************** -uint32_t -PRCMPowerDomainStatus(uint32_t ui32Domains) -{ - bool bStatus; - uint32_t ui32StatusRegister0; - uint32_t ui32StatusRegister1; - - // - // Check the arguments. - // - ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | - PRCM_DOMAIN_SERIAL | - PRCM_DOMAIN_PERIPH))); - - bStatus = true; - ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0); - ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1); - - // - // Return the correct power status. - // - if(ui32Domains & PRCM_DOMAIN_RFCORE) - { - bStatus = bStatus && - ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || - (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); - } - if(ui32Domains & PRCM_DOMAIN_SERIAL) - { - bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); - } - if(ui32Domains & PRCM_DOMAIN_PERIPH) - { - bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); - } - - // - // Return the status. - // - return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); -} -//***************************************************************************** -// -//! Put the processor into deep-sleep mode -// -//***************************************************************************** -void -PRCMDeepSleep(void) -{ - // - // Enable deep-sleep. - // - HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; - - // - // Wait for an interrupt. - // - CPUwfi(); - - // - // Disable deep-sleep so that a future sleep will work correctly. - // - HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); -} -//***************************************************************************** -// -//! Enable retention on specific power domains -// -//***************************************************************************** -void -PRCMRetentionEnable(uint32_t ui32PowerDomain) -{ - uint32_t ui32Retention; - - // - // Check the arguments. - // - ASSERT((PRCM_DOMAIN_PERIPH & ui32PowerDomain) || - (PRCM_DOMAIN_CPU & ui32PowerDomain)); - - // - // Get the current register. - // - ui32Retention = HWREG(PRCM_BASE + PRCM_O_PDRETEN); - - // - // Set the bits. - // - if(PRCM_DOMAIN_PERIPH & ui32PowerDomain) - { - ui32Retention |= PRCM_PDRETEN_PERIPH; - } - if(PRCM_DOMAIN_CPU & ui32PowerDomain) - { - ui32Retention |= PRCM_PDRETEN_CPU; - } - - // - // Reconfigure retention. - // - HWREG(PRCM_BASE + PRCM_O_PDRETEN) = ui32Retention; - - // - // Get the current register values. - // - ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN); - - // - // Enable retention on RF core SRAM. - // - if(PRCM_DOMAIN_RFCORE & ui32PowerDomain) - { - ui32Retention |= PRCM_RAMRETEN_RFC_M; - } - - // - // Enable retention on VIMS cache. - // - if(PRCM_DOMAIN_VIMS & ui32PowerDomain) - { - ui32Retention |= PRCM_RAMRETEN_VIMS_M; - } - - // - // Reconfigure retention. - // - HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; -} -//***************************************************************************** -// -//! Disable retention on power domains -// -//***************************************************************************** -void -PRCMRetentionDisable(uint32_t ui32PowerDomain) -{ - uint32_t ui32Retention; - - // - // Check the arguments. - // - ASSERT((PRCM_DOMAIN_PERIPH & ui32PowerDomain) || - (PRCM_DOMAIN_CPU & ui32PowerDomain)); - - // - // Get the current register. - // - ui32Retention = HWREG(PRCM_BASE + PRCM_O_PDRETEN); - - // - // Clear the bits. - // - if(PRCM_DOMAIN_PERIPH & ui32PowerDomain) - { - ui32Retention &= ~PRCM_PDRETEN_PERIPH; - } - if(PRCM_DOMAIN_CPU & ui32PowerDomain) - { - ui32Retention &= ~PRCM_PDRETEN_CPU; - } - - // - // Reconfigure retention. - // - HWREG(PRCM_BASE + PRCM_O_PDRETEN) = ui32Retention; - - // - // Get the current register values - // - ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN); - - // - // Disable retention on RF core SRAM - // - if(PRCM_DOMAIN_RFCORE & ui32PowerDomain) - { - ui32Retention &= ~PRCM_RAMRETEN_RFC_M; - } - - // - // Disable retention on VIMS cache - // - if(PRCM_DOMAIN_VIMS & ui32PowerDomain) - { - ui32Retention &= ~PRCM_RAMRETEN_VIMS_M; - } - - // - // Reconfigure retention. - // - HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; -} -//! @} -//! \\addtogroup smph_api -//! @{ -//***************************************************************************** -// -//! Acquire a semaphore -// -//***************************************************************************** -void -SMPHAcquire(uint32_t ui32Semaphore) -{ - // - // Check the arguments. - // - ASSERT((ui32Semaphore == SMPH_0) || - (ui32Semaphore == SMPH_1) || - (ui32Semaphore == SMPH_2) || - (ui32Semaphore == SMPH_3) || - (ui32Semaphore == SMPH_4) || - (ui32Semaphore == SMPH_5) || - (ui32Semaphore == SMPH_6) || - (ui32Semaphore == SMPH_7) || - (ui32Semaphore == SMPH_8) || - (ui32Semaphore == SMPH_9) || - (ui32Semaphore == SMPH_10) || - (ui32Semaphore == SMPH_11) || - (ui32Semaphore == SMPH_12) || - (ui32Semaphore == SMPH_13) || - (ui32Semaphore == SMPH_14) || - (ui32Semaphore == SMPH_15) || - (ui32Semaphore == SMPH_16) || - (ui32Semaphore == SMPH_17) || - (ui32Semaphore == SMPH_18) || - (ui32Semaphore == SMPH_19) || - (ui32Semaphore == SMPH_20) || - (ui32Semaphore == SMPH_21) || - (ui32Semaphore == SMPH_22) || - (ui32Semaphore == SMPH_23) || - (ui32Semaphore == SMPH_24) || - (ui32Semaphore == SMPH_25) || - (ui32Semaphore == SMPH_26) || - (ui32Semaphore == SMPH_27) || - (ui32Semaphore == SMPH_28) || - (ui32Semaphore == SMPH_29) || - (ui32Semaphore == SMPH_30) || - (ui32Semaphore == SMPH_31)); - - // - // Wait for semaphore to be release such that it can be claimed - // Semaphore register reads 1 when lock was acquired otherwise 0 - // (i.e. SMPH_CLAIMED). - // - while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == - SMPH_CLAIMED) - { - } -} -//! @} -//! \\addtogroup spis_api -//! @{ -//***************************************************************************** -// -// This is the mapping between an TX Fifo index and the corresponding -// register. -// -//***************************************************************************** -static const uint32_t g_pui32SPISTxFifo[] = -{ - SPIS_O_TXFMEM0, SPIS_O_TXFMEM1, SPIS_O_TXFMEM2, SPIS_O_TXFMEM3, SPIS_O_TXFMEM4, - SPIS_O_TXFMEM5, SPIS_O_TXFMEM6, SPIS_O_TXFMEM7, SPIS_O_TXFMEM8, SPIS_O_TXFMEM9, - SPIS_O_TXFMEM10, SPIS_O_TXFMEM11, SPIS_O_TXFMEM12, SPIS_O_TXFMEM13, - SPIS_O_TXFMEM14, SPIS_O_TXFMEM15 -}; - -//***************************************************************************** -// -// This is the mapping between an RX Fifo index and the corresponding -// register. -// -//***************************************************************************** -static const uint32_t g_pui32SPISRxFifo[] = -{ - SPIS_O_RXFMEM0, SPIS_O_RXFMEM1, SPIS_O_RXFMEM2, SPIS_O_RXFMEM3, SPIS_O_RXFMEM4, - SPIS_O_RXFMEM5, SPIS_O_RXFMEM6, SPIS_O_RXFMEM7, SPIS_O_RXFMEM8, SPIS_O_RXFMEM9, - SPIS_O_RXFMEM10, SPIS_O_RXFMEM11, SPIS_O_RXFMEM12, SPIS_O_RXFMEM13, - SPIS_O_RXFMEM14, SPIS_O_RXFMEM15 -}; -//***************************************************************************** -// -//! Puts a data element into the SPIS transmit FIFO -// -//***************************************************************************** -void -SPISDataPut(uint32_t ui32Data) -{ - // - // Wait until there is space. - // - while(HWREG(SPIS_BASE + SPIS_O_TXFSTAT) & SPIS_TXFSTAT_FULL) - { - } - - // - // Write the data to the SPIS Tx Fifo. - // - HWREG(SPIS_BASE + SPIS_O_TXFPUSH) = ui32Data; -} -//***************************************************************************** -// -//! Get a specific value in the Tx Fifo -// -//***************************************************************************** -uint32_t -SPISTxGetValue(uint32_t ui32Index) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT(ui32Index < TX_FIFO_SIZE); - - // - // Find the correct register. - // - ui32Reg = g_pui32SPISTxFifo[ui32Index]; - - // - // Return the value of the TX Fifo at the specified index. - // - return HWREG(SPIS_BASE + ui32Reg); -} -//***************************************************************************** -// -//! Gets a data element from the SPIS Rx FIFO -// -//***************************************************************************** -void -SPISDataGet(uint32_t *pui32Data) -{ - // - // Wait until there is data to be read. - // - while(!(HWREG(SPIS_BASE + SPIS_O_RXFSTAT) & SPIS_RXFSTAT_NOT_EMPTY)) - { - } - - // - // Read data from SPIS Rx Fifo. - // - *pui32Data = HWREG(SPIS_BASE + SPIS_O_RXFPOP); -} -//***************************************************************************** -// -//! Get a specific value in the Rx Fifo -// -//***************************************************************************** -uint32_t -SPISRxGetValue(uint32_t ui32Index) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT(ui32Index < RX_FIFO_SIZE); - - // - // Find the correct register. - // - ui32Reg = g_pui32SPISRxFifo[ui32Index]; - - // - // Return the value of the RX Fifo at the specified index. - // - return HWREG(SPIS_BASE + ui32Reg); -} -//***************************************************************************** -// -//! Gets the current interrupt status -//! -//! \param bMasked is \b false if the raw interrupt status is required or -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the SPIS module. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status consisting of a bitwise OR value -//! of the available interrupts sources as described in \b SPISIntEnable(). -// -//***************************************************************************** -uint32_t -SPISIntStatus(bool bMasked) -{ - uint32_t ui32IntStatus, ui32Tmp; - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - ui32Tmp = HWREG(SPIS_BASE + SPIS_O_TXFFLAGSCLRN); - ui32IntStatus = ui32Tmp & HWREG(SPIS_BASE + SPIS_O_TXFFLAGSMASK); - ui32Tmp = HWREG(SPIS_BASE + SPIS_O_RXFFLAGSCLRN); - ui32IntStatus |= (ui32Tmp & HWREG(SPIS_BASE + SPIS_O_RXFFLAGSMASK)) << 8; - ui32Tmp = HWREG(SPIS_BASE + SPIS_O_GPFLAGS); - ui32IntStatus |= (ui32Tmp & HWREG(SPIS_BASE + SPIS_O_GPFLAGSMASK)) << 16; - } - else - { - ui32IntStatus = HWREG(SPIS_BASE + SPIS_O_TXFFLAGSCLRN) & SPIS_TX_MASK; - ui32IntStatus |= (HWREG(SPIS_BASE + SPIS_O_RXFFLAGSCLRN) << 8) & SPIS_RX_MASK; - ui32IntStatus |= (HWREG(SPIS_BASE + SPIS_O_GPFLAGS) << 16) & SPIS_GP_MASK; - } - return ui32IntStatus; -} -//! @} -//! \\addtogroup ssi_api -//! @{ -//***************************************************************************** -// -//! Configures the synchronous serial port -// -//***************************************************************************** -void -SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, - uint32_t ui32Protocol, uint32_t ui32Mode, - uint32_t ui32BitRate, uint32_t ui32DataWidth) -{ - uint32_t ui32MaxBitRate; - uint32_t ui32RegVal; - uint32_t ui32PreDiv; - uint32_t ui32SCR; - uint32_t ui32SPH_SPO; - - // - // Check the arguments. - // - ASSERT(SSIBaseValid(ui32Base)); - ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || - (ui32Protocol == SSI_FRF_MOTO_MODE_1) || - (ui32Protocol == SSI_FRF_MOTO_MODE_2) || - (ui32Protocol == SSI_FRF_MOTO_MODE_3) || - (ui32Protocol == SSI_FRF_TI) || - (ui32Protocol == SSI_FRF_NMW)); - ASSERT((ui32Mode == SSI_MODE_MASTER) || - (ui32Mode == SSI_MODE_SLAVE) || - (ui32Mode == SSI_MODE_SLAVE_OD)); - ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || - ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); - ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); - ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); - - // - // Set the mode. - // - ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; - ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; - HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; - - // - // Set the clock predivider. - // - ui32MaxBitRate = ui32SSIClk / ui32BitRate; - ui32PreDiv = 0; - do - { - ui32PreDiv += 2; - ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; - } - while(ui32SCR > 255); - HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; - - // - // Set protocol and clock rate. - // - ui32SPH_SPO = (ui32Protocol & 3) << 6; - ui32Protocol &= SSI_CR0_FRF_M; - ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); - HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; -} -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO -// -//***************************************************************************** -void -SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(SSIBaseValid(ui32Base)); - ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & - SSI_CR0_DSS_M))) == 0); - - // - // Wait until there is space. - // - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) - { - } - - // - // Write the data to the SSI. - // - HWREG(ui32Base + SSI_O_DR) = ui32Data; -} -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO -// -//***************************************************************************** -int32_t -SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(SSIBaseValid(ui32Base)); - ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & - SSI_CR0_DSS_M))) == 0); - - // - // Check for space to write. - // - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) - { - HWREG(ui32Base + SSI_O_DR) = ui32Data; - return(1); - } - else - { - return(0); - } -} -//***************************************************************************** -// -//! Gets a data element from the SSI receive FIFO -// -//***************************************************************************** -void -SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) -{ - // - // Check the arguments. - // - ASSERT(SSIBaseValid(ui32Base)); - - // - // Wait until there is data to be read. - // - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) - { - } - - // - // Read data from SSI. - // - *pui32Data = HWREG(ui32Base + SSI_O_DR); -} -//***************************************************************************** -// -//! Gets a data element from the SSI receive FIFO -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pui32Data is a pointer to a storage location for data that was -//! received over the SSI interface. -//! -//! This function gets received data from the receive FIFO of the specified SSI -//! module and places that data into the location specified by the \e ui32Data -//! parameter. If there is no data in the FIFO, then this function returns a -//! zero. -//! -//! \note Only the lower N bits of the value written to \e pui32Data contain -//! valid data, where N is the data width as configured by \sa -//! SSIConfigSetExpClk(). For example, if the interface is configured for -//! 8-bit data width, only the lower 8 bits of the value written to \e pui32Data -//! contain valid data. -//! -//! \return Returns the number of elements read from the SSI receive FIFO. -// -//***************************************************************************** -int32_t -SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) -{ - // - // Check the arguments. - // - ASSERT(SSIBaseValid(ui32Base)); - - // - // Check for data to read. - // - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) - { - *pui32Data = HWREG(ui32Base + SSI_O_DR); - return(1); - } - else - { - return(0); - } -} -//! @} -//! \\addtogroup timer_api -//! @{ -//***************************************************************************** -// -//! Configures the timer(s) -// -//***************************************************************************** -void -TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || - (ui32Config == TIMER_CFG_ONE_SHOT_UP) || - (ui32Config == TIMER_CFG_PERIODIC) || - (ui32Config == TIMER_CFG_PERIODIC_UP) || - (ui32Config == TIMER_CFG_RTC) || - ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); - ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || - ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && - (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); - - // - // Disable the timers. - // - HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); - - // - // Set the global timer configuration. - // - HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; - - // - // Set the configuration of the A and B timers. Note that the B timer - // configuration is ignored by the hardware in 32-bit modes. - // - HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; - HWREG(ui32Base + GPT_O_TBMR) = - ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; -} -//***************************************************************************** -// -//! Controls the output level -// -//***************************************************************************** -void -TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the output levels as requested. - // - ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; - HWREG(ui32Base + GPT_O_CTL) = (bInvert ? - (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : - (HWREG(ui32Base + GPT_O_CTL) & - ~(ui32Timer))); -} -//***************************************************************************** -// -//! Enables or disables the ADC trigger output -// -//***************************************************************************** -void -TimerTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bEnable) -{ - uint32_t ui32Val; - - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Determine which bits to set or clear in GPTM_ADCEV. - // - ui32Val = (GPT_ADCEV_TATOADCEN | GPT_ADCEV_TBTOADCEN); - ui32Val &= ui32Timer; - - // - // Write the GPTM ADC Event register to enable or disable the trigger. - // to the ADC. - // - HWREG(ui32Base + GPT_O_ADCEV) = (bEnable ? - (HWREG(ui32Base + GPT_O_ADCEV) | ui32Val) : - (HWREG(ui32Base + GPT_O_ADCEV) & - ~(ui32Val))); - - // - // Set the trigger output as requested. - // Set the ADC trigger output as requested. - // - ui32Timer &= GPT_CTL_TAOTE | GPT_CTL_TBOTE; - HWREG(ui32Base + GPT_O_CTL) = (bEnable ? - (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : - (HWREG(ui32Base + GPT_O_CTL) & - ~(ui32Timer))); -} -//***************************************************************************** -// -//! Controls the stall handling -// -//***************************************************************************** -void -TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the stall mode. - // - ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; - HWREG(ui32Base + GPT_O_CTL) = (bStall ? - (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : - (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); -} -//***************************************************************************** -// -//! Controls the wait on trigger handling -// -//***************************************************************************** -void -TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // - // Set the wait on trigger mode for timer A. - // - if(ui32Timer & TIMER_A) - { - if(bWait) - { - HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; - } - else - { - HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); - } - } - - // - // Set the wait on trigger mode for timer B. - // - if(ui32Timer & TIMER_B) - { - if(bWait) - { - HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; - } - else - { - HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); - } - } -} -//! @} -//! \\addtogroup trng_api -//! @{ -//***************************************************************************** -// -//! Configure the true random number generator -// -//***************************************************************************** -void -TRNGConfigure(uint32_t ui32MinSamplesPerCycle, - uint32_t ui32MaxSamplesPerCycle, - uint32_t ui32ClocksPerSample) -{ - uint32_t ui32Val; - - // - // Make sure the TRNG is disabled. - // - ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; - HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; - - // - // Configure the startup number of samples. - // - ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; - ui32Val |= ((ui32MaxSamplesPerCycle >> 8) & 0xFFFF) << 16; - HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; - - // - // Configure the minimum and maximum number of samples pr generated number - // and the number of clocks per sample. - // - HWREG(TRNG_BASE + TRNG_O_CFG0) = - (((ui32MaxSamplesPerCycle >> 8) & 0xFFFF) << 16) | - ((ui32ClocksPerSample & 0xFF) << 8) | - ((ui32MinSamplesPerCycle >> 6) & 0xFF); -} -//***************************************************************************** -// -//! Get a random number from the generator -// -//***************************************************************************** -uint32_t -TRNGNumberGet(uint32_t ui32Word) -{ - uint32_t ui32RandomNumber; - - // - // Check the arguments. - // - ASSERT((ui32Word == TRNG_HI_WORD) || - (ui32Word == TRNG_LOW_WORD)); - - // - // Return the right requested part of the generated number. - // - if(ui32Word == TRNG_HI_WORD) - { - ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); - } - else - { - ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); - } - - // - // Initiate generation of new number. - // - HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; - - // - // Return the random number. - // - return ui32RandomNumber; -} -//! @} -//! \\addtogroup uart_api -//! @{ -//***************************************************************************** -// -//! Gets the FIFO level at which interrupts are generated -// -//***************************************************************************** -void -UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, - uint32_t *pui32RxLevel) -{ - uint32_t ui32Temp; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ui32Base)); - - // - // Read the FIFO level register. - // - ui32Temp = HWREG(ui32Base + UART_O_IFLS); - - // - // Extract the transmit and receive FIFO levels. - // - *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; - *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; -} -//***************************************************************************** -// -//! Sets the configuration of a UART -// -//***************************************************************************** -void -UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t ui32Baud, uint32_t ui32Config) -{ - uint32_t ui32Div; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ui32Base)); - ASSERT(ui32Baud != 0); - - // - // Stop the UART. - // - UARTDisable(ui32Base); - - // - // Compute the fractional baud rate divider. - // - ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; - - // - // Set the baud rate. - // - HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; - HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; - - // - // Set parity, data length, and number of stop bits. - // - HWREG(ui32Base + UART_O_LCRH) = ui32Config; - - // - // Clear the flags register. - // - HWREG(ui32Base + UART_O_FR) = 0; -} -//***************************************************************************** -// -//! Gets the current configuration of a UART -// -//***************************************************************************** -void -UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t *pui32Baud, uint32_t *pui32Config) -{ - uint32_t ui32Int, ui32Frac; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ui32Base)); - - // - // Compute the baud rate. - // - ui32Int = HWREG(ui32Base + UART_O_IBRD); - ui32Frac = HWREG(ui32Base + UART_O_FBRD); - *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); - - // - // Get the parity, data length, and number of stop bits. - // - *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | - UART_LCRH_EPS | UART_LCRH_PEN)); -} -//***************************************************************************** -// -//! Disables transmitting and receiving -// -//***************************************************************************** -void -UARTDisable(uint32_t ui32Base) -{ - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ui32Base)); - - // - // Wait for end of TX. - // - while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) - { - } - - // - // Disable the FIFO. - // - HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); - - // - // Disable the UART. - // - HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} -//***************************************************************************** -// -//! Receives a character from the specified port -// -//***************************************************************************** -int32_t -UARTCharGetNonBlocking(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ui32Base)); - - // - // See if there are any characters in the receive FIFO. - // - if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) - { - // - // Read and return the next character. - // - return(HWREG(ui32Base + UART_O_DR)); - } - else - { - // - // There are no characters, so return a failure. - // - return(-1); - } -} -//***************************************************************************** -// -//! Waits for a character from the specified port -// -//***************************************************************************** -int32_t -UARTCharGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ui32Base)); - - // - // Wait until a char is available. - // - while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) - { - } - - // - // Now get the character. - // - return(HWREG(ui32Base + UART_O_DR)); -} -//***************************************************************************** -// -//! Sends a character to the specified port -// -//***************************************************************************** -bool -UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ui32Base)); - - // - // See if there is space in the transmit FIFO. - // - if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) - { - // - // Write this character to the transmit FIFO. - // - HWREG(ui32Base + UART_O_DR) = ui8Data; - - // - // Success. - // - return(true); - } - else - { - // - // There is no space in the transmit FIFO, so return a failure. - // - return(false); - } -} -//***************************************************************************** -// -//! Waits to send a character from the specified port -// -//***************************************************************************** -void -UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ui32Base)); - - // - // Wait until space is available. - // - while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) - { - } - - // - // Send the char. - // - HWREG(ui32Base + UART_O_DR) = ui8Data; -} -//! @} -//! \\addtogroup udma_api -//! @{ -//***************************************************************************** -// -//! Enables attributes of a uDMA channel -// -//***************************************************************************** -void -uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, - uint32_t ui32Attr) -{ - // - // Check the arguments. - // - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // - // Set the useburst bit for this channel if set in ui32Attr. - // - if(ui32Attr & UDMA_ATTR_USEBURST) - { - HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; - } - - // - // Set the alternate control select bit for this channel, - // if set in ui32Attr. - // - if(ui32Attr & UDMA_ATTR_ALTSELECT) - { - HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; - } - - // - // Set the high priority bit for this channel, if set in ui32Attr. - // - if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; - } - - // - // Set the request mask bit for this channel, if set in ui32Attr. - // - if(ui32Attr & UDMA_ATTR_REQMASK) - { - HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; - } -} -//***************************************************************************** -// -//! Disables attributes of an uDMA channel -// -//***************************************************************************** -void -uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, - uint32_t ui32Attr) -{ - // - // Check the arguments. - // - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // - // Clear the useburst bit for this channel if set in ui32Attr. - // - if(ui32Attr & UDMA_ATTR_USEBURST) - { - HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; - } - - // - // Clear the alternate control select bit for this channel, if set in - // ululAttr. - // - if(ui32Attr & UDMA_ATTR_ALTSELECT) - { - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; - } - - // - // Clear the high priority bit for this channel, if set in ui32Attr. - // - if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; - } - - // - // Clear the request mask bit for this channel, if set in ui32Attr. - // - if(ui32Attr & UDMA_ATTR_REQMASK) - { - HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; - } -} -//***************************************************************************** -// -//! Gets the enabled attributes of a uDMA channel -// -//***************************************************************************** -uint32_t -uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - uint32_t ui32Attr = 0; - - // - // Check the arguments. - // - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // - // Check to see if useburst bit is set for this channel. - // - if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_USEBURST; - } - - // - // Check to see if the alternate control bit is set for this channel. - // - if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_ALTSELECT; - } - - // - // Check to see if the high priority bit is set for this channel. - // - if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; - } - - // - // Check to see if the request mask bit is set for this channel. - // - if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_REQMASK; - } - - // - // Return the configuration flags. - // - return(ui32Attr); -} -//***************************************************************************** -// -//! Sets the control parameters for a uDMA channel control structure -// -//***************************************************************************** -void -uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, - uint32_t ui32Control) -{ - tDMAControlTable *pControlTable; - - // - // Check the arguments. - // - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // - // Get the current control word value and mask off the fields to be - // changed, then OR in the new settings. - // - pControlTable[ui32ChannelStructIndex].ui32Control = - ((pControlTable[ui32ChannelStructIndex].ui32Control & - ~(UDMA_DST_INC_M | - UDMA_SRC_INC_M | - UDMA_SIZE_M | - UDMA_ARB_M | - UDMA_NEXT_USEBURST)) | - ui32Control); -} -//***************************************************************************** -// -//! Sets the transfer parameters for a uDMA channel control structure -// -//***************************************************************************** -void -uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, - uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, - uint32_t ui32TransferSize) -{ - tDMAControlTable *pControlTable; - uint32_t ui32Control; - uint32_t ui32Inc; - uint32_t ui32BufferBytes; - - // - // Check the arguments. - // - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); - ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); - ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); - ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // - // Get the current control word value and mask off the mode and size - // fields. - // - ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & - ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); - - // - // Adjust the mode if the alt control structure is selected. - // - if(ui32ChannelStructIndex & UDMA_ALT_SELECT) - { - if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - ui32Mode |= UDMA_MODE_ALT_SELECT; - } - } - - // - // Set the transfer size and mode in the control word (but don't write the - // control word yet as it could kick off a transfer). - // - ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); - - // - // Get the address increment value for the source, from the control word. - // - ui32Inc = (ui32Control & UDMA_SRC_INC_M); - - // - // Compute the ending source address of the transfer. If the source - // increment is set to none, then the ending address is the same as the - // beginning. - // - if(ui32Inc != UDMA_SRC_INC_NONE) - { - ui32Inc = ui32Inc >> UDMA_SRC_INC_S; - ui32BufferBytes = ui32TransferSize << ui32Inc; - pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - 1); - } - - // - // Load the source ending address into the control block. - // - pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; - - // - // Get the address increment value for the destination, from the control - // word. - // - ui32Inc = ui32Control & UDMA_DST_INC_M; - - // - // Compute the ending destination address of the transfer. If the - // destination increment is set to none, then the ending address is the - // same as the beginning. - // - if(ui32Inc != UDMA_DST_INC_NONE) - { - // - // There is a special case if this is setting up a scatter-gather - // transfer. The destination pointer needs to point to the end of - // the alternate structure for this channel instead of calculating - // the end of the buffer in the normal way. - // - if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - pvDstAddr = - (void *)&pControlTable[ui32ChannelStructIndex | - UDMA_ALT_SELECT].ui32Spare; - } - // - // Not a scatter-gather transfer, calculate end pointer normally. - // - else - { - ui32Inc = ui32Inc >> UDMA_DST_INC_S; - ui32BufferBytes = ui32TransferSize << ui32Inc; - pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); - } - } - - // - // Load the destination ending address into the control block. - // - pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; - - // - // Write the new control word value. - // - pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; -} -//***************************************************************************** -// -//! Configures a uDMA channel for scatter-gather mode -// -//***************************************************************************** -void -uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, - uint32_t ui32TaskCount, void *pvTaskList, - uint32_t ui32IsPeriphSG) -{ - tDMAControlTable *pControlTable; - tDMAControlTable *pTaskTable; - - // - // Check the parameters. - // - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - ASSERT(pvTaskList != 0); - ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); - ASSERT(ui32TaskCount != 0); - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // - // Get a handy pointer to the task list. - // - pTaskTable = (tDMAControlTable *)pvTaskList; - - // - // Compute the ending address for the source pointer. This will be the - // last element of the last task in the task table. - // - pControlTable[ui32ChannelNum].pvSrcEndAddr = - &pTaskTable[ui32TaskCount - 1].ui32Spare; - - // - // Compute the ending address for the destination pointer. This will be - // the end of the alternate structure for this channel. - // - pControlTable[ui32ChannelNum].pvDstEndAddr = - &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; - - // - // Compute the control word. Most configurable items are fixed for - // scatter-gather. Item and increment sizes are all 32-bit and arb - // size must be 4. The count is the number of items in the task list - // times 4 (4 words per task). - // - pControlTable[ui32ChannelNum].ui32Control = - (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | - UDMA_SIZE_32 | UDMA_ARB_4 | - (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | - (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : - UDMA_MODE_MEM_SCATTER_GATHER)); - - // - // Scatter-gather operations can leave the alt bit set. So if doing - // back to back scatter-gather transfers, the second attempt may not - // work correctly because the alt bit is set. Therefore, clear the - // alt bit here to ensure that it is always cleared before a new SG - // transfer is started. - // - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; - -} -//***************************************************************************** -// -//! Gets the current transfer size for a uDMA channel control structure -// -//***************************************************************************** -uint32_t -uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) -{ - tDMAControlTable *pControlTable; - uint32_t ui32Control; - - // - // Check the arguments. - // - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // - // Get the current control word value and mask off all but the size field - // and the mode field. - // - ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & - (UDMA_XFER_SIZE_M | UDMA_MODE_M)); - - // - // If the size field and mode field are 0 then the transfer is finished - // and there are no more items to transfer. - // - if(ui32Control == 0) - { - return(0); - } - - // - // Otherwise, if either the size field or more field is non-zero, then - // not all the items have been transferred. - // - else - { - // - // Shift the size field and add one, then return to user. - // - return((ui32Control >> UDMA_XFER_SIZE_S) + 1); - } -} -//***************************************************************************** -// -//! Gets the transfer mode for a uDMA channel control structure -// -//***************************************************************************** -uint32_t -uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) -{ - tDMAControlTable *pControlTable; - uint32_t ui32Control; - - // - // Check the arguments. - // - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // - // Get the current control word value and mask off all but the mode field. - // - ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & - UDMA_MODE_M); - - // - // Check if scatter/gather mode, and if so, mask off the alt bit. - // - if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || - ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) - { - ui32Control &= ~UDMA_MODE_ALT_SELECT; - } - - // - // Return the mode to the caller. - // - return(ui32Control); -} -//! @} -//! \\addtogroup vims_api -//! @{ -//***************************************************************************** -// -//! Configures the VIMS. -// -//***************************************************************************** -void -VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT(VIMSBaseValid(ui32Base)); - - ui32Reg = HWREG(ui32Base + VIMS_O_CTL); - ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); - if(bRoundRobin) - { - ui32Reg |= VIMS_CTL_ARB_CFG; - } - if(bPrefetch) - { - ui32Reg |= VIMS_CTL_PREF_EN; - } - - // - // Set the Arbitration and prefetch mode. - // - HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; -} -//***************************************************************************** -// -//! Set the operational mode of the VIMS -// -//***************************************************************************** -void -VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT(VIMSBaseValid(ui32Base)); - - ASSERT((ui32Mode == VIMS_MODE_INVALIDATE) || - (ui32Mode == VIMS_MODE_DISABLED) || - (ui32Mode == VIMS_MODE_ENABLED) || - (ui32Mode == VIMS_MODE_OFF) || - (ui32Mode == VIMS_MODE_SPLIT)); - - // - // Set the mode. - // - ui32Reg = HWREG(ui32Base + VIMS_O_CTL); - ui32Reg &= ~VIMS_CTL_MODE_M; - ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); - - HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; -} -//***************************************************************************** -// -//! Get the current operational mode of the VIMS. -// -//***************************************************************************** -uint32_t -VIMSModeGet(uint32_t ui32Base) -{ - uint32_t ui32Reg; - - // - // Check the arguments. - // - ASSERT(VIMSBaseValid(ui32Base)); - - ui32Reg = HWREG(ui32Base + VIMS_O_STAT); - if(ui32Reg & VIMS_STAT_INV) - { - return (VIMS_MODE_INVALIDATE); - } - else - { - return (ui32Reg & VIMS_STAT_MODE_M); - } -} -//! @} diff --git a/third_party/ti/devices/cc26x0/rom/driverlib.elf b/third_party/ti/devices/cc26x0/rom/driverlib.elf deleted file mode 100644 index 95e00d402b01ecef244049f8e9435a7ccb870ed1..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 254872 zcmeFadwf*Y)i=J+nVDpg4CG`IFklQblYmJGk_6PKC}(Dp$xITGkN|>GGfB8ikjrpU zv5$Qi6g6JjVrwn6)}pN~y*&a2t3J{R2nuT331|yXwWh5V8mvwrm;-^#`(5WUGnp{9 z{e6DV``63ovvT%Yd+oK>-h1t}uL+x~>s=hjG3_7EiWp(H&t`(LSI3F~JY$BL%mR85 z8_&iuB(o@gZ8a0t1MZ3gO^)`}@(9<`~kkRZCZIpmfKY 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a/third_party/ti/devices/cc26x0/rom/readme.txt b/third_party/ti/devices/cc26x0/rom/readme.txt deleted file mode 100644 index 2513432e5..000000000 --- a/third_party/ti/devices/cc26x0/rom/readme.txt +++ /dev/null @@ -1,32 +0,0 @@ -Debugging sessions in IAR Embedded Workbench (IAR) and Code Composer Studio (CCS) -can load symbol information covering the code in ROM. -Symbols are loaded by selecting the ELF files found in the same folder as this -readme.txt file. -In addition the source code for the driverlib functions in ROM is found in the -driverlib.c file in this folder. - -Loading ROM code symbols in CCS debug session: -- Start a debug session in your project -- Select Run > Load > Add Symbols to create additional symbols -- Browse to and select each ELF file in this folder in the 'Program file' field -- Set the value of 0 in the 'Code offset' field for each ELF file -- If you enter a driverlib function in ROM during your debuging session and - get this information: - 'Can't find a source file at "..//driverlib.c"' - you can navigate to the driverlib.c file in this folder by selecting - the 'Locate File..' button. - -Loading ROM code symbols for use in IAR debug session: -- In your project select the following before starting debug session: - Project > Options.. > Debugger and then select the 'Images'-tab -- In the 'Images'-tab do the following for each of the ELF files - located in the same folder as this reame.txt file: - -- Select the 'Download extra image' box - -- Browse to the ELF file in the 'Path:' field - -- Set the value of 0 in the 'Offset:' field - -- Select the 'Debug info only' box -- If you during a debug session enters a driverlib function in ROM you will - be notified by this message: - 'Could not find following file: ..//driverlib.c' - Select the browse button and select the driverlib.c file located in this - folder. diff --git a/third_party/ti/devices/cc26x0/startup_files/ccfg.c b/third_party/ti/devices/cc26x0/startup_files/ccfg.c deleted file mode 100644 index ec6a6eae4..000000000 --- a/third_party/ti/devices/cc26x0/startup_files/ccfg.c +++ /dev/null @@ -1,500 +0,0 @@ -/****************************************************************************** -* Filename: ccfg.c -* Revised: $Date: 2017-07-31 14:52:44 +0200 (Mon, 31 Jul 2017) $ -* Revision: $Revision: 17856 $ -* -* Description: Customer Configuration for CC26x0 device family (HW rev 2). -* -* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __CCFC_C__ -#define __CCFC_C__ - -#include -#include "../inc/hw_types.h" -#include "../inc/hw_ccfg.h" -#include "../inc/hw_ccfg_simple_struct.h" - -//***************************************************************************** -// -// Introduction -// -// This file contains fields used by Boot ROM, startup code, and SW radio -// stacks to configure chip behavior. -// -// Fields are documented in more details in hw_ccfg.h and CCFG.html in -// DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG). -// -// PLEASE NOTE: -// It is not recommended to do modifications inside the ccfg.c file. -// This file is part of the CoreSDK release and future releases may have -// important modifications and new fields added without notice. -// The recommended method to modify the CCFG settings is to have your -// own .c file that defines the specific CCFG values to be -// overridden and finally including ccfg.c from the .c file. -// -// Example: -// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader -// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC -// //---- Use default values for all others ---- -// #include "/source/ti/devices//startup_files/ccfg.c" -// -//***************************************************************************** - -//***************************************************************************** -// -// Set the values of the individual bit fields. -// -//***************************************************************************** - -//##################################### -// Alternative DC/DC settings -//##################################### - -#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING -#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled -// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled -#endif - -#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN -#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V -#endif - -#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN -#define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Disable -// #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Enable -#endif - -#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK -#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x2 // 39mA -#endif - -//##################################### -// XOSC override settings -//##################################### - -#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR -// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override -#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override -#endif - -#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT -#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0 -#endif - -#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET -#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0 -#endif - -#ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START -#define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us -#endif - -//##################################### -// Power settings -//##################################### - -#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA -#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation) -#endif - -#ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE -#define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown -// #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown -#endif - -#ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE -#define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode -// #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode -#endif - -#ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL -// #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V -#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode) -#endif - -#ifndef SET_CCFG_MODE_CONF_VDDR_CAP -#define SET_CCFG_MODE_CONF_VDDR_CAP 0x3A // Unsigned 8-bit integer representing the min. decoupling capacitance on VDDR in units of 100nF -#endif - -#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC -#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default) -// #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled -#endif - -//##################################### -// Clock settings -//##################################### - -#ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION -// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from High Frequency XOSC -// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock -#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC -// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC -#endif - -#ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD -// #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta -#define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta -#endif - -#ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA -#define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value -#endif - -#ifndef SET_CCFG_EXT_LF_CLK_DIO -#define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock -#endif - -#ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT -#define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency -#endif - -//##################################### -// Special HF clock source setting -//##################################### -#ifndef SET_CCFG_MODE_CONF_XOSC_FREQ -// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // Use HPOSC as HF source (if executing on a HPOSC chip, otherwise using default (=0x3)) -// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal -#define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (default) -#endif - -//##################################### -// Bootloader settings -//##################################### - -#ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE -#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader -// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader -#endif - -#ifndef SET_CCFG_BL_CONFIG_BL_LEVEL -// #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor -#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor -#endif - -#ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER -#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor -#endif - -#ifndef SET_CCFG_BL_CONFIG_BL_ENABLE -// #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor -#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor -#endif - -//##################################### -// Debug access settings -//##################################### - -#ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE -#define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option. -// #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock code -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE -// #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled -#define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE -#define SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE 0x00 // Access disabled -// #define SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE -// #define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled -#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE -#define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled -// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE -#define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled -// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE -#define SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE 0x00 // Access disabled -// #define SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -//##################################### -// Alternative IEEE 802.15.4 MAC address -//##################################### -#ifndef SET_CCFG_IEEE_MAC_0 -#define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0] -#endif - -#ifndef SET_CCFG_IEEE_MAC_1 -#define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32] -#endif - -//##################################### -// Alternative BLE address -//##################################### -#ifndef SET_CCFG_IEEE_BLE_0 -#define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0] -#endif - -#ifndef SET_CCFG_IEEE_BLE_1 -#define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32] -#endif - -//##################################### -// Flash erase settings -//##################################### - -#ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N -// #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored -#define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW -#endif - -#ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N -// #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function -#define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function -#endif - -//##################################### -// Flash image valid -//##################################### -#ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID -#define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image is valid -// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID // Flash image is invalid. ROM boot loader is called. -#endif - -//##################################### -// Flash sector write protection -//##################################### -#ifndef SET_CCFG_CCFG_PROT_31_0 -#define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF -#endif - -#ifndef SET_CCFG_CCFG_PROT_63_32 -#define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF -#endif - -#ifndef SET_CCFG_CCFG_PROT_95_64 -#define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF -#endif - -#ifndef SET_CCFG_CCFG_PROT_127_96 -#define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF -#endif - -//##################################### -// Select between cache or GPRAM -//##################################### -#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM -// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF -#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable) -#endif - -//##################################### -// Select TCXO -//##################################### -#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO -#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 // Disable TCXO -// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x0 // Enable TXCO -#endif - -//***************************************************************************** -// -// CCFG values that should not be modified. -// -//***************************************************************************** -#define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058 -#define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M >> CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S) - -#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1 -#define SET_CCFG_MODE_CONF_RTC_COMP 0x1 -#define SET_CCFG_MODE_CONF_HF_COMP 0x1 - -#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF -#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF -#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF -#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF - -#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF -#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF -#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF -#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF - -#define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF -#define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF -#define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF - -#define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF -#define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF -#define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF - -//***************************************************************************** -// -// Concatenate bit fields to words. -// DO NOT EDIT! -// -//***************************************************************************** -#define DEFAULT_CCFG_EXT_LF_CLK ( \ - ((((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO )) << CCFG_EXT_LF_CLK_DIO_S ) | ~CCFG_EXT_LF_CLK_DIO_M ) & \ - ((((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT )) << CCFG_EXT_LF_CLK_RTC_INCREMENT_S ) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) ) - -#define DEFAULT_CCFG_MODE_CONF_1 ( \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN )) << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN )) << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK )) << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT )) << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET )) << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START )) << CCFG_MODE_CONF_1_XOSC_MAX_START_S ) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) ) - -#define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG )) << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS )) << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M ) & \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) ) - -#define DEFAULT_CCFG_MODE_CONF ( \ - ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE )) << CCFG_MODE_CONF_DCDC_RECHARGE_S ) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE )) << CCFG_MODE_CONF_DCDC_ACTIVE_S ) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD )) << CCFG_MODE_CONF_VDDR_EXT_LOAD_S ) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL )) << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S ) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION )) << CCFG_MODE_CONF_SCLK_LF_OPTION_S ) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP )) << CCFG_MODE_CONF_RTC_COMP_S ) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ )) << CCFG_MODE_CONF_XOSC_FREQ_S ) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD )) << CCFG_MODE_CONF_XOSC_CAP_MOD_S ) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP )) << CCFG_MODE_CONF_HF_COMP_S ) | ~CCFG_MODE_CONF_HF_COMP_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA )) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_CAP )) << CCFG_MODE_CONF_VDDR_CAP_S ) | ~CCFG_MODE_CONF_VDDR_CAP_M ) ) - -#define DEFAULT_CCFG_VOLT_LOAD_0 ( \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) ) - -#define DEFAULT_CCFG_VOLT_LOAD_1 ( \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) ) - -#define DEFAULT_CCFG_RTC_OFFSET ( \ - ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 )) << CCFG_RTC_OFFSET_RTC_COMP_P0_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \ - ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 )) << CCFG_RTC_OFFSET_RTC_COMP_P1_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \ - ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 )) << CCFG_RTC_OFFSET_RTC_COMP_P2_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) ) - -#define DEFAULT_CCFG_FREQ_OFFSET ( \ - ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 )) << CCFG_FREQ_OFFSET_HF_COMP_P0_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \ - ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 )) << CCFG_FREQ_OFFSET_HF_COMP_P1_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \ - ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 )) << CCFG_FREQ_OFFSET_HF_COMP_P2_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) ) - -#define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0 -#define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1 -#define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0 -#define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1 - -#define DEFAULT_CCFG_BL_CONFIG ( \ - ((((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE )) << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S ) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \ - ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL )) << CCFG_BL_CONFIG_BL_LEVEL_S ) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \ - ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER )) << CCFG_BL_CONFIG_BL_PIN_NUMBER_S ) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \ - ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE )) << CCFG_BL_CONFIG_BL_ENABLE_S ) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) ) - -#define DEFAULT_CCFG_ERASE_CONF ( \ - ((((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N )) << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \ - ((((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N )) << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) ) - -#define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \ - ((((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE )) << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S ) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) ) - -#define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M ) & \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) ) - -#define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M ) ) - -#define DEFAULT_CCFG_IMAGE_VALID_CONF SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID - -#define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0 -#define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32 -#define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64 -#define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96 - -//***************************************************************************** -// -// Customer Configuration Area in Lock Page -// -//***************************************************************************** -#if defined(__IAR_SYSTEMS_ICC__) -__root const ccfg_t __ccfg @ ".ccfg" = -#elif defined(__TI_COMPILER_VERSION__) -#pragma DATA_SECTION(__ccfg, ".ccfg") -#pragma RETAIN(__ccfg) -const ccfg_t __ccfg = -#else -const ccfg_t __ccfg __attribute__((section(".ccfg"))) __attribute__((used)) = -#endif -{ // Mapped to address - DEFAULT_CCFG_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last - DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH. - DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size) - DEFAULT_CCFG_MODE_CONF , // 0x50003FB4 - DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8 - DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC - DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0 - DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4 - DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8 - DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC - DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0 - DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4 - DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8 - DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC - DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0 - DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4 - DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8 - DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC - DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0 - DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4 - DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8 - DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC -}; - -#endif // __CCFC_C__ diff --git a/third_party/ti/devices/cc26x0/startup_files/startup_ccs.c b/third_party/ti/devices/cc26x0/startup_files/startup_ccs.c deleted file mode 100644 index 4811e6cdf..000000000 --- a/third_party/ti/devices/cc26x0/startup_files/startup_ccs.c +++ /dev/null @@ -1,230 +0,0 @@ -/****************************************************************************** -* Filename: startup_ccs.c -* Revised: $Date: 2017-02-03 19:16:24 +0100 (Fri, 03 Feb 2017) $ -* Revision: $Revision: 17634 $ -* -* Description: Startup code for CC26x0 rev2 device family for use with CCS. -* -* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - - -//***************************************************************************** -// -// Check if compiler is CCS -// -//***************************************************************************** -#if !(defined(__TI_COMPILER_VERSION__)) -#error "startup_ccs.c: Unsupported compiler!" -#endif - -#include "../inc/hw_types.h" -#include "../driverlib/setup.h" - - -//***************************************************************************** -// -//! Forward declaration of the reset ISR and the default fault handlers. -// -//***************************************************************************** -void ResetISR( void ); -static void NmiSR( void ); -static void FaultISR( void ); -static void IntDefaultHandler( void ); -extern int main(void); - - -//***************************************************************************** -// -//! The entry point for the application startup code. -// -//***************************************************************************** -extern void _c_int00(void); - - -//***************************************************************************** -// -// CCS: Linker variable that marks the top of the stack. -// -//***************************************************************************** -extern unsigned long __STACK_END; - - -//! The vector table. Note that the proper constructs must be placed on this to -//! ensure that it ends up at physical address 0x0000.0000 or at the start of -//! the program if located at a start address other than 0. -// -//***************************************************************************** -#pragma DATA_SECTION(g_pfnVectors, ".intvecs") -void (* const g_pfnVectors[])(void) = -{ - (void (*)(void))((unsigned long)&__STACK_END), - // 0 The initial stack pointer - ResetISR, // 1 The reset handler - NmiSR, // 2 The NMI handler - FaultISR, // 3 The hard fault handler - IntDefaultHandler, // 4 The MPU fault handler - IntDefaultHandler, // 5 The bus fault handler - IntDefaultHandler, // 6 The usage fault handler - 0, // 7 Reserved - 0, // 8 Reserved - 0, // 9 Reserved - 0, // 10 Reserved - IntDefaultHandler, // 11 SVCall handler - IntDefaultHandler, // 12 Debug monitor handler - 0, // 13 Reserved - IntDefaultHandler, // 14 The PendSV handler - IntDefaultHandler, // 15 The SysTick handler - //--- External interrupts --- - IntDefaultHandler, // 16 AON edge detect - IntDefaultHandler, // 17 I2C - IntDefaultHandler, // 18 RF Core Command & Packet Engine 1 - IntDefaultHandler, // 19 Reserved - IntDefaultHandler, // 20 AON RTC - IntDefaultHandler, // 21 UART0 Rx and Tx - IntDefaultHandler, // 22 AUX software event 0 - IntDefaultHandler, // 23 SSI0 Rx and Tx - IntDefaultHandler, // 24 SSI1 Rx and Tx - IntDefaultHandler, // 25 RF Core Command & Packet Engine 0 - IntDefaultHandler, // 26 RF Core Hardware - IntDefaultHandler, // 27 RF Core Command Acknowledge - IntDefaultHandler, // 28 I2S - IntDefaultHandler, // 29 AUX software event 1 - IntDefaultHandler, // 30 Watchdog timer - IntDefaultHandler, // 31 Timer 0 subtimer A - IntDefaultHandler, // 32 Timer 0 subtimer B - IntDefaultHandler, // 33 Timer 1 subtimer A - IntDefaultHandler, // 34 Timer 1 subtimer B - IntDefaultHandler, // 35 Timer 2 subtimer A - IntDefaultHandler, // 36 Timer 2 subtimer B - IntDefaultHandler, // 37 Timer 3 subtimer A - IntDefaultHandler, // 38 Timer 3 subtimer B - IntDefaultHandler, // 39 Crypto Core Result available - IntDefaultHandler, // 40 uDMA Software - IntDefaultHandler, // 41 uDMA Error - IntDefaultHandler, // 42 Flash controller - IntDefaultHandler, // 43 Software Event 0 - IntDefaultHandler, // 44 AUX combined event - IntDefaultHandler, // 45 AON programmable 0 - IntDefaultHandler, // 46 Dynamic Programmable interrupt - // source (Default: PRCM) - IntDefaultHandler, // 47 AUX Comparator A - IntDefaultHandler, // 48 AUX ADC new sample or ADC DMA - // done, ADC underflow, ADC overflow - IntDefaultHandler // 49 TRNG event -}; - - -//***************************************************************************** -// -//! This is the code that gets called when the processor first starts execution -//! following a reset event. Only the absolutely necessary set is performed, -//! after which the application supplied entry() routine is called. Any fancy -//! actions (such as making decisions based on the reset cause register, and -//! resetting the bits in that register) are left solely in the hands of the -//! application. -// -//***************************************************************************** -void -ResetISR(void) -{ - // - // Final trim of device - // - SetupTrimDevice(); - - // - // Jump to the CCS C Initialization Routine. - // - __asm(" .global _c_int00\n" - " b.w _c_int00"); - - // - // If we ever return signal Error - // - FaultISR(); -} - -//***************************************************************************** -// -//! This is the code that gets called when the processor receives a NMI. This -//! simply enters an infinite loop, preserving the system state for examination -//! by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -//! This is the code that gets called when the processor receives a fault -//! interrupt. This simply enters an infinite loop, preserving the system state -//! for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - - -//***************************************************************************** -// -//! This is the code that gets called when the processor receives an unexpected -//! interrupt. This simply enters an infinite loop, preserving the system state -//! for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/third_party/ti/devices/cc26x0/startup_files/startup_gcc.c b/third_party/ti/devices/cc26x0/startup_files/startup_gcc.c deleted file mode 100644 index 3a8a5692b..000000000 --- a/third_party/ti/devices/cc26x0/startup_files/startup_gcc.c +++ /dev/null @@ -1,313 +0,0 @@ -/****************************************************************************** -* Filename: startup_gcc.c -* Revised: $Date: 2017-05-03 09:38:30 +0200 (Wed, 03 May 2017) $ -* Revision: $Revision: 17770 $ -* -* Description: Startup code for CC26x0 rev2 device family for use with GCC. -* -* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -// Check if compiler is GNU Compiler -// -//***************************************************************************** -#if !(defined(__GNUC__)) -#error "startup_gcc.c: Unsupported compiler!" -#endif - -#include "../inc/hw_types.h" -#include "../driverlib/setup.h" - - -//***************************************************************************** -// -// Macro for weak symbol aliasing -// -//***************************************************************************** -#define WEAK_ALIAS(x) __attribute__ ((weak, alias(#x))) - -//***************************************************************************** -// -// Forward declaration of the reset ISR and the default fault handlers. -// -//***************************************************************************** -void ResetISR( void ); -static void NmiSRHandler( void ); -static void FaultISRHandler( void ); -static void IntDefaultHandler( void ); -extern int main( void ); - - -// Default interrupt handlers -void NmiSR(void) WEAK_ALIAS(NmiSRHandler); -void FaultISR(void) WEAK_ALIAS(FaultISRHandler); -void MPUFaultIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void BusFaultIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void UsageFaultIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void SVCallIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void DebugMonIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void PendSVIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void SysTickIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void GPIOIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void I2CIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void RFCCPE1IntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void AONRTCIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void UART0IntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void AUXSWEvent0IntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void SSI0IntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void SSI1IntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void RFCCPE0IntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void RFCHardwareIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void RFCCmdAckIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void I2SIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void AUXSWEvent1IntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void WatchdogIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void Timer0AIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void Timer0BIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void Timer1AIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void Timer1BIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void Timer2AIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void Timer2BIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void Timer3AIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void Timer3BIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void CryptoIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void uDMAIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void uDMAErrIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void FlashIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void SWEvent0IntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void AUXCombEventIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void AONProgIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void DynProgIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void AUXCompAIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void AUXADCIntHandler(void) WEAK_ALIAS(IntDefaultHandler); -void TRNGIntHandler(void) WEAK_ALIAS(IntDefaultHandler); - - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. -// -//***************************************************************************** -extern uint32_t _ldata; -extern uint32_t _data; -extern uint32_t _edata; -extern uint32_t _bss; -extern uint32_t _ebss; -extern uint32_t _estack; -extern uint32_t _init_array; -extern uint32_t _einit_array; - -//***************************************************************************** -// -//! The vector table. Note that the proper constructs must be placed on this to -//! ensure that it ends up at physical address 0x0000.0000 or at the start of -//! the program if located at a start address other than 0. -// -//***************************************************************************** -__attribute__ ((section(".vectors"), used)) -void (* const g_pfnVectors[])(void) = -{ - (void (*)(void))((unsigned long)&_estack), - // 0 The initial stack pointer - ResetISR, // 1 The reset handler - NmiSR, // 2 The NMI handler - FaultISR, // 3 The hard fault handler - MPUFaultIntHandler, // 4 The MPU fault handler - BusFaultIntHandler, // 5 The bus fault handler - UsageFaultIntHandler, // 6 The usage fault handler - 0, // 7 Reserved - 0, // 8 Reserved - 0, // 9 Reserved - 0, // 10 Reserved - SVCallIntHandler, // 11 SVCall handler - DebugMonIntHandler, // 12 Debug monitor handler - 0, // 13 Reserved - PendSVIntHandler, // 14 The PendSV handler - SysTickIntHandler, // 15 The SysTick handler - //--- External interrupts --- - GPIOIntHandler, // 16 AON edge detect - I2CIntHandler, // 17 I2C - RFCCPE1IntHandler, // 18 RF Core Command & Packet Engine 1 - IntDefaultHandler, // 19 Reserved - AONRTCIntHandler, // 20 AON RTC - UART0IntHandler, // 21 UART0 Rx and Tx - AUXSWEvent0IntHandler, // 22 AUX software event 0 - SSI0IntHandler, // 23 SSI0 Rx and Tx - SSI1IntHandler, // 24 SSI1 Rx and Tx - RFCCPE0IntHandler, // 25 RF Core Command & Packet Engine 0 - RFCHardwareIntHandler, // 26 RF Core Hardware - RFCCmdAckIntHandler, // 27 RF Core Command Acknowledge - I2SIntHandler, // 28 I2S - AUXSWEvent1IntHandler, // 29 AUX software event 1 - WatchdogIntHandler, // 30 Watchdog timer - Timer0AIntHandler, // 31 Timer 0 subtimer A - Timer0BIntHandler, // 32 Timer 0 subtimer B - Timer1AIntHandler, // 33 Timer 1 subtimer A - Timer1BIntHandler, // 34 Timer 1 subtimer B - Timer2AIntHandler, // 35 Timer 2 subtimer A - Timer2BIntHandler, // 36 Timer 2 subtimer B - Timer3AIntHandler, // 37 Timer 3 subtimer A - Timer3BIntHandler, // 38 Timer 3 subtimer B - CryptoIntHandler, // 39 Crypto Core Result available - uDMAIntHandler, // 40 uDMA Software - uDMAErrIntHandler, // 41 uDMA Error - FlashIntHandler, // 42 Flash controller - SWEvent0IntHandler, // 43 Software Event 0 - AUXCombEventIntHandler, // 44 AUX combined event - AONProgIntHandler, // 45 AON programmable 0 - DynProgIntHandler, // 46 Dynamic Programmable interrupt - // source (Default: PRCM) - AUXCompAIntHandler, // 47 AUX Comparator A - AUXADCIntHandler, // 48 AUX ADC new sample or ADC DMA - // done, ADC underflow, ADC overflow - TRNGIntHandler // 49 TRNG event -}; - -typedef void (*init_fn_t)(void); - -//***************************************************************************** -// -//! This is the code that gets called when the processor first starts execution -//! following a reset event. Only the absolutely necessary set is performed, -//! after which the application supplied entry() routine is called. Any fancy -//! actions (such as making decisions based on the reset cause register, and -//! resetting the bits in that register) are left solely in the hands of the -//! application. -// -//***************************************************************************** -void -ResetISR(void) -{ - uint32_t *pSrc; - uint32_t *pDest; - init_fn_t *fp; - - // - // Final trim of device - // - SetupTrimDevice(); - - // - // Copy the data segment initializers from FLASH to SRAM. - // - pSrc = &_ldata; - for(pDest = &_data; pDest < &_edata; ) - { - *pDest++ = *pSrc++; - } - - // - // Zero fill the bss segment. - // - __asm(" ldr r0, =_bss\n" - " ldr r1, =_ebss\n" - " mov r2, #0\n" - " .thumb_func\n" - "zero_loop:\n" - " cmp r0, r1\n" - " it lt\n" - " strlt r2, [r0], #4\n" - " blt zero_loop"); - - // C++ runtime initialization (BSS, Data, relocation, etc.) - for (fp = (init_fn_t *)&_init_array; fp < (init_fn_t *)&_einit_array; fp++) - { - (*fp)(); - } - - // - // Call the application's entry point. - // - main(); - - // - // If we ever return signal Error - // - FaultISR(); -} - -//***************************************************************************** -// -//! This is the code that gets called when the processor receives a NMI. This -//! simply enters an infinite loop, preserving the system state for examination -//! by a debugger. -// -//***************************************************************************** -static void -NmiSRHandler(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -//! This is the code that gets called when the processor receives a fault -//! interrupt. This simply enters an infinite loop, preserving the system state -//! for examination by a debugger. -// -//***************************************************************************** -static void -FaultISRHandler(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -//! This is the code that gets called when the processor receives an unexpected -//! interrupt. This simply enters an infinite loop, preserving the system state -//! for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/third_party/ti/devices/cc26x0/startup_files/startup_iar.c b/third_party/ti/devices/cc26x0/startup_files/startup_iar.c deleted file mode 100644 index 2813cb730..000000000 --- a/third_party/ti/devices/cc26x0/startup_files/startup_iar.c +++ /dev/null @@ -1,320 +0,0 @@ -/****************************************************************************** -* Filename: startup_iar.c -* Revised: $Date: 2017-02-03 19:16:24 +0100 (Fri, 03 Feb 2017) $ -* Revision: $Revision: 17634 $ -* -* Description: Startup code for CC26x0 rev2 device family for use with IAR. -* -* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - - -//***************************************************************************** -// -// Check if compiler is IAR -// -//***************************************************************************** -#if !(defined(__IAR_SYSTEMS_ICC__)) -#error "startup_iar.c: Unsupported compiler!" -#endif - - -// We need intrinsic functions for IAR (if used in source code) -#include -#include "../inc/hw_types.h" -#include "../driverlib/setup.h" - - -//***************************************************************************** -// -//! Forward declaration of the reset ISR and the default fault handlers. -// -//***************************************************************************** -void ResetISR( void ); -static void NmiSRHandler( void ); -static void FaultISRHandler( void ); -static void IntDefaultHandler( void ); -extern int main( void ); - -extern void NmiSR( void ); -extern void FaultISR( void ); -extern void MPUFaultIntHandler( void ); -extern void BusFaultIntHandler( void ); -extern void UsageFaultIntHandler( void ); -extern void SVCallIntHandler( void ); -extern void DebugMonIntHandler( void ); -extern void PendSVIntHandler( void ); -extern void SysTickIntHandler( void ); -extern void GPIOIntHandler( void ); -extern void I2CIntHandler( void ); -extern void RFCCPE1IntHandler( void ); -extern void AONRTCIntHandler( void ); -extern void UART0IntHandler( void ); -extern void AUXSWEvent0IntHandler( void ); -extern void SSI0IntHandler( void ); -extern void SSI1IntHandler( void ); -extern void RFCCPE0IntHandler( void ); -extern void RFCHardwareIntHandler( void ); -extern void RFCCmdAckIntHandler( void ); -extern void I2SIntHandler( void ); -extern void AUXSWEvent1IntHandler( void ); -extern void WatchdogIntHandler( void ); -extern void Timer0AIntHandler( void ); -extern void Timer0BIntHandler( void ); -extern void Timer1AIntHandler( void ); -extern void Timer1BIntHandler( void ); -extern void Timer2AIntHandler( void ); -extern void Timer2BIntHandler( void ); -extern void Timer3AIntHandler( void ); -extern void Timer3BIntHandler( void ); -extern void CryptoIntHandler( void ); -extern void uDMAIntHandler( void ); -extern void uDMAErrIntHandler( void ); -extern void FlashIntHandler( void ); -extern void SWEvent0IntHandler( void ); -extern void AUXCombEventIntHandler( void ); -extern void AONProgIntHandler( void ); -extern void DynProgIntHandler( void ); -extern void AUXCompAIntHandler( void ); -extern void AUXADCIntHandler( void ); -extern void TRNGIntHandler( void ); - -// Default interrupt handlers -#pragma weak NmiSR = NmiSRHandler -#pragma weak FaultISR = FaultISRHandler -#pragma weak MPUFaultIntHandler = IntDefaultHandler -#pragma weak BusFaultIntHandler = IntDefaultHandler -#pragma weak UsageFaultIntHandler = IntDefaultHandler -#pragma weak SVCallIntHandler = IntDefaultHandler -#pragma weak DebugMonIntHandler = IntDefaultHandler -#pragma weak PendSVIntHandler = IntDefaultHandler -#pragma weak SysTickIntHandler = IntDefaultHandler -#pragma weak GPIOIntHandler = IntDefaultHandler -#pragma weak I2CIntHandler = IntDefaultHandler -#pragma weak RFCCPE1IntHandler = IntDefaultHandler -#pragma weak AONRTCIntHandler = IntDefaultHandler -#pragma weak UART0IntHandler = IntDefaultHandler -#pragma weak AUXSWEvent0IntHandler = IntDefaultHandler -#pragma weak SSI0IntHandler = IntDefaultHandler -#pragma weak SSI1IntHandler = IntDefaultHandler -#pragma weak RFCCPE0IntHandler = IntDefaultHandler -#pragma weak RFCHardwareIntHandler = IntDefaultHandler -#pragma weak RFCCmdAckIntHandler = IntDefaultHandler -#pragma weak I2SIntHandler = IntDefaultHandler -#pragma weak AUXSWEvent1IntHandler = IntDefaultHandler -#pragma weak WatchdogIntHandler = IntDefaultHandler -#pragma weak Timer0AIntHandler = IntDefaultHandler -#pragma weak Timer0BIntHandler = IntDefaultHandler -#pragma weak Timer1AIntHandler = IntDefaultHandler -#pragma weak Timer1BIntHandler = IntDefaultHandler -#pragma weak Timer2AIntHandler = IntDefaultHandler -#pragma weak Timer2BIntHandler = IntDefaultHandler -#pragma weak Timer3AIntHandler = IntDefaultHandler -#pragma weak Timer3BIntHandler = IntDefaultHandler -#pragma weak CryptoIntHandler = IntDefaultHandler -#pragma weak uDMAIntHandler = IntDefaultHandler -#pragma weak uDMAErrIntHandler = IntDefaultHandler -#pragma weak FlashIntHandler = IntDefaultHandler -#pragma weak SWEvent0IntHandler = IntDefaultHandler -#pragma weak AUXCombEventIntHandler = IntDefaultHandler -#pragma weak AONProgIntHandler = IntDefaultHandler -#pragma weak DynProgIntHandler = IntDefaultHandler -#pragma weak AUXCompAIntHandler = IntDefaultHandler -#pragma weak AUXADCIntHandler = IntDefaultHandler -#pragma weak TRNGIntHandler = IntDefaultHandler - -//***************************************************************************** -// -//! The entry point for the application startup code. -// -//***************************************************************************** -extern void __iar_program_start(void); - -//***************************************************************************** -// -//! Get stack start (highest address) symbol from linker file. -// -//***************************************************************************** -extern const void* STACK_TOP; - -// It is required to place something in the CSTACK segment to get the stack -// check feature in IAR to work as expected -__root static void* dummy_stack @ ".stack"; - - -//***************************************************************************** -// -//! The vector table. Note that the proper constructs must be placed on this to -//! ensure that it ends up at physical address 0x0000.0000 or at the start of -//! the program if located at a start address other than 0. -// -//***************************************************************************** -__root void (* const __vector_table[])(void) @ ".intvec" = -{ - (void (*)(void))&STACK_TOP, // 0 The initial stack pointer - ResetISR, // 1 The reset handler - NmiSR, // 2 The NMI handler - FaultISR, // 3 The hard fault handler - MPUFaultIntHandler, // 4 The MPU fault handler - BusFaultIntHandler, // 5 The bus fault handler - UsageFaultIntHandler, // 6 The usage fault handler - 0, // 7 Reserved - 0, // 8 Reserved - 0, // 9 Reserved - 0, // 10 Reserved - SVCallIntHandler, // 11 SVCall handler - DebugMonIntHandler, // 12 Debug monitor handler - 0, // 13 Reserved - PendSVIntHandler, // 14 The PendSV handler - SysTickIntHandler, // 15 The SysTick handler - //--- External interrupts --- - GPIOIntHandler, // 16 AON edge detect - I2CIntHandler, // 17 I2C - RFCCPE1IntHandler, // 18 RF Core Command & Packet Engine 1 - IntDefaultHandler, // 19 Reserved - AONRTCIntHandler, // 20 AON RTC - UART0IntHandler, // 21 UART0 Rx and Tx - AUXSWEvent0IntHandler, // 22 AUX software event 0 - SSI0IntHandler, // 23 SSI0 Rx and Tx - SSI1IntHandler, // 24 SSI1 Rx and Tx - RFCCPE0IntHandler, // 25 RF Core Command & Packet Engine 0 - RFCHardwareIntHandler, // 26 RF Core Hardware - RFCCmdAckIntHandler, // 27 RF Core Command Acknowledge - I2SIntHandler, // 28 I2S - AUXSWEvent1IntHandler, // 29 AUX software event 1 - WatchdogIntHandler, // 30 Watchdog timer - Timer0AIntHandler, // 31 Timer 0 subtimer A - Timer0BIntHandler, // 32 Timer 0 subtimer B - Timer1AIntHandler, // 33 Timer 1 subtimer A - Timer1BIntHandler, // 34 Timer 1 subtimer B - Timer2AIntHandler, // 35 Timer 2 subtimer A - Timer2BIntHandler, // 36 Timer 2 subtimer B - Timer3AIntHandler, // 37 Timer 3 subtimer A - Timer3BIntHandler, // 38 Timer 3 subtimer B - CryptoIntHandler, // 39 Crypto Core Result available - uDMAIntHandler, // 40 uDMA Software - uDMAErrIntHandler, // 41 uDMA Error - FlashIntHandler, // 42 Flash controller - SWEvent0IntHandler, // 43 Software Event 0 - AUXCombEventIntHandler, // 44 AUX combined event - AONProgIntHandler, // 45 AON programmable 0 - DynProgIntHandler, // 46 Dynamic Programmable interrupt - // source (Default: PRCM) - AUXCompAIntHandler, // 47 AUX Comparator A - AUXADCIntHandler, // 48 AUX ADC new sample or ADC DMA - // done, ADC underflow, ADC overflow - TRNGIntHandler // 49 TRNG event -}; - - -//***************************************************************************** -// -//! This is the code that gets called when the processor first starts execution -//! following a reset event. Only the absolutely necessary set is performed, -//! after which the application supplied entry() routine is called. Any fancy -//! actions (such as making decisions based on the reset cause register, and -//! resetting the bits in that register) are left solely in the hands of the -//! application. -// -//***************************************************************************** -void -ResetISR(void) -{ - // - // Final trim of device - // - SetupTrimDevice(); - - // - // Jump to IAR initialization routine - // - __iar_program_start(); - - // - // If we ever return signal Error - // - FaultISR(); -} - -//***************************************************************************** -// -//! This is the code that gets called when the processor receives a NMI. This -//! simply enters an infinite loop, preserving the system state for examination -//! by a debugger. -// -//***************************************************************************** -static void -NmiSRHandler(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -//! This is the code that gets called when the processor receives a fault -//! interrupt. This simply enters an infinite loop, preserving the system state -//! for examination by a debugger. -// -//***************************************************************************** -static void -FaultISRHandler(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -//! This is the code that gets called when the processor receives an unexpected -//! interrupt. This simply enters an infinite loop, preserving the system state -//! for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/third_party/ti/devices/cc26x0/startup_files/startup_keil.s b/third_party/ti/devices/cc26x0/startup_files/startup_keil.s deleted file mode 100644 index 04765e21c..000000000 --- a/third_party/ti/devices/cc26x0/startup_files/startup_keil.s +++ /dev/null @@ -1,296 +0,0 @@ -; /****************************************************************************** -; * Filename: startup_keil.c -; * Revised: $Date: 2016-09-21 10:57:23 +0200 (Wed, 21 Sep 2016) $ -; * Revision: $Revision: 17335 $ -; * -; * Description: Startup code for CC26xx device family for use with KEIL. -; * -; * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -; * -; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions -; * are met: -; * -; * Redistributions of source code must retain the above copyright -; * notice, this list of conditions and the following disclaimer. -; * -; * Redistributions in binary form must reproduce the above copyright -; * notice, this list of conditions and the following disclaimer in the -; * documentation and/or other materials provided with the distribution. -; * -; * Neither the name of Texas Instruments Incorporated nor the names of -; * its contributors may be used to endorse or promote products derived -; * from this software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -; * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -; * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -; * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -; * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -; * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; ******************************************************************************/ -;// <<< Use Configuration Wizard in Context Menu >>> -;*/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB -;// <<< end of configuration section >>> - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; 0 Top of Stack - DCD ResetISR ; 1 Reset Handler - DCD NmiSR ; 2 NMI Handler - DCD FaultISR ; 3 Hard Fault Handler - DCD MPUFaultIntHandler ; 4 The MPU fault handler - DCD BusFaultIntHandler ; 5 The bus fault handler - DCD UsageFaultIntHandler ; 6 The usage fault handler - DCD 0 ; 7 Reserved - DCD 0 ; 8 Reserved - DCD 0 ; 9 Reserved - DCD 0 ; 10 Reserved - DCD SVCallIntHandler ; 11 SVCall Handler - DCD DebugMonIntHandler ; 12 Debug monitor handler - DCD 0 ; 13 Reserved - DCD PendSVIntHandler ; 14 PendSV Handler - DCD SysTickIntHandler ; 15 SysTick Handler - - ; External Interrupts - DCD GPIOIntHandler ; 16 AON edge detect - DCD I2CIntHandler ; 17 I2C - DCD RFCCPE1IntHandler ; 18 RF Core Command & Packet Engine 1 - DCD IntDefaultHandler ; 19 Reserved - DCD AONRTCIntHandler ; 20 AON RTC - DCD UART0IntHandler ; 21 UART0 Rx and Tx - DCD IntDefaultHandler ; 22 AUX software event 0 - DCD SSI0IntHandler ; 23 SSI0 Rx and Tx - DCD SSI1IntHandler ; 24 SSI1 Rx and Tx - DCD RFCCPE0IntHandler ; 25 RF Core Command & Packet Engine 0 - DCD RFCHardwareIntHandler ; 26 RF Core Hardware - DCD RFCCmdAckIntHandler ; 27 RF Core Command Acknowledge - DCD I2SIntHandler ; 28 I2S - DCD IntDefaultHandler ; 29 AUX software event 1 - DCD WatchdogIntHandler ; 30 Watchdog timer - DCD Timer0AIntHandler ; 31 Timer 0 subtimer A - DCD Timer0BIntHandler ; 32 Timer 0 subtimer B - DCD Timer1AIntHandler ; 33 Timer 1 subtimer A - DCD Timer1BIntHandler ; 34 Timer 1 subtimer B - DCD Timer2AIntHandler ; 35 Timer 2 subtimer A - DCD Timer2BIntHandler ; 36 Timer 2 subtimer B - DCD Timer3AIntHandler ; 37 Timer 3 subtimer A - DCD Timer3BIntHandler ; 38 Timer 3 subtimer B - DCD CryptoIntHandler ; 39 Crypto Core Result available - DCD uDMAIntHandler ; 40 uDMA Software - DCD uDMAErrIntHandler ; 41 uDMA Error - DCD FlashIntHandler ; 42 Flash controller - DCD SWEvent0IntHandler ; 43 Software Event 0 - DCD AUXCombEventIntHandler ; 44 AUX combined event - DCD AONProgIntHandler ; 45 AON programmable 0 - DCD DynProgIntHandler ; 46 Dynamic Programmable interrupt - ; source (Default: PRCM) - DCD AUXCompAIntHandler ; 47 AUX Comparator A - DCD AUXADCIntHandler ; 48 AUX ADC new sample or ADC DMA - ; done, ADC underflow, ADC overflow - DCD TRNGIntHandler ; 49 TRNG event -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -ResetISR PROC - EXPORT ResetISR [WEAK] - IMPORT NOROM_SetupTrimDevice - IMPORT __main - ; Final trim of device (setup.c in CC26xxWare) - LDR R0, =NOROM_SetupTrimDevice - BLX R0 - ; Jump to initialization routine - LDR R0, =__main - BX R0 - ; If we ever return, signal error - LDR R0, =FaultISR - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NmiSR PROC - EXPORT NmiSR [WEAK] - B . - ENDP -FaultISR PROC - EXPORT FaultISR [WEAK] - B . - ENDP -MPUFaultIntHandler\ - PROC - EXPORT MPUFaultIntHandler [WEAK] - B . - ENDP -BusFaultIntHandler\ - PROC - EXPORT BusFaultIntHandler [WEAK] - B . - ENDP -UsageFaultIntHandler\ - PROC - EXPORT UsageFaultIntHandler [WEAK] - B . - ENDP -SVCallIntHandler\ - PROC - EXPORT SVCallIntHandler [WEAK] - B . - ENDP -DebugMonIntHandler\ - PROC - EXPORT DebugMonIntHandler [WEAK] - B . - ENDP -PendSVIntHandler\ - PROC - EXPORT PendSVIntHandler [WEAK] - B . - ENDP -SysTickIntHandler\ - PROC - EXPORT SysTickIntHandler [WEAK] - B . - ENDP - -IntDefaultHandler\ - PROC - EXPORT GPIOIntHandler [WEAK] - EXPORT I2CIntHandler [WEAK] - EXPORT RFCCPE1IntHandler [WEAK] - EXPORT AONRTCIntHandler [WEAK] - EXPORT UART0IntHandler [WEAK] - EXPORT SSI0IntHandler [WEAK] - EXPORT SSI1IntHandler [WEAK] - EXPORT RFCCPE0IntHandler [WEAK] - EXPORT RFCHardwareIntHandler [WEAK] - EXPORT RFCCmdAckIntHandler [WEAK] - EXPORT I2SIntHandler [WEAK] - EXPORT WatchdogIntHandler [WEAK] - EXPORT Timer0AIntHandler [WEAK] - EXPORT Timer0BIntHandler [WEAK] - EXPORT Timer1AIntHandler [WEAK] - EXPORT Timer1BIntHandler [WEAK] - EXPORT Timer2AIntHandler [WEAK] - EXPORT Timer2BIntHandler [WEAK] - EXPORT Timer3AIntHandler [WEAK] - EXPORT Timer3BIntHandler [WEAK] - EXPORT CryptoIntHandler [WEAK] - EXPORT uDMAIntHandler [WEAK] - EXPORT uDMAErrIntHandler [WEAK] - EXPORT FlashIntHandler [WEAK] - EXPORT SWEvent0IntHandler [WEAK] - EXPORT AUXCombEventIntHandler [WEAK] - EXPORT AONProgIntHandler [WEAK] - EXPORT DynProgIntHandler [WEAK] - EXPORT AUXCompAIntHandler [WEAK] - EXPORT AUXADCIntHandler [WEAK] - EXPORT TRNGIntHandler [WEAK] -GPIOIntHandler -I2CIntHandler -RFCCPE1IntHandler -AONRTCIntHandler -UART0IntHandler -SSI0IntHandler -SSI1IntHandler -RFCCPE0IntHandler -RFCHardwareIntHandler -RFCCmdAckIntHandler -I2SIntHandler -WatchdogIntHandler -Timer0AIntHandler -Timer0BIntHandler -Timer1AIntHandler -Timer1BIntHandler -Timer2AIntHandler -Timer2BIntHandler -Timer3AIntHandler -Timer3BIntHandler -CryptoIntHandler -uDMAIntHandler -uDMAErrIntHandler -FlashIntHandler -SWEvent0IntHandler -AUXCombEventIntHandler -AONProgIntHandler -DynProgIntHandler -AUXCompAIntHandler -AUXADCIntHandler -TRNGIntHandler - B . - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/third_party/ti/manifest_driverlib_cc13xx_cc26xx_3_xx_xx.html b/third_party/ti/manifest_driverlib_cc13xx_cc26xx_3_xx_xx.html deleted file mode 100644 index 9dd7c52da..000000000 --- a/third_party/ti/manifest_driverlib_cc13xx_cc26xx_3_xx_xx.html +++ /dev/null @@ -1,445 +0,0 @@ - - - - - - - Manifest File - - - - - -
    -
    - -
    -
    -
    -
    -

    - -Driverlib_CC13xx_CC26xx Manifest - -

    - -

    - -04-20-2017 - -

    - - -

    - -Manifest ID - SRAS00003869 - -

    -
    -

    Legend

    -

    (explanation of the fields in the Manifest Table below)

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    -Software Name - -The name of the application or file -
    -Version - -Version of the application or file -
    -License Type - -Type of license(s) under which TI will be providing -software to the licensee (e.g. BSD-3-Clause, GPL-2.0, TI TSPA License, TI -Commercial License). The license could be under Commercial terms or Open Source. See Open Source Reference License Disclaimer in -the Disclaimers Section. Whenever possible, TI will use an SPDX Short Identifier for an Open Source -License. TI Commercial license terms are not usually included in the manifest and are conveyed through a variety -of means such as a clickwrap license upon install, -a signed license agreement and so forth. -
    -Location - -The directory name and path on the media or a specific file where the Software is located. Typically fully qualified path names -are not used and instead the relevant top level directory of the application is given. -A notation often used in the manifests is [as installed]/directory/*. Note that the asterisk implies that all -files under that directory are licensed as the License Type field denotes. Any exceptions to this will -generally be denoted as [as installed]/directory/* except as noted below which means as shown in subsequent rows of -the manifest. -
    -Delivered As - -This field will either be “Source”, “Binary” or “Source -and Binary” and is the primary form the content of the Software is delivered -in. If the Software is delivered in an archive format, this field -applies to the contents of the archive. If the word Limited is used -with Source, as in “Limited Source” or “Limited Source and Binary” then -only portions of the Source for the application are provided. -
    -Modified by TI - -This field will either be “Yes” or “No”. A “Yes” means -TI has made changes to the Software. A “No” means TI has not made any -changes. Note: This field is not applicable for Software “Obtained -from” TI. -
    -Obtained from - -This field specifies from where or from whom TI obtained -the Software. It may be a URL to an Open Source site, a 3rd -party licensor, or TI. See Links Disclaimer in the Disclaimers -Section. -
    -
    -

    Disclaimers

    -

    Export Control Classification Number (ECCN)

    -

    Any use of ECCNs listed in the Manifest is at the user’s risk -and without recourse to TI. Your -company, as the exporter of record, is responsible for determining the -correct classification of any item at -the time of export. Any export classification by TI of Software is for -TI’s internal use only and shall not be construed as a representation -or warranty -regarding the proper export classification for such Software or whether -an export -license or other documentation is required for exporting such Software

    -

    Links in the Manifest

    -

    Any -links appearing on this Manifest -(for example in the “Obtained from” field) were verified at the time -the Manifest was created. TI makes no guarantee that any listed links -will -remain active in the future.

    -

    Open Source License References

    -

    Your company is responsible for confirming the -applicable license terms for any open source Software -listed in this Manifest that was not “Obtained from” TI. Any open -source license -specified in this Manifest for Software that was -not “Obtained from” TI is for TI’s internal use only and shall not be -construed as a representation or warranty regarding the proper open -source license terms -for such Software.

    -
    -

    Export Information

    -

    ECCN for Software included in this release:

    -Other ECCN: 5D992 -
    - - - - - -

    - Driverlib_CC13xx_CC26xx Manifest Table -

    - - -

    - - See the Legend above for a description of these columns. - -

    - -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Software NameVersionLicense TypeDelivered AsModified by TI
    - driverlib - - 3.xx.xx - - BSD-3-Clause - - Source and binary - - N/A - Location - driverlib, driverlib/bin -
    Obtained from - TI -
    - CC13xx/CC26xx RF patches - - 3.xx.xx - - BSD-3-Clause - - Source - - N/A - Location - rf_patches -
    Obtained from - TI -
    - CC13xx/CC26xx hardware header files - - 3.xx.xx - - BSD-3-Clause - - Source - - N/A - Location - inc -
    Obtained from - TI -
    - CC13xx/CC26xx startup files - - 3.xx.xx - - BSD-3-Clause - - Source - - N/A - Location - startup_files -
    Obtained from - TI -
    - CC13xx/CC26xx linker files - - 3.xx.xx - - BSD-3-Clause - - Source - - N/A - Location - linker_files -
    Obtained from - TI -
    - jquery.js - - 1.7.1 - - MIT - - Source - - No - Location - doc/driverlib -
    Obtained from - jquery.org -
    - ChaCha cipher - - 20080118 - - Public domain - - Source and binary - - Yes - Location - driverlib,driverlib/bin -
    Obtained from - http://cr.yp.to/chacha.html,2016-10-07 -
    - poly1305-donna,32 bit - - e6ad6e0(Mar 29 2016) - - MIT - - Source and binary - - Yes - Location - driverlib/sw_poly1305*,driverlib/bin -
    Obtained from - https://github.com/floodyberry/poly1305-donna,2016-10-07 -
    - -

    -

    -

    - -

    -

    Credits

    -




    -
    -

    Licenses

    -

    Driverlib_CC13xx_CC26xx Licenses




    BSD-3-Clause license:
    Copyright (c) 2016, Texas Instruments Incorporated
    All rights reserved.

    Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

    1) Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

    2) Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

    3) Neither the name of the ORGANIZATION nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


    MIT license for jquery:

    Copyright 2011, John Resig
    Copyright 2011, The Dojo Foundation
    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to deal
    in the Software without restriction, including without limitation the rights
    to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    copies of the Software, and to permit persons to whom the Software is
    furnished to do so, subject to the following conditions:
    The above copyright notice and this permission notice shall be included in
    all copies or substantial portions of the Software.
    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
    AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    THE SOFTWARE.
    MIT license for poly1305-donna:
    Copyright (c) 2016 Andrew Moon (floodberry @ github)
    Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
    The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.



    -
    -
    -

    TI is a global semiconductor design and manufacturing company. Innovate - with 100,000+ analog ICs and embedded processors, along with software, tools - and the industry's largest sales/support staff.

    -
    - \ No newline at end of file diff --git a/third_party/ti/release_notes_driverlib_cc13xx_cc26xx.html b/third_party/ti/release_notes_driverlib_cc13xx_cc26xx.html deleted file mode 100644 index 07ae5e637..000000000 --- a/third_party/ti/release_notes_driverlib_cc13xx_cc26xx.html +++ /dev/null @@ -1,2091 +0,0 @@ - - - - - - Release notes for driverlib_cc13xx_cc26xx - - - - - - - - - -
    - - Texas Instruments - - - Technology for Innovators -
    -

    Release notes for driverlib_cc13xx_cc26xx

    - Keyword used to group changes done: - - - - - - - - - - - -
    [RF_API] RF Application interface
    [RF_PATCH] RF Patches
    [RF_SETTING] RF Settings
    [HW_INC] Hardware interface description
    [DRV_API] Driverlib Application interface
    [DRV_SRC] Driverlib source code
    [DRV_DOC] Driverlib documentation
    [DRV_LIB] Prebuilt libraries
    - - -
    -

    driverlib_cc13xx_cc26xx_3_05_06_18894

    -
    - Release date: Feb 27, 2019
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2
      • -
        -
      • [RF_PATCH] CC13X2P/R, CC26X2: CPE patches had equal NWORD definitions, which this update fixes.
        • -
      • [RF_PATCH] CC13X2P/R, CC26X2: Updated BLE patches due to BLE tester failure.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] CC2640R2F: Updated BLE patches due to BLE tester failure.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_05_05_18873

    -
    - Release date: Feb 15, 2019
    - -

    New features

    -
      -
    • CC13x2_CC26x2 -
        -
      • [DRV_API] OSC: New API functions called OSC_IsHPOSCEnabledWithHfDerivedLfClock() and OSC_HPOSCRtcCompensate()have been added for support of future device variant with HPOSC.
        • -
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • None
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_05_04_18846

    -
    - Release date: Jan 31, 2019
    - -

    New features

    -
      -
    • CC26x0R2
      • - CC26x0
      - CC13x0
      -
        -
      • [DRV_API] AES: New API for AES crypto functions has been added by the aes.c and aes.h files.
        • -
      -
    • CC13x2_CC26x2 -
        -
      • [RF_PATCH] CC13X2R, CC13X2P, CC26X2: Multiprotocol patch including RTLS, implementing AoA/AoD for Bluetooth 5.1 and time-of-flight.
        • -
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC26x0R2
      • -
        -
      • [RF_PATCH] CC2640R2: Bug fix for Bluetooth CTE generic RX.
        • -
      • [RF_PATCH] CC2640R2: Updated time-of-flight patches (MCE, RFE and CPE) for CC2640R2, including new commandNo, fix for double buffer and removal of STIM compensation.
        • -
      -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_05_03_18798

    -
    - Release date: Dec 06, 2018
    - -

    New features

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_API] I2S: New static inline API function called I2SWclkCounterReset() has been added.
        • -
      • -
    • CC13x2_CC26x2
      • -
        -
      • [DRV_SRC] OSC: Support for future device variant with HPOSC has been added.
        • -
      -
    - -

    Improvements

    -
      -
    • CC13x2_CC26x2
      • -
        -
      • [DRV_SRC] CCFG: Default IPEAK setting changed to 0 for optimized power consumption.
        • -
      -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2
      • -
        -
      • [DRV_SRC]: Corrected handling of VDDR boost mode. Boost mode can be enabled in CCFG.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] CC2640R2F: Bugfix regarding BLE CTE GRX CPE patch, there was a missing include in the Makefile which caused the patch not to function.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_05_02_18760

    -
    - Release date: Nov 02, 2018
    - -

    New features

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_API] I2S: New API has been added. Legacy API is marked as deprecated.
        • -
      • -
    • CC13x2_CC26x2
      • -
        -
      • [RF_PATCH] CC13X2, CC26X2: Release of IQ-dump patch.
        • -
      • [RF_PATCH] CC26X2: API definitions needed for HPOSC support.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] CC2640R2F: Updated time of flight (ToF) patches. Includes bug and stability fixes, STIM and correlation compensation integration and features which reduce RAM usage for the system. UserFunAddr = 0x21000914 for this CPE patch.
        • -
      • [RF_PATCH] CC2640R2F: Release of patches for AoA support using constant tone extension (CTE).
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_DOC] General: General improvement of the documentation.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2
      • -
        -
      • [DRV_API]: The rom.h file contains defines with wrong AUXIOn indexes.
        • -
      • [RF_PATCH] CC1352P, CC1352R, CC2652R: Bug fix regarding RSSI value read-out for 1 and 2 Mbps BLE and Multi.
        • -
      -
    • CC13x0 -
        -
      • [RF_PATCH] CC1350, CC1310: A bug was found in the release script, which resulted in the patches not being cleaned properly before export. This caused the CS bug fix to not be up to date. This update includes the latest fixes in the CC13x0 related to the CS fix in prop CPE patches.
        • -
      • [RF_PATCH] CC1350, CC1310: Updated wireless M-bus CT mode MCE patch. This patch includes two bug-fixes.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_05_01_18740

    -
    - Release date: Oct 11, 2018
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • CC13x2_CC26x2
      • -
        -
      • [DRV_DOC] General: General improvement of the documentation.
        • -
      -
    - -

    Bug fixes

    -
      -
    • CC13x0 -
        -
      • [RF_PATCH] CC1350, CC1310: Bug fix in WMBUS CT-mode MCE, where if the 1st bit was 1, an error floor was present. This patch includes a fix to that bug.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_05_00_18715

    -
    - Release date: Sep 24, 2018
    - -

    New features

    -
      -
    • CC13x2_CC26x2 -
        -
      • [DRV_SRC] General: Driverlib does no longer support early revisions of the CC13x2/CC26x2 devices forcing the driverlib folder "cc13x2_cc26x2_v1" to have been removed.
        • -
      • [DRV_SRC] General: Driverlib folder "cc13x2_cc26x2_v2" for supported CC13x2/CC26x2 devices has been renamed to "cc13x2_cc26x2".
        • -
      • [DRV_SRC] rom_crypto: Added access to ECC crypto functions in ROM by the new rom_crypto driverlib module. These functions can only to be used in applications not containing the BLE SW stack. Note that if these functions are called by the application they will make use of the SRAM address range of 0x2000012C - 0x200001AB as a scratch pad area. Calling any of these functions will require the linker file to be updated with the specified SRAM area.
        • -
      • [RF_PATCH] CC13X2, CC26X2: Release of IQ-dump patch.
        • -
      • -
    - -

    Improvements

    -
      -
    • CC13x2_CC26x2
      • -
        -
      • [DRV_DOC] General: General improvement of the documentation.
        • -
      -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2 -
        -
      • [RF_PATCH] CC13X2, CC26X2: Bug fix regarding the generation of the .bin-files used for CPE patches.
        • -
      • -
    • CC13x0 -
        -
      • [RF_PATCH] CC13X0: (Re-)relase of bitrepetition RFE patch, used to be genfsk patch but for consistency it has now been copied and renamed to brepeat. No changes in patch has been made except for the name.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_16_18623

    -
    - Release date: Aug 17, 2018
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      -
        -
      • [RF_PATCH] CC13X2, CC26X2: Repeat mode with Sniff Command; a flag was not cleared in CPE when running which is solved with this patch.
        • -
      • [RF_PATCH] CC13X2, CC26X2: Patch that fixes the case where RX end time may be delayed in sniff mode.
        • -
      -
    • CC13x0 -
        -
      • [RF_PATCH] CC13X0: Repeat mode with Sniff Command; a flag was not cleared in CPE when running which is solved with this patch.
        • -
      • [RF_PATCH] CC13X0: Patch that fixes the case where RX end time may be delayed in sniff mode.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_15_18598

    -
    - Release date: Aug 09, 2018
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      -
        -
      • [DRV_SRC] RFC: Re-distribute the functionality between driverlib and RF driver required by the High Gain PA configuration.
        • -
      -
    - -

    Bug fixes

    -
      -
    • None
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_14_18578

    -
    - Release date: Aug 01, 2018
    - -

    New features

    -
      -
    • CC13x2_CC26x2_v2
      • -
        -
      • [RF_API] CC1312R, CC1352R, CC1352P, CC2642R, CC2652R: Updated API header files to extend common API with new commands to set TX power with possibility to switch between PAs (only applicable to CC1352P): A new command "CMD_CHANGE_PA" and a new CPE interrupt line definition "IRQ_PA_CHANGED" has been added, and new extended variants for each of the existing radio setup command has been introduced ("CMD_RADIO_SETUP_PA", "CMD_BLE5_RADIO_SETUP_PA", "CMD_PROP_RADIO_SETUP_PA", "CMD_PROP_RADIO_DIV_SETUP_PA") with additional PA switching fields -- these additional fields will be used by RF driver when switching PA, not radio CPU. Separately, a new common CPE command "CMD_SET_CMD_START_IRQ" has been added that can be used by RF driver to get interrupt notification when a background/foreground radioOp command starts (e.g. for IEEE 802.15.4 protocols).
        • -
      -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      -
        -
      • [DRV_SRC] RFC: Expand the RFCOverrideUpdate to handle the front-end specific overrides.
        • -
      • [DRV_SRC] Crypto PKA: Added function to erase PKA RAM.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] CC2640R2F: Updated CPE patch used for time-of-flight measurements ("tof"). This includes the passive node functionality.
        • -
      • -
    - -

    Improvements

    -
      -
    • CC13x2_CC26x2_v2
      • -
        -
      • [DRV_DOC] General: General improvement of the documentation.
        • -
      -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      -
        -
      • [DRV_SRC] Setup and OSC: DCDC without clock loss detection while switching to XOSC_HF.
        • -
      -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_13_18486

    -
    - Release date: May 30, 2018
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] CC2640R2F: Updated MCE patch used for time-of-flight measurements ("tof"). This corrects a build problem with the previous patch that caused it to not work as intended.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_12_18461

    -
    - Release date: May 15, 2018
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] CC2640R2F: Updated CPE and RFE patches used for time-of-flight measurements ("tof") to estimate RF link distance. The new CPE patch has some simplifications, and consequently a smaller patch code size, before first public release. The RFE patch has been updated to remove unnecessary debug information.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • None
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_11_18442

    -
    - Release date: May 08, 2018
    - -

    New features

    -
      -
    • CC13x2_CC26x2_v1
      • -
        -
      • [RF_API] General: Updated API header files to extend common API with new command to set TX power with possibility to switch between PAs. The command is named "CMD_CHANGE_PA". Also, a new extended variants for each of the existing radio setup command has been introduced ("CMD_RADIO_SETUP_PA", "CMD_BLE5_RADIO_SETUP_PA", "CMD_PROP_RADIO_SETUP_PA", "CMD_PROP_RADIO_DIV_SETUP_PA") with additional PA switching fields -- these additional fields will be used by RF driver when switching PA, not radio CPU.
        • -
      • [RF_PATCH] General: Updated all CPE patches to extend API with new common command to set TX power with possibility to switch between PAs. The command is named "CMD_CHANGE_PA".
        • -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] General: Added a set of new radio patches to support time-of-flight measurements ("tof") to estimate RF link distance.
        • -
      • [RF_PATCH] General: Added a set of new radio patches to support Bluetooth 4.2 and proprietary angle of arrival and departure measurements ("aoa_aod").
        • -
      • -
    - -

    Improvements

    -
      -
    • CC13x0 -
        -
      • [RF_PATCH] General: Updated all CPE patches with improved synthesizer start-up sequence that reduces the probability of synthesizer calibration failure.
        • -
      • [RF_PATCH] General: Added MCE patch for generic FSK ("genfsk") PHY to avoid receive sensitivity degradation in continuous RX operation over long time.
        • -
      • [RF_PATCH] General: CC1310, CC1350: Added latest version of MCE patch for WB-DSSS PHY (No change for customer. DSSS pattern is hard coded in the patch).
        • -
      • -
    - -

    Bug fixes

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] CPU: GCC CPUdelay() inline assembly incorrect.
        • -
      • -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      -
        -
      • [DRV_SRC] Crypto PKA: PKAGetBigNumResult() and PKAGetBigNumResultRemainder() static analysis warning.
        • -
      • [DRV_SRC] Crypto AES: AESConfigureCCMCtrl() static analysis warning.
        • -
      -
    • CC13x2_CC26x2_v1 -
        -
      • [RF_PATCH] General: Updated various CPE patch files ("ble", "bt5", "prop", "multi_protocol") to fix an issue with RAT_GPO1 output signal that can be routed out of RF core. The problem was that if RX is restarted within the same command, the RAT_GPO1 output signal would only be asserted on the first sync word received, but it would not be asserted after that if the radio is in RX after restart of the receiver, for example due to repeat mode being enabled.
        • -
      • [RF_PATCH] General: Updated all CPE patches supporting proprietary command set ("prop", "multi_protocol") to give correct time-out operation when using "CMD_PROP_RX_SNIFF" or "CMD_PROP_RX_ADV_SNIFF" commands. The carrier sense operation will continue after the csEndTrigger has occurred, if so configured.
        • -
      • [RF_PATCH] CC1352R, CC1352P, CC2652R: Added RFE patch for IEEE 802.15.4 O-QPSK DSSS ("ieee_802_15_4") PHY to resolve issue with RSSIMAXVAL reporting incorrect value.
        • -
      • -
    • CC26x0R2 -
        -
      • [RF_PATCH] General: Updated all CPE patches to align frequency word representation between frequency synthesizer and demodulator. This prevents temporary loss of receive function during continuous receive operation over long time for any "fractFreq" setting used.
        • -
      • -
    • CC26x0 -
        -
      • [RF_PATCH] General: Updated all CPE patches to align frequency word representation between frequency synthesizer and demodulator. This prevents temporary loss of receive function during continuous receive operation over long time for any "fractFreq" setting used.
        • -
      • -
    • CC13x0 -
        -
      • [RF_PATCH] General: Updated all CPE patches to align frequency word representation between frequency synthesizer and demodulator. This prevents temporary loss of receive function during continuous receive operation over long time for any "fractFreq" setting used.
        • -
      • [RF_PATCH] General: Updated all CPE patches supporting proprietary command set ("ant_div", "brepeat", "genfsk", "genook", "ghs", "lrm", "sl_longrange", "wb_dsss", "wbmus_ctmode", "wmbus_smode") to give correct time-out operation when using "CMD_PROP_RX_SNIFF" or "CMD_PROP_RX_ADV_SNIFF" commands. The carrier sense operation will continue after the csEndTrigger has occurred, if so configured.
        • -
      • [RF_PATCH] CC1350: Added RFE patch for IEEE 802.15.4 O-QPSK DSSS ("ieee") PHY to resolve issue with RSSIMAXVAL reporting incorrect value.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_10_18419

    -
    - Release date: May 05, 2018
    - -

    New features

    -
      -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      -
        -
      • [RF_API] General: Introduce new RFCGetPaType and RFCGetPaGain functions.
        • -
      -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_DOC] General: List include file for each DriverLib module in HTML documentation.
        • -
      • [DRV_DOC] OSC: Function in Oscillator API is missing description for parameter.
        • -
      • [DRV_SRC] CPU: GCC CPUdelay() inline assembly incorrect.
        • -
      • [DRV_SRC] GPIO: Compile error in gpio.h when DRIVERLIB_DEBUG is defined.
        • -
      • -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      -
        -
      • [DRV_SRC] Crypto SHA: Defines in SHA2 module have semi-colon at the end of the line.
        • -
      • [DRV_SRC] GPIO: dioNumberLegal() in gpio.h can return incorrect value for cc26x2/cc13x2 devices.
        • -
      • [DRV_SRC] Crypto PKA: PKABigNumModGetResult can leave junk data in most significant bytes.
        • -
      • [DRV_SRC] General: Compile errors in ASSERTs when DRIVERLIB_DEBUG is defined.
        • -
      -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_09_18364

    -
    - Release date: April 17, 2018
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_DOC] General: General improvement of the documentation.
        • -
      • -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      -
        -
      • [HW_INC] RFC_DBELL: Renamed defines in hw_rfc_dbell.h for bit[13] and bit[12] of the RFCPEIFG, RFCPEIEN and RFCPEISL registers.
        • -
      -
    - -

    Bug fixes

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] GPIO: Compile error in gpio.h when DRIVERLIB_DEBUG is defined.
        • -
      • -
    - - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_08_18312

    -
    - Release date: March 2, 2018
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      -
        -
      • [DRV_SRC] Crypto PKA: Functions PKABigNumModGetResult and PKABigNumInvModGetResult both do not return how many bytes were written to the resultBuf. They can yield less than expected because the HW does not zero-pad beyond word boundaries. This is now handled by zero-out resultBuf before fetching the result so that correct assumptions about the result lengths can be made.
        • -
      -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_07_18288

    -
    - Release date: February 22, 2018
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2_v1
      • -
        -
      • [RF_PATCH] CC1312, CC1352, CC2642, CC2652: Updated all CPE patch files ("ble", "bt5", "ieee_802_15_4", "prop", "multi_protocol") to fix a problem in CPE's dynamic reconfiguration of the ADI_3_REFSYS:DCDCCTL5[3:0] register when radio enters RX or TX. A bug in the save/restore mechanism that should write DCDCCTL5[3:0] register back to its original setting when radio operation has ended caused the register setting to always be restored to setting 0x0. This undesired setting change of DCDCCTL5.IPEAK can cause an increased current consumption, if the DC/DC regulator is used. This fix will ensure DCDCCTL5[3:0] is correctly restored to original setting.
        • -
      • [RF_PATCH] CC1312, CC1352, CC2642, CC2652: Updated all CPE patch files ("ble", "bt5", "ieee_802_15_4", "prop", "multi_protocol") to fix an issue with CPEGPO1 output signal. This signal, available in IO Controller as "RFC_GPO1" signal, represents "PA_EN" status signal. This status signal should go high when the power amplifier (PA) is enabled (start of transmission), and then low when PA is disabled (end of transmission). For all protocols/PHYs other than Bluetooth low energy, there was an issue that prevented this signal to correctly go low at end of transmission, which has now been fixed.
        • -
      -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_06_18273

    -
    - Release date: February 21, 2018
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • CC13x2_CC26x2_v1 -
        -
      • [DRV_SRC] Setup: TrimAfterColdResetWakeupFromShutDown(): Removed workaround that was only valid for discontinued silicon revision.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      -
        -
      • [DRV_SRC] Crypto: Fixed potential race conditions when using aes.c.
        • -
      -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_05_18251

    -
    - Release date: February 07, 2018
    - -

    New features

    -
      -
    • CC13x2_CC26x2_v1
      • -
        -
      • [RF_PATCH] CC1352P: Updated CPE Bluetooth 5 ("bt5") and CPE multi-protocol patch files, and added a new RFE Bluetooth 5 ("bt5") patch file, to allow higher bandwidth in synthesizer PLL during Tx start-up. This allows faster PA settling when transmitting with 20-dBm PA.
        • -
      -
    - -

    Improvements

    -
      -
    • CC13x2_CC26x2_v2 -
        -
      • [DRV_SRC] Setup: TrimAfterColdResetWakeupFromShutDown(): HW register bit fields ADI_3_REFSYS:AUX_DEBUG.LPM_BIAS_BACKUP_EN and ADI_4_AUX:COMP.LPM_BIAS_WIDTH_TRIM are now written with values from FCFG1.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • None
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_04_18225

    -
    - Release date: February 01, 2018
    - -

    New features

    -
      -
    • CC13x2_CC26x2_v2
      • - CC13x2_CC26x2_v1
      - CC26x0
      - CC26x0R2
      - CC13x0 -
        -
      • [RF_API] General: The RFCOverrideSearch() function is now available on all devices and no longer static.
        • -
      -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • None
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_03_18200

    -
    - Release date: January 25, 2018
    - -

    New features

    -
      -
    • CC13x2_CC26x2_v2
      • -
        -
      • [RF_API] CC1312, CC1352, CC2642, CC2652: Updated API header files.
        • -
      -
    • CC13x2_CC26x2_v1
      • -
        -
      • [RF_PATCH] CC1352, CC2642, CC2652: Updated CPE Bluetooth 5 ("bt5") and CPE multi-protocol patch files with new API functionality for configuring the 20-dBm PA output power when using CMD_BLE5_* command API.
        • -
      • [RF_API] ] CC1312, CC1352, CC2642, CC2652: -
          -
        • rf_ble_cmd.h: All CMD_BLE5_* radio operation command structs are extended with a new, optional "tx20Power" struct. This can be used to immediately set new 20-dBm PA setting in Tx.
          • -
        • rf_common_cmd.h: The common CMD_SET_TX20_POWER command is modified with "txPower" struct field renamed to "tx20Power". This is to highlight that the parameter is for the 20-dBm PA and not the normal PA.
          • -
        • -
      -
    - -

    Improvements

    -
      -
    • CC13x2_CC26x2_v2 -
        -
      • [DRV_SRC] Crypto PKA: Added missing length define (Curve25519_PARAM_SIZE_BYTES) in PKA module for Curve25519.
        • -
      • [DRV_SRC] Crypto PKA: Removed function PKAEccVerifyPublicKeyGetResult() since only the NIST and Brainpool curves are supported and they have a cofactor of 1. It's not needed to perform the Q*n = point at infinity check during public key validation.
        • -
      • -
    • CC13x2_CC26x2_v1 -
        -
      • [RF_PATCH] CC1312, CC1352, CC2652: Updated the RFE generic FSK ("genfsk") PHY patches with a new default setting for PA ramp-down wait time. This has been reduced from 31 µs down to 21 µs.
        • -
      • [DRV_SRC] Crypto PKA: Added missing length define (Curve25519_PARAM_SIZE_BYTES) in PKA module for Curve25519.
        • -
      • [DRV_SRC] Crypto PKA: Removed function PKAEccVerifyPublicKeyGetResult() since only the NIST and Brainpool curves are supported and they have a cofactor of 1. It's not needed to perform the Q*n = point at infinity check during public key validation.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • None
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_02_18173

    -
    - Release date: January 15, 2018
    - -

    New features

    -
      -
    • CC13x2_CC26x2_v2
      • -
        -
      • [RF_API] General: Initial release of preliminary API header files.
        • -
      • [DRV_SRC] Crypto PKA: Added Montgomery Curve25519 multiplication support.
        • -
      -
    • CC13x2_CC26x2_v1
      • -
        -
      • [DRV_SRC] Crypto PKA: Added Montgomery Curve25519 multiplication support.
        • -
      -
    - -

    Improvements

    -
      -
    • CC13x2_CC26x2_v1 -
        -
      • [RF_PATCH] General: CC1312, CC1352, CC2652: Updated the RFE and MCE generic FSK ("genfsk") PHY patches with small optimizations in TX timing for PA enable at start of packet, and increased default setting for PA ramp-down time from 10 µs to 31 µs. Modulator timing has also been tuned for better performance at high data rates (>500 kbps) and now waits 4 µs with tone before starting preamble to better align with PA ramp-up.
        • -
      • [RF_PATCH] General: CC1352, CC2652: Updated the IEEE 802.15.4 O-QPSK DSSS ("ieee_802_15_4") PHY patch with improvements in modem re-initialization between RX packets.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2_v1
      • -
        -
      • [RF_API] General: CC1312, CC1352, CC2642, CC2652: Updated API header file "rf_mailbox.h" to remove an incorrect interrupt "BG_COMMAND_SUSPENDED" (interrupt line 12) which does not exist.
        • -
      • [RF_PATCH] General: CC1312, CC1352: Updated the MCE SimpleLink Long Range ("sl_longrange") PHY patch to fix a potential problem related to stopping the demodulator when using SimpleLink Long Range PHY formats. The problem was that use of CMD_ABORT or CMD_PROP_RESTART_RX to stop an on-going RX operation with this PHY could result in RF core doorbell interface to become unresponsive, and a re-initialization (power-cycle) of RF core would be needed to recover.
        • -
      -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_01_18155

    -
    - Release date: January 05, 2018
    - -

    New features

    -
      -
    • CC13x2_CC26x2_v1
      • - CC13x2_CC26x2_v2 -
        -
      • [DRV_SRC] AUX_ADC: Added additional defines for supported trigger events.
        • -
      -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] Crypto: Improved key loading error handling to avoid system crash during heavy bus load.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2_v1
      • - CC13x2_CC26x2_v2 -
        -
      • [DRV_SRC] Crypto PKA: Fixed PKAEccVerifyPublicKeyWeierstrassStart() function which incorrectly failed for curves that were not a multiple of 4 bytes in length.
        • -
      -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_04_00_18127

    -
    - Release date: December 14, 2017
    - -

    New features

    -
      -
    • CC13x2_CC26x2 -
        -
      • [DRV_SRC] General:Two variants of driverlib are introduced. The driverlib folder for the legacy version is renamed from "cc13x2_cc26x2" to "cc13x2_cc26x2_v1". A new driverlib folder for a planned upgraded silicon revision of cc13x2_cc26x2 devices is called "cc13x2_cc26x2_v2".
        • -
      • [DRV_SRC] Crypto PKA: Added support for Short-Weierstrass public key validation, NIST-P224 and NIST-P384 to PKA module.
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] ChipInfo: Renamed enumerations returned from function ChipInfo_GetChipType(). Renamed CHIP_TYPE_CC2644 to CHIP_TYPE_unused and CHIP_TYPE_CC1354 to CHIP_TYPE_CC1352P.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] AUX_ADC: AUXADCDisable() now flushes the ADC FIFO in order to remove stale samples in the FIFO after the ADC module is disabled. If samples are left in the FIFO after disabling the ADC, the related ADC_IRQ flag may not be cleared. This is a potential problem when operating at high sampling rates where additional conversions may complete between handling an ISR and disabling the ADC, possibly causing an infinite ISR loop.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_03_04_18115

    -
    - Release date: December 7, 2017
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch with bug fix for Bluetooth 5 LE Advertising Extensions: The Bluetooth 5 initiator command sometimes outputs a "connectTime" that does not correspond to the transmitted AUX_CONNECT_REQ.
        • -
      • -
    • CC13x2_CC26x2 -
        -
      • [RF_PATCH] CPE: CC1352, CC2642, CC2652: Updated CPE BT5 and CPE multi-protocol patches with bug fix for Bluetooth 5 LE Advertising Extensions: The Bluetooth 5 initiator command sometimes outputs a "connectTime" that does not correspond to the transmitted AUX_CONNECT_REQ.
        • -
      • [RF_PATCH] RFE: CC1312, CC1352, CC2652: Updated the RFE generic FSK ("genfsk") PHY patch with bug fix in PA ramp mechanism: the RFE, and thus CPE, may hang if TX is aborted shortly after start.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_03_03_18107

    -
    - Release date: December 1, 2017
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2 -
        -
      • [RF_PATCH] CPE/MCE: CC1312, CC1352: Updated the CPE PROP, CPE multi-protocol, and MCE SimpleLink Long Range (SLR) PHY patches to fix a problem related to stopping the demodulator when using SLR PHY formats. The problem was that use of CMD_ABORT or CMD_PROP_RESTART_RX to stop an on-going RX operation with this PHY could result in RF core doorbell interface to become unresponsive, and a re-initialization (power-cycle) of RF core would be needed to recover. (internal: RFCORE-163).
        • -
      • [RF_PATCH] MCE BT5: CC1352, CC2642, CC2652: Updated MCE BT5 patch to resolve a potential PHY problem where too high TX symbol rate error (up to 100 ppm) may be used for LE Coded PHY, which will violate Bluetooth 5 PHY specification requirements (max 50 ppm). The problem could be invoked, depending on a timing condition, as part of doing an RX to TX transition using LE Coded PHY. (internal: RFCORE-166).
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_03_02_18061

    -
    - Release date: November 10, 2017
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • Changes that apply to all devices -
        -
      • [RF_API] General: In all API files, resolved CCS compiler warning when using attribute "aligned(4)" on structs with struct member of type uint64_t.
        • -
      • -
    • CC13x2_CC26x2 -
        -
      • [DRV_SRC] Setup: SetupTrimDevice(): Fixed bug that caused the supported "Boost mode" during boot to be non-functional. The supported mode boosts VDDR to support +14dBm.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_03_01_18037

    -
    - Release date: November 3, 2017
    - -

    New features

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_API] New functions in rfc.c and rfc.h: -
          -
        • __STATIC_INLINE void RFCCpe0IntSelect(uint32_t ui32Mask): This function maps the interrupt lines provided within the argument to CPE0.
          • -
        • __STATIC_INLINE void RFCCpe1IntSelect(uint32_t ui32Mask): This function maps the interrupt lines provided within the argument to CPE1.
          • -
        • -
      • [DRV_SRC] OSC: Add debug/test function OSC_AdjustXoscHfCapArray(). Useful for production preparations when trying to find optimal HF XOSC Cap Array setting for a specific design. Ref. SET_CCFG_MODE_CONF_XOSC_CAP... in ccfg.c
        • -
      • [DRV_SRC] PowerCtrl: Added the following functions: -
          -
        • PowerCtrlPadSleepEnable()
          • -
        • PowerCtrlPadSleepDisable()
          • -
        • -
      • -
    • CC13x0 -
        -
      • [RF_PATCH] MCE: Added new MCE patch for Generic FSK with CC1101-compatible FEC and interleaver ("genfsk_fec_cc1101").
        • -
      • -
    • CC26x0R2 -
        -
      • [RF_API] BLE5: Updated Bluetooth 5 command API ("BLE5"): Added Bluetooth 5 variants of legacy advertiser commands (CMD_BLE5_ADV, CMD_BLE5_ADV_DIR, CMD_BLE5_ADV_NC, CMD_BLE5_ADV_SCAN). These new commands are only available when using an updated CPE BT5 patch.
        • -
      • [RF_API] PROP: In PROP API command CMD_PROP_RADIO_SETUP the bit-fields "symbolRate.bPdifDecim" and "symbolRate.pdifDecim" have been merged into one new bit-field ".symbolRate.decimMode". This is to make the CC2640R2F API the same as for CC13x0.
        • -
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch to include Bluetooth 5 variants of legacy advertiser commands (CMD_BLE5_ADV, CMD_BLE5_ADV_DIR, CMD_BLE5_ADV_NC, CMD_BLE5_ADV_SCAN).
        • -
      • -
    • CC13x2_CC26x2 -
        -
      • [RF_API] BLE5: Updated Bluetooth 5 command API ("BLE5"): Added Bluetooth 5 variants of legacy advertiser commands (CMD_BLE5_ADV, CMD_BLE5_ADV_DIR, CMD_BLE5_ADV_NC, CMD_BLE5_ADV_SCAN). These new commands are only available when using an updated CPE BT5 or CPE multi-protocol patch.
        • -
      • [RF_API] PROP: In PROP API commands CMD_PROP_RADIO_SETUP and CMD_PROP_RADIO_DIV_SETUP a new bit-field "modulation.deviationStepSz" has been added. This can be used to configure the resolution of the existing bit-field "modulation.deviation".
        • -
      • [RF_PATCH] CPE: Updated CPE BT5 and CPE multi-protocol patches to include Bluetooth 5 variants of legacy advertiser commands (CMD_BLE5_ADV, CMD_BLE5_ADV_DIR, CMD_BLE5_ADV_NC, CMD_BLE5_ADV_SCAN).
        • -
      • [RF_PATCH] CPE: The CPE patch files "rf_patch_cpe_sl_longrange.h" and "rf_patch_cpe_genfsk.h" have been removed. The CPE PROP patch ("rf_patch_cpe_prop.h") already covers these cases and should be used instead. Alternatively, the CPE multi-protocol patch may be used.
        • -
      • [DRV_SRC] Setup: Added support in SetupTrimDevice() to enable "Boost mode" during boot, boosting VDDR to support +14dBm.
        • -
      • [DRV_SRC] sys_ctrl: Added SysCtrlShutdownWithAbort() as a workaround to detect pre-shutdown wakeup events.
        • -
      • [DRV_SRC] sys_ctrl: Added handling of optional temperature compensation of the recharge level (enabled by setting CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC = 0).
        • -
      • [DRV_SRC] Crypto PKA: Added subtraction function to PKA module and EC-JPAKE updates.
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] Eliminated functions in rfc.c and rfc.h:
        - These functions did not provided a safe way to handle clock management, hence they have been removed from the rfc.h file.
        - It is recommended that enabling/disabling clocks in the RF core should be requested through radio commands instead. -
          -
        • __STATIC_INLINE void RFCClockSet(uint32_t ui32Mask)
          • -
        • __STATIC_INLINE void RFCClockClear(uint32_t ui32Mask)
          • -
        • -
      • [HW_INC] General: Updated/improved hardware register descriptions (inc/hw_*.h and doc/../*.html files).
        • -
      • [DRV_SRC] PowerCtrl: The following functions are either removed or marked as derprecated: -
          -
        • PowerCtrlIOFreezeEnable() removed
          • -
        • PowerCtrlIOFreezeDisable() removed
          • -
        • PowerCtrlResetSourceGet() marked as deprecated. It will be removed in a future release. Use SysCtrlResetSourceGet() instead.
          • -
        • -
      • -
    • CC13x0 -
        -
      • [RF_PATCH] MCE: Updated MCE bit-repeat patch ("brepeat") to add support for very long or infinite preamble.
        • -
      • -
    • CC26x0R2 -
        -
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch for Bluetooth 5 to implement that CPE re-reads the "pConnectReqData" parameter pointer before sending AUX_CONNECT_REQ.
        • -
      • -
    • CC13x2_CC26x2 -
        -
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch for Bluetooth 5 to implement that CPE re-reads the "pConnectReqData" parameter pointer before sending AUX_CONNECT_REQ.
        • -
      • [RF_PATCH] CPE: Updated CPE BLE, CPE BT5, CPE PROP, and CPE multi-protocol patches with improvement to make the (G)FSK deviation in Tx constant over the frequency band by recalculating the Tx shape when RF synth is programmed to a new frequency.
        • -
      • [DRV_SRC] The following functions are not applicable on these devices and hence been removed from rfc.c and rfc.h: -
          -
        • void RFCRfTrimRead(rfc_radioOp_t *pOpSetup, rfTrim_t* pRfTrim)
          • -
        • void RFCRTrim(rfc_radioOp_t *pOpSetup)
          • -
        • void RFCRfTrimSet(rfTrim_t* pRfTrim)
          • -
        • void RFCAdi3VcoLdoVoltageMode(bool bEnable)
          • -
        • -
      • [DRV_SRC] Crypto SHA2: Updated SHA2 driverlib to support partial hashing of multiple blocks at a time.
        • -
      • [DRV_SRC] sys_ctrl: SysCtrlShutdown() now terminates in a while(1) to make sure it never returns.
        • -
      • [DRV_SRC] AON/sys_ctrl: Removed function AONPMCTLShutDownEnable(), use SysCtrlShutdown() instead.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • Changes that apply to all devices -
        -
      • [RF_API] General: In all API files, resolved a syntax problem with the struct attribute when compiling with GCC or CCS.
        • -
      • [DRV_SRC] Behavioural change in rfc.c and rfc.h: -
          -
        • __STATIC_INLINE void RFCClockEnable(void): This function only enables the interrupts which are needed to get the CM0 running. This is to optimize consumption.
          • -
        • __STATIC_INLINE void RFCHwIntEnable(uint32_t ui32Mask): The old function was clearing the interrupts before enabling.
          • -
        • __STATIC_INLINE void RFCCpeIntEnable(uint32_t ui32Mask): This function only enables the interrupts, regardless if it is mapped to CPE0 or CPE1. It does not modify the pending interrupt flags.
          • -
        • -
      • [DRV_API] Function prototype changes in rfc.c and rfc.h: -
          -
        • uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask): This function was reading and clearing all the CPE interrupt flags, regardless if the handler routine has actually the right to do so. This could cause problems in applications where multiple users share the CPE interrupts. The new function only handles the interrupts which match the provided bitmask.
          • -
        • void RFCCpePatchReset(void): The function name was aligned with the camel-case naming convention of driverlib functions.
          • -
        • void RFCSynthPowerDown(void): This function is now explicitly takes no argument.
          • -
        • RFCHwIntGetAndClear(uint32_t ui32Mask): The function name was aligned with the camel-case naming convention of driverlib functions.
          • -
        • __STATIC_INLINE void RFCCpe0IntSelectClearEnable(uint32_t ui32Mask): The function was renamed to reflect its internal behavior.
          • -
        • __STATIC_INLINE void RFCCpe1IntSelectClearEnable(uint32_t ui32Mask): The function was renamed to reflect its internal behavior.
          • -
        • -
      • -
    • CC13x2_CC26x2 -
        -
      • [RF_API] IEEE: In API for "IEEE" commands, a type problem for the struct member "CMD_IEEE_RX.pShortEntryList" was fixed. This fix aligns the API structs with the existing API for CC26x0.
        • -
      • [RF_PATCH] CPE: Updated CPE PROP and CPE multi-protocol patches with bug fix: if a packet is received with a proprietary mode Rx command (CMD_PROP_RX*) and a partial read Rx buffer is used, the CPE will hang if an abort command is received while a packet is being received.
        • -
      • [DRV_SRC] Crypto PKA: Fixed issue where PKAGetECCResult would read and uninitialized variable when not copying back the x coordinate.
        • -
      • [DRV_SRC] Crypto PKA: Fixed bug where PKAGetECCResult would calculate an incorrect offset for curvePointY in PKA RAM and copy back an incorrect result.
        • -
      • [DRV_SRC] Setup: SetupTrimDevice(): Include the LPM_BIAS trims in the boot sequence.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • -
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_02_03_17972

    -
    - Release date: September 21, 2017
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch to include bug fix for Bluetooth 5: Address type of received ADV_AUX_IND packets is not treated correctly.
        • -
      • -
    • CC13x2_CC26x2 -
        -
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch to include bug fix for Bluetooth 5: Address type of received ADV_AUX_IND packets is not treated correctly.
        • -
      • [RF_PATCH] CPE multi-protocol: Updated CPE multi-protocol patch to include bug fix for Bluetooth 5: Address type of received ADV_AUX_IND packets is not treated correctly.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: GPO control not functional. (The PA_EN status signal does not go low).
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_02_02_17958

    -
    - Release date: September 21, 2017
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch to include bug fix for Bluetooth 5: receiving ADV_EXT_IND that contains AuxPtr with CRC error causes stall.
        • -
      • -
    • CC13x2_CC26x2 -
        -
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch to include bug fix for Bluetooth 5: receiving ADV_EXT_IND that contains AuxPtr with CRC error causes stall.
        • -
      • [RF_PATCH] CPE multi-protocol: Updated CPE multi-protocol patch to include bug fix for Bluetooth 5: receiving ADV_EXT_IND that contains AuxPtr with CRC error causes stall.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: GPO control not functional. (The PA_EN status signal does not go low).
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_02_01_17905

    -
    - Release date: August 31, 2017
    - -

    New features

    -
      -
    • CC13x2_CC26x2 -
        -
      • [RF_PATCH] CPE PROP: Added new CPE PROP patch, to prepare for future PHYs using "PROP" API commands. (This patch code is currently identical to the existing CPE GenFSK and CPE SimpleLink Long Range patches).
        • -
      • [RF_PATCH] CPE BLE: Added new CPE BLE patch, to be used for Bluetooth 4.2 using "BLE" API commands. This patch does not include Bluetooth 5 related fixes, and may therefore be smaller in patch code size. This is to supplement the existing CPE BT5 patch for Bluetooth 5, for use cases where only Bluetooth 4.2 functionality is desired.
        • -
      • [RF_PATCH] CPE MULTI: Added new CPE multi-protocol patch, to be used for multi-PHY use case. This patch contains bug fixes related to all available API command sets (i.e. "BLE", "BLE5", "IEEE", "PROP", "HS") and should be used in a multi-protocol use case instead of switching between multiple CPE patches.
        • -
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • CC13x2_CC26x2 -
        -
      • [DRV_SRC] Crypto: Function SHA2ExecuteHash(): Fixed bug that that yielded incorrect digests for messages whose length is a multiple of the hash block size.
        • -
      • [RF_PATCH] MCE IEEE 802.15.4: Added new MCE patch for IEEE 802.15.14-2006 at 2.4 GHz. This contains fix for Rx correlation search failure.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: GPO control not functional. (The PA_EN status signal does not go low).
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_02_00_17858

    -
    - Release date: August 2, 2017
    - -

    New features

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] sys_ctrl: Added configurable initial VDDR recharge period margin to permit setting a more conservative initial recharge period.
        • -
      • [DRV_API] sys_ctrl: Added a new parameter to function SysCtrlAdjustRechargeAfterPowerDown().
        • -
      • -
    • CC13x0 -
        -
      • [RF_PATCH]: GHS Added new CPE/MCE patch set for general high-speed GenFSK ("ghs" patch). CPE patch is identical to GenFSK.
        • -
      • [RF_PATCH]: BREPEAT Added new CPE/MCE patch set for using bit-repeat mode ("brepeat" patch), for symbol rate. CPE patch is identical to GenFSK.
        • -
      • [RF_API] Headers: In CPE commands CMD_PROP_RADIO_SETUP and CMD_PROP_RADIO_DIV_SETUP, the struct bit fields symbolRate.bPdifDecim and symbolRate.pdifDecim have been joined into one field, symbolRate.decimMode, with unchanged functionality. This change is to have same API for CC13x0 as exists for CC13x2 and CC26x2 devices. This field is needed used when using "brepeat" radio patch.
        • -
      • -
    • CC13x2_CC26x2 -
        -
      • Initial revision of driverlib for new devices CC13x2 and CC26x2.
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_API] sys_ctrl: Removed definition "RSTSRC_VDD_LOSS" since this value will never be returned when calling SysCtrlResetSourceGet().
        • -
      • [DRV_SRC] CCFG: Removed gcc compiler warning (change of sign) when compiling ccfg.c.
        • -
      • [DRV_SRC] CPU: Removed gcc compiler warning for function CPUbasepriSet().
        • -
      • -
    • CC26x0R2 -
        -
      • [RF_PATCH] CPE BLE: Updated CPE patch for Bluetooth 4.2 to fix known issue related to CMD_SCH_IMM. This also includes a fix for a rare problem where CPE may hang when running BLE master command.
        • -
      • [RF_PATCH] CPE BT5: Updated CPE patch for Bluetooth 5 to fix known issue related to CMD_SCH_IMM. This also includes a fix for a rare problem where CPE may hang when running BLE master command.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] CPE BT5: CPE BT5 patch for Bluetooth 5: Corrected an error when ignoring identity address for resolvable private addresses in legacy advertiser.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    • CC26x0R2 -
        -
      • [RF_API] General: GPO control not functional. (The PA_EN status signal does not go low).
        • -
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_01_03_17842

    -
    - Release date: July 20, 2017
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • None
      • -
    - -

    Bug fixes

    -
      -
    • None
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • - CC26x0R2 -
        -
      • [RF_API] General: GPO control not functional.
        • -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_01_02_17805

    -
    - Release date: June 1, 2017
    - -

    New features

    -
      -
    • CC13x0 -
        -
      • [RF_PATCH] General: Added GenFSK Antenna diversity CPE patch.
        • -
      • [RF_PATCH] General: Added high speed GenFSK patches.
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_DOC] General: General improvement of the documentation.
        • -
      • [HW_INC] General: Updated/improved hardware register descriptions (inc/hw_*.h and doc/../*.html files).
        • -
      • -
    • CC13x0 -
        -
      • [RF_API] Headers: Added bPdifDecim and pdifDecim to symbolRate structure.
        • -
      • -
    • CC26x0R2 -
        -
      • [RF_API] Headers: Removed unnecessary RF_MODE_MULTIPLE define.
        • -
      • [RF_API] Headers: Added bPdifDecim and pdifDecim to symbolRate structure.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • None
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • - CC26x0R2 -
        -
      • [RF_API] General: GPO control not functional.
        • -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_01_01_17779

    -
    - Release date: May 5, 2017
    - -

    New features

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] RFC: Added new function RFCOverrideUpdate() that deprecates RFCRTrim().
        • -
      • [DRV_SRC] RFC: Added new function RFCHWIntGetAndClear().
        • -
      • -
    • CC13x0 -
        -
      • [RF_PATCH] PHY: Added GenFSK Antenna diversity MCE/RFE patches.
        • -
      • [RF_PATCH] PHY: Added IQ dump MCE patch.
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_DOC] General: General improvement of the documentation.
        • -
      • [HW_INC] General: Updated/improved hardware register descriptions (inc/hw_*.h and doc/../*.html files).
        • -
      • -
    • CC26x0R2 -
        -
      • [RF_API] BLE: Changed comment in BLE5 commands.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] AUX_TIMER: Corrected masking of TICK_SRC in AUXTimerConfigure().
        • -
      • [DRV_SRC] GCC: Fixed problem with vector table in startup_gcc.c that gave pointer conversion error when compiling with GNU tools.
        • -
      • -
    • CC26x0R2 -
        -
      • [RF_API] IEEE 802.15.4: Changed pShortEntryList pointer to uint32_t from shortAddrEntry.
        • -
      • [RF_API] BLE: Added missing defines in ble_mailbox.h.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • - CC26x0R2 -
        -
      • [RF_API] General: GPO control not functional.
        • -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_01_00_17751

    -
    - Release date: April 20, 2017
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] I2S: Removed deprecated parameter (unusedChanCfgWrite0) from function I2SChannelConfigure().
        • -
      • [DRV_LIB] IAR: Built IAR library (driverlib.lib) with version 8.11.1
        • -
      • -
    - -

    Bug fixes

    -
      -
    • None
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • - CC26x0R2 -
        -
      • [RF_API] General: GPO control not functional.
        • -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_00_06_17733

    -
    - Release date: March 29, 2017
    - -

    New features

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] RFC: Added new functions RFCOverrideUpdate() and RFCOverrideSearch().
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [RF_PATCH] Patches: Changed include path for hw_types.h
        • -
      • [HW_INC] General: Updated/improved hardware register descriptions (inc/hw_*.h and doc/../*.html files).
        • -
      • -
    - -

    Bug fixes

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_LIB] CCS: Added missing linker section ".TI.noinit" to all Code Composer Studio linker files.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • - CC26x0R2 -
        -
      • [RF_API] General: GPO control not functional.
        • -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_00_05_17708

    -
    - Release date: March 17, 2017
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [HW_INC] General: Updated/improved hardware register descriptions (inc/hw_*.h and doc/../*.html files).
        • -
      • -
    • CC26x0R2 -
        -
      • [RF_PATCH] BLE: Updated BLE5 RFE Patch.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] BLE: Added missing defines in ble header files.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • - CC26x0R2 -
        -
      • [RF_API] General: GPO control not functional.
        • -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_00_04_17647

    -
    - Release date: February 7, 2017
    - -

    New features

    -
      -
    • None
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] GCC linker files: Now ensures that CCFG structure is kept.
        • -
      • -
    • CC26x0R2 -
        -
      • [DRV_SRC] All linker files: Linker files have been renamed to match device name (example: cc26x0rf128.cmd has been renamed to cc26x0r2f.cmd).
        • -
      • -
    - -

    Bug fixes

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] Crypto: Function CRYPTOAesLoadKey(): Corrected one more problem with storing multiple keys (ref. bug fix in the driverlib_cc13xx_cc26xx_3_00_03_17619 release).
        • -
      • [DRV_SRC] GCC linker files: Fixed problem where initialized variables (.data section) did not get loaded correctly.
        • -
      • [RF_PATCH] General: Added missing DEVICE_FAMILY_PATH macro to all MCE and RFE patches.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • - CC26x0R2 -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_00_03_17619

    -
    - Release date: February 2, 2017
    - -

    New features

    -
      -
    • CC26x0R2 -
        -
      • [RF_API] BT5: Added command header files.
        • -
      • [RF_PATCH] BT5: Added CPE patch.
        • -
      • -
    • CC26x0 -
        -
      • [RF_API] IEEE 802.15.4: Added command header files.
        • -
      • [RF_PATCH] IEEE 802.15.4: Added CPE patch.
        • -
      • [RF_PATCH] IEEE 802.15.4: Added MCE/RFE patches for use with single ended frontend.
        • -
      • -
    • CC13x0 -
        -
      • [RF_PATCH] WMBUS: Added S1- and S2-Mode CPE, MCE and RFE patch.
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [RF_PATCH] General: All MCE and RFE patches have new include paths for the hw_type.h file.
        • -
      • [RF_PATCH] General: Added RFE_PATCH_MODE and MCE_PATCH_MODE defines for future partial patching support.
        • -
      • [DRV_SRC] General: Removed deprecated functions: -
          -
        • OSCInterfaceEnable()
          • -
        • OSCInterfaceDisable()
          • -
        • SysCtrlPowerEverything()
          • -
        • -
      • [DRV_SRC] ChipInfo: Added support for new chip and package types (Note that packages available for a specific device are shown in the device datasheet). -
          -
        • Added PACKAGE_7x7_Q1 as new return option from function ChipInfo_GetPackageType() and added function ChipInfo_PackageTypeIs7x7Q1().
          • -
        • Added HWREV_2_4 as new return option from function ChipInfo_GetHwRevision() and added function ChipInfo_HwRevisionIs_GTEQ_2_4().
          • -
        • -
      • [HW_INC] General: Updated/improved hardware register descriptions (inc/hw_*.h and doc/../*.html files).
        • -
      • -
    • CC26x0R2 -
        -
      • [RF_API] BLE: Updating structures with BT5 fields.
        • -
      • [DRV_SRC] SysCtrl: Added RSTSRC_WAKEUP_FROM_TCK_NOISE as new return option from function SysCtrlResetSourceGet().
        • -
      • -
    • CC26x0 -
        -
      • [RF_API] General: Added dummy define for rfc_CMD_BLE5_RADIO_SETUP_t to increase compatibility with other chips.
        • -
      • -
    • CC13x0 -
        -
      • [RF_API] General: Added dummy define for rfc_CMD_BLE5_RADIO_SETUP_t to increase compatibility with other chips.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] Crypto: Function CRYPTOAesLoadKey(): Corrected problem with storing multiple keys.
        • -
      • -
    • CC13x0 -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands. Fixed with CPE patch.
        • -
      • -
    - -

    Known issues

    -
      -
    • CC26x0
      • - CC26x0R2 -
        -
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
      -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_00_02_17545

    -
    - Release date: December 1, 2016
    - -

    New features

    -
      -
    • CC26x0R2 -
        -
      • [RF_PATCH] Added optional BLE 4.x RFE patch. This will improve interference performance. Not used in provided settings.
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] IOC Added missing RF defines to be used for antenna diversity implementation (IOC_PORT_RFC_SMI_*).
        • -
      • [DRV_LIB] ROM Debug improvement: Include symbols and source for driverlib functions in ROM to enable for source level debugging (Look into additional "rom" folder).
        • -
      • [HW_INC] General: Updated/improved hardware register descriptions (inc/hw_*.h and doc/../*.html files).
        • -
      • -
    - -

    Bug fixes

    -
      -
    • CC26x0
      • - CC26x0R2 -
        -
      • [RF_API] Updated comment of txPower field to better describe function.
        • -
      -
    - -

    Known issues

    -
      -
    • None
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_00_01_17470

    -
    - Release date: November 15, 2016
    - -

    New features

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] RFC Added functions RFCClockSet() and RFCClockClear().
        • -
      • -
    • CC13x0 -
        -
      • [RF_PATCH] Added WMBUS C- and T-Mode CPE/MCE/RFE patch.
        • -
      • [RF_PATCH] Added SimpleLink Long Range CPE/MCE/RFE patch.
        • -
      • [RF_PATCH] New Wideband DSSS CPE/RFE patch. Same as GENFSK.
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [RF_API] General improvement of all comments.
        • -
      • -
    - -

    Bug fixes

    -
      -
    • CC26x0R2 -
        -
      • [DRV_SRC] FLASH Handle the FLASH:CFG.DIS_STANDBY configuration as for CC26x0.
        • -
      • -
    - -

    Known issues

    -
      -
    • None
      • -
    -
    -
    -
    -

    driverlib_cc13xx_cc26xx_3_00_00_17434

    -
    - Release date: October 28, 2016
    - -

    New features

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] sw_crypto: Added open source software crypto for ChaCha20 and Poly1305 into the library.
        • -
      • [DRV_SRC] rom_crypto: Removed direct access to the ROM located crypto software since it's only supported through crypto driver.
        • -
      • [DRV_SRC] ChipInfo: Added CC2630, CC2640 and CC2640R2 to known types returned from function ChipInfo_GetChipType().
        • -
      • [DRV_SRC] ChipInfo: Renamed CC13xx and CC26xx to CC13x0 and CC26x0. This applies to both chip family returned from function ChipInfo_GetChipFamily() and the name of all ChipInfo_ChipFamilyIs_...() functions.
        • -
      • -
    • CC13x0 -
        -
      • [RF_PATCH] New Wideband DSSS MCE patch.
        • -
      • -
    • CC26x0 -
        -
      • None
        • -
      • -
    • CC26x0R2 -
        -
      • Initial revision
        • -
      • -
    - -

    Improvements

    -
      -
    • Changes that apply to all devices -
        -
      • [DRV_SRC] ChipInfo: Code size optimization of all functions in the ChipInfo module.
        • -
      • [HW_INC] General: Updated/improved hardware register descriptions (inc/hw_*.h and doc/../*.html files).
        • -
      • -
    • CC13x0 -
        -
      • None
        • -
      • -
    • CC26x0 -
        -
      • [RF_PATCH] Updated BLE RFE patch. Improved startup sequence.
        • -
      • -
    • CC26x0R2 -
        -
      • Initial revision
        • -
      • -
    - -

    Bug fixes

    -
      -
    • None
      • -
    - -

    Known issues

    -
      -
    • None
      • -
    -
    -
    - - -
    - © 2016. Texas Instruments | All Rights Reserved -
    - - - diff --git a/third_party/ti/ti-openthread_1.01.0_manifest.html b/third_party/ti/ti-openthread_1.01.0_manifest.html deleted file mode 100644 index bf3ecf2bc..000000000 --- a/third_party/ti/ti-openthread_1.01.0_manifest.html +++ /dev/null @@ -1,1816 +0,0 @@ - - - - - - - Manifest File - - - - - -
    -
    - -
    -
    -
    -
    -

    - -ti-openthread Manifest - -

    - -

    - -06-05-2018 - -

    - - -

    - -Manifest ID - SRAS00005101 - -

    -
    -

    Legend

    -

    (explanation of the fields in the Manifest Table below)

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    -Software Name - -The name of the application or file -
    -Version - -Version of the application or file -
    -License Type - -Type of license(s) under which TI will be providing -software to the licensee (e.g. BSD-3-Clause, GPL-2.0, TI Text File License, TI -Commercial License). The license could be under Commercial terms or Open Source. See Open Source Reference License Disclaimer in -the Disclaimers Section. Whenever possible, TI will use an SPDX Short Identifier for an Open Source -License. TI Commercial license terms are not usually included in the manifest and are conveyed through a variety -of means such as a clickwrap license upon install, -a signed license agreement and so forth. -
    -Location - -The directory name and path on the media or a specific file where the Software is located. Typically fully qualified path names -are not used and instead the relevant top level directory of the application is given. -A notation often used in the manifests is [as installed]/directory/*. Note that the asterisk implies that all -files under that directory are licensed as the License Type field denotes. Any exceptions to this will -generally be denoted as [as installed]/directory/* except as noted below which means as shown in subsequent rows of -the manifest. -
    -Delivered As - -This field will either be “Source”, “Binary” or “Source -and Binary” and is the primary form the content of the Software is delivered -in. If the Software is delivered in an archive format, this field -applies to the contents of the archive. If the word Limited is used -with Source, as in “Limited Source” or “Limited Source and Binary” then -only portions of the Source for the application are provided. -
    -Modified by TI - -This field will either be “Yes” or “No”. A “Yes” means -TI has made changes to the Software. A “No” means TI has not made any -changes. Note: This field is not applicable for Software “Obtained -from” TI. -
    -Obtained from - -This field specifies from where or from whom TI obtained -the Software. It may be a URL to an Open Source site, a 3rd -party licensor, or TI. See Links Disclaimer in the Disclaimers -Section. -
    -
    -

    Disclaimers

    -

    Export Control Classification Number (ECCN)

    -

    Any use of ECCNs listed in the Manifest is at the user’s risk -and without recourse to TI. Your -company, as the exporter of record, is responsible for determining the -correct classification of any item at -the time of export. Any export classification by TI of Software is for -TI’s internal use only and shall not be construed as a representation -or warranty -regarding the proper export classification for such Software or whether -an export -license or other documentation is required for exporting such Software

    -

    Links in the Manifest

    -

    Any -links appearing on this Manifest -(for example in the “Obtained from” field) were verified at the time -the Manifest was created. TI makes no guarantee that any listed links -will -remain active in the future.

    -

    Open Source License References

    -

    Your company is responsible for confirming the -applicable license terms for any open source Software -listed in this Manifest that was not “Obtained from” TI. Any open -source license -specified in this Manifest for Software that was -not “Obtained from” TI is for TI’s internal use only and shall not be -construed as a representation or warranty regarding the proper open -source license terms -for such Software.

    -
    -

    Export Information

    -

    ECCN for Software included in this release:

    -Publicly Available -
    - - - - - -

    - ti-openthread OpenThread Code -

    - - -

    - - See the Legend above for a description of these columns. - -

    - -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Software NameVersionLicense TypeDelivered AsModified by TI
    - CI build scripts - - 0.01.00 - - BSD-3-Clause - - Source - - Yes - Location - [as_installed]/.appveyor[as_installed]/.appveyor.yml[as_installed]/.codecov.yml[as_installed]/.travis -
    Obtained from - github.com/openthread/openthread -
    - OpenThread test automation tools - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/tools -
    Obtained from - github.com/openthread/openthread -
    - synopsys third party - - Unknown - - BSD-3-Clause - - Source - - No - Location - [as_installed]/third_party/synopsys -
    Obtained from - github.com/openthread/openthread -
    - Qorvo third party - - 0.8.0.0 - - Qorvo Proprietary - - Binary - - No - Location - [as_installed]/third_party/Qorvo -
    Obtained from - github.com/openthread/openthread -
    - OpenThread test driver - - 2016-01-11.22 - - GPL-2.0 - - Source - - No - Location - [as_installed]/third_party/openthread-test-driver -
    Obtained from - github.com/openthread/openthread -
    - NXP third party - - 2.0 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/third_party/nxp -
    Obtained from - github.com/openthread/openthread -
    - Nordic Semiconductor third party - - 12.2.0 - - BSD-3-Clause - - Source and Binary - - No - Location - [as_installed]/third_party/NordicSemiconductor -
    Obtained from - github.com/openthread/openthread -
    - Nest autotools - - Unknown - - Apache-2.0 - - Source and Binary - - No - Location - [as_installed]/third_party/nlbuild-autotools -
    Obtained from - github.com/openthread/openthread -
    - Mbed TLS - - 2.3.1 - - Apache-2.0 - - Source - - No - Location - [as_installed]/third_party/mbedtls -
    Obtained from - github.com/openthread/openthread -
    - Dialog third party - - Unknown - - BSD-3-Clause - - Source and Binary - - No - Location - [as_installed]/third_party/dialog -
    Obtained from - github.com/openthread/openthread -
    - OpenThread test harness - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/tests -
    Obtained from - github.com/openthread/openthread -
    - OpenThread - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/src/ -
    Obtained from - github.com/openthread/openthread -
    - Environment and Build Scripts - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/script/[as_installed]/bootstrap[as_installed]/configure.ac[as_installed]/Makefile.am -
    Obtained from - github.com/openthread/openthread -
    - OpenThread includes - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/include -
    Obtained from - github.com/openthread/openthread -
    - Windows Driver - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/drivers -
    Obtained from - github.com/openthread/openthread -
    - Examples - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/apps -
    Obtained from - github.com/openthread/openthread -
    - samr21 Makefile - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/Makefile-samr21 -
    Obtained from - github.com/openthread/openthread -
    - samr21 platform layer - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/platforms/samr21 -
    Obtained from - github.com/openthread/openthread -
    - Posix Makefile - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/Makefile-simulation -
    Obtained from - github.com/openthread/openthread -
    - simulation platform layer - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/platforms/simulation -
    Obtained from - github.com/openthread/openthread -
    - nrf52840 Makefile - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/Makefile- nrf52840 -
    Obtained from - github.com/openthread/openthread -
    - nrf52840 platform layer - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/platforms/ nrf52840 -
    Obtained from - github.com/openthread/openthread -
    - kw41z Makefile - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/Makefile-kw41z -
    Obtained from - github.com/openthread/openthread -
    - kw41z platform layer - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/platforms/kw41z -
    Obtained from - github.com/openthread/openthread -
    - gp712 Makefile - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/Makefile-gp712 -
    Obtained from - github.com/openthread/openthread -
    - gp712 platform layer - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/platforms/gp712 -
    Obtained from - github.com/openthread/openthread -
    - emsk Makefile - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/Makefile-emsk -
    Obtained from - github.com/openthread/openthread -
    - emsk platform layer - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/platforms/emsk -
    Obtained from - github.com/openthread/openthread -
    - erf32 Makefile - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/Makefile-erf32 -
    Obtained from - github.com/openthread/openthread -
    - erf32 platform layer - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/platforms/erf32 -
    Obtained from - github.com/openthread/openthread -
    - da15000 Makefile - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/Makefile- da15000 -
    Obtained from - github.com/openthread/openthread -
    - da15000 platform layer - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/platforms/da15000 -
    Obtained from - github.com/openthread/openthread -
    - cc2538 Makefile - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/Makefile-cc2538 -
    Obtained from - github.com/openthread/openthread -
    - cc2538 platform layer - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/examples/platforms/cc2538 -
    Obtained from - github.com/openthread/openthread -
    - Windows Build - - 0.01.00 - - BSD-3-Clause - - Source and Binary - - No - Location - [as_installed]/etc/visual-studio -
    Obtained from - github.com/openthread/openthread -
    - Vagrant Environment - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/etc/vagrant -
    Obtained from - github.com/openthread/openthread -
    - OpenThread documentation - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/doc[as_installed]/.default-version[as_installed]/AUTHORS[as_installed]/CODE_OF_CONDUCT.md[as_installed]/CONTRIBUTING.md[as_installed]/LICENSE[as_installed]/NOTICE[as_installed]/README.md[as_installed]/STYLE_GUIDE.md -
    Obtained from - github.com/openthread/openthread -
    - Travis CI build scripts - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/.travis -
    Obtained from - github.com/openthread/openthread -
    - Github templates - - 0.01.00 - - BSD-3-Clause - - Source - - No - Location - [as_installed]/.github -
    Obtained from - github.com/openthread/openthread -
    - -

    - - - -

    - ti-openthread Platform Layer Manifest Table -

    - - -

    - - See the Legend above for a description of these columns. - -

    - -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Software NameVersionLicense TypeDelivered AsModified by TI
    - cc1352 platform layer - - 0.01.0 - - BSD-3-Clause - - Source - - N/A - Location - [as_installed]/examples/platforms/cc1352 -
    Obtained from - Texas Instruments Incorporated -
    - cc1352 platform Makefile - - 0.01.0 - - BSD-3-Clause - - Source - - N/A - Location - [as_installed]/examples/Makefile-cc1352 -
    Obtained from - Texas Instruments Incorporated -
    - cc2650 platform layer - - 0.01.0 - - BSD-3-Clause - - Source - - N/A - Location - [as_installed]/examples/platforms/cc2650 -
    Obtained from - Texas Intstruments Incorporated -
    - cc2650 platform Makefile - - 0.01.0 - - BSD-3-Clause - - Source - - N/A - Location - [as_installed]/examples/Makefile-cc2650 -
    Obtained from - Texas Instruments Incorporated -
    - cc2652 platform layer - - 0.01.0 - - BSD-3-Clause - - Source - - N/A - Location - [as_installed]/examples/platforms/cc2652 -
    Obtained from - Texas Instruments Incorporated -
    - cc2652 platform Makefile - - 0.01.0 - - BSD-3-Clause - - Source - - N/A - Location - [as_installed]/examples/Makefile-cc2652 -
    Obtained from - Texas Instruments Incorporated -
    - -

    -

    -

    - - - - -

    - Driverlib_CC13xx_CC26xx Manifest Table -

    - - -

    - - See the Legend above for a description of these columns. - -

    - -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Software NameVersionLicense TypeDelivered AsModified by TI
    - driverlib - - 3.xx.xx - - BSD-3-Clause - - Source and binary - - N/A - Location - driverlib, driverlib/bin -
    Obtained from - TI -
    - CC13xx/CC26xx RF patches - - 3.xx.xx - - BSD-3-Clause - - Source - - N/A - Location - rf_patches -
    Obtained from - TI -
    - CC13xx/CC26xx hardware header files - - 3.xx.xx - - BSD-3-Clause - - Source - - N/A - Location - inc -
    Obtained from - TI -
    - CC13xx/CC26xx startup files - - 3.xx.xx - - BSD-3-Clause - - Source - - N/A - Location - startup_files -
    Obtained from - TI -
    - CC13xx/CC26xx linker files - - 3.xx.xx - - BSD-3-Clause - - Source - - N/A - Location - linker_files -
    Obtained from - TI -
    - jquery.js - - 1.7.1 - - MIT - - Source - - No - Location - doc/driverlib -
    Obtained from - jquery.org -
    - ChaCha cipher - - 20080118 - - Public domain - - Source and binary - - Yes - Location - driverlib,driverlib/bin -
    Obtained from - http://cr.yp.to/chacha.html,2016-10-07 -
    - poly1305-donna,32 bit - - e6ad6e0(Mar 29 2016) - - MIT - - Source and binary - - Yes - Location - driverlib/sw_poly1305*,driverlib/bin -
    Obtained from - https://github.com/floodyberry/poly1305-donna,2016-10-07 -
    - -

    -

    -

    - -

    -

    Credits

    -









    -
    -

    Licenses

    -

    ti-openthread Licenses




    BSD-3-Clause
    ------------

    Copyright (c) 2016, The OpenThread Authors.
    All rights reserved.

    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
    1. Redistributions of source code must retain the above copyright
    notice, this list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright
    notice, this list of conditions and the following disclaimer in the
    documentation and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the
    names of its contributors may be used to endorse or promote products
    derived from this software without specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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    Apache-2.0 License
    ------------

    Apache License
    Version 2.0, January 2004
    http://www.apache.org/licenses/

    TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION

    1. Definitions.

    "License" shall mean the terms and conditions for use, reproduction,
    and distribution as defined by Sections 1 through 9 of this document.

    "Licensor" shall mean the copyright owner or entity authorized by
    the copyright owner that is granting the License.

    "Legal Entity" shall mean the union of the acting entity and all
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    "You" (or "Your") shall mean an individual or Legal Entity
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    "Object" form shall mean any form resulting from mechanical
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    "Work" shall mean the work of authorship, whether in Source or
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    (an example is provided in the Appendix below).

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    "Contribution" shall mean any work of authorship, including
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    (b) You must cause any modified files to carry prominent notices
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    You may add Your own copyright statement to Your modifications and
    may provide additional or different license terms and conditions
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    5. Submission of Contributions. Unless You explicitly state otherwise,
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    by You to the Licensor shall be under the terms and conditions of
    this License, without any additional terms or conditions.
    Notwithstanding the above, nothing herein shall supersede or modify
    the terms of any separate license agreement you may have executed
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    6. Trademarks. This License does not grant permission to use the trade
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    whether in tort (including negligence), contract, or otherwise,
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    liable to You for damages, including any direct, indirect, special,
    incidental, or consequential damages of any character arising as a
    result of this License or out of the use or inability to use the
    Work (including but not limited to damages for loss of goodwill,
    work stoppage, computer failure or malfunction, or any and all
    other commercial damages or losses), even if such Contributor
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    9. Accepting Warranty or Additional Liability. While redistributing
    the Work or Derivative Works thereof, You may choose to offer,
    and charge a fee for, acceptance of support, warranty, indemnity,
    or other liability obligations and/or rights consistent with this
    License. However, in accepting such obligations, You may act only
    on Your own behalf and on Your sole responsibility, not on behalf
    of any other Contributor, and only if You agree to indemnify,
    defend, and hold each Contributor harmless for any liability
    incurred by, or claims asserted against, such Contributor by reason
    of your accepting any such warranty or additional liability.

    END OF TERMS AND CONDITIONS

    APPENDIX: How to apply the Apache License to your work.

    To apply the Apache License to your work, attach the following
    boilerplate notice, with the fields enclosed by brackets "[]"
    replaced with your own identifying information. (Don't include
    the brackets!) The text should be enclosed in the appropriate
    comment syntax for the file format. We also recommend that a
    file or class name and description of purpose be included on the
    same "printed page" as the copyright notice for easier
    identification within third-party archives.

    Copyright [yyyy] [name of copyright owner]

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.


    GPL-2.0 License
    ------------
    GNU GENERAL PUBLIC LICENSE
    Version 2, June 1991

    Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
    Everyone is permitted to copy and distribute verbatim copies
    of this license document, but changing it is not allowed.

    Preamble

    The licenses for most software are designed to take away your
    freedom to share and change it. By contrast, the GNU General Public
    License is intended to guarantee your freedom to share and change free
    software--to make sure the software is free for all its users. This
    General Public License applies to most of the Free Software
    Foundation's software and to any other program whose authors commit to
    using it. (Some other Free Software Foundation software is covered by
    the GNU Lesser General Public License instead.) You can apply it to
    your programs, too.

    When we speak of free software, we are referring to freedom, not
    price. Our General Public Licenses are designed to make sure that you
    have the freedom to distribute copies of free software (and charge for
    this service if you wish), that you receive source code or can get it
    if you want it, that you can change the software or use pieces of it
    in new free programs; and that you know you can do these things.

    To protect your rights, we need to make restrictions that forbid
    anyone to deny you these rights or to ask you to surrender the rights.
    These restrictions translate to certain responsibilities for you if you
    distribute copies of the software, or if you modify it.

    For example, if you distribute copies of such a program, whether
    gratis or for a fee, you must give the recipients all the rights that
    you have. You must make sure that they, too, receive or can get the
    source code. And you must show them these terms so they know their
    rights.

    We protect your rights with two steps: (1) copyright the software, and
    (2) offer you this license which gives you legal permission to copy,
    distribute and/or modify the software.

    Also, for each author's protection and ours, we want to make certain
    that everyone understands that there is no warranty for this free
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    want its recipients to know that what they have is not the original, so
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    authors' reputations.

    Finally, any free program is threatened constantly by software
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    program will individually obtain patent licenses, in effect making the
    program proprietary. To prevent this, we have made it clear that any
    patent must be licensed for everyone's free use or not licensed at all.

    The precise terms and conditions for copying, distribution and
    modification follow.

    GNU GENERAL PUBLIC LICENSE
    TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION

    0. This License applies to any program or other work which contains
    a notice placed by the copyright holder saying it may be distributed
    under the terms of this General Public License. The "Program", below,
    refers to any such program or work, and a "work based on the Program"
    means either the Program or any derivative work under copyright law:
    that is to say, a work containing the Program or a portion of it,
    either verbatim or with modifications and/or translated into another
    language. (Hereinafter, translation is included without limitation in
    the term "modification".) Each licensee is addressed as "you".

    Activities other than copying, distribution and modification are not
    covered by this License; they are outside its scope. The act of
    running the Program is not restricted, and the output from the Program
    is covered only if its contents constitute a work based on the
    Program (independent of having been made by running the Program).
    Whether that is true depends on what the Program does.

    1. You may copy and distribute verbatim copies of the Program's
    source code as you receive it, in any medium, provided that you
    conspicuously and appropriately publish on each copy an appropriate
    copyright notice and disclaimer of warranty; keep intact all the
    notices that refer to this License and to the absence of any warranty;
    and give any other recipients of the Program a copy of this License
    along with the Program.

    You may charge a fee for the physical act of transferring a copy, and
    you may at your option offer warranty protection in exchange for a fee.

    2. You may modify your copy or copies of the Program or any portion
    of it, thus forming a work based on the Program, and copy and
    distribute such modifications or work under the terms of Section 1
    above, provided that you also meet all of these conditions:

    a) You must cause the modified files to carry prominent notices
    stating that you changed the files and the date of any change.

    b) You must cause any work that you distribute or publish, that in
    whole or in part contains or is derived from the Program or any
    part thereof, to be licensed as a whole at no charge to all third
    parties under the terms of this License.

    c) If the modified program normally reads commands interactively
    when run, you must cause it, when started running for such
    interactive use in the most ordinary way, to print or display an
    announcement including an appropriate copyright notice and a
    notice that there is no warranty (or else, saying that you provide
    a warranty) and that users may redistribute the program under
    these conditions, and telling the user how to view a copy of this
    License. (Exception: if the Program itself is interactive but
    does not normally print such an announcement, your work based on
    the Program is not required to print an announcement.)

    These requirements apply to the modified work as a whole. If
    identifiable sections of that work are not derived from the Program,
    and can be reasonably considered independent and separate works in
    themselves, then this License, and its terms, do not apply to those
    sections when you distribute them as separate works. But when you
    distribute the same sections as part of a whole which is a work based
    on the Program, the distribution of the whole must be on the terms of
    this License, whose permissions for other licensees extend to the
    entire whole, and thus to each and every part regardless of who wrote it.

    Thus, it is not the intent of this section to claim rights or contest
    your rights to work written entirely by you; rather, the intent is to
    exercise the right to control the distribution of derivative or
    collective works based on the Program.

    In addition, mere aggregation of another work not based on the Program
    with the Program (or with a work based on the Program) on a volume of
    a storage or distribution medium does not bring the other work under
    the scope of this License.

    3. You may copy and distribute the Program (or a work based on it,
    under Section 2) in object code or executable form under the terms of
    Sections 1 and 2 above provided that you also do one of the following:

    a) Accompany it with the complete corresponding machine-readable
    source code, which must be distributed under the terms of Sections
    1 and 2 above on a medium customarily used for software interchange; or,

    b) Accompany it with a written offer, valid for at least three
    years, to give any third party, for a charge no more than your
    cost of physically performing source distribution, a complete
    machine-readable copy of the corresponding source code, to be
    distributed under the terms of Sections 1 and 2 above on a medium
    customarily used for software interchange; or,

    c) Accompany it with the information you received as to the offer
    to distribute corresponding source code. (This alternative is
    allowed only for noncommercial distribution and only if you
    received the program in object code or executable form with such
    an offer, in accord with Subsection b above.)

    The source code for a work means the preferred form of the work for
    making modifications to it. For an executable work, complete source
    code means all the source code for all modules it contains, plus any
    associated interface definition files, plus the scripts used to
    control compilation and installation of the executable. However, as a
    special exception, the source code distributed need not include
    anything that is normally distributed (in either source or binary
    form) with the major components (compiler, kernel, and so on) of the
    operating system on which the executable runs, unless that component
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    If distribution of executable or object code is made by offering
    access to copy from a designated place, then offering equivalent
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    distribution of the source code, even though third parties are not
    compelled to copy the source along with the object code.

    4. You may not copy, modify, sublicense, or distribute the Program
    except as expressly provided under this License. Any attempt
    otherwise to copy, modify, sublicense or distribute the Program is
    void, and will automatically terminate your rights under this License.
    However, parties who have received copies, or rights, from you under
    this License will not have their licenses terminated so long as such
    parties remain in full compliance.

    5. You are not required to accept this License, since you have not
    signed it. However, nothing else grants you permission to modify or
    distribute the Program or its derivative works. These actions are
    prohibited by law if you do not accept this License. Therefore, by
    modifying or distributing the Program (or any work based on the
    Program), you indicate your acceptance of this License to do so, and
    all its terms and conditions for copying, distributing or modifying
    the Program or works based on it.

    6. Each time you redistribute the Program (or any work based on the
    Program), the recipient automatically receives a license from the
    original licensor to copy, distribute or modify the Program subject to
    these terms and conditions. You may not impose any further
    restrictions on the recipients' exercise of the rights granted herein.
    You are not responsible for enforcing compliance by third parties to
    this License.

    7. If, as a consequence of a court judgment or allegation of patent
    infringement or for any other reason (not limited to patent issues),
    conditions are imposed on you (whether by court order, agreement or
    otherwise) that contradict the conditions of this License, they do not
    excuse you from the conditions of this License. If you cannot
    distribute so as to satisfy simultaneously your obligations under this
    License and any other pertinent obligations, then as a consequence you
    may not distribute the Program at all. For example, if a patent
    license would not permit royalty-free redistribution of the Program by
    all those who receive copies directly or indirectly through you, then
    the only way you could satisfy both it and this License would be to
    refrain entirely from distribution of the Program.

    If any portion of this section is held invalid or unenforceable under
    any particular circumstance, the balance of the section is intended to
    apply and the section as a whole is intended to apply in other
    circumstances.

    It is not the purpose of this section to induce you to infringe any
    patents or other property right claims or to contest validity of any
    such claims; this section has the sole purpose of protecting the
    integrity of the free software distribution system, which is
    implemented by public license practices. Many people have made
    generous contributions to the wide range of software distributed
    through that system in reliance on consistent application of that
    system; it is up to the author/donor to decide if he or she is willing
    to distribute software through any other system and a licensee cannot
    impose that choice.

    This section is intended to make thoroughly clear what is believed to
    be a consequence of the rest of this License.

    8. If the distribution and/or use of the Program is restricted in
    certain countries either by patents or by copyrighted interfaces, the
    original copyright holder who places the Program under this License
    may add an explicit geographical distribution limitation excluding
    those countries, so that distribution is permitted only in or among
    countries not thus excluded. In such case, this License incorporates
    the limitation as if written in the body of this License.

    9. The Free Software Foundation may publish revised and/or new versions
    of the General Public License from time to time. Such new versions will
    be similar in spirit to the present version, but may differ in detail to
    address new problems or concerns.

    Each version is given a distinguishing version number. If the Program
    specifies a version number of this License which applies to it and "any
    later version", you have the option of following the terms and conditions
    either of that version or of any later version published by the Free
    Software Foundation. If the Program does not specify a version number of
    this License, you may choose any version ever published by the Free Software
    Foundation.

    10. If you wish to incorporate parts of the Program into other free
    programs whose distribution conditions are different, write to the author
    to ask for permission. For software which is copyrighted by the Free
    Software Foundation, write to the Free Software Foundation; we sometimes
    make exceptions for this. Our decision will be guided by the two goals
    of preserving the free status of all derivatives of our free software and
    of promoting the sharing and reuse of software generally.

    NO WARRANTY

    11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
    FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
    OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
    PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
    OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
    TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
    PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
    REPAIR OR CORRECTION.

    12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
    WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
    REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
    INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
    OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
    TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
    YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
    PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGES.

    END OF TERMS AND CONDITIONS

    How to Apply These Terms to Your New Programs

    If you develop a new program, and you want it to be of the greatest
    possible use to the public, the best way to achieve this is to make it
    free software which everyone can redistribute and change under these terms.

    To do so, attach the following notices to the program. It is safest
    to attach them to the start of each source file to most effectively
    convey the exclusion of warranty; and each file should have at least
    the "copyright" line and a pointer to where the full notice is found.

    <one line to give the program's name and a brief idea of what it does.>
    Copyright (C) <year> <name of author>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License along
    with this program; if not, write to the Free Software Foundation, Inc.,
    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

    Also add information on how to contact you by electronic and paper mail.

    If the program is interactive, make it output a short notice like this
    when it starts in an interactive mode:

    Gnomovision version 69, Copyright (C) year name of author
    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
    This is free software, and you are welcome to redistribute it
    under certain conditions; type `show c' for details.

    The hypothetical commands `show w' and `show c' should show the appropriate
    parts of the General Public License. Of course, the commands you use may
    be called something other than `show w' and `show c'; they could even be
    mouse-clicks or menu items--whatever suits your program.

    You should also get your employer (if you work as a programmer) or your
    school, if any, to sign a "copyright disclaimer" for the program, if
    necessary. Here is a sample; alter the names:

    Yoyodyne, Inc., hereby disclaims all copyright interest in the program
    `Gnomovision' (which makes passes at compilers) written by James Hacker.

    <signature of Ty Coon>, 1 April 1989
    Ty Coon, President of Vice

    This General Public License does not permit incorporating your program into
    proprietary programs. If your program is a subroutine library, you may
    consider it more useful to permit linking proprietary applications with the
    library. If this is what you want to do, use the GNU Lesser General
    Public License instead of this License.


    Qorvo Proprietary
    ------------

    Copyright (c) 2012-2016, GreenPeak Technologies
    Copyright (c) 2017, Qorvo Inc

    This software is owned by Qorvo Inc
    and protected under applicable copyright laws.
    It is delivered under the terms of the license
    and is intended and supplied for use solely and
    exclusively with products manufactured by
    Qorvo Inc.

    THIS SOFTWARE IS PROVIDED IN AN "AS IS"
    CONDITION. NO WARRANTIES, WHETHER EXPRESS,
    IMPLIED OR STATUTORY, INCLUDING, BUT NOT
    LIMITED TO, IMPLIED WARRANTIES OF
    MERCHANTABILITY AND FITNESS FOR A
    PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
    QORVO INC. SHALL NOT, IN ANY
    CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
    INCIDENTAL OR CONSEQUENTIAL DAMAGES,
    FOR ANY REASON WHATSOEVER.


    Driverlib_CC13xx_CC26xx License




    BSD-3-Clause license:
    Copyright (c) 2016, Texas Instruments Incorporated
    All rights reserved.

    Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

    1) Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

    2) Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

    3) Neither the name of the ORGANIZATION nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


    MIT license for jquery:

    Copyright 2011, John Resig
    Copyright 2011, The Dojo Foundation
    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to deal
    in the Software without restriction, including without limitation the rights
    to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    copies of the Software, and to permit persons to whom the Software is
    furnished to do so, subject to the following conditions:
    The above copyright notice and this permission notice shall be included in
    all copies or substantial portions of the Software.
    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
    AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    THE SOFTWARE.
    MIT license for poly1305-donna:
    Copyright (c) 2016 Andrew Moon (floodberry @ github)
    Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
    The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.



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