From b9d20b590e51b410c6f6faa0b3c886aa303cf248 Mon Sep 17 00:00:00 2001 From: Seth Rickard Date: Tue, 4 Jun 2019 17:04:46 -0500 Subject: [PATCH] [cc13x2,cc26x2] update CC13X2 CC26X2 driverlib (#3888) --- examples/platforms/cc1352/radio.c | 40 +- examples/platforms/cc2652/radio.c | 41 +- third_party/ti/README.md | 11 +- .../ti/devices/cc13x2_cc26x2/driverlib/aes.c | 5 +- .../ti/devices/cc13x2_cc26x2/driverlib/aes.h | 17 +- .../driverlib/bin/ccs/driverlib.lib | Bin 1658276 -> 1713930 bytes .../cc13x2_cc26x2/driverlib/bin/ccs/makefile | 4 +- .../driverlib/bin/gcc/driverlib.a | Bin 384530 -> 402288 bytes .../cc13x2_cc26x2/driverlib/bin/gcc/makefile | 4 +- .../driverlib/bin/iar/driverlib.lib | Bin 873144 -> 914248 bytes .../cc13x2_cc26x2/driverlib/bin/iar/makefile | 5 +- .../driverlib/bin/keil/driverlib.lib | Bin 167772 -> 171862 bytes .../cc13x2_cc26x2/driverlib/bin/keil/makefile | 4 +- .../cc13x2_cc26x2/driverlib/chipinfo.c | 20 +- .../cc13x2_cc26x2/driverlib/chipinfo.h | 16 +- .../ti/devices/cc13x2_cc26x2/driverlib/cpu.h | 8 +- .../ti/devices/cc13x2_cc26x2/driverlib/ddi.c | 6 +- .../ti/devices/cc13x2_cc26x2/driverlib/ddi.h | 60 +- .../driverlib/driverlib_release.c | 2 +- .../driverlib/driverlib_release.h | 6 +- .../ti/devices/cc13x2_cc26x2/driverlib/i2s.h | 551 ++- .../devices/cc13x2_cc26x2/driverlib/i2s_doc.h | 141 + .../ti/devices/cc13x2_cc26x2/driverlib/osc.c | 199 +- .../ti/devices/cc13x2_cc26x2/driverlib/osc.h | 187 +- .../ti/devices/cc13x2_cc26x2/driverlib/pka.c | 31 +- .../ti/devices/cc13x2_cc26x2/driverlib/pka.h | 18 +- .../ti/devices/cc13x2_cc26x2/driverlib/prcm.c | 66 +- .../ti/devices/cc13x2_cc26x2/driverlib/prcm.h | 82 +- .../cc13x2_cc26x2/driverlib/rf_ble_cmd.h | 164 +- .../cc13x2_cc26x2/driverlib/rf_ble_mailbox.h | 5 +- .../cc13x2_cc26x2/driverlib/rf_common_cmd.h | 30 +- .../cc13x2_cc26x2/driverlib/rf_data_entry.h | 4 +- .../cc13x2_cc26x2/driverlib/rf_hs_cmd.h | 4 +- .../cc13x2_cc26x2/driverlib/rf_hs_mailbox.h | 4 +- .../cc13x2_cc26x2/driverlib/rf_ieee_cmd.h | 4 +- .../cc13x2_cc26x2/driverlib/rf_mailbox.h | 25 +- .../cc13x2_cc26x2/driverlib/rf_prop_cmd.h | 4 +- .../cc13x2_cc26x2/driverlib/rf_prop_mailbox.h | 4 +- .../ti/devices/cc13x2_cc26x2/driverlib/rfc.c | 75 +- .../ti/devices/cc13x2_cc26x2/driverlib/rfc.h | 36 +- .../ti/devices/cc13x2_cc26x2/driverlib/rom.h | 264 +- .../cc13x2_cc26x2/driverlib/rom_crypto.c | 159 + .../cc13x2_cc26x2/driverlib/rom_crypto.h | 212 ++ .../devices/cc13x2_cc26x2/driverlib/setup.c | 198 +- .../devices/cc13x2_cc26x2/driverlib/setup.h | 25 +- .../cc13x2_cc26x2/driverlib/setup_rom.h | 59 +- .../cc13x2_cc26x2/driverlib/sys_ctrl.c | 13 +- .../cc13x2_cc26x2/driverlib/sys_ctrl.h | 4 +- .../cc13x2_cc26x2/inc/hw_adi_2_refsys.h | 4 +- .../cc13x2_cc26x2/inc/hw_adi_3_refsys.h | 22 +- .../devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h | 35 +- .../devices/cc13x2_cc26x2/inc/hw_aon_batmon.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_aon_event.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_aux_anaif.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_aux_evctl.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_aux_smph.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_aux_spim.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_aux_sysif.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h | 4 +- .../cc13x2_cc26x2/inc/hw_aux_timer01.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_aux_timer2.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h | 8 +- .../cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_chip_def.h | 2 +- .../ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h | 4 +- .../cc13x2_cc26x2/inc/hw_cpu_rom_table.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_crypto.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_event.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h | 495 +-- .../ti/devices/cc13x2_cc26x2/inc/hw_flash.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_gpio.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_gpram.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_gpt.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_i2c.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_i2s.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_ints.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_ioc.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_memmap.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_pka.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_prcm.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_smph.h | 4 +- .../devices/cc13x2_cc26x2/inc/hw_sram_mmr.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_ssi.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_trng.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_uart.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_udma.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_vims.h | 4 +- .../ti/devices/cc13x2_cc26x2/inc/hw_wdt.h | 4 +- .../cc13x2_cc26x2/linker_files/cc26x2r1f.cmd | 6 +- .../cc13x2_cc26x2/linker_files/cc26x2r1f.icf | 6 +- .../cc13x2_cc26x2/linker_files/cc26x2r1f.lds | 6 +- .../cc13x2_cc26x2/linker_files/cc26x2r1f.sct | 6 +- .../linker_files/cc26x2r1f_ram.icf | 143 - .../rf_patches/rf_patch_cpe_ble.h | 321 -- .../rf_patches/rf_patch_cpe_bt5.h | 555 +-- .../rf_patches/rf_patch_cpe_ieee_802_15_4.h | 163 +- .../rf_patches/rf_patch_cpe_multi_protocol.h | 724 +--- .../rf_patch_cpe_multi_protocol_rtls.h | 1452 ++++++++ .../rf_patches/rf_patch_cpe_prop.h | 405 +-- .../rf_patches/rf_patch_mce_bt5.h | 623 ---- .../rf_patches/rf_patch_mce_genfsk.h | 591 ---- .../rf_patches/rf_patch_mce_ieee_802_15_4.h | 479 --- .../rf_patches/rf_patch_mce_iqdump.h | 438 +++ .../rf_patches/rf_patch_mce_sl_longrange.h | 335 -- .../rf_patches/rf_patch_mce_slr.h | 365 -- .../rf_patches/rf_patch_mce_tof.h | 609 ++++ .../rf_patches/rf_patch_rfe_bt5.h | 610 ---- .../rf_patches/rf_patch_rfe_genfsk.h | 611 ---- .../rf_patches/rf_patch_rfe_ieee_802_15_4.h | 438 --- .../rf_patches/rf_patch_rfe_tof.h | 571 ++++ .../ti/devices/cc13x2_cc26x2/rom/driverlib.c | 3025 ++++++++++++----- .../devices/cc13x2_cc26x2/rom/driverlib.elf | Bin 343036 -> 372940 bytes .../cc13x2_cc26x2/startup_files/ccfg.c | 8 +- .../cc13x2_cc26x2/startup_files/startup_ccs.c | 2 +- .../cc13x2_cc26x2/startup_files/startup_gcc.c | 2 +- .../cc13x2_cc26x2/startup_files/startup_iar.c | 2 +- .../startup_files/startup_keil.s | 2 +- ...release_notes_driverlib_cc13xx_cc26xx.html | 1454 +++++++- 137 files changed, 9449 insertions(+), 8098 deletions(-) create mode 100644 third_party/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h create mode 100644 third_party/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c create mode 100644 third_party/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h delete mode 100644 third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f_ram.icf delete mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ble.h create mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h delete mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_bt5.h delete mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_genfsk.h delete mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_ieee_802_15_4.h create mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h delete mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_sl_longrange.h delete mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_slr.h create mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h delete mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_bt5.h delete mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_genfsk.h delete mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_ieee_802_15_4.h create mode 100644 third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h diff --git a/examples/platforms/cc1352/radio.c b/examples/platforms/cc1352/radio.c index 00ee63156..6b4d8965d 100644 --- a/examples/platforms/cc1352/radio.c +++ b/examples/platforms/cc1352/radio.c @@ -58,8 +58,6 @@ #include #include #include -#include -#include enum { @@ -81,38 +79,10 @@ static output_config_t const *sCurrentOutputPower = &(rgOutputPower[0]); /* Overrides from SmartRF Studio 7 2.10.0#94 */ static uint32_t sIEEEOverrides[] = { // override_ieee_802_15_4.xml - // PHY: Use MCE RAM patch, RFE ROM bank 1 - MCE_RFE_OVERRIDE(1, 0, 0, 0, 1, 0), - // Synth: Use 48 MHz crystal, enable extra PLL filtering - (uint32_t)0x02400403, - // Synth: Configure extra PLL filtering - (uint32_t)0x001C8473, - // Synth: Configure synth hardware - (uint32_t)0x00088433, - // Synth: Set minimum RTRIM to 3 - (uint32_t)0x00038793, - // Synth: Configure faster calibration - HW32_ARRAY_OVERRIDE(0x4004, 1), - // Synth: Configure faster calibration - (uint32_t)0x1C0C0618, - // Synth: Configure faster calibration - (uint32_t)0xC00401A1, - // Synth: Configure faster calibration - (uint32_t)0x00010101, - // Synth: Configure faster calibration - (uint32_t)0xC0040141, - // Synth: Configure faster calibration - (uint32_t)0x00214AD3, - // Synth: Decrease synth programming time-out (0x0298 RAT ticks = 166 us) - (uint32_t)0x02980243, - // DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). In Rx, use DCDCCTL5[3:0]=0xC - // (DITHER_EN=1 and IPEAK=4). - (uint32_t)0xFCFC08C3, + // DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0x3 (DITHER_EN=0 and IPEAK=3). + (uint32_t)0x00F388D3, // Rx: Set LNA bias current offset to +15 to saturate trim to max (default: 0) - (uint32_t)0x000F8883, - // override_frontend_id.xml - (uint32_t)0xFFFFFFFF, -}; + (uint32_t)0x000F8883, (uint32_t)0xFFFFFFFF}; /* * Number of retry counts left to the currently transmitting frame. @@ -919,13 +889,11 @@ static void rfCorePowerOff(void) } /** - * Applies CPE, RFE, and MCE patches to the radio. + * Applies CPE patche to the radio. */ static void rfCoreApplyPatch(void) { rf_patch_cpe_ieee_802_15_4(); - rf_patch_mce_ieee_802_15_4(); - rf_patch_rfe_ieee_802_15_4(); /* disable ram bus clocks */ RFCDoorbellSendTo(CMDR_DIR_CMD_2BYTE(CC1352_RF_CMD0, 0)); diff --git a/examples/platforms/cc2652/radio.c b/examples/platforms/cc2652/radio.c index 71805ded6..08aabefa0 100644 --- a/examples/platforms/cc2652/radio.c +++ b/examples/platforms/cc2652/radio.c @@ -57,8 +57,6 @@ #include #include #include -#include -#include enum { @@ -80,38 +78,10 @@ static output_config_t const *sCurrentOutputPower = &(rgOutputPower[0]); /* Overrides from SmartRF Studio 7 2.10.0#94 */ static uint32_t sIEEEOverrides[] = { // override_ieee_802_15_4.xml - // PHY: Use MCE RAM patch, RFE ROM bank 1 - MCE_RFE_OVERRIDE(1, 0, 0, 0, 1, 0), - // Synth: Use 48 MHz crystal, enable extra PLL filtering - (uint32_t)0x02400403, - // Synth: Configure extra PLL filtering - (uint32_t)0x001C8473, - // Synth: Configure synth hardware - (uint32_t)0x00088433, - // Synth: Set minimum RTRIM to 3 - (uint32_t)0x00038793, - // Synth: Configure faster calibration - HW32_ARRAY_OVERRIDE(0x4004, 1), - // Synth: Configure faster calibration - (uint32_t)0x1C0C0618, - // Synth: Configure faster calibration - (uint32_t)0xC00401A1, - // Synth: Configure faster calibration - (uint32_t)0x00010101, - // Synth: Configure faster calibration - (uint32_t)0xC0040141, - // Synth: Configure faster calibration - (uint32_t)0x00214AD3, - // Synth: Decrease synth programming time-out (0x0298 RAT ticks = 166 us) - (uint32_t)0x02980243, - // DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). In Rx, use DCDCCTL5[3:0]=0xC - // (DITHER_EN=1 and IPEAK=4). - (uint32_t)0xFCFC08C3, + // DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0x3 (DITHER_EN=0 and IPEAK=3). + (uint32_t)0x00F388D3, // Rx: Set LNA bias current offset to +15 to saturate trim to max (default: 0) - (uint32_t)0x000F8883, - // override_frontend_id.xml - (uint32_t)0xFFFFFFFF, -}; + (uint32_t)0x000F8883, (uint32_t)0xFFFFFFFF}; /* * Number of retry counts left to the currently transmitting frame. @@ -918,13 +888,11 @@ static void rfCorePowerOff(void) } /** - * Applies CPE, RFE, and MCE patches to the radio. + * Applies CPE patche to the radio. */ static void rfCoreApplyPatch(void) { rf_patch_cpe_ieee_802_15_4(); - rf_patch_mce_ieee_802_15_4(); - rf_patch_rfe_ieee_802_15_4(); /* disable ram bus clocks */ RFCDoorbellSendTo(CMDR_DIR_CMD_2BYTE(CC2652_RF_CMD0, 0)); @@ -1415,6 +1383,7 @@ otError otPlatRadioSleep(otInstance *aInstance) else { sState = cc2652_stateSleep; + error = OT_ERROR_NONE; } } diff --git a/third_party/ti/README.md b/third_party/ti/README.md index 461935802..a5ad0a0ee 100644 --- a/third_party/ti/README.md +++ b/third_party/ti/README.md @@ -1,11 +1,10 @@ #CC26XXware ## URL - -http://www.ti.com/tool/simplelink-cc26x2-sdk +http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk ## Version -`driverlib_cc13xx_cc26xx_3_30_03_00` +`driverlib_cc13xx_cc26xx_3_05_06_18894` ## License @@ -18,7 +17,7 @@ BSD-3-Clause ## Documentation This version of cc26xxware is copied from the [SimpleLink CC26x2 Software -Development Kit](http://www.ti.com/tool/simplelink-cc26x2-sdk). Modifications +Development Kit](http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk). Modifications were made to the software package to support the GCC Automake pedantic build. Also see: release_notes_driverlib_cc13xx_cc26xx.html @@ -31,9 +30,7 @@ Also see: release_notes_driverlib_cc13xx_cc26xx.html | `device/cc13x52_cc26x2/linker_files/cc26x2r1f.lds` | `end` symbol added for GCC stdlib | Documentation can be found within the [SimpleLink CC26x2 Software Development -Kit](http://www.ti.com/tool/simplelink-cc26x2-sdk). - -**TODO** Update above link +Kit](http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk). ## Description diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/aes.c b/third_party/ti/devices/cc13x2_cc26x2/driverlib/aes.c index 43c030c92..c480bf7c6 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/aes.c +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/aes.c @@ -1,7 +1,8 @@ + /****************************************************************************** * Filename: crypto.c -* Revised: 2018-05-08 10:29:36 +0200 (Tue, 08 May 2018) -* Revision: 51973 +* Revised: 2019-01-25 13:11:50 +0100 (Fri, 25 Jan 2019) +* Revision: 54285 * * Description: Driver for the aes functions of the crypto module * diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/aes.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/aes.h index 636337895..f1ac452f5 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/aes.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/aes.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: aes.h -* Revised: 2018-04-17 14:54:06 +0200 (Tue, 17 Apr 2018) -* Revision: 51890 +* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) +* Revision: 54287 * * Description: AES header file. * @@ -583,6 +583,19 @@ __STATIC_INLINE void AESSetAuthLength(uint32_t length) HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = length; } +//***************************************************************************** +// +//! \brief Reset the accelerator and cancel ongoing operations +//! +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESReset(void) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = 0x00000001; +} + //***************************************************************************** // //! \brief Enable individual crypto interrupt sources. diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/ccs/driverlib.lib b/third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/ccs/driverlib.lib index 0f663e6ce4978c8e81210bad8153175354c20abc..004e8f7fd0c31c766904f5892d9f6aafa2a528dc 100644 GIT binary patch delta 400705 zcmce<3tSb|`aV8u_RPK@oBLHRf}o-zZth^3;05uPsA!g!AZ&wDM8wjL26olb(suf4 zY3b>vr5%-OTWMk0$?j<7vC_h_lO63GEh|jT-}BDQh7DoAe&7H1{P%~MXRY^n*Zsa` zX7R)$&U-(oSeaXwmYI_g$G;LENs?`nH07V|ulxNZ>3?{M+|Q)nT?@k`(RS5&TXgfG zK9cZUzYLLtamf+aOPyZR{3Q8*eAVfWP1dWV)~ol8lBwf0cd}&a?0Pv?GI_4g2S}zr zc`4T&lC-PNW9SSYyG>I57cP~8q|04(t;D4&N%gwSNe89YtKfRc?742Jk<9-~mu2Xy zbrNp+Ren&i{L!`d3(4|7xU5rNl`enP{Sm2iHs9N&|Jqe&c<$qOv-H1tb@AIN{h6!o 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-mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -Wall -fno-strict-aliasing -gstrict-dwarf -pedantic -ffunction-sections -fdata-sections -std=c99 -c --asm -g -o "pwr_ctrl.o" $(MAKEFILE_DIR)../../../driverlib/pwr_ctrl.c @ echo GCC: Compile rfc.c @ $(COMPILER_TOOL) -mthumb -march=armv7e-m -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -Wall -fno-strict-aliasing -gstrict-dwarf -pedantic -ffunction-sections -fdata-sections -std=c99 -c --asm -g -o "rfc.o" $(MAKEFILE_DIR)../../../driverlib/rfc.c + @ echo GCC: Compile rom_crypto.c + @ $(COMPILER_TOOL) -mthumb -march=armv7e-m -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -Wall -fno-strict-aliasing -gstrict-dwarf -pedantic -ffunction-sections -fdata-sections -std=c99 -c --asm -g -o "rom_crypto.o" $(MAKEFILE_DIR)../../../driverlib/rom_crypto.c @ echo GCC: Compile setup.c @ $(COMPILER_TOOL) -mthumb -march=armv7e-m -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -Wall -fno-strict-aliasing -gstrict-dwarf -pedantic -ffunction-sections -fdata-sections -std=c99 -c --asm -g -o "setup.o" $(MAKEFILE_DIR)../../../driverlib/setup.c @ echo GCC: Compile setup_rom.c @@ -104,7 +106,7 @@ all : @ echo GCC: Compile watchdog.c @ $(COMPILER_TOOL) -mthumb -march=armv7e-m -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -Wall -fno-strict-aliasing -gstrict-dwarf -pedantic -ffunction-sections -fdata-sections -std=c99 -c --asm -g -o "watchdog.o" $(MAKEFILE_DIR)../../../driverlib/watchdog.c @ echo GCC: Archive driverlib.lib - @ $(ARCHIVER_TOOL) rcs $(MAKEFILE_DIR)driverlib.lib $(MAKEFILE_DIR)adi.o $(MAKEFILE_DIR)aes.o $(MAKEFILE_DIR)aon_batmon.o $(MAKEFILE_DIR)aon_event.o $(MAKEFILE_DIR)aon_ioc.o $(MAKEFILE_DIR)aon_pmctl.o $(MAKEFILE_DIR)aon_rtc.o $(MAKEFILE_DIR)aux_adc.o $(MAKEFILE_DIR)aux_smph.o $(MAKEFILE_DIR)aux_sysif.o $(MAKEFILE_DIR)aux_tdc.o $(MAKEFILE_DIR)ccfgread.o $(MAKEFILE_DIR)chipinfo.o $(MAKEFILE_DIR)cpu.o $(MAKEFILE_DIR)crypto.o $(MAKEFILE_DIR)ddi.o $(MAKEFILE_DIR)debug.o $(MAKEFILE_DIR)driverlib_release.o $(MAKEFILE_DIR)event.o $(MAKEFILE_DIR)flash.o $(MAKEFILE_DIR)gpio.o $(MAKEFILE_DIR)i2c.o $(MAKEFILE_DIR)i2s.o $(MAKEFILE_DIR)interrupt.o $(MAKEFILE_DIR)ioc.o $(MAKEFILE_DIR)osc.o $(MAKEFILE_DIR)pka.o $(MAKEFILE_DIR)prcm.o $(MAKEFILE_DIR)pwr_ctrl.o $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup_rom.o $(MAKEFILE_DIR)sha2.o $(MAKEFILE_DIR)smph.o $(MAKEFILE_DIR)ssi.o $(MAKEFILE_DIR)sw_chacha.o $(MAKEFILE_DIR)sw_poly1305-donna.o $(MAKEFILE_DIR)systick.o $(MAKEFILE_DIR)sys_ctrl.o $(MAKEFILE_DIR)timer.o $(MAKEFILE_DIR)trng.o $(MAKEFILE_DIR)uart.o $(MAKEFILE_DIR)udma.o $(MAKEFILE_DIR)vims.o $(MAKEFILE_DIR)watchdog.o + @ $(ARCHIVER_TOOL) rcs $(MAKEFILE_DIR)driverlib.lib $(MAKEFILE_DIR)adi.o $(MAKEFILE_DIR)aes.o $(MAKEFILE_DIR)aon_batmon.o $(MAKEFILE_DIR)aon_event.o $(MAKEFILE_DIR)aon_ioc.o $(MAKEFILE_DIR)aon_pmctl.o $(MAKEFILE_DIR)aon_rtc.o $(MAKEFILE_DIR)aux_adc.o $(MAKEFILE_DIR)aux_smph.o $(MAKEFILE_DIR)aux_sysif.o $(MAKEFILE_DIR)aux_tdc.o $(MAKEFILE_DIR)ccfgread.o $(MAKEFILE_DIR)chipinfo.o $(MAKEFILE_DIR)cpu.o $(MAKEFILE_DIR)crypto.o $(MAKEFILE_DIR)ddi.o $(MAKEFILE_DIR)debug.o $(MAKEFILE_DIR)driverlib_release.o $(MAKEFILE_DIR)event.o $(MAKEFILE_DIR)flash.o $(MAKEFILE_DIR)gpio.o $(MAKEFILE_DIR)i2c.o $(MAKEFILE_DIR)i2s.o $(MAKEFILE_DIR)interrupt.o $(MAKEFILE_DIR)ioc.o $(MAKEFILE_DIR)osc.o $(MAKEFILE_DIR)pka.o $(MAKEFILE_DIR)prcm.o $(MAKEFILE_DIR)pwr_ctrl.o $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)rom_crypto.o $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup_rom.o $(MAKEFILE_DIR)sha2.o $(MAKEFILE_DIR)smph.o $(MAKEFILE_DIR)ssi.o $(MAKEFILE_DIR)sw_chacha.o $(MAKEFILE_DIR)sw_poly1305-donna.o $(MAKEFILE_DIR)systick.o $(MAKEFILE_DIR)sys_ctrl.o $(MAKEFILE_DIR)timer.o $(MAKEFILE_DIR)trng.o $(MAKEFILE_DIR)uart.o $(MAKEFILE_DIR)udma.o $(MAKEFILE_DIR)vims.o $(MAKEFILE_DIR)watchdog.o @ rm -f $(MAKEFILE_DIR)*.o # Deletes previous output and temporary files diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/iar/driverlib.lib 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a/third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/iar/makefile b/third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/iar/makefile index f8e350027..0073e34fa 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/iar/makefile +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/iar/makefile @@ -108,6 +108,9 @@ all : @ echo IAR: Compile rfc.c @ $(COMPILER_TOOL) $(MAKEFILE_DIR)../../../driverlib/rfc.c -D nDEBUG $(ADD_PARAM) -o $(MAKEFILE_DIR)rfc.o --no_clustering --debug --endian=little --cpu=Cortex-M4 -e --fpu=FPv4_sp -Ohz --require_prototypes --silent @ $(OBJ_MANIP_TOOL) --remove_file_path --remove_section ".comment" --silent $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)rfc.o + @ echo IAR: Compile rom_crypto.c + @ $(COMPILER_TOOL) $(MAKEFILE_DIR)../../../driverlib/rom_crypto.c -D nDEBUG $(ADD_PARAM) -o $(MAKEFILE_DIR)rom_crypto.o --no_clustering --debug --endian=little --cpu=Cortex-M4 -e --fpu=FPv4_sp -Ohz --require_prototypes --silent + @ $(OBJ_MANIP_TOOL) --remove_file_path --remove_section ".comment" --silent $(MAKEFILE_DIR)rom_crypto.o $(MAKEFILE_DIR)rom_crypto.o @ echo IAR: Compile setup.c @ $(COMPILER_TOOL) $(MAKEFILE_DIR)../../../driverlib/setup.c -D nDEBUG $(ADD_PARAM) -o $(MAKEFILE_DIR)setup.o --no_clustering --debug --endian=little --cpu=Cortex-M4 -e --fpu=FPv4_sp -Ohz --require_prototypes --silent @ $(OBJ_MANIP_TOOL) --remove_file_path --remove_section ".comment" --silent $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup.o @@ -154,7 +157,7 @@ all : @ $(COMPILER_TOOL) $(MAKEFILE_DIR)../../../driverlib/watchdog.c -D nDEBUG $(ADD_PARAM) -o $(MAKEFILE_DIR)watchdog.o --no_clustering --debug --endian=little --cpu=Cortex-M4 -e --fpu=FPv4_sp -Ohz --require_prototypes --silent @ $(OBJ_MANIP_TOOL) --remove_file_path --remove_section ".comment" --silent $(MAKEFILE_DIR)watchdog.o $(MAKEFILE_DIR)watchdog.o @ echo IAR: Archive driverlib.lib - @ $(ARCHIVER_TOOL) $(MAKEFILE_DIR)adi.o $(MAKEFILE_DIR)aes.o $(MAKEFILE_DIR)aon_batmon.o $(MAKEFILE_DIR)aon_event.o $(MAKEFILE_DIR)aon_ioc.o $(MAKEFILE_DIR)aon_pmctl.o $(MAKEFILE_DIR)aon_rtc.o $(MAKEFILE_DIR)aux_adc.o $(MAKEFILE_DIR)aux_smph.o $(MAKEFILE_DIR)aux_sysif.o $(MAKEFILE_DIR)aux_tdc.o $(MAKEFILE_DIR)ccfgread.o $(MAKEFILE_DIR)chipinfo.o $(MAKEFILE_DIR)cpu.o $(MAKEFILE_DIR)crypto.o $(MAKEFILE_DIR)ddi.o $(MAKEFILE_DIR)debug.o $(MAKEFILE_DIR)driverlib_release.o $(MAKEFILE_DIR)event.o $(MAKEFILE_DIR)flash.o $(MAKEFILE_DIR)gpio.o $(MAKEFILE_DIR)i2c.o $(MAKEFILE_DIR)i2s.o $(MAKEFILE_DIR)interrupt.o $(MAKEFILE_DIR)ioc.o $(MAKEFILE_DIR)osc.o $(MAKEFILE_DIR)pka.o $(MAKEFILE_DIR)prcm.o $(MAKEFILE_DIR)pwr_ctrl.o $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup_rom.o $(MAKEFILE_DIR)sha2.o $(MAKEFILE_DIR)smph.o $(MAKEFILE_DIR)ssi.o $(MAKEFILE_DIR)sw_chacha.o $(MAKEFILE_DIR)sw_poly1305-donna.o $(MAKEFILE_DIR)systick.o $(MAKEFILE_DIR)sys_ctrl.o $(MAKEFILE_DIR)timer.o $(MAKEFILE_DIR)trng.o $(MAKEFILE_DIR)uart.o $(MAKEFILE_DIR)udma.o $(MAKEFILE_DIR)vims.o $(MAKEFILE_DIR)watchdog.o --create -o $(MAKEFILE_DIR)driverlib.lib + @ $(ARCHIVER_TOOL) $(MAKEFILE_DIR)adi.o $(MAKEFILE_DIR)aes.o $(MAKEFILE_DIR)aon_batmon.o $(MAKEFILE_DIR)aon_event.o $(MAKEFILE_DIR)aon_ioc.o $(MAKEFILE_DIR)aon_pmctl.o $(MAKEFILE_DIR)aon_rtc.o $(MAKEFILE_DIR)aux_adc.o $(MAKEFILE_DIR)aux_smph.o $(MAKEFILE_DIR)aux_sysif.o $(MAKEFILE_DIR)aux_tdc.o $(MAKEFILE_DIR)ccfgread.o $(MAKEFILE_DIR)chipinfo.o $(MAKEFILE_DIR)cpu.o $(MAKEFILE_DIR)crypto.o $(MAKEFILE_DIR)ddi.o $(MAKEFILE_DIR)debug.o $(MAKEFILE_DIR)driverlib_release.o $(MAKEFILE_DIR)event.o $(MAKEFILE_DIR)flash.o $(MAKEFILE_DIR)gpio.o $(MAKEFILE_DIR)i2c.o $(MAKEFILE_DIR)i2s.o $(MAKEFILE_DIR)interrupt.o $(MAKEFILE_DIR)ioc.o $(MAKEFILE_DIR)osc.o $(MAKEFILE_DIR)pka.o $(MAKEFILE_DIR)prcm.o $(MAKEFILE_DIR)pwr_ctrl.o $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)rom_crypto.o $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup_rom.o $(MAKEFILE_DIR)sha2.o $(MAKEFILE_DIR)smph.o $(MAKEFILE_DIR)ssi.o $(MAKEFILE_DIR)sw_chacha.o $(MAKEFILE_DIR)sw_poly1305-donna.o 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Bits 0 and 5-7 will //! not be affected by the operation, as long as the corresponding bits are //! not set in the \c ui16Mask. //! -//! \note Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! //! \param ui32Base is the base address of the DDI port. //! \param ui32Reg is the Least Significant Register in the DDI slave that //! will be affected by the write operation. @@ -300,14 +288,11 @@ DDI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Byte, //! This function allows 16 bit masked access to the DDI slave registers. //! //! Use this function to write any value in the range 0-15 bits aligned on a -//! half-word boundary. Fx. for writing the value 0b101 to bits 1-3 set +//! half-word boundary. For example, for writing the value 0b101 to bits 1-3 set //! ui32Val = 0x000A and ui32Mask = 0x000E. Bits 0 and 5-15 will not be //! affected by the operation, as long as the corresponding bits are not set //! in the \c ui32Mask. //! -//! \note Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! //! \param ui32Base is the base address of the DDI port. //! \param ui32Reg is register to access. //! \param bWriteHigh defines which part of the register to write in. @@ -350,9 +335,6 @@ DDI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, //! conservation of the previous value of the register will be kept (i.e. this //! is NOT read-modify-write on the register). //! -//! \note Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! //! \param ui32Base is DDI base address. //! \param ui32Reg is the register to write. //! \param ui32Val is the 32 bit value to write to the register. @@ -368,15 +350,10 @@ extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) //! //! A '1' is written to the bit if \c ui32WrData is non-zero, else a '0' is written. //! -//! \note Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! //! \param ui32Base is the base address of the DDI port. //! \param ui32Reg is register to access. -//! \param ui32Mask is the mask defining which of the 16 bit that should be -//! overwritten. The mask must be defined in the lower half of the 32 bits. -//! \param ui32WrData is the value to write. The value must be defined in the lower -//! half of the 32 bits. +//! \param ui32Mask is the mask defining which of the 16 bit that should be overwritten. +//! \param ui32WrData is the value to write. The value must be defined in the lower half of the 32 bits. //! //! \return None // @@ -389,17 +366,13 @@ extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, // //! \brief Write a bit field via the DDI using 16-bit maskable write. //! -//! Requires that bitfields not space the low/high word boundary. -//! -//! \note Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. +//! Requires that entire bit field is within the half word boundary. //! //! \param ui32Base is the base address of the DDI port. //! \param ui32Reg is register to access. -//! \param ui32Mask is the mask defining which of the 16 bits that should be -//! overwritten. The mask must be defined in the lower half of the 32 bits. -//! \param ui32Shift -//! \param ui32Data +//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. +//! \param ui32Shift is the shift value for the bit field. +//! \param ui32Data is the data aligned to bit 0. //! //! \return None // @@ -412,9 +385,6 @@ extern void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, // //! \brief Read a bit via the DDI using 16-bit read. //! -//! \note Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! //! \param ui32Base is the base address of the DDI module. //! \param ui32Reg is the register to read. //! \param ui32Mask defines the bit which should be read. @@ -427,17 +397,13 @@ extern uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, //***************************************************************************** // -//! \brief Read a bitfield via the DDI using 16-bit read. +//! \brief Read a bit field via the DDI using 16-bit read. //! -//! Requires that bit fields do not space the low/high word boundary. -//! -//! \note Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. +//! Requires that entire bit field is within the half word boundary. //! //! \param ui32Base is the base address of the DDI port. //! \param ui32Reg is register to access. -//! \param ui32Mask is the mask defining which of the 16 bits that should be -//! overwritten. The mask must be defined in the lower half of the 32 bits. +//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. //! \param ui32Shift defines the required shift of the data to align with bit 0. //! //! \return Returns data aligned to bit 0. diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c b/third_party/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c index 00b054730..cdb08e35d 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c @@ -42,4 +42,4 @@ /// Declare the current DriverLib release -DRIVERLIB_DECLARE_RELEASE(0, 51995); +DRIVERLIB_DECLARE_RELEASE(0, 54539); diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h index 5d52f7e6c..497f8b0f9 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h @@ -63,7 +63,7 @@ extern "C" /// DriverLib release group number #define DRIVERLIB_RELEASE_GROUP 0 /// DriverLib release build number -#define DRIVERLIB_RELEASE_BUILD 51995 +#define DRIVERLIB_RELEASE_BUILD 54539 @@ -83,7 +83,7 @@ extern "C" const volatile uint8_t driverlib_release_##group##_##build /// External declaration of the DriverLib release locking object -extern DRIVERLIB_DECLARE_RELEASE(0, 51995); +extern DRIVERLIB_DECLARE_RELEASE(0, 54539); @@ -135,7 +135,7 @@ extern DRIVERLIB_DECLARE_RELEASE(0, 51995); // //***************************************************************************** #define DRIVERLIB_ASSERT_CURR_RELEASE() \ - DRIVERLIB_ASSERT_RELEASE(0, 51995) + DRIVERLIB_ASSERT_RELEASE(0, 54539) diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/i2s.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/i2s.h index 0ef2441c6..62c2c5ef3 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/i2s.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/i2s.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: i2s.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 +* Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) +* Revision: 53356 * * Description: Defines and prototypes for the I2S. * @@ -97,6 +97,8 @@ extern "C" //! \brief A structure that defines an audio control table. Note: Memory for this //! structure \b must be initialized by user application. See detailed description! //! +//! \deprecated This structure will be removed in a future release. +//! //! These fields are used by the I2S and normally it is not necessary for //! software to directly read or write fields in the table. //! @@ -113,6 +115,7 @@ extern "C" //! // //***************************************************************************** +#ifndef DEPRECATED typedef struct { uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. @@ -125,6 +128,7 @@ typedef struct uint32_t ui32OutBase; //!< Base address of the output buffer. uint32_t ui32OutOffset; //!< Value of the current output pointer offset. } I2SControlTable; +#endif //***************************************************************************** // @@ -137,42 +141,51 @@ typedef struct // g_pControlTable = &g_controlTable; // //***************************************************************************** +#ifndef DEPRECATED extern I2SControlTable *g_pControlTable; +#endif //***************************************************************************** // // Defines for the I2S DMA buffer sizes // //***************************************************************************** +#ifndef DEPRECATED #define I2S_DMA_BUF_SIZE_64 0x00000040 #define I2S_DMA_BUF_SIZE_128 0x00000080 #define I2S_DMA_BUF_SIZE_256 0x00000100 +#endif //***************************************************************************** // // Defines for the I2S audio clock configuration // //***************************************************************************** +#ifndef DEPRECATED #define I2S_EXT_WCLK 0x00000001 #define I2S_INT_WCLK 0x00000002 #define I2S_INVERT_WCLK 0x00000004 #define I2S_NORMAL_WCLK 0x00000000 +#endif //***************************************************************************** // // Defines for the audio data line input/output configuration // //***************************************************************************** +#ifndef DEPRECATED #define I2S_LINE_UNUSED 0x00000000 #define I2S_LINE_INPUT 0x00000001 #define I2S_LINE_OUTPUT 0x00000002 #define I2S_LINE_MASK 0x00000003 +#endif //***************************************************************************** // // Defines for activating an audio channel. // //***************************************************************************** +#ifndef DEPRECATED #define I2S_CHAN0_ACT 0x00000100 #define I2S_CHAN1_ACT 0x00000200 #define I2S_CHAN2_ACT 0x00000400 @@ -184,6 +197,16 @@ extern I2SControlTable *g_pControlTable; #define I2S_MONO_MODE 0x00000100 #define I2S_STEREO_MODE 0x00000300 #define I2S_CHAN_CFG_MASK 0x0000FF00 +#endif + +#define I2S_CHAN0_MASK 0x00000001 +#define I2S_CHAN1_MASK 0x00000002 +#define I2S_CHAN2_MASK 0x00000004 +#define I2S_CHAN3_MASK 0x00000008 +#define I2S_CHAN4_MASK 0x00000010 +#define I2S_CHAN5_MASK 0x00000020 +#define I2S_CHAN6_MASK 0x00000040 +#define I2S_CHAN7_MASK 0x00000080 //***************************************************************************** // @@ -205,8 +228,10 @@ extern I2SControlTable *g_pControlTable; // Defines for the sample stamp counters // //***************************************************************************** +#ifndef DEPRECATED #define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 #define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 +#endif #define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when // calculating the sample stamp @@ -255,6 +280,8 @@ I2SBaseValid(uint32_t ui32Base) // //! \brief Enables the I2S module for operation. //! +//! \deprecated This function will be removed in a future release. +//! //! \note The module should only be enabled after configuration. When the //! module is disabled, no data or clocks will be generated on the I2S signals. //! @@ -268,12 +295,16 @@ I2SBaseValid(uint32_t ui32Base) //! \return None // //***************************************************************************** +#ifndef DEPRECATED extern void I2SEnable(uint32_t ui32Base); +#endif //***************************************************************************** // //! \brief Disables the I2S module for operation. //! +//! \deprecated This function will be removed in a future release. +//! //! This function will immediately disable the I2S module. To ensure that //! all buffer operations are completed before shutting down, the correct //! procedure is: @@ -288,6 +319,7 @@ extern void I2SEnable(uint32_t ui32Base); //! \return None // //***************************************************************************** +#ifndef DEPRECATED __STATIC_INLINE void I2SDisable(uint32_t ui32Base) { @@ -297,11 +329,14 @@ I2SDisable(uint32_t ui32Base) // Disable the I2S module. HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x0; } +#endif //***************************************************************************** // //! \brief Configures the I2S module. //! +//! \deprecated This function will be removed in a future release. +//! //! The word length defines the size of the word transmitted on the data //! lines. For single phased formats \c I2S_WORD_LENGTH_x is the exact number //! of bits per word. In dual phased format this is the maximum number of bits @@ -337,13 +372,17 @@ I2SDisable(uint32_t ui32Base) //! \sa \ref I2SChannelConfigure() // //***************************************************************************** +#ifndef DEPRECATED extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, uint32_t ui32BitClkDelay); +#endif //**************************************************************************** // //! \brief Setup the audio channel configuration. //! +//! \deprecated This function will be removed in a future release. +//! //! The channel configuration is a bitwise OR of the input/output mode of each //! data line and the active audio channels within a specific audio frame. //! @@ -380,13 +419,17 @@ extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, //! \sa \ref I2SAudioFormatConfigure() // //**************************************************************************** +#ifndef DEPRECATED extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, uint32_t ui32Chan1Cfg); +#endif //**************************************************************************** // //! \brief Configure the I2S frame clock. //! +//! \deprecated This function will be removed in a future release. +//! //! Configure I2S clock to be either internal or external and either normal //! or inverted. //! @@ -407,6 +450,7 @@ extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, //! \return None // //**************************************************************************** +#ifndef DEPRECATED __STATIC_INLINE void I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig) { @@ -418,11 +462,14 @@ I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig) (I2S_AIFWCLKSRC_WCLK_INV_M | I2S_AIFWCLKSRC_WCLK_SRC_M); } +#endif //**************************************************************************** // //! \brief Set the input buffer pointers. //! +//! \deprecated This function will be removed in a future release. +//! //! The next pointer should always be written while the DMA is using the //! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will //! occur and all outputs will be disabled. @@ -439,14 +486,18 @@ I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig) //! \return None // //**************************************************************************** +#ifndef DEPRECATED extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, uint16_t ui16ChanBufSize); +#endif //**************************************************************************** // //! \brief Update the buffer pointers. //! +//! \deprecated This function will be removed in a future release. +//! //! The next pointer should always be written while the DMA is using the //! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur //! and all outputs will be disabled. Nothing is preventing the pointers from @@ -466,12 +517,16 @@ extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, //! \sa \ref I2SPointerSet() // //**************************************************************************** +#ifndef DEPRECATED extern void I2SPointerUpdate(uint32_t ui32Base, bool bInput); +#endif //**************************************************************************** // //! \brief Set a buffer pointer (input or output) directly. //! +//! \deprecated This function will be removed in a future release. +//! //! This function allows bypassing of the pointers in the global control table. //! //! The next pointer should always be written while the DMA is using the @@ -494,12 +549,16 @@ extern void I2SPointerUpdate(uint32_t ui32Base, bool bInput); //! \sa \ref I2SPointerUpdate() // //**************************************************************************** +#ifndef DEPRECATED extern void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer); +#endif //***************************************************************************** // //! \brief Registers an interrupt handler for an I2S interrupt in the dynamic interrupt table. //! +//! \deprecated This function will be removed in a future release. +//! //! \note Only use this function if you want to use the dynamic vector table (in SRAM)! //! //! This function registers a function as the interrupt handler for a specific @@ -518,6 +577,7 @@ extern void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer); //! handlers. // //***************************************************************************** +#ifndef DEPRECATED __STATIC_INLINE void I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) { @@ -530,11 +590,14 @@ I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) // Enable the I2S interrupt. IntEnable(INT_I2S_IRQ); } +#endif //***************************************************************************** // //! \brief Unregisters an interrupt handler for a I2S interrupt in the dynamic interrupt table. //! +//! \deprecated This function will be removed in a future release. +//! //! This function does the actual unregistering of the interrupt handler. It //! clears the handler to be called when an I2S interrupt occurs. This //! function also masks off the interrupt in the interrupt controller so that @@ -548,6 +611,7 @@ I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) //! handlers. // //***************************************************************************** +#ifndef DEPRECATED __STATIC_INLINE void I2SIntUnregister(uint32_t ui32Base) { @@ -560,6 +624,27 @@ I2SIntUnregister(uint32_t ui32Base) // Unregister the interrupt handler. IntUnregister(INT_I2S_IRQ); } +#endif + +//***************************************************************************** +// +//! \brief Configure the sample stamp generator. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput enables triggering of the sample stamp generator on input. +//! \param bOutput enables triggering of the sample stamp generator on output. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, + bool bOutput); +#endif //***************************************************************************** // @@ -732,6 +817,9 @@ I2SIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) __STATIC_INLINE void I2SSampleStampEnable(uint32_t ui32Base) { + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + // Set the enable bit. HWREG(I2S0_BASE + I2S_O_STMPCTL) = I2S_STMPCTL_STMP_EN; } @@ -749,27 +837,14 @@ I2SSampleStampEnable(uint32_t ui32Base) __STATIC_INLINE void I2SSampleStampDisable(uint32_t ui32Base) { + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + // Clear the enable bit. HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0; } -//***************************************************************************** -// -//! \brief Configure the sample stamp generator. -//! -//! Use this function to configure the sample stamp generator. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param bInput enables triggering of the sample stamp generator on input. -//! \param bOutput enables triggering of the sample stamp generator on output. -//! -//! \return None -// -//***************************************************************************** -extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, - bool bOutput); - //***************************************************************************** // //! \brief Get the current value of a sample stamp counter. @@ -782,6 +857,446 @@ extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, //***************************************************************************** extern uint32_t I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel); +//***************************************************************************** +// +//! \brief Starts the I2S. +//! +//! I2S must be configured before it is started. +//! +//! \note Immediately after enabling the module the programmer must update +//! the DMA data pointer registers using \ref I2SInPointerSet() and +//! \ref I2SOutPointerSet() to ensure a new pointer is written before the DMA +//! transfer completes. Failure to update the pointer in time will result in +//! an \ref I2S_INT_PTR_ERR. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui8FixDMALength is the length of the DMA buffer: this will allow +//! the DMA to read ui8FixDMALength between to pointer refreshes. +//! +//! \return None +//! +//! \sa \ref I2SStop() +// +//***************************************************************************** +__STATIC_INLINE void I2SStart(uint32_t ui32Base, uint8_t ui8FixDMALength) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Enable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = ui8FixDMALength; +} + +//***************************************************************************** +// +//! \brief Stops the I2S module for operation. +//! +//! This function will immediately disable the I2S module. To ensure that +//! all buffer operations are completed before shutting down, the correct +//! procedure is: +//! 1. Do not update the data pointers using \ref I2SInPointerSet() and +//! \ref I2SOutPointerSet(). +//! 2. Await that values returned by \ref I2SInPointerNextGet(), +//! \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and \ref I2SOutPointerGet() +//! are zero. +//! 3. Disable the I2S using \ref I2SStop() and clear the pointer +//! error using \ref I2SIntClear(). +//! 4. Disable bit clock source (done externally). +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +//! +//! \sa \ref I2SStart() +// +//***************************************************************************** +__STATIC_INLINE void I2SStop(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x00; +} + +//***************************************************************************** +// +//! \brief Configure the serial format of the I2S module. +//! +//! The word length defines the size of the word transmitted on the data +//! lines. For single phased formats \c ui8BitsPerSample is the exact number +//! of bits per word. In dual phased format this is the maximum number of bits +//! per word. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui8iDataDelay is the number of BCLK periods between the first WCLK +//! edge and the MSB of the first audio channel data transferred during +//! the phase. +//! \param ui8iMemory24Bits selects if the samples in memory are coded on 16 bits +//! or 24 bits. Possible values are: +//! - \ref I2S_MEM_LENGTH_16 +//! - \ref I2S_MEM_LENGTH_24 +//! \param ui8iSamplingEdge selects if sampling on falling or rising edges. +//! Possible values are: +//! - \ref I2S_NEG_EDGE +//! - \ref I2S_POS_EDGE +//! \param boolDualPhase must be set to true for dual phase and to false for +//! single phase and user-defined phase. +//! \param ui8BitsPerSample is the number of bits transmitted for each sample. +//! If this number does not match with the memory length selected +//! (16 bits or24 bits), samples will be truncated or padded. +//! \param ui16transmissionDelay is the number of WCLK periods before the first +//! transmission. +//! +//! \return None +//! +//! \sa \ref I2SFrameConfigure() +// +//***************************************************************************** +__STATIC_INLINE void +I2SFormatConfigure(uint32_t ui32Base, + uint8_t ui8iDataDelay, + uint8_t ui8iMemory24Bits, + uint8_t ui8iSamplingEdge, + bool boolDualPhase, + uint8_t ui8BitsPerSample, + uint16_t ui16transmissionDelay) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui8BitsPerSample <= I2S_AIFFMTCFG_WORD_LEN_MAX); + ASSERT(ui8BitsPerSample >= I2S_AIFFMTCFG_WORD_LEN_MIN); + + // Setup register AIFFMTCFG Source. + HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) = + (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | + (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | + (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S ) | + (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | + (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S ); + + // Number of WCLK periods before the first read / write + HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay; +} + +//**************************************************************************** +// +//! \brief Setup the two interfaces SD0 and SD1 (also called AD0 and AD1). +//! +//! This function sets interface's direction and activated channels. +//! +//! \param ui32Base is base address of the I2S module. +//! \param ui8StatusAD0 defines the usage of AD0 +//! 0x00: AD0 is disabled +//! 0x01, AD0 is an input +//! 0x02, AD0 is an output +//! \param ui8ChanAD0 defines the channel mask for AD0. +//! Use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_MASK +//! - \ref I2S_CHAN1_MASK +//! - \ref I2S_CHAN2_MASK +//! - \ref I2S_CHAN3_MASK +//! - \ref I2S_CHAN4_MASK +//! - \ref I2S_CHAN5_MASK +//! - \ref I2S_CHAN6_MASK +//! - \ref I2S_CHAN7_MASK +//! \param ui8StatusAD1 defines the usage of AD1 +//! 0x00: AD1 is disabled +//! 0x10, AD1 is an input +//! 0x20, AD1 is an output +//! \param ui8ChanAD1 defines the channel mask for AD1. +//! Use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_MASK +//! - \ref I2S_CHAN1_MASK +//! - \ref I2S_CHAN2_MASK +//! - \ref I2S_CHAN3_MASK +//! - \ref I2S_CHAN4_MASK +//! - \ref I2S_CHAN5_MASK +//! - \ref I2S_CHAN6_MASK +//! - \ref I2S_CHAN7_MASK +//! +//! \return None +//! +//! \sa \ref I2SFormatConfigure() +// +//**************************************************************************** +__STATIC_INLINE void +I2SFrameConfigure(uint32_t ui32Base, + uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, + uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Configure input/output channels. + HWREGB(I2S0_BASE + I2S_O_AIFDIRCFG) = (ui8StatusAD0 | ui8StatusAD1); + + // Configure the valid channel mask. + HWREGB(I2S0_BASE + I2S_O_AIFWMASK0) = ui8ChanAD0; + HWREGB(I2S0_BASE + I2S_O_AIFWMASK1) = ui8ChanAD1; +} + +//**************************************************************************** +// +//! \brief Configure the I2S frame clock (also called WCLK or WS). +//! +//! Configure WCLK clock to be either internal (master) or external (slave). +//! Configure WCLK clock either normal or inverted. +//! +//! \note The bit clock configuration is done externally, but the internal/ +//! external setting must match what is chosen internally in the I2S module +//! for the frame clock. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param boolMaster false: the device is a slave (external clock) +//! true: the device is a master (internal clock) +//! \param boolWCLKInvert false: WCLK is not inverted +//! true: WCLK is internally inverted +//! +//! \return None +// +//**************************************************************************** +__STATIC_INLINE void +I2SWclkConfigure(uint32_t ui32Base, + bool boolMaster, + bool boolWCLKInvert) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui8ClkSource < I2S_AIFWCLKSRC_WCLK_SRC_RESERVED); + + // if(boolMaster == 0) then ui8ClkSource = 1 + // if(boolMaster == 1) then ui8ClkSource = 2 + uint8_t ui8ClkSource = (uint8_t)boolMaster + 0x01; + + // Setup register WCLK Source. + HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) = + ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | + (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S )); +} + +//**************************************************************************** +// +//! \brief Set the input buffer pointer. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR +//! will occur and all inputs and outputs will be disabled. +//! This function relies on pointer is pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32NextPointer is the adress of the data +//! +//! \return None +//! +//! \sa \ref I2SOutPointerSet() +// +//**************************************************************************** +__STATIC_INLINE void +I2SInPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = ui32NextPointer; +} + +//**************************************************************************** +// +//! \brief Set the output buffer pointer. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR +//! will occur and all inputs and outputs will be disabled. +//! This function relies on pointer is pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32NextPointer is the adress of the data +//! +//! \return None +//! +//! \sa \ref I2SInPointerSet() +// +//**************************************************************************** +__STATIC_INLINE void +I2SOutPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = ui32NextPointer; +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR NEXT IN register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR NEXT IN. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SInPointerNextGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT)); +} + + +//**************************************************************************** +// +//! \brief Get value stored in PTR NEXT OUT register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR NEXT OUT. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SOutPointerNextGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT)); +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR IN register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR IN. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SInPointerGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFINPTR)); +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR OUT register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR OUT. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SOutPointerGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTR)); +} + +//***************************************************************************** +// +//! \brief Configure the IN sample stamp generator. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui16TrigValue value used to set the trigger. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampInConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup the sample stamp trigger for input streams. + HWREGH(I2S0_BASE + I2S_O_STMPINTRIG) = ui16TrigValue; +} + +//***************************************************************************** +// +//! \brief Configure the OUT sample stamp generator. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui16TrigValue value used to set the trigger. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampOutConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup the sample stamp trigger for output streams. + HWREGH(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui16TrigValue; +} + +//***************************************************************************** +// +//! \brief Add the specified value to the WCLK count. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param i16Value is the offset to add to the counter (this value can be negative) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SWclkCounterConfigure(uint32_t ui32Base, int16_t i16Value) +{ + uint16_t ui16MinusValue; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + if (i16Value >= 0) + { + HWREGH(I2S0_BASE + I2S_O_STMPWADD) = i16Value; + } + else + { + ui16MinusValue = (uint16_t)(-i16Value); + HWREGH(I2S0_BASE + I2S_O_STMPWADD) = HWREGH(I2S0_BASE + I2S_O_STMPWPER) - ui16MinusValue; + } +} + +//***************************************************************************** +// +//! \brief Reset the WCLK count. +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SWclkCounterReset(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREGH(I2S0_BASE + I2S_O_STMPWSET) = 0; +} + //***************************************************************************** // // Support for DriverLib in ROM: diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h new file mode 100644 index 000000000..5f2e1d9e0 --- /dev/null +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h @@ -0,0 +1,141 @@ +/****************************************************************************** +* Filename: i2s_doc.h +* Revised: $$ +* Revision: $$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup i2s_api +//! @{ +//! \section sec_i2s Introduction +//! +//! The I2S API provides a set of functions for using the I2S module. +//! This module provides a standardized serial interface to transfer +//! audio samples from and to external audio devices such as a codec, +//! DAC, or ADC. +//! +//! The I2S module has the following features: +//! - Audio clock signals are internally generated by the PRCM module +//! or externally by another device. +//! - One or two data pins, which can be configured independently as +//! input or output +//! - Various data formats according to the settings of the module +//! - Up to two channels per data pin for dual phase formats and up +//! to eight channels per data pin for single phase formats +//! - DMA with double-buffered pointers +//! - Error detection for DMA and audio clock signal integrity +//! - A Samplestamp generator that allows maintaining of constant +//! audio latency +//! +//! The I2S module is configured through the functions \ref I2SFormatConfigure(), +//! \ref I2SFrameConfigure() and \ref I2SWclkConfigure(). +//! Transfers are enabled using \ref I2SStart(). Transfers are disabled using +//! \ref I2SStop(). Please note that a specific procedure exists in order +//! to disable transfers without losing data (refer to \ref I2SStop()). +//! +//! Data are transmitted using the two double-buffered pointers. +//! For each interface, two registers are set with the address of the data to +//! transfer. These registers are named INPTR and INPTRNEXT for the input +//! interface and OUTPTR and OUTPTRNEXT for the output. When PTR is consumed, +//! the hardware copies the content of PTRNEXT into PTR and the next transfer +//! begins. +//! The address of the next value to write or to read in memory (i.e. to receive +//! or to send out) is set using \ref I2SInPointerSet() and \ref I2SOutPointerSet(). +//! The values contented by INPTRNEXT, OUTPTRNEXT, INPTR and OUTPTR can be read using +//! \ref I2SInPointerNextGet(), \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and +//! \ref I2SOutPointerGet() functions. +//! +//! Interrupts can help the user to refresh pointers on time. Interrupts can also +//! be used to detect I2S errors. \ref I2SIntEnable() and \ref I2SIntDisable() +//! activate and deactivate interrupt(s). Interrupt status can be read through +//! \ref I2SIntStatus() and a pending interrupt can be acquitted by +//! \ref I2SIntClear() function. +//! +//! The sample stamps generator can be configured to slightly delay the +//! emission or the reception of the data (based on the number of WCLK +//! cycles) using \ref I2SSampleStampInConfigure(), \ref I2SSampleStampOutConfigure(), +//! \ref I2SWclkCounterReset() and \ref I2SWclkCounterConfigure(). The current sample stamp +//! can be computed using \ref I2SSampleStampGet(). +//! To finish, the sample stamps generator can be enable and disable using +//! the following functions: \ref I2SSampleStampEnable() and +//! \ref I2SSampleStampDisable(). +//! The sample stamps generator must be enabled prior to any transfer. +//! +//! Note: Other functions contained in the PRCM API are required to handle I2S. +//! +//! \section sec_i2s_api API +//! +//! Two APIs are coexisting. +//! It is recommended to only use the new API as the old one is deprecated and +//! will be removed soon. +//! +//! New API: +//! Functions to perform I2S configuration: +//! - \ref I2SStart() +//! - \ref I2SStop() +//! - \ref I2SFormatConfigure() +//! - \ref I2SFrameConfigure() +//! - \ref I2SWclkConfigure() +//! +//! Functions to perform transfers: +//! - \ref I2SInPointerSet() +//! - \ref I2SOutPointerSet() +//! - \ref I2SInPointerGet() +//! - \ref I2SOutPointerGet() +//! - \ref I2SInPointerNextGet() +//! - \ref I2SOutPointerNextGet() +//! +//! Functions to handle interruptions: +//! - \ref I2SIntEnable() +//! - \ref I2SIntDisable() +//! - \ref I2SIntStatus() +//! - \ref I2SIntClear() +//! +//! Functions to handle sample stamps +//! - \ref I2SSampleStampEnable() +//! - \ref I2SSampleStampDisable() +//! - \ref I2SSampleStampInConfigure() +//! - \ref I2SSampleStampOutConfigure() +//! - \ref I2SSampleStampGet() +//! - \ref I2SWclkCounterConfigure() +//! - \ref I2SWclkCounterReset() +//! +//! Old API: +//! \ref I2SEnable(), \ref I2SDisable(), \ref I2SAudioFormatConfigure(), +//! \ref I2SChannelConfigure(), \ref I2SClockConfigure(), +//! \ref I2SBufferConfig(), \ref I2SIntEnable(), \ref I2SIntDisable(), +//! \ref I2SIntStatus(), \ref I2SIntClear(), \ref I2SSampleStampEnable(), +//! \ref I2SSampleStampDisable(), \ref I2SSampleStampGet(), +//! \ref I2SPointerSet (), \ref I2SPointerUpdate(), +//! \ref I2SSampleStampConfigure(), \ref I2SIntRegister(), +//! \ref I2SIntUnregister() +//! +//! @} diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/osc.c b/third_party/ti/devices/cc13x2_cc26x2/driverlib/osc.c index 3c557c182..1212d01e7 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/osc.c +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/osc.c @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: osc.c -* Revised: 2017-09-01 10:21:01 +0200 (Fri, 01 Sep 2017) -* Revision: 49677 +* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) +* Revision: 54539 * * Description: Driver for setting up the system Oscillators * @@ -67,14 +67,32 @@ #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #undef OSC_HPOSC_Debug_InitFreqOffsetParams + #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #undef OSC_HPOSCInitializeFrequencyOffsetParameters + #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters #undef OSC_HPOSCRelativeFrequencyOffsetGet #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet #undef OSC_AdjustXoscHfCapArray #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #undef OSC_HPOSCRtcCompensate + #define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate #endif +//***************************************************************************** +// +// Global HPOSC curve fitting polynomials +// Parameters found/calculated when calling function +// OSC_HPOSCInitializeFrequencyOffsetParameters() +// (or OSC_HPOSC_Debug_InitFreqOffsetParams() used for debugging only) +// These global variables must be updated before using HPOSC +// +//***************************************************************************** + +static int16_t _hpOscPolynomials[ 4 ]; + //***************************************************************************** // // OSCHF switch time calculator defines and globals @@ -311,6 +329,132 @@ OSC_AdjustXoscHfCapArray( int32_t capArrDelta ) DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg )); } +//***************************************************************************** +// +// Initialize the frequency offset curve fitting parameters +// These are either picked diretly from FCFG1:FREQ_OFFSET & FCFG1:MISC_CONF_2 or +// calculated based on the FCFG1:HPOSC_MEAS_x parameters. +// +//***************************************************************************** + +// Using the following hardcoded constants (Using temporary constants for now) +#define D1OFFSET_p25C -24 +#define D2OFFSET_p85C -36 +#define D3OFFSET_m40C 18 +#define P3_POLYNOMIAL -47 +#define N_INSERTIONS 3 + +typedef struct { + int32_t dFreq ; + int32_t temp ; +} insertion_t ; + +static void +InitializeMeasurmentSet( insertion_t * pInsertion, uint32_t registerAddress, int32_t deltaOffset, int32_t p3PolOffset ) +{ + // Doing the following adjustment to the deltaFrequence before finding the polynomials P0, P1, P2 + // Dx = Dx + DxOFFSET - ((P3*Tx^3)/2^18) + uint32_t insertionData = HWREG( registerAddress ); + pInsertion->dFreq = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W - FCFG1_HPOSC_MEAS_1_HPOSC_D1_S ))) + >> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W )); + pInsertion->temp = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W - FCFG1_HPOSC_MEAS_1_HPOSC_T1_S ))) + >> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W )); + pInsertion->dFreq = pInsertion->dFreq + deltaOffset - (( p3PolOffset * pInsertion->temp * pInsertion->temp * pInsertion->temp ) >> 18 ); +} + +static void +FindPolynomialsAndUpdateGlobals( insertion_t * pMeasurment ) +{ + uint32_t loopCount ; + int32_t polynomial_0 ; + int32_t polynomial_1 ; + int32_t polynomial_2 ; + + int32_t Syi_ = 0 ; + int32_t Sxi_ = 0 ; + int32_t Sxi2_ = 0 ; + int32_t Sxiyi_ = 0 ; + int32_t Sxi2yi_ = 0 ; + int32_t Sxi3_ = 0 ; + int32_t Sxi4_ = 0 ; + + for ( loopCount = 0 ; loopCount < N_INSERTIONS ; loopCount++ ) { + int32_t x ; + int32_t x2 ; + int32_t y ; + + x = pMeasurment[ loopCount ].temp ; + x2 = ( x * x ); + y = pMeasurment[ loopCount ].dFreq ; + + Syi_ += ( y ); + Sxi_ += ( x ); + Sxi2_ += ( x2 ); + Sxiyi_ += ( x * y ); + Sxi2yi_ += ( x2 * y ); + Sxi3_ += ( x2 * x ); + Sxi4_ += ( x2 * x2 ); + } + + int32_t Sxx_ = ( Sxi2_ * N_INSERTIONS ) - ( Sxi_ * Sxi_ ); + int32_t Sxy_ = ( Sxiyi_ * N_INSERTIONS ) - ( Sxi_ * Syi_ ); + int32_t Sxx2_ = ( Sxi3_ * N_INSERTIONS ) - ( Sxi_ * Sxi2_ ); + int32_t Sx2y_ = ( Sxi2yi_ * N_INSERTIONS ) - ( Sxi2_ * Syi_ ); + int32_t Sx2x2_ = ( Sxi4_ * N_INSERTIONS ) - ( Sxi2_ * Sxi2_ ); + + int32_t divisor = ((((int64_t) Sxx_ * Sx2x2_ ) - ((int64_t) Sxx2_ * Sxx2_ )) + (1<<9)) >> 10 ; + if ( divisor == 0 ) { + polynomial_2 = 0 ; + polynomial_1 = 0 ; + } else { + polynomial_2 = (((int64_t) Sx2y_ * Sxx_ ) - ((int64_t) Sxy_ * Sxx2_ )) / divisor ; + polynomial_1 = (((int64_t) Sxy_ * Sx2x2_ ) - ((int64_t) Sx2y_ * Sxx2_ )) / divisor ; + } + polynomial_0 = ( Syi_ - (((( polynomial_1 * Sxi_ ) + ( polynomial_2 * Sxi2_ )) + (1<<9)) >> 10 )) / N_INSERTIONS ; + polynomial_1 = ( polynomial_1 + (1<<6)) >> 7 ; + + _hpOscPolynomials[ 0 ] = polynomial_0 ; + _hpOscPolynomials[ 1 ] = polynomial_1 ; + _hpOscPolynomials[ 2 ] = polynomial_2 ; + _hpOscPolynomials[ 3 ] = P3_POLYNOMIAL ; +} + +//***************************************************************************** +// Degub function to calculate the HPOSC polynomials for experimental data sets. +//***************************************************************************** +void +OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData ) +{ + // Calculate the curve fitting parameters from temp insertion measurements + // But first adjust the measurements with constants found in characterization + insertion_t pMeasurment[ 3 ]; + + InitializeMeasurmentSet( &pMeasurment[ 0 ], (uint32_t)&pDebugData->meas_1, pDebugData->offsetD1, pDebugData->polyP3 ); + InitializeMeasurmentSet( &pMeasurment[ 1 ], (uint32_t)&pDebugData->meas_2, pDebugData->offsetD2, pDebugData->polyP3 ); + InitializeMeasurmentSet( &pMeasurment[ 2 ], (uint32_t)&pDebugData->meas_3, pDebugData->offsetD3, pDebugData->polyP3 ); + + FindPolynomialsAndUpdateGlobals( pMeasurment ); +} + +//***************************************************************************** +// The general HPOSC initialization function - Must always be called before using HPOSC +//***************************************************************************** +void +OSC_HPOSCInitializeFrequencyOffsetParameters( void ) +{ + { + // Calculate the curve fitting parameters from temp insertion measurements + // But first adjust the measurements with constants found in characterization + insertion_t pMeasurment[ 3 ]; + + InitializeMeasurmentSet( &pMeasurment[ 0 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_1, D1OFFSET_p25C, P3_POLYNOMIAL ); + InitializeMeasurmentSet( &pMeasurment[ 1 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_2, D2OFFSET_p85C, P3_POLYNOMIAL ); + InitializeMeasurmentSet( &pMeasurment[ 2 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_3, D3OFFSET_m40C, P3_POLYNOMIAL ); + + FindPolynomialsAndUpdateGlobals( pMeasurment ); + } +} + //***************************************************************************** // // Calculate the temperature dependent relative frequency offset of HPOSC @@ -320,17 +464,11 @@ int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ) { // Estimate HPOSC frequency, using temperature and curve fitting parameters - uint32_t fitParams = HWREG(FCFG1_BASE + FCFG1_O_FREQ_OFFSET); - // Extract the P0,P1,P2 params, and sign extend them via shifting up/down - int32_t paramP0 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S)) - >> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W)); - int32_t paramP1 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S)) - >> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W)); - int32_t paramP2 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S)) - >> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W)); - int32_t paramP3 = ((((int32_t) HWREG(FCFG1_BASE + FCFG1_O_MISC_CONF_2)) - << (32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S)) - >> (32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W)); + + int32_t paramP0 = _hpOscPolynomials[ 0 ]; + int32_t paramP1 = _hpOscPolynomials[ 1 ]; + int32_t paramP2 = _hpOscPolynomials[ 2 ]; + int32_t paramP3 = _hpOscPolynomials[ 3 ]; // Now we can find the HPOSC freq offset, given as a signed variable d, expressed by: // @@ -395,6 +533,41 @@ OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffs return ( rfCoreFreqOffset ); } +//***************************************************************************** +// +// Compensate the RTC increment based on the relative frequency offset of HPOSC +// +//***************************************************************************** +void +OSC_HPOSCRtcCompensate( int32_t relFreqOffset ) +{ + uint32_t rtcSubSecInc; + uint32_t lfClkFrequency; + uint32_t hfFreq; + int64_t calcFactor; + + // Calculate SCLK_HF frequency, defined as: + // hfFreq = 48000000 * (1 + relFreqOffset/(2^22)) + if( relFreqOffset >= 0 ) + { + calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) + 0x200000 ) / 0x400000; + } + else + { + calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) - 0x200000 ) / 0x400000; + } + hfFreq = 48000000 + calcFactor; + + // Calculate SCLK_LF frequency, defined as SCLK_LF_FREQ = SCLK_HF_FREQ / 1536 + lfClkFrequency = ( hfFreq + 768 ) / 1536; + + // Calculate SUBSECINC, defined as: SUBSECINC = 2^38 / SCLK_LF_FREQ + rtcSubSecInc = 0x4000000000 / lfClkFrequency; + + /* Update SUBSECINC value */ + SetupSetAonRtcSubSecInc(rtcSubSecInc); +} + //***************************************************************************** // // Get crystal amplitude (assuming crystal is running). diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/osc.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/osc.h index 20215fd14..52fe0f30a 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/osc.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/osc.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: osc.h -* Revised: 2018-04-18 15:47:09 +0200 (Wed, 18 Apr 2018) -* Revision: 51907 +* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) +* Revision: 54539 * * Description: Defines and prototypes for the system oscillator control. * @@ -62,6 +62,8 @@ extern "C" #include #include #include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" #include "../inc/hw_types.h" #include "../inc/hw_memmap.h" #include "../inc/hw_ddi.h" @@ -92,9 +94,12 @@ extern "C" #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate #endif //***************************************************************************** @@ -208,9 +213,9 @@ OSCClockLossEventDisable( void ) //! Use this function to set the oscillator source for one or more of the //! system source clocks. //! -//! When selecting the high frequency clock source, this function will not do +//! When selecting the high frequency clock source (OSC_SRC_CLK_HF), this function will not do //! the actual switch. Enabling the high frequency XTAL can take several hundred -//! micro seconds, so the actual switch is split into a separate function, +//! micro seconds, so the actual switch is done in a separate function, \ref OSCHfSourceSwitch(), //! leaving System CPU free to perform other tasks as the XTAL starts up. //! //! \note The High Frequency (\ref OSC_SRC_CLK_HF) can only be derived from the @@ -232,7 +237,7 @@ OSCClockLossEventDisable( void ) //! - \ref OSC_RCOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) //! - \ref OSC_XOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) //! -//! \sa OSCClockSourceGet() +//! \sa \ref OSCClockSourceGet(), \ref OSCHfSourceSwitch() //! //! \return None // @@ -292,7 +297,7 @@ OSCHfSourceReady(void) //! //! When switching the HF clock source the clock period might be prolonged //! leaving the clock 'stuck-at' high or low for a few cycles. To ensure that -//! this does not coincide with a read access to the Flash potentially +//! this does not coincide with a read access to the Flash, potentially //! freezing the device, the HF clock source switch must be executed from ROM. //! //! \note This function will not return until the clock source has been @@ -307,8 +312,82 @@ OSCHfSourceReady(void) __STATIC_INLINE void OSCHfSourceSwitch(void) { + // Read target clock (lower half of the 32-bit CTL0 register) + uint16_t hfSrc = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0) & DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M; + + // If target clock source is RCOSC, change clock source for DCDC to RCOSC + if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC) + { + // Force DCDC to use RCOSC before switching SCLK_HF to RCOSC + HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16); + // Dummy read to ensure that the write has propagated + HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); + } + // Switch the HF clock source HapiHFSourceSafeSwitch(); + + // If target clock source is XOSC, change clock source for DCDC to "auto" + if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC) + { + // Set DCDC clock source back to "auto" after SCLK_HF was switched to XOSC + HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M; + } +} + +//***************************************************************************** +// +//! \brief Identifies if HPOSC is enabled. +//! +//! This function checks if the device supports HPOSC and that HPOSC is selected +//! as HF oscillator for use when the radio is active. +//! +//! \return Returns status of HPOSC functionality: +//! - \c true : HPOSC is enabled. +//! - \c false : HPOSC is not enabled. +// +//***************************************************************************** +__STATIC_INLINE bool +OSC_IsHPOSCEnabled(void) +{ + bool enabled = false; + + if((( HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & CCFG_MODE_CONF_XOSC_FREQ_M) == CCFG_MODE_CONF_XOSC_FREQ_HPOSC) && + (( HWREG(FCFG1_BASE + FCFG1_O_OSC_CONF) & FCFG1_OSC_CONF_HPOSC_OPTION) == 0)) + { + enabled = true; + } + + return (enabled); +} + +//***************************************************************************** +// +//! \brief Identifies if HPOSC is enabled and that SCLK_LF is derived from XOSC_HF. +//! +//! This function checks if the device supports HPOSC and that HPOSC is selected +//! as HF oscillator for use when the radio is active and also that SCLK_LF is +//! derived from XOSC_HF. +//! +//! \return Returns status of HPOSC and SCLK_LF configuration: +//! - \c true : HPOSC is enabled and SCLK_LF is derived from XOSC_HF. +//! - \c false : Either HPOSC not enabled or SCLK_LF is not derived from XOSC_HF. +// +//***************************************************************************** +__STATIC_INLINE bool +OSC_IsHPOSCEnabledWithHfDerivedLfClock(void) +{ + bool enabled = false; + + // Check configuration by reading lower half of the 32-bit CTL0 register + uint16_t regVal = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); + if( ( ( regVal & DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M ) == DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF ) && + ( ( regVal & DDI_0_OSC_CTL0_HPOSC_MODE_EN_M ) == DDI_0_OSC_CTL0_HPOSC_MODE_EN ) ) + { + enabled = true; + } + + return (enabled); } //***************************************************************************** @@ -402,6 +481,53 @@ extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); //***************************************************************************** extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); +//***************************************************************************** +// +//! \brief Data structure for experimental HPOSC polynomials calculation. +//! +//! The structure of the meas_1, meas_2 and meas_3 parameter is +//! as defined in FCFG1_O_HPOSC_MEAS_1, 2 and 3. +//! +//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams() +// +//***************************************************************************** +typedef struct { + uint32_t meas_1 ; //!< Measurement set 1 (typically at room temp) + uint32_t meas_2 ; //!< Measurement set 2 (typically at high temp) + uint32_t meas_3 ; //!< Measurement set 3 (typically at low temp) + int32_t offsetD1 ; //!< Offset to measurement set 1 + int32_t offsetD2 ; //!< Offset to measurement set 2 + int32_t offsetD3 ; //!< Offset to measurement set 3 + int32_t polyP3 ; //!< The P3 polynomial +} HposcDebugData_t; + +//***************************************************************************** +// +//! \brief Debug function to calculate the HPOSC polynomials for experimental data sets. +//! +//! \param pDebugData pointer to the input data collected in \ref HposcDebugData_t +//! +//! \return None +//! +//! \sa OSC_HPOSCInitializeFrequencyOffsetParameters() +// +//***************************************************************************** +extern void OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData ); + +//***************************************************************************** +// +//! \brief HPOSC initialization function. Must always be called before using HPOSC. +//! +//! Calculates the fitting curve parameters (polynomials) to used by the +//! HPOSC temperature compensation. +//! +//! \return None +//! +//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams() +// +//***************************************************************************** +extern void OSC_HPOSCInitializeFrequencyOffsetParameters( void ); + //***************************************************************************** // //! \brief Calculate the temperature dependent relative frequency offset of HPOSC @@ -481,6 +607,43 @@ extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); //***************************************************************************** extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ); +//***************************************************************************** +// +//! \brief Compensate the RTC increment based on the relative frequency offset of HPOSC +//! +//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature. +//! This variation forces the RTC increment to be compensated if SCLK_LF is configured +//! to be derived from the HF clock of HPOSC. +//! This function must only be called if SCLK_LF is configured to be derived from +//! the HF clock of HPOSC. The status of this configuration can be determined +//! by calling the \ref OSC_IsHPOSCEnabledWithHfDerivedLfClock() function. +//! +//! This function first calculates the HPOSC frequency, defined as: +//! 

+//!     F_HPOSC = F_nom * (1 + d/(2^22))
+//!
+//! where +//! - F_HPOSC is the current HPOSC frequency. +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - d is the relative frequency offset given by the input argument relFreqOffset. +//! Then the SCLK_LF frequency is calculated, defined as: +//! 
+//!     F_SCLK_LF = F_HPOSC / 1536
+//!
+//! Then the RTC increment SUBSECINC is calculated, defined as; +//! 
+//!     SUBSECINC = (2^38) / F_SCLK_LF
+//!
+//! Finally the RTC module is updated with the calculated SUBSECINC value. +//! +//! \param relFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet() +//! +//! \return None +//! +// +//***************************************************************************** +extern void OSC_HPOSCRtcCompensate( int32_t relFreqOffset ); + //***************************************************************************** // // Support for DriverLib in ROM: @@ -521,6 +684,14 @@ extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HP #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude #define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude #endif + #ifdef ROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #undef OSC_HPOSC_Debug_InitFreqOffsetParams + #define OSC_HPOSC_Debug_InitFreqOffsetParams ROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #endif + #ifdef ROM_OSC_HPOSCInitializeFrequencyOffsetParameters + #undef OSC_HPOSCInitializeFrequencyOffsetParameters + #define OSC_HPOSCInitializeFrequencyOffsetParameters ROM_OSC_HPOSCInitializeFrequencyOffsetParameters + #endif #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet #undef OSC_HPOSCRelativeFrequencyOffsetGet #define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet @@ -533,6 +704,10 @@ extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HP #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #endif + #ifdef ROM_OSC_HPOSCRtcCompensate + #undef OSC_HPOSCRtcCompensate + #define OSC_HPOSCRtcCompensate ROM_OSC_HPOSCRtcCompensate + #endif #endif //***************************************************************************** diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/pka.c b/third_party/ti/devices/cc13x2_cc26x2/driverlib/pka.c index ad3f04e68..57e4b5818 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/pka.c +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/pka.c @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: pka.c -* Revised: 2018-05-08 10:58:47 +0200 (Tue, 08 May 2018) -* Revision: 51975 +* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018) +* Revision: 52294 * * Description: Driver for the PKA module * @@ -45,6 +45,8 @@ // //***************************************************************************** #if !defined(DOXYGEN) + #undef PKAClearPkaRam + #define PKAClearPkaRam NOROM_PKAClearPkaRam #undef PKAGetOpsStatus #define PKAGetOpsStatus NOROM_PKAGetOpsStatus #undef PKAArrayAllZeros @@ -102,6 +104,8 @@ // //***************************************************************************** #if !defined(DOXYGEN) + #undef PKAClearPkaRam + #define PKAClearPkaRam NOROM_PKAClearPkaRam #undef PKAGetOpsStatus #define PKAGetOpsStatus NOROM_PKAGetOpsStatus #undef PKAArrayAllZeros @@ -569,6 +573,29 @@ const PKA_EccParam256 Curve25519_order = {.byte = {0xb9, 0xdc, 0xf5, 0x5c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +//***************************************************************************** +// +// Zeroize PKA RAM. Not threadsafe. +// +//***************************************************************************** +void PKAClearPkaRam(void){ + // Get initial state + uint32_t secdmaclkgr = HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR); + + // OR in zeroize bit + secdmaclkgr |= PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N; + + // Start zeroization + HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr; + + // Wait 256 cycles for PKA RAM to be cleared + CPUdelay(256 / 4); + + // Turn off zeroization + HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr & (~PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N); +} + //***************************************************************************** // // Write a PKA parameter to the PKA module, set required registers, and add an offset. diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/pka.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/pka.h index d178c9249..e175ada8d 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/pka.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/pka.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: pka.h -* Revised: 2018-03-02 10:51:37 +0100 (Fri, 02 Mar 2018) -* Revision: 51635 +* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018) +* Revision: 52294 * * Description: PKA header file. * @@ -83,6 +83,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) + #define PKAClearPkaRam NOROM_PKAClearPkaRam #define PKAGetOpsStatus NOROM_PKAGetOpsStatus #define PKAArrayAllZeros NOROM_PKAArrayAllZeros #define PKAZeroOutArray NOROM_PKAZeroOutArray @@ -603,6 +604,15 @@ extern const PKA_EccParam256 Curve25519_order; // //***************************************************************************** +//***************************************************************************** +// +//! \brief Zeroizes PKA RAM. +//! +//! This function uses the zeroization function in PRCM to clear the PKA RAM. +// +//***************************************************************************** +extern void PKAClearPkaRam(void); + //***************************************************************************** // //! \brief Gets the PKA operation status. @@ -1323,6 +1333,10 @@ extern uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX //***************************************************************************** #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" + #ifdef ROM_PKAClearPkaRam + #undef PKAClearPkaRam + #define PKAClearPkaRam ROM_PKAClearPkaRam + #endif #ifdef ROM_PKAGetOpsStatus #undef PKAGetOpsStatus #define PKAGetOpsStatus ROM_PKAGetOpsStatus diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/prcm.c b/third_party/ti/devices/cc13x2_cc26x2/driverlib/prcm.c index b4e36119d..e81df8f93 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/prcm.c +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/prcm.c @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: prcm.c -* Revised: 2017-07-19 10:58:53 +0200 (Wed, 19 Jul 2017) -* Revision: 49363 +* Revised: 2018-10-18 17:33:32 +0200 (Thu, 18 Oct 2018) +* Revision: 52954 * * Description: Driver for the PRCM. * @@ -53,6 +53,10 @@ #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet #undef PRCMAudioClockConfigSetOverride #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride + #undef PRCMAudioClockInternalSource + #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource + #undef PRCMAudioClockExternalSource + #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource #undef PRCMPowerDomainOn #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn #undef PRCMPowerDomainOff @@ -350,6 +354,64 @@ PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; } +//***************************************************************************** +// +// Configure the audio clocks for I2S module +// +//***************************************************************************** +void +PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv) +{ + // Check the arguments. + ASSERT( ui8BitsPerSample == PRCM_WCLK_SINGLE_PHASE + || ui8BitsPerSample == PRCM_WCLK_DUAL_PHASE + || ui8BitsPerSample == PRCM_WCLK_USER_DEF); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui8WCLKPhase) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity and enable it. + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = (ui8SamplingEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S) | + (ui8WCLKPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S ) | + (1 << PRCM_I2SCLKCTL_EN_S ); +} + +//***************************************************************************** +// +// Configure the clocks as "internally generated". +// +//***************************************************************************** +void PRCMAudioClockInternalSource(void) +{ + HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 1; +} + +//***************************************************************************** +// +// Configure the clocks as "externally generated". +// +//***************************************************************************** +void PRCMAudioClockExternalSource(void) +{ + HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 0; +} + //***************************************************************************** // // Turn power on in power domains in the MCU domain diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/prcm.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/prcm.h index fabda4b42..783ca4214 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/prcm.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/prcm.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: prcm.h -* Revised: 2017-12-11 16:44:38 +0100 (Mon, 11 Dec 2017) -* Revision: 50602 +* Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) +* Revision: 52979 * * Description: Defines and prototypes for the PRCM * @@ -71,6 +71,7 @@ extern "C" #include "debug.h" #include "cpu.h" + //***************************************************************************** // // Support for DriverLib in ROM: @@ -89,6 +90,8 @@ extern "C" #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride + #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource + #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable @@ -169,6 +172,11 @@ extern "C" #define PRCM_WCLK_SINGLE_PHASE 0x00000000 #define PRCM_WCLK_DUAL_PHASE 0x00000002 #define PRCM_WCLK_USER_DEF 0x00000004 +#define PRCM_I2S_WCLK_NEG_EDGE 0 +#define PRCM_I2S_WCLK_POS_EDGE 1 +#define PRCM_I2S_WCLK_SINGLE_PHASE 0 +#define PRCM_I2S_WCLK_DUAL_PHASE 1 +#define PRCM_I2S_WCLK_USER_DEF 2 #define I2S_SAMPLE_RATE_16K 0x00000001 #define I2S_SAMPLE_RATE_24K 0x00000002 @@ -428,6 +436,8 @@ PRCMAudioClockDisable(void) // //! \brief Configure the audio clock generation. //! +//! \deprecated This function will be removed in a future release. +//! //! Use this function to set the sample rate when using internal audio clock //! generation for the I2S module. //! @@ -455,13 +465,17 @@ PRCMAudioClockDisable(void) //! \sa \ref PRCMAudioClockConfigSetOverride() // //***************************************************************************** +#ifndef DEPRECATED extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate); +#endif //***************************************************************************** // //! \brief Configure the audio clock generation with manual setting of clock divider. //! +//! \deprecated This function will be removed in a future release. +//! //! Use this function to set the audio clock divider values manually. //! //! \note See hardware documentation before setting audio clock dividers manually. @@ -483,8 +497,64 @@ extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, //! \sa \ref PRCMAudioClockConfigSet() // //***************************************************************************** +#ifndef DEPRECATED extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv); +#endif + +//***************************************************************************** +// +//! \brief Configure the audio clocks for I2S module. +//! +//! \note See hardware documentation before setting audio clock dividers. +//! This is user's responsability to provide valid clock dividers. +//! +//! \param ui8SamplingEdge Define the clock polarity: +//! - \ref PRCM_I2S_WCLK_NEG_EDGE +//! - \ref PRCM_I2S_WCLK_POS_EDGE +//! \param ui8WCLKPhase Define I2S phase used +//! - PRCM_I2S_WCLK_SINGLE_PHASE +//! - PRCM_I2S_WCLK_DUAL_PHASE +//! - PRCM_I2S_WCLK_USER_DEF +//! \param ui32MstDiv is the desired master clock divider. +//! \param ui32BitDiv is the desired bit clock divider. +//! \param ui32WordDiv is the desired word clock divider. +//! +//! \return None +//! +//***************************************************************************** +extern void PRCMAudioClockConfigOverride + (uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv); + +//***************************************************************************** +// +//! \brief Configure the audio clocks to be internally generated. +//! +//! Use this function to set the audio clocks as internal. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockExternalSource() +// +//***************************************************************************** +extern void PRCMAudioClockInternalSource(void); + +//***************************************************************************** +// +//! \brief Configure the audio clocks to be externally generated. +//! +//! Use this function to set the audio clocks as external. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockInternalSource() +// +//***************************************************************************** +extern void PRCMAudioClockExternalSource(void); //***************************************************************************** // @@ -1094,6 +1164,14 @@ PRCMCacheRetentionDisable( void ) #undef PRCMAudioClockConfigSetOverride #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride #endif + #ifdef ROM_PRCMAudioClockInternalSource + #undef PRCMAudioClockInternalSource + #define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource + #endif + #ifdef ROM_PRCMAudioClockExternalSource + #undef PRCMAudioClockExternalSource + #define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource + #endif #ifdef ROM_PRCMPowerDomainOn #undef PRCMPowerDomainOn #define PRCMPowerDomainOn ROM_PRCMPowerDomainOn diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h index 2fc251fbb..d8517d0e4 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rf_ble_cmd.h -* Revised: 2018-05-07 15:02:01 +0200 (Mon, 07 May 2018) -* Revision: 18438 +* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018) +* Revision: 18572 * * Description: CC13x2/CC26x2 API for Bluetooth Low Energy commands * @@ -203,9 +203,8 @@ struct __RFC_STRUCT rfc_ble5RadioOp_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) uint8_t* pParams; //!< Pointer to command specific parameter structure uint8_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; @@ -258,12 +257,11 @@ struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) uint8_t* pParams; //!< Pointer to command specific parameter structure uint8_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -812,12 +810,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_ble5SlavePar_t *pParams; //!< Pointer to command specific parameter structure rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -875,12 +872,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_ble5MasterPar_t *pParams; //!< Pointer to command specific parameter structure rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -938,12 +934,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_ble5AdvExtPar_t *pParams; //!< Pointer to command specific parameter structure rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -1001,12 +996,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_ble5AdvAuxPar_t *pParams; //!< Pointer to command specific parameter structure rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -1064,12 +1058,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_ble5ScannerPar_t *pParams; //!< Pointer to command specific parameter structure rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -1127,12 +1120,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_ble5InitiatorPar_t *pParams; //!< Pointer to command specific parameter structure rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -1190,12 +1182,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -1253,12 +1244,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -1316,12 +1306,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -1379,12 +1368,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -1442,12 +1430,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -1505,12 +1492,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s { uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
//!< 0x0000: Use default TX power
- //!< 0xFFFF: Use field tx20Power to set power for 20-dBm PA or to switch PA - //!< (command structure that includes tx20Power must be used; patch - //!< required) + //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF (patch required):
+ uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
//!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; //!< overrides the one given in radio setup for the duration of the command.
//!< If tx20Power >= 0x10000000: Pointer to PA change override structure @@ -1760,9 +1746,9 @@ struct __RFC_STRUCT rfc_bleAdvPar_s { uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
//!< 1: Discard messages with illegal length for the given packet type uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
- //!< 1: Report support of Channel Selection Algorithm #2 (patch required) - uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used (if patch is used) - //!< 1: Filter on bPrivIgn always (patch required) + //!< 1: Report support of Channel Selection Algorithm #2 + uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used + //!< 1: Filter on bPrivIgn always uint8_t rpaMode:1; //!< \brief Resolvable private address mode
//!< 0: Normal operation
//!< 1: Use white list for a received RPA regardless of filter policy @@ -1777,7 +1763,12 @@ struct __RFC_STRUCT rfc_bleAdvPar_s { rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed //!< advertiser). If least significant bit is 1, the address type given by //!< advConfig.peerAddrType is inverted. - uint16_t __dummy0; + struct { + uint8_t scanRspEndType:1; //!< \brief Command status at end if SCAN_RSP was sent:
+ //!< 0: End with BLE_DONE_OK and result True
+ //!< 1: End with BLE_DONE_SCAN_RSP and result False + } behConfig; + uint8_t __dummy0; uint8_t __dummy1; struct { uint8_t triggerType:4; //!< The type of trigger @@ -1897,7 +1888,7 @@ struct __RFC_STRUCT rfc_bleInitiatorPar_s { uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
//!< 1: Discard messages with illegal length for the given packet type uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
- //!< 1: Report support of Channel Selection Algorithm #2 (patch required) + //!< 1: Report support of Channel Selection Algorithm #2 } initConfig; uint8_t __dummy0; uint8_t connectReqLen; //!< Size of connect request data @@ -2171,13 +2162,17 @@ struct __RFC_STRUCT rfc_ble5AdvAuxPar_s { //!< 1: Discard messages with illegal length for the given packet type uint8_t bDirected:1; //!< \brief 0: Advertiser is undirected: pWhiteList points to a white list //!< 1: Advertiser is directed: pWhiteList points to a single device address - uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used (if patch is used) - //!< 1: Filter on bPrivIgn always (patch required) + uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used + //!< 1: Filter on bPrivIgn always uint8_t rpaMode:1; //!< \brief Resolvable private address mode
//!< 0: Normal operation
//!< 1: Use white list for a received RPA regardless of filter policy } advConfig; - uint8_t __dummy0; + struct { + uint8_t scanRspEndType:1; //!< \brief Command status at end if AUX_SCAN_RSP was sent:
+ //!< 0: End with BLE_DONE_OK and result True
+ //!< 1: End with BLE_DONE_SCAN_RSP and result False + } behConfig; uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points @@ -2258,14 +2253,41 @@ struct __RFC_STRUCT rfc_ble5ScannerPar_s { struct { uint8_t bCheckAdi:1; //!< \brief 0: Do not perform ADI filtering
//!< 1: Perform ADI filtering on packets where ADI is present - uint8_t bAutoAdiUpdate:1; //!< \brief 0: Do not update ADI entries in radio CPU
- //!< 1: Automatically update ADI entry for received packets with AuxPtr - uint8_t bApplyDuplicateFiltering:1;//!< \brief 0: Do not apply duplicate filtering based on device address for extended advertiser packets
- //!< 1: Apply duplicate filtering based on device address for extended advertiser packets with no ADI field + uint8_t bAutoAdiUpdate:1; //!< \brief 0: Do not update ADI entries in radio CPU using legacy mode (recommended)
+ //!< 1: Legacy mode: Automatically update ADI entry for received packets with + //!< AdvDataInfo after first occurrence + uint8_t bApplyDuplicateFiltering:1;//!< \brief 0: Do not apply duplicate filtering based on device address for extended + //!< advertiser packets (recommended)
+ //!< 1: Apply duplicate filtering based on device address for extended advertiser + //!< packets with no ADI field uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for extended advertising packets
//!< 1: Automatically set ignore bit in white list for extended advertising packets + uint8_t bAutoAdiProcess:1; //!< \brief 0: Do not use automatic ADI processing
+ //!< 1: Automatically update ADI entry for received packets so that only the same + //!< ADI is accepted for the rest of the chain and the SID/DID combination is + //!< ignored after the entire chain is received. + uint8_t bExclusiveSid:1; //!< \brief 0: Set adiStatus.state to 0 when command starts so that all + //!< valid SIDs are accepted
+ //!< 1: Do not modify adiStatus.state when command starts
} extFilterConfig; - uint32_t __dummy0; + struct { + uint8_t lastAcceptedSid:4; //!< Indication of SID of last successfully received packet that was not ignored + uint8_t state:3; //!< \brief 0: No extended packet received, or last extended packet didn't have an ADI; + //!< lastAcceptedSid field is not valid
+ //!< 1: A message with ADI has been received, but no chain is under reception; + //!< ADI filtering to be performed normally
+ //!< 2: A message with SID as given in lastAcceptedSid has been + //!< received, and chained messages are still pending. Messages without this + //!< SID will be ignored
+ //!< 3: An AUX_SCAN_RSP message has been received after receiving messages with SID + //!< as given in lastAcceptedSid, and chained messages are + //!< pending. Messages with an ADI field will be ignored.
+ //!< 4: A message with no ADI has been received, and chained messages are still + //!< pending. Messages with an ADI field will be ignored.
+ //!< Others: Reserved + } adiStatus; + uint8_t __dummy0; + uint16_t __dummy1; uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. //!< If least significant bit is 1, the address type given by //!< scanConfig.deviceAddrType is inverted. @@ -2332,7 +2354,7 @@ struct __RFC_STRUCT rfc_ble5InitiatorPar_s { uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
//!< 1: Discard messages with illegal length for the given packet type uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2 in CONNECT_IND
- //!< 1: Report support of Channel Selection Algorithm #2 in CONNECT_IND (patch required) + //!< 1: Report support of Channel Selection Algorithm #2 in CONNECT_IND } initConfig; uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h index 66bf7c208..b43d0993d 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rf_ble_mailbox.h -* Revised: 2018-01-23 19:51:42 +0100 (Tue, 23 Jan 2018) -* Revision: 18189 +* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) +* Revision: 18171 * * Description: Definitions for BLE interface * @@ -54,6 +54,7 @@ #define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command #define BLE_DONE_AUX 0x1409 ///< Operation ended after following aux pointer pointing far ahead #define BLE_DONE_CONNECT_CHSEL0 0x140A ///< CONNECT_IND received or transmitted; peer does not support channel selection algorithm #2 +#define BLE_DONE_SCAN_RSP 0x140B ///< SCAN_RSP or AUX_SCAN_RSP transmitted ///@} /// \name Operation finished with error ///@{ diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h index 5bf60b069..b479f8883 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rf_common_cmd.h -* Revised: 2018-05-07 15:02:01 +0200 (Mon, 07 May 2018) -* Revision: 18438 +* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018) +* Revision: 18756 * * Description: CC13x2/CC26x2 API for common/generic commands * @@ -103,9 +103,11 @@ typedef struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s rfc_CMD_DISARM_RAT_CH_t; typedef struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s rfc_CMD_SET_TX_POWER_t; typedef struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s rfc_CMD_SET_TX20_POWER_t; typedef struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s rfc_CMD_CHANGE_PA_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s rfc_CMD_UPDATE_HPOSC_FREQ_t; typedef struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s rfc_CMD_UPDATE_FS_t; typedef struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s rfc_CMD_MODIFY_FS_t; typedef struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s rfc_CMD_BUS_REQUEST_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s rfc_CMD_SET_CMD_START_IRQ_t; //! \addtogroup command //! @{ @@ -256,7 +258,7 @@ struct __RFC_STRUCT rfc_CMD_FS_s { uint8_t bTxMode:1; //!< \brief 0: Start synth in RX mode
//!< 1: Start synth in TX mode uint8_t refFreq:6; //!< \brief 0: Use default reference frequency
- //!< Others: Use reference frequency 24 MHz/refFreq + //!< Others: Use reference frequency 48 MHz/refFreq } synthConf; uint8_t __dummy0; //!< Reserved, always write 0 uint8_t __dummy1; //!< Reserved @@ -1020,6 +1022,17 @@ struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s { //! @} +//! \addtogroup CMD_UPDATE_HPOSC_FREQ +//! @{ +#define CMD_UPDATE_HPOSC_FREQ 0x0608 +//! Set New Frequency Offset for HPOSC +struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s { + uint16_t commandNo; //!< The command ID number 0x0608 + int16_t freqOffset; //!< Relative frequency offset, signed, scaled by 2-22 +} __RFC_STRUCT_ATTR; + +//! @} + //! \addtogroup CMD_UPDATE_FS //! @{ #define CMD_UPDATE_FS 0x0011 @@ -1060,6 +1073,17 @@ struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s { //! @} +//! \addtogroup CMD_SET_CMD_START_IRQ +//! @{ +#define CMD_SET_CMD_START_IRQ 0x0411 +//! Enable or disable generation of IRQ when a radio operation command starts +struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s { + uint16_t commandNo; //!< The command ID number 0x0411 + uint8_t bEna; //!< 1 to enable interrupt generation; 0 to disable it +} __RFC_STRUCT_ATTR; + +//! @} + //! @} //! @} #endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h index a8a2031ff..c79465c4f 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rf_data_entry.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 +* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) +* Revision: 18170 * * Description: Definition of API for data exchange * diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h index 90345694e..e681acc04 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rf_hs_cmd.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 +* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) +* Revision: 18170 * * Description: CC13x2/CC26x2 API for high-speed mode commands * diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h index f112d4f57..e1fb7a05c 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rf_hs_mailbox.h -* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) -* Revision: 18032 +* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) +* Revision: 18171 * * Description: Definitions for high-speed mode radio interface * diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h index fa54308c7..f33facdfe 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rf_ieee_cmd.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 +* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) +* Revision: 18170 * * Description: CC13x2/CC26x2 API for IEEE 802.15.4 commands * diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h index 48af9ab12..a23d71ad0 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rf_mailbox.h -* Revised: 2018-05-07 15:02:01 +0200 (Mon, 07 May 2018) -* Revision: 18438 +* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018) +* Revision: 18756 * * Description: Definitions for interface between system and radio CPU * @@ -83,6 +83,8 @@ typedef struct { #define IRQN_TX_RETRANS 9 ///< Packet retransmitted #define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished #define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete +#define IRQN_COMMAND_STARTED 12 ///< A radio operation command has gone into active state +#define IRQN_FG_COMMAND_STARTED 13 ///< FG level radio operation command has gone into active state #define IRQN_PA_CHANGED 14 ///< PA is changed #define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored #define IRQN_RX_NOK 17 ///< Packet received with CRC error @@ -117,6 +119,8 @@ typedef struct { #define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) #define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) +#define IRQ_COMMAND_STARTED (1U << IRQN_COMMAND_STARTED) +#define IRQ_FG_COMMAND_STARTED (1U << IRQN_FG_COMMAND_STARTED) #define IRQ_PA_CHANGED (1U << IRQN_PA_CHANGED) #define IRQ_RX_OK (1U << IRQN_RX_OK) @@ -301,13 +305,19 @@ typedef struct { (((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) /// 8-bit SW register as defined in radio_par_def.txt #define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \ -((uint32_t)(val) << 16)) +(((uint32_t)(val) & 0xFF) << 16)) /// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte. #define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \ (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) +#define SW_REG_MASK_OVERRIDE(cmd, field, offset, mask, val) (0x8003 | \ +((_POSITION_##cmd##_##field + (offset)) << 4) | (((uint32_t)(val) & 0xFF) << 16) | (((uint32_t)(mask) & 0xFF) << 24)) + #define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) #define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \ ((uint32_t)(length) << 16) | (1U << 30)) +#define HW16_MASK_ARRAY_OVERRIDE(addr, length) (0x20000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_MASK_ARRAY_OVERRIDE(addr, length) (0x60000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW16_MASK_VAL(mask, val) ((mask) << 16 | (val)) #define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \ ((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) #define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \ @@ -317,10 +327,15 @@ typedef struct { ((mceCfg & 1) << 6) | (((mceRomBank) & 0x0F) << 7) | \ ((rfeCfg & 1) << 11) | (((rfeRomBank) & 0x0F) << 12) | \ (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24)) -#define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x001B | ((flags & 0x07) << 9) | \ - ((((((12 * 24) << 20) / ((uint32_t) centerFreq)) + 1) / 2) << 12)) +#define HPOSC_OVERRIDE(freqOffset) (0x000B | ((freqOffset) << 16)) #define TX20_POWER_OVERRIDE(tx20Power) (0x002B | (((uint32_t) tx20Power) << 10)) #define TX_STD_POWER_OVERRIDE(txPower) (0x022B | (((uint32_t) txPower) << 10)) +#define MCE_RFE_SPLIT_OVERRIDE(mceRxCfg, mceTxCfg, rfeRxCfg, rfeTxCfg) \ + (0x003B | ((mceRxCfg) << 12) | ((mceTxCfg) << 17) | ((rfeRxCfg) << 22) | ((rfeTxCfg) << 27)) +#define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x004B | ((flags & 0x03) << 18) | \ + ((centerFreq) << 20)) +#define MOD_TYPE_OVERRIDE(modType, deviation, stepSz, flags) (0x005B | ((flags & 0x01) << 15) | \ + ((modType) << 16) | ((deviation) << 19) |((stepSz) << 30) ) #define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \ (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \ diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h index ba069f975..6dbccd655 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rf_prop_cmd.h -* Revised: 2018-05-07 15:02:01 +0200 (Mon, 07 May 2018) -* Revision: 18438 +* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018) +* Revision: 18572 * * Description: CC13x2/CC26x2 API for Proprietary mode commands * diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h index bb8c541e0..6819d8c8c 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rf_prop_mailbox.h -* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) -* Revision: 18032 +* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) +* Revision: 18171 * * Description: Definitions for proprietary mode radio interface * diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rfc.c b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rfc.c index 14db54f3a..474768506 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rfc.c +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rfc.c @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rfc.c -* Revised: 2018-01-30 17:42:58 +0100 (Tue, 30 Jan 2018) -* Revision: 51371 +* Revised: 2018-08-08 11:04:37 +0200 (Wed, 08 Aug 2018) +* Revision: 52334 * * Description: Driver for the RF Core. * @@ -61,9 +61,10 @@ #define RFCOverrideUpdate NOROM_RFCOverrideUpdate #undef RFCHwIntGetAndClear #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #undef RFCAnaDivTxOverride + #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride #endif - // Function is not complete //***************************************************************************** // @@ -144,7 +145,8 @@ RFCSynthPowerDown(void) // Reset previously patched CPE RAM to a state where it can be patched again // //***************************************************************************** -void RFCCpePatchReset(void) +void +RFCCpePatchReset(void) { // Function is not complete } @@ -174,15 +176,74 @@ RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint3 return 0xFF; } +//***************************************************************************** +// +// Function to calculate the proper override run-time for the High Gain PA. +// +//***************************************************************************** +uint32_t +RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode) +{ + uint16_t fsOnly; + uint16_t txSetting; + + switch (loDivider) + { + case 0: fsOnly = 0x0502; + break; + case 2: + fsOnly = 0x0102; + break; + case 4: + case 6: + case 12: + fsOnly = 0xF101; + break; + case 5: + case 10: + case 15: + case 30: + fsOnly = 0x1101; + break; + default: + // Error, should not occur! + fsOnly = 0; + break; + } + + if (frontEndMode == 255) + { + // Special value meaning 20 dBm PA + txSetting = (fsOnly | 0x00C0) & ~0x0400; + } + else if (frontEndMode == 0) + { + // Differential + txSetting = fsOnly | 0x0030; + } + else if (frontEndMode & 1) + { + // Single ended on RFP + txSetting = fsOnly | 0x0010; + } + else + { + // Single ended on RFN + txSetting = fsOnly | 0x0020; + } + + return ((((uint32_t) txSetting) << 16) | RFC_FE_OVERRIDE_ADDRESS); +} //***************************************************************************** // // Update the override list based on values stored in FCFG1 // //***************************************************************************** -uint8_t RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams) +uint8_t +RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams) { - // Function is not complete + // Function is left blank for compatibility reasons. return 0; } @@ -227,6 +288,8 @@ RFCHwIntGetAndClear(uint32_t ui32Mask) #define RFCOverrideUpdate NOROM_RFCOverrideUpdate #undef RFCHwIntGetAndClear #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #undef RFCAnaDivTxOverride + #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride #endif // See rfc.h for implementation diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rfc.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rfc.h index 45c8717ba..00d8f188c 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rfc.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rfc.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rfc.h -* Revised: 2018-04-25 22:52:33 +0200 (Wed, 25 Apr 2018) -* Revision: 51935 +* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) +* Revision: 52338 * * Description: Defines and prototypes for the RF Core. * @@ -63,12 +63,12 @@ extern "C" #include "../inc/hw_memmap.h" #include "../inc/hw_rfc_pwr.h" #include "../inc/hw_rfc_dbell.h" -#include "rf_common_cmd.h" -#include "rf_prop_cmd.h" -#include "rf_ble_cmd.h" #include "../inc/hw_fcfg1.h" #include "../inc/hw_adi_3_refsys.h" #include "../inc/hw_adi.h" +#include "rf_common_cmd.h" +#include "rf_prop_cmd.h" +#include "rf_ble_cmd.h" // Definition of RFTRIM container typedef struct { @@ -79,11 +79,14 @@ typedef struct { } rfTrim_t; // Definition of maximum search depth used by the RFCOverrideUpdate function -#define RFC_MAX_SEARCH_DEPTH 5 -#define RFC_PA_TYPE_ADDRESS 0x21000345 -#define RFC_PA_TYPE_MASK 0x04 -#define RFC_PA_GAIN_ADDRESS 0x2100034C -#define RFC_PA_GAIN_MASK 0x003FFFFF +#define RFC_MAX_SEARCH_DEPTH 5 +#define RFC_PA_TYPE_ADDRESS 0x21000345 +#define RFC_PA_TYPE_MASK 0x04 +#define RFC_PA_GAIN_ADDRESS 0x2100034C +#define RFC_PA_GAIN_MASK 0x003FFFFF +#define RFC_FE_MODE_ESCAPE_VALUE 0xFF +#define RFC_FE_OVERRIDE_ADDRESS 0x0703 +#define RFC_FE_OVERRIDE_MASK 0x0000FFFF //***************************************************************************** // @@ -106,6 +109,7 @@ typedef struct { #define RFCOverrideSearch NOROM_RFCOverrideSearch #define RFCOverrideUpdate NOROM_RFCOverrideUpdate #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride #endif //***************************************************************************** @@ -392,6 +396,14 @@ RFCGetPaGain(void) } +//***************************************************************************** +// +//! Function to calculate the proper override run-time for the High Gain PA. +// +//***************************************************************************** +extern uint32_t RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode); + + //***************************************************************************** // // Support for DriverLib in ROM: @@ -428,6 +440,10 @@ RFCGetPaGain(void) #undef RFCHwIntGetAndClear #define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear #endif + #ifdef ROM_RFCAnaDivTxOverride + #undef RFCAnaDivTxOverride + #define RFCAnaDivTxOverride ROM_RFCAnaDivTxOverride + #endif #endif //***************************************************************************** diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rom.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rom.h index 9dd309b6a..fc79556d7 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rom.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rom.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: rom.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 +* Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) +* Revision: 53196 * * Description: Prototypes for the ROM utility functions. * @@ -157,8 +157,8 @@ typedef struct #define HapiSelectDACVref(a) P_HARD_API->SelectDACVref(a) // Defines for input parameter to the HapiSelectCompAInput function. -// The define values can not be changed! #define COMPA_IN_NC 0x00 +// Defines used in CC13x0/CC26x0 devices #define COMPA_IN_AUXIO7 0x09 #define COMPA_IN_AUXIO6 0x0A #define COMPA_IN_AUXIO5 0x0B @@ -167,14 +167,23 @@ typedef struct #define COMPA_IN_AUXIO2 0x0E #define COMPA_IN_AUXIO1 0x0F #define COMPA_IN_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 +#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 +#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 +#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 +#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 +#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 +#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 +#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 // Defines for input parameter to the HapiSelectCompARef function. -// The define values can not be changed! #define COMPA_REF_NC 0x00 #define COMPA_REF_DCOUPL 0x01 #define COMPA_REF_VSS 0x02 #define COMPA_REF_VDDS 0x03 #define COMPA_REF_ADCVREFP 0x04 +// Defines used in CC13x0/CC26x0 devices #define COMPA_REF_AUXIO7 0x09 #define COMPA_REF_AUXIO6 0x0A #define COMPA_REF_AUXIO5 0x0B @@ -183,13 +192,22 @@ typedef struct #define COMPA_REF_AUXIO2 0x0E #define COMPA_REF_AUXIO1 0x0F #define COMPA_REF_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 +#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 +#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 +#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 +#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 +#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 +#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 +#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 // Defines for input parameter to the HapiSelectADCCompBInput function. -// The define values can not be changed! #define ADC_COMPB_IN_NC 0x00 #define ADC_COMPB_IN_DCOUPL 0x03 #define ADC_COMPB_IN_VSS 0x04 #define ADC_COMPB_IN_VDDS 0x05 +// Defines used in CC13x0/CC26x0 devices #define ADC_COMPB_IN_AUXIO7 0x09 #define ADC_COMPB_IN_AUXIO6 0x0A #define ADC_COMPB_IN_AUXIO5 0x0B @@ -198,6 +216,15 @@ typedef struct #define ADC_COMPB_IN_AUXIO2 0x0E #define ADC_COMPB_IN_AUXIO1 0x0F #define ADC_COMPB_IN_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 +#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 +#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 +#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 +#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 +#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 +#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 +#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 // Defines for input parameter to the HapiSelectDACVref function. // The define values can not be changed! @@ -243,6 +270,9 @@ typedef struct #define ROM_API_SETUP_ROM_TABLE ((uint32_t*) (ROM_API_TABLE[28])) #define ROM_API_I2S_TABLE ((uint32_t*) (ROM_API_TABLE[29])) #define ROM_API_PWR_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[30])) +#define ROM_API_AES_TABLE ((uint32_t*) (ROM_API_TABLE[31])) +#define ROM_API_PKA_TABLE ((uint32_t*) (ROM_API_TABLE[32])) +#define ROM_API_SHA2_TABLE ((uint32_t*) (ROM_API_TABLE[33])) // AON_EVENT FUNCTIONS #define ROM_AONEventMcuWakeUpSet \ @@ -668,56 +698,6 @@ typedef struct ROM_API_VIMS_TABLE[3]) -// CRYPTO FUNCTIONS -#define ROM_CRYPTOAesEcb \ - ((uint32_t (*)(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable)) \ - ROM_API_CRYPTO_TABLE[0]) - -#define ROM_CRYPTOAesEcbStatus \ - ((uint32_t (*)(void)) \ - ROM_API_CRYPTO_TABLE[1]) - -#define ROM_CRYPTOCcmAuthEncrypt \ - ((uint32_t (*)(bool bEncrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32PlainText, uint32_t ui32PlainTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable)) \ - ROM_API_CRYPTO_TABLE[3]) - -#define ROM_CRYPTOCcmAuthEncryptResultGet \ - ((uint32_t (*)(uint32_t ui32TagLength, uint32_t *pui32CcmTag)) \ - ROM_API_CRYPTO_TABLE[4]) - -#define ROM_CRYPTOCcmAuthEncryptStatus \ - ((uint32_t (*)(void)) \ - ROM_API_CRYPTO_TABLE[5]) - -#define ROM_CRYPTOCcmInvAuthDecrypt \ - ((uint32_t (*)(bool bDecrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable)) \ - ROM_API_CRYPTO_TABLE[6]) - -#define ROM_CRYPTOCcmInvAuthDecryptResultGet \ - ((uint32_t (*)(uint32_t ui32AuthLength, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32CcmTag)) \ - ROM_API_CRYPTO_TABLE[7]) - -#define ROM_CRYPTOCcmInvAuthDecryptStatus \ - ((uint32_t (*)(void)) \ - ROM_API_CRYPTO_TABLE[8]) - -#define ROM_CRYPTOAesCbc \ - ((uint32_t (*)(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength, uint32_t *pui32Nonce, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable)) \ - ROM_API_CRYPTO_TABLE[9]) - -#define ROM_CRYPTOAesCbcStatus \ - ((uint32_t (*)(void)) \ - ROM_API_CRYPTO_TABLE[10]) - -#define ROM_CRYPTODmaDisable \ - ((void (*)(uint32_t ui32Channels)) \ - ROM_API_CRYPTO_TABLE[11]) - -#define ROM_CRYPTODmaEnable \ - ((void (*)(uint32_t ui32Channels)) \ - ROM_API_CRYPTO_TABLE[12]) - - // OSC FUNCTIONS #define ROM_OSCClockSourceGet \ ((uint32_t (*)(uint32_t ui32SrcClk)) \ @@ -727,10 +707,6 @@ typedef struct ((void (*)(uint32_t ui32SrcClk, uint32_t ui32Osc)) \ ROM_API_OSC_TABLE[1]) -#define ROM_OSC_HPOSCRelativeFrequencyOffsetGet \ - ((int32_t (*)(int32_t tempDegC)) \ - ROM_API_OSC_TABLE[2]) - #define ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert \ ((int16_t (*)(int32_t HPOSC_RelFreqOffset)) \ ROM_API_OSC_TABLE[3]) @@ -807,6 +783,10 @@ typedef struct // SETUP_ROM FUNCTIONS +#define ROM_SetupAfterColdResetWakeupFromShutDownCfg1 \ + ((void (*)(uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[0]) + #define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \ ((void (*)(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)) \ ROM_API_SETUP_ROM_TABLE[1]) @@ -879,6 +859,10 @@ typedef struct ((void (*)(void)) \ ROM_API_SETUP_ROM_TABLE[18]) +#define ROM_SetupStepVddrTrimTo \ + ((void (*)(uint32_t toCode)) \ + ROM_API_SETUP_ROM_TABLE[19]) + // I2S FUNCTIONS #define ROM_I2SPointerSet \ @@ -896,6 +880,168 @@ typedef struct ROM_API_PWR_CTRL_TABLE[0]) +// AES FUNCTIONS +#define ROM_AESConfigureCCMCtrl \ + ((void (*)(uint32_t nonceLength, uint32_t macLength, bool encrypt)) \ + ROM_API_AES_TABLE[0]) + +#define ROM_AESReadFromKeyStore \ + ((uint32_t (*)(uint32_t keyStoreArea)) \ + ROM_API_AES_TABLE[1]) + +#define ROM_AESReadTag \ + ((uint32_t (*)(uint8_t *tag, uint32_t tagLength)) \ + ROM_API_AES_TABLE[2]) + +#define ROM_AESSetInitializationVector \ + ((void (*)(const uint32_t *initializationVector)) \ + ROM_API_AES_TABLE[3]) + +#define ROM_AESStartDMAOperation \ + ((void (*)(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ + ROM_API_AES_TABLE[4]) + +#define ROM_AESVerifyTag \ + ((uint32_t (*)(const uint8_t *tag, uint32_t tagLength)) \ + ROM_API_AES_TABLE[5]) + +#define ROM_AESWaitForIRQFlags \ + ((uint32_t (*)(uint32_t irqFlags)) \ + ROM_API_AES_TABLE[6]) + +#define ROM_AESWriteCCMInitializationVector \ + ((void (*)(const uint8_t *nonce, uint32_t nonceLength)) \ + ROM_API_AES_TABLE[7]) + +#define ROM_AESWriteToKeyStore \ + ((uint32_t (*)(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea)) \ + ROM_API_AES_TABLE[8]) + + +// PKA FUNCTIONS +#define ROM_PKABigNumAddGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[0]) + +#define ROM_PKABigNumCmpGetResult \ + ((uint32_t (*)(void)) \ + ROM_API_PKA_TABLE[1]) + +#define ROM_PKABigNumInvModGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[2]) + +#define ROM_PKABigNumModGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[3]) + +#define ROM_PKABigNumMultGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[4]) + +#define ROM_PKAEccAddGetResult \ + ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ + ROM_API_PKA_TABLE[5]) + +#define ROM_PKAEccAddStart \ + ((uint32_t (*)(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[6]) + +#define ROM_PKAEccMultiplyGetResult \ + ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ + ROM_API_PKA_TABLE[7]) + +#define ROM_PKAEccMultiplyStart \ + ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[8]) + +#define ROM_PKAGetOpsStatus \ + ((uint32_t (*)(void)) \ + ROM_API_PKA_TABLE[9]) + +#define ROM_PKABigNumAddStart \ + ((uint32_t (*)(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[10]) + +#define ROM_PKABigNumCmpStart \ + ((uint32_t (*)(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length)) \ + ROM_API_PKA_TABLE[11]) + +#define ROM_PKABigNumInvModStart \ + ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[12]) + +#define ROM_PKABigNumModStart \ + ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[13]) + +#define ROM_PKABigNumMultiplyStart \ + ((uint32_t (*)(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[14]) + +#define ROM_PKABigNumSubGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[15]) + +#define ROM_PKABigNumSubStart \ + ((uint32_t (*)(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[16]) + +#define ROM_PKAArrayAllZeros \ + ((bool (*)(const uint8_t *array, uint32_t arrayLength)) \ + ROM_API_PKA_TABLE[17]) + +#define ROM_PKABigNumDivideGetQuotient \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr)) \ + ROM_API_PKA_TABLE[18]) + +#define ROM_PKABigNumDivideGetRemainder \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr)) \ + ROM_API_PKA_TABLE[19]) + +#define ROM_PKABigNumDivideStart \ + ((uint32_t (*)(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr)) \ + ROM_API_PKA_TABLE[20]) + +#define ROM_PKAEccVerifyPublicKeyWeierstrassStart \ + ((uint32_t (*)(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length)) \ + ROM_API_PKA_TABLE[21]) + +#define ROM_PKAZeroOutArray \ + ((void (*)(const uint8_t *array, uint32_t arrayLength)) \ + ROM_API_PKA_TABLE[22]) + +#define ROM_PKAEccMontgomeryMultiplyStart \ + ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[23]) + + +// SHA2 FUNCTIONS +#define ROM_SHA2ComputeFinalHash \ + ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm)) \ + ROM_API_SHA2_TABLE[0]) + +#define ROM_SHA2ComputeHash \ + ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm)) \ + ROM_API_SHA2_TABLE[1]) + +#define ROM_SHA2ComputeInitialHash \ + ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength)) \ + ROM_API_SHA2_TABLE[2]) + +#define ROM_SHA2ComputeIntermediateHash \ + ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength)) \ + ROM_API_SHA2_TABLE[3]) + +#define ROM_SHA2StartDMAOperation \ + ((void (*)(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ + ROM_API_SHA2_TABLE[4]) + +#define ROM_SHA2WaitForIRQFlags \ + ((uint32_t (*)(uint32_t irqFlags)) \ + ROM_API_SHA2_TABLE[5]) + + //***************************************************************************** // diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c new file mode 100644 index 000000000..2f284cdf3 --- /dev/null +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c @@ -0,0 +1,159 @@ +/******************************************************************************* +* Filename: rom_crypto.c +* Revised: 2018-09-17 08:57:21 +0200 (Mon, 17 Sep 2018) +* Revision: 52619 +* +* Description: This is the implementation for the API to the ECC functions +* built into ROM on the CC13x2/CC26x2. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +#include +#include "rom_crypto.h" + + +////////////////////////////////////* ECC *//////////////////////////////////// +#ifdef ECC_PRIME_NIST256_CURVE +//#define TEST_NIST256 +//#define PARAM_P NIST256_p; +#define PARAM_P 0x100257d4; + +//#define PARAM_R NIST256_r; +#define PARAM_R 0x100257f8; + +//#define PARAM_A NIST256_a; +#define PARAM_A 0x1002581c; + +//#define PARAM_B NIST256_b; +#define PARAM_B 0x10025840; + +//#define PARAM_GX NIST256_Gx; +#define PARAM_GX 0x10025864; + +//#define PARAM_GY NIST256_Gy; +#define PARAM_GY 0x10025888; + +#endif + + +//***************************************************************************** +// ECC_initialize +//***************************************************************************** +void +ECC_initialize(uint32_t *pWorkzone) +{ + // Initialize curve parameters + //data_p = (uint32_t *)PARAM_P; + *((uint32_t **)0x20000138) = (uint32_t *)PARAM_P; + + //data_r = (uint32_t *)PARAM_R; + *((uint32_t **)0x2000013c) = (uint32_t *)PARAM_R; + + //data_a = (uint32_t *)PARAM_A; + *((uint32_t **)0x20000140) = (uint32_t *)PARAM_A; + + //data_b = (uint32_t *)PARAM_B; + *((uint32_t **)0x20000144) = (uint32_t *)PARAM_B; + + //data_Gx = (uint32_t *)PARAM_GX; + *((uint32_t **)0x2000012c) = (uint32_t *)PARAM_GX; + + //data_Gy = (uint32_t *)PARAM_GY; + *((uint32_t **)0x20000130) = (uint32_t *)PARAM_GY; + + // Initialize window size + //win = (uint8_t) ECC_WINDOW_SIZE; + *((uint8_t *)0x20000148) = (uint8_t) ECC_WINDOW_SIZE; + + // Initialize work zone + //workzone = (uint32_t *) pWorkzone; + *((uint32_t **)0x20000134) = (uint32_t *) pWorkzone; +} + +typedef uint8_t(*ecc_keygen_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *); +ecc_keygen_t ecc_generatekey = (ecc_keygen_t)(0x1001f94d); + +typedef uint8_t(*ecdsa_sign_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdsa_sign_t ecc_ecdsa_sign = (ecdsa_sign_t)(0x10010381); + +typedef uint8_t(*ecdsa_verify_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdsa_verify_t ecc_ecdsa_verify = (ecdsa_verify_t)(0x1000c805); + +typedef uint8_t(*ecdh_computeSharedSecret_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdh_computeSharedSecret_t ecdh_computeSharedSecret = (ecdh_computeSharedSecret_t)(0x10023485); + +//***************************************************************************** +// ECC_generateKey +//***************************************************************************** +uint8_t +ECC_generateKey(uint32_t *randString, uint32_t *privateKey, + uint32_t *publicKey_x, uint32_t *publicKey_y) +{ + return (uint8_t)ecc_generatekey((uint32_t*)randString, (uint32_t*)privateKey, + (uint32_t*)publicKey_x, (uint32_t*)publicKey_y); + +} + +//***************************************************************************** +// ECC_ECDSA_sign +//***************************************************************************** +uint8_t +ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, + uint32_t *sign1, uint32_t *sign2) +{ + return (uint8_t)ecc_ecdsa_sign((uint32_t*)secretKey, (uint32_t*)text, (uint32_t*)randString, + (uint32_t*)sign1, (uint32_t*)sign2); +} + +//***************************************************************************** +// ECC_ECDSA_verify +//***************************************************************************** +uint8_t +ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, + uint32_t *text, uint32_t *sign1, uint32_t *sign2) +{ + return (uint8_t)ecc_ecdsa_verify((uint32_t*)publicKey_x, (uint32_t*)publicKey_y, (uint32_t*)text, + (uint32_t*)sign1, (uint32_t*)sign2); +} + +//***************************************************************************** +// ECC_ECDH_computeSharedSecret +//***************************************************************************** +uint8_t +ECC_ECDH_computeSharedSecret(uint32_t *privateKey, uint32_t *publicKey_x, + uint32_t *publicKey_y, uint32_t *sharedSecret_x, + uint32_t *sharedSecret_y) +{ + return (uint8_t)ecdh_computeSharedSecret((uint32_t*)privateKey, (uint32_t*)publicKey_x, + (uint32_t*)publicKey_y, (uint32_t*)sharedSecret_x, + (uint32_t*)sharedSecret_y); +} diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h new file mode 100644 index 000000000..eecafac5a --- /dev/null +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h @@ -0,0 +1,212 @@ +/****************************************************************************** +* Filename: rom_crypto.h +* Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) +* Revision: 52624 +* +* Description: This header file is the API to the crypto functions +* built into ROM on the CC13xx/CC26xx. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup rom_crypto_api +//! @{ +// +//***************************************************************************** + +#ifndef ROM_CRYPTO_H +#define ROM_CRYPTO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +////////////////////////////////////* ECC *///////////////////////////////////// + +/* Window size, valid values are 2,3,4,5. + * Higher the value, faster the computation at the expense of memory usage. + * + * Recommended workzone size (in 4-byte words) + * Window size: 3, Workzone size: 275 + * + */ +#define ECC_WINDOW_SIZE 3 + +/* + * ECC Supported Curves, define one: + * ECC_PRIME_NIST256_CURVE + */ +#define ECC_PRIME_NIST256_CURVE + +/* + * ECC Return Status Flags. + */ +// Scalar multiplication status +#define ECC_MODULUS_EVEN 0xDC +#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 +#define ECC_MODULUS_LENGTH_ZERO 0x08 +#define ECC_MODULUS_MSW_IS_ZERO 0x30 +#define ECC_SCALAR_TOO_LONG 0x35 +#define ECC_SCALAR_LENGTH_ZERO 0x53 +#define ECC_ORDER_TOO_LONG 0xC6 +#define ECC_ORDER_LENGTH_ZERO 0x6C +#define ECC_X_COORD_TOO_LONG 0x3C +#define ECC_X_COORD_LENGTH_ZERO 0xC3 +#define ECC_Y_COORD_TOO_LONG 0x65 +#define ECC_Y_COORD_LENGTH_ZERO 0x56 +#define ECC_A_COEF_TOO_LONG 0x5C +#define ECC_A_COEF_LENGTH_ZERO 0xC5 +#define ECC_BAD_WINDOW_SIZE 0x66 +#define ECC_SCALAR_MUL_OK 0x99 + +// ECDSA and ECDH status +#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 +#define ECC_ORDER_EVEN 0x82 +#define ECC_ORDER_MSW_IS_ZERO 0x23 +#define ECC_ECC_KEY_TOO_LONG 0x25 +#define ECC_ECC_KEY_LENGTH_ZERO 0x52 +#define ECC_DIGEST_TOO_LONG 0x27 +#define ECC_DIGEST_LENGTH_ZERO 0x72 +#define ECC_ECDSA_SIGN_OK 0x32 +#define ECC_ECDSA_INVALID_SIGNATURE 0x5A +#define ECC_ECDSA_VALID_SIGNATURE 0xA5 +#define ECC_SIG_P1_TOO_LONG 0x11 +#define ECC_SIG_P1_LENGTH_ZERO 0x12 +#define ECC_SIG_P2_TOO_LONG 0x22 +#define ECC_SIG_P2_LENGTH_ZERO 0x21 + +#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK + +//***************************************************************************** +/*! + * \brief Pass pointer to ECC memory allocation to ECC engine. + * + * This function can be called again to point the ECC workzone at + * a different memory buffer. + * + * \param pWorkzone Pointer to memory allocated for computations, input. + * See description at beginning of ECC section for + * memory requirements. + * + * \return None + */ +//***************************************************************************** + extern void ECC_initialize(uint32_t *pWorkzone); + +//***************************************************************************** + /*! + * \brief Generate a key. + * + * This is used for both ECDH and ECDSA. + * + * \param randString Pointer to random string, input. + * \param privateKey Pointer to the private key, output. + * \param publicKey_x Pointer to public key X-coordinate, output. + * \param publicKey_y Pointer to public key Y-coordinate, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_generateKey(uint32_t *randString, uint32_t *privateKey, + uint32_t *publicKey_x, uint32_t *publicKey_y); + +//***************************************************************************** +/*! + * \brief Sign data. + * + * \param secretKey Pointer to the secret key, input. + * \param text Pointer to the message, input. + * \param randString Pointer to random string, input. + * \param sign1 Pointer to signature part 1, output. + * \param sign2 Pointer to signature part 2, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, + uint32_t *sign1, uint32_t *sign2); + +//***************************************************************************** +/*! + * \brief Verify signature. + * + * \param publicKey_x Pointer to public key X-coordinate, input. + * \param publicKey_y Pointer to public key Y-coordinate, input. + * \param text Pointer to message data, input. + * \param sign1 Pointer to signature part 1, input. + * \param sign2 Pointer to signature part 2, input. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, + uint32_t *text, uint32_t *sign1, uint32_t *sign2); + +//***************************************************************************** +/*! + * \brief Compute the shared secret. + * + * \param privateKey Pointer to private key, input. + * \param publicKey_x Pointer to public key X-coordinate, input. + * \param publicKey_y Pointer to public key Y-coordinate, input. + * \param sharedSecret_x Pointer to shared secret X-coordinate, output. + * \param sharedSecret_y Pointer to shared secret Y-coordinate, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t *privateKey, + uint32_t *publicKey_x, + uint32_t *publicKey_y, + uint32_t *sharedSecret_x, + uint32_t *sharedSecret_y); + + +#ifdef __cplusplus +} +#endif + +#endif /* ROM_CRYPTO_H */ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup.c b/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup.c index 8752ff3a3..1f438bed0 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup.c +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup.c @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: setup.c -* Revised: 2018-04-05 13:46:03 +0200 (Thu, 05 Apr 2018) -* Revision: 51853 +* Revised: 2018-11-06 15:08:57 +0100 (Tue, 06 Nov 2018) +* Revision: 53239 * * Description: Setup file for CC13xx/CC26xx devices. * @@ -53,6 +53,7 @@ #include "../inc/hw_aon_pmctl.h" #include "../inc/hw_aon_rtc.h" #include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_ddi.h" #include "../inc/hw_ccfg.h" #include "../inc/hw_fcfg1.h" #include "../inc/hw_flash.h" @@ -121,9 +122,9 @@ SetupTrimDevice(void) ui32Fcfg1Revision = 0; } - // This driverlib version and setup file is for the CC13x2, CC26x2 chips. + // This driverlib version and setup file is for the CC13x2, CC26x2 PG2.0 or later chips. // Halt if violated - ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated(); + ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated(); // Enable standby in flash bank HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; @@ -227,58 +228,6 @@ TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ) // Currently no specific trim for Powerdown } -// Special shadow register trim propagation on first batch of devices - -static void -Step_RCOSCHF_CTRIM( uint32_t toCode ) -{ - uint32_t currentRcoscHfCtlReg ; - uint32_t currentTrim ; - - currentRcoscHfCtlReg = HWREGH( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_RCOSCHFCTL ); - currentTrim = ((( currentRcoscHfCtlReg & DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M ) >> - DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S ) ^ 0xC0 ); - - while ( toCode != currentTrim ) { - HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) - - if ( toCode > currentTrim ) currentTrim++; - else currentTrim--; - - HWREGH( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_RCOSCHFCTL ) = - ( currentRcoscHfCtlReg & ~DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M ) | - (( currentTrim ^ 0xC0 ) << DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S ); - } -} - -static void -Step_VBG( int32_t targetSigned ) -{ - // VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG) - uint32_t refSysCtl3Reg ; - int32_t currentSigned ; - - do { - refSysCtl3Reg = HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ); - currentSigned = - (((int32_t)( refSysCtl3Reg << ( 32 - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S ))) - >> ( 32 - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W )); - - HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) - - if ( targetSigned != currentSigned ) { - if ( targetSigned > currentSigned ) currentSigned++; - else currentSigned--; - - HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) = - ( refSysCtl3Reg & ~( ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN | ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M )) | - ((((uint32_t)currentSigned) << ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S ) & ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M ); - - HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; // Bit set by doing a read modify write - } - } while ( targetSigned != currentSigned ); -} - //***************************************************************************** // //! \brief Trims to be applied when coming from SHUTDOWN (also called when @@ -304,7 +253,16 @@ TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision) } - // TBD-Agama - Temporarily removed for Agama + // TBD - Temporarily removed for CC13x2 / CC26x2 + + // Force DCDC to use RCOSC before starting up XOSC. + // Clock loss detector does not use XOSC until SCLK_HF actually switches + // and thus DCDC is not protected from clock loss on XOSC in that time frame. + // The force must be released when the switch to XOSC has happened. This is done + // in OSCHfSourceSwitch(). + HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16); + // Dummy read to ensure that the write has propagated + HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); // read the MODE_CONF register in CCFG ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); @@ -314,6 +272,14 @@ TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision) // -Configure DCDC. SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg ); + // Addition to the CC1352 boost mode for HWREV >= 2.0 + // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode + if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && + (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) + { + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL3 ) = ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST ; + } + // Second part of trim done after cold reset and wakeup from shutdown: // -Configure XOSC. #if ( CCFG_BASE == CCFG_BASE_DEFAULT ) @@ -322,106 +288,6 @@ TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision) NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); #endif - // Special shadow register trim propagation on first batch of devices - { - uint32_t ui32EfuseData ; - uint32_t orgResetCtl ; - - // Get VTRIM_COARSE and VTRIM_DIG from EFUSE shadow register OSC_BIAS_LDO_TRIM - ui32EfuseData = HWREG( FCFG1_BASE + FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM ); - - Step_RCOSCHF_CTRIM(( ui32EfuseData & - FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M ) >> - FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S ) ; - - // Write to register SOCLDO_0_1 (addr offset 3) bits[7:4] (VTRIM_COARSE) and - // bits[3:0] (VTRIM_DIG) in ADI_2_REFSYS. Direct write can be used since - // all register bit fields are trimmed. - HWREGB(ADI2_BASE + ADI_O_DIR + ADI_2_REFSYS_O_SOCLDOCTL1) = - ((((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M) >> - FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S) << - ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S) | - - (((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M) >> - FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S) << - ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S)); - - // Write to register CTLSOCREFSYS0 (addr offset 0) bits[4:0] (TRIMIREF) in - // ADI_2_REFSYS. Avoid using masked write access since bit field spans - // nibble boundary. Direct write can be used since this is the only defined - // bit field in this register. - HWREGB(ADI2_BASE + ADI_O_DIR + ADI_2_REFSYS_O_REFSYSCTL0) = - (((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M) >> - FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S) << - ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S); - - // Write to register CTLSOCREFSYS2 (addr offset 4) bits[7:4] (TRIMMAG) in - // ADI_3_REFSYS - HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL2 << 1)) = - (ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M << 8) | - (((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M) >> - FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S) << - ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S); - - // Get TRIMBOD_EXTMODE or TRIMBOD_INTMODE from EFUSE shadow register in FCFG1 - ui32EfuseData = HWREG( FCFG1_BASE + FCFG1_O_SHDW_ANA_TRIM ); - - orgResetCtl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ); - HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = - ( orgResetCtl & ~( AON_PMCTL_RESETCTL_CLK_LOSS_EN | - AON_PMCTL_RESETCTL_VDD_LOSS_EN | - AON_PMCTL_RESETCTL_VDDR_LOSS_EN | - AON_PMCTL_RESETCTL_VDDS_LOSS_EN )); - HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for xxx_LOSS_EN setting to propagate - - // The VDDS_BOD trim and the VDDR trim is already stepped up to max/HH if "CC1352 boost mode" is requested. - // See function SetupAfterColdResetWakeupFromShutDownCfg1() in setup_rom.c for details. - if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) != 0 ) || - (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) == 0 ) ) - { - if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & - AON_PMCTL_PWRCTL_EXT_REG_MODE) - { - // Apply VDDS BOD trim value - // Write to register CTLSOCREFSYS1 (addr offset 3) bit[7:3] (TRIMBOD) - // in ADI_3_REFSYS - HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL1 << 1)) = - (ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8) | - (((ui32EfuseData & FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M) >> - FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S) << - ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S); - } - else - { - // Apply VDDS BOD trim value - // Write to register CTLSOCREFSYS1 (addr offset 3) bit[7:3] (TRIMBOD) - // in ADI_3_REFSYS - HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL1 << 1)) = - (ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8) | - (((ui32EfuseData & FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M) >> - FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S) << - ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S); - } - // Load the new VDDS_BOD setting - HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) &= ~ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; // Bit clear by doing a read modify write - HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; // Bit set by doing a read modify write - - SetupStepVddrTrimTo(( ui32EfuseData & - FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M ) >> - FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S ) ; - } - - // VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG) - Step_VBG(((int32_t)( ui32EfuseData << ( 32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S ))) - >> ( 32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W )); - - // Wait two more LF edges before restoring xxx_LOSS_EN settings - HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) - HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) - HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = orgResetCtl; - HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for xxx_LOSS_EN setting to propagate - } - { uint32_t trimReg ; uint32_t ui32TrimValue ; @@ -432,11 +298,19 @@ TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision) FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S ) ; HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_LPMBIAS ) = (( ui32TrimValue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S ) & ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M ) ; - //--- Set fixed LPM_BIAS values --- LPM_BIAS_BACKUP_EN = 1 and LPM_BIAS_WIDTH_TRIM = 3 - HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN; - HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3 - (( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8 ) | // Set mask (bits to be written) in [15:8] - ( 3 << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S ) ); // Set value (in correct bit pos) in [7:0] + // Set LPM_BIAS_BACKUP_EN according to FCFG1 configuration + if ( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN ) { + HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN; + } else { + HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN; + } + // Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration + { + uint32_t widthTrim = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M ) >> FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S ); + HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3 + (( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8 ) | // Set mask (bits to be written) in [15:8] + ( widthTrim << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S ) ); // Set value (in correct bit pos) in [7:0] + } } // Third part of trim done after cold reset and wakeup from shutdown: diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup.h index d032d71d7..c2093d7fa 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: setup.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 +* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) +* Revision: 52993 * * Description: Prototypes and defines for the setup API. * @@ -83,11 +83,24 @@ extern "C" //***************************************************************************** // -//! \brief Performs the necessary trim of the device which is not done in boot code. +//! \brief Performs the necessary trim of the device which is not done in ROM boot code. //! -//! This function should only execute coming from ROM boot. The current -//! implementation does not take soft reset into account. However, it does no -//! damage to execute it again. It only consumes time. +//! This function should only execute coming from ROM boot. +//! +//! The following is handled by this function: +//! - Checks if the driverlib variant used by the application is supported by the +//! device. Execution is halted in case of unsupported driverlib variant. +//! - Configures VIMS cache mode based on setting in CCFG. +//! - Configures functionalities like DCDC and XOSC dependent on startup modes like +//! cold reset, wakeup from shutdown and wakeup from from powerdown. +//! - Configures VIMS power domain control. +//! - Configures optimal wait time for flash FSM in cases where flash pump wakes up from sleep. +//! +//! \note The current implementation does not take soft reset into account. However, +//! it does no damage to execute it again. It only consumes time. +//! +//! \note This function is called by the compiler specific device startup codes +//! that are integrated in the SimpleLink SDKs for CC13xx/CC26XX devices. //! //! \return None // diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h index dcc0751ca..e06ba2931 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: setup_rom.h -* Revised: 2017-09-04 19:00:53 +0200 (Mon, 04 Sep 2017) -* Revision: 49686 +* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) +* Revision: 52993 * * Description: Prototypes and defines for the setup API. * @@ -102,9 +102,19 @@ extern "C" //***************************************************************************** // -//! \brief First part of configuration required when waking up from shutdown. +//! \brief First part of configuration required after cold reset and when waking up from shutdown. //! -//! \param ccfg_ModeConfReg +//! Configures the following based on settings in CCFG (Customer Configuration area: +//! - Boost mode for CC13xx devices +//! - Minimal VDDR voltage threshold used during sleep mode +//! - DCDC functionality: +//! - Selects if DCDC or GLDO regulator will be used for VDDR in active mode +//! - Selects if DCDC or GLDO regulator will be used for VDDR in sleep mode +//! +//! In addition the battery monitor low limit for internal regulator mode is set +//! to a hard coded value. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register //! //! \return None // @@ -113,10 +123,14 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg //***************************************************************************** // -//! \brief Second part of configuration required when waking up from shutdown. +//! \brief Second part of configuration required after cold reset and when waking up from shutdown. //! -//! \param ui32Fcfg1Revision -//! \param ccfg_ModeConfReg +//! Configures and trims functionalites required for use of XOSC_HF. +//! The configurations and trimmings are based on settings in FCFG1 (Factory +//! Configuration area) and partly on \c ccfg_ModeConfReg. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register //! //! \return None // @@ -125,9 +139,18 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revisio //***************************************************************************** // -//! \brief Third part of configuration required when waking up from shutdown. +//! \brief Third part of configuration required after cold reset and when waking up from shutdown. //! -//! \param ccfg_ModeConfReg +//! Configures the following: +//! - XOSC source selection based on \c ccfg_ModeConfReg. If HPOSC is selected on a +//! HPOSC device the oscillator is configured based on settings in FCFG1 (Factory +//! Configuration area). +//! - Clock loss detection is disabled. Will be re-enabled by TIRTOS power driver. +//! - Duration of the XOSC_HF fast startup mode based on FCFG1 setting. +//! - SCLK_LF based on \c ccfg_ModeConfReg. +//! - Output voltage of ADC fixed reference based on FCFG1 setting. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register //! //! \return None // @@ -138,7 +161,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg // //! \brief Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting. //! -//! \param ui32Fcfg1Revision +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register //! //! \return Returns the trim value from FCFG1. // @@ -149,7 +172,7 @@ extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); // //! \brief Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting. //! -//! \param ui32Fcfg1Revision +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register //! //! \return Returns the trim value from FCFG1. // @@ -160,7 +183,7 @@ extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); // //! \brief Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG. //! -//! \param ui32Fcfg1Revision +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register //! //! \return Returns the trim value. // @@ -189,7 +212,7 @@ extern uint32_t SetupGetTrimForAmpcompTh2( void ); // //! \brief Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG. //! -//! \param ccfg_ModeConfReg +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register //! //! \return Returns the trim value. // @@ -200,7 +223,7 @@ extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); // //! \brief Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting. //! -//! \param ui32Fcfg1Revision +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register //! //! \return Returns the trim value from FCFG1. // @@ -211,7 +234,7 @@ extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Rev // //! \brief Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG. //! -//! \param ui32Fcfg1Revision +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register //! //! \return Returns the trim value. // @@ -222,7 +245,7 @@ extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); // //! \brief Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM. //! -//! \param ui32Fcfg1Revision +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register //! //! \return Returns the trim value from FCFG1. // @@ -243,7 +266,7 @@ extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); // //! \brief Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG. //! -//! \param ui32Fcfg1Revision +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register //! //! \return Returns the trim value. // @@ -274,7 +297,7 @@ extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); //! \brief Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet //! spanning bits [5:0] in the returned value. //! -//! \param ui32Fcfg1Revision +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register //! //! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet. // diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c b/third_party/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c index 3cfefa8c6..1dd35f40e 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: sys_ctrl.c -* Revised: 2017-11-07 11:56:04 +0100 (Tue, 07 Nov 2017) -* Revision: 50203 +* Revised: 2018-06-26 15:19:11 +0200 (Tue, 26 Jun 2018) +* Revision: 52220 * * Description: Driver for the System Control. * @@ -199,13 +199,8 @@ void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode // adaptive recharge mode and fixed parameter values if(rechargeMode == SYSCTRL_PREFERRED_RECHARGE_MODE) { - if (( HWREG( FCFG1_BASE + FCFG1_O_TFW_FT ) % 10000 ) >= 683 ) { - // Enable the Recharge Comparator - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = AON_PMCTL_RECHARGECFG_MODE_COMPARATOR; - } else { - // Set conservative recharge mode - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = 0x80A4E708; - } + // Enable the Recharge Comparator + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = AON_PMCTL_RECHARGECFG_MODE_COMPARATOR; } else { diff --git a/third_party/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h b/third_party/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h index 4742ba8d1..6dbe83184 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h +++ b/third_party/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: sys_ctrl.h -* Revised: 2017-11-07 11:56:04 +0100 (Tue, 07 Nov 2017) -* Revision: 50203 +* Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) +* Revision: 52634 * * Description: Defines and prototypes for the System Controller. * diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h index 0d4602506..68d37bde9 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_adi_2_refsys_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h index d95f3058c..2315d8d55 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_adi_3_refsys_h -* Revised: 2017-02-18 14:22:30 +0100 (Sat, 18 Feb 2017) -* Revision: 48483 +* Revised: 2018-09-27 10:33:21 +0200 (Thu, 27 Sep 2018) +* Revision: 52772 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. @@ -67,7 +67,7 @@ // DCDC Control 2 #define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 -// DCDC Control 3 +// Internal #define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 // Internal @@ -451,6 +451,22 @@ // Register: ADI_3_REFSYS_O_DCDCCTL3 // //***************************************************************************** +// Field: [1:0] VDDR_BOOST_COMP +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BOOST_P1 Internal. Only to be used through TI provided API. +// BOOST Internal. Only to be used through TI provided API. +// BOOST_N1 Internal. Only to be used through TI provided API. +// DEFAULT Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_W 2 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_M 0x00000003 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_S 0 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_P1 0x00000003 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST 0x00000002 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_N1 0x00000001 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_DEFAULT 0x00000000 + //***************************************************************************** // // Register: ADI_3_REFSYS_O_DCDCCTL4 diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h index 237df6496..45fdfc31b 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_adi_4_aux_h -* Revised: 2017-05-04 11:51:48 +0200 (Thu, 04 May 2017) -* Revision: 48895 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. @@ -76,6 +76,9 @@ // ADC Reference 1 #define ADI_4_AUX_O_ADCREF1 0x0000000B +// Internal +#define ADI_4_AUX_O_LPMBIAS 0x0000000E + //***************************************************************************** // // Register: ADI_4_AUX_O_MUX0 @@ -272,6 +275,13 @@ #define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 #define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 +// Field: [5:3] LPM_BIAS_WIDTH_TRIM +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_W 3 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3 + // Field: [2] COMPB_EN // // COMPB enable @@ -421,9 +431,14 @@ //***************************************************************************** // Field: [6] REF_ON_IDLE // -// Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE = 0. +// Enable ADCREF in IDLE state. // -// Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us sampling time) +// 0: Disabled in IDLE state +// 1: Enabled in IDLE state +// +// Keep ADCREF enabled when ADC0.SMPL_MODE = 0. +// Recommendation: Enable ADCREF always when ADC0.SMPL_CYCLE_EXP is less than +// 0x6 (21.3us sampling time). #define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 #define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 #define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 @@ -482,5 +497,17 @@ #define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F #define ADI_4_AUX_ADCREF1_VTRIM_S 0 +//***************************************************************************** +// +// Register: ADI_4_AUX_O_LPMBIAS +// +//***************************************************************************** +// Field: [5:0] LPM_TRIM_IOUT +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_W 6 +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0 + #endif // __ADI_4_AUX__ diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h index c482c44cc..ded130e50 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aon_batmon_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h index 05e86ed53..81c93f387 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aon_event_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h index 11c2d5c1c..d2e6d1f4f 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aon_ioc_h -* Revised: 2017-05-18 09:01:49 +0200 (Thu, 18 May 2017) -* Revision: 49008 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h index a057f9693..e97121777 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aon_pmctl_h -* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018) -* Revision: 51887 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h index 8bdb43091..1718015db 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aon_rtc_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h index 7c725d795..a66a0d5d6 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_aiodio_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h index c14c12fca..8b08db3d2 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_anaif_h -* Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017) -* Revision: 49733 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h index 2dbd185a6..b92db6443 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_evctl_h -* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018) -* Revision: 51887 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h index b78856b56..83dea0bb8 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_mac_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h index 7a627e923..6a20b9156 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_ram_h -* Revised: 2017-05-06 20:38:09 +0200 (Sat, 06 May 2017) -* Revision: 48921 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h index 717133003..39f175867 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_sce_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h index a49d041d0..0bee0c53b 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_smph_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h index 1dd7aa6ef..c2f354da7 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_spim_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h index 970c78a68..a3de3f94f 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_sysif_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h index 17213e3b5..002d740a5 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_tdc_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h index 8c5c5621e..288a8fd82 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_timer01_h -* Revised: 2017-05-22 18:50:33 +0200 (Mon, 22 May 2017) -* Revision: 49040 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h index ce327a28e..aa7423f4d 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_aux_timer2_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h index b26c525b6..568eca055 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_ccfg_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-10-19 08:48:09 +0200 (Fri, 19 Oct 2018) +* Revision: 52957 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. @@ -415,9 +415,7 @@ // Field: [19:18] XOSC_FREQ // -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. +// Selects high precision HF oscillator (activated when using the radio). // ENUMs: // 24M 24 MHz XOSC_HF // 48M 48 MHz XOSC_HF diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h index 172c48f6a..59fec5862 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_ccfg_simple_struct_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h index 1b68415c2..19f70e087 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h @@ -195,7 +195,7 @@ extern "C" #define CC_GET_CHIP_FAMILY 0x26 #define CC_GET_CHIP_OPTION 0x3 -#define CC_GET_CHIP_HWREV 0x10 +#define CC_GET_CHIP_HWREV 0x20 #ifdef CC_CHIP_ID /* Define chip package only if specified */ diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h index bc991e4b3..fa62b893f 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_cpu_dwt_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h index 2355dfb23..efc475c58 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_cpu_fpb_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h index 6fd74b1c4..430c0b0df 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_cpu_itm_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h index 8744cbb00..e9e9e0606 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_cpu_rom_table_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h index b173612d1..2906f4432 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_cpu_scs_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h index dc0cd2071..29e314e16 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_cpu_tiprop_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h index 04c1933dc..43c7c8e80 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_cpu_tpiu_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h index 04984d1a4..2952afda1 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_crypto_h -* Revised: 2017-05-04 11:51:48 +0200 (Thu, 04 May 2017) -* Revision: 48895 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h index 36d5c09fe..ee49e2709 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_ddi_0_osc_h -* Revised: 2017-05-04 11:51:48 +0200 (Thu, 04 May 2017) -* Revision: 48895 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_event.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_event.h index de107b545..754774f01 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_event.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_event.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_event_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h index cf8607cd8..cd6cb570d 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_fcfg1_h -* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018) -* Revision: 51887 +* Revised: 2018-11-06 14:08:24 +0100 (Tue, 06 Nov 2018) +* Revision: 53237 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. @@ -49,6 +49,21 @@ // Internal #define FCFG1_O_MISC_CONF_2 0x000000A4 +// Internal +#define FCFG1_O_HPOSC_MEAS_5 0x000000B0 + +// Internal +#define FCFG1_O_HPOSC_MEAS_4 0x000000B4 + +// Internal +#define FCFG1_O_HPOSC_MEAS_3 0x000000B8 + +// Internal +#define FCFG1_O_HPOSC_MEAS_2 0x000000BC + +// Internal +#define FCFG1_O_HPOSC_MEAS_1 0x000000C0 + // Internal #define FCFG1_O_CONFIG_CC26_FE 0x000000C4 @@ -226,40 +241,16 @@ // Internal #define FCFG1_O_MISC_OTP_DATA_1 0x00000398 -// Power Down Current Control 20C -#define FCFG1_O_PWD_CURR_20C 0x0000039C - -// Power Down Current Control 35C -#define FCFG1_O_PWD_CURR_35C 0x000003A0 - -// Power Down Current Control 50C -#define FCFG1_O_PWD_CURR_50C 0x000003A4 - -// Power Down Current Control 65C -#define FCFG1_O_PWD_CURR_65C 0x000003A8 - -// Power Down Current Control 80C -#define FCFG1_O_PWD_CURR_80C 0x000003AC - -// Power Down Current Control 95C -#define FCFG1_O_PWD_CURR_95C 0x000003B0 - -// Power Down Current Control 110C -#define FCFG1_O_PWD_CURR_110C 0x000003B4 - -// Power Down Current Control 125C -#define FCFG1_O_PWD_CURR_125C 0x000003B8 - -// Shadow of EFUSE:DIE_ID_0 +// Shadow of EFUSE:DIE_ID_0 register #define FCFG1_O_SHDW_DIE_ID_0 0x000003D0 -// Shadow of EFUSE:DIE_ID_1 +// Shadow of EFUSE:DIE_ID_1 register #define FCFG1_O_SHDW_DIE_ID_1 0x000003D4 -// Shadow of EFUSE:DIE_ID_2 +// Shadow of EFUSE:DIE_ID_2 register #define FCFG1_O_SHDW_DIE_ID_2 0x000003D8 -// Shadow of EFUSE:DIE_ID_3 +// Shadow of EFUSE:DIE_ID_3 register #define FCFG1_O_SHDW_DIE_ID_3 0x000003DC // Internal @@ -316,6 +307,136 @@ #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF #define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_5 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_W 16 +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_S 16 + +// Field: [15:8] HPOSC_T5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_W 8 +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_S 8 + +// Field: [7:0] HPOSC_DT5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_W 8 +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_M 0x000000FF +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_4 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_W 16 +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_S 16 + +// Field: [15:8] HPOSC_T4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_W 8 +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_S 8 + +// Field: [7:0] HPOSC_DT4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_W 8 +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_M 0x000000FF +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_3 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_W 16 +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_S 16 + +// Field: [15:8] HPOSC_T3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_W 8 +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_S 8 + +// Field: [7:0] HPOSC_DT3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_W 8 +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_M 0x000000FF +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_2 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_W 16 +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_S 16 + +// Field: [15:8] HPOSC_T2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_W 8 +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_S 8 + +// Field: [7:0] HPOSC_DT2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_W 8 +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_M 0x000000FF +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_1 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_W 16 +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_S 16 + +// Field: [15:8] HPOSC_T1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_W 8 +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_S 8 + +// Field: [7:0] HPOSC_DT1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_W 8 +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_M 0x000000FF +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_S 0 + //***************************************************************************** // // Register: FCFG1_O_CONFIG_CC26_FE @@ -1360,11 +1481,7 @@ //***************************************************************************** // Field: [31:28] PG_REV // -// Field used to distinguish revisions of the device. -// -// 0: Silicon revision 1.0 -// 1: Silicon revision 1.01 -// 2: Silicon revision 1.1 +// Field used to distinguish revisions of the device #define FCFG1_USER_ID_PG_REV_W 4 #define FCFG1_USER_ID_PG_REV_M 0xF0000000 #define FCFG1_USER_ID_PG_REV_S 28 @@ -1879,10 +1996,6 @@ // Field: [31:28] PG_REV // // Field used to distinguish revisions of the device. -// -// 0: Silicon revision 1.0 -// 1: Silicon revision 1.01 -// 2: Silicon revision 1.1 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 @@ -1953,15 +2066,6 @@ #define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 #define FCFG1_MISC_OTP_DATA_PER_E_S 12 -// Field: [7:0] TEST_PROGRAM_REV -// -// The revision of the test program used in the production process when FCFG1 -// was programmed. -// Value migth change without warning. -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8 -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0 - //***************************************************************************** // // Register: FCFG1_O_IOCONF @@ -2488,278 +2592,6 @@ #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F #define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_20C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_20C_BASELINE_W 8 -#define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_20C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_35C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_35C_BASELINE_W 8 -#define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_35C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_50C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_50C_BASELINE_W 8 -#define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_50C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_65C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_65C_BASELINE_W 8 -#define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_65C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_80C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_80C_BASELINE_W 8 -#define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_80C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_95C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_95C_BASELINE_W 8 -#define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_95C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_110C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_110C_BASELINE_W 8 -#define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_110C_BASELINE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_PWD_CURR_125C -// -//***************************************************************************** -// Field: [31:24] DELTA_CACHE_REF -// -// Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24 - -// Field: [23:16] DELTA_RFMEM_RET -// -// Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16 - -// Field: [15:8] DELTA_XOSC_LPM -// -// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power -// mode -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8 - -// Field: [7:0] BASELINE -// -// Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_125C_BASELINE_W 8 -#define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_125C_BASELINE_S 0 - //***************************************************************************** // // Register: FCFG1_O_SHDW_DIE_ID_0 @@ -2860,6 +2692,29 @@ // Register: FCFG1_O_SHDW_ANA_TRIM // //***************************************************************************** +// Field: [30] ALT_VDDR_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM 0x40000000 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_BITN 30 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_M 0x40000000 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_S 30 + +// Field: [29] DET_LOGIC_DIS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS 0x20000000 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_BITN 29 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_M 0x20000000 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_S 29 + +// Field: [28:27] BOD_BANDGAP_TRIM_CNF_EXT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_M 0x18000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_S 27 + // Field: [26:25] BOD_BANDGAP_TRIM_CNF // // Internal. Only to be used through TI provided API. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_flash.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_flash.h index 6815a3d87..d7e03e795 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_flash.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_flash.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_flash_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h index a5bfbbf9b..8ec4bfb7b 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_gpio_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h index e21892a0c..1042a0f12 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_gpram_h -* Revised: 2017-05-06 20:38:09 +0200 (Sat, 06 May 2017) -* Revision: 48921 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h index bf70bf343..5cf056ea5 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_gpt_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h index 31842e275..7408570c5 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_i2c_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h index 9886e95a6..c7ed79aa2 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_i2s_h -* Revised: 2017-11-02 10:21:28 +0100 (Thu, 02 Nov 2017) -* Revision: 50141 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ints.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ints.h index b5d10df81..940695eca 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ints.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ints.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_ints_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h index dc02fb9e0..9e7c982a8 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_ioc_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h index e634c600e..e8a9e8bae 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_memmap_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka.h index f8039bb21..377f08e10 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_pka_h -* Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017) -* Revision: 49733 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h index e36409a39..159ea4c3b 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_pka_int_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h index a19b23654..3a9c12cd0 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_pka_ram_h -* Revised: 2017-05-06 20:38:09 +0200 (Sat, 06 May 2017) -* Revision: 48921 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h index eaf43ab1c..1aa7f034e 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_prcm_h -* Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017) -* Revision: 49733 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h index c586325f0..612d3ec24 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_rfc_dbell_h -* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018) -* Revision: 51887 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h index d6313bcdf..355626efd 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_rfc_pwr_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h index f3f6f1dcc..4f68d8d27 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_rfc_rat_h -* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018) -* Revision: 51887 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h index c410c728f..0159b94b7 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_rfc_ullram_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_smph.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_smph.h index 06ee2f730..7bbdcd610 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_smph.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_smph.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_smph_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h index c57de092e..80d642200 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_sram_mmr_h -* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018) -* Revision: 51887 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h index 525f64ce2..403d6620a 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_ssi_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_trng.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_trng.h index f02cb2bcd..44d4eb26d 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_trng.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_trng.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_trng_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_uart.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_uart.h index 3f3f9e056..b35541fb8 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_uart.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_uart.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_uart_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_udma.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_udma.h index e1aa1d9e2..2a4b161e3 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_udma.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_udma.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_udma_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_vims.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_vims.h index 70420b50f..e3de5ea6e 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_vims.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_vims.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_vims_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h index 5125b9172..2c826ea81 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h +++ b/third_party/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h @@ -1,7 +1,7 @@ /****************************************************************************** * Filename: hw_wdt_h -* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017) -* Revision: 48190 +* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) +* Revision: 51990 * * Copyright (c) 2015 - 2017, Texas Instruments Incorporated * All rights reserved. diff --git a/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.cmd b/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.cmd index fef203bb5..4362abdce 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.cmd +++ b/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.cmd @@ -1,9 +1,9 @@ //***************************************************************************** //! @file cc26x2r1f.cmd -//! @brief CC26x2R1F linker file for Code Composer Studio. +//! @brief CC26x2R1F rev2 linker file for Code Composer Studio. //! -//! Revised $Date: 2017-03-28 15:32:09 +0200 (ti, 28 mar 2017) $ -//! Revision $Revision: 17730 $ +//! Revised $Date$ +//! Revision $Revision$ // // This file is auto-generated. // diff --git a/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.icf b/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.icf index 181aa27f4..ef2d9888f 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.icf +++ b/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.icf @@ -1,9 +1,9 @@ //***************************************************************************** //! @file cc26x2r1f.icf -//! @brief CC26x2R1F linker file for IAR EWARM. +//! @brief CC26x2R1F rev2 linker file for IAR EWARM. //! -//! Revised $Date: 2017-02-06 11:55:41 +0100 (ma, 06 feb 2017) $ -//! Revision $Revision: 17642 $ +//! Revised $Date$ +//! Revision $Revision$ // // This file is auto-generated. // diff --git a/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.lds b/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.lds index c7523613b..2d36722e6 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.lds +++ b/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.lds @@ -1,9 +1,9 @@ /* @file cc26x2r1f.lds - @brief CC26x2R1F linker configuration file for GNU compiler. + @brief CC26x2R1F rev2 linker configuration file for GNU compiler. - Revised $Date: 2017-08-07 11:45:00 +0200 (ma, 07 aug 2017) $ - Revision $Revision: 17871 $ + Revised $Date$ + Revision $Revision$ This file is auto-generated. diff --git a/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.sct b/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.sct index b248f3fa5..f0ae96ed15 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.sct +++ b/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f.sct @@ -1,9 +1,9 @@ ; /**************************************************************************** ; * @file cc26x2r1f.sct -; * @brief CC26x2R1F scatter loading file for ARM linker. +; * @brief CC26x2R1F rev2 scatter loading file for ARM linker. ; * -; * Revised $Date: 2017-02-06 11:55:41 +0100 (ma, 06 feb 2017) $ -; * Revision $Revision: 17642 $ +; * Revised $Date$ +; * Revision $Revision$ ; * ; * This file is auto-generated. ; * diff --git a/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f_ram.icf b/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f_ram.icf deleted file mode 100644 index 742819ec1..000000000 --- a/third_party/ti/devices/cc13x2_cc26x2/linker_files/cc26x2r1f_ram.icf +++ /dev/null @@ -1,143 +0,0 @@ -//***************************************************************************** -//! @file cc26x2r1f.icf -//! @brief CC26x2R1F linker file for IAR EWARM. -//! -//! Revised $Date: 2017-02-06 11:55:41 +0100 (ma, 06 feb 2017) $ -//! Revision $Revision: 17642 $ -// -// This file is auto-generated. -// -// Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ -// -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//****************************************************************************/ - - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00057FFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20013FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x1000; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __GPRAM_START__ = 0x11000000; -define symbol __GPRAM_END__ = 0x11001FFF; - -// -// Define a memory region that covers the entire 4 GB addressable space of the -// processor. -// -define memory mem with size = 4G; - -// -// Define a region for the on-chip flash. -// -define region FLASH_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -// -// Define a region for the on-chip SRAM. -// -define region SRAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -// -// Place the interrupt vectors at the start of flash. -// -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -keep { section .intvec }; - -// -// Place the CCFG area at the end of flash -// -//place at end of FLASH_region { readonly section .ccfg }; -//keep { section .ccfg }; - -// -// Place remaining 'read only' in RAM -// -place in SRAM_region { readonly }; - - -// -// Place .vtable_ram in start of RAM -// -//place at start of SRAM_region { section .vtable_ram }; - -// -// Define CSTACK block to contain .stack section. This enables the IAR IDE -// to properly show the stack content during debug. Place stack at end of -// retention RAM, do not initialize (initializing the stack will destroy the -// return address from the initialization code, causing the processor to branch -// to zero and fault) -// -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { section .stack }; -place at end of SRAM_region { block CSTACK }; -do not initialize { section .stack, section .noinit}; - -// -// Export stack top symbol. Used by startup file. -// -define exported symbol STACK_TOP = __ICFEDIT_region_RAM_end__ + 1; - -// -// Define a block for the heap. The size should be set to something other -// than zero if things in the C library that require the heap are used. -// -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -place in SRAM_region { block HEAP }; - -// -// Place all read/write items into RAM. -// -place in SRAM_region { readwrite }; -//initialize by copy { readwrite }; - -// -// The USE_TIRTOS_ROM symbol is defined internally in the build flow (using -// --config_def USE_TIRTOS_ROM=1) for TI-RTOS applications whose app.cfg file -// specifies to use the ROM. -// -if (isdefinedsymbol(USE_TIRTOS_ROM)) { - include "TIRTOS_ROM.icf"; -} - -// -// Define a region for the on-chip GPRAM/cache. -// Application can use this region as RAM if cache is disabled in the CCFG -// (DEFAULT_CCFG_SIZE_AND_DIS_FLAGS.SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM = 0) -// -define region GPRAM_region = mem:[from __GPRAM_START__ to __GPRAM_END__]; -place in GPRAM_region {section .gpram}; diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ble.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ble.h deleted file mode 100644 index bf7a27935..000000000 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ble.h +++ /dev/null @@ -1,321 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_cpe_ble.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ -* -* Description: RF core patch for Bluetooth low energy version 4.0, 4.1, and 4.2 support ("BLE" API command set) in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2018, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -#ifndef _RF_PATCH_CPE_BLE_H -#define _RF_PATCH_CPE_BLE_H - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#ifndef CPE_PATCH_TYPE -#define CPE_PATCH_TYPE static const uint32_t -#endif - -#ifndef SYS_PATCH_TYPE -#define SYS_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef _APPLY_PATCH_TAB -#define _APPLY_PATCH_TAB -#endif - - -CPE_PATCH_TYPE patchImageBle[] = { - 0x210040c9, - 0x21004141, - 0x21004073, - 0x21004061, - 0x21004209, - 0x2100421d, - 0x21004237, - 0x210040ad, - 0xb081b5ff, - 0x9d0a4803, - 0xb5f84700, - 0x48024684, - 0x47004613, - 0x00007f43, - 0x00005145, - 0x2270480b, - 0x43916801, - 0x43112240, - 0x48096001, - 0x48094700, - 0x460c7801, - 0x43912208, - 0xf0007001, - 0x4805f803, - 0xbd107004, - 0x4804b510, - 0x00004700, - 0x40043018, - 0x0000710f, - 0x210000b3, - 0x00005603, - 0x4801b510, - 0x00004700, - 0x000009df, - 0x49044803, - 0x05c068c0, - 0x47880fc0, - 0x47084902, - 0x21000340, - 0x000087d1, - 0x000053cd, - 0x4614b5f8, - 0x9b06461a, - 0x46139300, - 0xf7ff4622, - 0x9000ffb5, - 0xd12d2800, - 0x6848492e, - 0xd0292800, - 0x00498809, - 0x43411b09, - 0x68c0482b, - 0x00640844, - 0x20187922, - 0xb2c61a80, - 0x04802001, - 0x0cc71808, - 0x46317965, - 0xf0004825, - 0x4824f8a1, - 0x19832201, - 0x408a1e69, - 0x21182000, - 0xe0071b8e, - 0x19090041, - 0x437988c9, - 0x40e91889, - 0x1c405419, - 0xdcf54286, - 0x4780481b, - 0xbdf89800, - 0xf7ffb510, - 0x4604ff84, - 0x20004914, - 0x60484a17, - 0x88006810, - 0x28030b00, - 0x0760d01d, - 0x6810d41b, - 0x28007bc0, - 0x2802d001, - 0x2013d115, - 0x4a0c01c0, - 0x68d08008, - 0xd00428c0, - 0xd00428d8, - 0x383938ff, - 0x480bd109, - 0x480be000, - 0x480b6048, - 0x211860d0, - 0xf0004804, - 0x4620f85f, - 0x0000bd10, - 0x21004260, - 0x21000028, - 0x21000000, - 0x0000764d, - 0x21000108, - 0x00063b91, - 0x0003fd29, - 0x000090fd, - 0x480eb570, - 0x4c0e6ac0, - 0x0f000700, - 0x28012502, - 0x2804d005, - 0x280cd00b, - 0x280dd001, - 0x6960d106, - 0x616043a8, - 0x49072001, - 0x60080280, - 0x4906bd70, - 0x47882001, - 0x43286960, - 0xbd706160, - 0x40046000, - 0x40041100, - 0xe000e180, - 0x00007d05, - 0x4c03b510, - 0xff48f7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x780a490b, - 0xd1042aff, - 0x7ad24a0a, - 0x0f120712, - 0x4908700a, - 0x75883140, - 0x49054770, - 0x29ff7809, - 0x0900d005, - 0x43080100, - 0x31404902, - 0x47707588, - 0x210002a5, - 0x40086200, - 0x4801b403, - 0xbd019001, - 0x000089dd, - 0x00000000, - 0x00000000, -}; -#define _NWORD_PATCHIMAGE_BLE 145 - -#define _NWORD_PATCHSYS_BLE 0 - -#define _IRQ_PATCH_0 0x210041bd - - -#ifndef _BLE_SYSRAM_START -#define _BLE_SYSRAM_START 0x20000000 -#endif - -#ifndef _BLE_CPERAM_START -#define _BLE_CPERAM_START 0x21000000 -#endif - -#define _BLE_SYS_PATCH_FIXED_ADDR 0x20000000 - -#define _BLE_PARSER_PATCH_TAB_OFFSET 0x0390 -#define _BLE_PATCH_TAB_OFFSET 0x0398 -#define _BLE_IRQPATCH_OFFSET 0x0434 -#define _BLE_PATCH_VEC_OFFSET 0x4024 - -#ifndef _BLE_NO_PROG_STATE_VAR -static uint8_t bBlePatchEntered = 0; -#endif - -PATCH_FUN_SPEC void enterBleCpePatch(void) -{ -#if (_NWORD_PATCHIMAGE_BLE > 0) - uint32_t *pPatchVec = (uint32_t *) (_BLE_CPERAM_START + _BLE_PATCH_VEC_OFFSET); - - memcpy(pPatchVec, patchImageBle, sizeof(patchImageBle)); -#endif -} - -PATCH_FUN_SPEC void enterBleSysPatch(void) -{ -} - -PATCH_FUN_SPEC void configureBlePatch(void) -{ - uint8_t *pPatchTab = (uint8_t *) (_BLE_CPERAM_START + _BLE_PATCH_TAB_OFFSET); - uint32_t *pIrqPatch = (uint32_t *) (_BLE_CPERAM_START + _BLE_IRQPATCH_OFFSET); - - - pPatchTab[142] = 0; - pPatchTab[66] = 1; - pPatchTab[73] = 2; - pPatchTab[117] = 3; - pPatchTab[28] = 4; - pPatchTab[105] = 5; - pPatchTab[106] = 6; - pPatchTab[70] = 7; - - pIrqPatch[21] = _IRQ_PATCH_0; -} - -PATCH_FUN_SPEC void applyBlePatch(void) -{ -#ifdef _BLE_NO_PROG_STATE_VAR - enterBleSysPatch(); - enterBleCpePatch(); -#else - if (!bBlePatchEntered) - { - enterBleSysPatch(); - enterBleCpePatch(); - bBlePatchEntered = 1; - } -#endif - configureBlePatch(); -} - -PATCH_FUN_SPEC void refreshBlePatch(void) -{ - configureBlePatch(); -} - -#ifndef _BLE_NO_PROG_STATE_VAR -PATCH_FUN_SPEC void cleanBlePatch(void) -{ - bBlePatchEntered = 0; -} -#endif - -PATCH_FUN_SPEC void rf_patch_cpe_ble(void) -{ - applyBlePatch(); -} - -#undef _IRQ_PATCH_0 - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // _RF_PATCH_CPE_BLE_H - diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h index a676d3d34..b293749a2 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h +++ b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h @@ -1,11 +1,11 @@ /****************************************************************************** * Filename: rf_patch_cpe_bt5.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ +* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ +* Revision: $Revision: 18889 $ * * Description: RF core patch for Bluetooth 5 support ("BLE" and "BLE5" API command sets) in CC13x2 and CC26x2 * -* Copyright (c) 2015-2018, Texas Instruments Incorporated +* Copyright (c) 2015-2019, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -70,477 +70,50 @@ extern "C" CPE_PATCH_TYPE patchImageBt5[] = { - 0x21004161, - 0x210041d9, - 0x21004255, - 0x2100440b, - 0x2100445b, - 0x21004091, - 0x2100409d, - 0x210040b5, - 0x210044df, - 0x210040d9, - 0x2100410b, - 0x210040f9, - 0x21004651, - 0x21004665, - 0x2100467f, - 0x21004145, - 0x21004701, - 0xb081b5ff, - 0x9d0a4803, - 0xb5f84700, - 0x48024684, - 0x47004613, - 0x00007f43, - 0x00005145, - 0x461db570, - 0x47204c00, - 0x00022281, - 0x0a804670, - 0x288d4a05, - 0x4710d004, - 0x32e44a03, - 0x90042001, - 0x20004902, - 0x47107008, - 0x00006f69, - 0x210001f8, - 0x88084903, - 0x46714a03, - 0xd0004290, - 0x47081c89, - 0x210001a6, - 0x00001404, - 0xb083b5f3, - 0x47004800, - 0x00020b17, - 0x68024805, - 0xd3030852, - 0x60da4b04, - 0x60022200, - 0x1d004670, - 0x00004700, - 0x21004764, - 0x21000340, - 0x2270480b, - 0x43916801, - 0x43112240, - 0x48096001, - 0x48094700, - 0x460c7801, - 0x43912208, - 0xf0007001, - 0x4805f803, - 0xbd107004, - 0x4804b510, - 0x00004700, - 0x40043018, - 0x0000710f, - 0x210000b3, - 0x00005603, - 0x4801b510, - 0x00004700, - 0x000009df, - 0x49044803, - 0x05c068c0, - 0x47880fc0, + 0x21004059, + 0x210040a5, + 0x21004085, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, 0x47084902, - 0x21000340, - 0x000087d1, - 0x000053cd, - 0x4614b5f8, - 0x9b06461a, - 0x46139300, - 0xf7ff4622, - 0x9000ff7b, - 0xd12d2800, - 0x6848492e, - 0xd0292800, - 0x00498809, - 0x43411b09, - 0x68c0482b, - 0x00640844, - 0x20187922, - 0xb2c61a80, - 0x04802001, - 0x0cc71808, - 0x46317965, - 0xf0004825, - 0x4824fad3, - 0x19832201, - 0x408a1e69, - 0x21182000, - 0xe0071b8e, - 0x19090041, - 0x437988c9, - 0x40e91889, - 0x1c405419, - 0xdcf54286, - 0x4780481b, - 0xbdf89800, - 0xf7ffb510, - 0x4604ff4a, - 0x20004914, - 0x60484a17, - 0x88006810, - 0x28030b00, - 0x0760d01d, - 0x6810d41b, - 0x28007bc0, - 0x2802d001, - 0x2013d115, - 0x4a0c01c0, - 0x68d08008, - 0xd00428c0, - 0xd00428d8, - 0x383938ff, - 0x480bd109, - 0x480be000, - 0x480b6048, - 0x211860d0, - 0xf0004804, - 0x4620fa91, - 0x0000bd10, - 0x2100475c, - 0x21000028, - 0x21000000, - 0x0000764d, - 0x21000108, - 0x00063b91, - 0x0003fd29, - 0x000090fd, - 0x4abb8801, - 0x29031889, - 0x48bad806, - 0x8501217c, - 0x624149b9, - 0x47702001, - 0x470849b8, - 0xb43048b8, - 0x31404601, - 0x2a027c0a, - 0x6802d116, - 0x754a79d2, - 0x68936802, - 0x32804602, - 0x7d486093, - 0xd00b2802, - 0xd0092800, - 0x2c061ec4, - 0x49aad809, - 0x18400080, - 0x6b803840, - 0x60901818, - 0xbc3048aa, - 0x20034700, - 0x80c802c0, - 0x72082002, - 0x2003bc30, - 0xb5704770, - 0x460448a3, - 0x7da53440, - 0xd0122d01, - 0x06497d01, - 0x21800fca, - 0x7c21540a, - 0xd10a2900, - 0x78403060, - 0x07c00880, - 0x7ce0d002, - 0xd5020700, - 0x75a02001, - 0x2000e000, - 0x489873a0, - 0x75a54780, - 0xb570bd70, - 0x48964c93, - 0x35504625, - 0x28024780, - 0x3440d109, - 0x4a9388e1, - 0xd1044291, - 0x06897ce9, - 0x1d91d401, - 0xbd7080e1, - 0x498ab570, - 0x4608890a, - 0xb2d23050, - 0xd1072a28, - 0x68d2680a, - 0x7a936142, - 0x02127ad2, - 0x8302189a, - 0x4a877803, - 0xd0102b00, - 0x2b017983, - 0x7c03d10d, - 0x07db095b, - 0x7d09d009, - 0x74c14d82, - 0x20207f6c, - 0x77684320, - 0x776c4790, - 0x21ffbd70, - 0x479074c1, - 0xb510bd70, - 0x4c75487c, - 0x28024780, - 0x4621d10e, - 0x88ca3140, - 0x429a4b75, - 0x7ccad108, - 0x07d20952, - 0x7d22d004, - 0xd4010692, - 0x80ca1d9a, - 0xb570bd10, - 0x4972486a, - 0x7cc03040, - 0x07c00940, - 0x4d6dd007, - 0x8b2c486f, - 0x83284320, - 0x832c4788, - 0x4788bd70, - 0xb570bd70, - 0x496b4c61, - 0x36404626, - 0x00a87935, - 0x6b401840, - 0x2d0a4780, - 0xd0104621, - 0x780a3154, - 0x07db0993, - 0x73b2d004, - 0x2303780a, - 0x700a431a, - 0xb2ca8921, - 0xd3012a2b, - 0x81213928, - 0x3153bd70, - 0x4952e7ed, - 0x71083140, - 0xd01a2825, - 0x280adc08, - 0x280bd011, - 0x2818d011, - 0x281ed011, - 0xe014d106, - 0xd010282a, - 0xd006283c, - 0xd010283d, - 0x00804951, - 0x6b401840, - 0x48504770, - 0x48504770, - 0x48504770, - 0x48504770, - 0x48504770, - 0x48504770, - 0x48504770, - 0xb5f84770, - 0x4c3d4607, - 0x5d00204e, - 0x07ee0985, - 0x2e0025fb, - 0x7d26d017, - 0x0f240734, - 0xd0032c05, - 0x42202401, - 0xe012d002, - 0xe7fa2402, - 0xd00509c0, - 0xd5030670, - 0x0f806848, - 0xd0082801, - 0x005b085b, - 0x00520852, - 0x2800e003, - 0x402bd001, - 0x2b06402a, - 0x2010d003, - 0xd0102b02, - 0x2302e010, - 0x4638402a, - 0xfde4f7ff, - 0xda072800, - 0x1ab900c2, - 0x7e493920, - 0x42112214, - 0x2000d100, - 0x4302bdf8, - 0x46384303, - 0xfdd4f7ff, - 0xb570bdf8, - 0xfdf4f7ff, - 0xd12b0005, - 0x481a4917, - 0x30406809, - 0x4b2a8982, - 0xd123429a, - 0x210169cc, - 0x22000709, - 0xd20c428c, - 0x794b4926, - 0xd506075b, - 0x4a2568c8, - 0x1c400040, - 0x60cc6010, - 0x8182e012, - 0x8182e010, - 0x49212075, - 0x478800c0, - 0x46204606, - 0xf8b6f000, - 0xd0012800, - 0x02ed2503, - 0xb2b0491b, - 0x47883912, - 0xbd704628, - 0xffffe7d5, - 0x21000108, - 0x00020619, - 0x00020625, - 0x21000160, - 0x000245a5, - 0x00022cfd, - 0x00023b49, - 0x00001404, - 0x000238fd, - 0x210000a8, - 0x000224fb, - 0x00021d4f, - 0x00002020, - 0x00024fc0, - 0x210043cb, - 0x210043a7, - 0x2100437b, - 0x21004329, - 0x21004303, - 0x210042c3, - 0x21004271, - 0x0000ffff, - 0x21000340, - 0x21004764, - 0x000040e5, - 0x4d20b5f8, - 0x882c4820, - 0x4e206ac0, - 0x20010701, - 0x02400f09, - 0x0b222702, - 0xd0202908, - 0x2901dc0d, - 0x2904d00f, - 0x491ad114, - 0xd01207d2, - 0x43824622, - 0x2001802a, - 0x802c4788, - 0x290ce00d, - 0x290dd001, - 0x6970d106, - 0x617043b8, - 0x49122001, - 0x60080280, - 0x2001bdf8, - 0x69704788, - 0x61704338, - 0x0a61bdf8, - 0xd0fb07c9, - 0xd0f907d1, - 0x47a04c0b, - 0x2201490b, - 0x03926a48, - 0x62484310, - 0x63484909, - 0x47a02000, - 0x0000bdf8, - 0x21000068, + 0x21000380, + 0x40041108, + 0x0000592d, + 0x21014805, + 0x438a6802, + 0x6b836002, + 0x6383438b, + 0x6002430a, + 0x47004801, 0x40046000, - 0x40041100, - 0x00007d05, - 0xe000e180, - 0x000045b7, - 0x210002c0, - 0x40044000, - 0x4c03b510, - 0xfd70f7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x780a490b, - 0xd1042aff, - 0x7ad24a0a, - 0x0f120712, - 0x4908700a, - 0x75883140, - 0x49054770, - 0x29ff7809, - 0x0900d005, - 0x43080100, - 0x31404902, - 0x47707588, - 0x210002a5, - 0x40086200, - 0x4e26b5f1, - 0x79742000, - 0x60f068f7, - 0x46254824, - 0x05c08800, - 0x2004d502, - 0x71744304, - 0x4b21221d, - 0x98002100, - 0x28004798, - 0x68f1d109, - 0x29001f03, - 0x9900d004, - 0xb2ca6809, - 0xd0032a2b, - 0x60f74618, - 0xbdf87175, - 0x0f890589, - 0xd1022902, - 0x400c21fb, - 0x21047174, - 0x400d400c, - 0xd0f242ac, - 0x03094a12, - 0xbdf86091, - 0x4604b570, - 0x28158800, - 0x490fd003, - 0x47884620, - 0x2075bd70, - 0x00c0490d, - 0x46054788, - 0xf7ff6860, - 0x2800ffbd, - 0x2487d001, - 0x2401e000, - 0x46284907, - 0x4788311c, - 0xbd704620, - 0x21000340, - 0x21000284, - 0x00004a99, - 0x40041100, - 0x0000270f, - 0x000045c7, - 0x4801b403, - 0xbd019001, - 0x000089dd, - 0x00000000, - 0x00000000, - 0x00000000, + 0x00005b3f, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, }; -#define _NWORD_PATCHIMAGE_BT5 465 +#define _NWORD_PATCHIMAGE_BT5 37 + +#define _NWORD_PATCHCPEHD_BT5 0 #define _NWORD_PATCHSYS_BT5 0 -#define _IRQ_PATCH_0 0x210045ad #ifndef _BT5_SYSRAM_START @@ -553,10 +126,12 @@ CPE_PATCH_TYPE patchImageBt5[] = { #define _BT5_SYS_PATCH_FIXED_ADDR 0x20000000 -#define _BT5_PARSER_PATCH_TAB_OFFSET 0x0390 -#define _BT5_PATCH_TAB_OFFSET 0x0398 -#define _BT5_IRQPATCH_OFFSET 0x0434 -#define _BT5_PATCH_VEC_OFFSET 0x4024 +#define _BT5_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _BT5_PATCH_TAB_OFFSET 0x03D4 +#define _BT5_IRQPATCH_OFFSET 0x0480 +#define _BT5_PATCH_VEC_OFFSET 0x404C + +#define _BT5_PATCH_CPEHD_OFFSET 0x04E0 #ifndef _BT5_NO_PROG_STATE_VAR static uint8_t bBt5PatchEntered = 0; @@ -571,36 +146,27 @@ PATCH_FUN_SPEC void enterBt5CpePatch(void) #endif } +PATCH_FUN_SPEC void enterBt5CpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_BT5 > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_BT5_CPERAM_START + _BT5_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + PATCH_FUN_SPEC void enterBt5SysPatch(void) { } PATCH_FUN_SPEC void configureBt5Patch(void) { - uint8_t *pParserPatchTab = (uint8_t *) (_BT5_CPERAM_START + _BT5_PARSER_PATCH_TAB_OFFSET); uint8_t *pPatchTab = (uint8_t *) (_BT5_CPERAM_START + _BT5_PATCH_TAB_OFFSET); - uint32_t *pIrqPatch = (uint32_t *) (_BT5_CPERAM_START + _BT5_IRQPATCH_OFFSET); - pPatchTab[142] = 0; - pPatchTab[66] = 1; - pParserPatchTab[1] = 2; - pPatchTab[1] = 3; - pPatchTab[18] = 4; - pPatchTab[112] = 5; - pPatchTab[115] = 6; - pPatchTab[22] = 7; - pPatchTab[10] = 8; - pPatchTab[36] = 9; - pPatchTab[73] = 10; - pPatchTab[117] = 11; - pPatchTab[28] = 12; - pPatchTab[105] = 13; - pPatchTab[106] = 14; - pPatchTab[70] = 15; - pParserPatchTab[0] = 16; - - pIrqPatch[21] = _IRQ_PATCH_0; + pPatchTab[76] = 0; + pPatchTab[91] = 1; + pPatchTab[79] = 2; } PATCH_FUN_SPEC void applyBt5Patch(void) @@ -616,11 +182,13 @@ PATCH_FUN_SPEC void applyBt5Patch(void) bBt5PatchEntered = 1; } #endif + enterBt5CpeHdPatch(); configureBt5Patch(); } PATCH_FUN_SPEC void refreshBt5Patch(void) { + enterBt5CpeHdPatch(); configureBt5Patch(); } @@ -636,7 +204,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_bt5(void) applyBt5Patch(); } -#undef _IRQ_PATCH_0 //***************************************************************************** // diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h index f1ba1dd08..855993da2 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h +++ b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h @@ -1,11 +1,11 @@ /****************************************************************************** * Filename: rf_patch_cpe_ieee_802_15_4.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ +* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ +* Revision: $Revision: 18889 $ * * Description: RF core patch for IEEE 802.15.4-2006 support ("IEEE" API command set) in CC13x2 and CC26x2 * -* Copyright (c) 2015-2018, Texas Instruments Incorporated +* Copyright (c) 2015-2019, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -70,121 +70,25 @@ extern "C" CPE_PATCH_TYPE patchImageIeee802154[] = { - 0x2100403d, - 0x210040d9, - 0x210040ed, - 0x21004107, - 0x21004071, - 0x21004189, - 0x6ac34807, - 0xf808f000, - 0x009b089b, - 0x6ac14804, - 0xd10007c9, - 0xbdf862c3, - 0xb5f84902, - 0x00004708, - 0x40045040, - 0x00029dd3, - 0x4801b510, - 0x00004700, - 0x000009df, - 0x49044803, - 0x05c068c0, - 0x47880fc0, + 0x21004051, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, 0x47084902, - 0x21000340, - 0x000087d1, - 0x000053cd, - 0x480eb570, - 0x4c0e6ac0, - 0x0f000700, - 0x28012502, - 0x2804d005, - 0x280cd00b, - 0x280dd001, - 0x6960d106, - 0x616043a8, - 0x49072001, - 0x60080280, - 0x4906bd70, - 0x47882001, - 0x43286960, - 0xbd706160, - 0x40046000, - 0x40041100, - 0xe000e180, - 0x00007d05, - 0x4c03b510, - 0xffc2f7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x780a490b, - 0xd1042aff, - 0x7ad24a0a, - 0x0f120712, - 0x4908700a, - 0x75883140, - 0x49054770, - 0x29ff7809, - 0x0900d005, - 0x43080100, - 0x31404902, - 0x47707588, - 0x210002a5, - 0x40086200, - 0x4e26b5f1, - 0x79742000, - 0x60f068f7, - 0x46254824, - 0x05c08800, - 0x2004d502, - 0x71744304, - 0x4b21221d, - 0x98002100, - 0x28004798, - 0x68f1d109, - 0x29001f03, - 0x9900d004, - 0xb2ca6809, - 0xd0032a2b, - 0x60f74618, - 0xbdf87175, - 0x0f890589, - 0xd1022902, - 0x400c21fb, - 0x21047174, - 0x400d400c, - 0xd0f242ac, - 0x03094a12, - 0xbdf86091, - 0x4604b570, - 0x28158800, - 0x490fd003, - 0x47884620, - 0x2075bd70, - 0x00c0490d, - 0x46054788, - 0xf7ff6860, - 0x2800ffbd, - 0x2487d001, - 0x2401e000, - 0x46284907, - 0x4788311c, - 0xbd704620, - 0x21000340, - 0x21000284, - 0x00004a99, - 0x40041100, - 0x0000270f, - 0x000045c7, + 0x21000380, + 0x40041108, + 0x0000592d, }; -#define _NWORD_PATCHIMAGE_IEEE_802_15_4 109 +#define _NWORD_PATCHIMAGE_IEEE_802_15_4 12 + +#define _NWORD_PATCHCPEHD_IEEE_802_15_4 0 #define _NWORD_PATCHSYS_IEEE_802_15_4 0 -#define _IRQ_PATCH_0 0x2100408d #ifndef _IEEE_802_15_4_SYSRAM_START @@ -197,10 +101,12 @@ CPE_PATCH_TYPE patchImageIeee802154[] = { #define _IEEE_802_15_4_SYS_PATCH_FIXED_ADDR 0x20000000 -#define _IEEE_802_15_4_PARSER_PATCH_TAB_OFFSET 0x0390 -#define _IEEE_802_15_4_PATCH_TAB_OFFSET 0x0398 -#define _IEEE_802_15_4_IRQPATCH_OFFSET 0x0434 -#define _IEEE_802_15_4_PATCH_VEC_OFFSET 0x4024 +#define _IEEE_802_15_4_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _IEEE_802_15_4_PATCH_TAB_OFFSET 0x03D4 +#define _IEEE_802_15_4_IRQPATCH_OFFSET 0x0480 +#define _IEEE_802_15_4_PATCH_VEC_OFFSET 0x404C + +#define _IEEE_802_15_4_PATCH_CPEHD_OFFSET 0x04E0 #ifndef _IEEE_802_15_4_NO_PROG_STATE_VAR static uint8_t bIeee802154PatchEntered = 0; @@ -215,25 +121,25 @@ PATCH_FUN_SPEC void enterIeee802154CpePatch(void) #endif } +PATCH_FUN_SPEC void enterIeee802154CpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_IEEE_802_15_4 > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + PATCH_FUN_SPEC void enterIeee802154SysPatch(void) { } PATCH_FUN_SPEC void configureIeee802154Patch(void) { - uint8_t *pParserPatchTab = (uint8_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PARSER_PATCH_TAB_OFFSET); uint8_t *pPatchTab = (uint8_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_TAB_OFFSET); - uint32_t *pIrqPatch = (uint32_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_IRQPATCH_OFFSET); - pPatchTab[53] = 0; - pPatchTab[28] = 1; - pPatchTab[105] = 2; - pPatchTab[106] = 3; - pPatchTab[70] = 4; - pParserPatchTab[0] = 5; - - pIrqPatch[21] = _IRQ_PATCH_0; + pPatchTab[76] = 0; } PATCH_FUN_SPEC void applyIeee802154Patch(void) @@ -249,11 +155,13 @@ PATCH_FUN_SPEC void applyIeee802154Patch(void) bIeee802154PatchEntered = 1; } #endif + enterIeee802154CpeHdPatch(); configureIeee802154Patch(); } PATCH_FUN_SPEC void refreshIeee802154Patch(void) { + enterIeee802154CpeHdPatch(); configureIeee802154Patch(); } @@ -269,7 +177,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_ieee_802_15_4(void) applyIeee802154Patch(); } -#undef _IRQ_PATCH_0 //***************************************************************************** // diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h index d6b9c9ddd..6a197337c 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h +++ b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h @@ -1,11 +1,11 @@ /****************************************************************************** * Filename: rf_patch_cpe_multi_protocol.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ +* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ +* Revision: $Revision: 18889 $ * * Description: RF core patch for multi-protocol support (all available API command sets) in CC13x2 and CC26x2 * -* Copyright (c) 2015-2018, Texas Instruments Incorporated +* Copyright (c) 2015-2019, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -70,626 +70,76 @@ extern "C" CPE_PATCH_TYPE patchImageMultiProtocol[] = { - 0x21004245, - 0x21004265, - 0x210042dd, - 0x21004385, - 0x2100442d, - 0x210045e3, - 0x21004633, - 0x210040bd, - 0x210040c9, - 0x210040e1, - 0x210046b7, - 0x21004105, - 0x21004125, - 0x21004785, - 0x21004159, - 0x2100417d, - 0x2100419f, - 0x2100418d, - 0x2100483d, - 0x21004857, - 0x210041d1, - 0x210041ed, - 0x210041fd, - 0x21004955, - 0x2100420d, - 0xb081b5ff, - 0x9d0a4803, - 0xb5f84700, - 0x48024684, - 0x47004613, - 0x00007f43, - 0x00005145, - 0x460cb5f7, - 0x47084900, - 0x0000681d, - 0x461db570, - 0x47204c00, - 0x00022281, - 0x0a804670, - 0x288d4a05, - 0x4710d004, - 0x32e44a03, - 0x90042001, - 0x20004902, - 0x47107008, - 0x00006f69, - 0x210001f8, - 0x88084903, - 0x46714a03, - 0xd0004290, - 0x47081c89, - 0x210001a6, - 0x00001404, - 0xb083b5f3, - 0x47004800, - 0x00020b17, - 0x68024805, - 0xd3030852, - 0x60da4b04, - 0x60022200, - 0x1d004670, - 0x00004700, - 0x210049b8, - 0x21000340, - 0x6ac34807, - 0xf808f000, - 0x009b089b, - 0x6ac14804, - 0xd10007c9, - 0xbdf862c3, - 0xb5f84902, - 0x00004708, - 0x40045040, - 0x00029dd3, - 0x4801b510, - 0x00004700, - 0x000009df, - 0x460db5f8, - 0x4b0a4616, - 0x290c6d59, - 0x4b03d104, - 0x78192408, - 0x70194321, - 0x47084901, - 0x21000340, - 0x0000699d, - 0x46864810, - 0x21804801, - 0x47706041, - 0x40045000, - 0x2270480d, - 0x43916801, - 0x43112240, - 0x480b6001, - 0x480b4700, - 0x460c7801, - 0x43912208, - 0xf0007001, - 0x4807f803, - 0xbd107004, - 0xf7ffb510, - 0x4801ffe3, - 0x470038c8, - 0x000056cb, - 0x40043018, - 0x0000710f, - 0x210000b3, - 0x49044803, - 0x05c068c0, - 0x47880fc0, + 0x21004061, + 0x210040cb, + 0x2100408d, + 0x2100410d, + 0x210040ed, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, 0x47084902, - 0x21000340, - 0x000087d1, - 0x000053cd, - 0xf0002000, - 0x4604fb41, - 0x47004800, - 0x0000545b, - 0xf0002004, - 0x4605fb39, - 0x47004800, - 0x0000533b, - 0xf811f000, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, 0x296cb2e1, 0x2804d00b, 0x2806d001, - 0x4907d107, + 0x490ed107, 0x07c97809, 0x7821d103, 0xd4000709, - 0xb0032002, + 0x490b2002, + 0x210c780a, + 0xd0024211, + 0x22804909, + 0xb003600a, 0xb5f0bdf0, - 0x4902b083, - 0x00004708, + 0x4907b083, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, 0x210000c8, - 0x0003071b, - 0x4905b672, - 0x22206808, - 0x600a4302, - 0x6ad24a03, - 0xb6626008, - 0x4770b250, - 0x40040000, - 0x40046040, - 0x4614b5f8, - 0x9b06461a, - 0x46139300, - 0xf7ff4622, - 0x9000ff09, - 0xd12d2800, - 0x6848495f, - 0xd0292800, - 0x00498809, - 0x43411b09, - 0x68c0485c, - 0x00640844, - 0x20187922, - 0xb2c61a80, - 0x04802001, - 0x0cc71808, - 0x46317965, - 0xf0004856, - 0x4855fb7b, - 0x19832201, - 0x408a1e69, - 0x21182000, - 0xe0071b8e, - 0x19090041, - 0x437988c9, - 0x40e91889, - 0x1c405419, - 0xdcf54286, - 0x4780484c, - 0xbdf89800, - 0xf7ffb570, - 0x4a46fed8, - 0x49492300, - 0x60534604, - 0x25136808, - 0x01ed8800, - 0x2e030b06, - 0x0760d00d, - 0x6808d43f, - 0x290c7bc1, - 0xdc0fd028, - 0xd0132904, - 0xd0142905, - 0xd10d290a, - 0xb2c0e01d, - 0xd0032806, - 0x8c006808, - 0xe02d8010, - 0xe02b8015, - 0xd018290f, - 0xd019291e, - 0xe0048015, - 0x01802013, - 0x4835e000, - 0x48308010, - 0x29c068c1, - 0x29d8d010, - 0x39ffd010, - 0xd1173939, - 0x20ffe00a, - 0xe7f130e7, - 0x309620ff, - 0x20ffe7ee, - 0xe7eb3045, - 0xe7e920a2, - 0xe000492a, - 0x6051492a, - 0x60c1492a, - 0x48232118, - 0xfb14f000, - 0x8013e000, - 0xbd704620, - 0x4604b5f8, - 0x4e1c481d, - 0x88003040, - 0x0a80460d, - 0xd00407c0, - 0x08644821, - 0x43447900, - 0x8830e025, - 0xd0222800, - 0x19000960, - 0xfe7af7ff, - 0x20014607, - 0x0240491b, - 0x46024788, - 0x1bc02005, - 0x40848831, - 0x18230848, - 0x62034817, - 0x21016241, - 0x430d61c1, - 0x60cd490a, - 0x07c969c1, - 0x6a80d1fc, - 0x60704910, - 0x39124610, - 0x46384788, - 0x2000bdf8, - 0x46206070, - 0xfe56f7ff, - 0x0000bdf8, - 0x210049b0, - 0x21000028, - 0x21000000, - 0x0000764d, - 0x21000108, - 0x000003cd, - 0x00063b91, - 0x0003fd29, - 0x000090fd, - 0x21000340, - 0x000040e5, - 0x40044100, - 0x4abb8801, - 0x29031889, - 0x48bad806, - 0x8501217c, - 0x624149b9, - 0x47702001, - 0x470849b8, - 0xb43048b8, - 0x31404601, - 0x2a027c0a, - 0x6802d116, - 0x754a79d2, - 0x68936802, - 0x32804602, - 0x7d486093, - 0xd00b2802, - 0xd0092800, - 0x2c061ec4, - 0x49aad809, - 0x18400080, - 0x6b803840, - 0x60901818, - 0xbc3048aa, - 0x20034700, - 0x80c802c0, - 0x72082002, - 0x2003bc30, - 0xb5704770, - 0x460448a3, - 0x7da53440, - 0xd0122d01, - 0x06497d01, - 0x21800fca, - 0x7c21540a, - 0xd10a2900, - 0x78403060, - 0x07c00880, - 0x7ce0d002, - 0xd5020700, - 0x75a02001, - 0x2000e000, - 0x489873a0, - 0x75a54780, - 0xb570bd70, - 0x48964c93, - 0x35504625, - 0x28024780, - 0x3440d109, - 0x4a9388e1, - 0xd1044291, - 0x06897ce9, - 0x1d91d401, - 0xbd7080e1, - 0x498ab570, - 0x4608890a, - 0xb2d23050, - 0xd1072a28, - 0x68d2680a, - 0x7a936142, - 0x02127ad2, - 0x8302189a, - 0x4a877803, - 0xd0102b00, - 0x2b017983, - 0x7c03d10d, - 0x07db095b, - 0x7d09d009, - 0x74c14d82, - 0x20207f6c, - 0x77684320, - 0x776c4790, - 0x21ffbd70, - 0x479074c1, - 0xb510bd70, - 0x4c75487c, - 0x28024780, - 0x4621d10e, - 0x88ca3140, - 0x429a4b75, - 0x7ccad108, - 0x07d20952, - 0x7d22d004, - 0xd4010692, - 0x80ca1d9a, - 0xb570bd10, - 0x4972486a, - 0x7cc03040, - 0x07c00940, - 0x4d6dd007, - 0x8b2c486f, - 0x83284320, - 0x832c4788, - 0x4788bd70, - 0xb570bd70, - 0x496b4c61, - 0x36404626, - 0x00a87935, - 0x6b401840, - 0x2d0a4780, - 0xd0104621, - 0x780a3154, - 0x07db0993, - 0x73b2d004, - 0x2303780a, - 0x700a431a, - 0xb2ca8921, - 0xd3012a2b, - 0x81213928, - 0x3153bd70, - 0x4952e7ed, - 0x71083140, - 0xd01a2825, - 0x280adc08, - 0x280bd011, - 0x2818d011, - 0x281ed011, - 0xe014d106, - 0xd010282a, - 0xd006283c, - 0xd010283d, - 0x00804951, - 0x6b401840, - 0x48504770, - 0x48504770, - 0x48504770, - 0x48504770, - 0x48504770, - 0x48504770, - 0x48504770, - 0xb5f84770, - 0x4c3d4607, - 0x5d00204e, - 0x07ee0985, - 0x2e0025fb, - 0x7d26d017, - 0x0f240734, - 0xd0032c05, - 0x42202401, - 0xe012d002, - 0xe7fa2402, - 0xd00509c0, - 0xd5030670, - 0x0f806848, - 0xd0082801, - 0x005b085b, - 0x00520852, - 0x2800e003, - 0x402bd001, - 0x2b06402a, - 0x2010d003, - 0xd0102b02, - 0x2302e010, - 0x4638402a, - 0xfd0ef7ff, - 0xda072800, - 0x1ab900c2, - 0x7e493920, - 0x42112214, - 0x2000d100, - 0x4302bdf8, - 0x46384303, - 0xfcfef7ff, - 0xb570bdf8, - 0xfd1ef7ff, - 0xd12b0005, - 0x481a4917, - 0x30406809, - 0x4b2a8982, - 0xd123429a, - 0x210169cc, - 0x22000709, - 0xd20c428c, - 0x794b4926, - 0xd506075b, - 0x4a2568c8, - 0x1c400040, - 0x60cc6010, - 0x8182e012, - 0x8182e010, - 0x49212075, - 0x478800c0, - 0x46204606, - 0xf8f4f000, - 0xd0012800, - 0x02ed2503, - 0xb2b0491b, - 0x47883912, - 0xbd704628, - 0xffffe7d5, - 0x21000108, - 0x00020619, - 0x00020625, - 0x21000160, - 0x000245a5, - 0x00022cfd, - 0x00023b49, - 0x00001404, - 0x000238fd, - 0x210000a8, - 0x000224fb, - 0x00021d4f, - 0x00002020, - 0x00024fc0, - 0x210045a3, - 0x2100457f, - 0x21004553, - 0x21004501, - 0x210044db, - 0x2100449b, - 0x21004449, - 0x0000ffff, - 0x21000340, - 0x210049b8, - 0x000040e5, - 0x4c03b510, - 0xfce0f7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x4d20b5f8, - 0x882c4820, - 0x4e206ac0, - 0x20010701, - 0x02400f09, - 0x0b222702, - 0xd0202908, - 0x2901dc0d, - 0x2904d00f, - 0x491ad114, - 0xd01207d2, - 0x43824622, - 0x2001802a, - 0x802c4788, - 0x290ce00d, - 0x290dd001, - 0x6970d106, - 0x617043b8, - 0x49122001, - 0x60080280, - 0x2001bdf8, - 0x69704788, - 0x61704338, - 0x0a61bdf8, - 0xd0fb07c9, - 0xd0f907d1, - 0x47a04c0b, - 0x2201490b, - 0x03926a48, - 0x62484310, - 0x63484909, - 0x47a02000, - 0x0000bdf8, - 0x21000068, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x00031b23, + 0x21014805, + 0x438a6802, + 0x6b836002, + 0x6383438b, + 0x6002430a, + 0x47004801, 0x40046000, - 0x40041100, - 0x00007d05, - 0xe000e180, - 0x000045b7, - 0x210002c0, - 0x40044000, - 0x780a490b, - 0xd1042aff, - 0x7ad24a0a, - 0x0f120712, - 0x4908700a, - 0x75883140, - 0x49054770, - 0x29ff7809, - 0x0900d005, - 0x43080100, - 0x31404902, - 0x47707588, - 0x210002a5, - 0x40086200, - 0x4c19b570, - 0x7ba14606, - 0xf820f000, - 0x7be14605, - 0xf0004630, - 0x4915f81b, - 0x78094604, - 0x070a2028, - 0x2d01d401, - 0x2038d100, - 0xd40106c9, - 0xd1012c01, - 0x43082140, - 0x4788490e, - 0xd0012dff, - 0x6145480d, - 0xd0012cff, - 0x61c4480c, - 0xbd704808, - 0xd0082900, - 0xd00629ff, - 0x070840c1, - 0x281c0ec0, - 0x2001d100, - 0x20ff4770, - 0x00004770, - 0x210000a8, - 0x21000340, - 0x000040e5, - 0x40045040, - 0x40046000, - 0x4e26b5f1, - 0x79742000, - 0x60f068f7, - 0x46254824, - 0x05c08800, - 0x2004d502, - 0x71744304, - 0x4b21221d, - 0x98002100, - 0x28004798, - 0x68f1d109, - 0x29001f03, - 0x9900d004, - 0xb2ca6809, - 0xd0032a2b, - 0x60f74618, - 0xbdf87175, - 0x0f890589, - 0xd1022902, - 0x400c21fb, - 0x21047174, - 0x400d400c, - 0xd0f242ac, - 0x03094a12, - 0xbdf86091, - 0x4604b570, - 0x28158800, - 0x490fd003, - 0x47884620, - 0x2075bd70, - 0x00c0490d, - 0x46054788, - 0xf7ff6860, - 0x2800ffbd, - 0x2487d001, - 0x2401e000, - 0x46284907, - 0x4788311c, - 0xbd704620, - 0x21000340, - 0x21000284, - 0x00004a99, - 0x40041100, - 0x0000270f, - 0x000045c7, - 0x4801b403, - 0xbd019001, - 0x000089dd, - 0x00000000, - 0x00000000, - 0x00000000, + 0x00005b3f, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, }; -#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL 614 +#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL 63 + +#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL 0 #define _NWORD_PATCHSYS_MULTI_PROTOCOL 0 -#define _IRQ_PATCH_0 0x21004799 #ifndef _MULTI_PROTOCOL_SYSRAM_START @@ -702,10 +152,12 @@ CPE_PATCH_TYPE patchImageMultiProtocol[] = { #define _MULTI_PROTOCOL_SYS_PATCH_FIXED_ADDR 0x20000000 -#define _MULTI_PROTOCOL_PARSER_PATCH_TAB_OFFSET 0x0390 -#define _MULTI_PROTOCOL_PATCH_TAB_OFFSET 0x0398 -#define _MULTI_PROTOCOL_IRQPATCH_OFFSET 0x0434 -#define _MULTI_PROTOCOL_PATCH_VEC_OFFSET 0x4024 +#define _MULTI_PROTOCOL_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _MULTI_PROTOCOL_PATCH_TAB_OFFSET 0x03D4 +#define _MULTI_PROTOCOL_IRQPATCH_OFFSET 0x0480 +#define _MULTI_PROTOCOL_PATCH_VEC_OFFSET 0x404C + +#define _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET 0x04E0 #ifndef _MULTI_PROTOCOL_NO_PROG_STATE_VAR static uint8_t bMultiProtocolPatchEntered = 0; @@ -720,44 +172,29 @@ PATCH_FUN_SPEC void enterMultiProtocolCpePatch(void) #endif } +PATCH_FUN_SPEC void enterMultiProtocolCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + PATCH_FUN_SPEC void enterMultiProtocolSysPatch(void) { } PATCH_FUN_SPEC void configureMultiProtocolPatch(void) { - uint8_t *pParserPatchTab = (uint8_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PARSER_PATCH_TAB_OFFSET); uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_TAB_OFFSET); - uint32_t *pIrqPatch = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_IRQPATCH_OFFSET); - pPatchTab[84] = 0; - pPatchTab[142] = 1; - pPatchTab[66] = 2; - pPatchTab[102] = 3; - pParserPatchTab[1] = 4; - pPatchTab[1] = 5; - pPatchTab[18] = 6; - pPatchTab[112] = 7; - pPatchTab[115] = 8; - pPatchTab[22] = 9; - pPatchTab[10] = 10; - pPatchTab[36] = 11; - pPatchTab[53] = 12; - pPatchTab[28] = 13; - pPatchTab[104] = 14; - pPatchTab[75] = 15; - pPatchTab[73] = 16; - pPatchTab[117] = 17; - pPatchTab[105] = 18; - pPatchTab[106] = 19; - pPatchTab[70] = 20; - pPatchTab[71] = 21; - pPatchTab[69] = 22; - pParserPatchTab[0] = 23; - pPatchTab[60] = 24; - - pIrqPatch[21] = _IRQ_PATCH_0; + pPatchTab[76] = 0; + pPatchTab[62] = 1; + pPatchTab[64] = 2; + pPatchTab[91] = 3; + pPatchTab[79] = 4; } PATCH_FUN_SPEC void applyMultiProtocolPatch(void) @@ -773,11 +210,13 @@ PATCH_FUN_SPEC void applyMultiProtocolPatch(void) bMultiProtocolPatchEntered = 1; } #endif + enterMultiProtocolCpeHdPatch(); configureMultiProtocolPatch(); } PATCH_FUN_SPEC void refreshMultiProtocolPatch(void) { + enterMultiProtocolCpeHdPatch(); configureMultiProtocolPatch(); } @@ -793,7 +232,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol(void) applyMultiProtocolPatch(); } -#undef _IRQ_PATCH_0 //***************************************************************************** // diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h new file mode 100644 index 000000000..6c6ddc9b5 --- /dev/null +++ b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h @@ -0,0 +1,1452 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_protocol_rtls.h +* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ +* Revision: $Revision: 18889 $ +* +* Description: RF core patch for multi-protocol support (all available API command sets) with RTLS components in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H +#define _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageMultiProtocolRtls[] = { + 0x21004631, + 0x21004683, + 0x21004075, + 0x2100486f, + 0x210040ad, + 0x21004117, + 0x210040d9, + 0x2100492d, + 0x21004139, + 0x21005349, + 0x68084908, + 0x43902221, + 0x48076008, + 0x68c34700, + 0x230260c3, + 0xd1fd1e5b, + 0x68c32210, + 0x60c34393, + 0x4770618a, + 0x40048000, + 0x00005c01, + 0x4801b430, + 0x00004700, + 0x00020efd, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x490ed107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490b2002, + 0x210c780a, + 0xd0024211, + 0x22804909, + 0xb003600a, + 0xb5f0bdf0, + 0x4907b083, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x00031b23, + 0x21014805, + 0x438a6802, + 0x6b836002, + 0x6383438b, + 0x6002430a, + 0x47004801, + 0x40046000, + 0x00005b3f, + 0x4803b510, + 0x30106800, + 0xfe72f000, + 0x47084901, + 0x21000108, + 0x000095e3, + 0x4cffb570, + 0x5d002044, + 0x008049fe, + 0x68801840, + 0x46054780, + 0xd0112801, + 0x5d00207e, + 0xd30d2805, + 0x06002021, + 0x00897e41, + 0x7f0a1809, + 0xd0072a02, + 0x77082003, + 0x49f43480, + 0x478888a0, + 0xbd704628, + 0x77012104, + 0x700148f1, + 0xb5ffe7f4, + 0x7e934aec, + 0x49ef185b, + 0x3280600b, + 0x09897891, + 0x49edd16e, + 0x29006909, + 0x680bd06a, + 0x041bb2da, + 0x4be40e1c, + 0x7edb3360, + 0xd01b2c01, + 0x005b2410, + 0x1edb46a6, + 0x4be5469c, + 0x681b684d, + 0x00923108, + 0x1f121852, + 0x9202402b, + 0x4ae13030, + 0x93002401, + 0x60549103, + 0x26224adf, + 0x27106914, + 0x6114433c, + 0xe0302200, + 0x009b2408, + 0x1f9b46a6, + 0xc910e7e2, + 0x40634fd9, + 0x9301402b, + 0x24014623, + 0x603c0364, + 0x34404cd3, + 0x4cd26060, + 0x68643c40, + 0xd5061a24, + 0x3c804cd1, + 0x04bf6827, + 0xbf20d401, + 0x4fcbe7fa, + 0x633c9c01, + 0x44709c02, + 0xd90042a1, + 0x4cc59903, + 0x42346864, + 0x4cc3d006, + 0x68263c80, + 0x43be2702, + 0x26006026, + 0x45621c52, + 0x9c00d3d1, + 0x405c49c0, + 0x3940402c, + 0x1a12684a, + 0x48bcd4fc, + 0x48bc6304, + 0x60412100, + 0x690248bb, + 0x438a2110, + 0xbdff6102, + 0x212248b4, + 0x420a6842, + 0x4ab2d0fc, + 0x68103a80, + 0x43882102, + 0xbdff6010, + 0x4daab5f3, + 0x5d46202f, + 0xb08148b2, + 0x05806900, + 0x2e011600, + 0x1c40d002, + 0xe0001040, + 0x49ad301e, + 0x6a093140, + 0x4ba14aac, + 0x691a4351, + 0x6a1b0e09, + 0xd0222e01, + 0x01591852, + 0x316731ff, + 0x18544b9f, + 0x68d93340, + 0xb2894fa0, + 0xb2821a08, + 0x68783f40, + 0xd4fc1b00, + 0x462860da, + 0x90003060, + 0x49958381, + 0x31122050, + 0x35804788, + 0x980180a8, + 0xd0082800, + 0x990278aa, + 0xfabef000, + 0x1852e007, + 0x31ce0119, + 0x4896e7dc, + 0x99006ac0, + 0x489577c8, + 0x68407829, + 0x08c14348, + 0xd00b2e01, + 0x38134620, + 0x687a340e, + 0xd4fc1b12, + 0x0c0b4a8f, + 0xb2896193, + 0xbdfe6151, + 0x38114620, + 0xe7f23409, + 0x4c7cb570, + 0x35604625, + 0x1e407fa8, + 0xd80d2802, + 0x28006aa0, + 0x2182d004, + 0x70015d09, + 0x62a01c40, + 0x1e406a60, + 0x7fa86260, + 0x77a81cc0, + 0x28057fa8, + 0xd112d322, + 0x28026a60, + 0x497ddd08, + 0x47881e80, + 0x62611c81, + 0xd0012800, + 0xbd702001, + 0x46082100, + 0xff7af7ff, + 0xf7ff2110, + 0x486afef2, + 0x6ac13840, + 0xd0fc07c9, + 0x38804867, + 0x22026801, + 0x60014311, + 0x8ba84964, + 0x60c83140, + 0x36404626, + 0x495e7930, + 0x18400080, + 0x47806880, + 0xd1de2800, + 0x29057fa9, + 0x7fead301, + 0x29047172, + 0x7de1d3d7, + 0xd1022900, + 0x29007e21, + 0x7eead0d1, + 0x015268e1, + 0x60e11889, + 0xb570bd70, + 0x20444d4f, + 0x48535d46, + 0x3820494e, + 0x00b07ec4, + 0x68801840, + 0x4b5a4780, + 0x781a09a1, + 0xd10a4211, + 0x21ff2221, + 0x76510612, + 0x22004948, + 0x600a1f09, + 0x2101604a, + 0x212f7019, + 0x29025d49, + 0x2e31d008, + 0x07e1d003, + 0xd0032900, + 0x0861e003, + 0xe7f907c9, + 0x35802400, + 0xbd70706c, + 0x4c39b5f8, + 0x46272500, + 0x723d3760, + 0x5d00202f, + 0xd03a2802, + 0x47804845, + 0x36404626, + 0x7ff04937, + 0x62203920, + 0x43087849, + 0x48347560, + 0x38406265, + 0x2d007fc5, + 0x7d20d006, + 0x43082120, + 0x06e87520, + 0x72380ec0, + 0x7f30493a, + 0x4a3a4788, + 0xd0112d00, + 0x61c54839, + 0x20074b28, + 0x63983b40, + 0x21054d26, + 0x07806950, + 0x6868d1fc, + 0xd0f94208, + 0x30404831, + 0x63186800, + 0x28007f30, + 0x6e60d001, + 0x6be16210, + 0x47882039, + 0x20006420, + 0x482cbdf8, + 0xb5f0e7fa, + 0x20444915, + 0x2b045c43, + 0x460ad00a, + 0x78103268, + 0x28004f12, + 0x28ffd070, + 0x2b04d012, + 0xe006d003, + 0x327b460a, + 0x68cce7f3, + 0x19640145, + 0x242f60cc, + 0x2c015c64, + 0x0640d101, + 0x62480e00, + 0x701020ff, + 0x4c09202f, + 0x60200200, + 0x6a484d07, + 0x68623d40, + 0xd03f07d2, + 0xe02b220f, + 0x21000160, + 0x00025500, + 0x0000423d, + 0x21000020, + 0x40045080, + 0x210000e8, + 0x40022080, + 0x40043040, + 0xe000ed00, + 0xe000e280, + 0x400452c0, + 0x00155556, + 0x40046040, + 0x210002c0, + 0x40045180, + 0x0002175f, + 0x210004e0, + 0x00020749, + 0x00020e45, + 0x40042000, + 0x40042100, + 0x0002469d, + 0x4ec363aa, + 0x2801e003, + 0x632edd07, + 0x28001e80, + 0x6862dd1a, + 0xd1f607d2, + 0x2007e006, + 0x20ff63a8, + 0xe0116328, + 0xdd0f2800, + 0x26146862, + 0xd0b64232, + 0x7b524ab8, + 0x60220212, + 0x22084bb7, + 0x4bb7601a, + 0x6248601a, + 0xbdf02001, + 0x19c00098, + 0x64086880, + 0xbdf02000, + 0x460148b2, + 0x7bca3120, + 0x76823060, + 0x73c82002, + 0x470048af, + 0xb50049ad, + 0x71083140, + 0xd01c2831, + 0x4603dc08, + 0xfec0f000, + 0x0e13190a, + 0x0e0e150e, + 0x0e1d1b0e, + 0xd0122835, + 0xd0122836, + 0xd00a2838, + 0xd006283b, + 0x008049a3, + 0x68801840, + 0x48a2bd00, + 0x48a2bd00, + 0x48a2bd00, + 0x48a2bd00, + 0x48a2bd00, + 0x48a2bd00, + 0xb5f0bd00, + 0xb0854c98, + 0x31204621, + 0x7bce9103, + 0x5d092144, + 0xd0012907, + 0xd17e2934, + 0x35804625, + 0x2a00786a, + 0x7d21d07a, + 0xd5770689, + 0x3180498b, + 0x7f09468e, + 0xd0282e01, + 0x0f090709, + 0x702b004b, + 0x025b2301, + 0x2300469c, + 0x93029300, + 0xd0302900, + 0x4f8e0993, + 0xd00b07db, + 0x2b007f3b, + 0x23f7d001, + 0x4b8a401a, + 0x781b3320, + 0xd0012b00, + 0x401a23ef, + 0x0f5b0693, + 0xd00b2b07, + 0x07db08d3, + 0x2200d00c, + 0x4a82767a, + 0x9200321c, + 0x0909e013, + 0xe7d77029, + 0x02922201, + 0xe7f24694, + 0x07d20912, + 0x2201d008, + 0x4a7a767a, + 0x92003220, + 0x02522201, + 0xe0009202, + 0x4a772100, + 0x63d32307, + 0x4a752322, + 0x68523240, + 0xd0fa421a, + 0x6b524a72, + 0x61da4b72, + 0x693b4f72, + 0x43932210, + 0x4b71613b, + 0x0792695a, + 0x4a6fd1fc, + 0x68123240, + 0x06d370aa, + 0x1e9a0edb, + 0xd3002a13, + 0x46222302, + 0x92013260, + 0x76d33008, + 0xd0552900, + 0x7f7f4677, + 0x469600da, + 0x2a041bd2, + 0x2204da00, + 0xd0232e01, + 0x330e0093, + 0xe052e001, + 0x4e60e04e, + 0x467362b3, + 0x485a181b, + 0x434a6203, + 0x45624617, + 0x4667dd00, + 0x9902485b, + 0x99026041, + 0x1e4919c9, + 0x68016081, + 0x43112221, + 0x6a266001, + 0x62261c76, + 0x98036266, + 0x28017bc0, + 0xe00ad006, + 0x4f5000d6, + 0x62be3616, + 0xe7dd011b, + 0x494f4849, + 0xf7ff3040, + 0x2e02fc48, + 0x78aadd06, + 0x98004639, + 0xf85cf000, + 0xe00f2102, + 0x98004639, + 0xfd5cf7ff, + 0x31404946, + 0x9a016ac9, + 0x210077d1, + 0xd0002e01, + 0xf7ff2108, + 0x2103fccc, + 0x77819801, + 0xbdf0b005, + 0x21019a01, + 0x6a217791, + 0x62211c49, + 0xe0026261, + 0x34602100, + 0x4a3777a1, + 0x62912100, + 0x62084931, + 0x7bc09803, + 0xd1e92801, + 0x3040482e, + 0x06c968c1, + 0x2100d5fc, + 0x29021c49, + 0x4930dbfc, + 0xfc0bf7ff, + 0x481ee7dc, + 0x4601b510, + 0x460a3160, + 0x232f7e89, + 0x29025419, + 0x7d01d010, + 0xd5130689, + 0x29016a01, + 0x6ec1dd10, + 0x06c97849, + 0x1e8b0ec9, + 0xd8092b12, + 0x1e5b7d43, + 0xe0067543, + 0xfbfcf7ff, + 0xd0002800, + 0xbd102001, + 0x76d12100, + 0xbd102000, + 0x33804b1b, + 0x7083695b, + 0x22017042, + 0x42910252, + 0x2102dd03, + 0x71017001, + 0x21014770, + 0x47707001, + 0x0000ffff, + 0x21000048, + 0xe000e280, + 0xe000e100, + 0x21000160, + 0x00020f47, + 0x00025500, + 0x2100461d, + 0x21004517, + 0x21004489, + 0x2100442f, + 0x2100437d, + 0x21004171, + 0x21000000, + 0x40045040, + 0x40042100, + 0x400451c0, + 0x40042000, + 0x40045300, + 0x40048000, + 0x40046000, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, + 0x2500b570, + 0x614548ff, + 0xf000207d, + 0x4cfefcfd, + 0x07c06ae0, + 0x62e5d0fc, + 0xf0002082, + 0x48fbfcf5, + 0x07c96ac1, + 0x62c5d0fc, + 0x60a12101, + 0x60a56025, + 0x384048f6, + 0x60056081, + 0xbd706085, + 0x4bf4b530, + 0x68db685b, + 0xd00d2b00, + 0x189c0852, + 0x4def4aef, + 0xe0053240, + 0x079b6853, + 0x6b6bd5fc, + 0x1c405423, + 0xdbf74288, + 0xb5f7bd30, + 0x2400468e, + 0x00c9214b, + 0x49e8468c, + 0x684e4627, + 0x46254623, + 0x62544ae6, + 0x6ad24ae1, + 0x4ae307d1, + 0x68520fc9, + 0x42821b92, + 0x2701d900, + 0x6a524ae0, + 0xd006429a, + 0x684648dd, + 0x46604bde, + 0xb29d6adb, + 0x29014613, + 0x2f00d001, + 0x4ad6d0e6, + 0x6ad16ad0, + 0x0fc006c0, + 0x0fc90689, + 0x29014ed3, + 0x2801d101, + 0x210fd011, + 0x020968b0, + 0x1d404008, + 0x48cc6190, + 0x62c12100, + 0x62012101, + 0x68784fcc, + 0x99026130, + 0xd00e2902, + 0x9802e013, + 0xd1032802, + 0x684048c7, + 0x61486871, + 0x20004671, + 0xf7ff9a02, + 0x2401ff9b, + 0x6871e7ea, + 0x8d892c01, + 0x1a40d01c, + 0x48c160f0, + 0x0a2a6ac0, + 0x0a08b281, + 0xb2c91880, + 0x1889b2ea, + 0x084a0840, + 0x23ff1811, + 0x1a103301, + 0x02001a59, + 0xfc6cf000, + 0x68706170, + 0x8d828873, + 0x18d56931, + 0xe00468f0, + 0x30f01a40, + 0x6879e7e0, + 0x1a096131, + 0xd3fa42a9, + 0x21009d02, + 0xd0052d02, + 0xd1032c01, + 0x1a086931, + 0x1ac11a80, + 0x1a406930, + 0x2c0160f0, + 0x2000d002, + 0xbdfe43c0, + 0xbdfe2000, + 0x4ba6b510, + 0x2402499e, + 0x28002201, + 0x48a4d007, + 0x694861d8, + 0x61484390, + 0x43206948, + 0x48a1e006, + 0x694861d8, + 0x61484310, + 0x43a06948, + 0x499b6148, + 0x6bc83940, + 0x40184b9c, + 0x43032303, + 0x431063cb, + 0xbd1063c8, + 0x9c02b510, + 0x02240112, + 0x3c013cff, + 0x43143a10, + 0x430c1e49, + 0x61cc498b, + 0x4b8a624b, + 0x3b402202, + 0x2200605a, + 0x620a62ca, + 0x02004a87, + 0x79926852, + 0xd0022a02, + 0x61881cc0, + 0x1d00bd10, + 0x7808e7fb, + 0x62c84983, + 0x49804770, + 0x68896849, + 0xd0042900, + 0x18080840, + 0x7800497e, + 0x487a62c8, + 0x38402103, + 0x60416001, + 0x20014976, + 0x60486008, + 0xb5384770, + 0xf7ff4605, + 0x4872ffe8, + 0x62c12100, + 0x62012108, + 0x78234c71, + 0x68a09300, + 0x05004b77, + 0x78620f00, + 0xffb6f7ff, + 0xf7ff2000, + 0x6861ff91, + 0x68082d02, + 0x8dc8d100, + 0x2101462a, + 0xfef9f7ff, + 0xb5f7bd38, + 0x46154966, + 0x684a2000, + 0x46944607, + 0x6ac94960, + 0x496207ce, + 0x68490ff6, + 0x1a8a4662, + 0x428a9900, + 0x2701d900, + 0x6a4c495e, + 0xd0074284, + 0xd0012c00, + 0xe0002001, + 0xf7ff2000, + 0x4620ff69, + 0xd0012e01, + 0xd0e32f00, + 0x21004851, + 0x4a526141, + 0x4e526ad0, + 0x0fc006c0, + 0xd1032d00, + 0x685b4b50, + 0x61636874, + 0xd0012f00, + 0xd01d2800, + 0x462a2401, + 0x99012000, + 0xfea8f7ff, + 0x6ac0484b, + 0xb2810223, + 0xb2ca0a08, + 0x1a101811, + 0x02001a59, + 0xfb88f000, + 0x4a436170, + 0x61316851, + 0x79836870, + 0x432f461f, + 0x2b01d00e, + 0xe01ad014, + 0x68b0230f, + 0x4018021b, + 0x61901d40, + 0x62c14837, + 0x62012101, + 0xe7e82400, + 0x2c008d83, + 0x1ac9d002, + 0xe00731f0, + 0xe0051ac9, + 0xd1042d00, + 0x1ac98d83, + 0x310531ff, + 0x8d8160f1, + 0x23008877, + 0x19c9468c, + 0x68f06932, + 0x4a2ce002, + 0x61326852, + 0x428a1a12, + 0x2d00d3f9, + 0x2c00d006, + 0x6931d004, + 0x46601a09, + 0x1bc31a08, + 0x1ac06930, + 0x2c0060f0, + 0x2000d001, + 0x2000bdfe, + 0xbdfe43c0, + 0x4605b538, + 0xff39f7ff, + 0x2100481a, + 0x210862c1, + 0x4c1a6201, + 0x93007823, + 0x4b2068a0, + 0x0f000500, + 0xf7ff7862, + 0x2000ff07, + 0xfee2f7ff, + 0x2d006861, + 0xd1006808, + 0x462a8dc8, + 0xf7ff2101, + 0xbd38ff52, + 0x4c0db530, + 0x62e52500, + 0x3a100112, + 0x430a1e49, + 0x626361e2, + 0x1c800200, + 0x480961a0, + 0x60012101, + 0x61456942, + 0x32404a06, + 0x68406011, + 0xe0173028, + 0x40041100, + 0x40046000, + 0x40045040, + 0x210053e8, + 0x40043000, + 0x40045300, + 0x400451c0, + 0x40044040, + 0x08180532, + 0x0818070e, + 0xfff000ff, + 0x0000aaaa, + 0x318049ff, + 0xbd306008, + 0x4605b538, + 0xfee5f7ff, + 0x210048fc, + 0x210662c1, + 0x4cfb6201, + 0x78232108, + 0x68a09300, + 0x05004bf9, + 0x78620f00, + 0xffb8f7ff, + 0x48f749f8, + 0x200161c8, + 0xfe8af7ff, + 0x462a6860, + 0x21016800, + 0xfefdf7ff, + 0xb530bd38, + 0x4bf24df2, + 0x35804cf2, + 0xd00e2a40, + 0x58420089, + 0x625a0c12, + 0xb2925842, + 0x1808629a, + 0x0c096841, + 0x684062a1, + 0x6328b280, + 0x00c9bd30, + 0x0c125842, + 0x584262da, + 0x631ab292, + 0x68411808, + 0x62590c09, + 0xb2896841, + 0x68816299, + 0x49e00c0a, + 0x634a31c0, + 0xb2926882, + 0x68c1638a, + 0x62a10c09, + 0xe7e168c0, + 0x4606b5f0, + 0x2080b089, + 0xfa8ef000, + 0x2500b662, + 0x204f4cd2, + 0x60e56066, + 0x00c049d6, + 0x47889501, + 0x68606125, + 0x290079c1, + 0x21ffd001, + 0x30203101, + 0x4acf60a1, + 0x62117901, + 0x21207902, + 0xd1002a00, + 0x70212140, + 0x21027980, + 0xd1002800, + 0x48ca2101, + 0x47807061, + 0x49c06860, + 0x79403020, + 0x62c83180, + 0x478048c6, + 0x80602000, + 0x384048bf, + 0x48c56bc0, + 0x610149c3, + 0x90002000, + 0x684849b8, + 0x24003020, + 0x46267c40, + 0x46259405, + 0x90029403, + 0x48b3e20c, + 0x4ab02700, + 0x68506147, + 0x31504601, + 0x48ade001, + 0x42886840, + 0x48b8d3fb, + 0x48b64780, + 0x48b76147, + 0x7ac07ac1, + 0x0fc907c9, + 0x40102202, + 0xd0024301, + 0xb00948b3, + 0x48a5bdf0, + 0x80412100, + 0x97076847, + 0x7cf93720, + 0x90060860, + 0xfa32f000, + 0xd1142900, + 0x42a09805, + 0x9802d011, + 0xd03b2800, + 0x07c09902, + 0x0fc00849, + 0x28009102, + 0x7cb8d002, + 0x90024048, + 0x98027c39, + 0xfa1cf000, + 0x9807460d, + 0x6b409405, + 0x5bc200ef, + 0x428a9900, + 0x1db9d02e, + 0x1d395a43, + 0x5c439300, + 0x5c421cb9, + 0x5c411cf9, + 0xf000200e, + 0x488afa0d, + 0x68402201, + 0x6b402300, + 0x5bc04611, + 0xf0000400, + 0x488dfa09, + 0x48924780, + 0x29037801, + 0x4882d1fc, + 0x8f096841, + 0x497e8041, + 0x46026848, + 0xe0073238, + 0x7c381c6d, + 0x42a8b2ed, + 0x2500d8cd, + 0x6848e7cb, + 0xd3fc4290, + 0x68404878, + 0x5bc06b40, + 0x48799000, + 0x68813840, + 0xf000207e, + 0x4873f9eb, + 0x6a386847, + 0xd0062800, + 0x46200041, + 0xf9d0f000, + 0xd0052900, + 0x496de014, + 0x780a69b8, + 0xe0334621, + 0xd00b2c00, + 0x30204638, + 0x07ca7fc1, + 0x2201d018, + 0x43917782, + 0x496f77c1, + 0x608802d0, + 0x900469b8, + 0x90076a38, + 0x46200041, + 0xf9b2f000, + 0x42819807, + 0x2c00d113, + 0x4638d00f, + 0x7fc13020, + 0xd401078a, + 0xe7664869, + 0x77822202, + 0x401122fd, + 0x200177c1, + 0x02c04960, + 0x69f86088, + 0x46209004, + 0xf0006a39, + 0x4852f997, + 0x98047802, + 0xfec1f7ff, + 0xd1042c00, + 0x6840484e, + 0x28027980, + 0x9806d00c, + 0x484b9001, + 0x79806840, + 0xd0072801, + 0x28004f48, + 0x2802d058, + 0xe078d07e, + 0xe12f2402, + 0xf7ff4620, + 0xb280fe87, + 0x48414684, + 0x6ac33040, + 0x68504a40, + 0x98016907, + 0x1d4800c1, + 0x6850543b, + 0x1d086903, + 0x4660541d, + 0xd00e2800, + 0x20006852, + 0x691243c0, + 0x50502c00, + 0xe002d167, + 0xb2a41ca4, + 0x9803e053, + 0x90031c40, + 0x6857e04f, + 0x5dc02027, + 0xd0012801, + 0xe0146950, + 0x30804832, + 0x071b6a83, + 0x61530f1b, + 0x05806a80, + 0x2b070e80, + 0x3b10dd01, + 0x281f6153, + 0x3840dd01, + 0x0100b200, + 0x010018c0, + 0x30ff6150, + 0x30014b33, + 0xd3014298, + 0x61502000, + 0x30804824, + 0x69536a40, + 0x18c00200, + 0x5058693b, + 0xb2816950, + 0xe0ca207f, + 0xf7ff4620, + 0xb281fddf, + 0x30404817, + 0x48176ac3, + 0x69076840, + 0x00c09801, + 0x54bb1d42, + 0x1d034a13, + 0x29006852, + 0x54d56912, + 0x4910d04e, + 0x68492200, + 0x690943d2, + 0x500a2c00, + 0x1c76d0af, + 0x2c01b2b6, + 0xf7ffd8a8, + 0x4809fbf5, + 0x8d386847, + 0xe00042b0, + 0xd303e040, + 0x99038d7a, + 0xd27e428a, + 0x42884914, + 0xe054e028, + 0x40043000, + 0x40046000, + 0x210053e8, + 0x0000aaaa, + 0x08180532, + 0x40044040, + 0x40045140, + 0x40045300, + 0x0000424f, + 0x00009083, + 0x00004be3, + 0x0000c210, + 0x40041100, + 0x00000de5, + 0x21000128, + 0x04040003, + 0x210002e4, + 0x04060003, + 0x00000201, + 0x0000ffff, + 0x8d78d102, + 0xd06f4288, + 0x484d2101, + 0x60810449, + 0xe684484c, + 0x21004a4c, + 0x69126852, + 0xe75f5011, + 0xf7ff4620, + 0xb282fcc6, + 0x46946878, + 0x98016903, + 0x00c04639, + 0x549d1d02, + 0x6ad34a44, + 0x6917687a, + 0x54bb1d42, + 0x2a004662, + 0x6849d00a, + 0x43d22200, + 0x2c026909, + 0xd800500a, + 0x1c76e745, + 0xe73fb2b6, + 0x68494939, + 0x3120468c, + 0x290179c9, + 0x4938d125, + 0x07136a8a, + 0x0f1b4a37, + 0x6a896997, + 0x0f3f073f, + 0x69920589, + 0x05920e89, + 0x2b070e92, + 0x3b10dd00, + 0xdd002f07, + 0x291f3f10, + 0x3940dd01, + 0x2a1fb209, + 0x3a40dd03, + 0xe01fe000, + 0x0109b212, + 0x19c918c9, + 0x18890112, + 0x4924010a, + 0x4923614a, + 0x694a4b26, + 0x320132ff, + 0xd301429a, + 0x614a2200, + 0x6a524a20, + 0x0212694b, + 0x466218d3, + 0x50136912, + 0xb2816948, + 0xf0002083, + 0xe6fbf873, + 0x98018fb9, + 0xf856f000, + 0xd1072900, + 0x28009801, + 0x8778d004, + 0x48102101, + 0x608103c9, + 0x68414810, + 0x42a18889, + 0xe5ecd900, + 0x480b2101, + 0x60810409, + 0x1e49480b, + 0x8d026840, + 0xd103428a, + 0x42888d40, + 0xe5d3d100, + 0x98014906, + 0x87486849, + 0xf0002081, + 0x2000f825, + 0x0000e5ef, + 0x40041100, + 0x04030003, + 0x210053e8, + 0x40046040, + 0x400451c0, + 0x40045080, + 0x00000201, + 0x49068800, + 0xd1064288, + 0x21004805, + 0x49058501, + 0x20016241, + 0x20824770, + 0x00004770, + 0x00006801, + 0x21000108, + 0x21004159, + 0x4801b403, + 0xbd019001, + 0x00003cc3, + 0x4801b403, + 0xbd019001, + 0x0000937d, + 0x4801b403, + 0xbd019001, + 0x00009361, + 0x4801b403, + 0xbd019001, + 0x0000867b, + 0x4801b403, + 0xbd019001, + 0x000049a3, + 0x4801b403, + 0xbd019001, + 0x00003c8f, + 0x4801b403, + 0xbd019001, + 0x00003ca9, + 0x4674b430, + 0x78251e64, + 0x42ab1c64, + 0x461dd200, + 0x005b5d63, + 0xbc3018e3, + 0x00004718, + 0x08180532, + 0x0818070e, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; +#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS 1261 + +CPE_PATCH_TYPE patchCpeHd[] = { + 0x00000000, +}; +#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS 1 + +#define _NWORD_PATCHSYS_MULTI_PROTOCOL_RTLS 0 + + + +#ifndef _MULTI_PROTOCOL_RTLS_SYSRAM_START +#define _MULTI_PROTOCOL_RTLS_SYSRAM_START 0x20000000 +#endif + +#ifndef _MULTI_PROTOCOL_RTLS_CPERAM_START +#define _MULTI_PROTOCOL_RTLS_CPERAM_START 0x21000000 +#endif + +#define _MULTI_PROTOCOL_RTLS_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _MULTI_PROTOCOL_RTLS_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET 0x03D4 +#define _MULTI_PROTOCOL_RTLS_IRQPATCH_OFFSET 0x0480 +#define _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET 0x404C + +#define _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR +static uint8_t bMultiProtocolRtlsPatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterMultiProtocolRtlsCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS > 0) + uint32_t *pPatchVec = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageMultiProtocolRtls, sizeof(patchImageMultiProtocolRtls)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolRtlsCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolRtlsSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureMultiProtocolRtlsPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET); + + + pPatchTab[1] = 0; + pPatchTab[18] = 1; + pPatchTab[81] = 2; + pPatchTab[26] = 3; + pPatchTab[76] = 4; + pPatchTab[62] = 5; + pPatchTab[64] = 6; + pPatchTab[91] = 7; + pPatchTab[79] = 8; + pPatchTab[168] = 9; +} + +PATCH_FUN_SPEC void applyMultiProtocolRtlsPatch(void) +{ +#ifdef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR + enterMultiProtocolRtlsSysPatch(); + enterMultiProtocolRtlsCpePatch(); +#else + if (!bMultiProtocolRtlsPatchEntered) + { + enterMultiProtocolRtlsSysPatch(); + enterMultiProtocolRtlsCpePatch(); + bMultiProtocolRtlsPatchEntered = 1; + } +#endif + enterMultiProtocolRtlsCpeHdPatch(); + configureMultiProtocolRtlsPatch(); +} + +PATCH_FUN_SPEC void refreshMultiProtocolRtlsPatch(void) +{ + enterMultiProtocolRtlsCpeHdPatch(); + configureMultiProtocolRtlsPatch(); +} + +#ifndef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR +PATCH_FUN_SPEC void cleanMultiProtocolRtlsPatch(void) +{ + bMultiProtocolRtlsPatchEntered = 0; +} +#endif + +PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol_rtls(void) +{ + applyMultiProtocolRtlsPatch(); +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H + diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h index c0ee68329..e9baefae1 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h +++ b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h @@ -1,11 +1,11 @@ /****************************************************************************** * Filename: rf_patch_cpe_prop.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ +* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ +* Revision: $Revision: 18889 $ * * Description: RF core patch for proprietary radio support ("PROP" API command set) in CC13x2 and CC26x2 * -* Copyright (c) 2015-2018, Texas Instruments Incorporated +* Copyright (c) 2015-2019, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -70,341 +70,51 @@ extern "C" CPE_PATCH_TYPE patchImageProp[] = { - 0x21004185, - 0x210041a5, - 0x2100421d, - 0x210042c5, - 0x2100436d, - 0x21004099, - 0x210040bd, - 0x210040df, - 0x210040cd, - 0x210043cd, - 0x210043e7, - 0x21004111, - 0x2100412d, - 0x2100413d, - 0x210044e5, - 0x2100414d, - 0xb081b5ff, - 0x9d0a4803, - 0xb5f84700, - 0x48024684, - 0x47004613, - 0x00007f43, - 0x00005145, - 0x460cb5f7, - 0x47084900, - 0x0000681d, - 0x4801b510, - 0x00004700, - 0x000009df, - 0x460db5f8, - 0x4b0a4616, - 0x290c6d59, - 0x4b03d104, - 0x78192408, - 0x70194321, - 0x47084901, - 0x21000340, - 0x0000699d, - 0x46864810, - 0x21804801, - 0x47706041, - 0x40045000, - 0x2270480d, - 0x43916801, - 0x43112240, - 0x480b6001, - 0x480b4700, - 0x460c7801, - 0x43912208, - 0xf0007001, - 0x4807f803, - 0xbd107004, - 0xf7ffb510, - 0x4801ffe3, - 0x470038c8, - 0x000056cb, - 0x40043018, - 0x0000710f, - 0x210000b3, - 0x49044803, - 0x05c068c0, - 0x47880fc0, + 0x21004059, + 0x210040c3, + 0x21004085, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, 0x47084902, - 0x21000340, - 0x000087d1, - 0x000053cd, - 0xf0002000, - 0x4604f969, - 0x47004800, - 0x0000545b, - 0xf0002004, - 0x4605f961, - 0x47004800, - 0x0000533b, - 0xf811f000, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, 0x296cb2e1, 0x2804d00b, 0x2806d001, - 0x4907d107, + 0x490ed107, 0x07c97809, 0x7821d103, 0xd4000709, - 0xb0032002, + 0x490b2002, + 0x210c780a, + 0xd0024211, + 0x22804909, + 0xb003600a, 0xb5f0bdf0, - 0x4902b083, - 0x00004708, + 0x4907b083, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, 0x210000c8, - 0x0003071b, - 0x4905b672, - 0x22206808, - 0x600a4302, - 0x6ad24a03, - 0xb6626008, - 0x4770b250, - 0x40040000, - 0x40046040, - 0x4614b5f8, - 0x9b06461a, - 0x46139300, - 0xf7ff4622, - 0x9000ff57, - 0xd12d2800, - 0x6848495f, - 0xd0292800, - 0x00498809, - 0x43411b09, - 0x68c0485c, - 0x00640844, - 0x20187922, - 0xb2c61a80, - 0x04802001, - 0x0cc71808, - 0x46317965, - 0xf0004856, - 0x4855f9a3, - 0x19832201, - 0x408a1e69, - 0x21182000, - 0xe0071b8e, - 0x19090041, - 0x437988c9, - 0x40e91889, - 0x1c405419, - 0xdcf54286, - 0x4780484c, - 0xbdf89800, - 0xf7ffb570, - 0x4a46ff26, - 0x49492300, - 0x60534604, - 0x25136808, - 0x01ed8800, - 0x2e030b06, - 0x0760d00d, - 0x6808d43f, - 0x290c7bc1, - 0xdc0fd028, - 0xd0132904, - 0xd0142905, - 0xd10d290a, - 0xb2c0e01d, - 0xd0032806, - 0x8c006808, - 0xe02d8010, - 0xe02b8015, - 0xd018290f, - 0xd019291e, - 0xe0048015, - 0x01802013, - 0x4835e000, - 0x48308010, - 0x29c068c1, - 0x29d8d010, - 0x39ffd010, - 0xd1173939, - 0x20ffe00a, - 0xe7f130e7, - 0x309620ff, - 0x20ffe7ee, - 0xe7eb3045, - 0xe7e920a2, - 0xe000492a, - 0x6051492a, - 0x60c1492a, - 0x48232118, - 0xf93cf000, - 0x8013e000, - 0xbd704620, - 0x4604b5f8, - 0x4e1c481d, - 0x88003040, - 0x0a80460d, - 0xd00407c0, - 0x08644821, - 0x43447900, - 0x8830e025, - 0xd0222800, - 0x19000960, - 0xfec8f7ff, - 0x20014607, - 0x0240491b, - 0x46024788, - 0x1bc02005, - 0x40848831, - 0x18230848, - 0x62034817, - 0x21016241, - 0x430d61c1, - 0x60cd490a, - 0x07c969c1, - 0x6a80d1fc, - 0x60704910, - 0x39124610, - 0x46384788, - 0x2000bdf8, - 0x46206070, - 0xfea4f7ff, - 0x0000bdf8, - 0x21004540, - 0x21000028, - 0x21000000, - 0x0000764d, - 0x21000108, - 0x000003cd, - 0x00063b91, - 0x0003fd29, - 0x000090fd, - 0x21000340, - 0x000040e5, - 0x40044100, - 0x4c03b510, - 0xfe8cf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x480eb570, - 0x4c0e6ac0, - 0x0f000700, - 0x28012502, - 0x2804d005, - 0x280cd00b, - 0x280dd001, - 0x6960d106, - 0x616043a8, - 0x49072001, - 0x60080280, - 0x4906bd70, - 0x47882001, - 0x43286960, - 0xbd706160, - 0x40046000, - 0x40041100, - 0xe000e180, - 0x00007d05, - 0x780a490b, - 0xd1042aff, - 0x7ad24a0a, - 0x0f120712, - 0x4908700a, - 0x75883140, - 0x49054770, - 0x29ff7809, - 0x0900d005, - 0x43080100, - 0x31404902, - 0x47707588, - 0x210002a5, - 0x40086200, - 0x4c19b570, - 0x7ba14606, - 0xf820f000, - 0x7be14605, - 0xf0004630, - 0x4915f81b, - 0x78094604, - 0x070a2028, - 0x2d01d401, - 0x2038d100, - 0xd40106c9, - 0xd1012c01, - 0x43082140, - 0x4788490e, - 0xd0012dff, - 0x6145480d, - 0xd0012cff, - 0x61c4480c, - 0xbd704808, - 0xd0082900, - 0xd00629ff, - 0x070840c1, - 0x281c0ec0, - 0x2001d100, - 0x20ff4770, - 0x00004770, - 0x210000a8, - 0x21000340, - 0x000040e5, - 0x40045040, - 0x40046000, - 0x4e26b5f1, - 0x79742000, - 0x60f068f7, - 0x46254824, - 0x05c08800, - 0x2004d502, - 0x71744304, - 0x4b21221d, - 0x98002100, - 0x28004798, - 0x68f1d109, - 0x29001f03, - 0x9900d004, - 0xb2ca6809, - 0xd0032a2b, - 0x60f74618, - 0xbdf87175, - 0x0f890589, - 0xd1022902, - 0x400c21fb, - 0x21047174, - 0x400d400c, - 0xd0f242ac, - 0x03094a12, - 0xbdf86091, - 0x4604b570, - 0x28158800, - 0x490fd003, - 0x47884620, - 0x2075bd70, - 0x00c0490d, - 0x46054788, - 0xf7ff6860, - 0x2800ffbd, - 0x2487d001, - 0x2401e000, - 0x46284907, - 0x4788311c, - 0xbd704620, - 0x21000340, - 0x21000284, - 0x00004a99, - 0x40041100, - 0x0000270f, - 0x000045c7, - 0x4801b403, - 0xbd019001, - 0x000089dd, - 0x00000000, - 0x00000000, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x00031b23, }; -#define _NWORD_PATCHIMAGE_PROP 329 +#define _NWORD_PATCHIMAGE_PROP 38 + +#define _NWORD_PATCHCPEHD_PROP 0 #define _NWORD_PATCHSYS_PROP 0 -#define _IRQ_PATCH_0 0x21004381 #ifndef _PROP_SYSRAM_START @@ -417,10 +127,12 @@ CPE_PATCH_TYPE patchImageProp[] = { #define _PROP_SYS_PATCH_FIXED_ADDR 0x20000000 -#define _PROP_PARSER_PATCH_TAB_OFFSET 0x0390 -#define _PROP_PATCH_TAB_OFFSET 0x0398 -#define _PROP_IRQPATCH_OFFSET 0x0434 -#define _PROP_PATCH_VEC_OFFSET 0x4024 +#define _PROP_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _PROP_PATCH_TAB_OFFSET 0x03D4 +#define _PROP_IRQPATCH_OFFSET 0x0480 +#define _PROP_PATCH_VEC_OFFSET 0x404C + +#define _PROP_PATCH_CPEHD_OFFSET 0x04E0 #ifndef _PROP_NO_PROG_STATE_VAR static uint8_t bPropPatchEntered = 0; @@ -435,35 +147,27 @@ PATCH_FUN_SPEC void enterPropCpePatch(void) #endif } +PATCH_FUN_SPEC void enterPropCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_PROP > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_PROP_CPERAM_START + _PROP_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + PATCH_FUN_SPEC void enterPropSysPatch(void) { } PATCH_FUN_SPEC void configurePropPatch(void) { - uint8_t *pParserPatchTab = (uint8_t *) (_PROP_CPERAM_START + _PROP_PARSER_PATCH_TAB_OFFSET); uint8_t *pPatchTab = (uint8_t *) (_PROP_CPERAM_START + _PROP_PATCH_TAB_OFFSET); - uint32_t *pIrqPatch = (uint32_t *) (_PROP_CPERAM_START + _PROP_IRQPATCH_OFFSET); - pPatchTab[84] = 0; - pPatchTab[142] = 1; - pPatchTab[66] = 2; - pPatchTab[102] = 3; - pPatchTab[28] = 4; - pPatchTab[104] = 5; - pPatchTab[75] = 6; - pPatchTab[73] = 7; - pPatchTab[117] = 8; - pPatchTab[105] = 9; - pPatchTab[106] = 10; - pPatchTab[70] = 11; - pPatchTab[71] = 12; - pPatchTab[69] = 13; - pParserPatchTab[0] = 14; - pPatchTab[60] = 15; - - pIrqPatch[21] = _IRQ_PATCH_0; + pPatchTab[76] = 0; + pPatchTab[62] = 1; + pPatchTab[64] = 2; } PATCH_FUN_SPEC void applyPropPatch(void) @@ -479,11 +183,13 @@ PATCH_FUN_SPEC void applyPropPatch(void) bPropPatchEntered = 1; } #endif + enterPropCpeHdPatch(); configurePropPatch(); } PATCH_FUN_SPEC void refreshPropPatch(void) { + enterPropCpeHdPatch(); configurePropPatch(); } @@ -499,7 +205,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_prop(void) applyPropPatch(); } -#undef _IRQ_PATCH_0 //***************************************************************************** // diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_bt5.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_bt5.h deleted file mode 100644 index 951834610..000000000 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_bt5.h +++ /dev/null @@ -1,623 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_mce_bt5.h -* Revised: $Date: 2017-12-01 13:47:22 +0100 (fr, 01 des 2017) $ -* Revision: $Revision: 18103 $ -* -* Description: RF core patch for Bluetooth 5 support in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -#ifndef _RF_PATCH_MCE_BT5_H -#define _RF_PATCH_MCE_BT5_H - -#include -#include "../inc/hw_types.h" - -#ifndef MCE_PATCH_TYPE -#define MCE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_MCERAM_BASE -#define RFC_MCERAM_BASE 0x21008000 -#endif - -#ifndef MCE_PATCH_MODE -#define MCE_PATCH_MODE 0 -#endif - -MCE_PATCH_TYPE patchBt5Mce[511] = { - 0x2dee609e, - 0x2dc22dce, - 0x2fef0f54, - 0x5f970fef, - 0x5000179d, - 0x048005a0, - 0x40007f40, - 0x0f080128, - 0x04000800, - 0x404003ff, - 0x00002e20, - 0x00130003, - 0x00210010, - 0x00320022, - 0x00430031, - 0x00500040, - 0x00620053, - 0x00710061, - 0x005f0072, - 0x005d0060, - 0x005b005e, - 0x0059005c, - 0x0055005a, - 0x00570056, - 0x00cc0058, - 0x003c00c3, - 0x00000033, - 0x00020001, - 0x04000003, - 0x00180800, - 0x00030008, - 0x000a001a, - 0x0011002c, - 0x0003003e, - 0x00180008, - 0x0011001a, - 0x000a002c, - 0x4000003e, - 0x0000000c, - 0x00091488, - 0x000105f9, - 0x008b8000, - 0x0f500080, - 0x0a1d0000, - 0x00000590, - 0x04000005, - 0x00c17b20, - 0x000f0000, - 0x017f7f27, - 0x000c8000, - 0x14980000, - 0x05f90009, - 0x80000000, - 0x0080008b, - 0x00000f70, - 0x0590121d, - 0x00050000, - 0x7b200400, - 0x000000c1, - 0x7f26000f, - 0x4000017f, - 0x000ca00c, - 0x00030387, - 0x050140cd, - 0x01ee8000, - 0x06700080, - 0x091e0000, - 0x00560500, - 0x0000000c, - 0x00505014, - 0x001f0000, - 0x00007f7f, - 0x7f7f8804, - 0x00002c7f, - 0x00000000, - 0x009f0000, - 0x2e204040, - 0xfd900c03, - 0x0000783c, - 0x720e720d, - 0x7210720f, - 0xa4e5a35d, - 0xb63c67d8, - 0x7100b0d0, - 0xb110a0d0, - 0x8162721b, - 0x39621020, - 0x00200630, - 0x11011630, - 0x6c011401, - 0x60cb60c2, - 0x613c60f2, - 0x60cd60c2, - 0x624e61d9, - 0x60d360c2, - 0x616460f2, - 0x60c31220, - 0x73111210, - 0x73137312, - 0x001081b1, - 0xb07091b0, - 0xc4b160a5, - 0xc79160d4, - 0xc1fb78bc, - 0xc540c302, - 0xc62160d8, - 0xc5fb78ac, - 0xc460c302, - 0x6f131820, - 0x16116e23, - 0x68d91612, - 0x9c8c94eb, - 0x1e008170, - 0xc03044c2, - 0xc1f092b0, - 0xc63292d0, - 0x1820c9c0, - 0x120340ef, - 0x16126e23, - 0x830068ec, - 0x60c29990, - 0x7291b005, - 0x91f0c100, - 0xb120b128, - 0xb111b113, - 0x7100b0e8, - 0xa0e8b128, - 0xb910b230, - 0x99308c80, - 0x84a2b111, - 0xc0f384b4, - 0x7100b0d1, - 0xb002b012, - 0xa0d1b111, - 0x722c7291, - 0xb013b630, - 0xb0e0b003, - 0xb1207100, - 0x92c08170, - 0x96408190, - 0xb1207100, - 0x964292c3, - 0xb1207100, - 0x71009644, - 0xa0e0b120, - 0xb633a630, - 0x7100b0d3, - 0xa0d3b113, - 0x9910c030, - 0x9930c020, - 0x7100b0d1, - 0xa0d1b111, - 0xa0037291, - 0x7263a002, - 0x73067305, - 0x72917391, - 0xc7c0a230, - 0x60c29010, - 0x65bd658d, - 0x710065c4, - 0x7393a910, - 0x8b4fb910, - 0x3d8f316f, - 0x7313720f, - 0x00000000, - 0xb231b074, - 0x970fb35d, - 0xa044a4e5, - 0x67d0b064, - 0x67e5c2b1, - 0x455722f3, - 0x971f7100, - 0x9933c0a3, - 0xa2359117, - 0xb0787100, - 0x67d4c243, - 0xc030453c, - 0x60c267f7, - 0x7860658d, - 0xc5f065be, - 0x65c46968, - 0xb115b0d5, - 0x7100c031, - 0x22508090, - 0xb07445ce, - 0x7393a910, - 0x720fb910, - 0xb2317313, - 0xb35da0d5, - 0x39208b40, - 0xa4e59700, - 0xb064a044, - 0xb23467d0, - 0x67e5c261, - 0x458722f3, - 0xb0787100, - 0x67d4c2a3, - 0x67f7c040, - 0x84b060c2, - 0x997095a0, - 0x100e8980, - 0x959084a0, - 0x89809970, - 0xc080140e, - 0xc080180e, - 0x8351180e, - 0x39213981, - 0x16310661, - 0x14101100, - 0x311e6c00, - 0x318e311e, - 0x972e398e, - 0x22308240, - 0xb0d545b0, - 0xb1157100, - 0x61a8a0d5, - 0x91e0c100, - 0x99107810, - 0x789a13e7, - 0xc540b4e5, - 0xb0029010, - 0xb006b004, - 0x78507000, - 0x90309050, - 0x90607870, - 0x70009040, - 0xb06cb235, - 0xb089b011, - 0xa0d1b4e5, - 0xb13da0d0, - 0x7000b0fd, - 0x8a439a31, - 0x31338a54, - 0x31343d63, - 0x96933d64, - 0xb05396a4, - 0x8990616b, - 0x73119300, - 0x721f7312, - 0x81707291, - 0x819092c0, - 0xc0509640, - 0xc15c67f7, - 0xc07ec31d, - 0xb0e8c008, - 0xb1287100, - 0xb230a0e8, - 0x8c80b910, - 0xb1119930, - 0x7100b0d1, - 0xb634a0d1, - 0xb002b0e1, - 0xb003b012, - 0xb121b013, - 0xa0e17100, - 0xb630a634, - 0xb0d3b113, - 0xb0e0b120, - 0xc0f084a4, - 0x663f104f, - 0x6a063914, - 0xc0f084b4, - 0x663f104f, - 0x6a0c3914, - 0xc0408c94, - 0x663f104f, - 0x6a123914, - 0x22048c94, - 0x81df4624, - 0x8210663f, - 0x421f2210, - 0xc0306219, - 0x663fc00f, - 0x62316a20, - 0xc01ec35d, - 0x663f81df, - 0x22108210, - 0x6224422c, - 0xc00fc030, - 0x6a2d663f, - 0xa0e16231, - 0x9910c030, - 0x9930c040, - 0xb0d1b111, - 0xa0d17100, - 0xa0037291, - 0x7223a002, - 0x061f60c2, - 0x148f313f, - 0x6ff214cf, - 0x39481028, - 0x14d20632, - 0x71006f23, - 0x92ceb120, - 0x70009643, - 0x67f7c060, - 0x93008990, - 0xdb007265, - 0xb31d9660, - 0x91e0c100, - 0x9320c0c0, - 0x97507b90, - 0xc3b1c100, - 0x6f13c7d2, - 0x16116e23, - 0x6a5f1612, - 0x677b67a8, - 0x22308240, - 0xb0d54670, - 0xb1157100, - 0x6266a0d5, - 0x67f7c070, - 0x7840b235, - 0x00018001, - 0x90109001, - 0x90307850, - 0x78809050, - 0x90609040, - 0x9380df20, - 0xb4e5b072, - 0xb63bb3f0, - 0x99107820, - 0x67f7c080, - 0xb10c7393, - 0xb13db14c, - 0xb10fb0fd, - 0xb008b14f, - 0xa0087100, - 0xa914b914, - 0xa910b14c, - 0x7100791e, - 0x894fb910, - 0x22c080c0, - 0x22f047f1, - 0xa0fd468c, - 0xa0447210, - 0xb074b064, - 0xb230b231, - 0x720f7232, - 0xa049a048, - 0xa009a04a, - 0x9930c200, - 0xb0d1b111, - 0xa0d17100, - 0x22208780, - 0xb0e74716, - 0xb127c1f0, - 0x6ab57100, - 0xa4e5b04f, - 0xb073a31d, - 0x9320c0c0, - 0xb041b04b, - 0x67f7c090, - 0x1e038183, - 0x895b42c2, - 0x18b08940, - 0x063c100c, - 0x31333920, - 0xc3201803, - 0x99331803, - 0x7830a910, - 0xb1119910, - 0xb0d1b910, - 0x46ff22f3, - 0x398a830a, - 0x866b395a, - 0x8650313b, - 0x39503980, - 0x1204000b, - 0x80907100, - 0x46ff2210, - 0x86528301, - 0xba3a8663, - 0x31858b25, - 0x1c543125, - 0x4af542fc, - 0x14b214a1, - 0x16135ef9, - 0x18a162f9, - 0x5af918b2, - 0x93011a13, - 0x96639652, - 0xb1271054, - 0xb23362e2, - 0x78d4b750, - 0x78c49794, - 0xc0e097a4, - 0x6b06b760, - 0x7223a0d1, - 0x8af473a3, - 0x9a14d0a0, - 0xa0e767f7, - 0x72047203, - 0x73067305, - 0x60c27291, - 0xc0d0a4e5, - 0x1cfe9930, - 0xd6a0471d, - 0xd690631f, - 0x93800000, - 0xb072b073, - 0x7ba0b04b, - 0xa0e79750, - 0xb0d1b111, - 0x7100b1b3, - 0xb04fb06f, - 0xb041b04d, - 0x9320c0c0, - 0x8af0ba39, - 0x97003110, - 0x7393b960, - 0x6b37cf00, - 0xa00ab01a, - 0x67f7c0b0, - 0x1e038183, - 0x895b433c, - 0x18b08940, - 0x18033133, - 0x180378e0, - 0xa9109933, - 0xb910b111, - 0x476722f3, - 0x89a189a0, - 0x434d1c10, - 0xb127b0e7, - 0x1201b750, - 0x80a07100, - 0x43632270, - 0x1e11b127, - 0x1611435d, - 0x89a06354, - 0x89b09790, - 0xb76097a0, - 0x80901201, - 0x43542210, - 0xb233a0e7, - 0xb750a04d, - 0x97a478f4, - 0x97947904, - 0xb760c0e0, - 0xa0d16b6f, - 0xc0c07223, - 0x720367f7, - 0x73057204, - 0x72917306, - 0xc15c60c2, - 0xc00ac00d, - 0xc070c008, - 0xc2db84ae, - 0x67996fb7, - 0x161b6b83, - 0xc0706fb7, - 0x6799c00a, - 0x84be6b89, - 0x6fb7161b, - 0xc00ac070, - 0x6b906799, - 0x6fb7161b, - 0xc00ac070, - 0x6b966799, - 0x10ef7000, - 0x313f061f, - 0x14cf148f, - 0x10286ff2, - 0x06323948, - 0x3f1a002a, - 0x6e7a3f1a, - 0x7000391e, - 0xc00dc15c, - 0xc0e0c008, - 0xc25b84ae, - 0x061f10ef, - 0x148f313f, - 0x6ff214cf, - 0x39481028, - 0x47ba0632, - 0x63c3ccca, - 0x47be1e12, - 0x63c3cc3a, - 0x47c21e22, - 0x63c3c3ca, - 0x2200c33a, - 0x10a643c7, - 0x6fb763cc, - 0x006a318a, - 0x161b6e7a, - 0x6bae391e, - 0x7000b064, - 0x1e038183, - 0x700043d0, - 0x91179933, - 0xa35d7100, - 0x73917223, - 0x72037291, - 0x72637204, - 0x9000c030, - 0x9010ffc0, - 0x73067305, - 0x895b7000, - 0x18b08940, - 0x18033123, - 0x99331813, - 0xb111a910, - 0xb0d1b910, - 0xb9147000, - 0xb14ca914, - 0x792ea910, - 0x9a006295, - 0x220089f0, - 0xb9e047f8, - 0x00007000 -}; - -PATCH_FUN_SPEC void rf_patch_mce_bt5(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 511; i++) { - HWREG(RFC_MCERAM_BASE + 4 * i) = patchBt5Mce[i]; - } -#else - const uint32_t *pS = patchBt5Mce; - volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 63; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; -#endif -} - -#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_genfsk.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_genfsk.h deleted file mode 100644 index d6074376a..000000000 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_genfsk.h +++ /dev/null @@ -1,591 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_mce_genfsk.h -* Revised: $Date: 2018-01-15 06:15:14 +0100 (ma, 15 jan 2018) $ -* Revision: $Revision: 18170 $ -* -* Description: RF core patch for Generic FSK support in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_MCE_GENFSK_H -#define _RF_PATCH_MCE_GENFSK_H - -#include -#include "../inc/hw_types.h" - -#ifndef MCE_PATCH_TYPE -#define MCE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_MCERAM_BASE -#define RFC_MCERAM_BASE 0x21008000 -#endif - -#ifndef MCE_PATCH_MODE -#define MCE_PATCH_MODE 0 -#endif - -MCE_PATCH_TYPE patchGenfskMce[484] = { - 0x2fcf603c, - 0x030c3f9d, - 0x070c680a, - 0xfff0003f, - 0xff0000ff, - 0x00c08080, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00070003, - 0x00003d1f, - 0x04000000, - 0x0000000f, - 0x000b0387, - 0x004340f4, - 0x00828000, - 0x06700080, - 0x091e0000, - 0x00540510, - 0x02000005, - 0x00613e10, - 0x002f0000, - 0x027f3030, - 0x00000000, - 0x00000000, - 0x00000000, - 0x0000aa00, - 0x00000000, - 0x00000000, - 0x72637223, - 0xa4e5a35d, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72917391, - 0xffc0b008, - 0xa0089010, - 0x720e720d, - 0x7210720f, - 0x7100b0d0, - 0xa0d0b110, - 0x8162721b, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x60796078, - 0x637960f8, - 0x60786078, - 0x60786078, - 0x60796078, - 0x637960f8, - 0x60786078, - 0x60786078, - 0x72231210, - 0x73127311, - 0x81b17313, - 0x91b00010, - 0x6050b070, - 0xc030606e, - 0xc14167c1, - 0xc4e0c2b2, - 0x6f131820, - 0x16116e23, - 0x687f1612, - 0x9c807830, - 0x9c907840, - 0x9ca07850, - 0x948078a0, - 0xc4f29490, - 0x1820c750, - 0x12034095, - 0x16126e23, - 0x78b06892, - 0x606e9990, - 0x81907291, - 0x81709640, - 0x2a703980, - 0x16111001, - 0x84b484a2, - 0xc0f5c0f3, - 0x1c01c200, - 0xc10040bd, - 0x40b31c10, - 0x10134cb5, - 0x18301803, - 0x1a101a13, - 0x68b03912, - 0x13f360bd, - 0x13f360bd, - 0xc1001015, - 0x1a151850, - 0x39141a10, - 0xb0e868bb, - 0xb1287100, - 0xb230a0e8, - 0x8990b910, - 0xb1119930, - 0x7100b0d1, - 0xb012b002, - 0xa0d1b111, - 0xb6307291, - 0xb013b003, - 0xb0e0722c, - 0xb1207100, - 0x92c08170, - 0xb1207100, - 0x22f08170, - 0x13f044d6, - 0x40e21c03, - 0x964292c3, - 0xb1207100, - 0x964492c5, - 0xb1207100, - 0xa630b0e0, - 0xa0e17000, - 0x9910c030, - 0x9930c040, - 0xb0d1b111, - 0xb1117100, - 0x7291a0d1, - 0xa002a003, - 0x7000a230, - 0x73127311, - 0x67c1c040, - 0x91f0c100, - 0xb6336498, - 0xb0d3b113, - 0xa0d37100, - 0x606e64e9, - 0xb016b006, - 0xb014b004, - 0xb012b002, - 0x78628440, - 0x81730420, - 0x2a733983, - 0xc1f294e3, - 0x31621832, - 0x31511021, - 0x00200012, - 0x10309440, - 0x10011610, - 0x39303121, - 0x41232210, - 0x31501220, - 0x31801003, - 0x16300010, - 0x12029380, - 0x22731204, - 0x84a04136, - 0x89829970, - 0x84c01a82, - 0x89849970, - 0x61381a84, - 0x41432263, - 0x997084b0, - 0x1a808980, - 0x84d01402, - 0x89809970, - 0x14041a80, - 0x84b0614f, - 0x04107891, - 0x89829970, - 0x84d01a42, - 0x04107891, - 0x89849970, - 0x31521a44, - 0x39633154, - 0x16130633, - 0x38343832, - 0x39823182, - 0x00423184, - 0x84a09722, - 0x84b09590, - 0x84c095a0, - 0x84d095b0, - 0x781095c0, - 0x90509030, - 0x90407820, - 0xb2359060, - 0x83338cb2, - 0xb0199332, - 0xc00cb018, - 0x8170c00b, - 0x39803180, - 0x81713940, - 0x0431c0f3, - 0x1441c014, - 0x1412c002, - 0x3122697b, - 0xc01084ed, - 0x312d140d, - 0x8c9e142d, - 0x311e318e, - 0x8c99397e, - 0x39793149, - 0x31293949, - 0x81a0109a, - 0x41922200, - 0xb008b009, - 0x720e720d, - 0xb121720f, - 0x7100b0e1, - 0xa0e1b072, - 0xb06ea04e, - 0xb06cb011, - 0x993ab089, - 0xb9147291, - 0xc662a914, - 0xc04f9912, - 0x8c8166fa, - 0x45ae22f1, - 0x22f18ca1, - 0x625845ae, - 0xb0737100, - 0x80b7b910, - 0x45e52207, - 0x8c81a910, - 0x41bf22f1, - 0x41bf2237, - 0x80b0b133, - 0x45ba2230, - 0x22e161cd, - 0x809041d2, - 0x41d22250, - 0x8240b115, - 0x41ae2220, - 0xb9149939, - 0xb116a914, - 0x993d61ae, - 0xa914b914, - 0x61aeb116, - 0x22f08ca0, - 0x223741de, - 0xb07541de, - 0x80b0b133, - 0x45d82230, - 0x61aeb087, - 0x433d22d1, - 0x22208090, - 0x66c0433d, - 0x993f61ae, - 0x8450c7f3, - 0x39803180, - 0x00303183, - 0xb0879450, - 0xb112a0f3, - 0xb115a0d2, - 0xb111a0d5, - 0xa0d6b0d1, - 0xb133b130, - 0x220080b0, - 0x223045f6, - 0x710045f6, - 0x99301260, - 0xba3fb111, - 0x87208b11, - 0x97011801, - 0x8c418c30, - 0xa009a008, - 0xa637a638, - 0x1801c022, - 0x4e181c21, - 0x4a161412, - 0x1c016219, - 0x4e184219, - 0x6219b637, - 0xb041b638, - 0x8ca0b061, - 0x422122e0, - 0x22208240, - 0x7100458d, - 0xb06eb04e, - 0x220180b1, - 0x223146b2, - 0x729146b2, - 0x84e1b116, - 0xc2603121, - 0x99301410, - 0x9910c7e0, - 0x9910c6f0, - 0xb0d6b116, - 0xb960a0d1, - 0x8c448c33, - 0x8c648c53, - 0x80b17100, - 0x46b22201, - 0x46b22231, - 0x22c08c80, - 0x8b414648, - 0x418d2201, - 0xc00081f1, - 0x84e091f0, - 0x6a4c81d2, - 0xc30091f1, - 0xb2319070, - 0x67c1c050, - 0xa0f3a0f0, - 0x7000a044, - 0xb0737100, - 0x80b7b910, - 0x46772207, - 0x46952237, - 0x8c81a910, - 0x427022e1, - 0x22508090, - 0xb1154270, - 0x22208240, - 0x993d4258, - 0xa914b914, - 0x6258b116, - 0x433d22d1, - 0x22208090, - 0x66c0433d, - 0x993f6258, - 0xa0d2b112, - 0xa0d5b115, - 0xb0d1b111, - 0xb130a0d6, - 0x80b0b133, - 0x467f2200, - 0x467f2230, - 0x12607100, - 0xb1119930, - 0x8b11ba3f, - 0x31808720, - 0x18013d80, - 0x8c309701, - 0xa1b28c41, - 0x993f6208, - 0xa0d2b112, - 0xa0d5b115, - 0xb0d1b111, - 0xb130a0d6, - 0x80b0b133, - 0x469d2200, - 0x469d2230, - 0x12607100, - 0xb1119930, - 0x8b11ba3f, - 0x3d808720, - 0x97011801, - 0x8c618c50, - 0x6208b1b2, - 0xa910b073, - 0xa960b910, - 0xa04eb072, - 0xb011b06e, - 0x22f08c80, - 0x220145e5, - 0x62954677, - 0x22b08c80, - 0x1e3b46c6, - 0x62c846f8, - 0x46f81e7b, - 0xba39c00b, - 0x31808af0, - 0x16103d80, - 0x140c3d30, - 0x220080b0, - 0x700042d4, - 0x39838c83, - 0x8c8106f3, - 0x0401cff0, - 0x1c1c3031, - 0x12004ef0, - 0x1c0c1810, - 0x80b04af2, - 0x42e52200, - 0x10c27000, - 0x3c321612, - 0x83508cb1, - 0x42f42210, - 0x933162f6, - 0x7000b112, - 0x62e1101c, - 0x62e1100c, - 0x62ed1821, - 0x62ed1421, - 0x62ee161b, - 0xb111b116, - 0xb133b130, - 0xb112b115, - 0x720e720d, - 0xb0f0720f, - 0x8c82b0f3, - 0x430b22f2, - 0xb913b0d6, - 0x8ca0630e, - 0x432e22f0, - 0xa444b445, - 0xa469b468, - 0x3180caa0, - 0x0001caa1, - 0x94d194c1, - 0x31838ca3, - 0x84503983, - 0x39803180, - 0x00303183, - 0x84409450, - 0x39503150, - 0x39838ca3, - 0xc1f406f3, - 0x31841834, - 0x00403134, - 0xb0899440, - 0x433822e2, - 0x394a8c9a, - 0x312a398a, - 0xb0d5993a, - 0xb913b0d6, - 0x22d28c82, - 0xb0d2433c, - 0xb23f7000, - 0xa0f3a0f0, - 0xb914993e, - 0xb116a914, - 0xb133b130, - 0x22f08240, - 0xb1154346, - 0xa0048002, - 0xa001a006, - 0x72047203, - 0x67c1c060, - 0xb9147100, - 0xb0d5b116, - 0x7100a23f, - 0xa0d5b115, - 0x90307810, - 0x78209002, - 0x90609040, - 0xa23fb072, - 0x993a66fa, - 0xb116a914, - 0xba3c61a7, - 0x8b5481b0, - 0x31843924, - 0x91b40004, - 0x67c1c070, - 0x72917391, - 0x72067263, - 0x72047202, - 0x73067305, - 0x8240606e, - 0x47812230, - 0x7100b0d5, - 0xa0d5b115, - 0x13006379, - 0xb63c91e0, - 0xc080b35d, - 0xb11867c1, - 0x12006506, - 0x99301a10, - 0x9910c380, - 0x9910c280, - 0xb0d6a0d1, - 0x22008090, - 0x81844450, - 0x43921e04, - 0xb1169934, - 0xd0908702, - 0x67c19a12, - 0x22118b41, - 0x8c5243a8, - 0xe0a08c63, - 0x9a239a12, - 0x63ae67c1, - 0x8c438c32, - 0x9a12e0b0, - 0x67c19a23, - 0x89318940, - 0x4bbe1c01, - 0x1ef11801, - 0x89314bbc, - 0x99311af1, - 0xb1167100, - 0x993116f1, - 0x7100a235, - 0xa0d6b116, - 0x9a006367, - 0x220089f0, - 0xb9e047c2, - 0x00007000 -}; - -PATCH_FUN_SPEC void rf_patch_mce_genfsk(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 484; i++) { - HWREG(RFC_MCERAM_BASE + 4 * i) = patchGenfskMce[i]; - } -#else - const uint32_t *pS = patchGenfskMce; - volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 60; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; -#endif -} - -#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_ieee_802_15_4.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_ieee_802_15_4.h deleted file mode 100644 index f72c7afb4..000000000 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_ieee_802_15_4.h +++ /dev/null @@ -1,479 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_mce_ieee_802_15_4.h -* Revised: $Date: 2018-01-15 06:15:14 +0100 (ma, 15 jan 2018) $ -* Revision: $Revision: 18170 $ -* -* Description: RF core patch for IEEE 802.15.4-2006 support in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -#ifndef _RF_PATCH_MCE_IEEE_802_15_4_H -#define _RF_PATCH_MCE_IEEE_802_15_4_H - -#include -#include "../inc/hw_types.h" - -#ifndef MCE_PATCH_TYPE -#define MCE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_MCERAM_BASE -#define RFC_MCERAM_BASE 0x21008000 -#endif - -#ifndef MCE_PATCH_MODE -#define MCE_PATCH_MODE 0 -#endif - -MCE_PATCH_TYPE patchIeee_802_15_4Mce[367] = { - 0xf7036064, - 0x70399b3a, - 0x039bb3af, - 0x39b33af7, - 0x9b3aaf70, - 0xb3aff703, - 0x3af77039, - 0xaf70039b, - 0x08fcb9b3, - 0x8fc664c5, - 0xfc644c50, - 0xc64cc508, - 0x64c5508f, - 0x4c5008fc, - 0xc5088fc6, - 0x508ffc64, - 0x2fc0c64c, - 0x079c0fcf, - 0x7f7f01e0, - 0x0000dead, - 0x00000003, - 0x0000001f, - 0x80000000, - 0x0004000c, - 0x00011400, - 0x00000009, - 0x00008000, - 0x06700000, - 0x16aa002b, - 0x00000a11, - 0x00000b60, - 0x00404010, - 0x00060000, - 0x001e1e1e, - 0x00000000, - 0x00000003, - 0x0000001f, - 0x80000000, - 0x0004000c, - 0x000114c4, - 0x00000009, - 0x00008000, - 0x0f900000, - 0x121d0000, - 0x00000a11, - 0x00000b60, - 0x00404010, - 0x00060000, - 0x00202020, - 0x00000000, - 0x720d7223, - 0x720f720e, - 0x72637210, - 0x7203a35d, - 0x73057204, - 0x73917306, - 0xc7c07291, - 0xb0d09010, - 0xa0d07100, - 0x721bb110, - 0x10208162, - 0x06703952, - 0x16300020, - 0x14011101, - 0x60a16c01, - 0x60ca60b2, - 0x61466119, - 0x60a160a1, - 0x60a160a1, - 0x60ca60ad, - 0x61466119, - 0x60a160a1, - 0x60a160a1, - 0x60ca60b2, - 0x61466119, - 0x60a160a1, - 0x60a160a1, - 0x60ca60ad, - 0x61466119, - 0x60a160a1, - 0x60a460a1, - 0x60a51220, - 0x73111210, - 0x73137312, - 0x001081b1, - 0xb07091b0, - 0xc4616073, - 0xc460c2b2, - 0x60b61820, - 0xc2b2c281, - 0x1820c460, - 0x6e236f13, - 0x16121611, - 0xc63268b6, - 0x1820c9c0, - 0x120340c3, - 0x16126e23, - 0x7a4068c0, - 0xc1409c80, - 0x12209c90, - 0x60a49990, - 0xc1307291, - 0xb11391f0, - 0x81621213, - 0xd0303982, - 0x66d89a12, - 0x40e41e02, - 0x40e41e12, - 0x40dd1e22, - 0x00238992, - 0xb00560e4, - 0x1e208990, - 0x60e444e2, - 0xa005b270, - 0xb0e8b128, - 0xb1287100, - 0x9233a0e8, - 0x1e008c80, - 0x993040f2, - 0xb111b910, - 0x7100b0d1, - 0xb002b012, - 0xb013b633, - 0xb111b003, - 0x7291a0d1, - 0x7100b0d3, - 0xa0d3b113, - 0xc0301000, - 0xc0209910, - 0xb0d19930, - 0xb1117100, - 0x7291a0d1, - 0x39828162, - 0x490d1a22, - 0x726366d1, - 0xa002a003, - 0x73057263, - 0x73917306, - 0xa2307291, - 0x9010c7c0, - 0xb63c60a4, - 0x94c07810, - 0x782095b0, - 0x95c094d0, - 0xc0f18190, - 0xc0120410, - 0x14023110, - 0x94a06f20, - 0x16129590, - 0x94b06f20, - 0x824095a0, - 0x45352230, - 0x7100b0d5, - 0xa0d5b115, - 0x7291612d, - 0x91e0c030, - 0xb004b002, - 0x8160b006, - 0x41402280, - 0x61417a20, - 0x90507a10, - 0x7a309030, - 0x90409060, - 0x8460b235, - 0x84613180, - 0x39813181, - 0x94500010, - 0x06f58195, - 0x1217120e, - 0x12f01206, - 0xc1909440, - 0xb0119440, - 0xb0f9b139, - 0xb089a0fc, - 0x12041203, - 0x39828162, - 0x9a12d040, - 0x1e2266d8, - 0x1e324227, - 0x7100421d, - 0xa0d17291, - 0xa0f9b139, - 0xb0fcb13c, - 0xc600a444, - 0x99303140, - 0xb111b910, - 0x7100b0d1, - 0x7291a0d1, - 0x22108090, - 0xb13c46d5, - 0x1e7665be, - 0x81904194, - 0x06f03940, - 0x45461c0f, - 0x1c908c90, - 0x12054d46, - 0x12761202, - 0x9070c300, - 0xc050b230, - 0xc0c066d8, - 0x7a509440, - 0x619b9450, - 0x91cf1647, - 0x1e008180, - 0x1c70419b, - 0x710049a0, - 0x22008090, - 0x617b4476, - 0x7291a235, - 0x72047203, - 0x73067305, - 0xa004a002, - 0x7263a006, - 0x73067305, - 0x72917391, - 0x9010c7c0, - 0x39808160, - 0x4dbb1a30, - 0x22508000, - 0x122045b9, - 0x124061bc, - 0x89c061bc, - 0x60a49990, - 0x120a1209, - 0x120dc0cc, - 0x8ad8ba3e, - 0x49c91c89, - 0x4dcf1c8a, - 0x108961d6, - 0x18801200, - 0x10db100a, - 0x108a61d6, - 0x18801200, - 0x10db1009, - 0x61d6168b, - 0x1e8d161d, - 0x908c41db, - 0x10bf61c2, - 0x41e61e82, - 0x16121495, - 0x45e61e82, - 0x81b03125, - 0x91b50005, - 0x49e91e8b, - 0xc0701a8b, - 0x163018b0, - 0x14011101, - 0x908c6c01, - 0x908c908c, - 0x908c908c, - 0x908c908c, - 0xb082908c, - 0xba3e1000, - 0xb0838ad3, - 0x1000b083, - 0x8ad4ba3e, - 0x4a071e8f, - 0x4a0c1ca3, - 0x4a0e1ca4, - 0x1c937000, - 0x1c944e0c, - 0x70004e0e, - 0x62101a1e, - 0x6210161e, - 0x1ce0c040, - 0x10e04a17, - 0x4a1a1640, - 0xc00e7000, - 0x7000b085, - 0xb084c00e, - 0xa3a77000, - 0x66acb3a5, - 0x6a21cbe0, - 0xc7f066ac, - 0xb3a76a24, - 0x8460a3a5, - 0x31801640, - 0x16418461, - 0x39813181, - 0x94500010, - 0x94b07810, - 0x782095a0, - 0x959094a0, - 0xb0d1a0f9, - 0xb258b005, - 0xc0307291, - 0xb1309910, - 0xc290b133, - 0x80b09440, - 0x465e2230, - 0x465e2200, - 0x9930c040, - 0xb910a910, - 0xa0f0a0f3, - 0x7100b111, - 0xc2f0b064, - 0xb1309930, - 0xb111b133, - 0x80b07100, - 0x465c2230, - 0x465c2200, - 0x623f66ac, - 0x625e66ac, - 0xc0408248, - 0xa9109930, - 0x3988b910, - 0x9a18d060, - 0xb11166d8, - 0xc2f07100, - 0xb0649930, - 0xb133b130, - 0x7100b111, - 0x220080b0, - 0x22304676, - 0x627d4676, - 0x39818241, - 0x9a11d070, - 0x1c1866d8, - 0x66ac4a86, - 0x9930c040, - 0xb910a910, - 0x66d8c080, - 0xb0647100, - 0x9440c190, - 0xb139b0f9, - 0xa0f0a0f3, - 0x06f08190, - 0x3110c012, - 0x6f201402, - 0x959094a0, - 0x6f201612, - 0x95a094b0, - 0x9930c5f0, - 0x31808460, - 0x31818461, - 0x00103981, - 0xa9109450, - 0xb111b910, - 0x7100b133, - 0x229080b0, - 0x22304568, - 0x622746a1, - 0x39808160, - 0x4eb81a30, - 0x22508000, - 0xb00546b5, - 0xb27062b7, - 0x7000a005, - 0x22128232, - 0x261246c0, - 0x92322a22, - 0x62c499c2, - 0x26222a12, - 0x99c29232, - 0x96a49693, - 0x9a30c030, - 0x8a548a43, - 0x82400662, - 0x1c020660, - 0xb05346cb, - 0x89907000, - 0x99900a60, - 0xc0907000, - 0x615366d8, - 0x89f09a00, - 0x46d92200, - 0x7000b9e0 -}; - -PATCH_FUN_SPEC void rf_patch_mce_ieee_802_15_4(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 367; i++) { - HWREG(RFC_MCERAM_BASE + 4 * i) = patchIeee_802_15_4Mce[i]; - } -#else - const uint32_t *pS = patchIeee_802_15_4Mce; - volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 45; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; -#endif -} - -#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h new file mode 100644 index 000000000..12390d3b2 --- /dev/null +++ b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h @@ -0,0 +1,438 @@ +/****************************************************************************** +* Filename: rf_patch_mce_iqdump.h +* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18842 $ +* +* Description: RF core patch for IQ-dump support in CC13x2 PG2.1 and CC26x2 PG2.1 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_IQDUMP_H +#define _RF_PATCH_MCE_IQDUMP_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchIqdumpMce[337] = { + 0x2fcf6030, + 0x00013f9d, + 0xff00003f, + 0x07ff0fff, + 0x0300f800, + 0x00068080, + 0x00170003, + 0x00003d1f, + 0x08000000, + 0x0000000f, + 0x00000387, + 0x00434074, + 0x00828000, + 0x06f00080, + 0x091e0000, + 0x00540510, + 0x00000007, + 0x00505014, + 0xc02f0000, + 0x017f0c30, + 0x00000000, + 0x00000000, + 0x00000000, + 0x0000aa00, + 0x66957223, + 0xa4e5a35d, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72917391, + 0xffc0b008, + 0xa0089010, + 0x720e720d, + 0x7210720f, + 0x7100b0d0, + 0xa0d0b110, + 0x8162721b, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60816080, + 0x610b60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x61af60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x611b60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x61cb60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x615360fd, + 0x72231210, + 0x73127311, + 0x81b17313, + 0x91b00010, + 0x6044b070, + 0xc0306076, + 0xc0c1669b, + 0xc4e0c2b2, + 0x6f131820, + 0x16116e23, + 0x68871612, + 0x99c07830, + 0x948078a0, + 0xc4f29490, + 0x1820c750, + 0x12034099, + 0x16126e23, + 0x78b06896, + 0x72639990, + 0x6076b63c, + 0x96408190, + 0x39808170, + 0x10012a70, + 0x84a21611, + 0xc0f384b4, + 0xc200c0f5, + 0x40c21c01, + 0x1c10c100, + 0x4cba40b8, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60c268b5, + 0x60c213f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68c03914, + 0x7100b0e8, + 0xa0e8b128, + 0xb910b230, + 0x99308990, + 0xb0d1b111, + 0xb0027100, + 0xb111b012, + 0x7291a0d1, + 0xb003b630, + 0x722cb013, + 0x7100b0e0, + 0x8170b120, + 0x710092c0, + 0x8170b120, + 0x44db22f0, + 0x1c0313f0, + 0x92c340e7, + 0x71009642, + 0x92c5b120, + 0x71009644, + 0xb0e0b120, + 0x7000a630, + 0xc030a0e1, + 0xc0409910, + 0xb1119930, + 0x7100b0d1, + 0xa0d1b111, + 0xa0037291, + 0xa230a002, + 0x73117000, + 0xc0407312, + 0xc100669b, + 0x649e91f0, + 0xb113b633, + 0x7100b0d3, + 0x64eea0d3, + 0xa0d26076, + 0xa0f3a0f0, + 0x73127311, + 0xc050660f, + 0xb0d2669b, + 0x7100c035, + 0xba389b75, + 0xb112b074, + 0xa0d26115, + 0xa0f3a0f0, + 0x73127311, + 0xc18b660f, + 0x91e0c000, + 0x1218120c, + 0x787d786a, + 0x10a9788e, + 0xb0d2b074, + 0xb112c020, + 0x692d7100, + 0x669bc060, + 0xb112c035, + 0x9b757100, + 0x65a48bf0, + 0x22018ca1, + 0x10804140, + 0x453f1ca8, + 0x16181208, + 0x8c00659b, + 0x8ca165a4, + 0x414b2201, + 0x1a191090, + 0x454b1e09, + 0x659b10a9, + 0x1e048184, + 0x14bc4133, + 0x4e7e1c4c, + 0xa0d26133, + 0xa0f3a0f0, + 0x73127311, + 0x721e660f, + 0x1205120c, + 0xb0d2b074, + 0xb112c020, + 0x695f7100, + 0x669bc070, + 0x89ce789d, + 0x7100b112, + 0x22008c90, + 0x8230416f, + 0x456f2210, + 0x9a3db231, + 0x31828ab2, + 0x8af03d82, + 0x3d803180, + 0x063e1802, + 0x41911e0e, + 0x41831e2e, + 0x418a1e3e, + 0x14261056, + 0x10653d16, + 0x10566192, + 0x18563126, + 0x3d261426, + 0x61921065, + 0x31361056, + 0x14261856, + 0x10653d36, + 0x10266192, + 0x91c63976, + 0x1e048184, + 0x161c4166, + 0x4e7e1c4c, + 0x10016166, + 0x91c1c0b0, + 0x10003911, + 0x10001000, + 0x7000699d, + 0x3d303130, + 0x4dab1cd0, + 0x49ad1ce0, + 0x10d07000, + 0x10e07000, + 0xc0807000, + 0xa0d2669b, + 0xa0f3a0f0, + 0x73127311, + 0xb130660f, + 0x7100b0f0, + 0x220080b0, + 0x61b945be, + 0xc090b231, + 0xb130669b, + 0xb0d2a0f0, + 0x7100c035, + 0xba389b75, + 0xb112b074, + 0xc0a061c5, + 0xa0d2669b, + 0xa0f3a0f0, + 0x73127311, + 0xc18b660f, + 0x91e0c000, + 0x1218120c, + 0x787d786a, + 0x10a9788e, + 0xb0f0b130, + 0x80b07100, + 0x45e32200, + 0xb07461de, + 0xc0b0b231, + 0xb130669b, + 0xb0d2a0f0, + 0xb112c020, + 0x69eb7100, + 0xb112c035, + 0x9b757100, + 0x65a48bf0, + 0x22018ca1, + 0x108041fc, + 0x45fb1ca8, + 0x16181208, + 0x8c00659b, + 0x8ca165a4, + 0x42072201, + 0x1a191090, + 0x46071e09, + 0x659b10a9, + 0x1e048184, + 0x14bc41ef, + 0x4e7e1c4c, + 0x824061ef, + 0x46172230, + 0x7100b0d5, + 0xa0d5b115, + 0xc0c0620f, + 0xb118669b, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78428440, + 0x81730420, + 0x2a733983, + 0xc1f294e3, + 0x31621832, + 0x31511021, + 0x00200012, + 0x10309440, + 0x39301610, + 0x42352210, + 0x31501220, + 0x31801003, + 0x93801630, + 0x12041202, + 0x42472273, + 0x997084a0, + 0x1a828982, + 0x997084c0, + 0x1a848984, + 0x22636249, + 0x84b04254, + 0x89809970, + 0x14021a80, + 0x997084d0, + 0x1a808980, + 0x62601404, + 0x785184b0, + 0x99700410, + 0x1a428982, + 0x785184d0, + 0x99700410, + 0x1a448984, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x97220042, + 0x959084a0, + 0x95a084b0, + 0x95b084c0, + 0x95c084d0, + 0x90307810, + 0x78209050, + 0x90609040, + 0xcd90b235, + 0x70009170, + 0xb112a235, + 0xa0d27100, + 0xba3cb112, + 0x8b5481b0, + 0x31843924, + 0x91b40004, + 0x669bc0d0, + 0x72917391, + 0x72066695, + 0x72047202, + 0x73067305, + 0x86306076, + 0x3151c801, + 0x96300410, + 0x9a007000, + 0x220089f0, + 0xb9e0469c, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_mce_iqdump(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 337; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchIqdumpMce[i]; + } +#else + const uint32_t *pS = patchIqdumpMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 42; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + *pD++ = t1; +#endif +} + +#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_sl_longrange.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_sl_longrange.h deleted file mode 100644 index 02157e0a5..000000000 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_sl_longrange.h +++ /dev/null @@ -1,335 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_mce_sl_longrange.h -* Revised: $Date: 2018-01-15 06:15:14 +0100 (ma, 15 jan 2018) $ -* Revision: $Revision: 18170 $ -* -* Description: RF core patch for SimpleLink Long Range support in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_MCE_SL_LONGRANGE_H -#define _RF_PATCH_MCE_SL_LONGRANGE_H - -#include -#include "../inc/hw_types.h" - -#ifndef MCE_PATCH_TYPE -#define MCE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_MCERAM_BASE -#define RFC_MCERAM_BASE 0x21008000 -#endif - -#ifndef MCE_PATCH_MODE -#define MCE_PATCH_MODE 0 -#endif - -MCE_PATCH_TYPE patchSimplelinkLrmMce[228] = { - 0x60466046, - 0x2fcf146f, - 0xdb3e0f9d, - 0x00007f7f, - 0x00020001, - 0x00000003, - 0x000c0003, - 0x00cc000f, - 0x003c00c3, - 0xcccc0033, - 0x33cccc33, - 0x0f003333, - 0x005f0f0f, - 0x005d0060, - 0x005b005e, - 0x0059005c, - 0x0003005a, - 0x001f0007, - 0x00000000, - 0x000f0400, - 0x03870000, - 0x40c00001, - 0x80000043, - 0x01000004, - 0x000006f0, - 0x0524091e, - 0x00050054, - 0x48200800, - 0x00000048, - 0x7f7f001f, - 0x8004004c, - 0x2e000000, - 0x00000000, - 0x00000000, - 0x10200000, - 0x65bb7223, - 0xa4e5a35d, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72917391, - 0xffc0b008, - 0xa0089010, - 0x720e720d, - 0x7210720f, - 0x7100b0d0, - 0xa0d0b110, - 0x8162721b, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x607e607d, - 0x60956095, - 0x607d607d, - 0x607d607d, - 0x60731220, - 0x72231210, - 0x73127311, - 0x73147313, - 0x001081b1, - 0xb07091b0, - 0x6072605a, - 0xc2b2c211, - 0x1820c4f0, - 0x6e236f13, - 0x16121611, - 0xc6326882, - 0x1820c9c0, - 0x1203408f, - 0x16126e23, - 0xb63c688c, - 0x91a0d000, - 0x9990c0c0, - 0xb1186072, - 0x409d8cb4, - 0xb0099334, - 0xb019b008, - 0x6594b018, - 0x94507860, - 0x81a7721e, - 0x39871076, - 0x99770677, - 0x16188988, - 0x9a17d030, - 0x64dc65c1, - 0x99c07850, - 0xb00764ef, - 0xb124b017, - 0xc205b0e4, - 0x657cc004, - 0x1c54658d, - 0x91c048ba, - 0x81811614, - 0x40b51e01, - 0x1c411671, - 0xa0e74cb5, - 0x798f797e, - 0x97af979e, - 0x658d1204, - 0x1c541614, - 0x91c040cd, - 0xa23560c7, - 0x65c1c040, - 0xa0e4a0e7, - 0x72027206, - 0x72037204, - 0x73057204, - 0x73917306, - 0x60727291, - 0x3181c061, - 0xcff3c002, - 0x16116e12, - 0x16116e12, - 0x6e13c7e0, - 0x6e121611, - 0x68e51611, - 0x6e12cff0, - 0x68eb1611, - 0xb0067000, - 0xb004b016, - 0xb002b014, - 0x7830b012, - 0x90509030, - 0x90407840, - 0xb2359060, - 0xc090b072, - 0xc60093f0, - 0x99303150, - 0x9910c060, - 0xb0f7b137, - 0xb10cb14c, - 0xb0d1b111, - 0x80b07100, - 0x45272270, - 0xa10cb073, - 0xb111a0f7, - 0xb127a0d1, - 0xba3eb0e7, - 0xb14c7100, - 0xb041b127, - 0xa044b061, - 0xa008a009, - 0xb1277100, - 0xb06db04d, - 0xb231b074, - 0xb1277100, - 0x80907000, - 0x41332210, - 0xa910b111, - 0x93308cb0, - 0x93f0c090, - 0xb008b009, - 0xb0e76104, - 0xa009a0f7, - 0xba39a008, - 0x93f0c0b0, - 0x31848af4, - 0x98d43d84, - 0x98e08990, - 0x6941c050, - 0xc40188f0, - 0x3d701410, - 0x31648334, - 0x18043d64, - 0x3520cff0, - 0x93340404, - 0x22c180c1, - 0xc060450e, - 0x80c17100, - 0x450e22c1, - 0x6952b127, - 0xb910b069, - 0xa0e7b127, - 0x12096104, - 0x6572120a, - 0x141a1409, - 0x416f1e17, - 0x14196572, - 0x1e37140a, - 0x6572416f, - 0x141a1409, - 0x14196572, - 0x3c89140a, - 0x70003c8a, - 0xb1277100, - 0xb1277100, - 0x318089a0, - 0x89b13980, - 0x70003981, - 0x109b655d, - 0x655d10ac, - 0x318d10bd, - 0x10cd14db, - 0x14dc318d, - 0x14a9318a, - 0x149c149b, - 0x97ac979b, - 0xa0e77000, - 0x7100b079, - 0xb0e7b124, - 0x700089d0, - 0x65c1c050, - 0xc0fcc19b, - 0xc07084a1, - 0x06321012, - 0x6f2314c2, - 0x41a22200, - 0x61a71034, - 0x00343183, - 0x6e746fb7, - 0x3921161b, - 0x84b1699a, - 0x1012c070, - 0x14c20632, - 0x22006f23, - 0x103441b3, - 0x318361b8, - 0x6fb70034, - 0x161b6e74, - 0x69ab3921, - 0x86307000, - 0x3151c801, - 0x96300410, - 0x9a007000, - 0x220089f0, - 0xb9e045c2, - 0x00007000 -}; - -PATCH_FUN_SPEC void rf_patch_mce_sl_longrange(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 228; i++) { - HWREG(RFC_MCERAM_BASE + 4 * i) = patchSimplelinkLrmMce[i]; - } -#else - const uint32_t *pS = patchSimplelinkLrmMce; - volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 28; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; -#endif -} - -#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_slr.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_slr.h deleted file mode 100644 index f114a7ab3..000000000 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_slr.h +++ /dev/null @@ -1,365 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_mce_slr.h -* Revised: $Date: 2017-12-01 13:47:22 +0100 (fr, 01 des 2017) $ -* Revision: $Revision: 18103 $ -* -* Description: RF core patch for SimpleLink Long Range support in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_MCE_SLR_H -#define _RF_PATCH_MCE_SLR_H - -#include -#include "../inc/hw_types.h" - -#ifndef MCE_PATCH_TYPE -#define MCE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_MCERAM_BASE -#define RFC_MCERAM_BASE 0x21008000 -#endif - -#ifndef MCE_PATCH_MODE -#define MCE_PATCH_MODE 0 -#endif - -MCE_PATCH_TYPE patchSlrMce[254] = { - 0x60456045, - 0x2fcf146f, - 0xdb3e0f9d, - 0x3c337f7f, - 0xcccc333c, - 0x00003cc3, - 0x00020001, - 0x00000003, - 0x000c0003, - 0x00cc000f, - 0x003c00c3, - 0xcccc0033, - 0x33cccc33, - 0x0f003333, - 0x00000f0f, - 0x00070003, - 0x0000001f, - 0x04000000, - 0x0000000f, - 0x00010387, - 0x004348c0, - 0x00048000, - 0x06f00080, - 0x091e0000, - 0x04500524, - 0x08000005, - 0x00484820, - 0x001f0000, - 0x004c7f7f, - 0x00009000, - 0x00007f7f, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72230000, - 0x73037263, - 0x72037305, - 0x73067304, - 0x73917204, - 0xc7c07291, - 0x00018001, - 0x90109001, - 0x90010801, - 0x720e720d, - 0x7210720f, - 0x7100b0d0, - 0xa0d0b110, - 0x8162721b, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x6077606c, - 0x610b608b, - 0x72231210, - 0x73127311, - 0x73147313, - 0x001081b1, - 0xb07091b0, - 0xc1e1605a, - 0xc4e0c2b2, - 0x6f131820, - 0x16116e23, - 0x687b1612, - 0xc9c0c632, - 0x40881820, - 0x6e231203, - 0x68851612, - 0x91a0d000, - 0x7311606c, - 0xc0007312, - 0xc00991f0, - 0x398081a0, - 0x16100670, - 0x449a1e10, - 0xc008c0b7, - 0x60a9c01e, - 0x44a01e20, - 0xc018c0f7, - 0x60a9c03e, - 0x44a61e40, - 0xc038c137, - 0x60a9c07e, - 0xc078c177, - 0xc030c0fe, - 0xb0e865f6, - 0xb1287100, - 0xb230a0e8, - 0xb003b630, - 0xb002b013, - 0x8176b012, - 0x06f63946, - 0xb0e01616, - 0xc13cc004, - 0x92c0c070, - 0xc0707821, - 0x06321012, - 0x6f2314c2, - 0x71009643, - 0x3921b120, - 0x161468c0, - 0x44be1c64, - 0x0bf17821, - 0x1012c070, - 0x14c20632, - 0x96436f23, - 0xb1207100, - 0x68cf3921, - 0xc6d5c4f4, - 0x81dfc066, - 0x821064f4, - 0x40e12210, - 0xc07060db, - 0xc00f1a10, - 0x68e364f4, - 0xc030a0e1, - 0x99309910, - 0xb0d1b111, - 0xb1117100, - 0x7291a0d1, - 0xa002a003, - 0x606c7223, - 0x316f061f, - 0x109100f9, - 0x99710441, - 0x061a898a, - 0x04511091, - 0x898b9971, - 0x311b061b, - 0x391914ba, - 0x6fa3147a, - 0x92ce9643, - 0xb1207100, - 0xb1187000, - 0x410f8cb4, - 0xc1f09334, - 0x78609440, - 0x721e9450, - 0x107681a7, - 0x06773987, - 0x89889977, - 0xd0401618, - 0x65f69a17, - 0x95907870, - 0x95a07880, - 0x95b07890, - 0x95c078a0, - 0x78506557, - 0x656a99c0, - 0xb007b017, - 0xb0e4b124, - 0xc004c205, - 0x65ef65de, - 0x49351c54, - 0x161491c0, - 0x1e018181, - 0x16714130, - 0x4d301c41, - 0x79bea0e7, - 0x979e79cf, - 0x120497af, - 0x161465ef, - 0x41481c54, - 0x614291c0, - 0xc050a235, - 0xa0e765f6, - 0x7206a0e4, - 0x72047202, - 0x72047203, - 0x73067305, - 0x72917391, - 0xc061606c, - 0xc0023181, - 0x6e12cff3, - 0x6e121611, - 0xc7e01611, - 0x16116e13, - 0x16116e12, - 0xcff06960, - 0x16116e12, - 0x70006966, - 0xb016b006, - 0xb014b004, - 0xb012b002, - 0x90307830, - 0x78409050, - 0x90609040, - 0xb072b235, - 0x93f0c090, - 0xb0f7b137, - 0xb0f6b136, - 0xb0737100, - 0xa0f7b127, - 0x80b0a0f7, - 0x459f2270, - 0xa0f7a0f6, - 0xba3eb0e7, - 0xb1367100, - 0xb041b127, - 0xc0f0b061, - 0xba3f93f0, - 0x31148b14, - 0xa0449704, - 0xb1277100, - 0xb06db04d, - 0xb231b074, - 0xb1277100, - 0xb0e77000, - 0x8af4ba39, - 0x3d843184, - 0xc05098d4, - 0xc05098e0, - 0x88f069a8, - 0x1410c201, - 0x83343d60, - 0x3d643164, - 0xcff01804, - 0x04043520, - 0xc0b09334, - 0xb06993f0, - 0x9a14d060, - 0x710065f6, - 0xa0e7b127, - 0x1209617a, - 0x65d4120a, - 0x141a1409, - 0x41d11e17, - 0x141965d4, - 0x1e37140a, - 0x65d441d1, - 0x141a1409, - 0x141965d4, - 0x3c89140a, - 0x70003c8a, - 0xb1277100, - 0xb1277100, - 0x318089a0, - 0x89b13980, - 0x70003981, - 0x109b65bf, - 0x65bf10ac, - 0x318d10bd, - 0x10cd14db, - 0x14dc318d, - 0x14a9318a, - 0x149c149b, - 0x97ac979b, - 0xa0e77000, - 0x7100b079, - 0xb0e7b124, - 0x700089d0, - 0x89f09a00, - 0x45f72200, - 0x7000b9e0 -}; - -PATCH_FUN_SPEC void rf_patch_mce_slr(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 254; i++) { - HWREG(RFC_MCERAM_BASE + 4 * i) = patchSlrMce[i]; - } -#else - const uint32_t *pS = patchSlrMce; - volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 31; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; -#endif -} - -#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h new file mode 100644 index 000000000..eeabf348d --- /dev/null +++ b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h @@ -0,0 +1,609 @@ +/****************************************************************************** +* Filename: rf_patch_mce_tof.h +* Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18843 $ +* +* Description: RF core MCE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_TOF_H +#define _RF_PATCH_MCE_TOF_H + +#include +#include "../inc/hw_types.h" + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchTofMce[506] = { + 0x0003605b, + 0x00f1000f, + 0x00000000, + 0x000c8000, + 0x00000000, + 0x0c650000, + 0x80000000, + 0x00800010, + 0x00000000, + 0x0594091e, + 0x00000350, + 0x7c200000, + 0x000000c2, + 0x34340013, + 0x0003005a, + 0x00000032, + 0xfe6b2840, + 0xdeade8ca, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x07d00011, + 0x6fdd2fea, + 0x0fb00ff0, + 0xf80f0003, + 0x007f7f30, + 0x3434001f, + 0x8010005a, + 0x01900000, + 0x40000800, + 0xc0300c65, + 0x722367ee, + 0xa35d7263, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72917391, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720d9001, + 0x720f720e, + 0xb0d07210, + 0xc0407100, + 0xa0d067ee, + 0x721bb110, + 0x10208162, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60936c01, + 0x60c260a4, + 0x6219617b, + 0x60936093, + 0x60936093, + 0x60c260a4, + 0x6219617b, + 0x60936093, + 0x60976093, + 0x12206095, + 0xc050609a, + 0x121267ee, + 0x73117223, + 0x73137312, + 0x81b17314, + 0x91b20012, + 0x6073b070, + 0xc2b2c011, + 0x1820c710, + 0x6e236f13, + 0x16121611, + 0x7d7068a8, + 0xc0229990, + 0x39818161, + 0xd0601812, + 0x67ee9a12, + 0x40971e01, + 0x99907d80, + 0x93807d50, + 0x93307d60, + 0x93007d90, + 0x6097b360, + 0xc07067e5, + 0x677e67ee, + 0x91f0c070, + 0x670bb750, + 0xb233b914, + 0xa750672d, + 0x95b488d4, + 0x95c488e4, + 0x95948ca4, + 0x95a487c4, + 0x2a007cb0, + 0x88d49060, + 0x88e495d4, + 0xc0f495e4, + 0x91449134, + 0x22008c80, + 0xb0f040e5, + 0xb0f6b130, + 0xb0d5b0d0, + 0xb110b136, + 0xb140b100, + 0x73137314, + 0x2a007cb0, + 0xc0f19060, + 0x40f51e0e, + 0x99311611, + 0xc037b912, + 0xb115b041, + 0xa910c031, + 0xb0737100, + 0xba3eb910, + 0x22008090, + 0x80b24574, + 0x45182262, + 0x220280c2, + 0xb061410b, + 0x2250b140, + 0x824040f9, + 0x45152200, + 0x40f9220f, + 0x679e100f, + 0x100f60f9, + 0x60f967b4, + 0xb234a913, + 0x93acba39, + 0xa0d58462, + 0xb0d1720f, + 0x7100b111, + 0xb1119937, + 0xb35d7100, + 0x9930c3f0, + 0xc0d0b074, + 0x894193f0, + 0x67bf9791, + 0x14018941, + 0x7100b111, + 0xba3aba3b, + 0xc210b078, + 0xa2329930, + 0xb111b235, + 0xa35d7100, + 0x7291b06e, + 0x8af2a0d1, + 0x3d823182, + 0x67eec080, + 0x8c528c33, + 0x8c441423, + 0x14248c62, + 0x06f28b32, + 0x31418b21, + 0x97a20012, + 0x0424cff2, + 0x31433143, + 0x97b40034, + 0x6957c8f0, + 0xb130b235, + 0xb136a0f0, + 0xb140a0f6, + 0xb914a100, + 0xa7507291, + 0xa002a003, + 0x9010c7c0, + 0x72047203, + 0x73067305, + 0xa23267e5, + 0x8242b235, + 0x456b1e02, + 0xc0907223, + 0x609767ee, + 0xa232b235, + 0xd0a08942, + 0x67ee9a12, + 0x67e56159, + 0x677ec00f, + 0x91f0c070, + 0xc0b0670b, + 0xb01367ee, + 0x22008c80, + 0xb0f04189, + 0xb0f6b130, + 0xb0d5b0d0, + 0xb136b111, + 0x72917313, + 0xc0e1b912, + 0x41951e0e, + 0x99311611, + 0xb041c037, + 0xc031b232, + 0xb115a910, + 0xb0737100, + 0xba3eb910, + 0x22008090, + 0x80b24614, + 0x45b32262, + 0x41992250, + 0x22008240, + 0x220f45b0, + 0x100f4199, + 0x6199679e, + 0x67b4100f, + 0xb9136199, + 0xba39b234, + 0xa0d593ac, + 0x7313720f, + 0x73147210, + 0x264081b0, + 0xb0d191b0, + 0x7100b111, + 0x9937b041, + 0x7100b111, + 0xc3f0b35d, + 0xb0749930, + 0x93f0c0d0, + 0x7100b111, + 0xc210b078, + 0xa2329930, + 0x7100b111, + 0xb06ea35d, + 0xa0d1a910, + 0x899167bf, + 0x81a01401, + 0x99311401, + 0xb0d6b116, + 0xb1167100, + 0x8090a0d6, + 0x46142200, + 0x88d4b012, + 0x88e495b4, + 0x8ca495c4, + 0x87c49594, + 0x729195a4, + 0x2a208230, + 0x92302630, + 0xc070672d, + 0x8af287b1, + 0x3d823182, + 0x69fbc310, + 0xb111b064, + 0xa0f6b136, + 0xa0f0b130, + 0x8242b235, + 0x46021e02, + 0x7291b914, + 0xa002a003, + 0x9010c7c0, + 0x72047203, + 0x73067305, + 0x67eec0c0, + 0x609767e5, + 0x67eec0d0, + 0x7291b235, + 0x677e6202, + 0xc070c00b, + 0x670b91f0, + 0x67eec0e0, + 0x727ab914, + 0xb0137226, + 0x73147313, + 0x8c8072c9, + 0x422d2200, + 0xb130b0f0, + 0x85b06231, + 0x95d085c1, + 0xb10095e1, + 0xb110b140, + 0xb0f6b064, + 0xb0d5b0d0, + 0x7313b136, + 0xb041b061, + 0x42411e1b, + 0xb9127291, + 0xc13772c9, + 0x1e0ec070, + 0x16104247, + 0x9930c0b7, + 0xb115b232, + 0xa910c031, + 0xb0737100, + 0xba3eb910, + 0x22008090, + 0x80b24705, + 0x46682262, + 0x220280c2, + 0xb061425b, + 0x2250b140, + 0x82404249, + 0x46652200, + 0x4249220f, + 0x679e100f, + 0x100f6249, + 0x624967b4, + 0x1e1bb234, + 0xa9154285, + 0xb913b916, + 0x8b33ba3b, + 0x8b2406f3, + 0x00433144, + 0x8c3397a3, + 0x14038c50, + 0x8c448c60, + 0x31431404, + 0x00343143, + 0x81b097b4, + 0x91b02650, + 0x67eec0f0, + 0xa91362bf, + 0x264081b0, + 0x993791b0, + 0x93acba39, + 0x720fa0d5, + 0xb111b0d1, + 0x7100b111, + 0xc3e0b35d, + 0xb0749930, + 0x93f0c0d0, + 0x97918941, + 0xb11167bf, + 0xb0787100, + 0x9930c210, + 0xb235a232, + 0x7100b111, + 0xb06ea35d, + 0xa0d17291, + 0x31828af2, + 0xba3b3d82, + 0x06f38b33, + 0x31448b24, + 0x92630043, + 0x8c508c33, + 0x8c601403, + 0x14048c44, + 0x31433143, + 0x97b40034, + 0x6abdc8f0, + 0xbc9062e3, + 0x95b488d4, + 0x95c488e4, + 0x95948ca4, + 0x95a487c4, + 0x85b0c01b, + 0x95d085c1, + 0x731195e1, + 0x73137312, + 0xb1007314, + 0xb0f6b140, + 0xb110b136, + 0xa232b064, + 0x22628242, + 0x722342d7, + 0xb115b064, + 0xc410b232, + 0x679e6ae0, + 0xb2356249, + 0xa100b140, + 0xa0f6b136, + 0x7291b914, + 0xa003a750, + 0xc7c0a002, + 0x72039010, + 0x73057204, + 0x73117306, + 0x73137312, + 0x720f7314, + 0x7210720d, + 0x7223720e, + 0xb235a232, + 0x1e028242, + 0x722346fc, + 0x67eec100, + 0xc1106097, + 0xb23567ee, + 0x8942a232, + 0x824262e4, + 0x430b2212, + 0xb016b006, + 0xb002b012, + 0xb014b004, + 0x90307ca0, + 0x7cb09050, + 0x90609040, + 0x73127311, + 0x73147313, + 0x720e720d, + 0x7210720f, + 0xb0e1b121, + 0xb0727100, + 0xd680a0e1, + 0x679e6b28, + 0x93f0c090, + 0xbc907000, + 0x9930c040, + 0xb910b911, + 0xb111b0d1, + 0x72917100, + 0xb111a0d1, + 0x9635722c, + 0xc0f38c82, + 0xb013b003, + 0x92c08170, + 0x96408190, + 0xb120b0e0, + 0x22027100, + 0x85b04750, + 0x92c39640, + 0x7100b120, + 0x964085c0, + 0x7100b120, + 0x96408590, + 0xb12092c3, + 0x85a07100, + 0xb1209640, + 0x8cb07100, + 0x0410cff1, + 0xb1209640, + 0x96367100, + 0x9930c040, + 0xb910b911, + 0xb111b0d1, + 0xb120a0e0, + 0x72917100, + 0xb111a0d1, + 0x1e108750, + 0xb2354371, + 0xa9156378, + 0xb913b916, + 0x2a308230, + 0x92302620, + 0x6b79c090, + 0xc120ac90, + 0x700067ee, + 0x721b7223, + 0x92c0c0f0, + 0xc1f1722f, + 0xc01592d1, + 0x7c977c86, + 0x8c807ccc, + 0x43912200, + 0x94407cf0, + 0x94607d10, + 0x7d206393, + 0xac909440, + 0xc1009636, + 0x816e91e0, + 0xc01d398e, + 0x439d1e0e, + 0x7000c03d, + 0x726a7269, + 0xb0537ce2, + 0xc76093a2, + 0x73a36ba4, + 0x96908a40, + 0x96a18a51, + 0x7cd093a6, + 0x8a4393a0, + 0x31338a54, + 0x31343d33, + 0x70003d34, + 0x8a439a31, + 0x31338a54, + 0x31343d63, + 0x96933d64, + 0xb05396a4, + 0x1e0e7000, + 0x8c3143d6, + 0x18108c40, + 0xc0024fd0, + 0x161110d1, + 0x16201812, + 0x1c203d20, + 0x10204fe4, + 0x63e41610, + 0x3d201620, + 0x4be41cd0, + 0x63e410d0, + 0xc082c000, + 0x8c448c33, + 0x1c241834, + 0x14424fe0, + 0x63e44be2, + 0x63e410d0, + 0x18d0c000, + 0x720d7000, + 0x720f720e, + 0x73117210, + 0x73137312, + 0x70007314, + 0x89f09a00, + 0x47ef2200, + 0x7000b9e0 +}; + +PATCH_FUN_SPEC void rf_patch_mce_tof(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 506; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchTofMce[i]; + } +#else + const uint32_t *pS = patchTofMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 63; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + *pD++ = t1; + *pD++ = t2; +#endif +} + +#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_bt5.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_bt5.h deleted file mode 100644 index ea3f7696c..000000000 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_bt5.h +++ /dev/null @@ -1,610 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_rfe_bt5.h -* Revised: $Date: 2018-02-07 13:42:20 +0100 (on, 07 feb 2018) $ -* Revision: $Revision: 18248 $ -* -* Description: RF core patch for Bluetooth 5 support in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_RFE_BT5_H -#define _RF_PATCH_RFE_BT5_H - -#include -#include "../inc/hw_types.h" - -#ifndef RFE_PATCH_TYPE -#define RFE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_RFERAM_BASE -#define RFC_RFERAM_BASE 0x2100C000 -#endif - -#ifndef RFE_PATCH_MODE -#define RFE_PATCH_MODE 0 -#endif - -RFE_PATCH_TYPE patchBt5Rfe[512] = { - 0x35f8615b, - 0xa24675f9, - 0x1f40a357, - 0x34f11307, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x6fcf7fcf, - 0x4fcf5fcf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x403b2241, - 0x700006f1, - 0x9150c050, - 0xc0707000, - 0x70009150, - 0x00213182, - 0xb1609181, - 0x10257000, - 0x9100c050, - 0xc080c3f4, - 0x6f031420, - 0x04411031, - 0x22f082a0, - 0x26514058, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92551405, - 0x642b7000, - 0x1031c2b2, - 0x31610631, - 0x642e02c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x7000642e, - 0x82b16428, - 0x39813181, - 0x642ec0e2, - 0xc111642b, - 0x642ec122, - 0x688bc470, - 0xc0c2c111, - 0x64a4642e, - 0x700064b7, - 0x82b16440, - 0x39813181, - 0x6446c182, - 0xc1116443, - 0x6446c0a2, - 0x689dc470, - 0xc162c331, - 0x64a46446, - 0x700064b7, - 0xb054b050, - 0x80407100, - 0x44b12240, - 0x40a42200, - 0x8081b060, - 0x44a41e11, - 0xa0547000, - 0x80f0b064, - 0x40a42200, - 0x12407000, - 0xb03290b0, - 0x395382a3, - 0x64713953, - 0x68bfc2f0, - 0xc1f18080, - 0xc1510410, - 0x40cb1c10, - 0xc221642b, - 0x642ec0c2, - 0x644360cf, - 0xc162c441, - 0x80906446, - 0x44d33950, - 0x68d3ce00, - 0x90b01280, - 0x7000b032, - 0xc201642b, - 0x642ec0c2, - 0x318080a0, - 0x68df3940, - 0xc0c2c101, - 0xc101642e, - 0x642ec122, - 0x647182a3, - 0x90b012c0, - 0x7000b032, - 0xc4016443, - 0x6446c162, - 0x318080a0, - 0x68f33940, - 0xc162c301, - 0xc1016446, - 0x6446c0a2, - 0x647182a3, - 0x90b012c0, - 0x7000b032, - 0xc272642b, - 0x642ec081, - 0xc111c122, - 0xc002642e, - 0x642ec111, - 0xc331c062, - 0xc362642e, - 0x642ec111, - 0xc111c302, - 0x82a3642e, - 0x64713953, - 0x6433c3e2, - 0x41162211, - 0xc881c242, - 0xc252642e, - 0x642ec111, - 0xcee1c272, - 0xc202642e, - 0x642ec881, - 0xc801c202, - 0xc170642e, - 0x7000692a, - 0xc242642b, - 0x642ec801, - 0xc011c252, - 0xc272642e, - 0x642ec0e1, - 0xc101c002, - 0xc062642e, - 0x642ec301, - 0xc101c122, - 0xc362642e, - 0x642ec101, - 0xc101c302, - 0x82a3642e, - 0x70006471, - 0x1e118081, - 0xb0504156, - 0x7100b054, - 0x22408040, - 0xa0544157, - 0x80f1b064, - 0x454b2201, - 0x22007000, - 0xb060414b, - 0x73066148, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0xeed08092, - 0x93529341, - 0x224167fa, - 0x8080457f, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61a061a0, - 0x61a061a0, - 0x61a061a0, - 0x61a761a3, - 0x61b161ad, - 0x62d361a0, - 0xc0f062d6, - 0x31320402, - 0x14122a41, - 0x11011632, - 0x6c011421, - 0x61a161bf, - 0x61a561bf, - 0x61a961af, - 0x61a061a0, - 0x61b362f4, - 0x61a562f4, - 0x61a961b5, - 0x61a061a0, - 0x61a161c5, - 0x61a561c5, - 0x61a961af, - 0x61a061a0, - 0x65d661b8, - 0x648061b8, - 0x648061b8, - 0x64d86548, - 0x649261b8, - 0x64ec6548, - 0x650061b8, - 0x650061b8, - 0x652c65d6, - 0x66fe61b8, - 0x650061b8, - 0x61b166fe, - 0x61bbb0b0, - 0x7306b0b1, - 0xb0307205, - 0x7810615f, - 0x7832c451, - 0xc5247853, - 0x782061ca, - 0x7842c451, - 0xc4c47853, - 0x926091a4, - 0x92829271, - 0xc0159293, - 0xc3f09245, - 0xc0f092b0, - 0x61b890a0, - 0x66cfb0e3, - 0x80f0a054, - 0x45e02250, - 0x22008040, - 0x61d846c3, - 0xc800a0e3, - 0x81a991b0, - 0x8091b050, - 0x469e2241, - 0x12f18262, - 0x102f0412, - 0x142f311f, - 0x22d68266, - 0xc08045f3, - 0xc18061f4, - 0x6f0d1420, - 0x10de396d, - 0x044ec3f4, - 0x3182c082, - 0x396d002e, - 0x3182c0a2, - 0x826a002d, - 0x06fa398a, - 0x31808270, - 0xc00b3980, - 0x10bc180b, - 0x825318ac, - 0x149b1439, - 0x06f08260, - 0x31101001, - 0x81a11410, - 0x140c1410, - 0x39408280, - 0x100206f0, - 0x3001c011, - 0x1801c010, - 0x31821802, - 0x26c10021, - 0xcec091e1, - 0x22c667fa, - 0xb003465a, - 0xb063b013, - 0x8041b053, - 0x46c32201, - 0x92148204, - 0x1cb58225, - 0x18954e39, - 0x80f091b5, - 0x422b2210, - 0x913d629c, - 0x913eb110, - 0x80e0b110, - 0x46432200, - 0x424322e6, - 0x1895b0e0, - 0x925f91b5, - 0x14f981a9, - 0x225080f0, - 0x221041d6, - 0x62d9469c, - 0x81a966cf, - 0x14598255, - 0x7100c0f0, - 0x6a53b063, - 0x422b22c6, - 0x6272a0e0, - 0x39808280, - 0x100206f0, - 0x3001c011, - 0x1801c010, - 0x31821802, - 0x26c10021, - 0x828791d1, - 0x39873947, - 0xb013b003, - 0xb053b063, - 0xb0637100, - 0xb012b002, - 0x22018041, - 0x81f446c3, - 0x82259214, - 0x4e801cb5, - 0x91b51895, - 0x221080f0, - 0x629c4272, - 0x92148204, - 0x18458224, - 0x4e8a1c75, - 0x221080f0, - 0x629c4272, - 0xb110913d, - 0x220080e0, - 0x22e64692, - 0xb0e04292, - 0x925f91b5, - 0x14f981a9, - 0x225080f0, - 0x221041d6, - 0x62d9469c, - 0x67faceb0, - 0x8280b063, - 0x100206f0, - 0x3001c011, - 0x1801c010, - 0x31821802, - 0x26c10021, - 0xb01391e1, - 0xb063b003, - 0xb064b053, - 0x7100b054, - 0x22018041, - 0xb06346c3, - 0x80f0b064, - 0x41d62250, - 0x46b12240, - 0x92118201, - 0x18918221, - 0xb03191b1, - 0xa0e362b1, - 0x8251a0e0, - 0x318281b2, - 0xeea03d82, - 0x93529341, - 0xa00367fa, - 0x82627000, - 0x06f23942, - 0x80a2604b, - 0x61b8644b, - 0x7100b050, - 0x829061b8, - 0x22018041, - 0x820446c3, - 0x82259214, - 0x91b51895, - 0x221180f1, - 0x6ada469c, - 0x22018041, - 0x820446c3, - 0x82259214, - 0x4a4e1cc5, - 0x91b51895, - 0x221080f0, - 0x629c42e6, - 0x91e07860, - 0x9250c2d0, - 0x7870c4c4, - 0xc132c2e1, - 0x61cacb03, - 0xb0e3a0e2, - 0x80f0a054, - 0x47082250, - 0x22008040, - 0x630047ef, - 0xa040a0e3, - 0x8260827d, - 0x0410c0f1, - 0x826a1009, - 0x041a394a, - 0x39808260, - 0x100e0410, - 0x10bc10ab, - 0x644b10c2, - 0x67face90, - 0xb003b013, - 0xb05367a1, - 0xb054b050, - 0xb013b064, - 0x678a6781, - 0x80417100, - 0x47ef2201, - 0x221080f0, - 0x22f04736, - 0xb06447dc, - 0x43262231, - 0x67a7b063, - 0x6326675a, - 0x81bfb064, - 0x3d8f318f, - 0x934fde80, - 0x710067fa, - 0x22018041, - 0xb06447ef, - 0x225080f0, - 0xb063434f, - 0x22c18261, - 0x67a7474a, - 0x22d18261, - 0x675a473d, - 0x81b1633d, - 0x318181c2, - 0x31823d81, - 0xee703d82, - 0x93529341, - 0x62fe67fa, - 0x92108200, - 0x18d38223, - 0x0bf34f67, - 0x1ce31613, - 0x92134b80, - 0x143b8233, - 0x1ce3636c, - 0x92134b80, - 0x183b8233, - 0x4f7c1cab, - 0x4b7e1c9b, - 0x43801cbc, - 0x826010b2, - 0x437922d0, - 0x221080f0, - 0x644b4780, - 0x63806781, - 0x637010ab, - 0x6370109b, - 0x82807000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6b84, - 0x7000b0e0, - 0x92128202, - 0x82518222, - 0x81a11812, - 0x82911812, - 0x3d813181, - 0x4b981c12, - 0xb032b0e2, - 0x1421c7f1, - 0xc8124f9c, - 0x91c291b2, - 0xb0e1b031, - 0x12087000, - 0xc800c006, - 0x91c091b0, - 0x82517000, - 0x92108200, - 0x18108220, - 0x181081a1, - 0x80e11406, - 0x31828292, - 0x1c203d82, - 0xb0e24bbb, - 0x47bf2221, - 0xce60b032, - 0x222167fa, - 0xa0e243bf, - 0x8281b032, - 0xc0f03941, - 0x1e010401, - 0x161843cd, - 0x3010c010, - 0x47db1c08, - 0x3c101060, - 0xc7f11006, - 0x4fd11461, - 0x91b6c816, - 0x318181c1, - 0x1c163d81, - 0x91c64bd8, - 0xc006b031, - 0x70001208, - 0xb063a003, - 0xb0efb064, - 0x7100652c, - 0x22008040, - 0xb06447ef, - 0xa0ef6500, - 0x80407100, - 0x47ef2200, - 0xb003b064, - 0xa0e36326, - 0x81b28251, - 0x3d823182, - 0x9341ee50, - 0x67fa9352, - 0x7000a003, - 0x83209330, - 0x47fb2200, - 0x7000b310 -}; - -PATCH_FUN_SPEC void rf_patch_rfe_bt5(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 512; i++) { - HWREG(RFC_RFERAM_BASE + 4 * i) = patchBt5Rfe[i]; - } -#else - const uint32_t *pS = patchBt5Rfe; - volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 64; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); -#endif -} - -#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_genfsk.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_genfsk.h deleted file mode 100644 index 6cd4247a2..000000000 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_genfsk.h +++ /dev/null @@ -1,611 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_rfe_genfsk.h -* Revised: $Date: 2018-01-24 16:44:53 +0100 (on, 24 jan 2018) $ -* Revision: $Revision: 18195 $ -* -* Description: RF core patch for Generic FSK support in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - - -#ifndef _RF_PATCH_RFE_GENFSK_H -#define _RF_PATCH_RFE_GENFSK_H - -#include -#include "../inc/hw_types.h" - -#ifndef RFE_PATCH_TYPE -#define RFE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_RFERAM_BASE -#define RFC_RFERAM_BASE 0x2100C000 -#endif - -#ifndef RFE_PATCH_MODE -#define RFE_PATCH_MODE 0 -#endif - -RFE_PATCH_TYPE patchGenfskRfe[512] = { - 0x13076286, - 0x1f2e34f1, - 0x0ab03f13, - 0xff07a000, - 0x4030ffc0, - 0x40014000, - 0x40074003, - 0x404f400f, - 0x41cf40cf, - 0x47cf43cf, - 0x3fcf4fcf, - 0x1fcf2fcf, - 0xc0500fcf, - 0x70009100, - 0x9100c070, - 0x31827000, - 0x91310021, - 0x7000b110, - 0xb1018101, - 0x3182a100, - 0xb1109132, - 0x10119101, - 0x22418141, - 0x06f1402c, - 0xc0507000, - 0x70009150, - 0x9150c070, - 0x31827000, - 0x91810021, - 0x7000b160, - 0xb1518151, - 0x3182a150, - 0xb1609182, - 0x10119151, - 0x22418191, - 0x06f14044, - 0x10257000, - 0x9100c050, - 0xc090c3f4, - 0x6f031420, - 0x04411031, - 0x22f082a0, - 0x26514056, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92551405, - 0x641c7000, - 0x1031c2b2, - 0x31610631, - 0x641f02c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x7000641f, - 0x22d082b0, - 0xc0c244a5, - 0x66416627, - 0x6419657d, - 0xb1109136, - 0xb1109134, - 0xc112665f, - 0xc3406424, - 0x40922201, - 0x1410c5f1, - 0x16356892, - 0x65b91634, - 0x65ebb051, - 0x65eb65c1, - 0x65fa65c9, - 0xb061a051, - 0xc6b0722c, - 0x128068a0, - 0xb03290b0, - 0x64197000, - 0x318182b1, - 0xc0e23981, - 0x665f641f, - 0x82b07000, - 0x44ba22d0, - 0xb05165b1, - 0x65a165eb, - 0x65a965fa, - 0xa05165fa, - 0x722cb061, - 0xc201641c, - 0x641fc0c2, - 0x318080a0, - 0x68c13940, - 0xc0c2c101, - 0xc101641f, - 0x641fc122, - 0x22d082b0, - 0x1a3544cf, - 0x91356419, - 0x82a3b110, - 0x12c0646f, - 0xb03290b0, - 0x82b07000, - 0x44f422d0, - 0x6627c162, - 0x657d6655, - 0x91866431, - 0x9184b160, - 0x6670b160, - 0x68e3c5f0, - 0x16741675, - 0xb05165b9, - 0x65c16609, - 0xa0516609, - 0x722cb061, - 0x68efc6b0, - 0x90b01280, - 0x7000b032, - 0x82b16431, - 0x39813181, - 0x6437c182, - 0x70006670, - 0x22d082b0, - 0x65a14507, - 0x6618b051, - 0x661865a9, - 0xb061a051, - 0x6434722c, - 0xc162c401, - 0x80a06437, - 0x39403180, - 0xc301690e, - 0x6437c162, - 0xc0a2c101, - 0x82b06437, - 0x451c22d0, - 0x64311a75, - 0xb1609185, - 0x646f82a3, - 0x90b012c0, - 0x7000b032, - 0xc272641c, - 0x641fc081, - 0xc111c122, - 0xc002641f, - 0x641fc111, - 0xc331c062, - 0xc362641f, - 0x641fc111, - 0xc111c302, - 0x82a3641f, - 0x646f3953, - 0x6424c3e2, - 0x41382211, - 0xc881c242, - 0xc252641f, - 0x641fc111, - 0xcee1c272, - 0xc202641f, - 0x641fc881, - 0xc801c202, - 0xc170641f, - 0x7000694c, - 0xc242641c, - 0x641fc801, - 0xc011c252, - 0xc272641f, - 0x641fc0e1, - 0xc101c002, - 0xc062641f, - 0x641fc301, - 0xc101c122, - 0xc362641f, - 0x641fc101, - 0xc101c302, - 0x82a3641f, - 0x7000646f, - 0x1e118081, - 0xb0504178, - 0x7100b054, - 0x22408040, - 0xa0544179, - 0x80f1b064, - 0x456d2201, - 0x22007000, - 0xb060416d, - 0xc108616a, - 0x39508270, - 0x1e003980, - 0xc1014186, - 0x14183001, - 0xc1091a18, - 0x39608280, - 0x1e003980, - 0xc1014190, - 0x14193001, - 0x827b1a19, - 0x393b313b, - 0x313b398b, - 0x45991e0b, - 0x828ac01b, - 0x392a312a, - 0x1e0a398a, - 0xc01a45a0, - 0x722c7000, - 0xb2c092e9, - 0x10731062, - 0xc3fd10a1, - 0x722c7000, - 0xb2c092e8, - 0x10531042, - 0xc1fd10b1, - 0x722c7000, - 0x10c292e9, - 0xc4011073, - 0xb2c0c03d, - 0x722c7000, - 0x104292e8, - 0x10b11053, - 0xb2c0c1fd, - 0x722c7000, - 0xb2c092e9, - 0x10731062, - 0xc3fd10a1, - 0x722c7000, - 0xb2c092e9, - 0x10c21073, - 0xc03dc401, - 0xb0507000, - 0x7100b054, - 0x22408040, - 0xb06441dc, - 0x220080f0, - 0x61e241d1, - 0x41d12200, - 0x8081b060, - 0x45d11e11, - 0xa054a050, - 0x90b01240, - 0x82a3b032, - 0x39533953, - 0xc0507000, - 0x10d09100, - 0x7100b061, - 0x1c231412, - 0x91334df6, - 0x7000b110, - 0xb1109132, - 0x700069ee, - 0x9100c050, - 0xb06110d0, - 0x18137100, - 0x4a051c32, - 0xb1109132, - 0x91337000, - 0x69fdb110, - 0xc0507000, - 0x10d09150, - 0x7100b061, - 0x1c231412, - 0x91834e14, - 0x7000b160, - 0xb1609182, - 0x70006a0c, - 0x9150c050, - 0xb06110d0, - 0x18137100, - 0x4a231c32, - 0xb1609182, - 0x91837000, - 0x6a1bb160, - 0x10247000, - 0x1c02c0c0, - 0x6424462d, - 0x643c622e, - 0x10421015, - 0xc0c01612, - 0x1c021610, - 0x64244637, - 0x643c6238, - 0x14153141, - 0x31801040, - 0x10541405, - 0x04047870, - 0xc0e67000, - 0x106c3186, - 0x398182b1, - 0x04017880, - 0x10671416, - 0x04077880, - 0xc3f082b1, - 0x14170401, - 0x318082b0, - 0x140c3980, - 0xc1867000, - 0x10673186, - 0x788082b1, - 0x14160401, - 0x141782b1, - 0x641c7000, - 0xc122c111, - 0xc470641f, - 0xc1116a64, - 0x641fc0c2, - 0x646f65d1, - 0x6a6bc2b0, - 0xc0c2c221, - 0x7000641f, - 0xc1116434, - 0x6437c0a2, - 0x6a75c470, - 0xc162c331, - 0x65d16437, - 0xc2b0646f, - 0xc4416a7c, - 0x6437c162, - 0x00007000, - 0x00000000, - 0x00000000, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xb0608081, - 0x8092a050, - 0x46a62241, - 0xc1f18080, - 0x16300410, - 0x14011101, - 0x62b86c01, - 0x62b862b8, - 0x62b862b8, - 0x62b862b8, - 0x62b862b8, - 0x62b862b8, - 0x62b862b8, - 0x06f18091, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x62b862cd, - 0x62b962cd, - 0x62bd62c1, - 0x62b862b8, - 0x647e62c5, - 0x64ad656a, - 0x64d562c5, - 0x64fc656a, - 0x652262c5, - 0x654e66e5, - 0x121062c5, - 0x720e90b0, - 0x72057306, - 0x90301210, - 0xc460628a, - 0x782091a0, - 0x78309260, - 0x78409270, - 0x78509280, - 0x78609290, - 0x781092b0, - 0xc1f091e0, - 0x826090a0, - 0x06f03940, - 0x31101001, - 0x92501410, - 0xa0bc62c5, - 0xb0e3a0e2, - 0x80f0a054, - 0x46f02250, - 0x22008040, - 0x62e847f6, - 0xa040a0e3, - 0x318d827d, - 0x8260398d, - 0x100906f0, - 0x394a826a, - 0x826006fa, - 0x06f03980, - 0x10ab100e, - 0x10c210bc, - 0x722e6449, - 0x67f9ce40, - 0xb003b013, - 0xb053679a, - 0xb054b050, - 0xb013b064, - 0x8260677c, - 0x471322e0, - 0x71006783, - 0x22018041, - 0x80f047f6, - 0x47262210, - 0x47e322f0, - 0x2231b064, - 0xb0634313, - 0x826067a0, - 0x471322e0, - 0x63136747, - 0x81bfb064, - 0x3d8f318f, - 0x934fde30, - 0x710067f9, - 0x22018041, - 0xb06447f6, - 0x225080f0, - 0xb0634340, - 0x22c18261, - 0x67a0473b, - 0x826167d4, - 0x472d22d1, - 0x632d6747, - 0x318181b1, - 0xde203d81, - 0x67f99341, - 0x820062e5, - 0x82239210, - 0xa2e082e7, - 0x4f5618d3, - 0x16130bf3, - 0x4b7b1ce3, - 0x82339213, - 0x6367143b, - 0x47621cba, - 0x4b621e23, - 0x4f621ce3, - 0x2207b2e0, - 0xa2e04362, - 0x636d1a1b, - 0x4b7b1ce3, - 0x82339213, - 0x1cab183b, - 0x1c9b4f77, - 0x1cbc4b79, - 0x10b2437b, - 0x22d08260, - 0x80f04374, - 0x477b2210, - 0x677c6449, - 0x10ab637b, - 0x109b636b, - 0x7000636b, - 0x06f08280, - 0x7100b063, - 0x10bc6b7e, - 0x82027000, - 0x82229212, - 0x18128251, - 0x181281a1, - 0x31818291, - 0x1c123d81, - 0xb0e24b91, - 0xc7f1b032, - 0x4f951421, - 0x91b2c812, - 0xb03191c2, - 0x7000b0e1, - 0xc0061208, - 0x91b0c800, - 0x700091c0, - 0x82008251, - 0x82209210, - 0x81a11810, - 0x14061810, - 0x829280e1, - 0x3d823182, - 0x4bb41c20, - 0x2221b0e2, - 0xb03247b8, - 0x67f9ce10, - 0x43b82221, - 0xb032a0e2, - 0x39418281, - 0x1e0106f1, - 0x161843c5, - 0x3010c010, - 0x47d31c08, - 0x3c101060, - 0xc7f11006, - 0x4fc91461, - 0x91b6c816, - 0x318181c1, - 0x1c163d81, - 0x91c64bd0, - 0xc006b031, - 0x70001208, - 0x318181b1, - 0x82903d81, - 0x18013980, - 0x4be21cf1, - 0x80b01401, - 0x47e222c0, - 0xb033b0bc, - 0xa0037000, - 0xb064b063, - 0x654eb0ef, - 0x80407100, - 0x47f62200, - 0x6522b064, - 0x7100a0ef, - 0x22008040, - 0xb06447f6, - 0x6313b003, - 0xa003a0e3, - 0x93307000, - 0x22008320, - 0xb31047fa, - 0x00007000 -}; - -PATCH_FUN_SPEC void rf_patch_rfe_genfsk(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 512; i++) { - HWREG(RFC_RFERAM_BASE + 4 * i) = patchGenfskRfe[i]; - } -#else - const uint32_t *pS = patchGenfskRfe; - volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 64; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); -#endif -} - -#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_ieee_802_15_4.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_ieee_802_15_4.h deleted file mode 100644 index 268878e39..000000000 --- a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_ieee_802_15_4.h +++ /dev/null @@ -1,438 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_rfe_ieee_802_15_4.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ -* -* Description: RF core patch for IEEE 802.15.4-2006 support in CC13x2 and CC26x2. Contains fix to correct RSSIMAXVAL calculation. -* -* Copyright (c) 2015-2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -// It should only be included from ONE source file to avoid duplicated constant arrays - - -#ifndef _RF_PATCH_RFE_IEEE_802_15_4_H -#define _RF_PATCH_RFE_IEEE_802_15_4_H - -#include -#include "../inc/hw_types.h" - -#ifndef RFE_PATCH_TYPE -#define RFE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_RFERAM_BASE -#define RFC_RFERAM_BASE 0x2100C000 -#endif - -#ifndef RFE_PATCH_MODE -#define RFE_PATCH_MODE 0 -#endif - -RFE_PATCH_TYPE patchIeee_802_15_4Rfe[331] = { - 0x163f614a, - 0x07ff07f7, - 0x000f0046, - 0x00040000, - 0x003f002e, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x402d2241, - 0x700006f1, - 0x9150c050, - 0xc0707000, - 0x70009150, - 0x00213182, - 0xb1609181, - 0x10257000, - 0x9100c050, - 0xc0a0c3f4, - 0x6f031420, - 0x04411031, - 0x22f082a0, - 0x2651404a, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92551405, - 0x641d7000, - 0x1031c2b2, - 0x31610631, - 0x642002c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006420, - 0x82b1641a, - 0x39813181, - 0x6420c0e2, - 0xc111641d, - 0x6420c122, - 0x687dc470, - 0xc0c2c111, - 0x64966420, - 0x700064a9, - 0x82b16432, - 0x39813181, - 0x6438c182, - 0xc1116435, - 0x6438c0a2, - 0x688fc470, - 0xc162c331, - 0x64966438, - 0x700064a9, - 0xb054b050, - 0x80407100, - 0x44a32240, - 0x40962200, - 0x8081b060, - 0x44961e11, - 0xa0547000, - 0x80f0b064, - 0x40962200, - 0x12407000, - 0xb03290b0, - 0x395382a3, - 0x64633953, - 0x68b1c2f0, - 0xc1f18080, - 0xc1510410, - 0x40bd1c10, - 0xc221641d, - 0x6420c0c2, - 0x643560c1, - 0xc162c441, - 0xce306438, - 0x128068c2, - 0xb03290b0, - 0x641d7000, - 0xc0c2c201, - 0x80a06420, - 0x39403180, - 0xc10168ce, - 0x6420c0c2, - 0xc122c101, - 0x82a36420, - 0x12c06463, - 0xb03290b0, - 0x64357000, - 0xc162c401, - 0x80a06438, - 0x39403180, - 0xc30168e2, - 0x6438c162, - 0xc0a2c101, - 0x82a36438, - 0x12c06463, - 0xb03290b0, - 0x641d7000, - 0xc081c272, - 0xc1226420, - 0x6420c111, - 0xc111c002, - 0xc0626420, - 0x6420c331, - 0xc111c362, - 0xc3026420, - 0x6420c111, - 0x395382a3, - 0xc3e26463, - 0x22116425, - 0xc2424105, - 0x6420c881, - 0xc111c252, - 0xc2726420, - 0x6420cee1, - 0xc881c202, - 0xc2026420, - 0x6420c801, - 0x6919c170, - 0x641d7000, - 0xc801c242, - 0xc2526420, - 0x6420c011, - 0xc0e1c272, - 0xc0026420, - 0x6420c101, - 0xc301c062, - 0xc1226420, - 0x6420c101, - 0xc101c362, - 0xc3026420, - 0x6420c101, - 0x646382a3, - 0x80817000, - 0x41451e11, - 0xb054b050, - 0x80407100, - 0x41462240, - 0xb064a054, - 0x220180f1, - 0x7000453a, - 0x413a2200, - 0x6137b060, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xb0608081, - 0x8092a050, - 0x9341ef80, - 0x668f9352, - 0x456e2241, - 0xc1f18080, - 0x16300410, - 0x14011101, - 0x617f6c01, - 0x617f617f, - 0x617f617f, - 0x6180617f, - 0x61846182, - 0x617f6186, - 0x6272626f, - 0x0402c0f0, - 0x2a413132, - 0x16321412, - 0x14211101, - 0x61a46c01, - 0x61a46188, - 0x618e618a, - 0x617f6192, - 0x6196617f, - 0x61966472, - 0x619664c7, - 0x619664ef, - 0x6196651b, - 0x619665ba, - 0x65376472, - 0x619664c7, - 0x65ba64ef, - 0x6196651b, - 0x65376484, - 0x619664db, - 0xdf708082, - 0x668f9342, - 0x90b01210, - 0x1220619f, - 0x730690b0, - 0x12107205, - 0x614e9030, - 0x91a07840, - 0x31107850, - 0x14107851, - 0x78709250, - 0x78513140, - 0x31400010, - 0x00107861, - 0x78809260, - 0x78909270, - 0xc0f092b0, - 0x619690a0, - 0xa054b0e3, - 0x225080f0, - 0x804045c3, - 0x46642200, - 0xa0e361ba, - 0x668fcf60, - 0x10e9826e, - 0x394e06f9, - 0x06fa10ea, - 0x394e10ac, - 0x10c206fe, - 0x827d643d, - 0x80f310cb, - 0x41d82213, - 0x61db6675, - 0x41db2223, - 0x78104682, - 0x662f91e0, - 0xb053b013, - 0xb050b063, - 0xb064b054, - 0x80f3b003, - 0x41ba2253, - 0x80417100, - 0x46642201, - 0x41f82241, - 0x80f3b064, - 0x41f42213, - 0x61e56675, - 0x41e52223, - 0x61e56682, - 0x8200b063, - 0x822f9210, - 0x318080e0, - 0x318f3980, - 0x90e000f0, - 0x80f3822f, - 0x46622203, - 0x22408090, - 0x10f34662, - 0x4e1418d3, - 0x16130bf3, - 0x4a621ce3, - 0x82339213, - 0x6219143b, - 0x4a621ce3, - 0x82339213, - 0x1cab183b, - 0x1c9b4e2b, - 0x1cbc4a2d, - 0x1cbc4262, - 0xa0e0b0e0, - 0x10b210bc, - 0x663f643d, - 0xb063663f, - 0xb0637100, - 0x10ab61e5, - 0x109b621d, - 0x7827621d, - 0x18707830, - 0xc0011a10, - 0x16176e71, - 0x78276a34, - 0xc0061208, - 0x91b0c800, - 0x10007000, - 0x10f01000, - 0x18108251, - 0x6d716d71, - 0x14061816, - 0x16176e70, - 0x1c177831, - 0x7827464c, - 0x1e881618, - 0x1060465f, - 0x81a13d30, - 0x80f11810, - 0x425f2251, - 0x81c191b0, - 0x3d813181, - 0x4a5d1c10, - 0xb03191c0, - 0x70001278, - 0x10001000, - 0x61e5663f, - 0x8251a0e3, - 0x318281b2, - 0xef503d82, - 0x93529341, - 0xa003668f, - 0x80a27000, - 0x6196643d, - 0x7100b050, - 0xc0506196, - 0xc0029100, - 0x3182c551, - 0x91310021, - 0xb0e1b110, - 0xcf40a0e2, - 0x7000668f, - 0x9100c050, - 0xca91c002, - 0x00213182, - 0xb1109131, - 0xb0e2a0e1, - 0x668fcf30, - 0x93307000, - 0x22008320, - 0xb3104690, - 0x00007000 -}; - -PATCH_FUN_SPEC void rf_patch_rfe_ieee_802_15_4(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 331; i++) { - HWREG(RFC_RFERAM_BASE + 4 * i) = patchIeee_802_15_4Rfe[i]; - } -#else - const uint32_t *pS = patchIeee_802_15_4Rfe; - volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 41; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; -#endif -} - -#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h new file mode 100644 index 000000000..d09cb4ad8 --- /dev/null +++ b/third_party/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h @@ -0,0 +1,571 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_tof.h +* Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $ +* Revision: $Revision: 18843 $ +* +* Description: RF core RFE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2 +* +* Copyright (c) 2015-2019, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_TOF_H +#define _RF_PATCH_RFE_TOF_H + +#include +#include "../inc/hw_types.h" + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static inline +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchTofRfe[461] = { + 0x00006194, + 0x004535aa, + 0x0421a355, + 0x1f40004c, + 0x0000003f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x6fcf7fcf, + 0x4fcf5fcf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x40772241, + 0x700006f1, + 0x9150c050, + 0xc0707000, + 0x70009150, + 0x00213182, + 0xb1609181, + 0x10257000, + 0x9100c050, + 0xc140c3f4, + 0x6f031420, + 0x04411031, + 0x22f082a0, + 0x26514094, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92551405, + 0x64677000, + 0x1031c2b2, + 0x31610631, + 0x646a02c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x7000646a, + 0x82b16464, + 0x39813181, + 0x646ac0e2, + 0xc1116467, + 0x646ac122, + 0x68c7c470, + 0xc0c2c111, + 0x64e0646a, + 0x700064f3, + 0x82b1647c, + 0x39813181, + 0x6482c182, + 0xc111647f, + 0x6482c0a2, + 0x68d9c470, + 0xc162c331, + 0x64e06482, + 0x700064f3, + 0xb054b050, + 0x80407100, + 0x44ed2240, + 0x40e02200, + 0x8081b060, + 0x44e01e11, + 0xa0547000, + 0x80f0b064, + 0x40e02200, + 0x12407000, + 0xb03290b0, + 0x395382a3, + 0x64ad3953, + 0x68fbc2f0, + 0xc1f18080, + 0xc1510410, + 0x41071c10, + 0xc2216467, + 0x646ac0c2, + 0x647f610b, + 0xc162c441, + 0xce306482, + 0x1280690c, + 0xb03290b0, + 0x64677000, + 0xc0c2c201, + 0x80a0646a, + 0x39403180, + 0xc1016918, + 0x646ac0c2, + 0xc122c101, + 0x82a3646a, + 0x12c064ad, + 0xb03290b0, + 0x647f7000, + 0xc162c401, + 0x80a06482, + 0x39403180, + 0xc301692c, + 0x6482c162, + 0xc0a2c101, + 0x82a36482, + 0x12c064ad, + 0xb03290b0, + 0x64677000, + 0xc081c272, + 0xc122646a, + 0x646ac111, + 0xc111c002, + 0xc062646a, + 0x646ac331, + 0xc111c362, + 0xc302646a, + 0x646ac111, + 0x395382a3, + 0xc3e264ad, + 0x2211646f, + 0xc242414f, + 0x646ac881, + 0xc111c252, + 0xc272646a, + 0x646acee1, + 0xc881c202, + 0xc202646a, + 0x646ac801, + 0x6963c170, + 0x64677000, + 0xc801c242, + 0xc252646a, + 0x646ac011, + 0xc0e1c272, + 0xc002646a, + 0x646ac101, + 0xc301c062, + 0xc122646a, + 0x646ac101, + 0xc101c362, + 0xc302646a, + 0x646ac101, + 0x64ad82a3, + 0x80817000, + 0x418f1e11, + 0xb054b050, + 0x80407100, + 0x41902240, + 0xb064a054, + 0x220180f1, + 0x70004584, + 0x41842200, + 0x6181b060, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xa050b060, + 0x80928081, + 0x45b32241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x61c66c01, + 0x61c661c6, + 0x61c661c6, + 0x61e661c6, + 0x61e661c6, + 0x61c661c6, + 0x809161c6, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x61c661cf, + 0x61c661cf, + 0x61c661c6, + 0x61c661c6, + 0x61c861c8, + 0x61cbb0b0, + 0x7306b0b1, + 0xb0307205, + 0x78206198, + 0x78427831, + 0x78547873, + 0x78667885, + 0x92719260, + 0x92939282, + 0x92b592a4, + 0xc01f91a6, + 0x3940924f, + 0x100106f0, + 0x14103110, + 0x61c89250, + 0xcff0b060, + 0x66306793, + 0xb0e16624, + 0xb054b050, + 0x8262b064, + 0x39823182, + 0x64873942, + 0x7100b0e1, + 0x22008040, + 0xb0644621, + 0x225280f2, + 0x22224611, + 0x22324608, + 0x1e02460f, + 0xdfe041f5, + 0x67939342, + 0x61f56511, + 0x663f663a, + 0x80f0b064, + 0x46112250, + 0x663561f5, + 0xcfd061f5, + 0xa0546793, + 0xa050b064, + 0xa052b060, + 0xa053b062, + 0x6565b063, + 0xcfc06511, + 0x720e6793, + 0xcfb061c8, + 0x62116793, + 0x82b16464, + 0x39813181, + 0x646ac0e2, + 0xc1116467, + 0x646ac122, + 0x700064f3, + 0x70006539, + 0x70006511, + 0x64676565, + 0xc0c2c111, + 0x7000646a, + 0xc1016467, + 0x646ac0c2, + 0xc8007000, + 0x81a991b0, + 0x8091b050, + 0x46b02241, + 0x31828262, + 0x39423982, + 0x82626487, + 0x102f06f2, + 0x142f311f, + 0x22d68266, + 0xc1404655, + 0xc5006256, + 0x6f0d1420, + 0x10de396d, + 0x044ec3f4, + 0x3182c082, + 0x396d002e, + 0x3182c0a2, + 0x826a002d, + 0x06fa398a, + 0x31808270, + 0xc00b3980, + 0x10bc180b, + 0x825318ac, + 0x149b1439, + 0x06f08260, + 0x31101001, + 0x81a11410, + 0x140c1410, + 0x46ea22c6, + 0x39408280, + 0x100206f0, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0xb00391e1, + 0xb063b013, + 0x8041b053, + 0x46e12201, + 0x92148204, + 0x1cb58225, + 0x18954e99, + 0x80f091b5, + 0x428b2240, + 0x913d62ae, + 0x913eb110, + 0x80e0b110, + 0x46a32200, + 0x42a322e6, + 0x1895b0e0, + 0x925f91b5, + 0x14f981a9, + 0x225080f0, + 0x224046e1, + 0x637646ae, + 0x6793cfa0, + 0xa052b063, + 0xc0f28280, + 0x10020420, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0x720e91e1, + 0xb01391e1, + 0xb063b003, + 0xb064b053, + 0x7100b054, + 0x22018041, + 0xb06346e1, + 0x80f0b064, + 0x42e12220, + 0x92118201, + 0x18918221, + 0xb03191b1, + 0x674e62c7, + 0x81a9a0e0, + 0x14598255, + 0x7100c080, + 0x6addb063, + 0xb0e6628b, + 0xa053a052, + 0x81b28251, + 0x3d823182, + 0x7000a003, + 0x39478287, + 0x82803987, + 0x06f03980, + 0xc0111002, + 0xc0103001, + 0x18021801, + 0x00213182, + 0x91d126c1, + 0xb012b002, + 0x39408280, + 0x100206f0, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0xb00391e1, + 0xb063b013, + 0x7100b053, + 0xb062a053, + 0x8041b052, + 0x46e12201, + 0x921481f4, + 0x82048225, + 0x4f201cb5, + 0x91b51895, + 0x224080f0, + 0x62ae4311, + 0x92148204, + 0x10408224, + 0x91b01890, + 0x1c751845, + 0x80f04f2d, + 0x43112240, + 0x913d62ae, + 0x913eb110, + 0x80e0b110, + 0x47372200, + 0x433722e6, + 0x91b5b0e0, + 0x81a9925f, + 0x80f014f9, + 0x463f2250, + 0x46ae2240, + 0x674e6355, + 0x81a9a0e0, + 0x14598255, + 0x7100c140, + 0x6b47b062, + 0x80a26311, + 0x61c86487, + 0x39428262, + 0x608706f2, + 0x7100b050, + 0x829061c8, + 0x22018041, + 0x81f446e1, + 0x82259214, + 0x91b51895, + 0x224180f1, + 0x6b5646ae, + 0x318181b1, + 0xdf903d81, + 0x67939341, + 0x22018041, + 0x81f446e1, + 0x82259214, + 0x4b411cc5, + 0x91b51895, + 0x224080f0, + 0x62ae4362, + 0x6793cf80, + 0x80418290, + 0x46e12201, + 0x92148204, + 0x18958225, + 0x80f191b5, + 0x46ae2241, + 0x80416b79, + 0x46e12201, + 0x92148204, + 0x1cc58225, + 0x18954ad7, + 0x80f091b5, + 0x43852240, + 0x933062ae, + 0x22008320, + 0xb3104794, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_tof(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 461; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchTofRfe[i]; + } +#else + const uint32_t *pS = patchTofRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 57; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} + +#endif diff --git a/third_party/ti/devices/cc13x2_cc26x2/rom/driverlib.c b/third_party/ti/devices/cc13x2_cc26x2/rom/driverlib.c index fb87586f9..7367cdc9c 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/rom/driverlib.c +++ b/third_party/ti/devices/cc13x2_cc26x2/rom/driverlib.c @@ -1,4 +1,5 @@ #include "../driverlib/adi.h" +#include "../driverlib/aes.h" #include "../driverlib/aon_batmon.h" #include "../driverlib/aon_batmon.h" #include "../driverlib/aon_batmon.h" @@ -17,6 +18,8 @@ #include "../driverlib/ddi.h" #include "../driverlib/event.h" #include "../driverlib/flash.h" +#include "../driverlib/flash.h" +#include "../driverlib/gpio.h" #include "../driverlib/i2c.h" #include "../driverlib/i2s.h" #include "../driverlib/interrupt.h" @@ -24,10 +27,13 @@ #include "../driverlib/ioc.h" #include "../driverlib/osc.h" #include "../driverlib/osc.h" +#include "../driverlib/pka.h" #include "../driverlib/prcm.h" #include "../driverlib/pwr_ctrl.h" #include "../driverlib/setup_rom.h" #include "../driverlib/setup_rom.h" +#include "../driverlib/setup_rom.h" +#include "../driverlib/sha2.h" #include "../driverlib/smph.h" #include "../driverlib/ssi.h" #include "../driverlib/sys_ctrl.h" @@ -53,6 +59,7 @@ #include "../inc/hw_fcfg1.h" #include "../inc/hw_fcfg1.h" #include "../inc/hw_fcfg1.h" +#include "../inc/hw_ioc.h" #include "../inc/hw_memmap.h" #include "../inc/hw_memmap.h" #include "../inc/hw_types.h" @@ -62,10 +69,16 @@ //***************************************************************************** // -//! Disable all external interrupts +// Disable all external interrupts // //***************************************************************************** -#if defined(__IAR_SYSTEMS_ICC__) +#if defined(DOXYGEN) +uint32_t +CPUcpsid(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) uint32_t CPUcpsid(void) { @@ -88,7 +101,7 @@ CPUcpsid(void) cpsid i; bx lr } -#elif defined(__TI_COMPILER_VERSION__) || defined(DOXYGEN) +#elif defined(__TI_COMPILER_VERSION__) uint32_t CPUcpsid(void) { @@ -111,10 +124,11 @@ CPUcpsid(void) uint32_t ui32Ret; // Read PRIMASK and disable interrupts - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " bx lr\n" - : "=r"(ui32Ret)); + __asm volatile (" mrs %0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); // The return is handled in the inline assembly, but the compiler will // still complain if there is not an explicit return here (despite the fact @@ -125,10 +139,16 @@ CPUcpsid(void) #endif //***************************************************************************** // -//! Enable all external interrupts +// Enable all external interrupts // //***************************************************************************** -#if defined(__IAR_SYSTEMS_ICC__) +#if defined(DOXYGEN) +uint32_t +CPUcpsie(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) uint32_t CPUcpsie(void) { @@ -151,7 +171,7 @@ CPUcpsie(void) cpsie i; bx lr } -#elif defined(__TI_COMPILER_VERSION__) || defined(DOXYGEN) +#elif defined(__TI_COMPILER_VERSION__) uint32_t CPUcpsie(void) { @@ -174,10 +194,11 @@ CPUcpsie(void) uint32_t ui32Ret; // Read PRIMASK and enable interrupts. - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " bx lr\n" - : "=r"(ui32Ret)); + __asm volatile (" mrs %0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); // The return is handled in the inline assembly, but the compiler will // still complain if there is not an explicit return here (despite the fact @@ -188,14 +209,20 @@ CPUcpsie(void) #endif //***************************************************************************** // -//! Provide a small delay +// Provide a small delay // //***************************************************************************** -#if defined(__IAR_SYSTEMS_ICC__) +#if defined(DOXYGEN) void CPUdelay(uint32_t ui32Count) { - // Delay the specified number of times (3 cycles pr. loop) + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +void +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times __asm("CPUdelay:\n" " subs r0, #1\n" " bne.n CPUdelay\n" @@ -213,11 +240,11 @@ CPUdel bne CPUdel; bx lr; } -#elif defined(__TI_COMPILER_VERSION__) || defined(DOXYGEN) +#elif defined(__TI_COMPILER_VERSION__) // For CCS implement this function in pure assembly. This prevents the TI // compiler from doing funny things with the optimizer. - // Delay the specified number of times (3 cycles pr. loop) + // Loop the specified number of times __asm(" .sect \".text:CPUdelay\"\n" " .clink\n" " .thumbfunc CPUdelay\n" @@ -228,13 +255,17 @@ __asm(" .sect \".text:CPUdelay\"\n" " bne.n CPUdelay\n" " bx lr\n"); #else +// GCC void __attribute__((naked)) CPUdelay(uint32_t ui32Count) { - // Delay the specified number of times (3 cycles pr. loop) - __asm(" subs r0, #1\n" - " bne CPUdelay\n" - " bx lr"); + // Loop the specified number of times + __asm volatile ("%=: subs %0, #1\n" + " bne %=b\n" + " bx lr\n" + : /* No output */ + : "r" (ui32Count) + ); } #endif @@ -568,13 +599,13 @@ static void SetWriteMode(void); static void TrimForWrite(void); static void SetReadMode(void); -void FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriode, uint32_t ui32PumpGracePeriode) { +void FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod) { // Check the arguments. ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || ui32PowerMode == FLASH_PWR_OFF_MODE || ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); - ASSERT(ui32BankGracePeriode <= 0xFF); - ASSERT(ui32PumpGracePeriode <= 0xFFFF); + ASSERT(ui32BankGracePeriod <= 0xFF); + ASSERT(ui32PumpGracePeriod <= 0xFFFF); switch(ui32PowerMode) { @@ -590,15 +621,15 @@ void FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriode, ui break; case FLASH_PWR_OFF_MODE: - // Set bank grace periode. + // Set bank grace period. HWREG(FLASH_BASE + FLASH_O_FBAC) = (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | - ((ui32BankGracePeriode << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); - // Set pump grace periode. + // Set pump grace period. HWREG(FLASH_BASE + FLASH_O_FPAC2) = (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | - ((ui32PumpGracePeriode << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); // Set bank power mode to SLEEP. HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR0_M; @@ -608,15 +639,15 @@ void FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriode, ui break; case FLASH_PWR_DEEP_STDBY_MODE: - // Set bank grace periode. + // Set bank grace period. HWREG(FLASH_BASE + FLASH_O_FBAC) = (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | - ((ui32BankGracePeriode << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); - // Set pump grace periode. + // Set pump grace period. HWREG(FLASH_BASE + FLASH_O_FPAC2) = (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | - ((ui32PumpGracePeriode << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); // Set bank power mode to DEEP STANDBY mode. HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = @@ -756,6 +787,13 @@ uint32_t FlashProtectionSave(uint32_t ui32SectorAddress) { } uint32_t FlashSectorErase(uint32_t ui32SectorAddress) { + // The below code part constitutes the variant of the FlashSectorErase() + // function that is located in ROM. The source code of this variant is not + // visible in internal or external driverlib. The source code is + // only compiled during a ROM build. + // The two above code parts (seperated by compile switches) constitute wrapper + // functions which both call this ROM variant of the function. + // The ROM variant is called by referrencing it directly through the ROM API table. uint32_t ui32ErrorReturn; uint32_t ui32Error; uint32_t ui32SectorBit; @@ -965,6 +1003,13 @@ uint32_t FlashhOtpEngrErase(void) { } uint32_t FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) { + // The below code part constitutes the variant of the FlashProgram() function + // that is located in ROM. The source code of this variant is not visible in + // internal or external driverlib. The source code is only compiled during a ROM + // build. + // The two above code parts (seperated by compile switches) constitute wrapper + // functions which both call this ROM variant of the function. + // The ROM variant is called by referrencing it directly through the ROM API table. uint32_t ui32StartIndex; uint32_t ui32StopIndex; uint32_t ui32Index; @@ -1345,7 +1390,7 @@ uint32_t FlashProgramEngr(uint8_t *pui8DataBuffer, uint32_t ui32AddressOffset, u // Disable sectors for programming. FlashDisableSectorsForWrite(); - // Reenable OTP protection. + // Re-enable OTP protection. HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; @@ -1384,7 +1429,7 @@ void FlashOtpProgramEraseSetup(void) { } void FlashOtpProgramEraseCleanup(void) { - // Reenable OTP protection. + // Re-enable OTP protection. HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS; HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; @@ -1463,9 +1508,9 @@ IssueFsmCommand(tFlashStateCommandsType eCommand) //! This function disables the idle reading power reduction mode, selects the //! flash bank and enables all sectors for erase and programming on the active //! bank. -//! Sectores may be protected from programming depending on the value of the +//! Sectors may be protected from programming depending on the value of the //! FLASH_O_FSM_BSLPx registers. -//! Sectores may be protected from erase depending on the value of the +//! Sectors may be protected from erase depending on the value of the //! FLASH_O_FSM_BSLEx registers. Additional sector erase protection is set by //! the FLASH_O_FSM_SECTOR1 register. //! @@ -1507,35 +1552,39 @@ EnableSectorsForWrite(void) //! Some registers shall be written with a value that is a number of FCLK //! cycles. The trim values controlling these registers have a value of //! number of half us. FCLK = SysClk / ((RWAIT+1) x 2). +//! //! In order to calculate the register value for these registers the //! following calculation must be done: //! -//! OtpValue SysClkMHz -//! -------- us OtpValue x --------- -//! 2 (RWAIT+1) -//! RegValue_in_no_of_clk_cycles = ----------------- = --------------------- -//! 1 4 -//! -------------- -//! SysClkMHz -//! ------------ -//! (RWAIT+1)x 2 +//! OtpValue SysClkMHz +//! -------- us OtpValue x --------- +//! 2 (RWAIT+1) +//! RegValue_in_no_of_clk_cycles = ----------------- = --------------------- +//! 1 4 +//! -------------- +//! SysClkMHz +//! ------------ +//! (RWAIT+1)x 2 //! -//! This is equevivalent to: +//! This is equivalent to: //! -//! 16 x SysClkMHz -//! OtpValue x --------------- -//! (RWAIT+1) -//! RegValue_in_no_of_clk_cycles = ---------------------------- -//! 64 +//! 16 x SysClkMHz +//! OtpValue x --------------- +//! (RWAIT+1) +//! RegValue_in_no_of_clk_cycles = ---------------------------- +//! 64 //! -//! 16 x SysClkMHz -//! A scaling factor is set equal to: ui32FclkScale = -------------- -//! (RWAIT+1) +//! A scaling factor is set equal to: +//! +//! 16 x SysClkMHz +//! ui32FclkScale = -------------- +//! (RWAIT+1) //! //! which gives: -//! OtpValue x ui32FclkScale -//! RegValue_in_no_of_clk_cycles = ------------------------ -//! 64 +//! +//! OtpValue x ui32FclkScale +//! RegValue_in_no_of_clk_cycles = ------------------------ +//! 64 //! //! \return None. // @@ -1569,7 +1618,7 @@ TrimForWrite(void) FLASH_FRDCTL_RWAIT_M) >> FLASH_FRDCTL_RWAIT_S; ui32FclkScale = (16 * FLASH_MODULE_CLK_FREQ) / (ui32RWait + 1); - // Configure Program puls width bits 15:0. + // Configure Program pulse width bits 15:0. // (FCFG1 offset 0x188 bits 15:0). ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) & @@ -1584,7 +1633,7 @@ TrimForWrite(void) ((ui32Value << FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S) & FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M); - // Configure Erase puls width bits 31:0. + // Configure Erase pulse width bits 31:0. // (FCFG1 offset 0x18C bits 31:0). ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_ERA_PW) & @@ -1699,7 +1748,7 @@ TrimForWrite(void) ((ui32Value << FLASH_FSM_PE_OSU_ERA_OSU_S) & FLASH_FSM_PE_OSU_ERA_OSU_M); - // Confgure Program Verify Setup time + // Configure Program Verify Setup time // (FCFG1 offset 0x170 bits 15:8). ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & FCFG1_FLASH_E_P_PVSU_M) >> @@ -3422,7 +3471,7 @@ void PRCMPowerDomainOff(uint32_t ui32Domains) { if(ui32Domains & PRCM_DOMAIN_VIMS) { // Write bits ui32Domains[17:16] to the VIMS_MODE alias register. - // (Legal values are 0b00 and 0b10 (PRCM_DOMAIN_VIMS or PRCM_DOMAIN_VIMS_OFF_NO_WAKUP)) + // PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP sets VIMS_MODE=0b10. ASSERT(!(ui32Domains & 0x00010000)); HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = ( ui32Domains >> 16 ) & 3; } @@ -3552,6 +3601,12 @@ void PRCMRetentionEnable(uint32_t ui32PowerDomain) { ui32Retention |= PRCM_RAMRETEN_VIMS_M; } + // Enable retention on RFC ULL SRAM. + if(PRCM_DOMAIN_RFCULL_SRAM & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_RFCULL_M; + } + // Reconfigure retention. HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; } @@ -3577,6 +3632,12 @@ void PRCMRetentionDisable(uint32_t ui32PowerDomain) { ui32Retention &= ~PRCM_RAMRETEN_VIMS_M; } + // Disable retention on RFC ULL SRAM. + if(PRCM_DOMAIN_RFCULL_SRAM & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_RFCULL_M; + } + // Reconfigure retention. HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; } @@ -4476,19 +4537,6 @@ void VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) { // First check that it actually is a mode change request if ( ui32NewMode != currentMode ) { - // Due to a hw-problem it is strongly recommended to go via VIMS_MODE_OFF - // when leaving VIMS_MODE_ENABLED (=VIMS_CTL_MODE_CACHE) - // (And no need to go via OFF, if OFF is the final state and will be set later) - if (( currentMode == VIMS_CTL_MODE_CACHE ) && - ( ui32NewMode != VIMS_CTL_MODE_OFF ) ) - { - VIMSModeSet( ui32Base, VIMS_MODE_OFF ); - - while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { - // Do nothing - wait for change to complete. - // (Needed blocking point but it takes only some few cycles) - } - } // Set new mode VIMSModeSet( ui32Base, ui32NewMode ); @@ -4501,759 +4549,9 @@ void VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) { } } -uint32_t CRYPTOAesLoadKey(uint32_t *pui32AesKey, uint32_t ui32KeyLocation) { - // Check the arguments. - ASSERT((ui32KeyLocation == CRYPTO_KEY_AREA_0) | - (ui32KeyLocation == CRYPTO_KEY_AREA_1) | - (ui32KeyLocation == CRYPTO_KEY_AREA_2) | - (ui32KeyLocation == CRYPTO_KEY_AREA_3) | - (ui32KeyLocation == CRYPTO_KEY_AREA_4) | - (ui32KeyLocation == CRYPTO_KEY_AREA_5) | - (ui32KeyLocation == CRYPTO_KEY_AREA_6) | - (ui32KeyLocation == CRYPTO_KEY_AREA_7)); - - // Disable the external interrupt to stop the interrupt form propagating - // from the module to the System CPU. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | - CRYPTO_IRQEN_RESULT_AVAIL; - - // Configure master control module. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_ALGSEL, CRYPTO_ALGSEL_KEY_STORE_BITN) = 1; - - // Clear any outstanding events. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Configure key store module for 128 bit operation. - HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) &= ~CRYPTO_KEYSIZE_SIZE_M; - HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) |= KEY_STORE_SIZE_128; - - // Enable keys to write (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation); - - // Enable Crypto DMA channel 0. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Base address of the key in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey; - - // Total key length in bytes (e.g. 16 for 1 x 128-bit key). - // Writing the length of the key enables the DMA operation. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = KEY_BLENGTH; - - // Wait for the DMA operation to complete. - do - { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & 0x00000001)); - - // Check for errors in DMA and key store. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & - (CRYPTO_IRQSTAT_DMA_BUS_ERR | - CRYPTO_IRQSTAT_KEY_ST_WR_ERR)) == 0) - { - // Acknowledge/clear the interrupt and disable the master control. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; - - // Check status, if error return error code. - if(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) != (0x00000001 << ui32KeyLocation)) - { - return (AES_KEYSTORE_READ_ERROR); - } - } - - // Return success. - return (AES_SUCCESS); -} - -uint32_t CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength, uint32_t *pui32Nonce, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable) { - uint32_t ui32CtrlVal; - - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; - - // Clear any outstanding interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Wait for interrupt lines from module to be cleared - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); - - // If using interrupts clear any pending interrupts and enable interrupts - // for the Crypto module. - if(bIntEnable) - { - IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); - } - - // Configure Master Control module. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; - - // Enable keys to read (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; - - //Wait until key is loaded to the AES module. - do - { - CPUdelay(1); - } - while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); - - // Check for Key store Read error. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) - { - return (AES_KEYSTORE_READ_ERROR); - } - - // Write initialization vector. - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = pui32Nonce[0]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = pui32Nonce[1]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = pui32Nonce[2]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = pui32Nonce[3]; - - // Configure AES engine for AES-CBC with 128-bit key size. - ui32CtrlVal = (CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CBC); - if(bEncrypt) - { - ui32CtrlVal |= CRYPTO_AES128_ENCRYPT; - } - else - { - ui32CtrlVal |= CRYPTO_AES128_DECRYPT; - } - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; - - // Write the length of the crypto block (plain text). - // Low and high part (high part is assumed to be always 0). - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32MsgLength; - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; - HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = 0; - - // Enable Crypto DMA channel 0. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Base address of the input data in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn; - - // Input data length in bytes, equal to the message. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32MsgLength; - - // Enable Crypto DMA channel 1. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - - // Set up the address and length of the output data. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut; - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32MsgLength; - - // Return success - return AES_SUCCESS; -} - -uint32_t CRYPTOAesCbcStatus(void) { - return(CRYPTOAesEcbStatus()); -} - -uint32_t CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable) { - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; - - // Clear any outstanding interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Wait for interrupt lines from module to be cleared - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); - - // If using interrupts clear any pending interrupts and enable interrupts - // for the Crypto module. - if(bIntEnable) - { - IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); - } - - // Configure Master Control module. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; - - // Enable keys to read (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; - - //Wait until key is loaded to the AES module. - do - { - CPUdelay(1); - } - while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); - - // Check for Key store Read error. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) - { - return (AES_KEYSTORE_READ_ERROR); - } - - // Configure AES engine (program AES-ECB-128 encryption and no - // initialization vector - IV). - if(bEncrypt) - { - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_ENCRYPT; - } - else - { - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_DECRYPT; - } - - // Write the length of the data. - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = AES_ECB_LENGTH; - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; - - // Enable Crypto DMA channel 0. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Base address of the input data in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn; - - // Input data length in bytes, equal to the message. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = AES_ECB_LENGTH; - - // Enable Crypto DMA channel 1. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - - // Set up the address and length of the output data. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut; - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = AES_ECB_LENGTH; - - // Return success - return AES_SUCCESS; -} - -uint32_t CRYPTOAesEcbStatus(void) { - uint32_t ui32Status; - - // Get the current DMA status. - ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); - - // Check if DMA is still busy. - if(ui32Status & CRYPTO_DMA_BSY) - { - return (AES_DMA_BSY); - } - - // Check the status of the DMA operation - return error if not success. - if(ui32Status & CRYPTO_DMA_BUS_ERROR) - { - return (AES_DMA_BUS_ERROR); - } - - // Operation successful - disable interrupt and return success. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - return (AES_SUCCESS); -} - -uint32_t CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength , uint32_t *pui32Nonce, uint32_t *pui32PlainText, uint32_t ui32PlainTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable) { - uint32_t ui32CtrlVal; - uint32_t i; - uint32_t *pui32CipherText; - union { - uint32_t w[4]; - uint8_t b[16]; - } ui8InitVec; - - // Input address for the encryption engine is the same as the output. - pui32CipherText = pui32PlainText; - - // Disable global interrupt, enable local interrupt and clear any pending - // interrupts. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | - CRYPTO_IRQEN_RESULT_AVAIL; - - // Configure master control module for AES operation. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; - - // Enable keys to read (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; - - // Wait until key is loaded to the AES module. - do - { - CPUdelay(1); - } - while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); - - // Check for Key store Read error. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) - { - return (AES_KEYSTORE_READ_ERROR); - } - - // Prepare the initialization vector (IV), - // Length of Nonce l(n) = 15 - ui32FieldLength. - ui8InitVec.b[0] = ui32FieldLength - 1; - for(i = 0; i < 12; i++) - { - ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i]; - } - if(ui32FieldLength == 2) - { - ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12]; - } - else - { - ui8InitVec.b[13] = 0; - } - ui8InitVec.b[14] = 0; - ui8InitVec.b[15] = 0; - - // Write initialization vector. - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3]; - - // Configure AES engine. - ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S); - if ( ui32AuthLength >= 2 ) { - ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); - } - ui32CtrlVal |= CRYPTO_AESCTL_CCM; - ui32CtrlVal |= CRYPTO_AESCTL_CTR; - ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; - ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S); - ui32CtrlVal |= (1 << CRYPTO_AESCTL_DIR_S); - ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S); - - // Write the configuration for 128 bit AES-CCM. - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; - - // Write the length of the crypto block (plain text). - // Low and high part (high part is assumed to be always 0). - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32PlainTextLength; - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; - - // Write the length of the header field. - // Also called AAD - Additional Authentication Data. - HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength; - - // Check if any header information (AAD). - // If so configure the DMA controller to fetch the header. - if(ui32HeaderLength != 0) - { - // Enable DMA channel 0. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Register the base address of the header (AAD). - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header; - - // Header length in bytes (may be non-block size aligned). - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength; - - // Wait for completion of the header data transfer, DMA_IN_DONE. - do - { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE)); - - // Check for DMA errors. - if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR) - { - return AES_DMA_BUS_ERROR; - } - } - - // Clear interrupt status. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Wait for interrupt lines from module to be cleared - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); - - // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only - // want interrupt to trigger once RESULT_AVAIL occurs. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; - - - // Is using interrupts enable globally. - if(bIntEnable) - { - IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); - } - - // Enable interrupts locally. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; - - // Perform encryption if requested. - if(bEncrypt) - { - // Enable DMA channel 0 - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // base address of the payload data in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = - (uint32_t)pui32PlainText; - - // Enable DMA channel 1 - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - - // Base address of the output data buffer. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = - (uint32_t)pui32CipherText; - - // Payload data length in bytes, equal to the plaintext length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32PlainTextLength; - // Output data length in bytes, equal to the plaintext length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32PlainTextLength; - } - - return AES_SUCCESS; -} - -uint32_t CRYPTOCcmAuthEncryptStatus(void) { - uint32_t ui32Status; - - // Get the current DMA status. - ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); - - // Check if DMA is still busy. - if(ui32Status & CRYPTO_DMA_BSY) - { - return (AES_DMA_BSY); - } - - // Check the status of the DMA operation - return error if not success. - if(ui32Status & CRYPTO_DMA_BUS_ERROR) - { - return (AES_DMA_BUS_ERROR); - } - - // Operation successful - disable interrupt and return success. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - return (AES_SUCCESS); -} - -uint32_t CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, uint32_t *pui32CcmTag) { - uint32_t volatile ui32Tag[4]; - uint32_t ui32Idx; - - // Result has already been copied to the output buffer by DMA - // Disable master control. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; - - // Read tag - wait for the context ready bit. - do - { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & - CRYPTO_AESCTL_SAVED_CONTEXT_RDY)); - - // Read the Tag registers. - ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); - ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); - ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); - ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); - - for(ui32Idx = 0; ui32Idx < ui32TagLength ; ui32Idx++) - { - *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx); - } - - // Operation successful - clear interrupt status. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - return AES_SUCCESS; -} - -uint32_t CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable) { - uint32_t ui32CtrlVal; - uint32_t i; - uint32_t *pui32PlainText; - uint32_t ui32CryptoBlockLength; - union { - uint32_t w[4]; - uint8_t b[16]; - } ui8InitVec; - - // Input address for the encryption engine is the same as the output. - pui32PlainText = pui32CipherText; - - // Disable global interrupt, enable local interrupt and clear any pending. - // interrupts. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | - CRYPTO_IRQEN_RESULT_AVAIL; - - // Configure master control module for AES operation. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; - - // Enable keys to read (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; - - // Wait until key is loaded to the AES module. - do - { - CPUdelay(1); - } - while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); - - // Check for Key store Read error. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) - { - return (AES_KEYSTORE_READ_ERROR); - } - - // Prepare the initialization vector (IV), - // Length of Nonce l(n) = 15 - ui32FieldLength. - ui8InitVec.b[0] = ui32FieldLength - 1; - for(i = 0; i < 12; i++) - { - ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i]; - } - if(ui32FieldLength == 2) - { - ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12]; - } - else - { - ui8InitVec.b[13] = 0; - } - ui8InitVec.b[14] = 0; - ui8InitVec.b[15] = 0; - - // Write initialization vector. - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3]; - - // Configure AES engine - ui32CryptoBlockLength = ui32CipherTextLength - ui32AuthLength; - ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S); - if ( ui32AuthLength >= 2 ) { - ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); - } - ui32CtrlVal |= CRYPTO_AESCTL_CCM; - ui32CtrlVal |= CRYPTO_AESCTL_CTR; - ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; - ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S); - ui32CtrlVal |= (0 << CRYPTO_AESCTL_DIR_S); - ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S); - - // Write the configuration for 128 bit AES-CCM. - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; - - // Write the length of the crypto block (plain text). - // Low and high part (high part is assumed to be always 0). - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32CryptoBlockLength; - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; - - // Write the length of the header field. - // Also called AAD - Additional Authentication Data. - HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength; - - // Check if any header information (AAD). - // If so configure the DMA controller to fetch the header. - if(ui32HeaderLength != 0) - { - // Enable DMA channel 0. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Register the base address of the header (AAD). - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header; - - // Header length in bytes (may be non-block size aligned). - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength; - - // Wait for completion of the header data transfer, DMA_IN_DONE. - do - { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE)); - - // Check for DMA errors. - if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR) - { - return AES_DMA_BUS_ERROR; - } - } - - // Clear interrupt status. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Wait for interrupt lines from module to be cleared - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); - - // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only - // want interrupt to trigger once RESULT_AVAIL occurs. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; - - // Is using interrupts - clear and enable globally. - if(bIntEnable) - { - IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); - } - - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; - - // Perform decryption if requested. - if(bDecrypt) - { - // Configure the DMA controller - enable both DMA channels. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Base address of the payload data in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = - (uint32_t)pui32CipherText; - - // Payload data length in bytes, equal to the cipher text length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32CryptoBlockLength; - - // Enable DMA channel 1. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - - // Base address of the output data buffer. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = - (uint32_t)pui32PlainText; - - // Output data length in bytes, equal to the cipher text length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32CryptoBlockLength; - } - - return AES_SUCCESS; -} - -uint32_t CRYPTOCcmInvAuthDecryptStatus(void) { - uint32_t ui32Status; - - // Get the current DMA status. - ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); - - // Check if DMA is still busy. - if(ui32Status & CRYPTO_DMA_BSY) - { - return (AES_DMA_BSY); - } - - // Check the status of the DMA operation - return error if not success. - if(ui32Status & CRYPTO_DMA_BUS_ERROR) - { - return (AES_DMA_BUS_ERROR); - } - - // Operation successful - disable interrupt and return success - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - return (AES_SUCCESS); -} - -uint32_t CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32CcmTag) { - uint32_t volatile ui32Tag[4]; - uint32_t ui32TagIndex; - uint32_t i; - uint32_t ui32Idx; - - ui32TagIndex = ui32CipherTextLength - ui32AuthLength; - - // Result has already been copied to the output buffer by DMA - // Disable master control. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; - - // Read tag - wait for the context ready bit. - do - { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & - CRYPTO_AESCTL_SAVED_CONTEXT_RDY)); - - // Read the Tag registers. - ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); - ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); - ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); - ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); - - for(ui32Idx = 0; ui32Idx < ui32AuthLength ; ui32Idx++) - { - *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx); - } - - // Operation successful - clear interrupt status. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Verify the Tag. - for(i = 0; i < ui32AuthLength; i++) - { - if(*((uint8_t *)pui32CcmTag + i) != - (*((uint8_t *)pui32CipherText + ui32TagIndex + i))) - { - return CCM_AUTHENTICATION_FAILED; - } - } - - return AES_SUCCESS; -} - -void CRYPTODmaEnable(uint32_t ui32Channels) { - // Check the arguments. - ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) | - (ui32Channels & CRYPTO_DMA_CHAN1)); - - // Enable the selected channels, - if(ui32Channels & CRYPTO_DMA_CHAN0) - { - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - } - if(ui32Channels & CRYPTO_DMA_CHAN1) - { - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - } -} - -void CRYPTODmaDisable(uint32_t ui32Channels) { - // Check the arguments. - ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) | - (ui32Channels & CRYPTO_DMA_CHAN1)); - - // Enable the selected channels. - if(ui32Channels & CRYPTO_DMA_CHAN0) - { - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 0; - } - if(ui32Channels & CRYPTO_DMA_CHAN1) - { - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 0; - } -} - void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc) { // Check the arguments. ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || - (ui32SrcClk & OSC_SRC_CLK_MF) || (ui32SrcClk & OSC_SRC_CLK_HF)); ASSERT((ui32Osc == OSC_RCOSC_HF) || (ui32Osc == OSC_RCOSC_LF) || @@ -5270,15 +4568,6 @@ void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc) { ui32Osc); } - // Configure the medium frequency source clock - if(ui32SrcClk & OSC_SRC_CLK_MF) - { - DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M, - DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S, - ui32Osc); - } - // Configure the low frequency source clock. if(ui32SrcClk & OSC_SRC_CLK_LF) { @@ -5393,6 +4682,10 @@ void AUXADCDisable(void) { // Ensure that scaling is enabled by default before next use of the ADC ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); + // Flush the FIFO before disabling the clocks + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) + // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately) HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = 0; @@ -5598,12 +4891,16 @@ void SysCtrl_DCDC_VoltageConditionalControl( void ) { } uint32_t SysCtrlResetSourceGet( void ) { - if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & AON_PMCTL_RESETCTL_WU_FROM_SD_M ) { - return ( RSTSRC_WAKEUP_FROM_SHUTDOWN ); + uint32_t aonPmctlResetCtl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ); + + if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_WU_FROM_SD_M ) { + if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M ) { + return ( RSTSRC_WAKEUP_FROM_SHUTDOWN ); + } else { + return ( RSTSRC_WAKEUP_FROM_TCK_NOISE ); + } } else { - return (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & - AON_PMCTL_RESETCTL_RESET_SRC_M ) >> - AON_PMCTL_RESETCTL_RESET_SRC_S ) ; + return (( aonPmctlResetCtl & AON_PMCTL_RESETCTL_RESET_SRC_M ) >> AON_PMCTL_RESETCTL_RESET_SRC_S ); } } @@ -5624,34 +4921,71 @@ int32_t AONBatMonTemperatureGetDegC( void ) { return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 ); } -// We need intrinsic functions for IAR (if used in source code) -#ifdef __IAR_SYSTEMS_ICC__ -#include -#endif + +void SetupStepVddrTrimTo( uint32_t toCode ) { + uint32_t pmctlResetctl_reg ; + int32_t targetTrim ; + int32_t currentTrim ; + + targetTrim = SetupSignExtendVddrTrimValue( toCode & ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M >> ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S )); + currentTrim = SetupSignExtendVddrTrimValue(( + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >> + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ; + + if ( targetTrim != currentTrim ) { + pmctlResetctl_reg = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ); + if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ( pmctlResetctl_reg & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ); + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for VDDR_LOSS_EN setting to propagate + } + + while ( targetTrim != currentTrim ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + + if ( targetTrim > currentTrim ) currentTrim++; + else currentTrim--; + + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = ( + ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) | + ((((uint32_t)currentTrim) << ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) ); + } + + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + + if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = pmctlResetctl_reg; + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate + } + } +} void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ) { - int32_t i32VddrSleepTrim; - int32_t i32VddrSleepDelta; - + // Check for CC1352 boost mode + // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode + if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && + (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) { - i32VddrSleepTrim = SetupSignExtendVddrTrimValue(( - HWREG( FCFG1_BASE + FCFG1_O_LDO_TRIM ) & - FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M ) >> - FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S ) ; - } + // Set VDDS_BOD trim - using masked write {MASK8:DATA8} + // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1 + // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to + // latch new VDDS BOD. Set to 0 first to guarantee a positive transition. + HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + // + // VDDS_BOD_LEVEL = 1 means that boost mode is selected + // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31) + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) = + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) | + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ; + HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; - // Adjust the VDDR_TRIM_SLEEP value with value adjustable by customer (CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA) - // Read and sign extend VddrSleepDelta (in range -8 to +7) - i32VddrSleepDelta = ((((int32_t)ccfg_ModeConfReg ) - << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S )) - >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )); - // Calculate new VDDR sleep trim - i32VddrSleepTrim = ( i32VddrSleepTrim + i32VddrSleepDelta + 1 ); - if ( i32VddrSleepTrim > 21 ) i32VddrSleepTrim = 21; - if ( i32VddrSleepTrim < -10 ) i32VddrSleepTrim = -10; - // Write adjusted value using MASKED write (MASK8) - HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_DCDCCTL1 * 2 )) = (( ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M << 8 ) | - (( i32VddrSleepTrim << ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S ) & ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M )); + SetupStepVddrTrimTo(( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ; + } // 1. // Do not allow DCDC to be enabled if in external regulator mode. @@ -5709,7 +5043,7 @@ void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH2, ui32Trim); ui32Trim = SetupGetTrimForAmpcompTh1(); DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH1, ui32Trim); -#if ( CCFG_BASE == 0x50003000 ) +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) ui32Trim = SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision ); #else ui32Trim = NOROM_SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision ); @@ -5770,21 +5104,20 @@ void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision); DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim); - // Setting FORCE_KICKSTART_EN (ref. CC26_V1_BUG00261). Should also be done for PG2 - // (This is bit 22 in DDI_0_OSC_O_CTL0) - HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_FORCE_KICKSTART_EN; } void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) { uint32_t fcfg1OscConf; uint32_t ui32Trim; +#if ( ! defined( SKIP_SCLK_LF_SRC_CHANGE )) uint32_t currentHfClock; uint32_t ccfgExtLfClk; +#endif - // Examin the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC + // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) { case 2 : - // XOSC source is a 48 MHz xtal + // XOSC source is a 48 MHz crystal // Do nothing (since this is the reset setting) break; case 1 : @@ -5821,14 +5154,14 @@ void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) { } // Not a HPOSC chip - fall through to default default : - // XOSC source is a 24 MHz xtal (default) + // XOSC source is a 24 MHz crystal (default) // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0) HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M; break; } // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO - // Please note that it is up to the custommer to make sure that the external clock source is up and running before XOSC_HF can be used. + // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used. if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) { HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS; } @@ -5841,11 +5174,21 @@ void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) { ui32Trim = SetupGetTrimForXoscHfFastStart(); HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim ); +#if ( defined( SKIP_SCLK_LF_SRC_CHANGE )) + // If SKIP_SCLK_LF_SRC_CHANGE is defined we will skip the switch-statement below, and + // remain on RCOSCHFDLF as LF source (since RCOSCHFDLF is the reset setting). + // (RCOSCHFDLF = Low frequency clock derived from RCOSC_HF). + // Note1: Function SetupAfterColdResetWakeupFromShutDownCfg3() is a ROM function in some devices (R2 and Agama) + // It must be removed from rom.h on these devices in order to avoid that the ROM version is called. + // Note2: It's not possible to enter STANDBY when running the LF clock from RCOSCHFDLF, however IDLE will work just fine. + // RCOSCHFDLF (RCOSC_HF/1536) -> SCLK_LF (=31250 Hz) + SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency +#else // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) { - case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250Hz) + case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz) OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF ); - SetupSetAonRtcSubSecInc( 0x8637BD ); + SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency break; case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) // Set SCLK_LF to use the same source as SCLK_HF @@ -5860,7 +5203,7 @@ void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) { IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S, IOC_PORT_AON_CLK32K, IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis - // Set XOSC_LF in bypass mode to allow external 32k clock + // Set XOSC_LF in bypass mode to allow external 32 kHz clock HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS; // Fall through to set XOSC_LF as SCLK_LF source case 2 : // XOSC_LF -> SLCK_LF (32768 Hz) @@ -5870,6 +5213,7 @@ void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) { OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF ); break; } +#endif // ( ! defined( SKIP_SCLK_LF_SRC_CHANGE )) // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1 HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) = @@ -5878,12 +5222,6 @@ void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) { ADI_4_AUX_ADCREF1_VTRIM_S ) & ADI_4_AUX_ADCREF1_VTRIM_M ); - // Set ADI_4_AUX:ADC0.SMPL_CYCLE_EXP to it's default minimum value (=3) - // (Note: Using MASK8B requires that the bits to be modified must be within the same - // byte boundary which is the case for the ADI_4_AUX_ADC0_SMPL_CYCLE_EXP field) - HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_ADC0 * 2 )) = - ( ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M << 8 ) | ( 3 << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S ); - // Sync with AON SysCtrlAonSync(); } @@ -5892,7 +5230,6 @@ uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ) { uint32_t ui32Fcfg1Value ; uint32_t ui32XoscHfRow ; uint32_t ui32XoscHfCol ; - int32_t i32CustomerDeltaAdjust ; uint32_t ui32TrimValue ; // Use device specific trim values located in factory configuration @@ -5908,15 +5245,16 @@ uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ) { FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >> FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S ); - i32CustomerDeltaAdjust = 0; if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) { // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by - // a define and sign extension must therefore be hardcoded. + // a define and sign extension must therefore be hard coded. // ( A small test program is created verifying the code lines below: // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) - i32CustomerDeltaAdjust = ((int32_t)ccfg_ModeConfReg << 16 ) >> 24; + int32_t i32CustomerDeltaAdjust = + (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ))) + >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W )); while ( i32CustomerDeltaAdjust < 0 ) { ui32XoscHfCol >>= 1; // COL 1 step down @@ -6064,20 +5402,24 @@ uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ) { modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ); // Both fields are signed 4-bit values. This is an assumption when doing the sign extension. - deltaAdjust = ((int32_t)modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S - 4 )) >> 28; + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W )); deltaAdjust += (int32_t)ibiasOffset; if ( deltaAdjust < 0 ) { - deltaAdjust = 0; + deltaAdjust = 0; } if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) { deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ); } ibiasOffset = (uint32_t)deltaAdjust; - deltaAdjust = ((int32_t)modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S - 4 )) >> 28; + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W )); deltaAdjust += (int32_t)ibiasInit; if ( deltaAdjust < 0 ) { - deltaAdjust = 0; + deltaAdjust = 0; } if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) { deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ); @@ -6252,8 +5594,13 @@ void SetupSetCacheModeAccordingToCcfgSetting( void ) { // Note that Mode=0 is equal to MODE_GPRAM vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M ); -#if defined( DO_NOT_ENABLE_CACHE_IN_TRIM_DEVICE ) +#if ( defined( DO_NOT_ENABLE_CACHE_IN_TRIM_DEVICE )) + #if ( defined( CODE_IN_FLASH )) + // Enable cache (and hence disable GPRAM) + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); + #else HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + #endif #else if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) { @@ -6349,3 +5696,1901 @@ void PowerCtrlSourceSet(uint32_t ui32PowerConfig) { PRCMMcuUldoConfigure(true); } } + +void AESSetInitializationVector(const uint32_t *initializationVector) { + // Write initialization vector to the aes registers + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3]; +} + +void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) { + if (channel0Length && channel0Addr) { + // We actually want to perform an operation. Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; // This might need AES_IRQEN_DMA_IN_DONE as well + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Length && channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +uint32_t AESWaitForIRQFlags(uint32_t irqFlags) { + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | + CRYPTO_IRQSTAT_RESULT_AVAIL_M | + CRYPTO_IRQSTAT_DMA_BUS_ERR_M | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags; + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqTrigger; + + return irqTrigger; +} + +uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea) { + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + ASSERT((aesKeyLength == AES_128_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_192_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_256_KEY_LENGTH_BYTES)); + + uint32_t keySize = 0; + + switch (aesKeyLength) { + case AES_128_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_128_BIT; + break; + case AES_192_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_192_BIT; + break; + case AES_256_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_256_BIT; + break; + } + + // Clear any previously written key at the keyLocation + AESInvalidateKey(keyStoreArea); + + // Disable the external interrupt to stop the interrupt form propagating + // from the module to the System CPU. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M; + + // Configure master control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_KEY_STORE; + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQCLR_RESULT_AVAIL); + + // Configure the size of keys contained within the key store + // Do not write to the register if the correct key size is already set. + // Writing to this register causes all current keys to be invalidated. + uint32_t keyStoreKeySize = HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE); + if (keySize != keyStoreKeySize) { + HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = keySize; + } + + // Enable key to write (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = 1 << keyStoreArea; + + // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key). + AESStartDMAOperation(aesKey, aesKeyLength, 0, 0); + + // Wait for the DMA operation to complete. + uint32_t irqTrigger = AESWaitForIRQFlags(CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR); + + // Re-enable interrupts globally. + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // If we had a bus error or the key is not in the CRYPTO_O_KEYWRITTENAREA, return an error. + if ((irqTrigger & (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)) || !(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + // There was an error in writing to the keyStore. + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +uint32_t AESReadFromKeyStore(uint32_t keyStoreArea) { + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Check if there is a valid key in the specified keyStoreArea + if (!(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + return AES_KEYSTORE_AREA_INVALID; + } + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = keyStoreArea; + + // Wait until key is loaded to the AES module. + // We cannot simply poll the IRQ status as only an error is communicated through + // the IRQ status and not the completion of the transfer. + do { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY_M)); + + // Check for keyStore read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M)) { + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength) { + // The intermediate array is used instead of a caller-provided one + // to enable a simple API with no unintuitive alignment or size requirements. + // This is a trade-off of stack-depth vs ease-of-use that came out on the + // ease-of-use side. + uint32_t computedTag[AES_BLOCK_SIZE / sizeof(uint32_t)]; + + // Wait until the computed tag is ready. + while (!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M)); + + // Read computed tag out from the HW registers + // Need to read out all 128 bits in four reads to correctly clear CRYPTO_AESCTL_SAVED_CONTEXT_RDY flag + computedTag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + computedTag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + computedTag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + computedTag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + memcpy(tag, computedTag, tagLength); + + return AES_SUCCESS; +} + +uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength) { + uint32_t resultStatus; + // The intermediate array is allocated on the stack to ensure users do not + // point the tag they provide and the one computed at the same location. + // That would cause memcmp to compare an array against itself. We could add + // a check that verifies that the arrays are not the same. If we did that and + // modified AESReadTag to just copy all 128 bits into a provided array, + // we could save 16 bytes of stack space while making the API much more + // complicated. + uint8_t computedTag[AES_BLOCK_SIZE]; + + resultStatus = AESReadTag(computedTag, tagLength); + + if (resultStatus != AES_SUCCESS) { + return resultStatus; + } + + resultStatus = memcmp(computedTag, tag, tagLength); + + if (resultStatus != 0) { + return AES_TAG_VERIFICATION_FAILED; + } + + return AES_SUCCESS; +} + +void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt) { + uint32_t ctrlVal = 0; + + ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( macLength >= 2 ) { + ctrlVal |= ((( macLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ctrlVal |= CRYPTO_AESCTL_CCM | + CRYPTO_AESCTL_CTR | + CRYPTO_AESCTL_SAVE_CONTEXT | + CRYPTO_AESCTL_CTR_WIDTH_128_BIT; + ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0; + + AESSetCtrl(ctrlVal); +} + +void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength) { + union { + uint32_t word[4]; + uint8_t byte[16]; + } initializationVector = {{0}}; + + initializationVector.byte[0] = 15 - nonceLength - 1; + + memcpy(&(initializationVector.byte[1]), nonce, nonceLength); + + AESSetInitializationVector(initializationVector.word); +} + + +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) +#define MIN(x,y) (((x) < (y)) ? (x) : (y)) +#define INRANGE(x,y,z) ((x) > (y) && (x) < (z)) + + +//***************************************************************************** +// +// Define for the maximum curve size supported by the PKA module in 32 bit +// word. +// \note PKA hardware module can support up to 384 bit curve size due to the +// 2K of PKA RAM. +// +//***************************************************************************** +#define PKA_MAX_CURVE_SIZE_32_BIT_WORD 12 + +//***************************************************************************** +// +// Define for the maximum length of the big number supported by the PKA module +// in 32 bit word. +// +//***************************************************************************** +#define PKA_MAX_LEN_IN_32_BIT_WORD PKA_MAX_CURVE_SIZE_32_BIT_WORD + +//***************************************************************************** +// +// Used in PKAWritePkaParam() and PKAWritePkaParamExtraOffset() to specify that +// the base address of the parameter should not be written to a NPTR register. +// +//***************************************************************************** +#define PKA_NO_POINTER_REG 0xFF + +//***************************************************************************** +// +// NIST P224 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP224_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint224 NISTP224_generator = { + .x = {.byte = {0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34, + 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A, + 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B, + 0xBD, 0x0C, 0x0E, 0xB7, }}, + .y = {.byte = {0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44, + 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD, + 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5, + 0x88, 0x63, 0x37, 0xBD, }}, +}; + +const PKA_EccParam224 NISTP224_prime = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +const PKA_EccParam224 NISTP224_a = {.byte = {0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +const PKA_EccParam224 NISTP224_b = {.byte = {0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27, + 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50, + 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C, + 0x85, 0x0A, 0x05, 0xB4}}; + +const PKA_EccParam224 NISTP224_order = {.byte = {0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13, + 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +//***************************************************************************** +// +// NIST P256 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP256_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 NISTP256_generator = { + .x = {.byte = {0x96, 0xc2, 0x98, 0xd8, 0x45, 0x39, 0xa1, 0xf4, + 0xa0, 0x33, 0xeb, 0x2d, 0x81, 0x7d, 0x03, 0x77, + 0xf2, 0x40, 0xa4, 0x63, 0xe5, 0xe6, 0xbc, 0xf8, + 0x47, 0x42, 0x2c, 0xe1, 0xf2, 0xd1, 0x17, 0x6b}}, + .y = {.byte = {0xf5, 0x51, 0xbf, 0x37, 0x68, 0x40, 0xb6, 0xcb, + 0xce, 0x5e, 0x31, 0x6b, 0x57, 0x33, 0xce, 0x2b, + 0x16, 0x9e, 0x0f, 0x7c, 0x4a, 0xeb, 0xe7, 0x8e, + 0x9b, 0x7f, 0x1a, 0xfe, 0xe2, 0x42, 0xe3, 0x4f}}, +}; + +const PKA_EccParam256 NISTP256_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam256 NISTP256_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam256 NISTP256_b = {.byte = {0x4b, 0x60, 0xd2, 0x27, 0x3e, 0x3c, 0xce, 0x3b, + 0xf6, 0xb0, 0x53, 0xcc, 0xb0, 0x06, 0x1d, 0x65, + 0xbc, 0x86, 0x98, 0x76, 0x55, 0xbd, 0xeb, 0xb3, + 0xe7, 0x93, 0x3a, 0xaa, 0xd8, 0x35, 0xc6, 0x5a}}; + +const PKA_EccParam256 NISTP256_order = {.byte = {0x51, 0x25, 0x63, 0xfc, 0xc2, 0xca, 0xb9, 0xf3, + 0x84, 0x9e, 0x17, 0xa7, 0xad, 0xfa, 0xe6, 0xbc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +//***************************************************************************** +// +// NIST P384 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP384_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint384 NISTP384_generator = { + .x = {.byte = {0xb7, 0x0a, 0x76, 0x72, 0x38, 0x5e, 0x54, 0x3a, + 0x6c, 0x29, 0x55, 0xbf, 0x5d, 0xf2, 0x02, 0x55, + 0x38, 0x2a, 0x54, 0x82, 0xe0, 0x41, 0xf7, 0x59, + 0x98, 0x9b, 0xa7, 0x8b, 0x62, 0x3b, 0x1d, 0x6e, + 0x74, 0xad, 0x20, 0xf3, 0x1e, 0xc7, 0xb1, 0x8e, + 0x37, 0x05, 0x8b, 0xbe, 0x22, 0xca, 0x87, 0xaa}}, + .y = {.byte = {0x5f, 0x0e, 0xea, 0x90, 0x7c, 0x1d, 0x43, 0x7a, + 0x9d, 0x81, 0x7e, 0x1d, 0xce, 0xb1, 0x60, 0x0a, + 0xc0, 0xb8, 0xf0, 0xb5, 0x13, 0x31, 0xda, 0xe9, + 0x7c, 0x14, 0x9a, 0x28, 0xbd, 0x1d, 0xf4, 0xf8, + 0x29, 0xdc, 0x92, 0x92, 0xbf, 0x98, 0x9e, 0x5d, + 0x6f, 0x2c, 0x26, 0x96, 0x4a, 0xde, 0x17, 0x36,}}, +}; + +const PKA_EccParam384 NISTP384_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam384 NISTP384_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam384 NISTP384_b = {.byte = {0xef, 0x2a, 0xec, 0xd3, 0xed, 0xc8, 0x85, 0x2a, + 0x9d, 0xd1, 0x2e, 0x8a, 0x8d, 0x39, 0x56, 0xc6, + 0x5a, 0x87, 0x13, 0x50, 0x8f, 0x08, 0x14, 0x03, + 0x12, 0x41, 0x81, 0xfe, 0x6e, 0x9c, 0x1d, 0x18, + 0x19, 0x2d, 0xf8, 0xe3, 0x6b, 0x05, 0x8e, 0x98, + 0xe4, 0xe7, 0x3e, 0xe2, 0xa7, 0x2f, 0x31, 0xb3}}; + +const PKA_EccParam384 NISTP384_order = {.byte = {0x73, 0x29, 0xc5, 0xcc, 0x6a, 0x19, 0xec, 0xec, + 0x7a, 0xa7, 0xb0, 0x48, 0xb2, 0x0d, 0x1a, 0x58, + 0xdf, 0x2d, 0x37, 0xf4, 0x81, 0x4d, 0x63, 0xc7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + + +//***************************************************************************** +// +// NIST P521 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP521_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint521 NISTP521_generator = { + .x = {.byte = {0x66, 0xbd, 0xe5, 0xc2, 0x31, 0x7e, 0x7e, 0xf9, + 0x9b, 0x42, 0x6a, 0x85, 0xc1, 0xb3, 0x48, 0x33, + 0xde, 0xa8, 0xff, 0xa2, 0x27, 0xc1, 0x1d, 0xfe, + 0x28, 0x59, 0xe7, 0xef, 0x77, 0x5e, 0x4b, 0xa1, + 0xba, 0x3d, 0x4d, 0x6b, 0x60, 0xaf, 0x28, 0xf8, + 0x21, 0xb5, 0x3f, 0x05, 0x39, 0x81, 0x64, 0x9c, + 0x42, 0xb4, 0x95, 0x23, 0x66, 0xcb, 0x3e, 0x9e, + 0xcd, 0xe9, 0x04, 0x04, 0xb7, 0x06, 0x8e, 0x85, + 0xc6, 0x00}}, + .y = {.byte = {0x50, 0x66, 0xd1, 0x9f, 0x76, 0x94, 0xbe, 0x88, + 0x40, 0xc2, 0x72, 0xa2, 0x86, 0x70, 0x3c, 0x35, + 0x61, 0x07, 0xad, 0x3f, 0x01, 0xb9, 0x50, 0xc5, + 0x40, 0x26, 0xf4, 0x5e, 0x99, 0x72, 0xee, 0x97, + 0x2c, 0x66, 0x3e, 0x27, 0x17, 0xbd, 0xaf, 0x17, + 0x68, 0x44, 0x9b, 0x57, 0x49, 0x44, 0xf5, 0x98, + 0xd9, 0x1b, 0x7d, 0x2c, 0xb4, 0x5f, 0x8a, 0x5c, + 0x04, 0xc0, 0x3b, 0x9a, 0x78, 0x6a, 0x29, 0x39, + 0x18, 0x01}}, +}; + +const PKA_EccParam521 NISTP521_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + +const PKA_EccParam521 NISTP521_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + +const PKA_EccParam521 NISTP521_b = {.byte = {0x00, 0x3f, 0x50, 0x6b, 0xd4, 0x1f, 0x45, 0xef, + 0xf1, 0x34, 0x2c, 0x3d, 0x88, 0xdf, 0x73, 0x35, + 0x07, 0xbf, 0xb1, 0x3b, 0xbd, 0xc0, 0x52, 0x16, + 0x7b, 0x93, 0x7e, 0xec, 0x51, 0x39, 0x19, 0x56, + 0xe1, 0x09, 0xf1, 0x8e, 0x91, 0x89, 0xb4, 0xb8, + 0xf3, 0x15, 0xb3, 0x99, 0x5b, 0x72, 0xda, 0xa2, + 0xee, 0x40, 0x85, 0xb6, 0xa0, 0x21, 0x9a, 0x92, + 0x1f, 0x9a, 0x1c, 0x8e, 0x61, 0xb9, 0x3e, 0x95, + 0x51, 0x00}}; + +const PKA_EccParam521 NISTP521_order = {.byte = {0x09, 0x64, 0x38, 0x91, 0x1e, 0xb7, 0x6f, 0xbb, + 0xae, 0x47, 0x9c, 0x89, 0xb8, 0xc9, 0xb5, 0x3b, + 0xd0, 0xa5, 0x09, 0xf7, 0x48, 0x01, 0xcc, 0x7f, + 0x6b, 0x96, 0x2f, 0xbf, 0x83, 0x87, 0x86, 0x51, + 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + + +//***************************************************************************** +// +// Brainpool P256r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP256R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 BrainpoolP256R1_generator = { + .x = {.byte = {0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A, + 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9, + 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C, + 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B}}, + .y = {.byte = {0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C, + 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2, + 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97, + 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54}}, +}; + +const PKA_EccParam256 BrainpoolP256R1_prime = {.byte = {0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20, + 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E, + 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, + 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; + +const PKA_EccParam256 BrainpoolP256R1_a = {.byte = {0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9, + 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB, + 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE, + 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D}}; + +const PKA_EccParam256 BrainpoolP256R1_b = {.byte = {0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B, + 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95, + 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3, + 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26,}}; + +const PKA_EccParam256 BrainpoolP256R1_order = {.byte = {0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90, + 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C, + 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, + 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; + +//***************************************************************************** +// +// Brainpool P384r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP384R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint384 BrainpoolP384R1_generator = { + .x = {.byte = {0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF, + 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8, + 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB, + 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88, + 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2, + 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D}}, + .y = {.byte = {0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42, + 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E, + 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1, + 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62, + 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C, + 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A}}, +}; + +const PKA_EccParam384 BrainpoolP384R1_prime = {.byte = {0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87, + 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC, + 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12, + 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, + 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, + 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; + +const PKA_EccParam384 BrainpoolP384R1_a = {.byte = {0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04, + 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A, + 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13, + 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2, + 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C, + 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B}}; + +const PKA_EccParam384 BrainpoolP384R1_b = {.byte = {0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A, + 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C, + 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E, + 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F, + 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B, + 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04}}; + +const PKA_EccParam384 BrainpoolP384R1_order = {.byte = {0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B, + 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF, + 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F, + 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, + 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, + 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; + +//***************************************************************************** +// +// Brainpool P512r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP512R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint512 BrainpoolP512R1_generator = { + .x = {.byte = {0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B, + 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C, + 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50, + 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF, + 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4, + 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85, + 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A, + 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81}}, + .y = {.byte = {0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78, + 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1, + 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B, + 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2, + 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0, + 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2, + 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0, + 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D}}, +}; + +const PKA_EccParam512 BrainpoolP512R1_prime = {.byte = {0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28, + 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28, + 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE, + 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D, + 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, + 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, + 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, + 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; + +const PKA_EccParam512 BrainpoolP512R1_a = {.byte = {0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7, + 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F, + 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A, + 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D, + 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8, + 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94, + 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2, + 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78}}; + +const PKA_EccParam512 BrainpoolP512R1_b = {.byte = {0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28, + 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98, + 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77, + 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B, + 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B, + 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8, + 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA, + 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D}}; + +const PKA_EccParam512 BrainpoolP512R1_order = {.byte = {0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5, + 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D, + 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41, + 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55, + 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, + 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, + 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, + 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; + +//***************************************************************************** +// +// Curve25519 constants in little endian format. byte[0] is the least +// significant byte and byte[Curve25519_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 Curve25519_generator = { + .x = {.byte = {0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}, + .y = {.byte = {0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29, + 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92, + 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0, + 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}}, +}; + +const PKA_EccParam256 Curve25519_prime = {.byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +const PKA_EccParam256 Curve25519_a = {.byte = {0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +const PKA_EccParam256 Curve25519_b = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +const PKA_EccParam256 Curve25519_order = {.byte = {0xb9, 0xdc, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, + 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +//***************************************************************************** +// +// Write a PKA parameter to the PKA module, set required registers, and add an offset. +// +//***************************************************************************** +static uint32_t PKAWritePkaParam(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) +{ + uint32_t i; + uint32_t *paramWordAlias = (uint32_t *)param; + // Take the floor of paramLength in 32-bit words + uint32_t paramLengthInWords = paramLength / sizeof(uint32_t); + + // Only copy data if it is specified. We may wish to simply allocate another buffer and get + // the required offset. + if (param) { + // Load the number in PKA RAM + for (i = 0; i < paramLengthInWords; i++) { + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = paramWordAlias[i]; + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. The extra zeros at the end should not matter, as the large + // number is little-endian and thus has no effect. + // We could have correctly calculated ceiling(paramLength / sizeof(uint32_t)) above. + // However, we would not have been able to zero-out the extra few most significant + // bytes of the most significant word. That would have resulted in doing maths operations + // on whatever follows param in RAM. + if (paramLength % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the param remainder + temp = paramWordAlias[i]; + + // Zero-out all bytes beyond the end of the param + for (j = paramLength % sizeof(uint32_t); j < sizeof(uint32_t); j++) { + ((uint8_t *)&temp)[j] = 0; + } + + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = temp; + + // Increment paramLengthInWords since we take the ceiling of length / sizeof(uint32_t) + paramLengthInWords++; + } + } + + // Update the A, B, C, or D pointer with the offset address of the PKA RAM location + // where the number will be stored. + switch (ptrRegOffset) { + case PKA_O_APTR: + HWREG(PKA_BASE + PKA_O_APTR) = paramOffset >> 2; + HWREG(PKA_BASE + PKA_O_ALENGTH) = paramLengthInWords; + break; + case PKA_O_BPTR: + HWREG(PKA_BASE + PKA_O_BPTR) = paramOffset >> 2; + HWREG(PKA_BASE + PKA_O_BLENGTH) = paramLengthInWords; + break; + case PKA_O_CPTR: + HWREG(PKA_BASE + PKA_O_CPTR) = paramOffset >> 2; + break; + case PKA_O_DPTR: + HWREG(PKA_BASE + PKA_O_DPTR) = paramOffset >> 2; + break; + } + + // Ensure 8-byte alignment of next parameter. + // Returns the offset for the next parameter. + return paramOffset + sizeof(uint32_t) * (paramLengthInWords + (paramLengthInWords % 2)); +} + +//***************************************************************************** +// +// Write a PKA parameter to the PKA module but return a larger offset. +// +//***************************************************************************** +static uint32_t PKAWritePkaParamExtraOffset(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) +{ + // Ensure 16-byte alignment. + return (sizeof(uint32_t) * 2) + PKAWritePkaParam(param, paramLength, paramOffset, ptrRegOffset); +} + +//***************************************************************************** +// +// Writes the result of a large number arithmetic operation to a provided buffer. +// +//***************************************************************************** +static uint32_t PKAGetBigNumResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + uint32_t mswOffset; + uint32_t lswOffset; + uint32_t lengthInWords; + uint32_t i; + uint32_t *resultWordAlias = (uint32_t *)resultBuf; + + // Check the arguments. + ASSERT(resultBuf); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Get the MSW register value. + mswOffset = HWREG(PKA_BASE + PKA_O_MSW); + + // If the result vector is zero, write back one zero byte so the caller does not need + // to handle a special error for the perhaps valid result of zero. + // They will only get the error status if they do not provide a buffer + if (mswOffset & PKA_MSW_RESULT_IS_ZERO_M) { + if (*resultLength){ + if(resultBuf){ + resultBuf[0] = 0; + } + + *resultLength = 1; + + return PKA_STATUS_SUCCESS; + } + else { + return PKA_STATUS_BUF_UNDERFLOW; + } + } + + // Get the length of the result + mswOffset = ((mswOffset & PKA_MSW_MSW_ADDRESS_M) + 1); + lswOffset = ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); + + if (mswOffset >= lswOffset) { + lengthInWords = mswOffset - lswOffset; + } + else { + return PKA_STATUS_RESULT_ADDRESS_INCORRECT; + } + + // Check if the provided buffer length is adequate to store the result data. + if (*resultLength < lengthInWords * sizeof(uint32_t)) { + return PKA_STATUS_BUF_UNDERFLOW; + } + + // Copy the resultant length. + *resultLength = lengthInWords * sizeof(uint32_t); + + + if (resultBuf) { + // Copy the result into the resultBuf. + for (i = 0; i < lengthInWords; i++) { + resultWordAlias[i]= HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + } + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Retrieve the result of a modulo operation or the remainder of a division. +// +//***************************************************************************** +static uint32_t PKAGetBigNumResultRemainder(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + uint32_t regMSWVal; + uint32_t lengthInWords; + uint32_t i; + uint32_t *resultWordAlias = (uint32_t *)resultBuf; + + // Check the arguments. + ASSERT(resultBuf); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Get the MSW register value. + regMSWVal = HWREG(PKA_BASE + PKA_O_DIVMSW); + + // If the result vector is zero, write back one zero byte so the caller does not need + // to handle a special error for the perhaps valid result of zero. + // They will only get the error status if they do not provide a buffer + if (regMSWVal & PKA_DIVMSW_RESULT_IS_ZERO_M) { + if (*resultLength){ + if(resultBuf){ + resultBuf[0] = 0; + } + + *resultLength = 1; + + return PKA_STATUS_SUCCESS; + } + else { + return PKA_STATUS_BUF_UNDERFLOW; + } + } + + // Get the length of the result + lengthInWords = ((regMSWVal & PKA_DIVMSW_MSW_ADDRESS_M) + 1) - ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); + + // Check if the provided buffer length is adequate to store the result data. + if (*resultLength < lengthInWords * sizeof(uint32_t)) { + return PKA_STATUS_BUF_UNDERFLOW; + } + + // Copy the resultant length. + *resultLength = lengthInWords * sizeof(uint32_t); + + if (resultBuf) { + // Copy the result into the resultBuf. + for (i = 0; i < lengthInWords; i++) { + resultWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + } + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Writes the resultant curve point of an ECC operation to the provided buffer. +// +//***************************************************************************** +static uint32_t PKAGetECCResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + uint32_t i = 0; + uint32_t *xWordAlias = (uint32_t *)curvePointX; + uint32_t *yWordAlias = (uint32_t *)curvePointY; + uint32_t lengthInWordsCeiling = 0; + + // Check for the arguments. + ASSERT(curvePointX); + ASSERT(curvePointY); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is completed. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + if (HWREG(PKA_BASE + PKA_O_SHIFT)) { + return PKA_STATUS_FAILURE; + } + + // Check to make sure that the result vector is not the point at infinity. + if (HWREG(PKA_BASE + PKA_O_MSW) & PKA_MSW_RESULT_IS_ZERO) { + return PKA_STATUS_POINT_AT_INFINITY; + } + + if (curvePointX != NULL) { + // Copy the x co-ordinate value of the result from vector D into + // the curvePoint. + for (i = 0; i < (length / sizeof(uint32_t)); i++) { + xWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. + if (length % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the coordinate remainder + temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + + // Write all remaining bytes to the coordinate + for (j = 0; j < length % sizeof(uint32_t); j++) { + curvePointX[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j]; + } + + } + } + + lengthInWordsCeiling = (length % sizeof(uint32_t)) ? length / sizeof(uint32_t) + 1 : length / sizeof(uint32_t); + + resultPKAMemAddr += sizeof(uint32_t) * (2 + lengthInWordsCeiling + (lengthInWordsCeiling % 2)); + + if (curvePointY != NULL) { + // Copy the y co-ordinate value of the result from vector D into + // the curvePoint. + for (i = 0; i < (length / sizeof(uint32_t)); i++) { + yWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. + if (length % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the coordinate remainder + temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + + // Write all remaining bytes to the coordinate + for (j = 0; j < length % sizeof(uint32_t); j++) { + curvePointY[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j]; + } + } + } + + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Provides the PKA operation status. +// +//***************************************************************************** +uint32_t PKAGetOpsStatus(void) +{ + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN_M) { + return PKA_STATUS_OPERATION_BUSY; + } + else { + return PKA_STATUS_OPERATION_RDY; + } +} + +//***************************************************************************** +// +// Check if an array consists only of zeros. +// +//***************************************************************************** +bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength) +{ + uint32_t i; + uint8_t arrayBits = 0; + + // We could speed things up by comparing word-wise rather than byte-wise. + // However, this extra overhead is inconsequential compared to running an + // actual PKA operation. Especially ECC operations. + for (i = 0; i < arrayLength; i++) { + arrayBits |= array[i]; + } + + if (arrayBits) { + return false; + } + else { + return true; + } + +} + +//***************************************************************************** +// +// Fill an array with zeros +// +//***************************************************************************** +void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength) +{ + uint32_t i; + // Take the floor of paramLength in 32-bit words + uint32_t arrayLengthInWords = arrayLength / sizeof(uint32_t); + + // Zero-out the array word-wise until i >= arrayLength + for (i = 0; i < arrayLengthInWords * sizeof(uint32_t); i += 4) { + HWREG(array + i) = 0; + } + + // If i != arrayLength, there are some remaining bytes to zero-out + if (arrayLength % sizeof(uint32_t)) { + // Subtract 4 from i, since i has already overshot the array + for (i -= 4; i < arrayLength; i++) { + HWREGB(array + i * sizeof(uint32_t)); + } + } +} + +//***************************************************************************** +// +// Start the big number modulus operation. +// +//***************************************************************************** +uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(modulus, modulusLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Start the PKCP modulo operation by setting the PKA Function register. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MODULO); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number modulus operation. +// +//***************************************************************************** +uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResultRemainder(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideStart(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(dividend); + ASSERT(divisor); + ASSERT(resultQuotientMemAddr); + ASSERT(resultRemainderMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(dividend, dividendLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(divisor, divisorLength, offset, PKA_O_BPTR); + + // Copy the remainder result vector address location. + if (resultRemainderMemAddr) { + *resultRemainderMemAddr = PKA_RAM_BASE + offset; + } + + // The remainder cannot ever be larger than the divisor. It should fit inside + // a buffer of that size. + offset = PKAWritePkaParamExtraOffset(0, divisorLength, offset, PKA_O_CPTR); + + // Copy the remainder result vector address location. + if (resultQuotientMemAddr) { + *resultQuotientMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the quotient location in PKA RAM + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Start the PKCP modulo operation by setting the PKA Function register. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_DIVIDE); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the quotient of the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) +{ + return PKAGetBigNumResult(resultBuf, length, resultQuotientMemAddr); +} + +//***************************************************************************** +// +// Get the remainder of the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) +{ + return PKAGetBigNumResultRemainder(resultBuf, length, resultQuotientMemAddr); +} + + +//***************************************************************************** +// +// Start the comparison of two big numbers. +// +//***************************************************************************** +uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum1); + ASSERT(bigNum2); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum1, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(bigNum2, length, offset, PKA_O_BPTR); + + // Set the PKA Function register for the Compare operation + // and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_COMPARE); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the comparison operation of two big numbers. +// +//***************************************************************************** +uint32_t PKABigNumCmpGetResult(void) +{ + uint32_t status; + + // verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Check the COMPARE register. + switch(HWREG(PKA_BASE + PKA_O_COMPARE)) { + case PKA_COMPARE_A_EQUALS_B: + status = PKA_STATUS_EQUAL; + break; + + case PKA_COMPARE_A_GREATER_THAN_B: + status = PKA_STATUS_A_GREATER_THAN_B; + break; + + case PKA_COMPARE_A_LESS_THAN_B: + status = PKA_STATUS_A_LESS_THAN_B; + break; + + default: + status = PKA_STATUS_FAILURE; + break; + } + + return status; +} + +//***************************************************************************** +// +// Start the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(modulus, modulusLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // set the PKA function to InvMod operation and the start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0x0000F000; + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResult(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number multiplication. +// +//***************************************************************************** +uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(multiplicand); + ASSERT(multiplier); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(multiplicand, multiplicandLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(multiplier, multiplierLength, offset, PKA_O_BPTR); + + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the PKA function to the multiplication and start it. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MULTIPLY); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the results of the big number multiplication. +// +//***************************************************************************** +uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the addition of two big number. +// +//***************************************************************************** +uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for arguments. + ASSERT(bigNum1); + ASSERT(bigNum2); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum1, bigNum1Length, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(bigNum2, bigNum2Length, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the function for the add operation and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_ADD); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the addition operation on two big number. +// +//***************************************************************************** +uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the addition of two big number. +// +//***************************************************************************** +uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for arguments. + ASSERT(minuend); + ASSERT(subtrahend); + ASSERT(resultPKAMemAddr); + + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(minuend, minuendLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(subtrahend, subtrahendLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the function for the add operation and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_SUBTRACT); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the addition operation on two big number. +// +//***************************************************************************** +uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + + +//***************************************************************************** +// +// Start ECC Multiplication. +// +//***************************************************************************** +uint32_t PKAEccMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(scalar); + ASSERT(curvePointX); + ASSERT(curvePointY); + ASSERT(prime); + ASSERT(a); + ASSERT(b); + ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); + ASSERT(resultPKAMemAddr); + + // Make sure no PKA operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + offset = PKAWritePkaParamExtraOffset(b, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); + offset = PKAWritePkaParamExtraOffset(curvePointY, length, offset, PKA_NO_POINTER_REG); + + // Update the result location. + // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity + if (resultPKAMemAddr) { + *resultPKAMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA function to ECC-MULT and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x05 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Start ECC Montgomery Multiplication. +// +//***************************************************************************** +uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(scalar); + ASSERT(curvePointX); + ASSERT(prime); + ASSERT(a); + ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); + ASSERT(resultPKAMemAddr); + + // Make sure no PKA operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); + + // Update the result location. + // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity + if (resultPKAMemAddr) { + *resultPKAMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA function to Montgomery ECC-MULT and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x02 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Get the result of ECC Multiplication +// +//***************************************************************************** +uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); +} + +//***************************************************************************** +// +// Start the ECC Addition. +// +//***************************************************************************** +uint32_t PKAEccAddStart(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(curvePoint1X); + ASSERT(curvePoint1Y); + ASSERT(curvePoint2X); + ASSERT(curvePoint2Y); + ASSERT(prime); + ASSERT(a); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParamExtraOffset(curvePoint1X, length, offset, PKA_O_APTR); + offset = PKAWritePkaParamExtraOffset(curvePoint1Y, length, offset, PKA_NO_POINTER_REG); + + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePoint2X, length, offset, PKA_O_CPTR); + offset = PKAWritePkaParamExtraOffset(curvePoint2Y, length, offset, PKA_NO_POINTER_REG); + + // Copy the result vector location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA Function to ECC-ADD and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION ) = PKA_FUNCTION_RUN_M | (0x03 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the ECC Addition +// +//***************************************************************************** +uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); +} + +//***************************************************************************** +// +// Verify a public key against the supplied elliptic curve equation +// +//***************************************************************************** +uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length) +{ + uint32_t pkaResult; + uint32_t resultAddress; + uint32_t resultLength; + uint8_t *scratchBuffer = (uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2); + uint8_t *scratchBuffer2 = scratchBuffer + 512; + + + // Verify X in range [0, prime - 1] + PKABigNumCmpStart(curvePointX, + prime, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return PKA_STATUS_X_LARGER_THAN_PRIME; + } + + // Verify Y in range [0, prime - 1] + PKABigNumCmpStart(curvePointY, + prime, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return PKA_STATUS_Y_LARGER_THAN_PRIME; + } + + // Verify point on curve + // Short-Weierstrass equation: Y ^ 2 = X ^3 + a * X + b mod P + // Reduced: Y ^ 2 = X * (X ^ 2 + a) + b + + // tmp = X ^ 2 + PKABigNumMultiplyStart(curvePointX, length, curvePointX, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp += a + PKABigNumAddStart(scratchBuffer, resultLength, a, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp *= x + PKABigNumMultiplyStart(scratchBuffer, resultLength, curvePointX, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp += b + PKABigNumAddStart(scratchBuffer, resultLength, b, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + + // tmp2 = tmp % prime to ensure we have no fraction in the division. + // The number will only shrink from here on out. + PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + // If the result is not a multiple of the word-length, the PKA HW will round up + // because it deals in words only. That means that using 'length' directly + // would cause and underflow, since length refers to the actual length in bytes of + // the curve parameters while the PKA HW reports that rounded up to the next + // word boundary. + // Use 200 as the resultLength instead since we are copying to the scratch buffer + // anyway. + // Practically, this only happens with curves such as NIST-P521 that are not word + // multiples. + resultLength = 200; + pkaResult = PKABigNumModGetResult(scratchBuffer2, resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp = y^2 + PKABigNumMultiplyStart(curvePointY, length, curvePointY, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp %= prime + PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + // If the result is not a multiple of the word-length, the PKA HW will round up + // because it deals in words only. That means that using 'length' directly + // would cause and underflow, since length refers to the actual length in bytes of + // the curve parameters while the PKA HW reports that rounded up to the next + // word boundary. + // Use 200 as the resultLength instead since we are copying to the scratch buffer + // anyway. + // Practically, this only happens with curves such as NIST-P521 that are not word + // multiples. + resultLength = 200; + pkaResult = PKABigNumModGetResult(scratchBuffer, resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp ?= tmp2 + PKABigNumCmpStart(scratchBuffer, + scratchBuffer2, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_EQUAL) { + return PKA_STATUS_POINT_NOT_ON_CURVE; + } + else { + return PKA_STATUS_SUCCESS; + } +} + + +static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash); + + +void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) { + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + if (channel0Addr) { + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags) { + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT); + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqFlags; + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + return irqTrigger; +} + +uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength) { + ASSERT(message); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + + return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, initialMessageLength, initialMessageLength, hashAlgorithm, true, false); +} + +uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength) { + ASSERT(message); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, 0, intermediateMessageLength, hashAlgorithm, false, false); +} + +uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm) { + ASSERT(message); + ASSERT(totalMsgLength); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + ASSERT(resultDigest); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, resultDigest, intermediateDigest, totalMsgLength, messageLength, hashAlgorithm, false, true); +} + +uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm) { + ASSERT(message); + ASSERT(totalMsgLength); + ASSERT(resultDigest); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, resultDigest, 0, totalMsgLength, totalMsgLength, hashAlgorithm, true, true); +} + +static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash) { + uint8_t digestLength = 0; + uint32_t dmaAlgorithmSelect = 0; + + SHA2ClearDigestAvailableFlag(); + + switch (hashAlgorithm) { + case SHA2_MODE_SELECT_SHA224: + digestLength = SHA2_SHA224_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; + break; + case SHA2_MODE_SELECT_SHA256: + digestLength = SHA2_SHA256_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; + break; + case SHA2_MODE_SELECT_SHA384: + digestLength = SHA2_SHA384_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; + break; + case SHA2_MODE_SELECT_SHA512: + digestLength = SHA2_SHA512_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; + break; + default: + return SHA2_INVALID_ALGORITHM; + } + + if (initialHash && finalHash) { + // The empty string is a perfectly valid message. It obviously has a length of 0. The DMA cannot + // handle running with a transfer length of 0. This workaround depends on the hash engine adding the + // trailing 1 bit and 0-padding bits after the DMAtransfer is complete and not in the DMA itself. + // totalMsgLength is purposefully not altered as it is appended to the end of the message during finalization + // and determines how many padding-bytes are added. + // Altering totalMsgLength would alter the final hash digest. + // Because totalMsgLength specifies that the message is of length 0, the content of the byte loaded + // through the DMA is irrelevant. It is overwritten internally in the hash engine. + messageLength = messageLength ? messageLength : 1; + } + + // Setting the incorrect number of bits here leads to the calculation of the correct result + // but a failure to read them out. + // The tag bit is set to read out the digest via DMA rather than through the slave interface. + SHA2SelectAlgorithm(dmaAlgorithmSelect | (resultDigest ? SHA2_ALGSEL_TAG : 0)); + SHA2IntClear(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + SHA2IntEnable(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + + HWREG(CRYPTO_BASE + CRYPTO_O_HASHMODE) = hashAlgorithm | (initialHash ? CRYPTO_HASHMODE_NEW_HASH_M : 0); + + // Only load the intermediate digest if requested. + if (intermediateDigest && !initialHash) { + SHA2SetDigest(intermediateDigest, digestLength); + } + + // If this is the final hash, finalization is required. This means appending a 1 bit, padding the message until this section + // is 448 bytes long, and adding the 64 bit total length of the message in bits. Thankfully, this is all done in hardware. + if (finalHash) { + // This specific length must be specified in bits not bytes. + SHA2SetMessageLength(totalMsgLength * 8); + HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M; + + } + + // The cast is fine in this case. SHA2StartDMAOperation channel one serves as input and no one does + // hash operations in-place. + SHA2StartDMAOperation((uint8_t *)message, messageLength, resultDigest, digestLength); + + return SHA2_SUCCESS; +} diff --git a/third_party/ti/devices/cc13x2_cc26x2/rom/driverlib.elf b/third_party/ti/devices/cc13x2_cc26x2/rom/driverlib.elf index 993929ecd6f410c1c4b8988ad309871860f91542..9d09f2a81df3a69550850f8a5b9ec2ce5e9a9d69 100644 GIT binary patch literal 372940 zcmeFadwf&H);B(TCuw%u(C%Kq0&Ur83#3q>t#~XKWhW_VQVJ~>6_umuMNErGz#DoH zQZ8BrwJ0jyj>XFnFGt%-6+HAb<)VO>leVCsqEQQl)JsYO+4Pq8J3B2DJwDHQ-rw_n ze*aiLD>JiZ&6+i9&#akQGkddUW}b;*7&7q35*?wbn&E_>{&y8w1YikKO(p{HIx>t5 zC5T4R{04#Wjexy_V1Um+IFLuv1M%UZgx7ye$c6&Kj|GgMOZd_A2|p9?!~()A<`KRL z_(+5k0J8vh0bT{&EITV%RczZw4vacY%9WcPB8u5LA9|1lqK1K>MA2jDq?Dw*)N0?Gl$0kcyH|1@BOj_{9- zM;}Zh{KqMT|7jxO6DASv7_biT4B#waZaVk__5;)zgpUFY2aE??1;_`K0{#Mc z1n?rD2CyIS1)vS!2TaK%{CvQRfaJ>w|0aO8^CN_x0u+-8KMk-9@EVO@LHH$r7XkHv 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  • CC13x0
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    • [RF_PATCH]: GHS Added new CPE/MCE patch set for general high-speed GenFSK ("ghs" patch). CPE patch is identical to GenFSK.
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    • [RF_PATCH]: GHS Added new CPE/MCE patch set for general high-speed GenFSK ("ghs" patch). CPE patch is identical to GenFSK.
    • [RF_PATCH]: BREPEAT Added new CPE/MCE patch set for using bit-repeat mode ("brepeat" patch), for symbol rate. CPE patch is identical to GenFSK.
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    • [RF_API] Headers: In CPE commands CMD_PROP_RADIO_SETUP and CMD_PROP_RADIO_DIV_SETUP, the struct bit fields symbolRate.bPdifDecim and symbolRate.pdifDecim have been joined into one field, symbolRate.decimMode, with unchanged functionality. This change is to have same API for CC13x0 as exists for CC13x2 and CC26x2 devices. This field is needed used when using "brepeat" radio patch.
      • +
    • [RF_API] Headers: In CPE commands CMD_PROP_RADIO_SETUP and CMD_PROP_RADIO_DIV_SETUP, the struct bit fields symbolRate.bPdifDecim and symbolRate.pdifDecim have been joined into one field, symbolRate.decimMode, with unchanged functionality. This change is to have same API for CC13x0 as exists for CC13x2 and CC26x2 devices. This field is needed used when using "brepeat" radio patch.
  • CC13x2_CC26x2
      @@ -173,14 +1558,12 @@
      • CC26x0
          • -
        • [RF_PATCH] General: CMD_SCH_IMM could cause loss of commands.
          • +
        • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
      • CC26x0R2
        • [RF_API] General: GPO control not functional. (The PA_EN status signal does not go low).
        • -
        -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
      @@ -207,13 +1590,11 @@

      Known issues

      • CC26x0
        • -
      • CC26x0R2 + CC26x0R2
        • [RF_API] General: GPO control not functional.
          • -
        • [RF_PATCH] General: CMD_SCH_IMM could cause loss of commands.
          • +
        • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
        -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
      @@ -257,13 +1638,11 @@

      Known issues

      • CC26x0
        • -
      • CC26x0R2 + CC26x0R2
        • [RF_API] General: GPO control not functional.
          • -
        • [RF_PATCH] General: CMD_SCH_IMM could cause loss of commands.
          • +
        • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
        -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
      @@ -316,13 +1695,11 @@

      Known issues

      • CC26x0
        • -
      • CC26x0R2 + CC26x0R2
        • [RF_API] General: GPO control not functional.
          • -
        • [RF_PATCH] General: CMD_SCH_IMM could cause loss of commands.
          • +
        • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
        -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
      @@ -353,13 +1730,11 @@

      Known issues

      • CC26x0
        • -
      • CC26x0R2 + CC26x0R2
        • [RF_API] General: GPO control not functional.
          • -
        • [RF_PATCH] General: CMD_SCH_IMM could cause loss of commands.
          • +
        • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
        -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
      @@ -396,13 +1771,11 @@

      Known issues

      • CC26x0
        • -
      • CC26x0R2 + CC26x0R2
        • [RF_API] General: GPO control not functional.
          • -
        • [RF_PATCH] General: CMD_SCH_IMM could cause loss of commands.
          • +
        • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
        -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
      @@ -439,13 +1812,11 @@

      Known issues

      • CC26x0
        • -
      • CC26x0R2 + CC26x0R2
        • [RF_API] General: GPO control not functional.
          • -
        • [RF_PATCH] General: CMD_SCH_IMM could cause loss of commands.
          • +
        • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
        -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
      @@ -484,12 +1855,10 @@

      Known issues

      • CC26x0
        • -
      • CC26x0R2 + CC26x0R2
          -
        • [RF_PATCH] General: CMD_SCH_IMM could cause loss of commands.
          • +
        • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • -
        -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
      @@ -559,19 +1928,17 @@
  • CC13x0
      -
    • [RF_PATCH] General: CMD_SCH_IMM could cause loss of commands. Fixed with CPE patch.
      • +
    • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands. Fixed with CPE patch.

    • Known issues

    • CC26x0
      • -
    • CC26x0R2 + CC26x0R2
        -
      • [RF_PATCH] General: CMD_SCH_IMM could cause loss of commands.
        • +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
      • -
      -
    • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
    @@ -601,7 +1968,7 @@

    Bug fixes

    • CC26x0
      • -
    • CC26x0R2 + CC26x0R2
      • [RF_API] Updated comment of txPower field to better describe function.
      • @@ -610,7 +1977,6 @@

      Known issues

      • None
        • -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
      @@ -652,7 +2018,6 @@

      Known issues

      • None
        • -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
      @@ -713,7 +2078,6 @@

      Known issues

      • None
        • -
      • For an updated list of known issues (including issues found after the release), see CC13xx_CC26xx_driverlib on the Texas Instruments wiki.
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zW+aqkG;A%W{|#;WNSOVn>;=6?>ik;I!j#%`>$)Rtpl+okqdn_c{cmW{N6uX>UqODP zHfWLfDK+JI>WFK~lw>qzy@o!#QLK5R=-OeBXZn7DJaeq_mu>ySlB`*hSnVI%8u0Pm zNIlzP;lNhb>kS3jz+jATQjK|iLJ46k>h10eFg!iuKXoq-!alq$#MS`c=2#@;g?|C; zG85`1{#-C-#N)JaL{bXB{AVhlhxY0iZ!#)!JPKCgtdY>I3gvhX5n$5>-cw*76~0SF z{++{SIMzfD{qbNL;t{DJ7jM|7%%A7+z0vjLGP5e~w zPumW=ic&j_=yr@Xk{!}n`Kb7)3^Xw#yC;xF^-;P{xa{6Ro$e!N6Y`_%#=z>BRA0Rn zzccWlEm22Ty6k@L#}9tQDTMeayPJUOm^5G7TgUFyDo*LX;Ii8|V>;XSsM6YT-0!mc z^Y>@4bKsjveN>1?Adqd3tJ;4)gB@H>z7ycL7)Dfn_4vOZ|Fvpo$H5Ww!IL4B9~IwI xVDy2?=g%LVsrm_*srq;tq{5J5#m8nc@+G7`O80XJ^z&Y`ZYKK=WrS~K_g{~<8C?JX diff --git a/third_party/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c b/third_party/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c index cee4b931e..00c0c9c56 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c +++ b/third_party/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c @@ -1,12 +1,12 @@ /****************************************************************************** * Filename: ccfg.c -* Revised: $Date: 2017-11-02 11:36:28 +0100 (to, 02 nov 2017) $ +* Revised: $Date: 2017-11-02 11:36:28 +0100 (Thu, 02 Nov 2017) $ * Revision: $Revision: 18030 $ * * Description: Customer Configuration for: -* CC13x2, CC13x4, CC26x2, CC26x4 device family (HW rev 1). +* CC13x2, CC13x4, CC26x2, CC26x4 device family (HW rev 2). * -* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ * * * Redistribution and use in source and binary forms, with or without @@ -118,7 +118,7 @@ #endif #ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK -#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x4 // Peak current +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 // Peak current #endif //##################################### diff --git a/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_ccs.c b/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_ccs.c index 3c4ee50ea..f81ec967d 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_ccs.c +++ b/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_ccs.c @@ -1,6 +1,6 @@ /****************************************************************************** * Filename: startup_ccs.c -* Revised: $Date: 2017-02-03 19:16:24 +0100 (fr, 03 feb 2017) $ +* Revised: $Date: 2017-02-03 19:16:24 +0100 (Fri, 03 Feb 2017) $ * Revision: $Revision: 17634 $ * * Description: Startup code for CC26x2 device family for use with CCS. diff --git a/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_gcc.c b/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_gcc.c index 3d02145fe..6851e3148 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_gcc.c +++ b/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_gcc.c @@ -1,6 +1,6 @@ /****************************************************************************** * Filename: startup_gcc.c -* Revised: $Date: 2017-06-01 16:01:48 +0200 (to, 01 jun 2017) $ +* Revised: $Date: 2017-06-01 16:01:48 +0200 (Thu, 01 Jun 2017) $ * Revision: $Revision: 17804 $ * * Description: Startup code for CC26x2 device family for use with GCC. diff --git a/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_iar.c b/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_iar.c index 491849d1d..b5680d505 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_iar.c +++ b/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_iar.c @@ -1,6 +1,6 @@ /****************************************************************************** * Filename: startup_iar.c -* Revised: $Date: 2017-02-03 19:16:24 +0100 (fr, 03 feb 2017) $ +* Revised: $Date: 2017-02-03 19:16:24 +0100 (Fri, 03 Feb 2017) $ * Revision: $Revision: 17634 $ * * Description: Startup code for CC26x2 device family for use with IAR. diff --git a/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_keil.s b/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_keil.s index cce982846..0a4f81416 100644 --- a/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_keil.s +++ b/third_party/ti/devices/cc13x2_cc26x2/startup_files/startup_keil.s @@ -1,6 +1,6 @@ ; /****************************************************************************** ; * Filename: startup_keil.c -; * Revised: $Date: 2016-09-13 11:33:40 +0200 (ti, 13 sep 2016) $ +; * Revised: $Date: 2016-09-13 11:33:40 +0200 (Tue, 13 Sep 2016) $ ; * Revision: $Revision: 17320 $ ; * ; * Description: Startup code for CC26xx device family for use with KEIL. diff --git a/third_party/ti/release_notes_driverlib_cc13xx_cc26xx.html b/third_party/ti/release_notes_driverlib_cc13xx_cc26xx.html index e984d58fd..07ae5e637 100644 --- a/third_party/ti/release_notes_driverlib_cc13xx_cc26xx.html +++ b/third_party/ti/release_notes_driverlib_cc13xx_cc26xx.html @@ -78,6 +78,1393 @@ +

    +

    driverlib_cc13xx_cc26xx_3_05_06_18894

    +
    + Release date: Feb 27, 2019
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2
      • +
        +
      • [RF_PATCH] CC13X2P/R, CC26X2: CPE patches had equal NWORD definitions, which this update fixes.
        • +
      • [RF_PATCH] CC13X2P/R, CC26X2: Updated BLE patches due to BLE tester failure.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_PATCH] CC2640R2F: Updated BLE patches due to BLE tester failure.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_05_05_18873

    +
    + Release date: Feb 15, 2019
    + +

    New features

    +
      +
    • CC13x2_CC26x2 +
        +
      • [DRV_API] OSC: New API functions called OSC_IsHPOSCEnabledWithHfDerivedLfClock() and OSC_HPOSCRtcCompensate()have been added for support of future device variant with HPOSC.
        • +
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • None
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_05_04_18846

    +
    + Release date: Jan 31, 2019
    + +

    New features

    +
      +
    • CC26x0R2
      • + CC26x0
      + CC13x0
      +
        +
      • [DRV_API] AES: New API for AES crypto functions has been added by the aes.c and aes.h files.
        • +
      +
    • CC13x2_CC26x2 +
        +
      • [RF_PATCH] CC13X2R, CC13X2P, CC26X2: Multiprotocol patch including RTLS, implementing AoA/AoD for Bluetooth 5.1 and time-of-flight.
        • +
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • CC26x0R2
      • +
        +
      • [RF_PATCH] CC2640R2: Bug fix for Bluetooth CTE generic RX.
        • +
      • [RF_PATCH] CC2640R2: Updated time-of-flight patches (MCE, RFE and CPE) for CC2640R2, including new commandNo, fix for double buffer and removal of STIM compensation.
        • +
      +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_05_03_18798

    +
    + Release date: Dec 06, 2018
    + +

    New features

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_API] I2S: New static inline API function called I2SWclkCounterReset() has been added.
        • +
      • +
    • CC13x2_CC26x2
      • +
        +
      • [DRV_SRC] OSC: Support for future device variant with HPOSC has been added.
        • +
      +
    + +

    Improvements

    +
      +
    • CC13x2_CC26x2
      • +
        +
      • [DRV_SRC] CCFG: Default IPEAK setting changed to 0 for optimized power consumption.
        • +
      +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2
      • +
        +
      • [DRV_SRC]: Corrected handling of VDDR boost mode. Boost mode can be enabled in CCFG.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_PATCH] CC2640R2F: Bugfix regarding BLE CTE GRX CPE patch, there was a missing include in the Makefile which caused the patch not to function.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_05_02_18760

    +
    + Release date: Nov 02, 2018
    + +

    New features

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_API] I2S: New API has been added. Legacy API is marked as deprecated.
        • +
      • +
    • CC13x2_CC26x2
      • +
        +
      • [RF_PATCH] CC13X2, CC26X2: Release of IQ-dump patch.
        • +
      • [RF_PATCH] CC26X2: API definitions needed for HPOSC support.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_PATCH] CC2640R2F: Updated time of flight (ToF) patches. Includes bug and stability fixes, STIM and correlation compensation integration and features which reduce RAM usage for the system. UserFunAddr = 0x21000914 for this CPE patch.
        • +
      • [RF_PATCH] CC2640R2F: Release of patches for AoA support using constant tone extension (CTE).
        • +
      • +
    + +

    Improvements

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_DOC] General: General improvement of the documentation.
        • +
      • +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2
      • +
        +
      • [DRV_API]: The rom.h file contains defines with wrong AUXIOn indexes.
        • +
      • [RF_PATCH] CC1352P, CC1352R, CC2652R: Bug fix regarding RSSI value read-out for 1 and 2 Mbps BLE and Multi.
        • +
      +
    • CC13x0 +
        +
      • [RF_PATCH] CC1350, CC1310: A bug was found in the release script, which resulted in the patches not being cleaned properly before export. This caused the CS bug fix to not be up to date. This update includes the latest fixes in the CC13x0 related to the CS fix in prop CPE patches.
        • +
      • [RF_PATCH] CC1350, CC1310: Updated wireless M-bus CT mode MCE patch. This patch includes two bug-fixes.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_05_01_18740

    +
    + Release date: Oct 11, 2018
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • CC13x2_CC26x2
      • +
        +
      • [DRV_DOC] General: General improvement of the documentation.
        • +
      +
    + +

    Bug fixes

    +
      +
    • CC13x0 +
        +
      • [RF_PATCH] CC1350, CC1310: Bug fix in WMBUS CT-mode MCE, where if the 1st bit was 1, an error floor was present. This patch includes a fix to that bug.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_05_00_18715

    +
    + Release date: Sep 24, 2018
    + +

    New features

    +
      +
    • CC13x2_CC26x2 +
        +
      • [DRV_SRC] General: Driverlib does no longer support early revisions of the CC13x2/CC26x2 devices forcing the driverlib folder "cc13x2_cc26x2_v1" to have been removed.
        • +
      • [DRV_SRC] General: Driverlib folder "cc13x2_cc26x2_v2" for supported CC13x2/CC26x2 devices has been renamed to "cc13x2_cc26x2".
        • +
      • [DRV_SRC] rom_crypto: Added access to ECC crypto functions in ROM by the new rom_crypto driverlib module. These functions can only to be used in applications not containing the BLE SW stack. Note that if these functions are called by the application they will make use of the SRAM address range of 0x2000012C - 0x200001AB as a scratch pad area. Calling any of these functions will require the linker file to be updated with the specified SRAM area.
        • +
      • [RF_PATCH] CC13X2, CC26X2: Release of IQ-dump patch.
        • +
      • +
    + +

    Improvements

    +
      +
    • CC13x2_CC26x2
      • +
        +
      • [DRV_DOC] General: General improvement of the documentation.
        • +
      +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2 +
        +
      • [RF_PATCH] CC13X2, CC26X2: Bug fix regarding the generation of the .bin-files used for CPE patches.
        • +
      • +
    • CC13x0 +
        +
      • [RF_PATCH] CC13X0: (Re-)relase of bitrepetition RFE patch, used to be genfsk patch but for consistency it has now been copied and renamed to brepeat. No changes in patch has been made except for the name.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_16_18623

    +
    + Release date: Aug 17, 2018
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      +
        +
      • [RF_PATCH] CC13X2, CC26X2: Repeat mode with Sniff Command; a flag was not cleared in CPE when running which is solved with this patch.
        • +
      • [RF_PATCH] CC13X2, CC26X2: Patch that fixes the case where RX end time may be delayed in sniff mode.
        • +
      +
    • CC13x0 +
        +
      • [RF_PATCH] CC13X0: Repeat mode with Sniff Command; a flag was not cleared in CPE when running which is solved with this patch.
        • +
      • [RF_PATCH] CC13X0: Patch that fixes the case where RX end time may be delayed in sniff mode.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_15_18598

    +
    + Release date: Aug 09, 2018
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      +
        +
      • [DRV_SRC] RFC: Re-distribute the functionality between driverlib and RF driver required by the High Gain PA configuration.
        • +
      +
    + +

    Bug fixes

    +
      +
    • None
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_14_18578

    +
    + Release date: Aug 01, 2018
    + +

    New features

    +
      +
    • CC13x2_CC26x2_v2
      • +
        +
      • [RF_API] CC1312R, CC1352R, CC1352P, CC2642R, CC2652R: Updated API header files to extend common API with new commands to set TX power with possibility to switch between PAs (only applicable to CC1352P): A new command "CMD_CHANGE_PA" and a new CPE interrupt line definition "IRQ_PA_CHANGED" has been added, and new extended variants for each of the existing radio setup command has been introduced ("CMD_RADIO_SETUP_PA", "CMD_BLE5_RADIO_SETUP_PA", "CMD_PROP_RADIO_SETUP_PA", "CMD_PROP_RADIO_DIV_SETUP_PA") with additional PA switching fields -- these additional fields will be used by RF driver when switching PA, not radio CPU. Separately, a new common CPE command "CMD_SET_CMD_START_IRQ" has been added that can be used by RF driver to get interrupt notification when a background/foreground radioOp command starts (e.g. for IEEE 802.15.4 protocols).
        • +
      +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      +
        +
      • [DRV_SRC] RFC: Expand the RFCOverrideUpdate to handle the front-end specific overrides.
        • +
      • [DRV_SRC] Crypto PKA: Added function to erase PKA RAM.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_PATCH] CC2640R2F: Updated CPE patch used for time-of-flight measurements ("tof"). This includes the passive node functionality.
        • +
      • +
    + +

    Improvements

    +
      +
    • CC13x2_CC26x2_v2
      • +
        +
      • [DRV_DOC] General: General improvement of the documentation.
        • +
      +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      +
        +
      • [DRV_SRC] Setup and OSC: DCDC without clock loss detection while switching to XOSC_HF.
        • +
      +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_13_18486

    +
    + Release date: May 30, 2018
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • CC26x0R2 +
        +
      • [RF_PATCH] CC2640R2F: Updated MCE patch used for time-of-flight measurements ("tof"). This corrects a build problem with the previous patch that caused it to not work as intended.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_12_18461

    +
    + Release date: May 15, 2018
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • CC26x0R2 +
        +
      • [RF_PATCH] CC2640R2F: Updated CPE and RFE patches used for time-of-flight measurements ("tof") to estimate RF link distance. The new CPE patch has some simplifications, and consequently a smaller patch code size, before first public release. The RFE patch has been updated to remove unnecessary debug information.
        • +
      • +
    + +

    Bug fixes

    +
      +
    • None
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_11_18442

    +
    + Release date: May 08, 2018
    + +

    New features

    +
      +
    • CC13x2_CC26x2_v1
      • +
        +
      • [RF_API] General: Updated API header files to extend common API with new command to set TX power with possibility to switch between PAs. The command is named "CMD_CHANGE_PA". Also, a new extended variants for each of the existing radio setup command has been introduced ("CMD_RADIO_SETUP_PA", "CMD_BLE5_RADIO_SETUP_PA", "CMD_PROP_RADIO_SETUP_PA", "CMD_PROP_RADIO_DIV_SETUP_PA") with additional PA switching fields -- these additional fields will be used by RF driver when switching PA, not radio CPU.
        • +
      • [RF_PATCH] General: Updated all CPE patches to extend API with new common command to set TX power with possibility to switch between PAs. The command is named "CMD_CHANGE_PA".
        • +
      +
    • CC26x0R2 +
        +
      • [RF_PATCH] General: Added a set of new radio patches to support time-of-flight measurements ("tof") to estimate RF link distance.
        • +
      • [RF_PATCH] General: Added a set of new radio patches to support Bluetooth 4.2 and proprietary angle of arrival and departure measurements ("aoa_aod").
        • +
      • +
    + +

    Improvements

    +
      +
    • CC13x0 +
        +
      • [RF_PATCH] General: Updated all CPE patches with improved synthesizer start-up sequence that reduces the probability of synthesizer calibration failure.
        • +
      • [RF_PATCH] General: Added MCE patch for generic FSK ("genfsk") PHY to avoid receive sensitivity degradation in continuous RX operation over long time.
        • +
      • [RF_PATCH] General: CC1310, CC1350: Added latest version of MCE patch for WB-DSSS PHY (No change for customer. DSSS pattern is hard coded in the patch).
        • +
      • +
    + +

    Bug fixes

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_SRC] CPU: GCC CPUdelay() inline assembly incorrect.
        • +
      • +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      +
        +
      • [DRV_SRC] Crypto PKA: PKAGetBigNumResult() and PKAGetBigNumResultRemainder() static analysis warning.
        • +
      • [DRV_SRC] Crypto AES: AESConfigureCCMCtrl() static analysis warning.
        • +
      +
    • CC13x2_CC26x2_v1 +
        +
      • [RF_PATCH] General: Updated various CPE patch files ("ble", "bt5", "prop", "multi_protocol") to fix an issue with RAT_GPO1 output signal that can be routed out of RF core. The problem was that if RX is restarted within the same command, the RAT_GPO1 output signal would only be asserted on the first sync word received, but it would not be asserted after that if the radio is in RX after restart of the receiver, for example due to repeat mode being enabled.
        • +
      • [RF_PATCH] General: Updated all CPE patches supporting proprietary command set ("prop", "multi_protocol") to give correct time-out operation when using "CMD_PROP_RX_SNIFF" or "CMD_PROP_RX_ADV_SNIFF" commands. The carrier sense operation will continue after the csEndTrigger has occurred, if so configured.
        • +
      • [RF_PATCH] CC1352R, CC1352P, CC2652R: Added RFE patch for IEEE 802.15.4 O-QPSK DSSS ("ieee_802_15_4") PHY to resolve issue with RSSIMAXVAL reporting incorrect value.
        • +
      • +
    • CC26x0R2 +
        +
      • [RF_PATCH] General: Updated all CPE patches to align frequency word representation between frequency synthesizer and demodulator. This prevents temporary loss of receive function during continuous receive operation over long time for any "fractFreq" setting used.
        • +
      • +
    • CC26x0 +
        +
      • [RF_PATCH] General: Updated all CPE patches to align frequency word representation between frequency synthesizer and demodulator. This prevents temporary loss of receive function during continuous receive operation over long time for any "fractFreq" setting used.
        • +
      • +
    • CC13x0 +
        +
      • [RF_PATCH] General: Updated all CPE patches to align frequency word representation between frequency synthesizer and demodulator. This prevents temporary loss of receive function during continuous receive operation over long time for any "fractFreq" setting used.
        • +
      • [RF_PATCH] General: Updated all CPE patches supporting proprietary command set ("ant_div", "brepeat", "genfsk", "genook", "ghs", "lrm", "sl_longrange", "wb_dsss", "wbmus_ctmode", "wmbus_smode") to give correct time-out operation when using "CMD_PROP_RX_SNIFF" or "CMD_PROP_RX_ADV_SNIFF" commands. The carrier sense operation will continue after the csEndTrigger has occurred, if so configured.
        • +
      • [RF_PATCH] CC1350: Added RFE patch for IEEE 802.15.4 O-QPSK DSSS ("ieee") PHY to resolve issue with RSSIMAXVAL reporting incorrect value.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal, available in IO Controller as "RFC_GPO1", signaling the "PA_EN" status signal is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far support only differential front-end mode only, and will need a run-time modification (not implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_10_18419

    +
    + Release date: May 05, 2018
    + +

    New features

    +
      +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      +
        +
      • [RF_API] General: Introduce new RFCGetPaType and RFCGetPaGain functions.
        • +
      +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_DOC] General: List include file for each DriverLib module in HTML documentation.
        • +
      • [DRV_DOC] OSC: Function in Oscillator API is missing description for parameter.
        • +
      • [DRV_SRC] CPU: GCC CPUdelay() inline assembly incorrect.
        • +
      • [DRV_SRC] GPIO: Compile error in gpio.h when DRIVERLIB_DEBUG is defined.
        • +
      • +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      +
        +
      • [DRV_SRC] Crypto SHA: Defines in SHA2 module have semi-colon at the end of the line.
        • +
      • [DRV_SRC] GPIO: dioNumberLegal() in gpio.h can return incorrect value for cc26x2/cc13x2 devices.
        • +
      • [DRV_SRC] Crypto PKA: PKABigNumModGetResult can leave junk data in most significant bytes.
        • +
      • [DRV_SRC] General: Compile errors in ASSERTs when DRIVERLIB_DEBUG is defined.
        • +
      +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_09_18364

    +
    + Release date: April 17, 2018
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_DOC] General: General improvement of the documentation.
        • +
      • +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      +
        +
      • [HW_INC] RFC_DBELL: Renamed defines in hw_rfc_dbell.h for bit[13] and bit[12] of the RFCPEIFG, RFCPEIEN and RFCPEISL registers.
        • +
      +
    + +

    Bug fixes

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_SRC] GPIO: Compile error in gpio.h when DRIVERLIB_DEBUG is defined.
        • +
      • +
    + + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_08_18312

    +
    + Release date: March 2, 2018
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      +
        +
      • [DRV_SRC] Crypto PKA: Functions PKABigNumModGetResult and PKABigNumInvModGetResult both do not return how many bytes were written to the resultBuf. They can yield less than expected because the HW does not zero-pad beyond word boundaries. This is now handled by zero-out resultBuf before fetching the result so that correct assumptions about the result lengths can be made.
        • +
      +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_07_18288

    +
    + Release date: February 22, 2018
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2_v1
      • +
        +
      • [RF_PATCH] CC1312, CC1352, CC2642, CC2652: Updated all CPE patch files ("ble", "bt5", "ieee_802_15_4", "prop", "multi_protocol") to fix a problem in CPE's dynamic reconfiguration of the ADI_3_REFSYS:DCDCCTL5[3:0] register when radio enters RX or TX. A bug in the save/restore mechanism that should write DCDCCTL5[3:0] register back to its original setting when radio operation has ended caused the register setting to always be restored to setting 0x0. This undesired setting change of DCDCCTL5.IPEAK can cause an increased current consumption, if the DC/DC regulator is used. This fix will ensure DCDCCTL5[3:0] is correctly restored to original setting.
        • +
      • [RF_PATCH] CC1312, CC1352, CC2642, CC2652: Updated all CPE patch files ("ble", "bt5", "ieee_802_15_4", "prop", "multi_protocol") to fix an issue with CPEGPO1 output signal. This signal, available in IO Controller as "RFC_GPO1" signal, represents "PA_EN" status signal. This status signal should go high when the power amplifier (PA) is enabled (start of transmission), and then low when PA is disabled (end of transmission). For all protocols/PHYs other than Bluetooth low energy, there was an issue that prevented this signal to correctly go low at end of transmission, which has now been fixed.
        • +
      +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_06_18273

    +
    + Release date: February 21, 2018
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • CC13x2_CC26x2_v1 +
        +
      • [DRV_SRC] Setup: TrimAfterColdResetWakeupFromShutDown(): Removed workaround that was only valid for discontinued silicon revision.
        • +
      • +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      +
        +
      • [DRV_SRC] Crypto: Fixed potential race conditions when using aes.c.
        • +
      +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_05_18251

    +
    + Release date: February 07, 2018
    + +

    New features

    +
      +
    • CC13x2_CC26x2_v1
      • +
        +
      • [RF_PATCH] CC1352P: Updated CPE Bluetooth 5 ("bt5") and CPE multi-protocol patch files, and added a new RFE Bluetooth 5 ("bt5") patch file, to allow higher bandwidth in synthesizer PLL during Tx start-up. This allows faster PA settling when transmitting with 20-dBm PA.
        • +
      +
    + +

    Improvements

    +
      +
    • CC13x2_CC26x2_v2 +
        +
      • [DRV_SRC] Setup: TrimAfterColdResetWakeupFromShutDown(): HW register bit fields ADI_3_REFSYS:AUX_DEBUG.LPM_BIAS_BACKUP_EN and ADI_4_AUX:COMP.LPM_BIAS_WIDTH_TRIM are now written with values from FCFG1.
        • +
      • +
    + +

    Bug fixes

    +
      +
    • None
      • +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_04_18225

    +
    + Release date: February 01, 2018
    + +

    New features

    +
      +
    • CC13x2_CC26x2_v2
      • + CC13x2_CC26x2_v1
      + CC26x0
      + CC26x0R2
      + CC13x0 +
        +
      • [RF_API] General: The RFCOverrideSearch() function is now available on all devices and no longer static.
        • +
      +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • None
      • +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_03_18200

    +
    + Release date: January 25, 2018
    + +

    New features

    +
      +
    • CC13x2_CC26x2_v2
      • +
        +
      • [RF_API] CC1312, CC1352, CC2642, CC2652: Updated API header files.
        • +
      +
    • CC13x2_CC26x2_v1
      • +
        +
      • [RF_PATCH] CC1352, CC2642, CC2652: Updated CPE Bluetooth 5 ("bt5") and CPE multi-protocol patch files with new API functionality for configuring the 20-dBm PA output power when using CMD_BLE5_* command API.
        • +
      • [RF_API] ] CC1312, CC1352, CC2642, CC2652: +
          +
        • rf_ble_cmd.h: All CMD_BLE5_* radio operation command structs are extended with a new, optional "tx20Power" struct. This can be used to immediately set new 20-dBm PA setting in Tx.
          • +
        • rf_common_cmd.h: The common CMD_SET_TX20_POWER command is modified with "txPower" struct field renamed to "tx20Power". This is to highlight that the parameter is for the 20-dBm PA and not the normal PA.
          • +
        • +
      +
    + +

    Improvements

    +
      +
    • CC13x2_CC26x2_v2 +
        +
      • [DRV_SRC] Crypto PKA: Added missing length define (Curve25519_PARAM_SIZE_BYTES) in PKA module for Curve25519.
        • +
      • [DRV_SRC] Crypto PKA: Removed function PKAEccVerifyPublicKeyGetResult() since only the NIST and Brainpool curves are supported and they have a cofactor of 1. It's not needed to perform the Q*n = point at infinity check during public key validation.
        • +
      • +
    • CC13x2_CC26x2_v1 +
        +
      • [RF_PATCH] CC1312, CC1352, CC2652: Updated the RFE generic FSK ("genfsk") PHY patches with a new default setting for PA ramp-down wait time. This has been reduced from 31 µs down to 21 µs.
        • +
      • [DRV_SRC] Crypto PKA: Added missing length define (Curve25519_PARAM_SIZE_BYTES) in PKA module for Curve25519.
        • +
      • [DRV_SRC] Crypto PKA: Removed function PKAEccVerifyPublicKeyGetResult() since only the NIST and Brainpool curves are supported and they have a cofactor of 1. It's not needed to perform the Q*n = point at infinity check during public key validation.
        • +
      • +
    + +

    Bug fixes

    +
      +
    • None
      • +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_02_18173

    +
    + Release date: January 15, 2018
    + +

    New features

    +
      +
    • CC13x2_CC26x2_v2
      • +
        +
      • [RF_API] General: Initial release of preliminary API header files.
        • +
      • [DRV_SRC] Crypto PKA: Added Montgomery Curve25519 multiplication support.
        • +
      +
    • CC13x2_CC26x2_v1
      • +
        +
      • [DRV_SRC] Crypto PKA: Added Montgomery Curve25519 multiplication support.
        • +
      +
    + +

    Improvements

    +
      +
    • CC13x2_CC26x2_v1 +
        +
      • [RF_PATCH] General: CC1312, CC1352, CC2652: Updated the RFE and MCE generic FSK ("genfsk") PHY patches with small optimizations in TX timing for PA enable at start of packet, and increased default setting for PA ramp-down time from 10 µs to 31 µs. Modulator timing has also been tuned for better performance at high data rates (>500 kbps) and now waits 4 µs with tone before starting preamble to better align with PA ramp-up.
        • +
      • [RF_PATCH] General: CC1352, CC2652: Updated the IEEE 802.15.4 O-QPSK DSSS ("ieee_802_15_4") PHY patch with improvements in modem re-initialization between RX packets.
        • +
      • +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2_v1
      • +
        +
      • [RF_API] General: CC1312, CC1352, CC2642, CC2652: Updated API header file "rf_mailbox.h" to remove an incorrect interrupt "BG_COMMAND_SUSPENDED" (interrupt line 12) which does not exist.
        • +
      • [RF_PATCH] General: CC1312, CC1352: Updated the MCE SimpleLink Long Range ("sl_longrange") PHY patch to fix a potential problem related to stopping the demodulator when using SimpleLink Long Range PHY formats. The problem was that use of CMD_ABORT or CMD_PROP_RESTART_RX to stop an on-going RX operation with this PHY could result in RF core doorbell interface to become unresponsive, and a re-initialization (power-cycle) of RF core would be needed to recover.
        • +
      +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_01_18155

    +
    + Release date: January 05, 2018
    + +

    New features

    +
      +
    • CC13x2_CC26x2_v1
      • + CC13x2_CC26x2_v2 +
        +
      • [DRV_SRC] AUX_ADC: Added additional defines for supported trigger events.
        • +
      +
    + +

    Improvements

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_SRC] Crypto: Improved key loading error handling to avoid system crash during heavy bus load.
        • +
      • +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2_v1
      • + CC13x2_CC26x2_v2 +
        +
      • [DRV_SRC] Crypto PKA: Fixed PKAEccVerifyPublicKeyWeierstrassStart() function which incorrectly failed for curves that were not a multiple of 4 bytes in length.
        • +
      +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_04_00_18127

    +
    + Release date: December 14, 2017
    + +

    New features

    +
      +
    • CC13x2_CC26x2 +
        +
      • [DRV_SRC] General:Two variants of driverlib are introduced. The driverlib folder for the legacy version is renamed from "cc13x2_cc26x2" to "cc13x2_cc26x2_v1". A new driverlib folder for a planned upgraded silicon revision of cc13x2_cc26x2 devices is called "cc13x2_cc26x2_v2".
        • +
      • [DRV_SRC] Crypto PKA: Added support for Short-Weierstrass public key validation, NIST-P224 and NIST-P384 to PKA module.
        • +
      • +
    + +

    Improvements

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_SRC] ChipInfo: Renamed enumerations returned from function ChipInfo_GetChipType(). Renamed CHIP_TYPE_CC2644 to CHIP_TYPE_unused and CHIP_TYPE_CC1354 to CHIP_TYPE_CC1352P.
        • +
      • +
    + +

    Bug fixes

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_SRC] AUX_ADC: AUXADCDisable() now flushes the ADC FIFO in order to remove stale samples in the FIFO after the ADC module is disabled. If samples are left in the FIFO after disabling the ADC, the related ADC_IRQ flag may not be cleared. This is a potential problem when operating at high sampling rates where additional conversions may complete between handling an ISR and disabling the ADC, possibly causing an infinite ISR loop.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_03_04_18115

    +
    + Release date: December 7, 2017
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • CC26x0R2 +
        +
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch with bug fix for Bluetooth 5 LE Advertising Extensions: The Bluetooth 5 initiator command sometimes outputs a "connectTime" that does not correspond to the transmitted AUX_CONNECT_REQ.
        • +
      • +
    • CC13x2_CC26x2 +
        +
      • [RF_PATCH] CPE: CC1352, CC2642, CC2652: Updated CPE BT5 and CPE multi-protocol patches with bug fix for Bluetooth 5 LE Advertising Extensions: The Bluetooth 5 initiator command sometimes outputs a "connectTime" that does not correspond to the transmitted AUX_CONNECT_REQ.
        • +
      • [RF_PATCH] RFE: CC1312, CC1352, CC2652: Updated the RFE generic FSK ("genfsk") PHY patch with bug fix in PA ramp mechanism: the RFE, and thus CPE, may hang if TX is aborted shortly after start.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_03_03_18107

    +
    + Release date: December 1, 2017
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • CC13x2_CC26x2 +
        +
      • [RF_PATCH] CPE/MCE: CC1312, CC1352: Updated the CPE PROP, CPE multi-protocol, and MCE SimpleLink Long Range (SLR) PHY patches to fix a problem related to stopping the demodulator when using SLR PHY formats. The problem was that use of CMD_ABORT or CMD_PROP_RESTART_RX to stop an on-going RX operation with this PHY could result in RF core doorbell interface to become unresponsive, and a re-initialization (power-cycle) of RF core would be needed to recover. (internal: RFCORE-163).
        • +
      • [RF_PATCH] MCE BT5: CC1352, CC2642, CC2652: Updated MCE BT5 patch to resolve a potential PHY problem where too high TX symbol rate error (up to 100 ppm) may be used for LE Coded PHY, which will violate Bluetooth 5 PHY specification requirements (max 50 ppm). The problem could be invoked, depending on a timing condition, as part of doing an RX to TX transition using LE Coded PHY. (internal: RFCORE-166).
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_03_02_18061

    +
    + Release date: November 10, 2017
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • Changes that apply to all devices +
        +
      • [RF_API] General: In all API files, resolved CCS compiler warning when using attribute "aligned(4)" on structs with struct member of type uint64_t.
        • +
      • +
    • CC13x2_CC26x2 +
        +
      • [DRV_SRC] Setup: SetupTrimDevice(): Fixed bug that caused the supported "Boost mode" during boot to be non-functional. The supported mode boosts VDDR to support +14dBm.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_03_01_18037

    +
    + Release date: November 3, 2017
    + +

    New features

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_API] New functions in rfc.c and rfc.h: +
          +
        • __STATIC_INLINE void RFCCpe0IntSelect(uint32_t ui32Mask): This function maps the interrupt lines provided within the argument to CPE0.
          • +
        • __STATIC_INLINE void RFCCpe1IntSelect(uint32_t ui32Mask): This function maps the interrupt lines provided within the argument to CPE1.
          • +
        • +
      • [DRV_SRC] OSC: Add debug/test function OSC_AdjustXoscHfCapArray(). Useful for production preparations when trying to find optimal HF XOSC Cap Array setting for a specific design. Ref. SET_CCFG_MODE_CONF_XOSC_CAP... in ccfg.c
        • +
      • [DRV_SRC] PowerCtrl: Added the following functions: +
          +
        • PowerCtrlPadSleepEnable()
          • +
        • PowerCtrlPadSleepDisable()
          • +
        • +
      • +
    • CC13x0 +
        +
      • [RF_PATCH] MCE: Added new MCE patch for Generic FSK with CC1101-compatible FEC and interleaver ("genfsk_fec_cc1101").
        • +
      • +
    • CC26x0R2 +
        +
      • [RF_API] BLE5: Updated Bluetooth 5 command API ("BLE5"): Added Bluetooth 5 variants of legacy advertiser commands (CMD_BLE5_ADV, CMD_BLE5_ADV_DIR, CMD_BLE5_ADV_NC, CMD_BLE5_ADV_SCAN). These new commands are only available when using an updated CPE BT5 patch.
        • +
      • [RF_API] PROP: In PROP API command CMD_PROP_RADIO_SETUP the bit-fields "symbolRate.bPdifDecim" and "symbolRate.pdifDecim" have been merged into one new bit-field ".symbolRate.decimMode". This is to make the CC2640R2F API the same as for CC13x0.
        • +
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch to include Bluetooth 5 variants of legacy advertiser commands (CMD_BLE5_ADV, CMD_BLE5_ADV_DIR, CMD_BLE5_ADV_NC, CMD_BLE5_ADV_SCAN).
        • +
      • +
    • CC13x2_CC26x2 +
        +
      • [RF_API] BLE5: Updated Bluetooth 5 command API ("BLE5"): Added Bluetooth 5 variants of legacy advertiser commands (CMD_BLE5_ADV, CMD_BLE5_ADV_DIR, CMD_BLE5_ADV_NC, CMD_BLE5_ADV_SCAN). These new commands are only available when using an updated CPE BT5 or CPE multi-protocol patch.
        • +
      • [RF_API] PROP: In PROP API commands CMD_PROP_RADIO_SETUP and CMD_PROP_RADIO_DIV_SETUP a new bit-field "modulation.deviationStepSz" has been added. This can be used to configure the resolution of the existing bit-field "modulation.deviation".
        • +
      • [RF_PATCH] CPE: Updated CPE BT5 and CPE multi-protocol patches to include Bluetooth 5 variants of legacy advertiser commands (CMD_BLE5_ADV, CMD_BLE5_ADV_DIR, CMD_BLE5_ADV_NC, CMD_BLE5_ADV_SCAN).
        • +
      • [RF_PATCH] CPE: The CPE patch files "rf_patch_cpe_sl_longrange.h" and "rf_patch_cpe_genfsk.h" have been removed. The CPE PROP patch ("rf_patch_cpe_prop.h") already covers these cases and should be used instead. Alternatively, the CPE multi-protocol patch may be used.
        • +
      • [DRV_SRC] Setup: Added support in SetupTrimDevice() to enable "Boost mode" during boot, boosting VDDR to support +14dBm.
        • +
      • [DRV_SRC] sys_ctrl: Added SysCtrlShutdownWithAbort() as a workaround to detect pre-shutdown wakeup events.
        • +
      • [DRV_SRC] sys_ctrl: Added handling of optional temperature compensation of the recharge level (enabled by setting CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC = 0).
        • +
      • [DRV_SRC] Crypto PKA: Added subtraction function to PKA module and EC-JPAKE updates.
        • +
      • +
    + +

    Improvements

    +
      +
    • Changes that apply to all devices +
        +
      • [DRV_SRC] Eliminated functions in rfc.c and rfc.h:
        + These functions did not provided a safe way to handle clock management, hence they have been removed from the rfc.h file.
        + It is recommended that enabling/disabling clocks in the RF core should be requested through radio commands instead. +
          +
        • __STATIC_INLINE void RFCClockSet(uint32_t ui32Mask)
          • +
        • __STATIC_INLINE void RFCClockClear(uint32_t ui32Mask)
          • +
        • +
      • [HW_INC] General: Updated/improved hardware register descriptions (inc/hw_*.h and doc/../*.html files).
        • +
      • [DRV_SRC] PowerCtrl: The following functions are either removed or marked as derprecated: +
          +
        • PowerCtrlIOFreezeEnable() removed
          • +
        • PowerCtrlIOFreezeDisable() removed
          • +
        • PowerCtrlResetSourceGet() marked as deprecated. It will be removed in a future release. Use SysCtrlResetSourceGet() instead.
          • +
        • +
      • +
    • CC13x0 +
        +
      • [RF_PATCH] MCE: Updated MCE bit-repeat patch ("brepeat") to add support for very long or infinite preamble.
        • +
      • +
    • CC26x0R2 +
        +
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch for Bluetooth 5 to implement that CPE re-reads the "pConnectReqData" parameter pointer before sending AUX_CONNECT_REQ.
        • +
      • +
    • CC13x2_CC26x2 +
        +
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch for Bluetooth 5 to implement that CPE re-reads the "pConnectReqData" parameter pointer before sending AUX_CONNECT_REQ.
        • +
      • [RF_PATCH] CPE: Updated CPE BLE, CPE BT5, CPE PROP, and CPE multi-protocol patches with improvement to make the (G)FSK deviation in Tx constant over the frequency band by recalculating the Tx shape when RF synth is programmed to a new frequency.
        • +
      • [DRV_SRC] The following functions are not applicable on these devices and hence been removed from rfc.c and rfc.h: +
          +
        • void RFCRfTrimRead(rfc_radioOp_t *pOpSetup, rfTrim_t* pRfTrim)
          • +
        • void RFCRTrim(rfc_radioOp_t *pOpSetup)
          • +
        • void RFCRfTrimSet(rfTrim_t* pRfTrim)
          • +
        • void RFCAdi3VcoLdoVoltageMode(bool bEnable)
          • +
        • +
      • [DRV_SRC] Crypto SHA2: Updated SHA2 driverlib to support partial hashing of multiple blocks at a time.
        • +
      • [DRV_SRC] sys_ctrl: SysCtrlShutdown() now terminates in a while(1) to make sure it never returns.
        • +
      • [DRV_SRC] AON/sys_ctrl: Removed function AONPMCTLShutDownEnable(), use SysCtrlShutdown() instead.
        • +
      • +
    + +

    Bug fixes

    +
      +
    • Changes that apply to all devices +
        +
      • [RF_API] General: In all API files, resolved a syntax problem with the struct attribute when compiling with GCC or CCS.
        • +
      • [DRV_SRC] Behavioural change in rfc.c and rfc.h: +
          +
        • __STATIC_INLINE void RFCClockEnable(void): This function only enables the interrupts which are needed to get the CM0 running. This is to optimize consumption.
          • +
        • __STATIC_INLINE void RFCHwIntEnable(uint32_t ui32Mask): The old function was clearing the interrupts before enabling.
          • +
        • __STATIC_INLINE void RFCCpeIntEnable(uint32_t ui32Mask): This function only enables the interrupts, regardless if it is mapped to CPE0 or CPE1. It does not modify the pending interrupt flags.
          • +
        • +
      • [DRV_API] Function prototype changes in rfc.c and rfc.h: +
          +
        • uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask): This function was reading and clearing all the CPE interrupt flags, regardless if the handler routine has actually the right to do so. This could cause problems in applications where multiple users share the CPE interrupts. The new function only handles the interrupts which match the provided bitmask.
          • +
        • void RFCCpePatchReset(void): The function name was aligned with the camel-case naming convention of driverlib functions.
          • +
        • void RFCSynthPowerDown(void): This function is now explicitly takes no argument.
          • +
        • RFCHwIntGetAndClear(uint32_t ui32Mask): The function name was aligned with the camel-case naming convention of driverlib functions.
          • +
        • __STATIC_INLINE void RFCCpe0IntSelectClearEnable(uint32_t ui32Mask): The function was renamed to reflect its internal behavior.
          • +
        • __STATIC_INLINE void RFCCpe1IntSelectClearEnable(uint32_t ui32Mask): The function was renamed to reflect its internal behavior.
          • +
        • +
      • +
    • CC13x2_CC26x2 +
        +
      • [RF_API] IEEE: In API for "IEEE" commands, a type problem for the struct member "CMD_IEEE_RX.pShortEntryList" was fixed. This fix aligns the API structs with the existing API for CC26x0.
        • +
      • [RF_PATCH] CPE: Updated CPE PROP and CPE multi-protocol patches with bug fix: if a packet is received with a proprietary mode Rx command (CMD_PROP_RX*) and a partial read Rx buffer is used, the CPE will hang if an abort command is received while a packet is being received.
        • +
      • [DRV_SRC] Crypto PKA: Fixed issue where PKAGetECCResult would read and uninitialized variable when not copying back the x coordinate.
        • +
      • [DRV_SRC] Crypto PKA: Fixed bug where PKAGetECCResult would calculate an incorrect offset for curvePointY in PKA RAM and copy back an incorrect result.
        • +
      • [DRV_SRC] Setup: SetupTrimDevice(): Include the LPM_BIAS trims in the boot sequence.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: The CPEGPO1 output signal (available in IO Controller as "RFC_GPO1"), signaling the "PA_EN" status, is not functional. The signal does not go low at end of transmission.
        • +
      • [RF_SETTING] BT5: All Bluetooth 5 radio settings so far only support differential front-end mode, and will need a run-time modification (not yet implemented) of trim value in override list to achieve correct settings.
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_02_03_17972

    +
    + Release date: September 21, 2017
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • CC26x0R2 +
        +
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch to include bug fix for Bluetooth 5: Address type of received ADV_AUX_IND packets is not treated correctly.
        • +
      • +
    • CC13x2_CC26x2 +
        +
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch to include bug fix for Bluetooth 5: Address type of received ADV_AUX_IND packets is not treated correctly.
        • +
      • [RF_PATCH] CPE multi-protocol: Updated CPE multi-protocol patch to include bug fix for Bluetooth 5: Address type of received ADV_AUX_IND packets is not treated correctly.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: GPO control not functional. (The PA_EN status signal does not go low).
        • +
      • +
    +
    +
    +
    +

    driverlib_cc13xx_cc26xx_3_02_02_17958

    +
    + Release date: September 21, 2017
    + +

    New features

    +
      +
    • None
      • +
    + +

    Improvements

    +
      +
    • None
      • +
    + +

    Bug fixes

    +
      +
    • CC26x0R2 +
        +
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch to include bug fix for Bluetooth 5: receiving ADV_EXT_IND that contains AuxPtr with CRC error causes stall.
        • +
      • +
    • CC13x2_CC26x2 +
        +
      • [RF_PATCH] CPE BT5: Updated CPE BT5 patch to include bug fix for Bluetooth 5: receiving ADV_EXT_IND that contains AuxPtr with CRC error causes stall.
        • +
      • [RF_PATCH] CPE multi-protocol: Updated CPE multi-protocol patch to include bug fix for Bluetooth 5: receiving ADV_EXT_IND that contains AuxPtr with CRC error causes stall.
        • +
      • +
    + +

    Known issues

    +
      +
    • CC26x0
      • +
        +
      • [RF_PATCH] General: CMD_SCH_IMM can cause loss of commands.
        • +
      +
    • CC26x0R2 +
        +
      • [RF_API] General: GPO control not functional. (The PA_EN status signal does not go low).
        • +
      • +
    +
    +

    driverlib_cc13xx_cc26xx_3_02_01_17905

    @@ -111,14 +1498,12 @@
    @@ -136,9 +1521,9 @@