diff --git a/third_party/NordicSemiconductor/nrfx/CHANGELOG.md b/third_party/NordicSemiconductor/nrfx/CHANGELOG.md
index 8a10a078e..a148f3340 100644
--- a/third_party/NordicSemiconductor/nrfx/CHANGELOG.md
+++ b/third_party/NordicSemiconductor/nrfx/CHANGELOG.md
@@ -1,6 +1,74 @@
# Changelog
All notable changes to this project are documented in this file.
+## [1.8.0] - 2019-08-27
+### Added
+- Added support for nRF52833.
+- Added bus recovery feature in the TWI and TWIM drivers.
+- Added the nrfx_gppi helper layer to facilitate developing generic code that can utilize PPI or DPPI, depending on which interface is available in a given SoC.
+
+### Changed
+- Updated MDK to version 8.27.0.
+
+### Fixed
+- Fixed an issue in the TWIM driver that would make the driver stuck when a premature STOP condition was generated by a slave device. The driver now handles this situation properly and signals that a bus error occurred.
+- Fixed a frame timing bug in the NFCT driver. Previously, the timing of the SENS_RES response could be violated after the NFCT peripheral was put to the Sleep state with the SLP_REQ command.
+
+## [1.7.2] - 2019-07-25
+### Added
+- Added functions in the DPPI, GPIOTE, PPI, RTC, and TIMER HALs for getting tasks and events specified by index.
+- Added the possibility of suspending transfers in the TWI driver. This allows combining several transfers into one continuous TWI transaction.
+- Added termination of transfers at deinitialization of the UARTE driver.
+- Added buffer alignment checks in the QSPI driver.
+- Introduced the NRFX_OFFSETOF macro that duplicates the functionality of the built-in offsetof() mechanism, but can be used without issues also with non-constant expressions.
+- Added an alternative way of ending the DMA transfer loop in the USBD driver.
+- Added the CTSTARTED and CTSTOPPED events to the CLOCK HAL.
+
+### Changed
+- Removed an assertion that prevented setting the data payload size of isochronous endpoints to zero, to fulfill requirements of the USB 2.0 specification, paragraph 5.6.3.
+- Declared the tx_buffer_length field in the UART driver's control block as volatile to prevent issues in case of compilation with high optimization level.
+
+### Fixed
+- Fixed an incorrect conversion of frequency values in the RADIO HAL.
+- Fixed an incorrectly enabled interrupt in the QSPI driver.
+- Corrected the LFCLK source selection values in the template configuration file for nRF9160.
+- Fixed support for external LFCLK sources for nRF52811.
+
+## [1.7.1] - 2019-04-08
+### Added
+- Added functions in the NVMC driver for getting the flash page size, the count of pages and the total flash size.
+
+### Fixed
+- Fixed handling of short unaligned write requests (1 or 2 bytes in length) in the nrfx_nvmc_bytes_write() function.
+
+## [1.7.0] - 2019-03-29
+### Added
+- Added drivers for NVMC and TEMP.
+- Added HALs: AAR and FICR.
+- Added support for the custom instruction long frame mode in the QSPI driver.
+
+### Changed
+- Reworked HAL for NVMC. Now it can be used for all SoCs supported by nrfx.
+- Reworked HAL for TEMP.
+- Improved documentation. Now it is more precise and can be generated without warnings with newer versions of doxygen.
+- Improved the UARTE driver to consume less current after the TX operation. Now at the end of the transmission the transmitter is turned off by the STOPTX task.
+- Improved C++ support in drivers. Now fields in structures are filled up in the correct order.
+- Changed to size_t the type used for holding the amount of data in the TWIS driver.
+
+### Fixed
+- Fixed a race condition in the USBD driver. It could occur when an IN transfer was interrupted by an OUT transaction, which in turn was interrupted by a process with a higher priority.
+
+## [1.6.2] - 2019-02-12
+### Added
+- Added the possibility to use the macro NRFX_COREDEP_DELAY_US_LOOP_CYCLES to specify the number of cycles consumed by one iteration of the internal loop in the function nrfx_coredep_delay_us().
+
+### Changed
+- Updated MDK to version 8.24.1.
+
+## [1.6.1] - 2019-01-29
+### Fixed
+- Fixed an issue in the NFCT driver that caused a performance loss on nRF52832. The interrupt configuration is now properly restored after the NRFX_NFCT_EVT_FIELD_LOST event.
+
## [1.6.0] - 2019-01-18
### Added
- Added support for nRF52811.
diff --git a/third_party/NordicSemiconductor/nrfx/README.md b/third_party/NordicSemiconductor/nrfx/README.md
index ab233c0ee..597398c67 100644
--- a/third_party/NordicSemiconductor/nrfx/README.md
+++ b/third_party/NordicSemiconductor/nrfx/README.md
@@ -16,6 +16,7 @@ SoCs, as well as startup and initialization files for them.
* nRF52810
* nRF52811
* nRF52832
+* nRF52833
* nRF52840
* nRF9160
@@ -24,12 +25,13 @@ SoCs, as well as startup and initialization files for them.
```
.
├── doc # Project documentation files
- ├── drivers # nrfx drivers files
- │ └── include # nrfx drivers headers
- │ └── src # nrfx drivers sources
+ ├── drivers # nrfx driver files
+ │ └── include # nrfx driver headers
+ │ └── src # nrfx driver sources
├── hal # Hardware Access Layer files
- ├── mdk # Nordic MDK files
- ├── soc # Nordic SoC related files
+ ├── helpers # nrfx driver helper files
+ ├── mdk # nRF MDK files
+ ├── soc # SoC specific files
└── templates # Templates of nrfx integration files
```
diff --git a/third_party/NordicSemiconductor/nrfx/doc/buildfiles/nordic_small.png b/third_party/NordicSemiconductor/nrfx/doc/buildfiles/nordic_small.png
index 7b6a313be..9ebfb7b56 100644
Binary files a/third_party/NordicSemiconductor/nrfx/doc/buildfiles/nordic_small.png and b/third_party/NordicSemiconductor/nrfx/doc/buildfiles/nordic_small.png differ
diff --git a/third_party/NordicSemiconductor/nrfx/doc/drv_supp_matrix.dox b/third_party/NordicSemiconductor/nrfx/doc/drv_supp_matrix.dox
index ea32f3c34..de320a6a2 100644
--- a/third_party/NordicSemiconductor/nrfx/doc/drv_supp_matrix.dox
+++ b/third_party/NordicSemiconductor/nrfx/doc/drv_supp_matrix.dox
@@ -3,51 +3,53 @@
The following matrix shows which drivers are supported by specific Nordic SoCs.
@{
-Driver | nRF51 Series | nRF52810/nRF52811 | nRF52832 | nRF52840 | nRF9160 |
------------------|--------------|-------------------| -------------| -------------| -------------|
-@ref nrf_adc |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |
-@ref nrf_acl |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |
-@ref nrf_bprot |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |
-@ref nrf_ccm |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_clock |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_comp |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_dppi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |
-@ref nrf_ecb |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_i2s |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_kmu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |
-@ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_mpu |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |
-@ref nrf_mwu |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_nfct |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_pdm |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_ppi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_pwm |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |
-@ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_spi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_spim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_spis |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_spu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |
-@ref nrf_systick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_swi_egu |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_temp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_timer |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_twi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_twim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_twis |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_uart |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
-@ref nrf_uarte |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
-@ref nrf_usbd |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |
-@ref nrf_vmc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |
-@ref nrf_wdt |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+Driver | nRF51 Series | nRF52810/nRF52811 | nRF52832 | nRF52833 | nRF52840 | nRF9160 |
+-----------------|--------------|-------------------| -------------| -------------| -------------| -------------|
+@ref nrf_aar |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_adc |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |
+@ref nrf_acl |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_bprot |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |
+@ref nrf_ccm |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_clock |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_comp |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_dppi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |
+@ref nrf_ecb |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_ficr |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_i2s |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_kmu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |
+@ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_mpu |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |
+@ref nrf_mwu |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_nfct |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_pdm |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_ppi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_pwm |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |
+@ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_spi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_spim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_spis |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_spu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |
+@ref nrf_systick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_swi_egu |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_temp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_timer |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_twi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_twim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_twis |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_uart |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_uarte |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
+@ref nrf_usbd |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |
+@ref nrf_vmc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |
+@ref nrf_wdt |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
@}
*/
diff --git a/third_party/NordicSemiconductor/nrfx/doc/nrf51_series.dox b/third_party/NordicSemiconductor/nrfx/doc/nrf51_series.dox
index 2e9a50555..3f8201f0e 100644
--- a/third_party/NordicSemiconductor/nrfx/doc/nrf51_series.dox
+++ b/third_party/NordicSemiconductor/nrfx/doc/nrf51_series.dox
@@ -2,6 +2,8 @@
@page nrf51_series_drivers nRF51 Series Drivers
@{
+@ref nrf_aar
+
@ref nrf_adc
@ref nrf_ccm
@@ -10,6 +12,8 @@
@ref nrf_ecb
+@ref nrf_ficr
+
@ref nrf_gpio
@ref nrf_gpiote
diff --git a/third_party/NordicSemiconductor/nrfx/doc/nrf52810.dox b/third_party/NordicSemiconductor/nrfx/doc/nrf52810.dox
index ab6aaef00..6aba43421 100644
--- a/third_party/NordicSemiconductor/nrfx/doc/nrf52810.dox
+++ b/third_party/NordicSemiconductor/nrfx/doc/nrf52810.dox
@@ -2,6 +2,8 @@
@page nrf52810_drivers nRF52810/nRF52811 Drivers
@{
+@ref nrf_aar
+
@ref nrf_bprot
@ref nrf_ccm
@@ -12,6 +14,8 @@
@ref nrf_ecb
+@ref nrf_ficr
+
@ref nrf_gpio
@ref nrf_gpiote
diff --git a/third_party/NordicSemiconductor/nrfx/doc/nrf52832.dox b/third_party/NordicSemiconductor/nrfx/doc/nrf52832.dox
index 5ddaea276..58f3bbda9 100644
--- a/third_party/NordicSemiconductor/nrfx/doc/nrf52832.dox
+++ b/third_party/NordicSemiconductor/nrfx/doc/nrf52832.dox
@@ -2,6 +2,8 @@
@page nrf52832_drivers nRF52832 Drivers
@{
+@ref nrf_aar
+
@ref nrf_bprot
@ref nrf_ccm
@@ -12,6 +14,8 @@
@ref nrf_ecb
+@ref nrf_ficr
+
@ref nrf_gpio
@ref nrf_gpiote
diff --git a/third_party/NordicSemiconductor/nrfx/doc/nrf52833.dox b/third_party/NordicSemiconductor/nrfx/doc/nrf52833.dox
new file mode 100644
index 000000000..d2637d98a
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/doc/nrf52833.dox
@@ -0,0 +1,80 @@
+/**
+@page nrf52833_drivers nRF52833 Drivers
+@{
+
+@ref nrf_aar
+
+@ref nrf_acl
+
+@ref nrf_ccm
+
+@ref nrf_clock
+
+@ref nrf_comp
+
+@ref nrf_ecb
+
+@ref nrf_ficr
+
+@ref nrf_gpio
+
+@ref nrf_gpiote
+
+@ref nrf_i2s
+
+@ref nrf_lpcomp
+
+@ref nrf_mwu
+
+@ref nrf_nfct
+
+@ref nrf_nvmc
+
+@ref nrf_pdm
+
+@ref nrf_power
+
+@ref nrf_ppi
+
+@ref nrf_pwm
+
+@ref nrf_qdec
+
+@ref nrf_radio
+
+@ref nrf_rng
+
+@ref nrf_rtc
+
+@ref nrf_saadc
+
+@ref nrf_spi
+
+@ref nrf_spim
+
+@ref nrf_spis
+
+@ref nrf_systick
+
+@ref nrf_swi_egu
+
+@ref nrf_temp
+
+@ref nrf_timer
+
+@ref nrf_twi
+
+@ref nrf_twim
+
+@ref nrf_twis
+
+@ref nrf_uart
+
+@ref nrf_uarte
+
+@ref nrf_usbd
+
+@ref nrf_wdt
+
+@}
+*/
diff --git a/third_party/NordicSemiconductor/nrfx/doc/nrf52840.dox b/third_party/NordicSemiconductor/nrfx/doc/nrf52840.dox
index a3595b0f7..7e9b51ece 100644
--- a/third_party/NordicSemiconductor/nrfx/doc/nrf52840.dox
+++ b/third_party/NordicSemiconductor/nrfx/doc/nrf52840.dox
@@ -2,6 +2,8 @@
@page nrf52840_drivers nRF52840 Drivers
@{
+@ref nrf_aar
+
@ref nrf_acl
@ref nrf_ccm
@@ -12,6 +14,8 @@
@ref nrf_ecb
+@ref nrf_ficr
+
@ref nrf_gpio
@ref nrf_gpiote
diff --git a/third_party/NordicSemiconductor/nrfx/doc/nrf9160.dox b/third_party/NordicSemiconductor/nrfx/doc/nrf9160.dox
index 3bdd9d79e..fd929ad0e 100644
--- a/third_party/NordicSemiconductor/nrfx/doc/nrf9160.dox
+++ b/third_party/NordicSemiconductor/nrfx/doc/nrf9160.dox
@@ -8,6 +8,8 @@
@ref nrf_dppi
+@ref nrf_ficr
+
@ref nrf_gpio
@ref nrf_gpiote
@@ -16,6 +18,8 @@
@ref nrf_kmu
+@ref nrf_nvmc
+
@ref nrf_pdm
@ref nrf_power
diff --git a/third_party/NordicSemiconductor/nrfx/doc/nrfx.doxyfile b/third_party/NordicSemiconductor/nrfx/doc/nrfx.doxyfile
index da96b8108..3bf06cc2d 100644
--- a/third_party/NordicSemiconductor/nrfx/doc/nrfx.doxyfile
+++ b/third_party/NordicSemiconductor/nrfx/doc/nrfx.doxyfile
@@ -1,1553 +1,2030 @@
-# Doxyfile 1.8.3.1
+# Doxyfile 1.8.14
# This file describes the settings to be used by the documentation system
# doxygen (www.doxygen.org) for a project.
#
-# All text after a hash (#) is considered a comment and will be ignored.
+# All text after a double hash (##) is considered a comment and is placed in
+# front of the TAG it is preceding.
+#
+# All text after a single hash (#) is considered a comment and will be ignored.
# The format is:
-# TAG = value [value, ...]
-# For lists items can also be appended using:
-# TAG += value [value, ...]
-# Values that contain spaces should be placed between quotes (" ").
+# TAG = value [value, ...]
+# For lists, items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (\" \").
#---------------------------------------------------------------------------
# Project related configuration options
#---------------------------------------------------------------------------
# This tag specifies the encoding used for all characters in the config file
-# that follow. The default is UTF-8 which is also the encoding used for all
-# text before the first occurrence of this tag. Doxygen uses libiconv (or the
-# iconv built into libc) for the transcoding. See
-# http://www.gnu.org/software/libiconv for the list of possible encodings.
+# that follow. The default is UTF-8 which is also the encoding used for all text
+# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv
+# built into libc) for the transcoding. See
+# https://www.gnu.org/software/libiconv/ for the list of possible encodings.
+# The default value is: UTF-8.
-DOXYFILE_ENCODING = UTF-8
+DOXYFILE_ENCODING = UTF-8
-# The PROJECT_NAME tag is a single word (or sequence of words) that should
-# identify the project. Note that if you do not use Doxywizard you need
-# to put quotes around the project name if it contains spaces.
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
+# double-quotes, unless you are using Doxywizard) that should identify the
+# project for which the documentation is generated. This name is used in the
+# title of most generated pages and in a few other places.
+# The default value is: My Project.
+
+PROJECT_NAME = "nrfx"
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number. This
+# could be handy for archiving the generated documentation or if some version
+# control system is used.
-PROJECT_NAME = "nrfx"
### EDIT THIS ###
-# The PROJECT_NUMBER tag can be used to enter a project or revision number.
-# This could be handy for archiving the generated documentation or
-# if some version control system is used.
-
-PROJECT_NUMBER = "1.6"
-### EDIT THIS ###
+PROJECT_NUMBER = "1.8"
# Using the PROJECT_BRIEF tag one can provide an optional one line description
-# for a project that appears at the top of each page and should give viewer
-# a quick idea about the purpose of the project. Keep the description short.
+# for a project that appears at the top of each page and should give viewer a
+# quick idea about the purpose of the project. Keep the description short.
-PROJECT_BRIEF =
-
-# With the PROJECT_LOGO tag one can specify an logo or icon that is
-# included in the documentation. The maximum height of the logo should not
-# exceed 55 pixels and the maximum width should not exceed 200 pixels.
-# Doxygen will copy the logo to the output directory.
-
-PROJECT_LOGO = buildfiles/nordic_small.png
-
-# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
-# base path where the generated documentation will be put.
-# If a relative path is entered, it will be relative to the location
-# where doxygen was started. If left blank the current directory will be used.
-
-OUTPUT_DIRECTORY =
### EDIT THIS ###
-# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
-# 4096 sub-directories (in 2 levels) under the output directory of each output
-# format and will distribute the generated files over these directories.
-# Enabling this option can be useful when feeding doxygen a huge amount of
-# source files, where putting all generated files in the same directory would
-# otherwise cause performance problems for the file system.
+PROJECT_BRIEF =
-CREATE_SUBDIRS = NO
+# With the PROJECT_LOGO tag one can specify a logo or an icon that is included
+# in the documentation. The maximum height of the logo should not exceed 55
+# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy
+# the logo to the output directory.
+
+PROJECT_LOGO = buildfiles/nordic_small.png
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
+# into which the generated documentation will be written. If a relative path is
+# entered, it will be relative to the location where doxygen was started. If
+# left blank the current directory will be used.
+
+OUTPUT_DIRECTORY =
+
+# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub-
+# directories (in 2 levels) under the output directory of each output format and
+# will distribute the generated files over these directories. Enabling this
+# option can be useful when feeding doxygen a huge amount of source files, where
+# putting all generated files in the same directory would otherwise causes
+# performance problems for the file system.
+# The default value is: NO.
+
+### EDIT THIS ###
+
+CREATE_SUBDIRS = NO
+
+# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII
+# characters to appear in the names of generated files. If set to NO, non-ASCII
+# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode
+# U+3044.
+# The default value is: NO.
+
+#ALLOW_UNICODE_NAMES = NO
# The OUTPUT_LANGUAGE tag is used to specify the language in which all
# documentation generated by doxygen is written. Doxygen will use this
# information to generate all constant output in the proper language.
-# The default language is English, other supported languages are:
-# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
-# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
-# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
-# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
-# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak,
-# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
+# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,
+# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),
+# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,
+# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),
+# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,
+# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,
+# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,
+# Ukrainian and Vietnamese.
+# The default value is: English.
-OUTPUT_LANGUAGE = English
+OUTPUT_LANGUAGE = English
-# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
-# include brief member descriptions after the members that are listed in
-# the file and class documentation (similar to JavaDoc).
-# Set to NO to disable this.
+# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member
+# descriptions after the members that are listed in the file and class
+# documentation (similar to Javadoc). Set to NO to disable this.
+# The default value is: YES.
-BRIEF_MEMBER_DESC = YES
+BRIEF_MEMBER_DESC = YES
-# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
-# the brief description of a member or function before the detailed description.
-# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief
+# description of a member or function before the detailed description
+#
+# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
# brief descriptions will be completely suppressed.
+# The default value is: YES.
-REPEAT_BRIEF = YES
+REPEAT_BRIEF = YES
-# This tag implements a quasi-intelligent brief description abbreviator
-# that is used to form the text in various listings. Each string
-# in this list, if found as the leading text of the brief description, will be
-# stripped from the text and the result after processing the whole list, is
-# used as the annotated text. Otherwise, the brief description is used as-is.
-# If left blank, the following values are used ("$name" is automatically
-# replaced with the name of the entity): "The $name class" "The $name widget"
-# "The $name file" "is" "provides" "specifies" "contains"
-# "represents" "a" "an" "the"
+# This tag implements a quasi-intelligent brief description abbreviator that is
+# used to form the text in various listings. Each string in this list, if found
+# as the leading text of the brief description, will be stripped from the text
+# and the result, after processing the whole list, is used as the annotated
+# text. Otherwise, the brief description is used as-is. If left blank, the
+# following values are used ($name is automatically replaced with the name of
+# the entity):The $name class, The $name widget, The $name file, is, provides,
+# specifies, contains, represents, a, an and the.
-ABBREVIATE_BRIEF =
+ABBREVIATE_BRIEF =
# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
-# Doxygen will generate a detailed section even if there is only a brief
+# doxygen will generate a detailed section even if there is only a brief
# description.
+# The default value is: NO.
-ALWAYS_DETAILED_SEC = NO
+ALWAYS_DETAILED_SEC = NO
# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
# inherited members of a class in the documentation of that class as if those
# members were ordinary class members. Constructors, destructors and assignment
# operators of the base classes will not be shown.
+# The default value is: NO.
-INLINE_INHERITED_MEMB = NO
+INLINE_INHERITED_MEMB = NO
-# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
-# path before files name in the file list and in the header files. If set
-# to NO the shortest path that makes the file name unique will be used.
+# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path
+# before files name in the file list and in the header files. If set to NO the
+# shortest path that makes the file name unique will be used
+# The default value is: YES.
-FULL_PATH_NAMES = YES
+FULL_PATH_NAMES = YES
-# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
-# can be used to strip a user-defined part of the path. Stripping is
-# only done if one of the specified strings matches the left-hand part of
-# the path. The tag can be used to show relative paths in the file list.
-# If left blank the directory from which doxygen is run is used as the
-# path to strip. Note that you specify absolute paths here, but also
-# relative paths, which will be relative from the directory where doxygen is
-# started.
+# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.
+# Stripping is only done if one of the specified strings matches the left-hand
+# part of the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the path to
+# strip.
+#
+# Note that you can specify absolute paths here, but also relative paths, which
+# will be relative from the directory where doxygen is started.
+# This tag requires that the tag FULL_PATH_NAMES is set to YES.
-STRIP_FROM_PATH = ..
+STRIP_FROM_PATH = ..
-# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
-# the path mentioned in the documentation of a class, which tells
-# the reader which header file to include in order to use a class.
-# If left blank only the name of the header file containing the class
-# definition is used. Otherwise one should specify the include paths that
-# are normally passed to the compiler using the -I flag.
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the
+# path mentioned in the documentation of a class, which tells the reader which
+# header file to include in order to use a class. If left blank only the name of
+# the header file containing the class definition is used. Otherwise one should
+# specify the list of include paths that are normally passed to the compiler
+# using the -I flag.
-STRIP_FROM_INC_PATH =
+STRIP_FROM_INC_PATH =
-# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
-# (but less readable) file names. This can be useful if your file system
-# doesn't support long names like on DOS, Mac, or CD-ROM.
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but
+# less readable) file names. This can be useful is your file systems doesn't
+# support long names like on DOS, Mac, or CD-ROM.
+# The default value is: NO.
-SHORT_NAMES = NO
+SHORT_NAMES = NO
-# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
-# will interpret the first line (until the first dot) of a JavaDoc-style
-# comment as the brief description. If set to NO, the JavaDoc
-# comments will behave just like regular Qt-style comments
-# (thus requiring an explicit @brief command for a brief description.)
+# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the
+# first line (until the first dot) of a Javadoc-style comment as the brief
+# description. If set to NO, the Javadoc-style will behave just like regular Qt-
+# style comments (thus requiring an explicit @brief command for a brief
+# description.)
+# The default value is: NO.
-JAVADOC_AUTOBRIEF = NO
+JAVADOC_AUTOBRIEF = NO
-# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
-# interpret the first line (until the first dot) of a Qt-style
-# comment as the brief description. If set to NO, the comments
-# will behave just like regular Qt-style comments (thus requiring
-# an explicit \brief command for a brief description.)
+# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first
+# line (until the first dot) of a Qt-style comment as the brief description. If
+# set to NO, the Qt-style will behave just like regular Qt-style comments (thus
+# requiring an explicit \brief command for a brief description.)
+# The default value is: NO.
-QT_AUTOBRIEF = NO
+QT_AUTOBRIEF = NO
-# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
-# treat a multi-line C++ special comment block (i.e. a block of //! or ///
-# comments) as a brief description. This used to be the default behaviour.
-# The new default is to treat a multi-line C++ comment block as a detailed
-# description. Set this tag to YES if you prefer the old behaviour instead.
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a
+# multi-line C++ special comment block (i.e. a block of //! or /// comments) as
+# a brief description. This used to be the default behavior. The new default is
+# to treat a multi-line C++ comment block as a detailed description. Set this
+# tag to YES if you prefer the old behavior instead.
+#
+# Note that setting this tag to YES also means that rational rose comments are
+# not recognized any more.
+# The default value is: NO.
MULTILINE_CPP_IS_BRIEF = NO
-# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
-# member inherits the documentation from any documented member that it
-# re-implements.
+# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the
+# documentation from any documented member that it re-implements.
+# The default value is: YES.
-INHERIT_DOCS = YES
+INHERIT_DOCS = YES
-# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
-# a new page for each member. If set to NO, the documentation of a member will
-# be part of the file/class/namespace that contains it.
+# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new
+# page for each member. If set to NO, the documentation of a member will be part
+# of the file/class/namespace that contains it.
+# The default value is: NO.
-SEPARATE_MEMBER_PAGES = NO
+SEPARATE_MEMBER_PAGES = NO
-# The TAB_SIZE tag can be used to set the number of spaces in a tab.
-# Doxygen uses this value to replace tabs by spaces in code fragments.
+# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen
+# uses this value to replace tabs by spaces in code fragments.
+# Minimum value: 1, maximum value: 16, default value: 4.
-TAB_SIZE = 4
+TAB_SIZE = 4
-# This tag can be used to specify a number of aliases that acts
-# as commands in the documentation. An alias has the form "name=value".
-# For example adding "sideeffect=\par Side Effects:\n" will allow you to
-# put the command \sideeffect (or @sideeffect) in the documentation, which
-# will result in a user-defined paragraph with heading "Side Effects:".
-# You can put \n's in the value part of an alias to insert newlines.
-
-ALIASES = \
-tagGreenTick="@htmlonly
✔ @endhtmlonly" \
-tagRedCross="@htmlonly✖ @endhtmlonly" \
-linkProductSpecification52="[nRF52840 Product Specification](http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52/dita/nrf52/chips/nrf52840_ps.html) or [nRF52832 Product Specification](http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52/dita/nrf52/chips/nrf52832_ps.html)" \
+# This tag can be used to specify a number of aliases that act as commands in
+# the documentation. An alias has the form:
+# name=value
+# For example adding
+# "sideeffect=@par Side Effects:\n"
+# will allow you to put the command \sideeffect (or @sideeffect) in the
+# documentation, which will result in a user-defined paragraph with heading
+# "Side Effects:". You can put \n's in the value part of an alias to insert
+# newlines (in the resulting output). You can put ^^ in the value part of an
+# alias to insert a newline as if a physical newline was in the original file.
+ALIASES = "tagGreenTick=@htmlonly✔ @endhtmlonly" \
+ "tagRedCross=@htmlonly✖ @endhtmlonly" \
+ "linkProductSpecification52=[nRF52840 Product Specification](http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52/dita/nrf52/chips/nrf52840_ps.html) or [nRF52832 Product Specification](http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52/dita/nrf52/chips/nrf52832_ps.html)"
# This tag can be used to specify a number of word-keyword mappings (TCL only).
-# A mapping has the form "name=value". For example adding
-# "class=itcl::class" will allow you to use the command class in the
-# itcl::class meaning.
+# A mapping has the form "name=value". For example adding "class=itcl::class"
+# will allow you to use the command class in the itcl::class meaning.
-TCL_SUBST =
+TCL_SUBST =
-# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
-# sources only. Doxygen will then generate output that is more tailored for C.
-# For instance, some of the names that are used will be different. The list
-# of all members will be omitted, etc.
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources
+# only. Doxygen will then generate output that is more tailored for C. For
+# instance, some of the names that are used will be different. The list of all
+# members will be omitted, etc.
+# The default value is: NO.
-OPTIMIZE_OUTPUT_FOR_C = YES
+OPTIMIZE_OUTPUT_FOR_C = YES
-# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
-# sources only. Doxygen will then generate output that is more tailored for
-# Java. For instance, namespaces will be presented as packages, qualified
-# scopes will look different, etc.
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or
+# Python sources only. Doxygen will then generate output that is more tailored
+# for that language. For instance, namespaces will be presented as packages,
+# qualified scopes will look different, etc.
+# The default value is: NO.
-OPTIMIZE_OUTPUT_JAVA = NO
+OPTIMIZE_OUTPUT_JAVA = NO
# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
-# sources only. Doxygen will then generate output that is more tailored for
-# Fortran.
+# sources. Doxygen will then generate output that is tailored for Fortran.
+# The default value is: NO.
-OPTIMIZE_FOR_FORTRAN = NO
+OPTIMIZE_FOR_FORTRAN = NO
# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
-# sources. Doxygen will then generate output that is tailored for
-# VHDL.
+# sources. Doxygen will then generate output that is tailored for VHDL.
+# The default value is: NO.
-OPTIMIZE_OUTPUT_VHDL = NO
+OPTIMIZE_OUTPUT_VHDL = NO
# Doxygen selects the parser to use depending on the extension of the files it
# parses. With this tag you can assign which parser to use for a given
# extension. Doxygen has a built-in mapping, but you can override or extend it
-# using this tag. The format is ext=language, where ext is a file extension,
-# and language is one of the parsers supported by doxygen: IDL, Java,
-# Javascript, CSharp, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL, C,
-# C++. For instance to make doxygen treat .inc files as Fortran files (default
-# is PHP), and .f files as C (default is Fortran), use: inc=Fortran f=C. Note
-# that for custom extensions you also need to set FILE_PATTERNS otherwise the
-# files are not read by doxygen.
+# using this tag. The format is ext=language, where ext is a file extension, and
+# language is one of the parsers supported by doxygen: IDL, Java, Javascript,
+# C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran:
+# FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran:
+# Fortran. In the later case the parser tries to guess whether the code is fixed
+# or free formatted code, this is the default for Fortran type files), VHDL. For
+# instance to make doxygen treat .inc files as Fortran files (default is PHP),
+# and .f files as C (default is Fortran), use: inc=Fortran f=C.
+#
+# Note: For files without extension you can use no_extension as a placeholder.
+#
+# Note that for custom extensions you also need to set FILE_PATTERNS otherwise
+# the files are not read by doxygen.
-EXTENSION_MAPPING =
+EXTENSION_MAPPING =
-# If MARKDOWN_SUPPORT is enabled (the default) then doxygen pre-processes all
-# comments according to the Markdown format, which allows for more readable
+# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments
+# according to the Markdown format, which allows for more readable
# documentation. See http://daringfireball.net/projects/markdown/ for details.
-# The output of markdown processing is further processed by doxygen, so you
-# can mix doxygen, HTML, and XML commands with Markdown formatting.
-# Disable only in case of backward compatibilities issues.
+# The output of markdown processing is further processed by doxygen, so you can
+# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in
+# case of backward compatibilities issues.
+# The default value is: YES.
-MARKDOWN_SUPPORT = YES
+MARKDOWN_SUPPORT = YES
-# When enabled doxygen tries to link words that correspond to documented classes,
-# or namespaces to their corresponding documentation. Such a link can be
-# prevented in individual cases by by putting a % sign in front of the word or
+# When the TOC_INCLUDE_HEADINGS tag is set to a non-zero value, all headings up
+# to that level are automatically included in the table of contents, even if
+# they do not have an id attribute.
+# Note: This feature currently applies only to Markdown headings.
+# Minimum value: 0, maximum value: 99, default value: 0.
+# This tag requires that the tag MARKDOWN_SUPPORT is set to YES.
+
+#TOC_INCLUDE_HEADINGS = 0
+
+# When enabled doxygen tries to link words that correspond to documented
+# classes, or namespaces to their corresponding documentation. Such a link can
+# be prevented in individual cases by putting a % sign in front of the word or
# globally by setting AUTOLINK_SUPPORT to NO.
+# The default value is: YES.
-AUTOLINK_SUPPORT = YES
+AUTOLINK_SUPPORT = YES
# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
-# to include (a tag file for) the STL sources as input, then you should
-# set this tag to YES in order to let doxygen match functions declarations and
-# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
-# func(std::string) {}). This also makes the inheritance and collaboration
+# to include (a tag file for) the STL sources as input, then you should set this
+# tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string);
+# versus func(std::string) {}). This also make the inheritance and collaboration
# diagrams that involve STL classes more complete and accurate.
+# The default value is: NO.
-BUILTIN_STL_SUPPORT = NO
+BUILTIN_STL_SUPPORT = NO
# If you use Microsoft's C++/CLI language, you should set this option to YES to
# enable parsing support.
+# The default value is: NO.
-CPP_CLI_SUPPORT = NO
+CPP_CLI_SUPPORT = NO
-# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
-# Doxygen will parse them like normal C++ but will assume all classes use public
-# instead of private inheritance when no explicit protection keyword is present.
+# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:
+# https://www.riverbankcomputing.com/software/sip/intro) sources only. Doxygen
+# will parse them like normal C++ but will assume all classes use public instead
+# of private inheritance when no explicit protection keyword is present.
+# The default value is: NO.
-SIP_SUPPORT = NO
+SIP_SUPPORT = NO
# For Microsoft's IDL there are propget and propput attributes to indicate
-# getter and setter methods for a property. Setting this option to YES (the
-# default) will make doxygen replace the get and set methods by a property in
-# the documentation. This will only work if the methods are indeed getting or
-# setting a simple type. If this is not the case, or you want to show the
-# methods anyway, you should set this option to NO.
+# getter and setter methods for a property. Setting this option to YES will make
+# doxygen to replace the get and set methods by a property in the documentation.
+# This will only work if the methods are indeed getting or setting a simple
+# type. If this is not the case, or you want to show the methods anyway, you
+# should set this option to NO.
+# The default value is: YES.
-IDL_PROPERTY_SUPPORT = YES
+IDL_PROPERTY_SUPPORT = YES
# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
-# tag is set to YES, then doxygen will reuse the documentation of the first
+# tag is set to YES then doxygen will reuse the documentation of the first
# member in the group (if any) for the other members of the group. By default
# all members of a group must be documented explicitly.
+# The default value is: NO.
-DISTRIBUTE_GROUP_DOC = NO
+DISTRIBUTE_GROUP_DOC = NO
-# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
-# the same type (for instance a group of public functions) to be put as a
-# subgroup of that type (e.g. under the Public Functions section). Set it to
-# NO to prevent subgrouping. Alternatively, this can be done per class using
-# the \nosubgrouping command.
+# If one adds a struct or class to a group and this option is enabled, then also
+# any nested class or struct is added to the same group. By default this option
+# is disabled and one has to add nested compounds explicitly via \ingroup.
+# The default value is: NO.
-SUBGROUPING = YES
+#GROUP_NESTED_COMPOUNDS = NO
-# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and
-# unions are shown inside the group in which they are included (e.g. using
-# @ingroup) instead of on a separate page (for HTML and Man pages) or
-# section (for LaTeX and RTF).
+# Set the SUBGROUPING tag to YES to allow class member groups of the same type
+# (for instance a group of public functions) to be put as a subgroup of that
+# type (e.g. under the Public Functions section). Set it to NO to prevent
+# subgrouping. Alternatively, this can be done per class using the
+# \nosubgrouping command.
+# The default value is: YES.
+
+SUBGROUPING = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions
+# are shown inside the group in which they are included (e.g. using \ingroup)
+# instead of on a separate page (for HTML and Man pages) or section (for LaTeX
+# and RTF).
+#
+# Note that this feature does not work in combination with
+# SEPARATE_MEMBER_PAGES.
+# The default value is: NO.
INLINE_GROUPED_CLASSES = NO
-# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and
-# unions with only public data fields will be shown inline in the documentation
-# of the scope in which they are defined (i.e. file, namespace, or group
-# documentation), provided this scope is documented. If set to NO (the default),
-# structs, classes, and unions are shown on a separate page (for HTML and Man
-# pages) or section (for LaTeX and RTF).
+# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions
+# with only public data fields or simple typedef fields will be shown inline in
+# the documentation of the scope in which they are defined (i.e. file,
+# namespace, or group documentation), provided this scope is documented. If set
+# to NO, structs, classes, and unions are shown on a separate page (for HTML and
+# Man pages) or section (for LaTeX and RTF).
+# The default value is: NO.
-INLINE_SIMPLE_STRUCTS = NO
+INLINE_SIMPLE_STRUCTS = NO
-# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
-# is documented as struct, union, or enum with the name of the typedef. So
+# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or
+# enum is documented as struct, union, or enum with the name of the typedef. So
# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
# with name TypeT. When disabled the typedef will appear as a member of a file,
-# namespace, or class. And the struct will be named TypeS. This can typically
-# be useful for C code in case the coding convention dictates that all compound
+# namespace, or class. And the struct will be named TypeS. This can typically be
+# useful for C code in case the coding convention dictates that all compound
# types are typedef'ed and only the typedef is referenced, never the tag name.
+# The default value is: NO.
-TYPEDEF_HIDES_STRUCT = NO
+TYPEDEF_HIDES_STRUCT = NO
-# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
-# determine which symbols to keep in memory and which to flush to disk.
-# When the cache is full, less often used symbols will be written to disk.
-# For small to medium size projects (<1000 input files) the default value is
-# probably good enough. For larger projects a too small cache size can cause
-# doxygen to be busy swapping symbols to and from disk most of the time
-# causing a significant performance penalty.
-# If the system has enough physical memory increasing the cache will improve the
-# performance by keeping more symbols in memory. Note that the value works on
-# a logarithmic scale so increasing the size by one will roughly double the
-# memory usage. The cache size is given by this formula:
-# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
-# corresponding to a cache size of 2^16 = 65536 symbols.
+# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This
+# cache is used to resolve symbols given their name and scope. Since this can be
+# an expensive process and often the same symbol appears multiple times in the
+# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small
+# doxygen will become slower. If the cache is too large, memory is wasted. The
+# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range
+# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536
+# symbols. At the end of a run doxygen will report the cache usage and suggest
+# the optimal cache size from a speed point of view.
+# Minimum value: 0, maximum value: 9, default value: 0.
-SYMBOL_CACHE_SIZE = 0
-
-# Similar to the SYMBOL_CACHE_SIZE the size of the symbol lookup cache can be
-# set using LOOKUP_CACHE_SIZE. This cache is used to resolve symbols given
-# their name and scope. Since this can be an expensive process and often the
-# same symbol appear multiple times in the code, doxygen keeps a cache of
-# pre-resolved symbols. If the cache is too small doxygen will become slower.
-# If the cache is too large, memory is wasted. The cache size is given by this
-# formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range is 0..9, the default is 0,
-# corresponding to a cache size of 2^16 = 65536 symbols.
-
-LOOKUP_CACHE_SIZE = 0
+LOOKUP_CACHE_SIZE = 0
#---------------------------------------------------------------------------
# Build related configuration options
#---------------------------------------------------------------------------
-# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
-# documentation are documented, even if no documentation was available.
-# Private class members and static file members will be hidden unless
-# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in
+# documentation are documented, even if no documentation was available. Private
+# class members and static file members will be hidden unless the
+# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.
+# Note: This will also disable the warnings about undocumented members that are
+# normally produced when WARNINGS is set to YES.
+# The default value is: NO.
-EXTRACT_ALL = NO
+EXTRACT_ALL = NO
-# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
-# will be included in the documentation.
+# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will
+# be included in the documentation.
+# The default value is: NO.
-EXTRACT_PRIVATE = NO
+EXTRACT_PRIVATE = NO
-# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal
+# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal
# scope will be included in the documentation.
+# The default value is: NO.
-EXTRACT_PACKAGE = NO
+EXTRACT_PACKAGE = NO
-# If the EXTRACT_STATIC tag is set to YES all static members of a file
-# will be included in the documentation.
+# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be
+# included in the documentation.
+# The default value is: NO.
-EXTRACT_STATIC = YES
+EXTRACT_STATIC = YES
-# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
-# defined locally in source files will be included in the documentation.
-# If set to NO only classes defined in header files are included.
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined
+# locally in source files will be included in the documentation. If set to NO,
+# only classes defined in header files are included. Does not have any effect
+# for Java sources.
+# The default value is: YES.
-EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_CLASSES = YES
-# This flag is only useful for Objective-C code. When set to YES local
-# methods, which are defined in the implementation section but not in
-# the interface are included in the documentation.
-# If set to NO (the default) only methods in the interface are included.
+# This flag is only useful for Objective-C code. If set to YES, local methods,
+# which are defined in the implementation section but not in the interface are
+# included in the documentation. If set to NO, only methods in the interface are
+# included.
+# The default value is: NO.
-EXTRACT_LOCAL_METHODS = NO
+EXTRACT_LOCAL_METHODS = NO
# If this flag is set to YES, the members of anonymous namespaces will be
# extracted and appear in the documentation as a namespace called
-# 'anonymous_namespace{file}', where file will be replaced with the base
-# name of the file that contains the anonymous namespace. By default
-# anonymous namespaces are hidden.
+# 'anonymous_namespace{file}', where file will be replaced with the base name of
+# the file that contains the anonymous namespace. By default anonymous namespace
+# are hidden.
+# The default value is: NO.
-EXTRACT_ANON_NSPACES = NO
+EXTRACT_ANON_NSPACES = NO
-# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
-# undocumented members of documented classes, files or namespaces.
-# If set to NO (the default) these members will be included in the
-# various overviews, but no documentation section is generated.
-# This option has no effect if EXTRACT_ALL is enabled.
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all
+# undocumented members inside documented classes or files. If set to NO these
+# members will be included in the various overviews, but no documentation
+# section is generated. This option has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
-HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_MEMBERS = NO
-# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
-# undocumented classes that are normally visible in the class hierarchy.
-# If set to NO (the default) these classes will be included in the various
-# overviews. This option has no effect if EXTRACT_ALL is enabled.
+# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy. If set
+# to NO, these classes will be included in the various overviews. This option
+# has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
-HIDE_UNDOC_CLASSES = NO
+HIDE_UNDOC_CLASSES = NO
-# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
-# friend (class|struct|union) declarations.
-# If set to NO (the default) these declarations will be included in the
-# documentation.
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend
+# (class|struct|union) declarations. If set to NO, these declarations will be
+# included in the documentation.
+# The default value is: NO.
-HIDE_FRIEND_COMPOUNDS = NO
+HIDE_FRIEND_COMPOUNDS = NO
-# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
-# documentation blocks found inside the body of a function.
-# If set to NO (the default) these blocks will be appended to the
-# function's detailed documentation block.
+# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any
+# documentation blocks found inside the body of a function. If set to NO, these
+# blocks will be appended to the function's detailed documentation block.
+# The default value is: NO.
-HIDE_IN_BODY_DOCS = NO
+HIDE_IN_BODY_DOCS = NO
-# The INTERNAL_DOCS tag determines if documentation
-# that is typed after a \internal command is included. If the tag is set
-# to NO (the default) then the documentation will be excluded.
-# Set it to YES to include the internal documentation.
+# The INTERNAL_DOCS tag determines if documentation that is typed after a
+# \internal command is included. If the tag is set to NO then the documentation
+# will be excluded. Set it to YES to include the internal documentation.
+# The default value is: NO.
-INTERNAL_DOCS = NO
+INTERNAL_DOCS = NO
-# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
-# file names in lower-case letters. If set to YES upper-case letters are also
+# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file
+# names in lower-case letters. If set to YES, upper-case letters are also
# allowed. This is useful if you have classes or files whose names only differ
# in case and if your file system supports case sensitive file names. Windows
# and Mac users are advised to set this option to NO.
+# The default value is: system dependent.
-CASE_SENSE_NAMES = NO
+CASE_SENSE_NAMES = NO
-# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
-# will show members with their full class and namespace scopes in the
-# documentation. If set to YES the scope will be hidden.
+# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with
+# their full class and namespace scopes in the documentation. If set to YES, the
+# scope will be hidden.
+# The default value is: NO.
-HIDE_SCOPE_NAMES = NO
+HIDE_SCOPE_NAMES = NO
-# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
-# will put a list of the files that are included by a file in the documentation
-# of that file.
+# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will
+# append additional text to a page's title, such as Class Reference. If set to
+# YES the compound reference will be hidden.
+# The default value is: NO.
-SHOW_INCLUDE_FILES = YES
+#HIDE_COMPOUND_REFERENCE= NO
-# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
-# will list include files with double quotes in the documentation
-# rather than with sharp brackets.
+# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of
+# the files that are included by a file in the documentation of that file.
+# The default value is: YES.
-FORCE_LOCAL_INCLUDES = NO
+SHOW_INCLUDE_FILES = YES
-# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
-# is inserted in the documentation for inline members.
+# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each
+# grouped member an include statement to the documentation, telling the reader
+# which file to include in order to use the member.
+# The default value is: NO.
-INLINE_INFO = YES
+#SHOW_GROUPED_MEMB_INC = NO
-# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
-# will sort the (detailed) documentation of file and class members
-# alphabetically by member name. If set to NO the members will appear in
-# declaration order.
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include
+# files with double quotes in the documentation rather than with sharp brackets.
+# The default value is: NO.
-SORT_MEMBER_DOCS = YES
+FORCE_LOCAL_INCLUDES = NO
-# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
-# brief documentation of file, namespace and class members alphabetically
-# by member name. If set to NO (the default) the members will appear in
-# declaration order.
+# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the
+# documentation for inline members.
+# The default value is: YES.
-SORT_BRIEF_DOCS = NO
+INLINE_INFO = YES
-# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen
-# will sort the (brief and detailed) documentation of class members so that
-# constructors and destructors are listed first. If set to NO (the default)
-# the constructors will appear in the respective orders defined by
-# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS.
-# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO
-# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
+# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the
+# (detailed) documentation of file and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order.
+# The default value is: YES.
+
+SORT_MEMBER_DOCS = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief
+# descriptions of file, namespace and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order. Note that
+# this will also influence the order of the classes in the class list.
+# The default value is: NO.
+
+SORT_BRIEF_DOCS = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the
+# (brief and detailed) documentation of class members so that constructors and
+# destructors are listed first. If set to NO the constructors will appear in the
+# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.
+# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief
+# member documentation.
+# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting
+# detailed member documentation.
+# The default value is: NO.
SORT_MEMBERS_CTORS_1ST = NO
-# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
-# hierarchy of group names into alphabetical order. If set to NO (the default)
-# the group names will appear in their defined order.
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy
+# of group names into alphabetical order. If set to NO the group names will
+# appear in their defined order.
+# The default value is: NO.
-SORT_GROUP_NAMES = NO
+SORT_GROUP_NAMES = NO
-# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
-# sorted by fully-qualified names, including namespaces. If set to
-# NO (the default), the class list will be sorted only by class name,
-# not including the namespace part.
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by
+# fully-qualified names, including namespaces. If set to NO, the class list will
+# be sorted only by class name, not including the namespace part.
# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
-# Note: This option applies only to the class list, not to the
-# alphabetical list.
+# Note: This option applies only to the class list, not to the alphabetical
+# list.
+# The default value is: NO.
-SORT_BY_SCOPE_NAME = NO
+SORT_BY_SCOPE_NAME = NO
-# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to
-# do proper type resolution of all parameters of a function it will reject a
-# match between the prototype and the implementation of a member function even
-# if there is only one candidate or it is obvious which candidate to choose
-# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen
-# will still accept a match between prototype and implementation in such cases.
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper
+# type resolution of all parameters of a function it will reject a match between
+# the prototype and the implementation of a member function even if there is
+# only one candidate or it is obvious which candidate to choose by doing a
+# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still
+# accept a match between prototype and implementation in such cases.
+# The default value is: NO.
-STRICT_PROTO_MATCHING = NO
+STRICT_PROTO_MATCHING = NO
-# The GENERATE_TODOLIST tag can be used to enable (YES) or
-# disable (NO) the todo list. This list is created by putting \todo
-# commands in the documentation.
+# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo
+# list. This list is created by putting \todo commands in the documentation.
+# The default value is: YES.
-GENERATE_TODOLIST = YES
+GENERATE_TODOLIST = YES
-# The GENERATE_TESTLIST tag can be used to enable (YES) or
-# disable (NO) the test list. This list is created by putting \test
-# commands in the documentation.
+# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test
+# list. This list is created by putting \test commands in the documentation.
+# The default value is: YES.
-GENERATE_TESTLIST = YES
+GENERATE_TESTLIST = YES
-# The GENERATE_BUGLIST tag can be used to enable (YES) or
-# disable (NO) the bug list. This list is created by putting \bug
-# commands in the documentation.
+# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug
+# list. This list is created by putting \bug commands in the documentation.
+# The default value is: YES.
-GENERATE_BUGLIST = YES
+GENERATE_BUGLIST = YES
-# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
-# disable (NO) the deprecated list. This list is created by putting
-# \deprecated commands in the documentation.
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO)
+# the deprecated list. This list is created by putting \deprecated commands in
+# the documentation.
+# The default value is: YES.
-GENERATE_DEPRECATEDLIST = YES
+GENERATE_DEPRECATEDLIST= YES
-# The ENABLED_SECTIONS tag can be used to enable conditional
-# documentation sections, marked by \if section-label ... \endif
-# and \cond section-label ... \endcond blocks.
+# The ENABLED_SECTIONS tag can be used to enable conditional documentation
+# sections, marked by \if ... \endif and \cond
+# ... \endcond blocks.
-ENABLED_SECTIONS =
+ENABLED_SECTIONS =
-# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
-# the initial value of a variable or macro consists of for it to appear in
-# the documentation. If the initializer consists of more lines than specified
-# here it will be hidden. Use a value of 0 to hide initializers completely.
-# The appearance of the initializer of individual variables and macros in the
-# documentation can be controlled using \showinitializer or \hideinitializer
-# command in the documentation regardless of this setting.
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the
+# initial value of a variable or macro / define can have for it to appear in the
+# documentation. If the initializer consists of more lines than specified here
+# it will be hidden. Use a value of 0 to hide initializers completely. The
+# appearance of the value of individual variables and macros / defines can be
+# controlled using \showinitializer or \hideinitializer command in the
+# documentation regardless of this setting.
+# Minimum value: 0, maximum value: 10000, default value: 30.
-MAX_INITIALIZER_LINES = 30
+MAX_INITIALIZER_LINES = 30
-# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
-# at the bottom of the documentation of classes and structs. If set to YES the
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at
+# the bottom of the documentation of classes and structs. If set to YES, the
# list will mention the files that were used to generate the documentation.
+# The default value is: YES.
-SHOW_USED_FILES = YES
+SHOW_USED_FILES = YES
-# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
-# This will remove the Files entry from the Quick Index and from the
-# Folder Tree View (if specified). The default is YES.
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This
+# will remove the Files entry from the Quick Index and from the Folder Tree View
+# (if specified).
+# The default value is: YES.
-SHOW_FILES = NO
+SHOW_FILES = NO
-# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
-# Namespaces page.
-# This will remove the Namespaces entry from the Quick Index
-# and from the Folder Tree View (if specified). The default is YES.
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces
+# page. This will remove the Namespaces entry from the Quick Index and from the
+# Folder Tree View (if specified).
+# The default value is: YES.
-SHOW_NAMESPACES = YES
+SHOW_NAMESPACES = YES
# The FILE_VERSION_FILTER tag can be used to specify a program or script that
# doxygen should invoke to get the current version for each file (typically from
# the version control system). Doxygen will invoke the program by executing (via
-# popen()) the command , where is the value of
-# the FILE_VERSION_FILTER tag, and is the name of an input file
-# provided by doxygen. Whatever the program writes to standard output
-# is used as the file version. See the manual for examples.
+# popen()) the command command input-file, where command is the value of the
+# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided
+# by doxygen. Whatever the program writes to standard output is used as the file
+# version. For an example see the documentation.
-FILE_VERSION_FILTER =
+FILE_VERSION_FILTER =
# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
# by doxygen. The layout file controls the global structure of the generated
# output files in an output format independent way. To create the layout file
-# that represents doxygen's defaults, run doxygen with the -l option.
-# You can optionally specify a file name after the option, if omitted
-# DoxygenLayout.xml will be used as the name of the layout file.
+# that represents doxygen's defaults, run doxygen with the -l option. You can
+# optionally specify a file name after the option, if omitted DoxygenLayout.xml
+# will be used as the name of the layout file.
+#
+# Note that if you run doxygen from a directory containing a file called
+# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE
+# tag is left empty.
-LAYOUT_FILE = buildfiles/layout.xml
+LAYOUT_FILE = buildfiles/layout.xml
-# The CITE_BIB_FILES tag can be used to specify one or more bib files
-# containing the references data. This must be a list of .bib files. The
-# .bib extension is automatically appended if omitted. Using this command
-# requires the bibtex tool to be installed. See also
-# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style
-# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this
-# feature you need bibtex and perl available in the search path. Do not use
-# file names with spaces, bibtex cannot handle them.
+# The CITE_BIB_FILES tag can be used to specify one or more bib files containing
+# the reference definitions. This must be a list of .bib files. The .bib
+# extension is automatically appended if omitted. This requires the bibtex tool
+# to be installed. See also https://en.wikipedia.org/wiki/BibTeX for more info.
+# For LaTeX the style of the bibliography can be controlled using
+# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the
+# search path. See also \cite for info how to create references.
-CITE_BIB_FILES =
+CITE_BIB_FILES =
#---------------------------------------------------------------------------
-# configuration options related to warning and progress messages
+# Configuration options related to warning and progress messages
#---------------------------------------------------------------------------
-# The QUIET tag can be used to turn on/off the messages that are generated
-# by doxygen. Possible values are YES and NO. If left blank NO is used.
+# The QUIET tag can be used to turn on/off the messages that are generated to
+# standard output by doxygen. If QUIET is set to YES this implies that the
+# messages are off.
+# The default value is: NO.
-QUIET = YES
+QUIET = YES
# The WARNINGS tag can be used to turn on/off the warning messages that are
-# generated by doxygen. Possible values are YES and NO. If left blank
-# NO is used.
+# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES
+# this implies that the warnings are on.
+#
+# Tip: Turn warnings on while writing the documentation.
+# The default value is: YES.
-WARNINGS = YES
+WARNINGS = YES
-# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
-# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
-# automatically be disabled.
+# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate
+# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag
+# will automatically be disabled.
+# The default value is: YES.
-WARN_IF_UNDOCUMENTED = NO
+WARN_IF_UNDOCUMENTED = YES
-# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
-# potential errors in the documentation, such as not documenting some
-# parameters in a documented function, or documenting parameters that
-# don't exist or using markup commands wrongly.
+# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some parameters
+# in a documented function, or documenting parameters that don't exist or using
+# markup commands wrongly.
+# The default value is: YES.
-WARN_IF_DOC_ERROR = YES
+WARN_IF_DOC_ERROR = YES
-# The WARN_NO_PARAMDOC option can be enabled to get warnings for
-# functions that are documented, but have no documentation for their parameters
-# or return value. If set to NO (the default) doxygen will only warn about
-# wrong or incomplete parameter documentation, but not about the absence of
-# documentation.
+# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that
+# are documented, but have no documentation for their parameters or return
+# value. If set to NO, doxygen will only warn about wrong or incomplete
+# parameter documentation, but not about the absence of documentation.
+# The default value is: NO.
-WARN_NO_PARAMDOC = NO
+WARN_NO_PARAMDOC = NO
-# The WARN_FORMAT tag determines the format of the warning messages that
-# doxygen can produce. The string should contain the $file, $line, and $text
-# tags, which will be replaced by the file and line number from which the
-# warning originated and the warning text. Optionally the format may contain
-# $version, which will be replaced by the version of the file (if it could
-# be obtained via FILE_VERSION_FILTER)
+# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when
+# a warning is encountered.
+# The default value is: NO.
-WARN_FORMAT = "$file:$line: $text"
+#WARN_AS_ERROR = NO
-# The WARN_LOGFILE tag can be used to specify a file to which warning
-# and error messages should be written. If left blank the output is written
-# to stderr.
+# The WARN_FORMAT tag determines the format of the warning messages that doxygen
+# can produce. The string should contain the $file, $line, and $text tags, which
+# will be replaced by the file and line number from which the warning originated
+# and the warning text. Optionally the format may contain $version, which will
+# be replaced by the version of the file (if it could be obtained via
+# FILE_VERSION_FILTER)
+# The default value is: $file:$line: $text.
+
+WARN_FORMAT = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning and error
+# messages should be written. If left blank the output is written to standard
+# error (stderr).
+
+WARN_LOGFILE = warnings_nrfx.txt
+
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag is used to specify the files and/or directories that contain
+# documented source files. You may enter file names like myfile.cpp or
+# directories like /usr/src/myproject. Separate the files or directories with
+# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING
+# Note: If this tag is empty the current directory is searched.
-WARN_LOGFILE = warnings_nrfx.txt
### EDIT THIS ###
-#---------------------------------------------------------------------------
-# configuration options related to the input files
-#---------------------------------------------------------------------------
-
-# The INPUT tag can be used to specify the files and/or directories that contain
-# documented source files. You may enter file names like "myfile.cpp" or
-# directories like "/usr/src/myproject". Separate the files or directories
-# with spaces.
-
-INPUT = ../drivers \
- ../hal \
- ../soc \
- ../templates \
- config_dox \
- .
+INPUT = ../helpers \
+ ../drivers \
+ ../hal \
+ ../soc \
+ ../templates \
+ config_dox \
+ .
# This tag can be used to specify the character encoding of the source files
-# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
-# also the default input encoding. Doxygen uses libiconv (or the iconv built
-# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
-# the list of possible encodings.
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses
+# libiconv (or the iconv built into libc) for the transcoding. See the libiconv
+# documentation (see: https://www.gnu.org/software/libiconv/) for the list of
+# possible encodings.
+# The default value is: UTF-8.
-INPUT_ENCODING = UTF-8
+INPUT_ENCODING = UTF-8
# If the value of the INPUT tag contains directories, you can use the
-# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
-# and *.h) to filter out the source-files in the directories. If left
-# blank the following patterns are tested:
-# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh
-# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py
-# *.f90 *.f *.for *.vhd *.vhdl
+# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and
+# *.h) to filter out the source-files in the directories.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# read by doxygen.
+#
+# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp,
+# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h,
+# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc,
+# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f95, *.f03, *.f08,
+# *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf and *.qsf.
-FILE_PATTERNS = *.h *.dox
+FILE_PATTERNS = *.h \
+ *.dox
-# The RECURSIVE tag can be used to turn specify whether or not subdirectories
-# should be searched for input files as well. Possible values are YES and NO.
-# If left blank NO is used.
+# The RECURSIVE tag can be used to specify whether or not subdirectories should
+# be searched for input files as well.
+# The default value is: NO.
-RECURSIVE = YES
+RECURSIVE = YES
# The EXCLUDE tag can be used to specify files and/or directories that should be
# excluded from the INPUT source files. This way you can easily exclude a
# subdirectory from a directory tree whose root is specified with the INPUT tag.
+#
# Note that relative paths are relative to the directory from which doxygen is
# run.
-EXCLUDE = # DO NOT ADD ANYTHING HERE - DEFINED IN SEPARATE FILE
+EXCLUDE =
# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
# directories that are symbolic links (a Unix file system feature) are excluded
# from the input.
+# The default value is: NO.
-EXCLUDE_SYMLINKS = NO
+EXCLUDE_SYMLINKS = NO
# If the value of the INPUT tag contains directories, you can use the
# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
-# certain files from those directories. Note that the wildcards are matched
-# against the file with absolute path, so to exclude all test directories
-# for example use the pattern */test/*
+# certain files from those directories.
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories for example use the pattern */test/*
-EXCLUDE_PATTERNS =
+EXCLUDE_PATTERNS =
# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
# (namespaces, classes, functions, etc.) that should be excluded from the
# output. The symbol name can be a fully qualified name, a word, or if the
# wildcard * is used, a substring. Examples: ANamespace, AClass,
# AClass::ANamespace, ANamespace::*Test
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories use the pattern */test/*
-EXCLUDE_SYMBOLS =
+EXCLUDE_SYMBOLS =
-# The EXAMPLE_PATH tag can be used to specify one or more files or
-# directories that contain example code fragments that are included (see
-# the \include command).
+# The EXAMPLE_PATH tag can be used to specify one or more files or directories
+# that contain example code fragments that are included (see the \include
+# command).
-EXAMPLE_PATH = # DO NOT ADD ANYTHING HERE - DEFINED IN SEPARATE FILE
+EXAMPLE_PATH =
# If the value of the EXAMPLE_PATH tag contains directories, you can use the
-# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
-# and *.h) to filter out the source-files in the directories. If left
-# blank all files are included.
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and
+# *.h) to filter out the source-files in the directories. If left blank all
+# files are included.
-EXAMPLE_PATTERNS =
+EXAMPLE_PATTERNS =
# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
-# searched for input files to be used with the \include or \dontinclude
-# commands irrespective of the value of the RECURSIVE tag.
-# Possible values are YES and NO. If left blank NO is used.
+# searched for input files to be used with the \include or \dontinclude commands
+# irrespective of the value of the RECURSIVE tag.
+# The default value is: NO.
-EXAMPLE_RECURSIVE = NO
+EXAMPLE_RECURSIVE = NO
-# The IMAGE_PATH tag can be used to specify one or more files or
-# directories that contain image that are included in the documentation (see
-# the \image command).
+# The IMAGE_PATH tag can be used to specify one or more files or directories
+# that contain images that are to be included in the documentation (see the
+# \image command).
-IMAGE_PATH =
+IMAGE_PATH =
# The INPUT_FILTER tag can be used to specify a program that doxygen should
# invoke to filter for each input file. Doxygen will invoke the filter program
-# by executing (via popen()) the command , where
-# is the value of the INPUT_FILTER tag, and is the name of an
-# input file. Doxygen will then use the output that the filter program writes
-# to standard output.
-# If FILTER_PATTERNS is specified, this tag will be
-# ignored.
+# by executing (via popen()) the command:
+#
+#
+#
+# where is the value of the INPUT_FILTER tag, and is the
+# name of an input file. Doxygen will then use the output that the filter
+# program writes to standard output. If FILTER_PATTERNS is specified, this tag
+# will be ignored.
+#
+# Note that the filter must not add or remove lines; it is applied before the
+# code is scanned, but not when the output code is generated. If lines are added
+# or removed, the anchors will not be placed correctly.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
-INPUT_FILTER =
+INPUT_FILTER =
# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
-# basis.
-# Doxygen will compare the file name with each pattern and apply the
-# filter if there is a match.
-# The filters are a list of the form:
-# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
-# info on how filters are used. If FILTER_PATTERNS is empty or if
-# non of the patterns match the file name, INPUT_FILTER is applied.
+# basis. Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match. The filters are a list of the form: pattern=filter
+# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how
+# filters are used. If the FILTER_PATTERNS tag is empty or if none of the
+# patterns match the file name, INPUT_FILTER is applied.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
-FILTER_PATTERNS =
+FILTER_PATTERNS =
# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
-# INPUT_FILTER) will be used to filter the input files when producing source
-# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+# INPUT_FILTER) will also be used to filter the input files that are used for
+# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).
+# The default value is: NO.
-FILTER_SOURCE_FILES = NO
+FILTER_SOURCE_FILES = NO
# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
-# pattern. A pattern will override the setting for FILTER_PATTERN (if any)
-# and it is also possible to disable source filtering for a specific pattern
-# using *.ext= (so without naming a filter). This option only has effect when
-# FILTER_SOURCE_FILES is enabled.
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and
+# it is also possible to disable source filtering for a specific pattern using
+# *.ext= (so without naming a filter).
+# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.
FILTER_SOURCE_PATTERNS =
-# If the USE_MD_FILE_AS_MAINPAGE tag refers to the name of a markdown file that
-# is part of the input, its contents will be placed on the main page (index.html).
-# This can be useful if you have a project on for instance GitHub and want reuse
-# the introduction page also for the doxygen output.
+# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that
+# is part of the input, its contents will be placed on the main page
+# (index.html). This can be useful if you have a project on for instance GitHub
+# and want to reuse the introduction page also for the doxygen output.
USE_MDFILE_AS_MAINPAGE =
#---------------------------------------------------------------------------
-# configuration options related to source browsing
+# Configuration options related to source browsing
#---------------------------------------------------------------------------
-# If the SOURCE_BROWSER tag is set to YES then a list of source files will
-# be generated. Documented entities will be cross-referenced with these sources.
-# Note: To get rid of all source code in the generated output, make sure also
-# VERBATIM_HEADERS is set to NO.
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will be
+# generated. Documented entities will be cross-referenced with these sources.
+#
+# Note: To get rid of all source code in the generated output, make sure that
+# also VERBATIM_HEADERS is set to NO.
+# The default value is: NO.
-SOURCE_BROWSER = NO
+SOURCE_BROWSER = NO
-# Setting the INLINE_SOURCES tag to YES will include the body
-# of functions and classes directly in the documentation.
+# Setting the INLINE_SOURCES tag to YES will include the body of functions,
+# classes and enums directly into the documentation.
+# The default value is: NO.
-INLINE_SOURCES = NO
+INLINE_SOURCES = NO
-# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
-# doxygen to hide any special comment blocks from generated source code
-# fragments. Normal C, C++ and Fortran comments will always remain visible.
+# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any
+# special comment blocks from generated source code fragments. Normal C, C++ and
+# Fortran comments will always remain visible.
+# The default value is: YES.
-STRIP_CODE_COMMENTS = NO
+STRIP_CODE_COMMENTS = NO
-# If the REFERENCED_BY_RELATION tag is set to YES
-# then for each documented function all documented
-# functions referencing it will be listed.
+# If the REFERENCED_BY_RELATION tag is set to YES then for each documented
+# function all documented functions referencing it will be listed.
+# The default value is: NO.
REFERENCED_BY_RELATION = NO
-# If the REFERENCES_RELATION tag is set to YES
-# then for each documented function all documented entities
-# called/used by that function will be listed.
+# If the REFERENCES_RELATION tag is set to YES then for each documented function
+# all documented entities called/used by that function will be listed.
+# The default value is: NO.
-REFERENCES_RELATION = NO
+REFERENCES_RELATION = NO
-# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
-# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
-# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
-# link to the source code.
-# Otherwise they will link to the documentation.
+# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set
+# to YES then the hyperlinks from functions in REFERENCES_RELATION and
+# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will
+# link to the documentation.
+# The default value is: YES.
REFERENCES_LINK_SOURCE = YES
-# If the USE_HTAGS tag is set to YES then the references to source code
-# will point to the HTML generated by the htags(1) tool instead of doxygen
-# built-in source browser. The htags tool is part of GNU's global source
-# tagging system (see http://www.gnu.org/software/global/global.html). You
-# will need version 4.8.6 or higher.
+# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the
+# source code will show a tooltip with additional information such as prototype,
+# brief description and links to the definition and documentation. Since this
+# will make the HTML file larger and loading of large files a bit slower, you
+# can opt to disable this feature.
+# The default value is: YES.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
-USE_HTAGS = NO
+#SOURCE_TOOLTIPS = YES
-# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
-# will generate a verbatim copy of the header file for each class for
-# which an include is specified. Set to NO to disable this.
+# If the USE_HTAGS tag is set to YES then the references to source code will
+# point to the HTML generated by the htags(1) tool instead of doxygen built-in
+# source browser. The htags tool is part of GNU's global source tagging system
+# (see https://www.gnu.org/software/global/global.html). You will need version
+# 4.8.6 or higher.
+#
+# To use it do the following:
+# - Install the latest version of global
+# - Enable SOURCE_BROWSER and USE_HTAGS in the config file
+# - Make sure the INPUT points to the root of the source tree
+# - Run doxygen as normal
+#
+# Doxygen will invoke htags (and that will in turn invoke gtags), so these
+# tools must be available from the command line (i.e. in the search path).
+#
+# The result: instead of the source browser generated by doxygen, the links to
+# source code will now point to the output of htags.
+# The default value is: NO.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
-VERBATIM_HEADERS = NO
+USE_HTAGS = NO
+
+# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a
+# verbatim copy of the header file for each class for which an include is
+# specified. Set to NO to disable this.
+# See also: Section \class.
+# The default value is: YES.
+
+VERBATIM_HEADERS = NO
+
+# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the
+# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the
+# cost of reduced performance. This can be particularly helpful with template
+# rich C++ code for which doxygen's built-in parser lacks the necessary type
+# information.
+# Note: The availability of this option depends on whether or not doxygen was
+# generated with the -Duse-libclang=ON option for CMake.
+# The default value is: NO.
+
+#CLANG_ASSISTED_PARSING = NO
+
+# If clang assisted parsing is enabled you can provide the compiler with command
+# line options that you would normally use when invoking the compiler. Note that
+# the include paths will already be set by doxygen for the files and directories
+# specified with INPUT and INCLUDE_PATH.
+# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
+
+#CLANG_OPTIONS =
+
+# If clang assisted parsing is enabled you can provide the clang parser with the
+# path to the compilation database (see:
+# http://clang.llvm.org/docs/HowToSetupToolingForLLVM.html) used when the files
+# were built. This is equivalent to specifying the "-p" option to a clang tool,
+# such as clang-check. These options will then be passed to the parser.
+# Note: The availability of this option depends on whether or not doxygen was
+# generated with the -Duse-libclang=ON option for CMake.
+# The default value is: 0.
+
+#CLANG_COMPILATION_DATABASE_PATH = 0
#---------------------------------------------------------------------------
-# configuration options related to the alphabetical class index
+# Configuration options related to the alphabetical class index
#---------------------------------------------------------------------------
-# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
-# of all compounds will be generated. Enable this if the project
-# contains a lot of classes, structs, unions or interfaces.
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all
+# compounds will be generated. Enable this if the project contains a lot of
+# classes, structs, unions or interfaces.
+# The default value is: YES.
-ALPHABETICAL_INDEX = NO
+ALPHABETICAL_INDEX = NO
-# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
-# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
-# in which this list will be split (can be a number in the range [1..20])
+# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in
+# which the alphabetical index list will be split.
+# Minimum value: 1, maximum value: 20, default value: 5.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
-COLS_IN_ALPHA_INDEX = 5
+COLS_IN_ALPHA_INDEX = 5
-# In case all classes in a project start with a common prefix, all
-# classes will be put under the same header in the alphabetical index.
-# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
-# should be ignored while generating the index headers.
+# In case all classes in a project start with a common prefix, all classes will
+# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag
+# can be used to specify a prefix (or a list of prefixes) that should be ignored
+# while generating the index headers.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
-IGNORE_PREFIX =
+IGNORE_PREFIX =
#---------------------------------------------------------------------------
-# configuration options related to the HTML output
+# Configuration options related to the HTML output
#---------------------------------------------------------------------------
-# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
-# generate HTML output.
+# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output
+# The default value is: YES.
-GENERATE_HTML = YES
+GENERATE_HTML = YES
-# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `html' will be used as the default path.
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_OUTPUT = html
+HTML_OUTPUT = html
-# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
-# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
-# doxygen will generate files with .html extension.
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each
+# generated HTML page (for example: .htm, .php, .asp).
+# The default value is: .html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_FILE_EXTENSION = .html
+HTML_FILE_EXTENSION = .html
-# The HTML_HEADER tag can be used to specify a personal HTML header for
-# each generated HTML page. If it is left blank doxygen will generate a
-# standard header. Note that when using a custom header you are responsible
-# for the proper inclusion of any scripts and style sheets that doxygen
-# needs, which is dependent on the configuration options used.
-# It is advised to generate a default header using "doxygen -w html
-# header.html footer.html stylesheet.css YourConfigFile" and then modify
-# that header. Note that the header is subject to change so you typically
-# have to redo this when upgrading to a newer version of doxygen or when
-# changing the value of configuration settings such as GENERATE_TREEVIEW!
+# The HTML_HEADER tag can be used to specify a user-defined HTML header file for
+# each generated HTML page. If the tag is left blank doxygen will generate a
+# standard header.
+#
+# To get valid HTML the header file that includes any scripts and style sheets
+# that doxygen needs, which is dependent on the configuration options used (e.g.
+# the setting GENERATE_TREEVIEW). It is highly recommended to start with a
+# default header using
+# doxygen -w html new_header.html new_footer.html new_stylesheet.css
+# YourConfigFile
+# and then modify the file new_header.html. See also section "Doxygen usage"
+# for information on how to generate the default header that doxygen normally
+# uses.
+# Note: The header is subject to change so you typically have to regenerate the
+# default header when upgrading to a newer version of doxygen. For a description
+# of the possible markers and block names see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_HEADER = buildfiles/header.html
+HTML_HEADER = buildfiles/header.html
-# The HTML_FOOTER tag can be used to specify a personal HTML footer for
-# each generated HTML page. If it is left blank doxygen will generate a
-# standard footer.
+# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each
+# generated HTML page. If the tag is left blank doxygen will generate a standard
+# footer. See HTML_HEADER for more information on how to generate a default
+# footer and what special commands can be used inside the footer. See also
+# section "Doxygen usage" for information on how to generate the default footer
+# that doxygen normally uses.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_FOOTER = buildfiles/footer.html
+HTML_FOOTER = buildfiles/footer.html
-# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
-# style sheet that is used by each HTML page. It can be used to
-# fine-tune the look of the HTML output. If left blank doxygen will
-# generate a default style sheet. Note that it is recommended to use
-# HTML_EXTRA_STYLESHEET instead of this one, as it is more robust and this
-# tag will in the future become obsolete.
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style
+# sheet that is used by each HTML page. It can be used to fine-tune the look of
+# the HTML output. If left blank doxygen will generate a default style sheet.
+# See also section "Doxygen usage" for information on how to generate the style
+# sheet that doxygen normally uses.
+# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as
+# it is more robust and this tag (HTML_STYLESHEET) will in the future become
+# obsolete.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_STYLESHEET =
+HTML_STYLESHEET =
-# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional
-# user-defined cascading style sheet that is included after the standard
-# style sheets created by doxygen. Using this option one can overrule
-# certain style aspects. This is preferred over using HTML_STYLESHEET
-# since it does not replace the standard style sheet and is therefor more
-# robust against future updates. Doxygen will copy the style sheet file to
-# the output directory.
+# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# cascading style sheets that are included after the standard style sheets
+# created by doxygen. Using this option one can overrule certain style aspects.
+# This is preferred over using HTML_STYLESHEET since it does not replace the
+# standard style sheet and is therefore more robust against future updates.
+# Doxygen will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list). For an example see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_EXTRA_STYLESHEET = buildfiles/extra_stylesheet.css
+HTML_EXTRA_STYLESHEET = buildfiles/extra_stylesheet.css
# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
# other source files which should be copied to the HTML output directory. Note
# that these files will be copied to the base HTML output directory. Use the
-# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
-# files. In the HTML_STYLESHEET file, use the file name only. Also note that
-# the files will be copied as-is; there are no commands or markers available.
+# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that the
+# files will be copied as-is; there are no commands or markers available.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_EXTRA_FILES = buildfiles/favicon.ico
+HTML_EXTRA_FILES = buildfiles/favicon.ico
-# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
-# Doxygen will adjust the colors in the style sheet and background images
-# according to this color. Hue is specified as an angle on a colorwheel,
-# see http://en.wikipedia.org/wiki/Hue for more information.
-# For instance the value 0 represents red, 60 is yellow, 120 is green,
-# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
-# The allowed range is 0 to 359.
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen
+# will adjust the colors in the style sheet and background images according to
+# this color. Hue is specified as an angle on a colorwheel, see
+# https://en.wikipedia.org/wiki/Hue for more information. For instance the value
+# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300
+# purple, and 360 is red again.
+# Minimum value: 0, maximum value: 359, default value: 220.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_COLORSTYLE_HUE = 196
+HTML_COLORSTYLE_HUE = 196
-# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
-# the colors in the HTML output. For a value of 0 the output will use
-# grayscales only. A value of 255 will produce the most vivid colors.
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors
+# in the HTML output. For a value of 0 the output will use grayscales only. A
+# value of 255 will produce the most vivid colors.
+# Minimum value: 0, maximum value: 255, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_COLORSTYLE_SAT = 46
+HTML_COLORSTYLE_SAT = 46
-# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to
-# the luminance component of the colors in the HTML output. Values below
-# 100 gradually make the output lighter, whereas values above 100 make
-# the output darker. The value divided by 100 is the actual gamma applied,
-# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,
-# and 100 does not change the gamma.
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the
+# luminance component of the colors in the HTML output. Values below 100
+# gradually make the output lighter, whereas values above 100 make the output
+# darker. The value divided by 100 is the actual gamma applied, so 80 represents
+# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not
+# change the gamma.
+# Minimum value: 40, maximum value: 240, default value: 80.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_COLORSTYLE_GAMMA = 92
+HTML_COLORSTYLE_GAMMA = 92
# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
-# page will contain the date and time when the page was generated. Setting
-# this to NO can help when comparing the output of multiple runs.
+# page will contain the date and time when the page was generated. Setting this
+# to YES can help to show when doxygen was last run and thus if the
+# documentation is up to date.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_TIMESTAMP = YES
+HTML_TIMESTAMP = YES
+
+# If the HTML_DYNAMIC_MENUS tag is set to YES then the generated HTML
+# documentation will contain a main index with vertical navigation menus that
+# are dynamically created via Javascript. If disabled, the navigation index will
+# consists of multiple levels of tabs that are statically embedded in every HTML
+# page. Disable this option to support browsers that do not have Javascript,
+# like the Qt help browser.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+#HTML_DYNAMIC_MENUS = YES
# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
# documentation will contain sections that can be hidden and shown after the
# page has loaded.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-HTML_DYNAMIC_SECTIONS = NO
+HTML_DYNAMIC_SECTIONS = NO
-# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of
-# entries shown in the various tree structured indices initially; the user
-# can expand and collapse entries dynamically later on. Doxygen will expand
-# the tree to such a level that at most the specified number of entries are
-# visible (unless a fully collapsed tree already exceeds this amount).
-# So setting the number of entries 1 will produce a full collapsed tree by
-# default. 0 is a special value representing an infinite number of entries
-# and will result in a full expanded tree by default.
+# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries
+# shown in the various tree structured indices initially; the user can expand
+# and collapse entries dynamically later on. Doxygen will expand the tree to
+# such a level that at most the specified number of entries are visible (unless
+# a fully collapsed tree already exceeds this amount). So setting the number of
+# entries 1 will produce a full collapsed tree by default. 0 is a special value
+# representing an infinite number of entries and will result in a full expanded
+# tree by default.
+# Minimum value: 0, maximum value: 9999, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
HTML_INDEX_NUM_ENTRIES = 100
-# If the GENERATE_DOCSET tag is set to YES, additional index files
-# will be generated that can be used as input for Apple's Xcode 3
-# integrated development environment, introduced with OSX 10.5 (Leopard).
-# To create a documentation set, doxygen will generate a Makefile in the
-# HTML output directory. Running make will produce the docset in that
-# directory and running "make install" will install the docset in
-# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
-# it at startup.
-# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# If the GENERATE_DOCSET tag is set to YES, additional index files will be
+# generated that can be used as input for Apple's Xcode 3 integrated development
+# environment (see: https://developer.apple.com/tools/xcode/), introduced with
+# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a
+# Makefile in the HTML output directory. Running make will produce the docset in
+# that directory and running make install will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at
+# startup. See https://developer.apple.com/tools/creatingdocsetswithdoxygen.html
# for more information.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-GENERATE_DOCSET = NO
+GENERATE_DOCSET = NO
-# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
-# feed. A documentation feed provides an umbrella under which multiple
-# documentation sets from a single provider (such as a company or product suite)
-# can be grouped.
+# This tag determines the name of the docset feed. A documentation feed provides
+# an umbrella under which multiple documentation sets from a single provider
+# (such as a company or product suite) can be grouped.
+# The default value is: Doxygen generated docs.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
-DOCSET_FEEDNAME = "Doxygen generated docs"
+DOCSET_FEEDNAME = "Doxygen generated docs"
-# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
-# should uniquely identify the documentation set bundle. This should be a
-# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
-# will append .docset to the name.
+# This tag specifies a string that should uniquely identify the documentation
+# set bundle. This should be a reverse domain-name style string, e.g.
+# com.mycompany.MyDocSet. Doxygen will append .docset to the name.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
-DOCSET_BUNDLE_ID = org.doxygen.Project
+DOCSET_BUNDLE_ID = org.doxygen.Project
-# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely
-# identify the documentation publisher. This should be a reverse domain-name
-# style string, e.g. com.mycompany.MyDocSet.documentation.
+# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+# The default value is: org.doxygen.Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
-DOCSET_PUBLISHER_ID = org.doxygen.Publisher
+DOCSET_PUBLISHER_ID = org.doxygen.Publisher
-# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
+# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.
+# The default value is: Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
-DOCSET_PUBLISHER_NAME = Publisher
+DOCSET_PUBLISHER_NAME = Publisher
-# If the GENERATE_HTMLHELP tag is set to YES, additional index files
-# will be generated that can be used as input for tools like the
-# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
-# of the generated HTML documentation.
+# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three
+# additional HTML index files: index.hhp, index.hhc, and index.hhk. The
+# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop
+# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on
+# Windows.
+#
+# The HTML Help Workshop contains a compiler that can convert all HTML output
+# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML
+# files are now used as the Windows 98 help format, and will replace the old
+# Windows help format (.hlp) on all Windows platforms in the future. Compressed
+# HTML files also contain an index, a table of contents, and you can search for
+# words in the documentation. The HTML workshop also contains a viewer for
+# compressed HTML files.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-GENERATE_HTMLHELP = NO
+GENERATE_HTMLHELP = NO
-# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
-# be used to specify the file name of the resulting .chm file. You
-# can add a path in front of the file if the result should not be
+# The CHM_FILE tag can be used to specify the file name of the resulting .chm
+# file. You can add a path in front of the file if the result should not be
# written to the html output directory.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-CHM_FILE =
+CHM_FILE =
-# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
-# be used to specify the location (absolute path including file name) of
-# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
-# the HTML help compiler on the generated index.hhp.
+# The HHC_LOCATION tag can be used to specify the location (absolute path
+# including file name) of the HTML help compiler (hhc.exe). If non-empty,
+# doxygen will try to run the HTML help compiler on the generated index.hhp.
+# The file has to be specified with full path.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-HHC_LOCATION =
+HHC_LOCATION =
-# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
-# controls if a separate .chi index file is generated (YES) or that
-# it should be included in the master .chm file (NO).
+# The GENERATE_CHI flag controls if a separate .chi index file is generated
+# (YES) or that it should be included in the master .chm file (NO).
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-GENERATE_CHI = NO
+GENERATE_CHI = NO
-# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
-# is used to encode HtmlHelp index (hhk), content (hhc) and project file
-# content.
+# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc)
+# and project file content.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-CHM_INDEX_ENCODING =
+CHM_INDEX_ENCODING =
-# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
-# controls whether a binary table of contents is generated (YES) or a
-# normal table of contents (NO) in the .chm file.
+# The BINARY_TOC flag controls whether a binary table of contents is generated
+# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it
+# enables the Previous and Next buttons.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-BINARY_TOC = NO
+BINARY_TOC = NO
-# The TOC_EXPAND flag can be set to YES to add extra items for group members
-# to the contents of the HTML help documentation and to the tree view.
+# The TOC_EXPAND flag can be set to YES to add extra items for group members to
+# the table of contents of the HTML help documentation and to the tree view.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-TOC_EXPAND = NO
+TOC_EXPAND = NO
# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
-# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated
-# that can be used as input for Qt's qhelpgenerator to generate a
-# Qt Compressed Help (.qch) of the generated HTML documentation.
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that
+# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help
+# (.qch) of the generated HTML documentation.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-GENERATE_QHP = NO
+GENERATE_QHP = NO
-# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
-# be used to specify the file name of the resulting .qch file.
-# The path specified is relative to the HTML output folder.
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify
+# the file name of the resulting .qch file. The path specified is relative to
+# the HTML output folder.
+# This tag requires that the tag GENERATE_QHP is set to YES.
-QCH_FILE =
+QCH_FILE =
-# The QHP_NAMESPACE tag specifies the namespace to use when generating
-# Qt Help Project output. For more information please see
-# http://doc.trolltech.com/qthelpproject.html#namespace
+# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help
+# Project output. For more information please see Qt Help Project / Namespace
+# (see: http://doc.qt.io/qt-4.8/qthelpproject.html#namespace).
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_QHP is set to YES.
-QHP_NAMESPACE = org.doxygen.Project
+QHP_NAMESPACE = org.doxygen.Project
-# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
-# Qt Help Project output. For more information please see
-# http://doc.trolltech.com/qthelpproject.html#virtual-folders
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt
+# Help Project output. For more information please see Qt Help Project / Virtual
+# Folders (see: http://doc.qt.io/qt-4.8/qthelpproject.html#virtual-folders).
+# The default value is: doc.
+# This tag requires that the tag GENERATE_QHP is set to YES.
-QHP_VIRTUAL_FOLDER = doc
+QHP_VIRTUAL_FOLDER = doc
-# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to
-# add. For more information please see
-# http://doc.trolltech.com/qthelpproject.html#custom-filters
+# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom
+# filter to add. For more information please see Qt Help Project / Custom
+# Filters (see: http://doc.qt.io/qt-4.8/qthelpproject.html#custom-filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
-QHP_CUST_FILTER_NAME =
+QHP_CUST_FILTER_NAME =
-# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the
-# custom filter to add. For more information please see
-#
-# Qt Help Project / Custom Filters .
+# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see Qt Help Project / Custom
+# Filters (see: http://doc.qt.io/qt-4.8/qthelpproject.html#custom-filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
-QHP_CUST_FILTER_ATTRS =
+QHP_CUST_FILTER_ATTRS =
# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
-# project's
-# filter section matches.
-#
-# Qt Help Project / Filter Attributes .
+# project's filter section matches. Qt Help Project / Filter Attributes (see:
+# http://doc.qt.io/qt-4.8/qthelpproject.html#filter-attributes).
+# This tag requires that the tag GENERATE_QHP is set to YES.
-QHP_SECT_FILTER_ATTRS =
+QHP_SECT_FILTER_ATTRS =
-# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
-# be used to specify the location of Qt's qhelpgenerator.
-# If non-empty doxygen will try to run qhelpgenerator on the generated
-# .qhp file.
+# The QHG_LOCATION tag can be used to specify the location of Qt's
+# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the
+# generated .qhp file.
+# This tag requires that the tag GENERATE_QHP is set to YES.
-QHG_LOCATION =
+QHG_LOCATION =
-# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
-# will be generated, which together with the HTML files, form an Eclipse help
-# plugin. To install this plugin and make it available under the help contents
-# menu in Eclipse, the contents of the directory containing the HTML and XML
-# files needs to be copied into the plugins directory of eclipse. The name of
-# the directory within the plugins directory should be the same as
-# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before
-# the help appears.
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be
+# generated, together with the HTML files, they form an Eclipse help plugin. To
+# install this plugin and make it available under the help contents menu in
+# Eclipse, the contents of the directory containing the HTML and XML files needs
+# to be copied into the plugins directory of eclipse. The name of the directory
+# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.
+# After copying Eclipse needs to be restarted before the help appears.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-GENERATE_ECLIPSEHELP = YES
+GENERATE_ECLIPSEHELP = YES
-# A unique identifier for the eclipse help plugin. When installing the plugin
-# the directory name containing the HTML and XML files should also have
-# this name.
+# A unique identifier for the Eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have this
+# name. Each documentation set should have its own identifier.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.
+
+ECLIPSE_DOC_ID = com.nordic.infocenter.nrfx
+
+# If you want full control over the layout of the generated HTML pages it might
+# be necessary to disable the index and replace it with your own. The
+# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top
+# of each HTML page. A value of NO enables the index and the value YES disables
+# it. Since the tabs in the index contain the same information as the navigation
+# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-ECLIPSE_DOC_ID = com.nordic.infocenter.nrfx
### EDIT THIS ###
-# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs)
-# at top of each HTML page. The value NO (the default) enables the index and
-# the value YES disables it. Since the tabs have the same information as the
-# navigation tree you can set this option to NO if you already set
-# GENERATE_TREEVIEW to YES.
-
-DISABLE_INDEX = YES
+DISABLE_INDEX = YES
# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
-# structure should be generated to display hierarchical information.
-# If the tag value is set to YES, a side panel will be generated
-# containing a tree-like index structure (just like the one that
-# is generated for HTML Help). For this to work a browser that supports
-# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
-# Windows users are probably better off using the HTML help feature.
-# Since the tree basically has the same information as the tab index you
-# could consider to set DISABLE_INDEX to NO when enabling this option.
+# structure should be generated to display hierarchical information. If the tag
+# value is set to YES, a side panel will be generated containing a tree-like
+# index structure (just like the one that is generated for HTML Help). For this
+# to work a browser that supports JavaScript, DHTML, CSS and frames is required
+# (i.e. any modern browser). Windows users are probably better off using the
+# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can
+# further fine-tune the look of the index. As an example, the default style
+# sheet generated by doxygen has an example that shows how to put an image at
+# the root of the tree instead of the PROJECT_NAME. Since the tree basically has
+# the same information as the tab index, you could consider setting
+# DISABLE_INDEX to YES when enabling this option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-GENERATE_TREEVIEW = YES
+GENERATE_TREEVIEW = YES
-# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values
-# (range [0,1..20]) that doxygen will group on one line in the generated HTML
-# documentation. Note that a value of 0 will completely suppress the enum
-# values from appearing in the overview section.
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
+# doxygen will group on one line in the generated HTML documentation.
+#
+# Note that a value of 0 will completely suppress the enum values from appearing
+# in the overview section.
+# Minimum value: 0, maximum value: 20, default value: 4.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-ENUM_VALUES_PER_LINE = 1
+ENUM_VALUES_PER_LINE = 1
-# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
-# used to set the initial width (in pixels) of the frame in which the tree
-# is shown.
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used
+# to set the initial width (in pixels) of the frame in which the tree is shown.
+# Minimum value: 0, maximum value: 1500, default value: 250.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-TREEVIEW_WIDTH = 250
+TREEVIEW_WIDTH = 250
-# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open
-# links to external symbols imported via tag files in a separate window.
+# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to
+# external symbols imported via tag files in a separate window.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-EXT_LINKS_IN_WINDOW = NO
+EXT_LINKS_IN_WINDOW = NO
-# Use this tag to change the font size of Latex formulas included
-# as images in the HTML documentation. The default is 10. Note that
-# when you change the font size after a successful doxygen run you need
-# to manually remove any form_*.png images from the HTML output directory
-# to force them to be regenerated.
+# Use this tag to change the font size of LaTeX formulas included as images in
+# the HTML documentation. When you change the font size after a successful
+# doxygen run you need to manually remove any form_*.png images from the HTML
+# output directory to force them to be regenerated.
+# Minimum value: 8, maximum value: 50, default value: 10.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-FORMULA_FONTSIZE = 10
+FORMULA_FONTSIZE = 10
-# Use the FORMULA_TRANPARENT tag to determine whether or not the images
-# generated for formulas are transparent PNGs. Transparent PNGs are
-# not supported properly for IE 6.0, but are supported on all modern browsers.
-# Note that when changing this option you need to delete any form_*.png files
-# in the HTML output before the changes have effect.
+# Use the FORMULA_TRANSPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are not
+# supported properly for IE 6.0, but are supported on all modern browsers.
+#
+# Note that when changing this option you need to delete any form_*.png files in
+# the HTML output directory before the changes have effect.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-FORMULA_TRANSPARENT = YES
+FORMULA_TRANSPARENT = YES
-# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax
-# (see http://www.mathjax.org) which uses client side Javascript for the
-# rendering instead of using prerendered bitmaps. Use this if you do not
-# have LaTeX installed or if you want to formulas look prettier in the HTML
-# output. When enabled you may also need to install MathJax separately and
-# configure the path to it using the MATHJAX_RELPATH option.
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see
+# https://www.mathjax.org) which uses client side Javascript for the rendering
+# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX
+# installed or if you want to formulas look prettier in the HTML output. When
+# enabled you may also need to install MathJax separately and configure the path
+# to it using the MATHJAX_RELPATH option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
-USE_MATHJAX = NO
+USE_MATHJAX = NO
# When MathJax is enabled you can set the default output format to be used for
-# thA MathJax output. Supported types are HTML-CSS, NativeMML (i.e. MathML) and
-# SVG. The default value is HTML-CSS, which is slower, but has the best
-# compatibility.
+# the MathJax output. See the MathJax site (see:
+# http://docs.mathjax.org/en/latest/output.html) for more details.
+# Possible values are: HTML-CSS (which is slower, but has the best
+# compatibility), NativeMML (i.e. MathML) and SVG.
+# The default value is: HTML-CSS.
+# This tag requires that the tag USE_MATHJAX is set to YES.
-MATHJAX_FORMAT = HTML-CSS
+MATHJAX_FORMAT = HTML-CSS
-# When MathJax is enabled you need to specify the location relative to the
-# HTML output directory using the MATHJAX_RELPATH option. The destination
-# directory should contain the MathJax.js script. For instance, if the mathjax
-# directory is located at the same level as the HTML output directory, then
-# MATHJAX_RELPATH should be ../mathjax. The default value points to
-# the MathJax Content Delivery Network so you can quickly see the result without
-# installing MathJax.
-# However, it is strongly recommended to install a local
-# copy of MathJax from http://www.mathjax.org before deployment.
+# When MathJax is enabled you need to specify the location relative to the HTML
+# output directory using the MATHJAX_RELPATH option. The destination directory
+# should contain the MathJax.js script. For instance, if the mathjax directory
+# is located at the same level as the HTML output directory, then
+# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax
+# Content Delivery Network so you can quickly see the result without installing
+# MathJax. However, it is strongly recommended to install a local copy of
+# MathJax from https://www.mathjax.org before deployment.
+# The default value is: https://cdnjs.cloudflare.com/ajax/libs/mathjax/2.7.2/.
+# This tag requires that the tag USE_MATHJAX is set to YES.
-MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest
+MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest
-# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension
-# names that should be enabled during MathJax rendering.
+# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax
+# extension names that should be enabled during MathJax rendering. For example
+# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols
+# This tag requires that the tag USE_MATHJAX is set to YES.
-MATHJAX_EXTENSIONS =
+MATHJAX_EXTENSIONS =
-# When the SEARCHENGINE tag is enabled doxygen will generate a search box
-# for the HTML output. The underlying search engine uses javascript
-# and DHTML and should work on any modern browser. Note that when using
-# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets
-# (GENERATE_DOCSET) there is already a search function so this one should
-# typically be disabled. For large projects the javascript based search engine
-# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
+# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces
+# of code that will be used on startup of the MathJax code. See the MathJax site
+# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an
+# example see the documentation.
+# This tag requires that the tag USE_MATHJAX is set to YES.
-SEARCHENGINE =
+#MATHJAX_CODEFILE =
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box for
+# the HTML output. The underlying search engine uses javascript and DHTML and
+# should work on any modern browser. Note that when using HTML help
+# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)
+# there is already a search function so this one should typically be disabled.
+# For large projects the javascript based search engine can be slow, then
+# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to
+# search using the keyboard; to jump to the search box use + S
+# (what the is depends on the OS and browser, but it is typically
+# , /, or both). Inside the search box use the to jump into the search results window, the results can be navigated
+# using the . Press to select an item or to cancel
+# the search. The filter options can be selected when the cursor is inside the
+# search box by pressing +. Also here use the
+# to select a filter and or to activate or cancel the filter
+# option.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+SEARCHENGINE = YES
# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
-# implemented using a web server instead of a web client using Javascript.
-# There are two flavours of web server based search depending on the
-# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for
-# searching and an index file used by the script. When EXTERNAL_SEARCH is
-# enabled the indexing and searching needs to be provided by external tools.
-# See the manual for details.
+# implemented using a web server instead of a web client using Javascript. There
+# are two flavors of web server based searching depending on the EXTERNAL_SEARCH
+# setting. When disabled, doxygen will generate a PHP script for searching and
+# an index file used by the script. When EXTERNAL_SEARCH is enabled the indexing
+# and searching needs to be provided by external tools. See the section
+# "External Indexing and Searching" for details.
+# The default value is: NO.
+# This tag requires that the tag SEARCHENGINE is set to YES.
-SERVER_BASED_SEARCH = NO
+SERVER_BASED_SEARCH = NO
-# When EXTERNAL_SEARCH is enabled doxygen will no longer generate the PHP
+# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP
# script for searching. Instead the search results are written to an XML file
# which needs to be processed by an external indexer. Doxygen will invoke an
-# external search engine pointed to by the SEARCHENGINE_URL option to obtain
-# the search results. Doxygen ships with an example indexer (doxyindexer) and
-# search engine (doxysearch.cgi) which are based on the open source search engine
-# library Xapian. See the manual for configuration details.
+# external search engine pointed to by the SEARCHENGINE_URL option to obtain the
+# search results.
+#
+# Doxygen ships with an example indexer (doxyindexer) and search engine
+# (doxysearch.cgi) which are based on the open source search engine library
+# Xapian (see: https://xapian.org/).
+#
+# See the section "External Indexing and Searching" for details.
+# The default value is: NO.
+# This tag requires that the tag SEARCHENGINE is set to YES.
-EXTERNAL_SEARCH = NO
+EXTERNAL_SEARCH = NO
# The SEARCHENGINE_URL should point to a search engine hosted by a web server
-# which will returned the search results when EXTERNAL_SEARCH is enabled.
-# Doxygen ships with an example search engine (doxysearch) which is based on
-# the open source search engine library Xapian. See the manual for configuration
-# details.
+# which will return the search results when EXTERNAL_SEARCH is enabled.
+#
+# Doxygen ships with an example indexer (doxyindexer) and search engine
+# (doxysearch.cgi) which are based on the open source search engine library
+# Xapian (see: https://xapian.org/). See the section "External Indexing and
+# Searching" for details.
+# This tag requires that the tag SEARCHENGINE is set to YES.
-SEARCHENGINE_URL =
+SEARCHENGINE_URL =
# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed
# search data is written to a file for indexing by an external tool. With the
# SEARCHDATA_FILE tag the name of this file can be specified.
+# The default file is: searchdata.xml.
+# This tag requires that the tag SEARCHENGINE is set to YES.
-SEARCHDATA_FILE = searchdata.xml
+SEARCHDATA_FILE = searchdata.xml
-# When SERVER_BASED_SEARCH AND EXTERNAL_SEARCH are both enabled the
+# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the
# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is
# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple
# projects and redirect the results back to the right project.
+# This tag requires that the tag SEARCHENGINE is set to YES.
-EXTERNAL_SEARCH_ID =
+EXTERNAL_SEARCH_ID =
# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen
# projects other than the one defined by this configuration file, but that are
# all added to the same external search index. Each project needs to have a
-# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id
-# of to a relative location where the documentation can be found.
-# The format is: EXTRA_SEARCH_MAPPINGS = id1=loc1 id2=loc2 ...
+# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of
+# to a relative location where the documentation can be found. The format is:
+# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...
+# This tag requires that the tag SEARCHENGINE is set to YES.
-EXTRA_SEARCH_MAPPINGS =
+EXTRA_SEARCH_MAPPINGS =
#---------------------------------------------------------------------------
-# configuration options related to the LaTeX output
+# Configuration options related to the LaTeX output
#---------------------------------------------------------------------------
-# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
-# generate Latex output.
+# If the GENERATE_LATEX tag is set to YES, doxygen will generate LaTeX output.
+# The default value is: YES.
-GENERATE_LATEX = NO
+GENERATE_LATEX = NO
-# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `latex' will be used as the default path.
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: latex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-LATEX_OUTPUT = latex
+LATEX_OUTPUT = latex
# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
-# invoked. If left blank `latex' will be used as the default command name.
-# Note that when enabling USE_PDFLATEX this option is only used for
-# generating bitmaps for formulas in the HTML output, but not in the
-# Makefile that is written to the output directory.
+# invoked.
+#
+# Note that when enabling USE_PDFLATEX this option is only used for generating
+# bitmaps for formulas in the HTML output, but not in the Makefile that is
+# written to the output directory.
+# The default file is: latex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-LATEX_CMD_NAME = latex
+LATEX_CMD_NAME = latex
-# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
-# generate index for LaTeX. If left blank `makeindex' will be used as the
-# default command name.
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate
+# index for LaTeX.
+# The default file is: makeindex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-MAKEINDEX_CMD_NAME = makeindex
+MAKEINDEX_CMD_NAME = makeindex
-# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
-# LaTeX documents. This may be useful for small projects and may help to
-# save some trees in general.
+# If the COMPACT_LATEX tag is set to YES, doxygen generates more compact LaTeX
+# documents. This may be useful for small projects and may help to save some
+# trees in general.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-COMPACT_LATEX = NO
+COMPACT_LATEX = NO
-# The PAPER_TYPE tag can be used to set the paper type that is used
-# by the printer. Possible values are: a4, letter, legal and
-# executive. If left blank a4wide will be used.
+# The PAPER_TYPE tag can be used to set the paper type that is used by the
+# printer.
+# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x
+# 14 inches) and executive (7.25 x 10.5 inches).
+# The default value is: a4.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-PAPER_TYPE = a4
+PAPER_TYPE = a4
-# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
-# packages that should be included in the LaTeX output.
+# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names
+# that should be included in the LaTeX output. The package can be specified just
+# by its name or with the correct syntax as to be used with the LaTeX
+# \usepackage command. To get the times font for instance you can specify :
+# EXTRA_PACKAGES=times or EXTRA_PACKAGES={times}
+# To use the option intlimits with the amsmath package you can specify:
+# EXTRA_PACKAGES=[intlimits]{amsmath}
+# If left blank no extra packages will be included.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-EXTRA_PACKAGES =
+EXTRA_PACKAGES =
-# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
-# the generated latex document. The header should contain everything until
-# the first chapter. If it is left blank doxygen will generate a
-# standard header. Notice: only use this tag if you know what you are doing!
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the
+# generated LaTeX document. The header should contain everything until the first
+# chapter. If it is left blank doxygen will generate a standard header. See
+# section "Doxygen usage" for information on how to let doxygen write the
+# default header to a separate file.
+#
+# Note: Only use a user-defined header if you know what you are doing! The
+# following commands have a special meaning inside the header: $title,
+# $datetime, $date, $doxygenversion, $projectname, $projectnumber,
+# $projectbrief, $projectlogo. Doxygen will replace $title with the empty
+# string, for the replacement values of the other commands the user is referred
+# to HTML_HEADER.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-LATEX_HEADER =
+LATEX_HEADER =
-# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for
-# the generated latex document. The footer should contain everything after
-# the last chapter. If it is left blank doxygen will generate a
-# standard footer. Notice: only use this tag if you know what you are doing!
+# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the
+# generated LaTeX document. The footer should contain everything after the last
+# chapter. If it is left blank doxygen will generate a standard footer. See
+# LATEX_HEADER for more information on how to generate a default footer and what
+# special commands can be used inside the footer.
+#
+# Note: Only use a user-defined footer if you know what you are doing!
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-LATEX_FOOTER =
+LATEX_FOOTER =
-# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
-# is prepared for conversion to pdf (using ps2pdf). The pdf file will
-# contain links (just like the HTML output) instead of page references
-# This makes the output suitable for online browsing using a pdf viewer.
+# The LATEX_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# LaTeX style sheets that are included after the standard style sheets created
+# by doxygen. Using this option one can overrule certain style aspects. Doxygen
+# will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list).
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-PDF_HYPERLINKS = YES
+#LATEX_EXTRA_STYLESHEET =
-# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
-# plain latex in the generated Makefile. Set this option to YES to get a
+# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the LATEX_OUTPUT output
+# directory. Note that the files will be copied as-is; there are no commands or
+# markers available.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+#LATEX_EXTRA_FILES =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is
+# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will
+# contain links (just like the HTML output) instead of page references. This
+# makes the output suitable for online browsing using a PDF viewer.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+PDF_HYPERLINKS = YES
+
+# If the USE_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate
+# the PDF file directly from the LaTeX files. Set this option to YES, to get a
# higher quality PDF documentation.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-USE_PDFLATEX = YES
+USE_PDFLATEX = YES
-# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
-# command to the generated LaTeX files. This will instruct LaTeX to keep
-# running if errors occur, instead of asking the user for help.
-# This option is also used when generating formulas in HTML.
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \batchmode
+# command to the generated LaTeX files. This will instruct LaTeX to keep running
+# if errors occur, instead of asking the user for help. This option is also used
+# when generating formulas in HTML.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-LATEX_BATCHMODE = NO
+LATEX_BATCHMODE = NO
-# If LATEX_HIDE_INDICES is set to YES then doxygen will not
-# include the index chapters (such as File Index, Compound Index, etc.)
-# in the output.
+# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the
+# index chapters (such as File Index, Compound Index, etc.) in the output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-LATEX_HIDE_INDICES = NO
+LATEX_HIDE_INDICES = NO
-# If LATEX_SOURCE_CODE is set to YES then doxygen will include
-# source code with syntax highlighting in the LaTeX output.
-# Note that which sources are shown also depends on other settings
-# such as SOURCE_BROWSER.
+# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source
+# code with syntax highlighting in the LaTeX output.
+#
+# Note that which sources are shown also depends on other settings such as
+# SOURCE_BROWSER.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-LATEX_SOURCE_CODE = NO
+LATEX_SOURCE_CODE = NO
# The LATEX_BIB_STYLE tag can be used to specify the style to use for the
-# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See
-# http://en.wikipedia.org/wiki/BibTeX for more info.
+# bibliography, e.g. plainnat, or ieeetr. See
+# https://en.wikipedia.org/wiki/BibTeX and \cite for more info.
+# The default value is: plain.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
-LATEX_BIB_STYLE = plain
+LATEX_BIB_STYLE = plain
+
+# If the LATEX_TIMESTAMP tag is set to YES then the footer of each generated
+# page will contain the date and time when the page was generated. Setting this
+# to NO can help when comparing the output of multiple runs.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+#LATEX_TIMESTAMP = NO
#---------------------------------------------------------------------------
-# configuration options related to the RTF output
+# Configuration options related to the RTF output
#---------------------------------------------------------------------------
-# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
-# The RTF output is optimized for Word 97 and may not look very pretty with
-# other RTF readers or editors.
+# If the GENERATE_RTF tag is set to YES, doxygen will generate RTF output. The
+# RTF output is optimized for Word 97 and may not look too pretty with other RTF
+# readers/editors.
+# The default value is: NO.
-GENERATE_RTF = NO
+GENERATE_RTF = NO
-# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `rtf' will be used as the default path.
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: rtf.
+# This tag requires that the tag GENERATE_RTF is set to YES.
-RTF_OUTPUT = rtf
+RTF_OUTPUT = rtf
-# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
-# RTF documents. This may be useful for small projects and may help to
-# save some trees in general.
+# If the COMPACT_RTF tag is set to YES, doxygen generates more compact RTF
+# documents. This may be useful for small projects and may help to save some
+# trees in general.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
-COMPACT_RTF = NO
+COMPACT_RTF = NO
-# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
-# will contain hyperlink fields. The RTF file will
-# contain links (just like the HTML output) instead of page references.
-# This makes the output suitable for online browsing using WORD or other
-# programs which support those fields.
-# Note: wordpad (write) and others do not support links.
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will
+# contain hyperlink fields. The RTF file will contain links (just like the HTML
+# output) instead of page references. This makes the output suitable for online
+# browsing using Word or some other Word compatible readers that support those
+# fields.
+#
+# Note: WordPad (write) and others do not support links.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
-RTF_HYPERLINKS = NO
+RTF_HYPERLINKS = NO
-# Load style sheet definitions from file. Syntax is similar to doxygen's
-# config file, i.e. a series of assignments. You only have to provide
-# replacements, missing definitions are set to their default value.
+# Load stylesheet definitions from file. Syntax is similar to doxygen's config
+# file, i.e. a series of assignments. You only have to provide replacements,
+# missing definitions are set to their default value.
+#
+# See also section "Doxygen usage" for information on how to generate the
+# default style sheet that doxygen normally uses.
+# This tag requires that the tag GENERATE_RTF is set to YES.
-RTF_STYLESHEET_FILE =
+RTF_STYLESHEET_FILE =
-# Set optional variables used in the generation of an rtf document.
-# Syntax is similar to doxygen's config file.
+# Set optional variables used in the generation of an RTF document. Syntax is
+# similar to doxygen's config file. A template extensions file can be generated
+# using doxygen -e rtf extensionFile.
+# This tag requires that the tag GENERATE_RTF is set to YES.
-RTF_EXTENSIONS_FILE =
+RTF_EXTENSIONS_FILE =
+
+# If the RTF_SOURCE_CODE tag is set to YES then doxygen will include source code
+# with syntax highlighting in the RTF output.
+#
+# Note that which sources are shown also depends on other settings such as
+# SOURCE_BROWSER.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+#RTF_SOURCE_CODE = NO
#---------------------------------------------------------------------------
-# configuration options related to the man page output
+# Configuration options related to the man page output
#---------------------------------------------------------------------------
-# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
-# generate man pages
+# If the GENERATE_MAN tag is set to YES, doxygen will generate man pages for
+# classes and files.
+# The default value is: NO.
-GENERATE_MAN = NO
+GENERATE_MAN = NO
-# The MAN_OUTPUT tag is used to specify where the man pages will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `man' will be used as the default path.
+# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it. A directory man3 will be created inside the directory specified by
+# MAN_OUTPUT.
+# The default directory is: man.
+# This tag requires that the tag GENERATE_MAN is set to YES.
-MAN_OUTPUT = man
+MAN_OUTPUT = man
-# The MAN_EXTENSION tag determines the extension that is added to
-# the generated man pages (default is the subroutine's section .3)
+# The MAN_EXTENSION tag determines the extension that is added to the generated
+# man pages. In case the manual section does not start with a number, the number
+# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is
+# optional.
+# The default value is: .3.
+# This tag requires that the tag GENERATE_MAN is set to YES.
-MAN_EXTENSION = .3
+MAN_EXTENSION = .3
-# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
-# then it will generate one additional man file for each entity
-# documented in the real man page(s). These additional files
-# only source the real man page, but without them the man command
-# would be unable to find the correct page. The default is NO.
+# The MAN_SUBDIR tag determines the name of the directory created within
+# MAN_OUTPUT in which the man pages are placed. If defaults to man followed by
+# MAN_EXTENSION with the initial . removed.
+# This tag requires that the tag GENERATE_MAN is set to YES.
-MAN_LINKS = NO
+#MAN_SUBDIR =
+
+# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
+# will generate one additional man file for each entity documented in the real
+# man page(s). These additional files only source the real man page, but without
+# them the man command would be unable to find the correct page.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_LINKS = NO
#---------------------------------------------------------------------------
-# configuration options related to the XML output
+# Configuration options related to the XML output
#---------------------------------------------------------------------------
-# If the GENERATE_XML tag is set to YES Doxygen will
-# generate an XML file that captures the structure of
-# the code including all documentation.
+# If the GENERATE_XML tag is set to YES, doxygen will generate an XML file that
+# captures the structure of the code including all documentation.
+# The default value is: NO.
-GENERATE_XML = NO
+GENERATE_XML = NO
-# The XML_OUTPUT tag is used to specify where the XML pages will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `xml' will be used as the default path.
+# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: xml.
+# This tag requires that the tag GENERATE_XML is set to YES.
-XML_OUTPUT = xml
+XML_OUTPUT = xml
-# The XML_SCHEMA tag can be used to specify an XML schema,
-# which can be used by a validating XML parser to check the
-# syntax of the XML files.
+# If the XML_PROGRAMLISTING tag is set to YES, doxygen will dump the program
+# listings (including syntax highlighting and cross-referencing information) to
+# the XML output. Note that enabling this will significantly increase the size
+# of the XML output.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_XML is set to YES.
-XML_SCHEMA =
-
-# The XML_DTD tag can be used to specify an XML DTD,
-# which can be used by a validating XML parser to check the
-# syntax of the XML files.
-
-XML_DTD =
-
-# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
-# dump the program listings (including syntax highlighting
-# and cross-referencing information) to the XML output. Note that
-# enabling this will significantly increase the size of the XML output.
-
-XML_PROGRAMLISTING = YES
+XML_PROGRAMLISTING = YES
#---------------------------------------------------------------------------
-# configuration options for the AutoGen Definitions output
+# Configuration options related to the DOCBOOK output
#---------------------------------------------------------------------------
-# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
-# generate an AutoGen Definitions (see autogen.sf.net) file
-# that captures the structure of the code including all
-# documentation. Note that this feature is still experimental
-# and incomplete at the moment.
+# If the GENERATE_DOCBOOK tag is set to YES, doxygen will generate Docbook files
+# that can be used to generate PDF.
+# The default value is: NO.
-GENERATE_AUTOGEN_DEF = NO
+#GENERATE_DOCBOOK = NO
+
+# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in
+# front of it.
+# The default directory is: docbook.
+# This tag requires that the tag GENERATE_DOCBOOK is set to YES.
+
+#DOCBOOK_OUTPUT = docbook
+
+# If the DOCBOOK_PROGRAMLISTING tag is set to YES, doxygen will include the
+# program listings (including syntax highlighting and cross-referencing
+# information) to the DOCBOOK output. Note that enabling this will significantly
+# increase the size of the DOCBOOK output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_DOCBOOK is set to YES.
+
+#DOCBOOK_PROGRAMLISTING = NO
#---------------------------------------------------------------------------
-# configuration options related to the Perl module output
+# Configuration options for the AutoGen Definitions output
#---------------------------------------------------------------------------
-# If the GENERATE_PERLMOD tag is set to YES Doxygen will
-# generate a Perl module file that captures the structure of
-# the code including all documentation. Note that this
-# feature is still experimental and incomplete at the
-# moment.
+# If the GENERATE_AUTOGEN_DEF tag is set to YES, doxygen will generate an
+# AutoGen Definitions (see http://autogen.sourceforge.net/) file that captures
+# the structure of the code including all documentation. Note that this feature
+# is still experimental and incomplete at the moment.
+# The default value is: NO.
-GENERATE_PERLMOD = NO
+GENERATE_AUTOGEN_DEF = NO
-# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
-# the necessary Makefile rules, Perl scripts and LaTeX code to be able
-# to generate PDF and DVI output from the Perl module output.
+#---------------------------------------------------------------------------
+# Configuration options related to the Perl module output
+#---------------------------------------------------------------------------
-PERLMOD_LATEX = NO
+# If the GENERATE_PERLMOD tag is set to YES, doxygen will generate a Perl module
+# file that captures the structure of the code including all documentation.
+#
+# Note that this feature is still experimental and incomplete at the moment.
+# The default value is: NO.
-# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
-# nicely formatted so it can be parsed by a human reader.
-# This is useful
-# if you want to understand what is going on.
-# On the other hand, if this
-# tag is set to NO the size of the Perl module output will be much smaller
-# and Perl will parse it just the same.
+GENERATE_PERLMOD = NO
-PERLMOD_PRETTY = YES
+# If the PERLMOD_LATEX tag is set to YES, doxygen will generate the necessary
+# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI
+# output from the Perl module output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
-# The names of the make variables in the generated doxyrules.make file
-# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
-# This is useful so different doxyrules.make files included by the same
-# Makefile don't overwrite each other's variables.
+PERLMOD_LATEX = NO
+
+# If the PERLMOD_PRETTY tag is set to YES, the Perl module output will be nicely
+# formatted so it can be parsed by a human reader. This is useful if you want to
+# understand what is going on. On the other hand, if this tag is set to NO, the
+# size of the Perl module output will be much smaller and Perl will parse it
+# just the same.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
+
+PERLMOD_PRETTY = YES
+
+# The names of the make variables in the generated doxyrules.make file are
+# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful
+# so different doxyrules.make files included by the same Makefile don't
+# overwrite each other's variables.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
PERLMOD_MAKEVAR_PREFIX =
@@ -1555,338 +2032,474 @@ PERLMOD_MAKEVAR_PREFIX =
# Configuration options related to the preprocessor
#---------------------------------------------------------------------------
-# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
-# evaluate all C-preprocessor directives found in the sources and include
-# files.
+# If the ENABLE_PREPROCESSING tag is set to YES, doxygen will evaluate all
+# C-preprocessor directives found in the sources and include files.
+# The default value is: YES.
-ENABLE_PREPROCESSING = YES
+ENABLE_PREPROCESSING = YES
-# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
-# names in the source code. If set to NO (the default) only conditional
-# compilation will be performed. Macro expansion can be done in a controlled
-# way by setting EXPAND_ONLY_PREDEF to YES.
+# If the MACRO_EXPANSION tag is set to YES, doxygen will expand all macro names
+# in the source code. If set to NO, only conditional compilation will be
+# performed. Macro expansion can be done in a controlled way by setting
+# EXPAND_ONLY_PREDEF to YES.
+# The default value is: NO.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-MACRO_EXPANSION = YES
+MACRO_EXPANSION = YES
-# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
-# then the macro expansion is limited to the macros specified with the
-# PREDEFINED and EXPAND_AS_DEFINED tags.
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then
+# the macro expansion is limited to the macros specified with the PREDEFINED and
+# EXPAND_AS_DEFINED tags.
+# The default value is: NO.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-EXPAND_ONLY_PREDEF = NO
+EXPAND_ONLY_PREDEF = NO
-# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
-# pointed to by INCLUDE_PATH will be searched when a #include is found.
+# If the SEARCH_INCLUDES tag is set to YES, the include files in the
+# INCLUDE_PATH will be searched if a #include is found.
+# The default value is: YES.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-SEARCH_INCLUDES = YES
+SEARCH_INCLUDES = YES
# The INCLUDE_PATH tag can be used to specify one or more directories that
-# contain include files that are not input files but should be processed by
-# the preprocessor.
+# contain include files that are not input files but should be processed by the
+# preprocessor.
+# This tag requires that the tag SEARCH_INCLUDES is set to YES.
-INCLUDE_PATH =
+INCLUDE_PATH =
# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
# patterns (like *.h and *.hpp) to filter out the header-files in the
-# directories. If left blank, the patterns specified with FILE_PATTERNS will
-# be used.
+# directories. If left blank, the patterns specified with FILE_PATTERNS will be
+# used.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-INCLUDE_FILE_PATTERNS =
+INCLUDE_FILE_PATTERNS =
-# The PREDEFINED tag can be used to specify one or more macro names that
-# are defined before the preprocessor is started (similar to the -D option of
-# gcc). The argument of the tag is a list of macros of the form: name
-# or name=definition (no spaces). If the definition and the = are
-# omitted =1 is assumed. To prevent a macro definition from being
-# undefined via #undef or recursively expanded use the := operator
-# instead of the = operator.
+# The PREDEFINED tag can be used to specify one or more macro names that are
+# defined before the preprocessor is started (similar to the -D option of e.g.
+# gcc). The argument of the tag is a list of macros of the form: name or
+# name=definition (no spaces). If the definition and the "=" are omitted, "=1"
+# is assumed. To prevent a macro definition from being undefined via #undef or
+# recursively expanded use the := operator instead of the = operator.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-PREDEFINED = SUPPRESS_INLINE_IMPLEMENTATION __NRFX_DOXYGEN__ \
- CONFIG_PURGE_ENABLED == 1 \
- CONFIG_DISASSOCIATE_ENABLED == 1 \
- CONFIG_GTS_ENABLED == 1 \
- CONFIG_ORPHAN_ENABLED == 1 \
- CONFIG_RXE_ENABLED == 1 \
- CONFIG_START_ENABLED == 1 \
- CONFIG_SYNC_ENABLED == 1 \
- CONFIG_PANID_CONFLICT_ENABLED == 1 \
+PREDEFINED = SUPPRESS_INLINE_IMPLEMENTATION \
+ __NRFX_DOXYGEN__ \
+ CONFIG_PURGE_ENABLED \
+ == \
+ 1 \
+ CONFIG_DISASSOCIATE_ENABLED \
+ == \
+ 1 \
+ CONFIG_GTS_ENABLED \
+ == \
+ 1 \
+ CONFIG_ORPHAN_ENABLED \
+ == \
+ 1 \
+ CONFIG_RXE_ENABLED \
+ == \
+ 1 \
+ CONFIG_START_ENABLED \
+ == \
+ 1 \
+ CONFIG_SYNC_ENABLED \
+ == \
+ 1 \
+ CONFIG_PANID_CONFLICT_ENABLED \
+ == \
+ 1
-# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
-# this tag can be used to specify a list of macro names that should be expanded.
-# The macro definition that is found in the sources will be used.
-# Use the PREDEFINED tag if you want to use a different macro definition that
-# overrules the definition found in the source code.
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this
+# tag can be used to specify a list of macro names that should be expanded. The
+# macro definition that is found in the sources will be used. Use the PREDEFINED
+# tag if you want to use a different macro definition that overrules the
+# definition found in the source code.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-EXPAND_AS_DEFINED =
+EXPAND_AS_DEFINED =
-# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
-# doxygen's preprocessor will remove all references to function-like macros
-# that are alone on a line, have an all uppercase name, and do not end with a
-# semicolon, because these will confuse the parser if not removed.
+# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will
+# remove all references to function-like macros that are alone on a line, have
+# an all uppercase name, and do not end with a semicolon. Such function macros
+# are typically used for boiler-plate code, and will confuse the parser if not
+# removed.
+# The default value is: YES.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-SKIP_FUNCTION_MACROS = YES
+SKIP_FUNCTION_MACROS = YES
#---------------------------------------------------------------------------
-# Configuration::additions related to external references
+# Configuration options related to external references
#---------------------------------------------------------------------------
-# The TAGFILES option can be used to specify one or more tagfiles. For each
-# tag file the location of the external documentation should be added. The
-# format of a tag file without this location is as follows:
-#
+# The TAGFILES tag can be used to specify one or more tag files. For each tag
+# file the location of the external documentation should be added. The format of
+# a tag file without this location is as follows:
# TAGFILES = file1 file2 ...
# Adding location for the tag files is done as follows:
-#
# TAGFILES = file1=loc1 "file2 = loc2" ...
-# where "loc1" and "loc2" can be relative or absolute paths
-# or URLs. Note that each tag file must have a unique name (where the name does
-# NOT include the path). If a tag file is not located in the directory in which
-# doxygen is run, you must also specify the path to the tagfile here.
+# where loc1 and loc2 can be relative or absolute paths or URLs. See the
+# section "Linking to external documentation" for more information about the use
+# of tag files.
+# Note: Each tag file must have a unique name (where the name does NOT include
+# the path). If a tag file is not located in the directory in which doxygen is
+# run, you must also specify the path to the tagfile here.
+
+TAGFILES =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create a
+# tag file that is based on the input files it reads. See section "Linking to
+# external documentation" for more information about the usage of tag files.
-TAGFILES =
### EDIT THIS ###
-# When a file name is specified after GENERATE_TAGFILE, doxygen will create
-# a tag file that is based on the input files it reads.
+GENERATE_TAGFILE =
-GENERATE_TAGFILE =
+# If the ALLEXTERNALS tag is set to YES, all external class will be listed in
+# the class index. If set to NO, only the inherited external classes will be
+# listed.
+# The default value is: NO.
-# If the ALLEXTERNALS tag is set to YES all external classes will be listed
-# in the class index. If set to NO only the inherited external classes
-# will be listed.
+ALLEXTERNALS = NO
-ALLEXTERNALS = NO
+# If the EXTERNAL_GROUPS tag is set to YES, all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will be
+# listed.
+# The default value is: YES.
-# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
-# in the modules index. If set to NO, only the current project's groups will
+EXTERNAL_GROUPS = NO
+
+# If the EXTERNAL_PAGES tag is set to YES, all external pages will be listed in
+# the related pages index. If set to NO, only the current project's pages will
# be listed.
+# The default value is: YES.
-EXTERNAL_GROUPS = NO
+#EXTERNAL_PAGES = YES
# The PERL_PATH should be the absolute path and name of the perl script
-# interpreter (i.e. the result of `which perl').
+# interpreter (i.e. the result of 'which perl').
+# The default file (with absolute path) is: /usr/bin/perl.
-PERL_PATH = /usr/bin/perl
+PERL_PATH = /usr/bin/perl
#---------------------------------------------------------------------------
# Configuration options related to the dot tool
#---------------------------------------------------------------------------
-# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
-# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
-# or super classes. Setting the tag to NO turns the diagrams off. Note that
-# this option also works with HAVE_DOT disabled, but it is recommended to
-# install and use dot, since it yields more powerful graphs.
+# If the CLASS_DIAGRAMS tag is set to YES, doxygen will generate a class diagram
+# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to
+# NO turns the diagrams off. Note that this option also works with HAVE_DOT
+# disabled, but it is recommended to install and use dot, since it yields more
+# powerful graphs.
+# The default value is: YES.
-CLASS_DIAGRAMS = YES
+CLASS_DIAGRAMS = YES
# You can define message sequence charts within doxygen comments using the \msc
-# command. Doxygen will then run the mscgen tool (see
-# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
+# command. Doxygen will then run the mscgen tool (see:
+# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the
# documentation. The MSCGEN_PATH tag allows you to specify the directory where
# the mscgen tool resides. If left empty the tool is assumed to be found in the
# default search path.
-MSCGEN_PATH =
+MSCGEN_PATH =
-# If set to YES, the inheritance and collaboration graphs will hide
-# inheritance and usage relations if the target is undocumented
-# or is not a class.
+# You can include diagrams made with dia in doxygen documentation. Doxygen will
+# then run dia to produce the diagram and insert it in the documentation. The
+# DIA_PATH tag allows you to specify the directory where the dia binary resides.
+# If left empty dia is assumed to be found in the default search path.
-HIDE_UNDOC_RELATIONS = YES
+#DIA_PATH =
+
+# If set to YES the inheritance and collaboration graphs will hide inheritance
+# and usage relations if the target is undocumented or is not a class.
+# The default value is: YES.
+
+HIDE_UNDOC_RELATIONS = YES
# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
-# available from the path. This tool is part of Graphviz, a graph visualization
-# toolkit from AT&T and Lucent Bell Labs. The other options in this section
-# have no effect if this option is set to NO (the default)
+# available from the path. This tool is part of Graphviz (see:
+# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent
+# Bell Labs. The other options in this section have no effect if this option is
+# set to NO
+# The default value is: NO.
-HAVE_DOT = NO
+HAVE_DOT = NO
-# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
-# allowed to run in parallel. When set to 0 (the default) doxygen will
-# base this on the number of processors available in the system. You can set it
-# explicitly to a value larger than 0 to get control over the balance
-# between CPU load and processing speed.
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed
+# to run in parallel. When set to 0 doxygen will base this on the number of
+# processors available in the system. You can set it explicitly to a value
+# larger than 0 to get control over the balance between CPU load and processing
+# speed.
+# Minimum value: 0, maximum value: 32, default value: 0.
+# This tag requires that the tag HAVE_DOT is set to YES.
-DOT_NUM_THREADS = 0
+DOT_NUM_THREADS = 0
-# By default doxygen will use the Helvetica font for all dot files that
-# doxygen generates. When you want a differently looking font you can specify
-# the font name using DOT_FONTNAME. You need to make sure dot is able to find
-# the font, which can be done by putting it in a standard location or by setting
-# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the
-# directory containing the font.
+# When you want a differently looking font in the dot files that doxygen
+# generates you can specify the font name using DOT_FONTNAME. You need to make
+# sure dot is able to find the font, which can be done by putting it in a
+# standard location or by setting the DOTFONTPATH environment variable or by
+# setting DOT_FONTPATH to the directory containing the font.
+# The default value is: Helvetica.
+# This tag requires that the tag HAVE_DOT is set to YES.
-DOT_FONTNAME = Helvetica
+DOT_FONTNAME = Helvetica
-# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.
-# The default size is 10pt.
+# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of
+# dot graphs.
+# Minimum value: 4, maximum value: 24, default value: 10.
+# This tag requires that the tag HAVE_DOT is set to YES.
-DOT_FONTSIZE = 10
+DOT_FONTSIZE = 10
-# By default doxygen will tell dot to use the Helvetica font.
-# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to
-# set the path where dot can find it.
+# By default doxygen will tell dot to use the default font as specified with
+# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set
+# the path where dot can find it using this tag.
+# This tag requires that the tag HAVE_DOT is set to YES.
-DOT_FONTPATH =
+DOT_FONTPATH =
-# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
-# will generate a graph for each documented class showing the direct and
-# indirect inheritance relations. Setting this tag to YES will force the
-# CLASS_DIAGRAMS tag to NO.
+# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for
+# each documented class showing the direct and indirect inheritance relations.
+# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
-CLASS_GRAPH = YES
+CLASS_GRAPH = YES
-# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
-# will generate a graph for each documented class showing the direct and
-# indirect implementation dependencies (inheritance, containment, and
-# class references variables) of the class with other documented classes.
+# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a
+# graph for each documented class showing the direct and indirect implementation
+# dependencies (inheritance, containment, and class references variables) of the
+# class with other documented classes.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
-COLLABORATION_GRAPH = YES
+COLLABORATION_GRAPH = YES
-# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
-# will generate a graph for groups, showing the direct groups dependencies
+# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for
+# groups, showing the direct groups dependencies.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
-GROUP_GRAPHS = YES
+GROUP_GRAPHS = YES
-# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
+# If the UML_LOOK tag is set to YES, doxygen will generate inheritance and
# collaboration diagrams in a style similar to the OMG's Unified Modeling
# Language.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
-UML_LOOK = NO
+UML_LOOK = NO
-# If the UML_LOOK tag is enabled, the fields and methods are shown inside
-# the class node. If there are many fields or methods and many nodes the
-# graph may become too big to be useful. The UML_LIMIT_NUM_FIELDS
-# threshold limits the number of items for each type to make the size more
-# managable. Set this to 0 for no limit. Note that the threshold may be
-# exceeded by 50% before the limit is enforced.
+# If the UML_LOOK tag is enabled, the fields and methods are shown inside the
+# class node. If there are many fields or methods and many nodes the graph may
+# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the
+# number of items for each type to make the size more manageable. Set this to 0
+# for no limit. Note that the threshold may be exceeded by 50% before the limit
+# is enforced. So when you set the threshold to 10, up to 15 fields may appear,
+# but if the number exceeds 15, the total amount of fields shown is limited to
+# 10.
+# Minimum value: 0, maximum value: 100, default value: 10.
+# This tag requires that the tag HAVE_DOT is set to YES.
-UML_LIMIT_NUM_FIELDS = 10
+UML_LIMIT_NUM_FIELDS = 10
-# If set to YES, the inheritance and collaboration graphs will show the
-# relations between templates and their instances.
+# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and
+# collaboration graphs will show the relations between templates and their
+# instances.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
-TEMPLATE_RELATIONS = NO
+TEMPLATE_RELATIONS = NO
-# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
-# tags are set to YES then doxygen will generate a graph for each documented
-# file showing the direct and indirect include dependencies of the file with
-# other documented files.
+# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to
+# YES then doxygen will generate a graph for each documented file showing the
+# direct and indirect include dependencies of the file with other documented
+# files.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
-INCLUDE_GRAPH = YES
+INCLUDE_GRAPH = YES
-# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
-# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
-# documented header file showing the documented files that directly or
-# indirectly include this file.
+# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are
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+# files.
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-INCLUDED_BY_GRAPH = YES
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-# or class method. Note that enabling this option will significantly increase
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-# for selected functions only using the \callgraph command.
+# If the CALL_GRAPH tag is set to YES then doxygen will generate a call
+# dependency graph for every global function or class method.
+#
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable call graphs for selected
+# functions only using the \callgraph command. Disabling a call graph can be
+# accomplished by means of the command \hidecallgraph.
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+# This tag requires that the tag HAVE_DOT is set to YES.
-CALL_GRAPH = NO
+CALL_GRAPH = NO
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-# or class method. Note that enabling this option will significantly increase
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-# graphs for selected functions only using the \callergraph command.
+# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller
+# dependency graph for every global function or class method.
+#
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable caller graphs for selected
+# functions only using the \callergraph command. Disabling a caller graph can be
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+CALLER_GRAPH = NO
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-# will generate a graphical hierarchy of all classes instead of a textual one.
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+GRAPHICAL_HIERARCHY = YES
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+# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the
+# dependencies a directory has on other directories in a graphical way. The
+# dependency relations are determined by the #include relations between the
+# files in the directories.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
-DIRECTORY_GRAPH = YES
+DIRECTORY_GRAPH = YES
# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
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-# If left blank png will be used. If you choose svg you need to set
-# HTML_FILE_EXTENSION to xhtml in order to make the SVG files
-# visible in IE 9+ (other browsers do not have this requirement).
+# generated by dot. For an explanation of the image formats see the section
+# output formats in the documentation of the dot tool (Graphviz (see:
+# http://www.graphviz.org/)).
+# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order
+# to make the SVG files visible in IE 9+ (other browsers do not have this
+# requirement).
+# Possible values are: png, jpg, gif, svg, png:gd, png:gd:gd, png:cairo,
+# png:cairo:gd, png:cairo:cairo, png:cairo:gdiplus, png:gdiplus and
+# png:gdiplus:gdiplus.
+# The default value is: png.
+# This tag requires that the tag HAVE_DOT is set to YES.
-DOT_IMAGE_FORMAT = svg
+DOT_IMAGE_FORMAT = svg
# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to
# enable generation of interactive SVG images that allow zooming and panning.
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-# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you
-# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files
-# visible. Older versions of IE do not have SVG support.
+#
+# Note that this requires a modern browser other than Internet Explorer. Tested
+# and working are Firefox, Chrome, Safari, and Opera.
+# Note: For IE 9+ you need to set HTML_FILE_EXTENSION to xhtml in order to make
+# the SVG files visible. Older versions of IE do not have SVG support.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
-INTERACTIVE_SVG = NO
+INTERACTIVE_SVG = NO
-# The tag DOT_PATH can be used to specify the path where the dot tool can be
+# The DOT_PATH tag can be used to specify the path where the dot tool can be
# found. If left blank, it is assumed the dot tool can be found in the path.
+# This tag requires that the tag HAVE_DOT is set to YES.
-DOT_PATH =
+DOT_PATH =
# The DOTFILE_DIRS tag can be used to specify one or more directories that
-# contain dot files that are included in the documentation (see the
-# \dotfile command).
+# contain dot files that are included in the documentation (see the \dotfile
+# command).
+# This tag requires that the tag HAVE_DOT is set to YES.
-DOTFILE_DIRS =
+DOTFILE_DIRS =
# The MSCFILE_DIRS tag can be used to specify one or more directories that
-# contain msc files that are included in the documentation (see the
-# \mscfile command).
+# contain msc files that are included in the documentation (see the \mscfile
+# command).
-MSCFILE_DIRS =
+MSCFILE_DIRS =
-# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
-# nodes that will be shown in the graph. If the number of nodes in a graph
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-# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
-# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+# The DIAFILE_DIRS tag can be used to specify one or more directories that
+# contain dia files that are included in the documentation (see the \diafile
+# command).
-DOT_GRAPH_MAX_NODES = 50
+#DIAFILE_DIRS =
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-# graphs generated by dot. A depth value of 3 means that only nodes reachable
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-# that lay further from the root node will be omitted. Note that setting this
-# option to 1 or 2 may greatly reduce the computation time needed for large
-# code bases. Also note that the size of a graph can be further restricted by
+# When using plantuml, the PLANTUML_JAR_PATH tag should be used to specify the
+# path where java can find the plantuml.jar file. If left blank, it is assumed
+# PlantUML is not used or called during a preprocessing step. Doxygen will
+# generate a warning when it encounters a \startuml command in this case and
+# will not generate output for the diagram.
+
+#PLANTUML_JAR_PATH =
+
+# When using plantuml, the PLANTUML_CFG_FILE tag can be used to specify a
+# configuration file for plantuml.
+
+#PLANTUML_CFG_FILE =
+
+# When using plantuml, the specified paths are searched for files specified by
+# the !include statement in a plantuml block.
+
+#PLANTUML_INCLUDE_PATH =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of nodes
+# that will be shown in the graph. If the number of nodes in a graph becomes
+# larger than this value, doxygen will truncate the graph, which is visualized
+# by representing a node as a red box. Note that doxygen if the number of direct
+# children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note that
+# the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+# Minimum value: 0, maximum value: 10000, default value: 50.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_GRAPH_MAX_NODES = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the graphs
+# generated by dot. A depth value of 3 means that only nodes reachable from the
+# root by following a path via at most 3 edges will be shown. Nodes that lay
+# further from the root node will be omitted. Note that setting this option to 1
+# or 2 may greatly reduce the computation time needed for large code bases. Also
+# note that the size of a graph can be further restricted by
# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+# Minimum value: 0, maximum value: 1000, default value: 0.
+# This tag requires that the tag HAVE_DOT is set to YES.
-MAX_DOT_GRAPH_DEPTH = 0
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-# seem to support this out of the box. Warning: Depending on the platform used,
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-# a graph (i.e. they become hard to read).
+# background. This is disabled by default, because dot on Windows does not seem
+# to support this out of the box.
+#
+# Warning: Depending on the platform used, enabling this option may lead to
+# badly anti-aliased labels on the edges of a graph (i.e. they become hard to
+# read).
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
-DOT_TRANSPARENT = NO
+DOT_TRANSPARENT = NO
-# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output
+# Set the DOT_MULTI_TARGETS tag to YES to allow dot to generate multiple output
# files in one run (i.e. multiple -o and -T options on the command line). This
-# makes dot run faster, but since only newer versions of dot (>1.8.10)
-# support this, this feature is disabled by default.
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+# this, this feature is disabled by default.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
-DOT_MULTI_TARGETS = NO
+DOT_MULTI_TARGETS = NO
-# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
-# generate a legend page explaining the meaning of the various boxes and
-# arrows in the dot generated graphs.
+# If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page
+# explaining the meaning of the various boxes and arrows in the dot generated
+# graphs.
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+# This tag requires that the tag HAVE_DOT is set to YES.
-GENERATE_LEGEND = YES
+GENERATE_LEGEND = YES
-# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
-# remove the intermediate dot files that are used to generate
-# the various graphs.
+# If the DOT_CLEANUP tag is set to YES, doxygen will remove the intermediate dot
+# files that are used to generate the various graphs.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
-DOT_CLEANUP = YES
+DOT_CLEANUP = YES
diff --git a/third_party/NordicSemiconductor/nrfx/doc/nrfx_api.dox b/third_party/NordicSemiconductor/nrfx/doc/nrfx_api.dox
index 0de2dcc89..3020a4351 100644
--- a/third_party/NordicSemiconductor/nrfx/doc/nrfx_api.dox
+++ b/third_party/NordicSemiconductor/nrfx/doc/nrfx_api.dox
@@ -2,6 +2,9 @@
@defgroup nrfx_drivers Drivers
@{
@brief List of all drivers available in nrfx.
+
+@defgroup nrf_aar AAR
+
@defgroup nrf_adc ADC
@defgroup nrf_acl ACL
@@ -18,6 +21,8 @@
@defgroup nrf_ecb ECB
+@defgroup nrf_ficr FICR
+
@defgroup nrf_gpio GPIO
@defgroup nrf_gpiote GPIOTE
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrf_bitmask.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrf_bitmask.h
index 9b71271de..2fa69acc6 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrf_bitmask.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrf_bitmask.h
@@ -45,14 +45,17 @@ extern "C" {
* @brief Bitmask managing module.
*/
+/** @brief Macro for getting index of byte in byte stream where @c abs_bit is put. */
#define BITMASK_BYTE_GET(abs_bit) ((abs_bit)/8)
+
+/** @brief Macro for getting relative index of bit in byte. */
#define BITMASK_RELBIT_GET(abs_bit) ((abs_bit) & 0x00000007)
/**
- * Function for checking if bit in the multi-byte bit mask is set.
+ * @brief Function for checking if bit in the multi-byte bit mask is set.
*
- * @param bit Bit index.
- * @param p_mask A pointer to mask with bit fields.
+ * @param[in] bit Bit index.
+ * @param[in] p_mask Pointer to mask with bit fields.
*
* @return 0 if bit is not set, positive value otherwise.
*/
@@ -65,10 +68,10 @@ __STATIC_INLINE uint32_t nrf_bitmask_bit_is_set(uint32_t bit, void const * p_mas
}
/**
- * Function for setting a bit in the multi-byte bit mask.
+ * @brief Function for setting a bit in the multi-byte bit mask.
*
- * @param bit Bit index.
- * @param p_mask A pointer to mask with bit fields.
+ * @param[in] bit Bit index.
+ * @param[in] p_mask Pointer to mask with bit fields.
*/
__STATIC_INLINE void nrf_bitmask_bit_set(uint32_t bit, void * p_mask)
{
@@ -79,10 +82,10 @@ __STATIC_INLINE void nrf_bitmask_bit_set(uint32_t bit, void * p_mask)
}
/**
- * Function for clearing a bit in the multi-byte bit mask.
+ * @brief Function for clearing a bit in the multi-byte bit mask.
*
- * @param bit Bit index.
- * @param p_mask A pointer to mask with bit fields.
+ * @param[in] bit Bit index.
+ * @param[in] p_mask Pointer to mask with bit fields.
*/
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
@@ -93,12 +96,12 @@ __STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
}
/**
- * Function for performing bitwise OR operation on two multi-byte bit masks.
+ * @brief Function for performing bitwise OR operation on two multi-byte bit masks.
*
- * @param p_mask1 A pointer to the first bit mask.
- * @param p_mask2 A pointer to the second bit mask.
- * @param p_out_mask A pointer to the output bit mask.
- * @param length Length of output mask in bytes.
+ * @param[in] p_mask1 Pointer to the first bit mask.
+ * @param[in] p_mask2 Pointer to the second bit mask.
+ * @param[in] p_out_mask Pointer to the output bit mask.
+ * @param[in] length Length of output mask in bytes.
*/
__STATIC_INLINE void nrf_bitmask_masks_or(void const * p_mask1,
void const * p_mask2,
@@ -116,12 +119,12 @@ __STATIC_INLINE void nrf_bitmask_masks_or(void const * p_mask1,
}
/**
- * Function for performing bitwise AND operation on two multi-byte bit masks.
+ * @brief Function for performing bitwise AND operation on two multi-byte bit masks.
*
- * @param p_mask1 A pointer to the first bit mask.
- * @param p_mask2 A pointer to the second bit mask.
- * @param p_out_mask A pointer to the output bit mask.
- * @param length Length of output mask in bytes.
+ * @param[in] p_mask1 Pointer to the first bit mask.
+ * @param[in] p_mask2 Pointer to the second bit mask.
+ * @param[in] p_out_mask Pointer to the output bit mask.
+ * @param[in] length Length of output mask in bytes.
*/
__STATIC_INLINE void nrf_bitmask_masks_and(void const * p_mask1,
void const * p_mask2,
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_adc.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_adc.h
index 589fed724..a042d87fd 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_adc.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_adc.h
@@ -46,35 +46,27 @@ extern "C" {
* @brief Analog-to-Digital Converter (ADC) peripheral driver.
*/
-/**
- * @brief Driver event types.
- */
+/** @brief Driver event types. */
typedef enum
{
NRFX_ADC_EVT_DONE, ///< Event generated when the buffer is filled with samples.
NRFX_ADC_EVT_SAMPLE, ///< Event generated when the requested channel is sampled.
} nrfx_adc_evt_type_t;
-/**
- * @brief Analog-to-digital converter driver DONE event.
- */
+/** @brief ADC driver DONE event structure. */
typedef struct
{
nrf_adc_value_t * p_buffer; ///< Pointer to the buffer with converted samples.
uint16_t size; ///< Number of samples in the buffer.
} nrfx_adc_done_evt_t;
-/**
- * @brief Analog-to-digital converter driver SAMPLE event.
- */
+/** @brief SAMPLE event structure. */
typedef struct
{
nrf_adc_value_t sample; ///< Converted sample.
} nrfx_adc_sample_evt_t;
-/**
- * @brief Analog-to-digital converter driver event.
- */
+/** @brief ADC driver event. */
typedef struct
{
nrfx_adc_evt_type_t type; ///< Event type.
@@ -82,10 +74,10 @@ typedef struct
{
nrfx_adc_done_evt_t done; ///< Data for DONE event.
nrfx_adc_sample_evt_t sample; ///< Data for SAMPLE event.
- } data;
+ } data; ///< Union to store event data.
} nrfx_adc_evt_t;
-/**@brief Macro for initializing the ADC channel with the default configuration. */
+/** @brief Macro for initializing the ADC channel with the default configuration. */
#define NRFX_ADC_DEFAULT_CHANNEL(analog_input) \
{ \
NULL, \
@@ -98,7 +90,7 @@ typedef struct
} \
}
-// Forward declaration of the nrfx_adc_channel_t type.
+/** @brief Forward declaration of the nrfx_adc_channel_t type. */
typedef struct nrfx_adc_channel_s nrfx_adc_channel_t;
/**
@@ -113,9 +105,7 @@ struct nrfx_adc_channel_s
nrf_adc_config_t config; ///< ADC configuration for the current channel.
};
-/**
- * @brief ADC configuration.
- */
+/** @brief ADC configuration. */
typedef struct
{
uint8_t interrupt_priority; ///< Priority of ADC interrupt.
@@ -142,11 +132,11 @@ typedef void (*nrfx_adc_event_handler_t)(nrfx_adc_evt_t const * p_event);
* If a valid event handler is provided, the driver is initialized in non-blocking mode.
* If event_handler is NULL, the driver works in blocking mode.
*
- * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] event_handler Event handler provided by the user.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver is already initialized.
*/
nrfx_err_t nrfx_adc_init(nrfx_adc_config_t const * p_config,
nrfx_adc_event_handler_t event_handler);
@@ -169,6 +159,8 @@ void nrfx_adc_uninit(void);
*
* @note The channel instance variable @p p_channel is used by the driver as an item
* in a list. Therefore, it cannot be an automatic variable that is located on the stack.
+ *
+ * @param[in] p_channel Pointer to the channel instance.
*/
void nrfx_adc_channel_enable(nrfx_adc_channel_t * const p_channel);
@@ -177,6 +169,8 @@ void nrfx_adc_channel_enable(nrfx_adc_channel_t * const p_channel);
*
* This function can be called only when there is no conversion in progress
* (the ADC is not busy).
+ *
+ * @param p_channel Pointer to the channel instance.
*/
void nrfx_adc_channel_disable(nrfx_adc_channel_t * const p_channel);
@@ -206,11 +200,11 @@ void nrfx_adc_sample(void);
* fail if ADC is busy. The channel does not need to be enabled to perform a single conversion.
*
* @param[in] p_channel Channel.
- * @param[out] p_value Pointer to the location where the result should be placed. Unless NULL is
+ * @param[out] p_value Pointer to the location where the result is to be placed. Unless NULL is
* provided, the function is blocking.
*
- * @retval NRFX_SUCCESS If conversion was successful.
- * @retval NRFX_ERROR_BUSY If the ADC driver is busy.
+ * @retval NRFX_SUCCESS Conversion was successful.
+ * @retval NRFX_ERROR_BUSY The ADC driver is busy.
*/
nrfx_err_t nrfx_adc_sample_convert(nrfx_adc_channel_t const * const p_channel,
nrf_adc_value_t * p_value);
@@ -241,16 +235,16 @@ nrfx_err_t nrfx_adc_sample_convert(nrfx_adc_channel_t const * const p_channel,
* @param[in] buffer Result buffer.
* @param[in] size Buffer size in samples.
*
- * @retval NRFX_SUCCESS If conversion was successful.
- * @retval NRFX_ERROR_BUSY If the driver is busy.
+ * @retval NRFX_SUCCESS Conversion was successful.
+ * @retval NRFX_ERROR_BUSY The driver is busy.
*/
nrfx_err_t nrfx_adc_buffer_convert(nrf_adc_value_t * buffer, uint16_t size);
/**
* @brief Function for retrieving the ADC state.
*
- * @retval true If the ADC is busy.
- * @retval false If the ADC is ready.
+ * @retval true The ADC is busy.
+ * @retval false The ADC is ready.
*/
bool nrfx_adc_is_busy(void);
@@ -273,12 +267,12 @@ __STATIC_INLINE uint32_t nrfx_adc_start_task_get(void)
#endif
+/** @} */
+
void nrfx_adc_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_clock.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_clock.h
index 0e6cd9812..c782b0280 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_clock.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_clock.h
@@ -47,9 +47,7 @@ extern "C" {
* @brief CLOCK peripheral driver.
*/
-/**
- * @brief Clock events.
- */
+/** @brief Clock events. */
typedef enum
{
NRFX_CLOCK_EVT_HFCLK_STARTED, ///< HFCLK has been started.
@@ -61,7 +59,7 @@ typedef enum
/**
* @brief Clock event handler.
*
- * @param[in] event Event.
+ * @param[in] event Event.
*/
typedef void (*nrfx_clock_event_handler_t)(nrfx_clock_evt_type_t event);
@@ -73,71 +71,57 @@ typedef void (*nrfx_clock_event_handler_t)(nrfx_clock_evt_type_t event);
* @param[in] event_handler Event handler provided by the user.
* Must not be NULL.
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_ALREADY_INITIALIZED If the driver was already initialized.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_ALREADY_INITIALIZED The driver is already initialized.
*/
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler);
-/**
- * @brief Function for enabling interrupts in the clock module.
- */
+/** @brief Function for enabling interrupts in the clock module. */
void nrfx_clock_enable(void);
-/**
- * @brief Function for disabling interrupts in the clock module.
- */
+/** @brief Function for disabling interrupts in the clock module. */
void nrfx_clock_disable(void);
-/**
- * @brief Function for uninitializing the clock module.
- */
+/** @brief Function for uninitializing the clock module. */
void nrfx_clock_uninit(void);
-/**
- * @brief Function for starting the LFCLK.
- */
+/** @brief Function for starting the LFCLK. */
void nrfx_clock_lfclk_start(void);
-/**
- * @brief Function for stoping the LFCLK.
- */
+/** @brief Function for stopping the LFCLK. */
void nrfx_clock_lfclk_stop(void);
/**
* @brief Function for checking the LFCLK state.
*
- * @retval true If the LFCLK is running.
- * @retval false If the LFCLK is not running.
+ * @retval true The LFCLK is running.
+ * @retval false The LFCLK is not running.
*/
__STATIC_INLINE bool nrfx_clock_lfclk_is_running(void);
-/**
- * @brief Function for starting the high-accuracy source HFCLK.
- */
+/** @brief Function for starting the high-accuracy source HFCLK. */
void nrfx_clock_hfclk_start(void);
-/**
- * @brief Function for stoping external high-accuracy source HFCLK.
- */
+/** @brief Function for stopping the external high-accuracy source HFCLK. */
void nrfx_clock_hfclk_stop(void);
/**
* @brief Function for checking the HFCLK state.
*
- * @retval true If the HFCLK is running (XTAL source).
- * @retval false If the HFCLK is not running.
+ * @retval true The HFCLK is running (XTAL source).
+ * @retval false The HFCLK is not running.
*/
__STATIC_INLINE bool nrfx_clock_hfclk_is_running(void);
/**
- * @brief Function for starting calibration of internal LFCLK.
+ * @brief Function for starting the calibration of internal LFCLK.
*
* This function starts the calibration process. The process cannot be aborted. LFCLK and HFCLK
* must be running before this function is called.
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the low-frequency of high-frequency clock is off.
- * @retval NRFX_ERROR_BUSY If calibration is in progress.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_INVALID_STATE The low-frequency of high-frequency clock is off.
+ * @retval NRFX_ERROR_BUSY Clock is in the calibration phase.
*/
nrfx_err_t nrfx_clock_calibration_start(void);
@@ -146,35 +130,34 @@ nrfx_err_t nrfx_clock_calibration_start(void);
*
* This function indicates that the system is in calibration phase.
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_BUSY If calibration is in progress.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_BUSY Clock is in the calibration phase.
*/
nrfx_err_t nrfx_clock_is_calibrating(void);
/**
* @brief Function for starting calibration timer.
- * @param interval Time after which the CTTO event and interrupt will be generated (in 0.25 s units).
+ *
+ * @param[in] interval Time after which the CTTO event and interrupt will be generated (in 0.25 s units).
*/
void nrfx_clock_calibration_timer_start(uint8_t interval);
-/**
- * @brief Function for stoping calibration timer.
- */
+/** @brief Function for stopping the calibration timer. */
void nrfx_clock_calibration_timer_stop(void);
/**@brief Function for returning a requested task address for the clock driver module.
*
- * @param[in] task One of the peripheral tasks.
+ * @param[in] task One of the peripheral tasks.
*
- * @return Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task);
/**@brief Function for returning a requested event address for the clock driver module.
*
- * @param[in] event One of the peripheral events.
+ * @param[in] event One of the peripheral events.
*
- * @return Event address.
+ * @return Event address.
*/
__STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event);
@@ -201,12 +184,12 @@ __STATIC_INLINE bool nrfx_clock_lfclk_is_running(void)
}
#endif //SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
void nrfx_clock_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_comp.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_comp.h
index 1089d8393..91efd4250 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_comp.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_comp.h
@@ -47,19 +47,20 @@ extern "C" {
*/
/**
- * @brief Macro to convert the threshold voltage to an integer value
+ * @brief Macro for converting the threshold voltage to an integer value
* (needed by the COMP_TH register).
*
- * @param[in] vol Voltage to be changed to COMP_TH register value. This value
- * must not be smaller than reference voltage divided by 64.
- * @param[in] ref Reference voltage.
+ * @param[in] vol Voltage to be changed to COMP_TH register value. This value
+ * must not be smaller than reference voltage divided by 64.
+ * @param[in] ref Reference voltage.
*/
#define NRFX_VOLTAGE_THRESHOLD_TO_INT(vol, ref) \
(uint8_t)(((vol) > ((ref) / 64)) ? (NRFX_ROUNDED_DIV((vol) * 64,(ref)) - 1) : 0)
/**
* @brief COMP event handler function type.
- * @param[in] event COMP event.
+ *
+ * @param[in] event COMP event.
*/
typedef void (* nrfx_comp_event_handler_t)(nrf_comp_event_t event);
@@ -88,7 +89,7 @@ typedef struct
nrf_comp_main_mode_t main_mode; /**< Main operation mode. */
nrf_comp_th_t threshold; /**< Structure holding THDOWN and THUP values needed by the COMP_TH register. */
nrf_comp_sp_mode_t speed_mode; /**< Speed and power mode. */
- nrf_comp_hyst_t hyst; /**< Comparator hysteresis.*/
+ nrf_comp_hyst_t hyst; /**< Comparator hysteresis. */
#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__)
nrf_isource_t isource; /**< Current source selected on analog input. */
#endif
@@ -108,6 +109,7 @@ typedef struct
#define NRFX_COMP_DEFAULT_CONFIG(_input) \
{ \
.reference = (nrf_comp_ref_t)NRFX_COMP_CONFIG_REF, \
+ .ext_ref = NRF_COMP_EXT_REF_0, \
.main_mode = (nrf_comp_main_mode_t)NRFX_COMP_CONFIG_MAIN_MODE, \
.threshold = NRFX_COMP_CONFIG_TH, \
.speed_mode = (nrf_comp_sp_mode_t)NRFX_COMP_CONFIG_SPEED_MODE, \
@@ -120,6 +122,7 @@ typedef struct
#define NRFX_COMP_DEFAULT_CONFIG(_input) \
{ \
.reference = (nrf_comp_ref_t)NRFX_COMP_CONFIG_REF, \
+ .ext_ref = NRF_COMP_EXT_REF_0, \
.main_mode = (nrf_comp_main_mode_t)NRFX_COMP_CONFIG_MAIN_MODE, \
.threshold = NRFX_COMP_CONFIG_TH, \
.speed_mode = (nrf_comp_sp_mode_t)NRFX_COMP_CONFIG_SPEED_MODE, \
@@ -135,35 +138,34 @@ typedef struct
* This function initializes the COMP driver, but does not enable the peripheral or any interrupts.
* To start the driver, call the function @ref nrfx_comp_start() after initialization.
*
- * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] event_handler Event handler provided by the user.
* Must not be NULL.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver has already been initialized.
- * @retval NRFX_ERROR_BUSY If the LPCOMP peripheral is already in use.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver has already been initialized.
+ * @retval NRFX_ERROR_BUSY The LPCOMP peripheral is already in use.
* This is possible only if @ref nrfx_prs module
* is enabled.
*/
nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config,
nrfx_comp_event_handler_t event_handler);
-
/**
- * @brief Function for uninitializing the COMP driver.
+ * @brief Function for uninitializing the COMP driver.
*
- * This function uninitializes the COMP driver. The COMP peripheral and
- * its interrupts are disabled, and local variables are cleaned. After this call, you must
- * initialize the driver again by calling nrfx_comp_init() if you want to use it.
+ * This function uninitializes the COMP driver. The COMP peripheral and
+ * its interrupts are disabled, and local variables are cleaned. After this call, you must
+ * initialize the driver again by calling nrfx_comp_init() if you want to use it.
*
- * @sa nrfx_comp_stop()
+ * @sa nrfx_comp_stop
*/
void nrfx_comp_uninit(void);
/**
* @brief Function for setting the analog input.
*
- * @param[in] psel COMP analog pin selection.
+ * @param[in] psel COMP analog pin selection.
*/
void nrfx_comp_pin_select(nrf_comp_input_t psel);
@@ -173,38 +175,37 @@ void nrfx_comp_pin_select(nrf_comp_input_t psel);
* Before calling this function, the driver must be initialized. This function
* enables the COMP peripheral and its interrupts.
*
- * @param[in] comp_evt_en_mask Mask of events to be enabled. This parameter should be built as
- * 'or' of elements from @ref nrfx_comp_evt_en_mask_t.
- * @param[in] comp_shorts_mask Mask of shorts to be enabled. This parameter should be built as
- * 'or' of elements from @ref nrfx_comp_short_mask_t.
- *
- * @sa nrfx_comp_init()
+ * @param[in] comp_evt_en_mask Mask of events to be enabled. This parameter is to be built as
+ * an OR of elements from @ref nrfx_comp_evt_en_mask_t.
+ * @param[in] comp_shorts_mask Mask of shortcuts to be enabled. This parameter is to be built as
+ * an OR of elements from @ref nrfx_comp_short_mask_t.
*
+ * @sa nrfx_comp_init
*/
void nrfx_comp_start(uint32_t comp_evt_en_mask, uint32_t comp_shorts_mask);
-/**@brief Function for stopping the COMP peripheral.
+/**
+ * @brief Function for stopping the COMP peripheral.
*
* Before calling this function, the driver must be enabled. This function disables the COMP
* peripheral and its interrupts.
*
- * @sa nrfx_comp_uninit()
- *
+ * @sa nrfx_comp_uninit
*/
void nrfx_comp_stop(void);
/**
* @brief Function for copying the current state of the comparator result to the RESULT register.
*
- * @retval 0 If the input voltage is below the threshold (VIN+ < VIN-).
- * @retval 1 If the input voltage is above the threshold (VIN+ > VIN-).
+ * @retval 0 The input voltage is below the threshold (VIN+ < VIN-).
+ * @retval 1 The input voltage is above the threshold (VIN+ > VIN-).
*/
uint32_t nrfx_comp_sample(void);
/**
* @brief Function for getting the address of a COMP task.
*
- * @param[in] task COMP task.
+ * @param[in] task COMP task.
*
* @return Address of the given COMP task.
*/
@@ -225,12 +226,12 @@ __STATIC_INLINE uint32_t nrfx_comp_event_address_get(nrf_comp_event_t event)
return (uint32_t)nrf_comp_event_address_get(event);
}
+/** @} */
+
void nrfx_comp_irq_handler(void);
-/** @} **/
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_dppi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_dppi.h
index d4dcbb5c6..84b1715ba 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_dppi.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_dppi.h
@@ -55,8 +55,8 @@ void nrfx_dppi_free(void);
*
* @param[out] p_channel Pointer to the DPPI channel number that has been allocated.
*
- * @retval NRFX_SUCCESS If the channel was successfully allocated.
- * @retval NRFX_ERROR_NO_MEM If there is no available channel to be used.
+ * @retval NRFX_SUCCESS The channel was successfully allocated.
+ * @retval NRFX_ERROR_NO_MEM There is no available channel to be used.
*/
nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel);
@@ -66,8 +66,8 @@ nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel);
*
* @param[in] channel DPPI channel to be freed.
*
- * @retval NRFX_SUCCESS If the channel was successfully freed.
- * @retval NRFX_ERROR_INVALID_PARAM If the specified channel is not allocated.
+ * @retval NRFX_SUCCESS The channel was successfully freed.
+ * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated.
*/
nrfx_err_t nrfx_dppi_channel_free(uint8_t channel);
@@ -76,8 +76,8 @@ nrfx_err_t nrfx_dppi_channel_free(uint8_t channel);
*
* @param[in] channel DPPI channel to be enabled.
*
- * @retval NRFX_SUCCESS If the channel was successfully enabled.
- * @retval NRFX_ERROR_INVALID_PARAM If the specified channel is not allocated.
+ * @retval NRFX_SUCCESS The channel was successfully enabled.
+ * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated.
*/
nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel);
@@ -86,8 +86,8 @@ nrfx_err_t nrfx_dppi_channel_enable(uint8_t channel);
*
* @param[in] channel DPPI channel to be disabled.
*
- * @retval NRFX_SUCCESS If the channel was successfully disabled.
- * @retval NRFX_ERROR_INVALID_PARAM If the specified channel is not allocated.
+ * @retval NRFX_SUCCESS The channel was successfully disabled.
+ * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated.
*/
nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel);
@@ -97,8 +97,8 @@ nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel);
*
* @param[out] p_group Pointer to the DPPI channel group that has been allocated.
*
- * @retval NRFX_SUCCESS If the channel group was successfully allocated.
- * @retval NRFX_ERROR_NO_MEM If there is no available channel group to be used.
+ * @retval NRFX_SUCCESS The channel group was successfully allocated.
+ * @retval NRFX_ERROR_NO_MEM There is no available channel group to be used.
*/
nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group);
@@ -108,8 +108,8 @@ nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group);
*
* @param[in] group DPPI channel group to be freed.
*
- * @retval NRFX_SUCCESS If the channel group was successfully freed.
- * @retval NRFX_ERROR_INVALID_PARAM If the specified group is not allocated.
+ * @retval NRFX_SUCCESS The channel group was successfully freed.
+ * @retval NRFX_ERROR_INVALID_PARAM The specified group is not allocated.
*/
nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group);
@@ -119,8 +119,8 @@ nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group);
* @param[in] channel DPPI channel to be added.
* @param[in] group Channel group in which to include the channel.
*
- * @retval NRFX_SUCCESS If the channel was successfully included.
- * @retval NRFX_ERROR_INVALID_PARAM If the specified group or channel is not allocated.
+ * @retval NRFX_SUCCESS The channel was successfully included.
+ * @retval NRFX_ERROR_INVALID_PARAM The specified group or channel is not allocated.
*/
nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel,
nrf_dppi_channel_group_t group);
@@ -131,8 +131,8 @@ nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel,
* @param[in] channel DPPI channel to be removed.
* @param[in] group Channel group from which to remove the channel.
*
- * @retval NRFX_SUCCESS If the channel was successfully removed.
- * @retval NRFX_ERROR_INVALID_PARAM If the specified group or channel is not allocated.
+ * @retval NRFX_SUCCESS The channel was successfully removed.
+ * @retval NRFX_ERROR_INVALID_PARAM The specified group or channel is not allocated.
*/
nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel,
nrf_dppi_channel_group_t group);
@@ -142,8 +142,8 @@ nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel,
*
* @param[in] group Channel group to be cleared.
*
- * @retval NRFX_SUCCESS If the group was successfully cleared.
- * @retval NRFX_ERROR_INVALID_PARAM If the specified group is not allocated.
+ * @retval NRFX_SUCCESS The group was successfully cleared.
+ * @retval NRFX_ERROR_INVALID_PARAM The specified group is not allocated.
*/
nrfx_err_t nrfx_dppi_group_clear(nrf_dppi_channel_group_t group);
@@ -152,8 +152,8 @@ nrfx_err_t nrfx_dppi_group_clear(nrf_dppi_channel_group_t group);
*
* @param[in] group Channel group to be enabled.
*
- * @retval NRFX_SUCCESS If the group was successfully enabled.
- * @retval NRFX_ERROR_INVALID_PARAM If the specified group is not allocated.
+ * @retval NRFX_SUCCESS The group was successfully enabled.
+ * @retval NRFX_ERROR_INVALID_PARAM The specified group is not allocated.
*/
nrfx_err_t nrfx_dppi_group_enable(nrf_dppi_channel_group_t group);
@@ -162,8 +162,8 @@ nrfx_err_t nrfx_dppi_group_enable(nrf_dppi_channel_group_t group);
*
* @param[in] group Channel group to be disabled.
*
- * @retval NRFX_SUCCESS If the group was successfully disabled.
- * @retval NRFX_ERROR_INVALID_PARAM If the specified group is not allocated.
+ * @retval NRFX_SUCCESS The group was successfully disabled.
+ * @retval NRFX_ERROR_INVALID_PARAM The specified group is not allocated.
*/
nrfx_err_t nrfx_dppi_group_disable(nrf_dppi_channel_group_t group);
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_gpiote.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_gpiote.h
index e94d1f31c..126f0f57c 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_gpiote.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_gpiote.h
@@ -44,87 +44,102 @@ extern "C" {
* @defgroup nrfx_gpiote GPIOTE driver
* @{
* @ingroup nrf_gpiote
- * @brief GPIOTE peripheral driver.
+ * @brief GPIO Task Event (GPIOTE) peripheral driver.
*/
-/**@brief Input pin configuration. */
+/** @brief Input pin configuration. */
typedef struct
{
- nrf_gpiote_polarity_t sense; /**< Transition that triggers interrupt. */
+ nrf_gpiote_polarity_t sense; /**< Transition that triggers the interrupt. */
nrf_gpio_pin_pull_t pull; /**< Pulling mode. */
bool is_watcher : 1; /**< True when the input pin is tracking an output pin. */
bool hi_accuracy : 1; /**< True when high accuracy (IN_EVENT) is used. */
bool skip_gpio_setup : 1; /**< Do not change GPIO configuration */
} nrfx_gpiote_in_config_t;
-/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition.
- * @details Set hi_accu to true to use IN_EVENT. */
+/**
+ * @brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition.
+ * @details Set hi_accu to true to use IN_EVENT.
+ */
#define NRFX_GPIOTE_CONFIG_IN_SENSE_LOTOHI(hi_accu) \
- { \
- .is_watcher = false, \
- .hi_accuracy = hi_accu, \
- .pull = NRF_GPIO_PIN_NOPULL, \
- .sense = NRF_GPIOTE_POLARITY_LOTOHI, \
- }
+{ \
+ .sense = NRF_GPIOTE_POLARITY_LOTOHI, \
+ .pull = NRF_GPIO_PIN_NOPULL, \
+ .is_watcher = false, \
+ .hi_accuracy = hi_accu, \
+ .skip_gpio_setup = false, \
+}
-/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition.
- * @details Set hi_accu to true to use IN_EVENT. */
+/**
+ * @brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition.
+ * @details Set hi_accu to true to use IN_EVENT.
+ */
#define NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(hi_accu) \
- { \
- .is_watcher = false, \
- .hi_accuracy = hi_accu, \
- .pull = NRF_GPIO_PIN_NOPULL, \
- .sense = NRF_GPIOTE_POLARITY_HITOLO, \
- }
+{ \
+ .sense = NRF_GPIOTE_POLARITY_HITOLO, \
+ .pull = NRF_GPIO_PIN_NOPULL, \
+ .is_watcher = false, \
+ .hi_accuracy = hi_accu, \
+ .skip_gpio_setup = false, \
+}
-/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin.
- * @details Set hi_accu to true to use IN_EVENT.*/
+/**
+ * @brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin.
+ * @details Set hi_accu to true to use IN_EVENT.
+ */
#define NRFX_GPIOTE_CONFIG_IN_SENSE_TOGGLE(hi_accu) \
- { \
- .is_watcher = false, \
- .hi_accuracy = hi_accu, \
- .pull = NRF_GPIO_PIN_NOPULL, \
- .sense = NRF_GPIOTE_POLARITY_TOGGLE, \
- }
+{ \
+ .sense = NRF_GPIOTE_POLARITY_TOGGLE, \
+ .pull = NRF_GPIO_PIN_NOPULL, \
+ .is_watcher = false, \
+ .hi_accuracy = hi_accu, \
+ .skip_gpio_setup = false, \
+}
-/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition.
+/**
+ * @brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition.
* @details Set hi_accu to true to use IN_EVENT.
- * @note This macro prepares configuration that skips GPIO setup. */
+ * @note This macro prepares configuration that skips the GPIO setup.
+ */
#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_LOTOHI(hi_accu) \
- { \
- .is_watcher = false, \
- .hi_accuracy = hi_accu, \
- .pull = NRF_GPIO_PIN_NOPULL, \
- .sense = NRF_GPIOTE_POLARITY_LOTOHI, \
- .skip_gpio_setup = true, \
- }
+{ \
+ .sense = NRF_GPIOTE_POLARITY_LOTOHI, \
+ .pull = NRF_GPIO_PIN_NOPULL, \
+ .is_watcher = false, \
+ .hi_accuracy = hi_accu, \
+ .skip_gpio_setup = true, \
+}
-/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition.
+/**
+ * @brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition.
* @details Set hi_accu to true to use IN_EVENT.
- * @note This macro prepares configuration that skips GPIO setup. */
+ * @note This macro prepares configuration that skips the GPIO setup.
+ */
#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_HITOLO(hi_accu) \
- { \
- .is_watcher = false, \
- .hi_accuracy = hi_accu, \
- .pull = NRF_GPIO_PIN_NOPULL, \
- .sense = NRF_GPIOTE_POLARITY_HITOLO, \
- .skip_gpio_setup = true, \
- }
+{ \
+ .sense = NRF_GPIOTE_POLARITY_HITOLO, \
+ .pull = NRF_GPIO_PIN_NOPULL, \
+ .is_watcher = false, \
+ .hi_accuracy = hi_accu, \
+ .skip_gpio_setup = true, \
+}
-/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin.
+/**
+ * @brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin.
* @details Set hi_accu to true to use IN_EVENT.
- * @note This macro prepares configuration that skips GPIO setup. */
+ * @note This macro prepares configuration that skips the GPIO setup.
+ */
#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_TOGGLE(hi_accu) \
- { \
- .is_watcher = false, \
- .hi_accuracy = hi_accu, \
- .pull = NRF_GPIO_PIN_NOPULL, \
- .sense = NRF_GPIOTE_POLARITY_TOGGLE, \
- .skip_gpio_setup = true, \
- }
+{ \
+ .sense = NRF_GPIOTE_POLARITY_TOGGLE, \
+ .pull = NRF_GPIO_PIN_NOPULL, \
+ .is_watcher = false, \
+ .hi_accuracy = hi_accu, \
+ .skip_gpio_setup = true, \
+}
-/**@brief Output pin configuration. */
+/** @brief Output pin configuration. */
typedef struct
{
nrf_gpiote_polarity_t action; /**< Configuration of the pin task. */
@@ -132,15 +147,18 @@ typedef struct
bool task_pin; /**< True if the pin is controlled by a GPIOTE task. */
} nrfx_gpiote_out_config_t;
-/**@brief Macro for configuring a pin to use as output. GPIOTE is not used for the pin. */
+/** @brief Macro for configuring a pin to use as output. GPIOTE is not used for the pin. */
#define NRFX_GPIOTE_CONFIG_OUT_SIMPLE(init_high) \
{ \
+ .action = NRF_GPIOTE_POLARITY_LOTOHI, \
.init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW, \
- .task_pin = false, \
+ .task_pin = false, \
}
-/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from high to low.
- * @details The task will clear the pin. Therefore, the pin is set initially. */
+/**
+ * @brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from high to low.
+ * @details The task will clear the pin. Therefore, the pin is set initially.
+ */
#define NRFX_GPIOTE_CONFIG_OUT_TASK_LOW \
{ \
.init_state = NRF_GPIOTE_INITIAL_VALUE_HIGH, \
@@ -148,22 +166,26 @@ typedef struct
.action = NRF_GPIOTE_POLARITY_HITOLO, \
}
-/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from low to high.
- * @details The task will set the pin. Therefore, the pin is cleared initially. */
+/**
+ * @brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from low to high.
+ * @details The task will set the pin. Therefore, the pin is cleared initially.
+ */
#define NRFX_GPIOTE_CONFIG_OUT_TASK_HIGH \
{ \
+ .action = NRF_GPIOTE_POLARITY_LOTOHI, \
.init_state = NRF_GPIOTE_INITIAL_VALUE_LOW, \
.task_pin = true, \
- .action = NRF_GPIOTE_POLARITY_LOTOHI, \
}
-/**@brief Macro for configuring a pin to use the GPIO OUT TASK to toggle the pin state.
- * @details The initial pin state must be provided. */
+/**
+ * @brief Macro for configuring a pin to use the GPIO OUT TASK to toggle the pin state.
+ * @details The initial pin state must be provided.
+ */
#define NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE(init_high) \
{ \
+ .action = NRF_GPIOTE_POLARITY_TOGGLE, \
.init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW, \
.task_pin = true, \
- .action = NRF_GPIOTE_POLARITY_TOGGLE, \
}
/** @brief Pin. */
@@ -172,8 +194,8 @@ typedef uint32_t nrfx_gpiote_pin_t;
/**
* @brief Pin event handler prototype.
*
- * @param pin Pin that triggered this event.
- * @param action Action that lead to triggering this event.
+ * @param[in] pin Pin that triggered this event.
+ * @param[in] action Action that led to triggering this event.
*/
typedef void (*nrfx_gpiote_evt_handler_t)(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action);
@@ -183,25 +205,23 @@ typedef void (*nrfx_gpiote_evt_handler_t)(nrfx_gpiote_pin_t pin, nrf_gpiote_pola
* @details Only static configuration is supported to prevent the shared
* resource being customized by the initiator.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver was already initialized.
*/
nrfx_err_t nrfx_gpiote_init(void);
/**
* @brief Function for checking if the GPIOTE module is initialized.
*
- * @details The GPIOTE module is a shared module. Therefore, you should check if
+ * @details The GPIOTE module is a shared module. Therefore, check if
* the module is already initialized and skip initialization if it is.
*
- * @retval true If the module is already initialized.
- * @retval false If the module is not initialized.
+ * @retval true The module is already initialized.
+ * @retval false The module is not initialized.
*/
bool nrfx_gpiote_is_init(void);
-/**
- * @brief Function for uninitializing the GPIOTE module.
- */
+/** @brief Function for uninitializing the GPIOTE module. */
void nrfx_gpiote_uninit(void);
/**
@@ -214,9 +234,9 @@ void nrfx_gpiote_uninit(void);
* @param[in] pin Pin.
* @param[in] p_config Initial configuration.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used.
- * @retval NRFX_ERROR_NO_MEM If no GPIOTE channel is available.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver is not initialized or the pin is already used.
+ * @retval NRFX_ERROR_NO_MEM No GPIOTE channel is available.
*/
nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin,
nrfx_gpiote_out_config_t const * p_config);
@@ -305,7 +325,7 @@ uint32_t nrfx_gpiote_clr_task_addr_get(nrfx_gpiote_pin_t pin);
* If high-accuracy mode is used, the driver attempts to allocate one
* of the available GPIOTE channels. If no channel is
* available, an error is returned.
- * In low accuracy mode SENSE feature is used. In this case only one active pin
+ * In low accuracy mode SENSE feature is used. In this case, only one active pin
* can be detected at a time. It can be worked around by setting all of the used
* low accuracy pins to toggle mode.
* For more information about SENSE functionality, refer to Product Specification.
@@ -314,9 +334,9 @@ uint32_t nrfx_gpiote_clr_task_addr_get(nrfx_gpiote_pin_t pin);
* @param[in] p_config Initial configuration.
* @param[in] evt_handler User function to be called when the configured transition occurs.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used.
- * @retval NRFX_ERROR_NO_MEM If no GPIOTE channel is available.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver is not initialized or the pin is already used.
+ * @retval NRFX_ERROR_NO_MEM No GPIOTE channel is available.
*/
nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin,
nrfx_gpiote_in_config_t const * p_config,
@@ -335,8 +355,7 @@ void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin);
*
* @details If the input pin is configured as high-accuracy pin, the function
* enables an IN_EVENT. Otherwise, the function enables the GPIO sense mechanism.
- * Note that a PORT event is shared between multiple pins, therefore the
- * interrupt is always enabled.
+ * The PORT event is shared between multiple pins, therefore the interrupt is always enabled.
*
* @param[in] pin Pin.
* @param[in] int_enable True to enable the interrupt. Always valid for a high-accuracy pin.
@@ -355,8 +374,8 @@ void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin);
*
* @param[in] pin Pin.
*
- * @retval true If the input pin is set.
- * @retval false If the input pin is not set.
+ * @retval true The input pin is set.
+ * @retval false The input pin is not set.
*/
bool nrfx_gpiote_in_is_set(nrfx_gpiote_pin_t pin);
@@ -365,6 +384,8 @@ bool nrfx_gpiote_in_is_set(nrfx_gpiote_pin_t pin);
* @details If the pin is configured to use low-accuracy mode, the address of the PORT event is returned.
*
* @param[in] pin Pin.
+ *
+ * @return Address of the specified input pin event.
*/
uint32_t nrfx_gpiote_in_event_addr_get(nrfx_gpiote_pin_t pin);
@@ -401,12 +422,12 @@ void nrfx_gpiote_set_task_trigger(nrfx_gpiote_pin_t pin);
void nrfx_gpiote_clr_task_trigger(nrfx_gpiote_pin_t pin);
#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__)
+/** @} */
+
void nrfx_gpiote_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_i2s.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_i2s.h
index 2c4bf96f1..24acbdc34 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_i2s.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_i2s.h
@@ -82,13 +82,11 @@ typedef struct
/** @brief I2S driver buffers structure. */
typedef struct
{
- uint32_t * p_rx_buffer;
- uint32_t const * p_tx_buffer;
+ uint32_t * p_rx_buffer; ///< Pointer to the buffer for received data.
+ uint32_t const * p_tx_buffer; ///< Pointer to the buffer with data to be sent.
} nrfx_i2s_buffers_t;
-/**
- * @brief I2S driver default configuration.
- */
+/** @brief I2S driver default configuration. */
#define NRFX_I2S_DEFAULT_CONFIG \
{ \
.sck_pin = NRFX_I2S_CONFIG_SCK_PIN, \
@@ -108,28 +106,28 @@ typedef struct
#define NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED (1UL << 0)
- /**< The application should provide buffers that are to be used in the next
- * part of the transfer. A call to @ref nrfx_i2s_next_buffers_set should
+ /**< The application must provide buffers that are to be used in the next
+ * part of the transfer. A call to @ref nrfx_i2s_next_buffers_set must
* be done before the currently used buffers are completely processed
- * (i.e. the time remaining for supplying the next buffers depends on
+ * (that is, the time remaining for supplying the next buffers depends on
* the used size of the buffers). */
/**
* @brief I2S driver data handler type.
*
- * A data handling function of this type must be specified during initialization
+ * A data handling function of this type must be specified during the initialization
* of the driver. The driver will call this function when it finishes using
* buffers passed to it by the application, and when it needs to be provided
* with buffers for the next part of the transfer.
*
* @note The @c p_released pointer passed to this function is temporary and
* will be invalid after the function returns, hence it cannot be stored
- * and used later. If needed, the pointed content (i.e. buffers pointers)
- * should be copied instead.
+ * and used later. If needed, the pointed content (that is, buffers pointers)
+ * must be copied instead.
*
* @param[in] p_released Pointer to a structure with pointers to buffers
* passed previously to the driver that will no longer
- * be access by it (they can be now safely released or
+ * be accessed by it (they can be now safely released or
* used for another purpose, in particular for a next
* part of the transfer).
* This pointer will be NULL if the application did not
@@ -158,13 +156,13 @@ typedef void (* nrfx_i2s_data_handler_t)(nrfx_i2s_buffers_t const * p_released,
/**
* @brief Function for initializing the I2S driver.
*
- * @param[in] p_config Pointer to the structure with initial configuration.
- * @param[in] handler Data handler provided by the user. Must not be NULL.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ * @param[in] handler Data handler provided by the user. Must not be NULL.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized.
- * @retval NRFX_ERROR_INVALID_PARAM If the requested combination of configuration
- * options is not allowed by the I2S peripheral.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver was already initialized.
+ * @retval NRFX_ERROR_INVALID_PARAM The requested combination of configuration
+ * options is not allowed by the I2S peripheral.
*/
nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config,
nrfx_i2s_data_handler_t handler);
@@ -179,7 +177,7 @@ void nrfx_i2s_uninit(void);
* only, TX (transmission) only, or in both directions simultaneously.
* The mode is selected by specifying a proper buffer for a given direction
* in the call to this function or by passing NULL instead if this direction
- * should be disabled.
+ * is to be disabled.
*
* The length of the buffer (which is a common value for RX and TX if both
* directions are enabled) is specified in 32-bit words. One 32-bit memory
@@ -192,20 +190,20 @@ void nrfx_i2s_uninit(void);
* to be placed in the Data RAM region. If this condition is not met,
* this function will fail with the error code NRFX_ERROR_INVALID_ADDR.
*
- * @param[in] p_initial_buffers Pointer to a structure specifying the buffers
- * to be used in the initial part of the transfer
- * (buffers for all consecutive parts are provided
- * through the data handler).
- * @param[in] buffer_size Size of the buffers (in 32-bit words).
- * Must not be 0.
- * @param[in] flags Transfer options (0 for default settings).
- * Currently, no additional flags are available.
+ * @param[in] p_initial_buffers Pointer to a structure specifying the buffers
+ * to be used in the initial part of the transfer
+ * (buffers for all consecutive parts are provided
+ * through the data handler).
+ * @param[in] buffer_size Size of the buffers (in 32-bit words).
+ * Must not be 0.
+ * @param[in] flags Transfer options (0 for default settings).
+ * Currently, no additional flags are available.
*
- * @retval NRFX_SUCCESS If the operation was successful.
- * @retval NRFX_ERROR_INVALID_STATE If a transfer was already started or
- * the driver has not been initialized.
- * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed
- * in the Data RAM region.
+ * @retval NRFX_SUCCESS The operation was successful.
+ * @retval NRFX_ERROR_INVALID_STATE Transfer was already started or
+ * the driver has not been initialized.
+ * @retval NRFX_ERROR_INVALID_ADDR The provided buffers are not placed
+ * in the Data RAM region.
*/
nrfx_err_t nrfx_i2s_start(nrfx_i2s_buffers_t const * p_initial_buffers,
uint16_t buffer_size,
@@ -215,7 +213,7 @@ nrfx_err_t nrfx_i2s_start(nrfx_i2s_buffers_t const * p_initial_buffers,
* @brief Function for supplying the buffers to be used in the next part of
* the transfer.
*
- * The application should call this function when the data handler receives
+ * The application must call this function when the data handler receives
* @ref NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED in the @c status parameter.
* The call can be done immediately from the data handler function or later,
* but it has to be done before the I2S peripheral finishes processing the
@@ -223,9 +221,9 @@ nrfx_err_t nrfx_i2s_start(nrfx_i2s_buffers_t const * p_initial_buffers,
*
* @sa nrfx_i2s_data_handler_t
*
- * @retval NRFX_SUCCESS If the operation was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the buffers were already supplied or
- * the peripheral is currently being stopped.
+ * @retval NRFX_SUCCESS If the operation was successful.
+ * @retval NRFX_ERROR_INVALID_STATE If the buffers were already supplied or
+ * the peripheral is currently being stopped.
*/
nrfx_err_t nrfx_i2s_next_buffers_set(nrfx_i2s_buffers_t const * p_buffers);
@@ -243,3 +241,4 @@ void nrfx_i2s_irq_handler(void);
#endif
#endif // NRFX_I2S_H__
+
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_lpcomp.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_lpcomp.h
index 1f4a4a064..f68ef1fe7 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_lpcomp.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_lpcomp.h
@@ -48,7 +48,7 @@ extern "C" {
/**
* @brief LPCOMP event handler function type.
- * @param[in] event LPCOMP event.
+ * @param[in] event LPCOMP event.
*/
typedef void (* nrfx_lpcomp_event_handler_t)(nrf_lpcomp_event_t event);
@@ -60,24 +60,24 @@ typedef struct
uint8_t interrupt_priority; /**< LPCOMP interrupt priority. */
} nrfx_lpcomp_config_t;
-/** @brief LPCOMP driver default configuration including the LPCOMP HAL configuration. */
+/** @brief LPCOMP driver default configuration, including the LPCOMP HAL configuration. */
#ifdef NRF52_SERIES
-#define NRFX_LPCOMP_DEFAULT_CONFIG \
- { \
- .hal = { (nrf_lpcomp_ref_t)NRFX_LPCOMP_CONFIG_REFERENCE , \
- (nrf_lpcomp_detect_t)NRFX_LPCOMP_CONFIG_DETECTION, \
- (nrf_lpcomp_hysteresis_t)NRFX_LPCOMP_CONFIG_HYST }, \
- .input = (nrf_lpcomp_input_t)NRFX_LPCOMP_CONFIG_INPUT, \
- .interrupt_priority = NRFX_LPCOMP_CONFIG_IRQ_PRIORITY \
- }
+#define NRFX_LPCOMP_DEFAULT_CONFIG \
+{ \
+ .hal = { (nrf_lpcomp_ref_t)NRFX_LPCOMP_CONFIG_REFERENCE , \
+ (nrf_lpcomp_detect_t)NRFX_LPCOMP_CONFIG_DETECTION, \
+ (nrf_lpcomp_hysteresis_t)NRFX_LPCOMP_CONFIG_HYST }, \
+ .input = (nrf_lpcomp_input_t)NRFX_LPCOMP_CONFIG_INPUT, \
+ .interrupt_priority = NRFX_LPCOMP_CONFIG_IRQ_PRIORITY \
+}
#else
-#define NRFX_LPCOMP_DEFAULT_CONFIG \
- { \
- .hal = { (nrf_lpcomp_ref_t)NRFX_LPCOMP_CONFIG_REFERENCE , \
- (nrf_lpcomp_detect_t)NRFX_LPCOMP_CONFIG_DETECTION }, \
- .input = (nrf_lpcomp_input_t)NRFX_LPCOMP_CONFIG_INPUT, \
- .interrupt_priority = NRFX_LPCOMP_CONFIG_IRQ_PRIORITY \
- }
+#define NRFX_LPCOMP_DEFAULT_CONFIG \
+{ \
+ .hal = { (nrf_lpcomp_ref_t)NRFX_LPCOMP_CONFIG_REFERENCE , \
+ (nrf_lpcomp_detect_t)NRFX_LPCOMP_CONFIG_DETECTION }, \
+ .input = (nrf_lpcomp_input_t)NRFX_LPCOMP_CONFIG_INPUT, \
+ .interrupt_priority = NRFX_LPCOMP_CONFIG_IRQ_PRIORITY \
+}
#endif
/**
@@ -86,13 +86,13 @@ typedef struct
* This function initializes the LPCOMP driver, but does not enable the peripheral or any interrupts.
* To start the driver, call the function nrfx_lpcomp_enable() after initialization.
*
- * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] event_handler Event handler provided by the user.
* Must not be NULL.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver has already been initialized.
- * @retval NRFX_ERROR_BUSY If the COMP peripheral is already in use.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver has already been initialized.
+ * @retval NRFX_ERROR_BUSY The COMP peripheral is already in use.
* This is possible only if @ref nrfx_prs module
* is enabled.
*/
@@ -100,39 +100,42 @@ nrfx_err_t nrfx_lpcomp_init(nrfx_lpcomp_config_t const * p_config,
nrfx_lpcomp_event_handler_t event_handler);
/**
- * @brief Function for uninitializing the LCOMP driver.
+ * @brief Function for uninitializing the LCOMP driver.
*
- * This function uninitializes the LPCOMP driver. The LPCOMP peripheral and
- * its interrupts are disabled, and local variables are cleaned. After this call, you must
- * initialize the driver again by calling nrfx_lpcomp_init() if you want to use it.
+ * This function uninitializes the LPCOMP driver. The LPCOMP peripheral and
+ * its interrupts are disabled, and local variables are cleaned. After this call, you must
+ * initialize the driver again by calling nrfx_lpcomp_init() if you want to use it.
*
- * @sa nrfx_lpcomp_disable()
- * @sa nrfx_lpcomp_init()
+ * @sa nrfx_lpcomp_disable
+ * @sa nrfx_lpcomp_init
*/
void nrfx_lpcomp_uninit(void);
-/**@brief Function for enabling the LPCOMP peripheral and interrupts.
+/**
+ * @brief Function for enabling the LPCOMP peripheral and interrupts.
*
* Before calling this function, the driver must be initialized. This function
* enables the LPCOMP peripheral and its interrupts.
*
- * @sa nrfx_lpcomp_disable()
+ * @sa nrfx_lpcomp_disable
*/
void nrfx_lpcomp_enable(void);
-/**@brief Function for disabling the LPCOMP peripheral.
+/**
+ * @brief Function for disabling the LPCOMP peripheral.
*
* Before calling this function, the driver must be initialized. This function disables the LPCOMP
* peripheral and its interrupts.
*
- * @sa nrfx_lpcomp_enable()
+ * @sa nrfx_lpcomp_enable
*/
void nrfx_lpcomp_disable(void);
+/** @} */
+
void nrfx_lpcomp_irq_handler(void);
-/** @} **/
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_nfct.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_nfct.h
index c90ca3dff..2bfa8827d 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_nfct.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_nfct.h
@@ -52,9 +52,7 @@ extern "C" {
#define NRFX_NFCT_NFCID1_DEFAULT_LEN NRFX_NFCT_NFCID1_DOUBLE_SIZE ///< Default length of NFC ID. */
-/**
- * @brief NFCT hardware states.
- */
+/** @brief NFCT hardware states. */
typedef enum
{
NRFX_NFCT_STATE_DISABLED = NRF_NFCT_TASK_DISABLE, ///< NFC Tag is disabled (no sensing of an external NFC field).
@@ -74,7 +72,7 @@ typedef enum
NRFX_NFCT_ACTIVE_STATE_DEFAULT, ///< NFC Tag is either sleeping or idle, depending on the previous state before being selected by a poller.
} nrfx_nfct_active_state_t;
-/**
+/**
* @brief NFCT driver event types, passed to the upper-layer callback function
* provided during the initialization.
*/
@@ -90,18 +88,14 @@ typedef enum
NRFX_NFCT_EVT_ERROR = NRF_NFCT_INT_ERROR_MASK, ///< Error occurred in an NFC communication.
} nrfx_nfct_evt_id_t;
-/**
- * @brief NFCT timing-related error types.
- */
+/** @brief NFCT timing-related error types. */
typedef enum
{
NRFX_NFCT_ERROR_FRAMEDELAYTIMEOUT, ///< No response frame was transmitted to the poller in the transmit window.
NRFX_NFCT_ERROR_NUM, ///< Total number of possible errors.
} nrfx_nfct_error_t;
-/**
- * @brief NFCT driver parameter types.
- */
+/** @brief NFCT driver parameter types. */
typedef enum
{
NRFX_NFCT_PARAM_ID_FDT, ///< NFC-A Frame Delay Time parameter.
@@ -109,18 +103,14 @@ typedef enum
NRFX_NFCT_PARAM_ID_NFCID1, ///< NFC-A NFCID1 setting (NFC tag identifier).
} nrfx_nfct_param_id_t;
-/**
- * @brief NFCID1 descriptor.
- */
+/** @brief NFCID1 descriptor. */
typedef struct
{
uint8_t const * p_id; ///< NFCID1 data.
uint8_t id_size; ///< NFCID1 size.
} nrfx_nfct_nfcid1_t;
-/**
- * @brief NFCT driver parameter descriptor.
- */
+/** @brief NFCT driver parameter descriptor. */
typedef struct
{
nrfx_nfct_param_id_t id; ///< Type of parameter.
@@ -129,46 +119,36 @@ typedef struct
uint32_t fdt; ///< NFC-A Frame Delay Time. Filled when nrfx_nfct_param_t::id is @ref NRFX_NFCT_PARAM_ID_FDT.
uint8_t sel_res_protocol; ///< NFC-A value of the 'Protocol' field in the SEL_RES frame. Filled when nrfx_nfct_param_t::id is @ref NRFX_NFCT_PARAM_ID_SEL_RES.
nrfx_nfct_nfcid1_t nfcid1; ///< NFC-A NFCID1 value (tag identifier). Filled when nrfx_nfct_param_t::id is @ref NRFX_NFCT_PARAM_ID_NFCID1.
- } data;
+ } data; ///< Union to store parameter data.
} nrfx_nfct_param_t;
-/**
- * @brief NFCT driver RX/TX buffer descriptor.
- */
+/** @brief NFCT driver RX/TX buffer descriptor. */
typedef struct
{
uint32_t data_size; ///< RX/TX buffer size.
uint8_t const * p_data; ///< RX/TX buffer.
} nrfx_nfct_data_desc_t;
-/**
- * @brief Structure used to describe the @ref NRFX_NFCT_EVT_RX_FRAMEEND event type.
- */
+/** @brief Structure used to describe the @ref NRFX_NFCT_EVT_RX_FRAMEEND event type. */
typedef struct
{
uint32_t rx_status; ///< RX error status.
nrfx_nfct_data_desc_t rx_data; ///< RX buffer.
} nrfx_nfct_evt_rx_frameend_t;
-/**
- * @brief Structure used to describe the @ref NRFX_NFCT_EVT_TX_FRAMESTART event type.
- */
+/** @brief Structure used to describe the @ref NRFX_NFCT_EVT_TX_FRAMESTART event type. */
typedef struct
{
nrfx_nfct_data_desc_t tx_data; ///< TX buffer.
} nrfx_nfct_evt_tx_framestart_t;
-/**
- * @brief Structure used to describe the @ref NRFX_NFCT_EVT_ERROR event type.
- */
+/** @brief Structure used to describe the @ref NRFX_NFCT_EVT_ERROR event type. */
typedef struct
{
nrfx_nfct_error_t reason; ///< Reason for error.
} nrfx_nfct_evt_error_t;
-/**
- * @brief NFCT driver event.
- */
+/** @brief NFCT driver event. */
typedef struct
{
nrfx_nfct_evt_id_t evt_id; ///< Type of event.
@@ -177,32 +157,30 @@ typedef struct
nrfx_nfct_evt_rx_frameend_t rx_frameend; ///< End of the RX frame data. Filled when nrfx_nfct_evt_t::evt_id is @ref NRFX_NFCT_EVT_RX_FRAMEEND.
nrfx_nfct_evt_tx_framestart_t tx_framestart; ///< Start of the TX frame data. Filled when nrfx_nfct_evt_t::evt_id is @ref NRFX_NFCT_EVT_TX_FRAMESTART.
nrfx_nfct_evt_error_t error; ///< Error data. Filled when nrfx_nfct_evt_t::evt_id is @ref NRFX_NFCT_EVT_ERROR.
- } params;
+ } params; ///< Union to store event data.
} nrfx_nfct_evt_t;
-/**
+/**
* @brief Callback descriptor to pass events from the NFCT driver to the upper layer.
*
* @param[in] p_event Pointer to the event descriptor.
*/
typedef void (*nrfx_nfct_handler_t)(nrfx_nfct_evt_t const * p_event);
-/**
- * @brief NFCT driver configuration structure.
- */
+/** @brief NFCT driver configuration structure. */
typedef struct
{
uint32_t rxtx_int_mask; ///< Mask for enabling RX/TX events. Indicate which events must be forwarded to the upper layer by using @ref nrfx_nfct_evt_id_t. By default, no events are enabled. */
nrfx_nfct_handler_t cb; ///< Callback.
} nrfx_nfct_config_t;
-/**
+/**
* @brief Function for initializing the NFCT driver.
*
* @param[in] p_config Pointer to the NFCT driver configuration structure.
*
- * @retval NRFX_SUCCESS If the NFCT driver was initialized successfully.
- * @retval NRFX_ERROR_INVALID_STATE If the NFCT driver is already initialized.
+ * @retval NRFX_SUCCESS The NFCT driver was initialized successfully.
+ * @retval NRFX_ERROR_INVALID_STATE The NFCT driver is already initialized.
*/
nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config);
@@ -231,26 +209,26 @@ void nrfx_nfct_disable(void);
/**
* @brief Function for checking whether the external NFC field is present in the range of the tag.
*
- * @retval true If the NFC field is present.
- * @retval false If no NFC field is present.
+ * @retval true The NFC field is present.
+ * @retval false No NFC field is present.
*/
bool nrfx_nfct_field_check(void);
-/**
+/**
* @brief Function for preparing the NFCT driver for receiving an NFC frame.
*
* @param[in] p_rx_data Pointer to the RX buffer.
*/
void nrfx_nfct_rx(nrfx_nfct_data_desc_t const * p_rx_data);
-/**
+/**
* @brief Function for transmitting an NFC frame.
*
* @param[in] p_tx_data Pointer to the TX buffer.
* @param[in] delay_mode Delay mode of the NFCT frame timer.
*
- * @retval NRFX_SUCCESS If the operation was successful.
- * @retval NRFX_ERROR_INVALID_LENGTH If the TX buffer size is invalid.
+ * @retval NRFX_SUCCESS The operation was successful.
+ * @retval NRFX_ERROR_INVALID_LENGTH The TX buffer size is invalid.
*/
nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data,
nrf_nfct_frame_delay_mode_t delay_mode);
@@ -265,7 +243,7 @@ nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data,
*/
void nrfx_nfct_state_force(nrfx_nfct_state_t state);
-/**
+/**
* @brief Function for moving the NFCT to a new initial substate within @ref NRFX_NFCT_STATE_ACTIVATED.
*
* @param[in] sub_state The required substate.
@@ -279,12 +257,12 @@ void nrfx_nfct_init_substate_force(nrfx_nfct_active_state_t sub_state);
*
* @param[in] p_param Pointer to parameter descriptor.
*
- * @retval NRFX_SUCCESS If the operation was successful.
- * @retval NRFX_ERROR_INVALID_PARAM If the parameter data is invalid.
+ * @retval NRFX_SUCCESS The operation was successful.
+ * @retval NRFX_ERROR_INVALID_PARAM The parameter data is invalid.
*/
nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param);
-/**
+/**
* @brief Function for getting default bytes for NFCID1.
*
* @param[in,out] p_nfcid1_buff In: empty buffer for data;
@@ -292,8 +270,8 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param);
* can be used to fill the Type 2 Tag Internal Bytes.
* @param[in] nfcid1_buff_len Length of the NFCID1 buffer.
*
- * @retval NRFX_SUCCESS If the operation was successful.
- * @retval NRFX_ERROR_INVALID_LENGTH If length of the NFCID buffer is different than
+ * @retval NRFX_SUCCESS The operation was successful.
+ * @retval NRFX_ERROR_INVALID_LENGTH Length of the NFCID buffer is different than
* @ref NRFX_NFCT_NFCID1_SINGLE_SIZE,
* @ref NRFX_NFCT_NFCID1_DOUBLE_SIZE, or
* @ref NRFX_NFCT_NFCID1_TRIPLE_SIZE.
@@ -301,7 +279,7 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param);
nrfx_err_t nrfx_nfct_nfcid1_default_bytes_get(uint8_t * const p_nfcid1_buff,
uint32_t nfcid1_buff_len);
-/**
+/**
* @brief Function for enabling the automatic collision resolution.
*
* @details As defined by the NFC Forum Digital Protocol Technical Specification (and ISO 14443-3),
@@ -310,19 +288,19 @@ nrfx_err_t nrfx_nfct_nfcid1_default_bytes_get(uint8_t * const p_nfcid1_buff,
*/
void nrfx_nfct_autocolres_enable(void);
-/**
+/**
* @brief Function for disabling the automatic collision resolution.
*
* @details See also details in @ref nrfx_nfct_autocolres_enable.
*/
void nrfx_nfct_autocolres_disable(void);
+/** @} */
+
void nrfx_nfct_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
@@ -338,7 +316,7 @@ void nrfx_nfct_irq_handler(void);
* - 79. NFCT: A false EVENTS_FIELDDETECTED event occurs after the field is lost.
* - 116. NFCT does not release HFCLK when switching from ACTIVATED to SENSE mode.
* To implement the first workaround, an instance of NRF_TIMER is used. After the NFC field is detected,
- * the timing module periodically polls its state to determine when the field is turned off.
+ * the timing module periodically polls its state to determine when the field is turned off.
* To implement the second workaround, power reset is used to release the clock acquired by NFCT
* after the field is turned off. Note that the NFCT register configuration is restored to defaults.
*
@@ -358,7 +336,7 @@ void nrfx_nfct_irq_handler(void);
* The application of the implemented workarounds for the nRF52840 chip is determined at runtime and depends
* on the chip variant.
*
- * The current code contains a patch for the anomaly 25 (NFCT: Reset value of
+ * The current code contains a patch for the anomaly 25 (NFCT: Reset value of
* SENSRES register is incorrect), so that the module now works on Windows Phone.
* @}
*/
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_nvmc.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_nvmc.h
new file mode 100644
index 000000000..39e9bb4f8
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_nvmc.h
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_NVMC_H__
+#define NRFX_NVMC_H__
+
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfx_nvmc NVMC driver
+ * @{
+ * @ingroup nrf_nvmc
+ * @brief Non-Volatile Memory Controller (NVMC) peripheral driver.
+ */
+
+/**
+ * @brief Function for erasing a page in flash.
+ *
+ * This function blocks until the erase operation finishes.
+ *
+ * @note Depending on the source of the code being executed,
+ * the CPU may be halted during the operation.
+ * Refer to the Product Specification for more information.
+ *
+ * @param address Address of the first word in the page to erase.
+ *
+ * @retval NRFX_SUCCESS Page erase complete.
+ * @retval NRFX_ERROR_INVALID_ADDR Address is not aligned to the size of the page.
+ */
+nrfx_err_t nrfx_nvmc_page_erase(uint32_t address);
+
+/**
+ * @brief Function for erasing the user information configuration register (UICR).
+ *
+ * @note Depending on the source of the code being executed,
+ * the CPU may be halted during the operation.
+ * Refer to the Product Specification for more information.
+ *
+ * @retval NRFX_SUCCESS UICR has been successfully erased.
+ * @retval NRFX_ERROR_NOT_SUPPORTED UICR erase is not supported.
+ */
+nrfx_err_t nrfx_nvmc_uicr_erase(void);
+
+/**
+ * @brief Function for erasing the whole flash memory.
+ *
+ * @note All user code and UICR will be erased.
+ */
+void nrfx_nvmc_all_erase(void);
+
+#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
+/**
+ * @brief Function for initiating a complete page erase split into parts (also known as partial erase).
+ *
+ * This function initiates a partial erase with the specified duration.
+ * To execute each part of the partial erase, use @ref nrfx_nvmc_page_partial_erase_continue.
+ *
+ * @param address Address of the first word in the page to erase.
+ * @param duration_ms Time in milliseconds that each partial erase will take.
+ *
+ * @retval NRFX_SUCCESS Partial erase started.
+ * @retval NRFX_ERROR_INVALID_ADDR Address is not aligned to the size of the page.
+ *
+ * @sa nrfx_nvmc_page_partial_erase_continue()
+ */
+nrfx_err_t nrfx_nvmc_page_partial_erase_init(uint32_t address, uint32_t duration_ms);
+
+/**
+ * @brief Function for performing a part of the complete page erase (also known as partial erase).
+ *
+ * This function must be called several times to erase the whole page, once for each erase part.
+ *
+ * @note The actual time needed to perform each part of the page erase is longer than the partial
+ * erase duration specified in the call to @ref nrfx_nvmc_page_partial_erase_init,
+ * since the NVMC peripheral needs certain additional amount of time to handle the process.
+ * For details regarding this additional time, see the "Electrical specification" section
+ * for the NVMC peripheral in the Product Specification.
+ *
+ * @note Using a page that was not completely erased leads to undefined behavior.
+ * Depending on the source of the code being executed,
+ * the CPU may be halted during the operation.
+ * Refer to the Product Specification for more information.
+ *
+ * @retval true Partial erase finished.
+ * @retval false Partial erase not finished.
+ * Call the function again to process the next part.
+ */
+bool nrfx_nvmc_page_partial_erase_continue(void);
+
+#endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
+
+/**
+ * @brief Function for checking whether a byte is writable at the specified address.
+ *
+ * The NVMC is only able to write '0' to bits in the flash that are erased (set to '1').
+ * It cannot rewrite a bit back to '1'. This function checks if the value currently
+ * residing at the specified address can be transformed to the desired value
+ * without any '0' to '1' transitions.
+ *
+ * @param address Address to be checked.
+ * @param value Value to be checked.
+ *
+ * @retval true Byte can be written at the specified address.
+ * @retval false Byte cannot be written at the specified address.
+ * Erase the page or change the address.
+ */
+bool nrfx_nvmc_byte_writable_check(uint32_t address, uint8_t value);
+
+/**
+ * @brief Function for writing a single byte to flash.
+ *
+ * To determine if the flash write has been completed, use @ref nrfx_nvmc_write_done_check().
+ *
+ * @note Depending on the source of the code being executed,
+ * the CPU may be halted during the operation.
+ * Refer to the Product Specification for more information.
+ *
+ * @param address Address to write to.
+ * @param value Value to write.
+ */
+void nrfx_nvmc_byte_write(uint32_t address, uint8_t value);
+
+/**
+ * @brief Function for checking whether a word is writable at the specified address.
+ *
+ * The NVMC is only able to write '0' to bits in the Flash that are erased (set to '1').
+ * It cannot rewrite a bit back to '1'. This function checks if the value currently
+ * residing at the specified address can be transformed to the desired value
+ * without any '0' to '1' transitions.
+ *
+ * @param address Address to be checked. Must be word-aligned.
+ * @param value Value to be checked.
+ *
+ * @retval true Word can be written at the specified address.
+ * @retval false Word cannot be written at the specified address.
+ * Erase page or change address.
+ */
+bool nrfx_nvmc_word_writable_check(uint32_t address, uint32_t value);
+
+/**
+ * @brief Function for writing a 32-bit word to flash.
+ *
+ * To determine if the flash write has been completed, use @ref nrfx_nvmc_write_done_check().
+ *
+ * @note Depending on the source of the code being executed,
+ * the CPU may be halted during the operation.
+ * Refer to the Product Specification for more information.
+ *
+ * @param address Address to write to. Must be word-aligned.
+ * @param value Value to write.
+ */
+void nrfx_nvmc_word_write(uint32_t address, uint32_t value);
+
+/**
+ * @brief Function for writing consecutive bytes to flash.
+ *
+ * To determine if the last flash write has been completed, use @ref nrfx_nvmc_write_done_check().
+ *
+ * @note Depending on the source of the code being executed,
+ * the CPU may be halted during the operation.
+ * Refer to the Product Specification for more information.
+ *
+ * @param address Address to write to.
+ * @param src Pointer to the data to copy from.
+ * @param num_bytes Number of bytes to write.
+ */
+void nrfx_nvmc_bytes_write(uint32_t address, void const * src, uint32_t num_bytes);
+
+/**
+ * @brief Function for writing consecutive words to flash.
+ *
+ * To determine if the last flash write has been completed, use @ref nrfx_nvmc_write_done_check().
+ *
+ * @note Depending on the source of the code being executed,
+ * the CPU may be halted during the operation.
+ * Refer to the Product Specification for more information.
+ *
+ * @param address Address to write to. Must be word-aligned.
+ * @param src Pointer to data to copy from. Must be word-aligned.
+ * @param num_words Number of words to write.
+ */
+void nrfx_nvmc_words_write(uint32_t address, void const * src, uint32_t num_words);
+
+/**
+ * @brief Function for getting the total flash size in bytes.
+ *
+ * @return Flash total size in bytes.
+ */
+uint32_t nrfx_nvmc_flash_size_get(void);
+
+/**
+ * @brief Function for getting the flash page size in bytes.
+ *
+ * @return Flash page size in bytes.
+ */
+uint32_t nrfx_nvmc_flash_page_size_get(void);
+
+/**
+ * @brief Function for getting the flash page count.
+ *
+ * @return Flash page count.
+ */
+uint32_t nrfx_nvmc_flash_page_count_get(void);
+
+/**
+ * @brief Function for checking if the last flash write has been completed.
+ *
+ * @retval true Last write completed successfully.
+ * @retval false Last write is still in progress.
+ */
+__STATIC_INLINE bool nrfx_nvmc_write_done_check(void);
+
+#if defined(NRF_NVMC_ICACHE_PRESENT)
+/**
+ * @brief Function for enabling the Instruction Cache (ICache).
+ *
+ * Enabling ICache reduces the amount of accesses to flash memory,
+ * which can boost performance and lower power consumption.
+ */
+__STATIC_INLINE void nrfx_nvmc_icache_enable(void);
+
+/** @brief Function for disabling ICache. */
+__STATIC_INLINE void nrfx_nvmc_icache_disable(void);
+
+#endif // defined(NRF_NVMC_ICACHE_PRESENT)
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE bool nrfx_nvmc_write_done_check(void)
+{
+ return nrf_nvmc_ready_check(NRF_NVMC);
+}
+
+#if defined(NRF_NVMC_ICACHE_PRESENT)
+__STATIC_INLINE void nrfx_nvmc_icache_enable(void)
+{
+ nrf_nvmc_icache_config_set(NRF_NVMC, NRF_NVMC_ICACHE_ENABLE_WITH_PROFILING);
+}
+
+__STATIC_INLINE void nrfx_nvmc_icache_disable(void)
+{
+ nrf_nvmc_icache_config_set(NRF_NVMC, NRF_NVMC_ICACHE_DISABLE);
+}
+#endif // defined(NRF_NVMC_ICACHE_PRESENT)
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_NVMC_H__
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pdm.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pdm.h
index d7896dd14..1fc2ee771 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pdm.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pdm.h
@@ -46,32 +46,25 @@ extern "C" {
* @brief Pulse Density Modulation (PDM) peripheral driver.
*/
-
+/** @brief Maximum supported PDM buffer size. */
#define NRFX_PDM_MAX_BUFFER_SIZE 32767
-
-/**
- * @brief PDM error type.
- */
+/** @brief PDM error type. */
typedef enum
{
- NRFX_PDM_NO_ERROR = 0,
- NRFX_PDM_ERROR_OVERFLOW = 1
+ NRFX_PDM_NO_ERROR = 0, ///< No error.
+ NRFX_PDM_ERROR_OVERFLOW = 1 ///< Overflow error.
} nrfx_pdm_error_t;
-/**
- * @brief PDM event structure.
- */
+/** @brief PDM event structure. */
typedef struct
{
- bool buffer_requested; ///< Buffer request flag.
- int16_t * buffer_released; ///< Pointer to the released buffer. Can be NULL.
- nrfx_pdm_error_t error; ///< Error type.
+ bool buffer_requested; ///< Buffer request flag.
+ int16_t * buffer_released; ///< Pointer to the released buffer. Can be NULL.
+ nrfx_pdm_error_t error; ///< Error type.
} nrfx_pdm_evt_t;
-/**
- * @brief PDM interface driver configuration structure.
- */
+/** @brief PDM interface driver configuration structure. */
typedef struct
{
nrf_pdm_mode_t mode; ///< Interface operation mode.
@@ -86,7 +79,7 @@ typedef struct
/**
* @brief Macro for setting @ref nrfx_pdm_config_t to default settings
- * in single ended mode.
+ * in the single-ended mode.
*
* @param _pin_clk CLK output pin.
* @param _pin_din DIN input pin.
@@ -104,7 +97,7 @@ typedef struct
}
/**
- * @brief Handler for PDM interface ready events.
+ * @brief Handler for the PDM interface ready events.
*
* This event handler is called on a buffer request, an error or when a buffer
* is full and ready to be processed.
@@ -117,12 +110,12 @@ typedef void (*nrfx_pdm_event_handler_t)(nrfx_pdm_evt_t const * const p_evt);
/**
* @brief Function for initializing the PDM interface.
*
- * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] event_handler Event handler provided by the user. Cannot be NULL.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized.
- * @retval NRFX_ERROR_INVALID_PARAM If invalid configuration was specified.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver is already initialized.
+ * @retval NRFX_ERROR_INVALID_PARAM Invalid configuration was specified.
*/
nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config,
nrfx_pdm_event_handler_t event_handler);
@@ -137,9 +130,9 @@ void nrfx_pdm_uninit(void);
/**
* @brief Function for getting the address of a PDM interface task.
*
- * @param[in] task Task.
+ * @param[in] task Task.
*
- * @return Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrfx_pdm_task_address_get(nrf_pdm_task_t task)
{
@@ -149,8 +142,8 @@ __STATIC_INLINE uint32_t nrfx_pdm_task_address_get(nrf_pdm_task_t task)
/**
* @brief Function for getting the state of the PDM interface.
*
- * @retval true If the PDM interface is enabled.
- * @retval false If the PDM interface is disabled.
+ * @retval true The PDM interface is enabled.
+ * @retval false The PDM interface is disabled.
*/
__STATIC_INLINE bool nrfx_pdm_enable_check(void)
{
@@ -158,46 +151,46 @@ __STATIC_INLINE bool nrfx_pdm_enable_check(void)
}
/**
- * @brief Function for starting PDM sampling.
+ * @brief Function for starting the PDM sampling.
*
- * @retval NRFX_SUCCESS If sampling was started successfully or was already in progress.
- * @retval NRFX_ERROR_BUSY If a previous start/stop operation is in progress.
+ * @retval NRFX_SUCCESS Sampling was started successfully or was already in progress.
+ * @retval NRFX_ERROR_BUSY Previous start/stop operation is in progress.
*/
nrfx_err_t nrfx_pdm_start(void);
/**
- * @brief Function for stopping PDM sampling.
+ * @brief Function for stopping the PDM sampling.
*
* When this function is called, the PDM interface is stopped after finishing
* the current frame.
* The event handler function might be called once more after calling this function.
*
- * @retval NRFX_SUCCESS If sampling was stopped successfully or was already stopped before.
- * @retval NRFX_ERROR_BUSY If a previous start/stop operation is in progress.
+ * @retval NRFX_SUCCESS Sampling was stopped successfully or was already stopped before.
+ * @retval NRFX_ERROR_BUSY Previous start/stop operation is in progress.
*/
nrfx_err_t nrfx_pdm_stop(void);
/**
- * @brief Function for supplying the sample buffer.
+ * @brief Function for supplying the sample buffer.
*
* Call this function after every buffer request event.
*
- * @param[in] buffer Pointer to the receive buffer. Cannot be NULL.
- * @param[in] buffer_length Length of the receive buffer in 16-bit words.
+ * @param[in] buffer Pointer to the receive buffer. Cannot be NULL.
+ * @param[in] buffer_length Length of the receive buffer in 16-bit words.
*
- * @retval NRFX_SUCCESS If the buffer was applied successfully.
- * @retval NRFX_ERROR_BUSY If the buffer was already supplied or the peripheral is currently being stopped.
- * @retval NRFX_ERROR_INVALID_STATE If the driver was not initialized.
- * @retval NRFX_ERROR_INVALID_PARAM If invalid parameters were provided.
+ * @retval NRFX_SUCCESS The buffer was applied successfully.
+ * @retval NRFX_ERROR_BUSY The buffer was already supplied or the peripheral is currently being stopped.
+ * @retval NRFX_ERROR_INVALID_STATE The driver was not initialized.
+ * @retval NRFX_ERROR_INVALID_PARAM Invalid parameters were provided.
*/
nrfx_err_t nrfx_pdm_buffer_set(int16_t * buffer, uint16_t buffer_length);
+/** @} */
+
void nrfx_pdm_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power.h
index ba87f29bc..adb65de22 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power.h
@@ -92,26 +92,26 @@ typedef enum
*/
typedef enum
{
- NRFX_POWER_USB_STATE_DISCONNECTED, /**< No power on USB lines detected */
- NRFX_POWER_USB_STATE_CONNECTED, /**< The USB power is detected, but USB power regulator is not ready */
- NRFX_POWER_USB_STATE_READY /**< From the power point of view USB is ready for working */
+ NRFX_POWER_USB_STATE_DISCONNECTED, /**< No power on USB lines detected. */
+ NRFX_POWER_USB_STATE_CONNECTED, /**< The USB power is detected, but USB power regulator is not ready. */
+ NRFX_POWER_USB_STATE_READY /**< From the power viewpoint, USB is ready for working. */
}nrfx_power_usb_state_t;
#endif /* NRF_POWER_HAS_USBREG */
/**
* @name Callback types
*
- * Defined types of callback functions
+ * Defined types of callback functions.
* @{
*/
/**
- * @brief Event handler for power failure warning
+ * @brief Event handler for power failure warning.
*/
typedef void (*nrfx_power_pofwarn_event_handler_t)(void);
#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__)
/**
- * @brief Event handler for entering/exiting sleep
+ * @brief Event handler for the sleep events.
*
* @param event Event type
*/
@@ -120,7 +120,7 @@ typedef void (*nrfx_power_sleep_event_handler_t)(nrfx_power_sleep_evt_t event);
#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__)
/**
- * @brief Event handler for USB related power events
+ * @brief Event handler for the USB-related power events.
*
* @param event Event type
*/
@@ -136,22 +136,22 @@ typedef void (*nrfx_power_usb_event_handler_t)(nrfx_power_usb_evt_t event);
typedef struct
{
/**
- * @brief Enable main DCDC regulator
+ * @brief Enable main DCDC regulator.
*
* This bit only informs the driver that elements for DCDC regulator
- * are installed and regulator can be used.
- * The regulator would be enabled or disabled automatically
+ * are installed and the regulator can be used.
+ * The regulator will be enabled or disabled automatically
* by the hardware, basing on current power requirement.
*/
bool dcdcen:1;
#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__)
/**
- * @brief Enable HV DCDC regulator
+ * @brief Enable HV DCDC regulator.
*
* This bit only informs the driver that elements for DCDC regulator
- * are installed and regulator can be used.
- * The regulator would be enabled or disabled automatically
+ * are installed and the regulator can be used.
+ * The regulator will be enabled or disabled automatically
* by the hardware, basing on current power requirement.
*/
bool dcdcenhv: 1;
@@ -159,44 +159,44 @@ typedef struct
}nrfx_power_config_t;
/**
- * @brief The configuration for power failure comparator
+ * @brief The configuration for power failure comparator.
*
- * Configuration used to enable and configure power failure comparator
+ * Configuration used to enable and configure the power failure comparator.
*/
typedef struct
{
- nrfx_power_pofwarn_event_handler_t handler; //!< Event handler
+ nrfx_power_pofwarn_event_handler_t handler; //!< Event handler.
#if NRF_POWER_HAS_POFCON || defined(__NRFX_DOXYGEN__)
nrf_power_pof_thr_t thr; //!< Threshold for power failure detection
#endif
#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__)
- nrf_power_pof_thrvddh_t thrvddh; //!< Threshold for power failure detection on VDDH pin
+ nrf_power_pof_thrvddh_t thrvddh; //!< Threshold for power failure detection on the VDDH pin.
#endif
}nrfx_power_pofwarn_config_t;
#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__)
/**
- * @brief The configuration of sleep event processing
+ * @brief The configuration of sleep event processing.
*
- * Configuration used to enable and configure sleep event handling
+ * Configuration used to enable and configure sleep event handling.
*/
typedef struct
{
- nrfx_power_sleep_event_handler_t handler; //!< Event handler
- bool en_enter:1; //!< Enable event on sleep entering
- bool en_exit :1; //!< Enable event on sleep exiting
+ nrfx_power_sleep_event_handler_t handler; //!< Event handler.
+ bool en_enter:1; //!< Enable event on sleep entering.
+ bool en_exit :1; //!< Enable event on sleep exiting.
}nrfx_power_sleepevt_config_t;
#endif
#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__)
/**
- * @brief The configuration of USB related power events
+ * @brief The configuration of the USB-related power events.
*
- * Configuration used to enable and configure USB power event handling
+ * Configuration used to enable and configure USB power event handling.
*/
typedef struct
{
- nrfx_power_usb_event_handler_t handler; //!< Event processing
+ nrfx_power_usb_event_handler_t handler; //!< Event processing.
}nrfx_power_usbevt_config_t;
#endif /* NRF_POWER_HAS_USBREG */
@@ -215,11 +215,11 @@ nrfx_power_usb_event_handler_t nrfx_power_usb_handler_get(void);
#endif
/**
- * @brief Initialize power module driver
+ * @brief Function for initializing the power module driver.
*
- * Enabled power module driver would process all the interrupts from power system.
+ * Enabled power module driver processes all the interrupts from the power system.
*
- * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
*
* @retval NRFX_SUCCESS Successfully initialized.
* @retval NRFX_ERROR_ALREADY_INITIALIZED Module was already initialized.
@@ -227,7 +227,7 @@ nrfx_power_usb_event_handler_t nrfx_power_usb_handler_get(void);
nrfx_err_t nrfx_power_init(nrfx_power_config_t const * p_config);
/**
- * @brief Unintialize power module driver
+ * @brief Function for unintializing the power module driver.
*
* Disables all the interrupt handling in the module.
*
@@ -237,36 +237,36 @@ void nrfx_power_uninit(void);
#if NRF_POWER_HAS_POFCON || defined(__NRFX_DOXYGEN__)
/**
- * @brief Initialize power failure comparator
+ * @brief Function for initializing the power failure comparator.
*
- * Configures the power failure comparator. This function does not setup and enable it.
- * Those steps can be done with functions @ref nrfx_power_pof_enable and @ref nrfx_power_pof_disable
- * or with Softdevice API (when Softdevice is using).
+ * Configures the power failure comparator. This function does not set it up and enable it.
+ * These steps can be done with functions @ref nrfx_power_pof_enable and @ref nrfx_power_pof_disable
+ * or with the SoftDevice API (when in use).
*
* @param[in] p_config Configuration with values and event handler.
- * If event handler is set to NULL, interrupt would be disabled.
+ * If event handler is set to NULL, the interrupt will be disabled.
*/
void nrfx_power_pof_init(nrfx_power_pofwarn_config_t const * p_config);
/**
- * @brief Enable power failure comparator
- * Sets and enables interrupt of the power failure comparator. This functions cannot be using
- * when Softdevice is enabled. If event handler set in init function is set to NULL, interrupt
- * would be disabled.
+ * @brief Function for enabling the power failure comparator.
+ * Sets and enables the interrupt of the power failure comparator. This function cannot be in use
+ * when SoftDevice is enabled. If the event handler set in the init function is set to NULL, the interrupt
+ * will be disabled.
*
* @param[in] p_config Configuration with values and event handler.
*/
void nrfx_power_pof_enable(nrfx_power_pofwarn_config_t const * p_config);
/**
- * @brief Disable the power failure comparator
+ * @brief Function for disabling the power failure comparator.
*
* Disables the power failure comparator interrupt.
*/
void nrfx_power_pof_disable(void);
/**
- * @brief Clear the power failure comparator settings
+ * @brief Function for clearing the power failure comparator settings.
*
* Clears the settings of the power failure comparator.
*/
@@ -275,9 +275,9 @@ void nrfx_power_pof_uninit(void);
#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__)
/**
- * @brief Initialize sleep entering and exiting events processing
+ * @brief Function for initializing the processing of the sleep events.
*
- * Configures and setups the sleep event processing.
+ * Configures and sets up the sleep event processing.
*
* @param[in] p_config Configuration with values and event handler.
*
@@ -287,19 +287,17 @@ void nrfx_power_pof_uninit(void);
void nrfx_power_sleepevt_init(nrfx_power_sleepevt_config_t const * p_config);
/**
- * @brief Enable sleep entering and exiting events processing
+ * @brief Function for enabling the processing of the sleep events.
*
* @param[in] p_config Configuration with values and event handler.
*/
void nrfx_power_sleepevt_enable(nrfx_power_sleepevt_config_t const * p_config);
-/**
- * @brief Disable sleep entering and exiting events processing
- */
+/** @brief Function for disabling the processing of the sleep events. */
void nrfx_power_sleepevt_disable(void);
/**
- * @brief Uninitialize sleep entering and exiting events processing
+ * @brief Function for uninitializing the processing of the sleep events.
*
* @sa nrfx_power_sleepevt_init
*/
@@ -308,9 +306,9 @@ void nrfx_power_sleepevt_uninit(void);
#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__)
/**
- * @brief Initialize USB power event processing
+ * @brief Function for initializing the processing of USB power event.
*
- * Configures and setups the USB power event processing.
+ * Configures and sets up the USB power event processing.
*
* @param[in] p_config Configuration with values and event handler.
*
@@ -318,27 +316,23 @@ void nrfx_power_sleepevt_uninit(void);
*/
void nrfx_power_usbevt_init(nrfx_power_usbevt_config_t const * p_config);
-/**
- * @brief Enable USB power event processing
- */
+/** @brief Function for enabling the processing of USB power event. */
void nrfx_power_usbevt_enable(void);
-/**
- * @brief Disable USB power event processing
- */
+/** @brief Function for disabling the processing of USB power event. */
void nrfx_power_usbevt_disable(void);
/**
- * @brief Uninitalize USB power event processing
+ * @brief Function for uninitalizing the processing of USB power event.
*
* @sa nrfx_power_usbevt_init
*/
void nrfx_power_usbevt_uninit(void);
/**
- * @brief Get the status of USB power
+ * @brief Function for getting the status of USB power.
*
- * @return Current USB power status
+ * @return Current USB power status.
*/
__STATIC_INLINE nrfx_power_usb_state_t nrfx_power_usbstatus_get(void);
@@ -364,12 +358,12 @@ __STATIC_INLINE nrfx_power_usb_state_t nrfx_power_usbstatus_get(void)
#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
+/** @} */
+
void nrfx_power_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power_clock.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power_clock.h
index 043b0e49b..e18858255 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power_clock.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_power_clock.h
@@ -47,13 +47,15 @@ __STATIC_INLINE void nrfx_power_clock_irq_init(void)
uint8_t priority;
#if NRFX_CHECK(NRFX_POWER_ENABLED) && NRFX_CHECK(NRFX_CLOCK_ENABLED)
#if NRFX_POWER_CONFIG_IRQ_PRIORITY != NRFX_CLOCK_CONFIG_IRQ_PRIORITY
- #error "IRQ priority for POWER and CLOCK have to be the same. Check ."
+ #error "IRQ priorities for POWER and CLOCK must be the same. Check ."
#endif
priority = NRFX_POWER_CONFIG_IRQ_PRIORITY;
#elif NRFX_CHECK(NRFX_POWER_ENABLED)
priority = NRFX_POWER_CONFIG_IRQ_PRIORITY;
#elif NRFX_CHECK(NRFX_CLOCK_ENABLED)
priority = NRFX_CLOCK_CONFIG_IRQ_PRIORITY;
+#else
+ #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif
if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_ppi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_ppi.h
index cbd26901d..e2f22cdde 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_ppi.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_ppi.h
@@ -46,23 +46,28 @@
extern "C" {
#endif
-#ifndef NRFX_PPI_CHANNELS_USED
+#if !defined (NRFX_PPI_CHANNELS_USED) || defined(__NRFX_DOXYGEN__)
+/** @brief Bitfield representing PPI channels used by external modules. */
#define NRFX_PPI_CHANNELS_USED 0
#endif
-#ifndef NRFX_PPI_GROUPS_USED
+#if !defined(NRFX_PPI_GROUPS_USED) || defined(__NRFX_DOXYGEN__)
+/** @brief Bitfield representing PPI groups used by external modules. */
#define NRFX_PPI_GROUPS_USED 0
#endif
-#if PPI_CH_NUM > 16
-#define NRFX_PPI_ALL_APP_CHANNELS_MASK ((uint32_t)0xFFFFFFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< All PPI channels available to the application. */
-#define NRFX_PPI_PROG_APP_CHANNELS_MASK ((uint32_t)0x000FFFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< Programmable PPI channels available to the application. */
+#if (PPI_CH_NUM > 16) || defined(__NRFX_DOXYGEN__)
+/** @brief Bitfield representing all PPI channels available to the application. */
+#define NRFX_PPI_ALL_APP_CHANNELS_MASK ((uint32_t)0xFFFFFFFFuL & ~(NRFX_PPI_CHANNELS_USED))
+/** @brief Bitfield representing programmable PPI channels available to the application. */
+#define NRFX_PPI_PROG_APP_CHANNELS_MASK ((uint32_t)0x000FFFFFuL & ~(NRFX_PPI_CHANNELS_USED))
#else
-#define NRFX_PPI_ALL_APP_CHANNELS_MASK ((uint32_t)0xFFF0FFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< All PPI channels available to the application. */
-#define NRFX_PPI_PROG_APP_CHANNELS_MASK ((uint32_t)0x0000FFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< Programmable PPI channels available to the application. */
+#define NRFX_PPI_ALL_APP_CHANNELS_MASK ((uint32_t)0xFFF0FFFFuL & ~(NRFX_PPI_CHANNELS_USED))
+#define NRFX_PPI_PROG_APP_CHANNELS_MASK ((uint32_t)0x0000FFFFuL & ~(NRFX_PPI_CHANNELS_USED))
#endif
-#define NRFX_PPI_ALL_APP_GROUPS_MASK (((1uL << PPI_GROUP_NUM) - 1) & ~(NRFX_PPI_GROUPS_USED)) /**< All PPI groups available to the application. */
+/** @brief Bitfield representing all PPI groups available to the application. */
+#define NRFX_PPI_ALL_APP_GROUPS_MASK (((1uL << PPI_GROUP_NUM) - 1) & ~(NRFX_PPI_GROUPS_USED))
/**
* @brief Function for uninitializing the PPI module.
@@ -77,8 +82,8 @@ void nrfx_ppi_free_all(void);
*
* @param[out] p_channel Pointer to the PPI channel that has been allocated.
*
- * @retval NRFX_SUCCESS If the channel was successfully allocated.
- * @retval NRFX_ERROR_NO_MEM If there is no available channel to be used.
+ * @retval NRFX_SUCCESS The channel was successfully allocated.
+ * @retval NRFX_ERROR_NO_MEM There is no available channel to be used.
*/
nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel);
@@ -88,8 +93,8 @@ nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel);
*
* @param[in] channel PPI channel to be freed.
*
- * @retval NRFX_SUCCESS If the channel was successfully freed.
- * @retval NRFX_ERROR_INVALID_PARAM If the channel is not user-configurable.
+ * @retval NRFX_SUCCESS The channel was successfully freed.
+ * @retval NRFX_ERROR_INVALID_PARAM The channel is not user-configurable.
*/
nrfx_err_t nrfx_ppi_channel_free(nrf_ppi_channel_t channel);
@@ -100,21 +105,21 @@ nrfx_err_t nrfx_ppi_channel_free(nrf_ppi_channel_t channel);
* @param[in] eep Event endpoint address.
* @param[in] tep Task endpoint address.
*
- * @retval NRFX_SUCCESS If the channel was successfully assigned.
- * @retval NRFX_ERROR_INVALID_STATE If the channel is not allocated for the user.
- * @retval NRFX_ERROR_INVALID_PARAM If the channel is not user-configurable.
+ * @retval NRFX_SUCCESS The channel was successfully assigned.
+ * @retval NRFX_ERROR_INVALID_STATE The channel is not allocated for the user.
+ * @retval NRFX_ERROR_INVALID_PARAM The channel is not user-configurable.
*/
nrfx_err_t nrfx_ppi_channel_assign(nrf_ppi_channel_t channel, uint32_t eep, uint32_t tep);
/**
- * @brief Function for assigning or clearing fork endpoint to the PPI channel.
+ * @brief Function for assigning fork endpoint to the PPI channel or clearing it.
*
* @param[in] channel PPI channel to be assigned endpoints.
* @param[in] fork_tep Fork task endpoint address or 0 to clear.
*
- * @retval NRFX_SUCCESS If the channel was successfully assigned.
- * @retval NRFX_ERROR_INVALID_STATE If the channel is not allocated for the user.
- * @retval NRFX_ERROR_NOT_SUPPORTED If function is not supported.
+ * @retval NRFX_SUCCESS The channel was successfully assigned.
+ * @retval NRFX_ERROR_INVALID_STATE The channel is not allocated for the user.
+ * @retval NRFX_ERROR_NOT_SUPPORTED Function is not supported.
*/
nrfx_err_t nrfx_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork_tep);
@@ -123,9 +128,9 @@ nrfx_err_t nrfx_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork
*
* @param[in] channel PPI channel to be enabled.
*
- * @retval NRFX_SUCCESS If the channel was successfully enabled.
- * @retval NRFX_ERROR_INVALID_STATE If the user-configurable channel is not allocated.
- * @retval NRFX_ERROR_INVALID_PARAM If the channel cannot be enabled by the user.
+ * @retval NRFX_SUCCESS The channel was successfully enabled.
+ * @retval NRFX_ERROR_INVALID_STATE The user-configurable channel is not allocated.
+ * @retval NRFX_ERROR_INVALID_PARAM The channel cannot be enabled by the user.
*/
nrfx_err_t nrfx_ppi_channel_enable(nrf_ppi_channel_t channel);
@@ -134,9 +139,9 @@ nrfx_err_t nrfx_ppi_channel_enable(nrf_ppi_channel_t channel);
*
* @param[in] channel PPI channel to be disabled.
*
- * @retval NRFX_SUCCESS If the channel was successfully disabled.
- * @retval NRFX_ERROR_INVALID_STATE If the user-configurable channel is not allocated.
- * @retval NRFX_ERROR_INVALID_PARAM If the channel cannot be disabled by the user.
+ * @retval NRFX_SUCCESS The channel was successfully disabled.
+ * @retval NRFX_ERROR_INVALID_STATE The user-configurable channel is not allocated.
+ * @retval NRFX_ERROR_INVALID_PARAM The channel cannot be disabled by the user.
*/
nrfx_err_t nrfx_ppi_channel_disable(nrf_ppi_channel_t channel);
@@ -146,8 +151,8 @@ nrfx_err_t nrfx_ppi_channel_disable(nrf_ppi_channel_t channel);
*
* @param[out] p_group Pointer to the PPI channel group that has been allocated.
*
- * @retval NRFX_SUCCESS If the channel group was successfully allocated.
- * @retval NRFX_ERROR_NO_MEM If there is no available channel group to be used.
+ * @retval NRFX_SUCCESS The channel group was successfully allocated.
+ * @retval NRFX_ERROR_NO_MEM There is no available channel group to be used.
*/
nrfx_err_t nrfx_ppi_group_alloc(nrf_ppi_channel_group_t * p_group);
@@ -157,8 +162,8 @@ nrfx_err_t nrfx_ppi_group_alloc(nrf_ppi_channel_group_t * p_group);
*
* @param[in] group PPI channel group to be freed.
*
- * @retval NRFX_SUCCESS If the channel group was successfully freed.
- * @retval NRFX_ERROR_INVALID_PARAM If the channel group is not user-configurable.
+ * @retval NRFX_SUCCESS The channel group was successfully freed.
+ * @retval NRFX_ERROR_INVALID_PARAM The channel group is not user-configurable.
*/
nrfx_err_t nrfx_ppi_group_free(nrf_ppi_channel_group_t group);
@@ -167,7 +172,7 @@ nrfx_err_t nrfx_ppi_group_free(nrf_ppi_channel_group_t group);
*
* @param[in] channel Channel number to transform to a mask.
*
- * @retval Channel mask.
+ * @return Channel mask.
*/
__STATIC_INLINE uint32_t nrfx_ppi_channel_to_mask(nrf_ppi_channel_t channel)
{
@@ -180,10 +185,10 @@ __STATIC_INLINE uint32_t nrfx_ppi_channel_to_mask(nrf_ppi_channel_t channel)
* @param[in] channel_mask PPI channels to be added.
* @param[in] group Channel group in which to include the channels.
*
- * @retval NRFX_SUCCESS If the channels was successfully included.
- * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channels are not an
+ * @retval NRFX_SUCCESS The channels was successfully included.
+ * @retval NRFX_ERROR_INVALID_PARAM Group is not an application group or channels are not an
* application channels.
- * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group.
+ * @retval NRFX_ERROR_INVALID_STATE Group is not an allocated group.
*/
nrfx_err_t nrfx_ppi_channels_include_in_group(uint32_t channel_mask,
nrf_ppi_channel_group_t group);
@@ -194,10 +199,10 @@ nrfx_err_t nrfx_ppi_channels_include_in_group(uint32_t channel_ma
* @param[in] channel PPI channel to be added.
* @param[in] group Channel group in which to include the channel.
*
- * @retval NRFX_SUCCESS If the channel was successfully included.
- * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channel is not an
+ * @retval NRFX_SUCCESS The channel was successfully included.
+ * @retval NRFX_ERROR_INVALID_PARAM Group is not an application group or channel is not an
* application channel.
- * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group.
+ * @retval NRFX_ERROR_INVALID_STATE Group is not an allocated group.
*/
__STATIC_INLINE nrfx_err_t nrfx_ppi_channel_include_in_group(nrf_ppi_channel_t channel,
nrf_ppi_channel_group_t group)
@@ -211,24 +216,24 @@ __STATIC_INLINE nrfx_err_t nrfx_ppi_channel_include_in_group(nrf_ppi_channel_t
* @param[in] channel_mask PPI channels to be removed.
* @param[in] group Channel group from which to remove the channels.
*
- * @retval NRFX_SUCCESS If the channel was successfully removed.
- * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channels are not an
+ * @retval NRFX_SUCCESS The channel was successfully removed.
+ * @retval NRFX_ERROR_INVALID_PARAM Group is not an application group or channels are not an
* application channels.
- * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group.
+ * @retval NRFX_ERROR_INVALID_STATE Group is not an allocated group.
*/
nrfx_err_t nrfx_ppi_channels_remove_from_group(uint32_t channel_mask,
nrf_ppi_channel_group_t group);
/**
- * @brief Function for removing a PPI channel from a channel group.
+ * @brief Function for removing a single PPI channel from a channel group.
*
* @param[in] channel PPI channel to be removed.
* @param[in] group Channel group from which to remove the channel.
*
- * @retval NRFX_SUCCESS If the channel was successfully removed.
- * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channel is not an
+ * @retval NRFX_SUCCESS The channel was successfully removed.
+ * @retval NRFX_ERROR_INVALID_PARAM Group is not an application group or channel is not an
* application channel.
- * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group.
+ * @retval NRFX_ERROR_INVALID_STATE Group is not an allocated group.
*/
__STATIC_INLINE nrfx_err_t nrfx_ppi_channel_remove_from_group(nrf_ppi_channel_t channel,
nrf_ppi_channel_group_t group)
@@ -241,9 +246,9 @@ __STATIC_INLINE nrfx_err_t nrfx_ppi_channel_remove_from_group(nrf_ppi_channel_t
*
* @param[in] group Channel group to be cleared.
*
- * @retval NRFX_SUCCESS If the group was successfully cleared.
- * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group.
- * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group.
+ * @retval NRFX_SUCCESS The group was successfully cleared.
+ * @retval NRFX_ERROR_INVALID_PARAM Group is not an application group.
+ * @retval NRFX_ERROR_INVALID_STATE Group is not an allocated group.
*/
__STATIC_INLINE nrfx_err_t nrfx_ppi_group_clear(nrf_ppi_channel_group_t group)
{
@@ -255,9 +260,9 @@ __STATIC_INLINE nrfx_err_t nrfx_ppi_group_clear(nrf_ppi_channel_group_t group)
*
* @param[in] group Channel group to be enabled.
*
- * @retval NRFX_SUCCESS If the group was successfully enabled.
- * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group.
- * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group.
+ * @retval NRFX_SUCCESS The group was successfully enabled.
+ * @retval NRFX_ERROR_INVALID_PARAM Group is not an application group.
+ * @retval NRFX_ERROR_INVALID_STATE Group is not an allocated group.
*/
nrfx_err_t nrfx_ppi_group_enable(nrf_ppi_channel_group_t group);
@@ -266,9 +271,9 @@ nrfx_err_t nrfx_ppi_group_enable(nrf_ppi_channel_group_t group);
*
* @param[in] group Channel group to be disabled.
*
- * @retval NRFX_SUCCESS If the group was successfully disabled.
- * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group.
- * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group.
+ * @retval NRFX_SUCCESS The group was successfully disabled.
+ * @retval NRFX_ERROR_INVALID_PARAM Group is not an application group.
+ * @retval NRFX_ERROR_INVALID_STATE Group is not an allocated group.
*/
nrfx_err_t nrfx_ppi_group_disable(nrf_ppi_channel_group_t group);
@@ -277,7 +282,7 @@ nrfx_err_t nrfx_ppi_group_disable(nrf_ppi_channel_group_t group);
*
* @param[in] task Task.
*
- * @retval Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrfx_ppi_task_addr_get(nrf_ppi_task_t task)
{
@@ -285,11 +290,11 @@ __STATIC_INLINE uint32_t nrfx_ppi_task_addr_get(nrf_ppi_task_t task)
}
/**
- * @brief Function for getting the address of a PPI group enable task.
+ * @brief Function for getting the address of the enable task of a PPI group.
*
* @param[in] group PPI channel group
*
- * @retval Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrfx_ppi_task_addr_group_enable_get(nrf_ppi_channel_group_t group)
{
@@ -297,11 +302,11 @@ __STATIC_INLINE uint32_t nrfx_ppi_task_addr_group_enable_get(nrf_ppi_channel_gro
}
/**
- * @brief Function for getting the address of a PPI group enable task.
+ * @brief Function for getting the address of the enable task of a PPI group.
*
* @param[in] group PPI channel group
*
- * @retval Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrfx_ppi_task_addr_group_disable_get(nrf_ppi_channel_group_t group)
{
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pwm.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pwm.h
index ec05b42dd..60cb6c551 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pwm.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_pwm.h
@@ -46,24 +46,21 @@ extern "C" {
* @brief Pulse Width Modulation (PWM) peripheral driver.
*/
-/**
- * @brief PWM driver instance data structure.
- */
+/** @brief PWM driver instance data structure. */
typedef struct
{
NRF_PWM_Type * p_registers; ///< Pointer to the structure with PWM peripheral instance registers.
- uint8_t drv_inst_idx; ///< Driver instance index.
+ uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only.
} nrfx_pwm_t;
-/**
- * @brief Macro for creating a PWM driver instance.
- */
+/** @brief Macro for creating a PWM driver instance. */
#define NRFX_PWM_INSTANCE(id) \
{ \
.p_registers = NRFX_CONCAT_2(NRF_PWM, id), \
.drv_inst_idx = NRFX_CONCAT_3(NRFX_PWM, id, _INST_IDX), \
}
+#ifndef __NRFX_DOXYGEN__
enum {
#if NRFX_CHECK(NRFX_PWM0_ENABLED)
NRFX_PWM0_INST_IDX,
@@ -79,6 +76,7 @@ enum {
#endif
NRFX_PWM_ENABLED_COUNT
};
+#endif
/**
* @brief This value can be provided instead of a pin number for any channel
@@ -87,15 +85,10 @@ enum {
*/
#define NRFX_PWM_PIN_NOT_USED 0xFF
-/**
- * @brief This value can be added to a pin number to inverse its polarity
- * (set idle state = 1).
- */
+/** @brief This value can be added to a pin number to invert its polarity (set idle state = 1). */
#define NRFX_PWM_PIN_INVERTED 0x80
-/**
- * @brief PWM driver configuration structure.
- */
+/** @brief PWM driver configuration structure. */
typedef struct
{
uint8_t output_pins[NRF_PWM_CHANNEL_COUNT]; ///< Pin numbers for individual output channels (optional).
@@ -109,9 +102,7 @@ typedef struct
nrf_pwm_dec_step_t step_mode; ///< Mode of advancing the active sequence.
} nrfx_pwm_config_t;
-/**
- * @brief PWM driver default configuration.
- */
+/** @brief PWM driver default configuration. */
#define NRFX_PWM_DEFAULT_CONFIG \
{ \
.output_pins = { NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN, \
@@ -126,14 +117,11 @@ typedef struct
.step_mode = (nrf_pwm_dec_step_t)NRFX_PWM_DEFAULT_CONFIG_STEP_MODE, \
}
-
-/**
- * @brief PWM flags providing additional playback options.
- */
+/** @brief PWM flags that provide additional playback options. */
typedef enum
{
NRFX_PWM_FLAG_STOP = 0x01, /**< When the requested playback is finished,
- the peripheral should be stopped.
+ the peripheral will be stopped.
@note The STOP task is triggered when
the last value of the final sequence is
loaded from RAM, and the peripheral stops
@@ -143,7 +131,7 @@ typedef enum
less than the requested number of repeats
of the last value. */
NRFX_PWM_FLAG_LOOP = 0x02, /**< When the requested playback is finished,
- it should be started from the beginning.
+ it will be started from the beginning.
This flag is ignored if used together
with @ref NRFX_PWM_FLAG_STOP.
@note The playback restart is done via a
@@ -157,28 +145,25 @@ typedef enum
the playback restart will occur right
after switching to the final value (this
final value will be played only once). */
- NRFX_PWM_FLAG_SIGNAL_END_SEQ0 = 0x04, /**< The event handler should be
+ NRFX_PWM_FLAG_SIGNAL_END_SEQ0 = 0x04, /**< The event handler is to be
called when the last value
from sequence 0 is loaded. */
- NRFX_PWM_FLAG_SIGNAL_END_SEQ1 = 0x08, /**< The event handler should be
+ NRFX_PWM_FLAG_SIGNAL_END_SEQ1 = 0x08, /**< The event handler is to be
called when the last value
from sequence 1 is loaded. */
NRFX_PWM_FLAG_NO_EVT_FINISHED = 0x10, /**< The playback finished event
- (enabled by default) should be
+ (enabled by default) is to be
suppressed. */
- NRFX_PWM_FLAG_START_VIA_TASK = 0x80, /**< The playback should not be
+ NRFX_PWM_FLAG_START_VIA_TASK = 0x80, /**< The playback must not be
started directly by the called
function. Instead, the function
- should only prepare it and
+ must only prepare it and
return the address of the task
to be triggered to start the
playback. */
} nrfx_pwm_flag_t;
-
-/**
- * @brief PWM driver event type.
- */
+/** @brief PWM driver event type. */
typedef enum
{
NRFX_PWM_EVT_FINISHED, ///< Sequence playback finished.
@@ -189,24 +174,20 @@ typedef enum
NRFX_PWM_EVT_STOPPED, ///< The PWM peripheral has been stopped.
} nrfx_pwm_evt_type_t;
-/**
- * @brief PWM driver event handler type.
- */
+/** @brief PWM driver event handler type. */
typedef void (* nrfx_pwm_handler_t)(nrfx_pwm_evt_type_t event_type);
-
/**
* @brief Function for initializing the PWM driver.
*
* @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_config Pointer to the structure with initial configuration.
- *
+ * @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] handler Event handler provided by the user. If NULL is passed
* instead, event notifications are not done and PWM
* interrupts are disabled.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver was already initialized.
*/
nrfx_err_t nrfx_pwm_init(nrfx_pwm_t const * const p_instance,
nrfx_pwm_config_t const * p_config,
@@ -227,20 +208,20 @@ void nrfx_pwm_uninit(nrfx_pwm_t const * const p_instance);
* To take advantage of the looping mechanism in the PWM peripheral, both
* sequences must be used (single sequence can be played back only once by
* the peripheral). Therefore, the provided sequence is internally set and
- * played back as both sequence 0 and sequence 1. Consequently, if end of
- * sequence notifications are required, events for both sequences should be
- * used (that means that both the @ref NRFX_PWM_FLAG_SIGNAL_END_SEQ0 flag
- * and the @ref NRFX_PWM_FLAG_SIGNAL_END_SEQ1 flag should be specified and
+ * played back as both sequence 0 and sequence 1. Consequently, if the end of
+ * sequence notifications are required, events for both sequences must be
+ * used (that is, both the @ref NRFX_PWM_FLAG_SIGNAL_END_SEQ0 flag
+ * and the @ref NRFX_PWM_FLAG_SIGNAL_END_SEQ1 flag must be specified, and
* the @ref NRFX_PWM_EVT_END_SEQ0 event and the @ref NRFX_PWM_EVT_END_SEQ1
- * event should be handled in the same way).
+ * event must be handled in the same way).
*
* Use the @ref NRFX_PWM_FLAG_START_VIA_TASK flag if you want the playback
* to be only prepared by this function, and you want to start it later by
- * triggering a task (using PPI for instance). The function will then return
+ * triggering a task (for example, by using PPI). The function will then return
* the address of the task to be triggered.
*
* @note The array containing the duty cycle values for the specified sequence
- * must be in RAM and cannot be allocated on stack.
+ * must be in RAM and cannot be allocated on the stack.
* For detailed information, see @ref nrf_pwm_sequence_t.
*
* @param[in] p_instance Pointer to the driver instance structure.
@@ -267,7 +248,7 @@ uint32_t nrfx_pwm_simple_playback(nrfx_pwm_t const * const p_instance,
* the address of the task to be triggered.
*
* @note The array containing the duty cycle values for the specified sequence
- * must be in RAM and cannot be allocated on stack.
+ * must be in RAM and cannot be allocated on the stack.
* For detailed information, see @ref nrf_pwm_sequence_t.
*
* @param[in] p_instance Pointer to the driver instance structure.
@@ -305,7 +286,7 @@ __STATIC_INLINE void nrfx_pwm_step(nrfx_pwm_t const * const p_instance);
* might appear on the output less times than requested.
*
* @note This function can be instructed to wait until the playback is stopped
- * (by setting @p wait_until_stopped to true). Note that, depending on
+ * (by setting @p wait_until_stopped to true). Depending on
* the length of the PMW period, this might take a significant amount of
* time. Alternatively, the @ref nrfx_pwm_is_stopped function can be
* used to poll the status, or the @ref NRFX_PWM_EVT_STOPPED event can
@@ -316,19 +297,18 @@ __STATIC_INLINE void nrfx_pwm_step(nrfx_pwm_t const * const p_instance);
* @param[in] wait_until_stopped If true, the function will not return until
* the playback is stopped.
*
- * @retval true If the PWM peripheral is stopped.
- * @retval false If the PWM peripheral is not stopped.
+ * @retval true The PWM peripheral is stopped.
+ * @retval false The PWM peripheral is not stopped.
*/
-bool nrfx_pwm_stop(nrfx_pwm_t const * const p_instance,
- bool wait_until_stopped);
+bool nrfx_pwm_stop(nrfx_pwm_t const * const p_instance, bool wait_until_stopped);
/**
* @brief Function for checking the status of the PWM peripheral.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval true If the PWM peripheral is stopped.
- * @retval false If the PWM peripheral is not stopped.
+ * @retval true The PWM peripheral is stopped.
+ * @retval false The PWM peripheral is not stopped.
*/
bool nrfx_pwm_is_stopped(nrfx_pwm_t const * const p_instance);
@@ -339,10 +319,9 @@ bool nrfx_pwm_is_stopped(nrfx_pwm_t const * const p_instance);
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] p_sequence Pointer to the new sequence definition.
*/
-__STATIC_INLINE void nrfx_pwm_sequence_update(
- nrfx_pwm_t const * const p_instance,
- uint8_t seq_id,
- nrf_pwm_sequence_t const * p_sequence);
+__STATIC_INLINE void nrfx_pwm_sequence_update(nrfx_pwm_t const * const p_instance,
+ uint8_t seq_id,
+ nrf_pwm_sequence_t const * p_sequence);
/**
* @brief Function for updating the pointer to the duty cycle values
@@ -370,7 +349,7 @@ __STATIC_INLINE void nrfx_pwm_sequence_length_update(nrfx_pwm_t const * const p_
/**
* @brief Function for updating the number of repeats for duty cycle values
- * in specified sequence during playback.
+ * in the specified sequence during playback.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] seq_id Identifier of the sequence (0 or 1).
@@ -404,18 +383,18 @@ __STATIC_INLINE void nrfx_pwm_sequence_end_delay_update(nrfx_pwm_t const * const
__STATIC_INLINE uint32_t nrfx_pwm_task_address_get(nrfx_pwm_t const * const p_instance,
nrf_pwm_task_t task);
-/**@brief Function for returning the address of a specified PWM event that can
+/**
+ * @brief Function for returning the address of a specified PWM event that can
* be used in PPI module.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] event Requested event.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] event Requested event.
*
* @return Event address.
*/
__STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * const p_instance,
nrf_pwm_event_t event);
-
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrfx_pwm_step(nrfx_pwm_t const * const p_instance)
@@ -472,6 +451,8 @@ __STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * const p_i
#endif // SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
void nrfx_pwm_0_irq_handler(void);
void nrfx_pwm_1_irq_handler(void);
@@ -479,8 +460,6 @@ void nrfx_pwm_2_irq_handler(void);
void nrfx_pwm_3_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qdec.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qdec.h
index f1e5a85ef..a86fd6027 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qdec.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qdec.h
@@ -46,7 +46,7 @@ extern "C" {
* @brief Quadrature Decoder (QDEC) peripheral driver.
*/
-/**@brief QDEC configuration structure.*/
+/** @brief QDEC configuration structure. */
typedef struct
{
nrf_qdec_reportper_t reportper; /**< Report period in samples. */
@@ -62,91 +62,102 @@ typedef struct
} nrfx_qdec_config_t;
/**@brief QDEC default configuration. */
-#define NRFX_QDEC_DEFAULT_CONFIG \
- { \
- .reportper = (nrf_qdec_reportper_t)NRFX_QDEC_CONFIG_REPORTPER, \
- .sampleper = (nrf_qdec_sampleper_t)NRFX_QDEC_CONFIG_SAMPLEPER, \
- .psela = NRFX_QDEC_CONFIG_PIO_A, \
- .pselb = NRFX_QDEC_CONFIG_PIO_B, \
- .pselled = NRFX_QDEC_CONFIG_PIO_LED, \
- .ledpre = NRFX_QDEC_CONFIG_LEDPRE, \
- .ledpol = (nrf_qdec_ledpol_t)NRFX_QDEC_CONFIG_LEDPOL, \
- .interrupt_priority = NRFX_QDEC_CONFIG_IRQ_PRIORITY, \
- .dbfen = NRFX_QDEC_CONFIG_DBFEN, \
- .sample_inten = NRFX_QDEC_CONFIG_SAMPLE_INTEN \
- }
+#define NRFX_QDEC_DEFAULT_CONFIG \
+{ \
+ .reportper = (nrf_qdec_reportper_t)NRFX_QDEC_CONFIG_REPORTPER, \
+ .sampleper = (nrf_qdec_sampleper_t)NRFX_QDEC_CONFIG_SAMPLEPER, \
+ .psela = NRFX_QDEC_CONFIG_PIO_A, \
+ .pselb = NRFX_QDEC_CONFIG_PIO_B, \
+ .pselled = NRFX_QDEC_CONFIG_PIO_LED, \
+ .ledpre = NRFX_QDEC_CONFIG_LEDPRE, \
+ .ledpol = (nrf_qdec_ledpol_t)NRFX_QDEC_CONFIG_LEDPOL, \
+ .dbfen = NRFX_QDEC_CONFIG_DBFEN, \
+ .sample_inten = NRFX_QDEC_CONFIG_SAMPLE_INTEN, \
+ .interrupt_priority = NRFX_QDEC_CONFIG_IRQ_PRIORITY, \
+}
-/**@brief QDEC sample event data.*/
+/** @brief QDEC sample event data. */
typedef struct
{
int8_t value; /**< Sample value. */
} nrfx_qdec_sample_data_evt_t;
-/**@brief QDEC report event data.*/
+/** @brief QDEC report event data. */
typedef struct
{
int16_t acc; /**< Accumulated transitions. */
- uint16_t accdbl; /**< Accumulated double transitions. */
+ uint16_t accdbl; /**< Accumulated double transitions. */
} nrfx_qdec_report_data_evt_t;
-/**@brief QDEC event handler structure. */
+/** @brief QDEC event handler structure. */
typedef struct
{
- nrf_qdec_event_t type;
+ nrf_qdec_event_t type; /**< Event type. */
union
{
nrfx_qdec_sample_data_evt_t sample; /**< Sample event data. */
nrfx_qdec_report_data_evt_t report; /**< Report event data. */
- } data;
+ } data; /**< Union to store event data. */
} nrfx_qdec_event_t;
-/**@brief QDEC event handler.
- * @param[in] event QDEC event structure.
+/**
+ * @brief QDEC event handler.
+ *
+ * @param[in] event QDEC event structure.
*/
typedef void (*nrfx_qdec_event_handler_t)(nrfx_qdec_event_t event);
-/**@brief Function for initializing QDEC.
+/**
+ * @brief Function for initializing QDEC.
*
- * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] event_handler Event handler provided by the user.
* Must not be NULL.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If QDEC was already initialized.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The QDEC was already initialized.
*/
nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config,
nrfx_qdec_event_handler_t event_handler);
-/**@brief Function for uninitializing QDEC.
- * @note Function asserts if module is uninitialized.
+/**
+ * @brief Function for uninitializing QDEC.
+ *
+ * @note Function asserts if module is uninitialized.
*/
void nrfx_qdec_uninit(void);
-/**@brief Function for enabling QDEC.
- * @note Function asserts if module is uninitialized or enabled.
+/**
+ * @brief Function for enabling QDEC.
+ *
+ * @note Function asserts if module is uninitialized or enabled.
*/
void nrfx_qdec_enable(void);
-/**@brief Function for disabling QDEC.
- * @note Function asserts if module is uninitialized or disabled.
+/**
+ * @brief Function for disabling QDEC.
+ *
+ * @note Function asserts if module is uninitialized or disabled.
*/
void nrfx_qdec_disable(void);
-/**@brief Function for reading accumulated transitions QDEC.
- * @note Function asserts if module is not enabled.
- * @note Accumulators are cleared after reading.
+/**
+ * @brief Function for reading accumulated transitions from the QDEC peripheral.
*
- * @param[out] p_acc Pointer to store accumulated transitions.
- * @param[out] p_accdbl Pointer to store accumulated double transitions.
+ * @note Function asserts if module is not enabled.
+ * @note Accumulators are cleared after reading.
+ *
+ * @param[out] p_acc Pointer to store the accumulated transitions.
+ * @param[out] p_accdbl Pointer to store the accumulated double transitions.
*/
void nrfx_qdec_accumulators_read(int16_t * p_acc, int16_t * p_accdbl);
/**
- * @brief Function for returning the address of a specific QDEC task.
+ * @brief Function for returning the address of the specified QDEC task.
*
- * @param task QDEC task.
+ * @param task QDEC task.
*
- * @return Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrfx_qdec_task_address_get(nrf_qdec_task_t task)
{
@@ -154,21 +165,22 @@ __STATIC_INLINE uint32_t nrfx_qdec_task_address_get(nrf_qdec_task_t task)
}
/**
- * @brief Function for returning the address of a specific QDEC event.
+ * @brief Function for returning the address of the specified QDEC event.
*
- * @param event QDEC event.
+ * @param event QDEC event.
*
- * @return Event address.
+ * @return Event address.
*/
__STATIC_INLINE uint32_t nrfx_qdec_event_address_get(nrf_qdec_event_t event)
{
return (uint32_t)nrf_qdec_event_address_get(event);
}
+/** @} */
+
void nrfx_qdec_irq_handler(void);
-/** @} */
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qspi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qspi.h
index 36bb579ce..e181cbffd 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qspi.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_qspi.h
@@ -46,21 +46,17 @@ extern "C" {
* @brief Quad Serial Peripheral Interface (QSPI) peripheral driver.
*/
-/**
- * @brief QSPI driver instance configuration structure.
- */
+/** @brief QSPI driver instance configuration structure. */
typedef struct
{
uint32_t xip_offset; /**< Address offset into the external memory for Execute in Place operation. */
- nrf_qspi_pins_t pins; /**< Pins configuration structure. */
+ nrf_qspi_pins_t pins; /**< Pin configuration structure. */
nrf_qspi_prot_conf_t prot_if; /**< Protocol layer interface configuration structure. */
nrf_qspi_phy_conf_t phy_if; /**< Physical layer interface configuration structure. */
uint8_t irq_priority; /**< Interrupt priority. */
} nrfx_qspi_config_t;
-/**
- * @brief QSPI instance default configuration.
- */
+/** @brief QSPI instance default configuration. */
#define NRFX_QSPI_DEFAULT_CONFIG \
{ \
.xip_offset = NRFX_QSPI_CONFIG_XIP_OFFSET, \
@@ -72,7 +68,6 @@ typedef struct
.io2_pin = NRFX_QSPI_PIN_IO2, \
.io3_pin = NRFX_QSPI_PIN_IO3, \
}, \
- .irq_priority = (uint8_t)NRFX_QSPI_CONFIG_IRQ_PRIORITY, \
.prot_if = { \
.readoc = (nrf_qspi_readoc_t)NRFX_QSPI_CONFIG_READOC, \
.writeoc = (nrf_qspi_writeoc_t)NRFX_QSPI_CONFIG_WRITEOC, \
@@ -80,16 +75,15 @@ typedef struct
.dpmconfig = false, \
}, \
.phy_if = { \
- .sck_freq = (nrf_qspi_frequency_t)NRFX_QSPI_CONFIG_FREQUENCY, \
.sck_delay = (uint8_t)NRFX_QSPI_CONFIG_SCK_DELAY, \
+ .dpmen = false, \
.spi_mode = (nrf_qspi_spi_mode_t)NRFX_QSPI_CONFIG_MODE, \
- .dpmen = false \
+ .sck_freq = (nrf_qspi_frequency_t)NRFX_QSPI_CONFIG_FREQUENCY, \
}, \
+ .irq_priority = (uint8_t)NRFX_QSPI_CONFIG_IRQ_PRIORITY, \
}
-/**
- * @brief QSPI custom instruction helper with default configuration.
- */
+/** @brief QSPI custom instruction helper with the default configuration. */
#define NRFX_QSPI_DEFAULT_CINSTR(opc, len) \
{ \
.opcode = (opc), \
@@ -109,16 +103,14 @@ typedef enum
NRFX_QSPI_EVENT_DONE, /**< Transfer done. */
} nrfx_qspi_evt_t;
-/**
- * @brief QSPI driver event handler type.
- */
+/** @brief QSPI driver event handler type. */
typedef void (*nrfx_qspi_handler_t)(nrfx_qspi_evt_t event, void * p_context);
/**
* @brief Function for initializing the QSPI driver instance.
*
- * This function configures the peripheral and its interrupts and activates it. During the
- * activation process, the internal clocks are started and the QSPI peripheral tries to read
+ * This function configures the peripheral and its interrupts, and activates it. During the
+ * activation process, the internal clocks are started and the QSPI peripheral tries to read
* the status byte to read the busy bit. Reading the status byte is done in a simple poll and wait
* mechanism.
* If the busy bit is 1, this indicates issues with the external memory device. As a result,
@@ -129,32 +121,30 @@ typedef void (*nrfx_qspi_handler_t)(nrfx_qspi_evt_t event, void * p_context);
* - Make sure that the memory device does not perform other operations like erasing or writing.
* - Check if there is a short circuit.
*
- * @param[in] p_config Pointer to the structure with initial configuration.
- * @param[in] handler Event handler provided by the user. If NULL, transfers
- * will be performed in blocking mode.
- * @param[in] p_context Pointer to context. Use in interrupt handler.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ * @param[in] handler Event handler provided by the user. If NULL, transfers
+ * will be performed in blocking mode.
+ * @param[in] p_context Pointer to context. Use in the interrupt handler.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_TIMEOUT If the peripheral cannot connect with external memory.
- * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized.
- * @retval NRFX_ERROR_INVALID_PARAM If the pin configuration was incorrect.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_TIMEOUT The peripheral cannot connect with external memory.
+ * @retval NRFX_ERROR_INVALID_STATE The driver was already initialized.
+ * @retval NRFX_ERROR_INVALID_PARAM The pin configuration was incorrect.
*/
nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config,
nrfx_qspi_handler_t handler,
void * p_context);
-/**
- * @brief Function for uninitializing the QSPI driver instance.
- */
+/** @brief Function for uninitializing the QSPI driver instance. */
void nrfx_qspi_uninit(void);
/**
- * @brief Function for reading data from QSPI memory.
+ * @brief Function for reading data from the QSPI memory.
*
* Write, read, and erase operations check memory device busy state before starting the operation.
* If the memory is busy, the resulting action depends on the mode in which the read operation is used:
- * - blocking mode (without handler) - a delay occurs until the last operation still runs and
- * until operation data is still being read.
+ * - blocking mode (without handler) - a delay occurs until the last operation runs and
+ * until the operation data is being read.
* - interrupt mode (with handler) - event emission occurs after the last operation
* and reading of data are finished.
*
@@ -162,10 +152,11 @@ void nrfx_qspi_uninit(void);
* @param[in] rx_buffer_length Size of the data to read.
* @param[in] src_address Address in memory to read from.
*
- * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation
+ * @retval NRFX_SUCCESS The operation was successful (blocking mode) or operation
* was commissioned (handler mode).
- * @retval NRFX_ERROR_BUSY If the driver currently handles another operation.
- * @retval NRFX_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region.
+ * @retval NRFX_ERROR_BUSY The driver currently handles another operation.
+ * @retval NRFX_ERROR_INVALID_ADDR The provided buffer is not placed in the Data RAM region
+ * or its address is not aligned to a 32-bit word.
*/
nrfx_err_t nrfx_qspi_read(void * p_rx_buffer,
size_t rx_buffer_length,
@@ -176,8 +167,8 @@ nrfx_err_t nrfx_qspi_read(void * p_rx_buffer,
*
* Write, read, and erase operations check memory device busy state before starting the operation.
* If the memory is busy, the resulting action depends on the mode in which the write operation is used:
- * - blocking mode (without handler) - a delay occurs until the last operation still runs and
- * until operation data is still being sent.
+ * - blocking mode (without handler) - a delay occurs until the last operation runs or
+ * until the operation data is being sent.
* - interrupt mode (with handler) - event emission occurs after the last operation
* and sending of operation data are finished.
* To manually control operation execution in the memory device, use @ref nrfx_qspi_mem_busy_check
@@ -189,10 +180,11 @@ nrfx_err_t nrfx_qspi_read(void * p_rx_buffer,
* @param[in] tx_buffer_length Size of the data to write.
* @param[in] dst_address Address in memory to write to.
*
- * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation
+ * @retval NRFX_SUCCESS The operation was successful (blocking mode) or operation
* was commissioned (handler mode).
- * @retval NRFX_ERROR_BUSY If the driver currently handles other operation.
- * @retval NRFX_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region.
+ * @retval NRFX_ERROR_BUSY The driver currently handles other operation.
+ * @retval NRFX_ERROR_INVALID_ADDR The provided buffer is not placed in the Data RAM region
+ * or its address is not aligned to a 32-bit word.
*/
nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer,
size_t tx_buffer_length,
@@ -203,8 +195,8 @@ nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer,
*
* Write, read, and erase operations check memory device busy state before starting the operation.
* If the memory is busy, the resulting action depends on the mode in which the erase operation is used:
- * - blocking mode (without handler) - a delay occurs until the last operation still runs and
- * until operation data is still being sent.
+ * - blocking mode (without handler) - a delay occurs until the last operation runs or
+ * until the operation data is being sent.
* - interrupt mode (with handler) - event emission occurs after the last operation
* and sending of operation data are finished.
* To manually control operation execution in the memory device, use @ref nrfx_qspi_mem_busy_check
@@ -216,9 +208,10 @@ nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer,
* @param[in] start_address Memory address to start erasing. If chip erase is performed, address
* field is ommited.
*
- * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation
- * was commissioned (handler mode).
- * @retval NRFX_ERROR_BUSY If the driver currently handles another operation.
+ * @retval NRFX_SUCCESS The operation was successful (blocking mode) or operation
+ * was commissioned (handler mode).
+ * @retval NRFX_ERROR_INVALID_ADDR The provided start address is not aligned to a 32-bit word.
+ * @retval NRFX_ERROR_BUSY The driver currently handles another operation.
*/
nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length,
uint32_t start_address);
@@ -226,9 +219,9 @@ nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length,
/**
* @brief Function for starting an erase operation of the whole chip.
*
- * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation
+ * @retval NRFX_SUCCESS The operation was successful (blocking mode) or operation
* was commissioned (handler mode).
- * @retval NRFX_ERROR_BUSY If the driver currently handles another operation.
+ * @retval NRFX_ERROR_BUSY The driver currently handles another operation.
*/
nrfx_err_t nrfx_qspi_chip_erase(void);
@@ -236,8 +229,8 @@ nrfx_err_t nrfx_qspi_chip_erase(void);
* @brief Function for getting the current driver status and status byte of memory device with
* testing WIP (write in progress) bit.
*
- * @retval NRFX_SUCCESS If the driver and memory are ready to handle a new operation.
- * @retval NRFX_ERROR_BUSY If the driver or memory currently handle another operation.
+ * @retval NRFX_SUCCESS The driver and memory are ready to handle a new operation.
+ * @retval NRFX_ERROR_BUSY The driver or memory currently handle another operation.
*/
nrfx_err_t nrfx_qspi_mem_busy_check(void);
@@ -252,13 +245,14 @@ nrfx_err_t nrfx_qspi_mem_busy_check(void);
* @param[in] p_tx_buffer Pointer to the array with data to send. Can be NULL if only opcode is transmitted.
* @param[out] p_rx_buffer Pointer to the array for data to receive. Can be NULL if there is nothing to receive.
*
- * @retval NRFX_SUCCESS If the operation was successful.
- * @retval NRFX_ERROR_TIMEOUT If the external memory is busy or there are connection issues.
- * @retval NRFX_ERROR_BUSY If the driver currently handles other operation.
+ * @retval NRFX_SUCCESS The operation was successful.
+ * @retval NRFX_ERROR_TIMEOUT The external memory is busy or there are connection issues.
+ * @retval NRFX_ERROR_BUSY The driver currently handles other operation.
*/
nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config,
void const * p_tx_buffer,
void * p_rx_buffer);
+
/**
* @brief Function for sending operation code and data to the memory device with simpler configuration.
*
@@ -269,17 +263,56 @@ nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config,
* @param[in] length Length of the data to send and opcode. See @ref nrf_qspi_cinstr_len_t.
* @param[in] p_tx_buffer Pointer to input data array.
*
- * @retval NRFX_SUCCESS If the operation was successful.
- * @retval NRFX_ERROR_BUSY If the driver currently handles another operation.
+ * @retval NRFX_SUCCESS The operation was successful.
+ * @retval NRFX_ERROR_BUSY The driver currently handles another operation.
*/
nrfx_err_t nrfx_qspi_cinstr_quick_send(uint8_t opcode,
nrf_qspi_cinstr_len_t length,
void const * p_tx_buffer);
+/**
+ * @brief Function for starting the custom instruction long frame mode.
+ *
+ * The long frame mode is a mechanism that allows for arbitrary byte length custom instructions.
+ * Use this function to initiate a custom transaction by sending custom instruction opcode.
+ * To send and receive data, use @ref nrfx_qspi_lfm_xfer.
+ *
+ * @param[in] p_config Pointer to the structure with custom instruction opcode and transfer
+ * configuration. Transfer length must be set to @ref NRF_QSPI_CINSTR_LEN_1B.
+ *
+ * @retval NRFX_SUCCESS Operation was successful.
+ * @retval NRFX_ERROR_BUSY Driver currently handles other operation.
+ * @retval NRFX_ERROR_TIMEOUT External memory is busy or there are connection issues.
+ */
+nrfx_err_t nrfx_qspi_lfm_start(nrf_qspi_cinstr_conf_t const * p_config);
+
+/**
+ * @brief Function for sending and receiving data in the custom instruction long frame mode.
+ *
+ * Both specified buffers must be at least @p transfer_length bytes in size.
+ *
+ * @param[in] p_tx_buffer Pointer to the array with data to send.
+ * Can be NULL if there is nothing to send.
+ * @param[out] p_rx_buffer Pointer to the array for receiving data.
+ * Can be NULL if there is nothing to receive.
+ * @param[in] transfer_length Number of bytes to send and receive.
+ * @param[in] finalize True if custom instruction long frame mode is to be finalized
+ * after this transfer.
+ *
+ * @retval NRFX_SUCCESS Operation was successful.
+ * @retval NRFX_ERROR_TIMEOUT External memory is busy or there are connection issues.
+ * Long frame mode becomes deactivated.
+ */
+nrfx_err_t nrfx_qspi_lfm_xfer(void const * p_tx_buffer,
+ void * p_rx_buffer,
+ size_t transfer_length,
+ bool finalize);
+
+/** @} */
+
void nrfx_qspi_irq_handler(void);
-/** @} */
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rng.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rng.h
index 6add7f73a..11968f393 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rng.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rng.h
@@ -45,13 +45,11 @@ extern "C" {
* @brief Random Number Generator (RNG) peripheral driver.
*/
-/**
- * @brief Struct for RNG configuration.
- */
+/** @brief Struct for RNG configuration. */
typedef struct
{
bool error_correction : 1; /**< Error correction flag. */
- uint8_t interrupt_priority; /**< interrupt priority */
+ uint8_t interrupt_priority; /**< Interrupt priority. */
} nrfx_rng_config_t;
/**
@@ -63,53 +61,49 @@ typedef struct
* { ...
* @endcode
*/
-#define NRFX_RNG_DEFAULT_CONFIG \
- { \
- .error_correction = NRFX_RNG_CONFIG_ERROR_CORRECTION, \
- .interrupt_priority = NRFX_RNG_CONFIG_IRQ_PRIORITY, \
- }
+#define NRFX_RNG_DEFAULT_CONFIG \
+{ \
+ .error_correction = NRFX_RNG_CONFIG_ERROR_CORRECTION, \
+ .interrupt_priority = NRFX_RNG_CONFIG_IRQ_PRIORITY, \
+}
-/**
- * @brief RNG driver event handler type.
- */
+/** @brief RNG driver event handler type. */
typedef void (* nrfx_rng_evt_handler_t)(uint8_t rng_data);
/**
* @brief Function for initializing the nrfx_rng module.
*
- * @param[in] p_config Pointer to the structure with initial configuration.
- * @param[in] handler Event handler provided by the user. Must not be NULL.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ * @param[in] handler Event handler provided by the user. Must not be NULL.
*
- * @retval NRFX_SUCCESS Driver was successfully initialized.
- * @retval NRFX_ERROR_ALREADY_INITIALIZED Driver was already initialized.
+ * @retval NRFX_SUCCESS Driver was successfully initialized.
+ * @retval NRFX_ERROR_ALREADY_INITIALIZED Driver was already initialized.
*/
nrfx_err_t nrfx_rng_init(nrfx_rng_config_t const * p_config, nrfx_rng_evt_handler_t handler);
/**
- * @brief Function for starting the random value generation.
+ * @brief Function for starting the generation of random values.
*
- * Function enables interrupts in perihperal and start them.
+ * New data should be handled by handler passed to the @ref nrfx_rng_init() function.
*/
void nrfx_rng_start(void);
/**
- * @brief Function for stoping the random value generation.
+ * @brief Function for stopping the generation of random values.
*
- * Function disables interrupts in perihperal and stop generation of new random values.
+ * Function disables interrupts in peripheral and stops the generation of new random values.
*/
void nrfx_rng_stop(void);
-/**
- * @brief Function for uninitializing the nrfx_rng module.
- */
+/** @brief Function for uninitializing the nrfx_rng module. */
void nrfx_rng_uninit(void);
+/** @} */
+
void nrfx_rng_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rtc.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rtc.h
index e41713b02..5cc5d81c0 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rtc.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_rtc.h
@@ -46,10 +46,10 @@ extern "C" {
* @brief Real Timer Counter (RTC) peripheral driver.
*/
-/**@brief Macro to convert microseconds into ticks. */
+/** @brief Macro for converting microseconds into ticks. */
#define NRFX_RTC_US_TO_TICKS(us,freq) (((us) * (freq)) / 1000000U)
-/**@brief RTC driver interrupt types. */
+/** @brief RTC driver interrupt types. */
typedef enum
{
NRFX_RTC_INT_COMPARE0 = 0, /**< Interrupt from COMPARE0 event. */
@@ -60,16 +60,16 @@ typedef enum
NRFX_RTC_INT_OVERFLOW = 5 /**< Interrupt from OVERFLOW event. */
} nrfx_rtc_int_type_t;
-/**@brief RTC driver instance structure. */
+/** @brief RTC driver instance structure. */
typedef struct
{
NRF_RTC_Type * p_reg; /**< Pointer to instance register set. */
IRQn_Type irq; /**< Instance IRQ ID. */
- uint8_t instance_id; /**< Instance index. */
+ uint8_t instance_id; /**< Index of the driver instance. For internal use only. */
uint8_t cc_channel_count; /**< Number of capture/compare channels. */
} nrfx_rtc_t;
-/**@brief Macro for creating RTC driver instance.*/
+/** @brief Macro for creating an RTC driver instance. */
#define NRFX_RTC_INSTANCE(id) \
{ \
.p_reg = NRFX_CONCAT_2(NRF_RTC, id), \
@@ -78,6 +78,7 @@ typedef struct
.cc_channel_count = NRF_RTC_CC_CHANNEL_COUNT(id), \
}
+#ifndef __NRFX_DOXYGEN__
enum {
#if NRFX_CHECK(NRFX_RTC0_ENABLED)
NRFX_RTC0_INST_IDX,
@@ -90,215 +91,223 @@ enum {
#endif
NRFX_RTC_ENABLED_COUNT
};
+#endif
-/**@brief RTC driver instance configuration structure. */
+/** @brief RTC driver instance configuration structure. */
typedef struct
{
uint16_t prescaler; /**< Prescaler. */
uint8_t interrupt_priority; /**< Interrupt priority. */
- uint8_t tick_latency; /**< Maximum length of interrupt handler in ticks (max 7.7 ms). */
+ uint8_t tick_latency; /**< Maximum length of the interrupt handler in ticks (maximum 7.7 ms). */
bool reliable; /**< Reliable mode flag. */
} nrfx_rtc_config_t;
-/**@brief RTC instance default configuration. */
+/** @brief RTC instance default configuration. */
#define NRFX_RTC_DEFAULT_CONFIG \
{ \
.prescaler = RTC_FREQ_TO_PRESCALER(NRFX_RTC_DEFAULT_CONFIG_FREQUENCY), \
.interrupt_priority = NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY, \
- .reliable = NRFX_RTC_DEFAULT_CONFIG_RELIABLE, \
.tick_latency = NRFX_RTC_US_TO_TICKS(NRFX_RTC_MAXIMUM_LATENCY_US, \
NRFX_RTC_DEFAULT_CONFIG_FREQUENCY), \
+ .reliable = NRFX_RTC_DEFAULT_CONFIG_RELIABLE, \
}
-/**@brief RTC driver instance handler type. */
+/** @brief RTC driver instance handler type. */
typedef void (*nrfx_rtc_handler_t)(nrfx_rtc_int_type_t int_type);
-/**@brief Function for initializing the RTC driver instance.
+/**
+ * @brief Function for initializing the RTC driver instance.
*
* After initialization, the instance is in power off state.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_config Pointer to the structure with initial configuration.
- * @param[in] handler Event handler provided by the user.
- * Must not be NULL.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ * @param[in] handler Event handler provided by the user.
+ * Must not be NULL.
*
- * @retval NRFX_SUCCESS If successfully initialized.
- * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized.
+ * @retval NRFX_SUCCESS Successfully initialized.
+ * @retval NRFX_ERROR_INVALID_STATE The instance is already initialized.
*/
nrfx_err_t nrfx_rtc_init(nrfx_rtc_t const * const p_instance,
nrfx_rtc_config_t const * p_config,
nrfx_rtc_handler_t handler);
-/**@brief Function for uninitializing the RTC driver instance.
+/**
+ * @brief Function for uninitializing the RTC driver instance.
*
* After uninitialization, the instance is in idle state. The hardware should return to the state
- * before initialization. The function asserts if the instance is in idle state.
+ * before initialization.
*
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_rtc_uninit(nrfx_rtc_t const * const p_instance);
-/**@brief Function for enabling the RTC driver instance.
+/**
+ * @brief Function for enabling the RTC driver instance.
*
- * @note Function asserts if instance is enabled.
- *
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_rtc_enable(nrfx_rtc_t const * const p_instance);
-/**@brief Function for disabling the RTC driver instance.
+/**
+ * @brief Function for disabling the RTC driver instance.
*
- * @note Function asserts if instance is disabled.
- *
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_rtc_disable(nrfx_rtc_t const * const p_instance);
-/**@brief Function for setting a compare channel.
+/**
+ * @brief Function for setting a compare channel.
*
- * The function asserts if the instance is not initialized or if the channel parameter is
- * wrong. The function powers on the instance if the instance was in power off state.
+ * The function powers on the instance if the instance was in power off state.
*
* The driver is not entering a critical section when configuring RTC, which means that it can be
- * preempted for a certain amount of time. When the driver was preempted and the value to be set
- * is short in time, there is a risk that the driver sets a compare value that is
- * behind. If RTCn_CONFIG_RELIABLE is 1 for the given instance, the Reliable mode handles that case.
- * However, to detect if the requested value is behind, this mode makes the following assumptions:
- * - The maximum preemption time in ticks (8 - bit value) is known and is less than 7.7 ms
- * (for prescaler = 0, RTC frequency 32 kHz).
- * - The requested absolute compare value is not bigger than (0x00FFFFFF) - tick_latency. It is
- * the user's responsibility to ensure that.
+ * preempted for a certain amount of time. When the driver was preempted and the value to be set
+ * is short in time, there is a risk that the driver sets a compare value that is
+ * behind. In this case, if the reliable mode is enabled for the specified instance,
+ * the risk is handled.
+ * However, to detect if the requested value is behind, this mode makes the following assumptions:
+ * - The maximum preemption time in ticks (8-bit value) is known and is less than 7.7 ms
+ * (for prescaler = 0, RTC frequency 32 kHz).
+ * - The requested absolute compare value is not bigger than (0x00FFFFFF)-tick_latency. It is
+ * the user's responsibility to ensure this.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] channel One of the instance's channels.
- * @param[in] val Absolute value to be set in the compare register.
- * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] channel One of the channels of the instance.
+ * @param[in] val Absolute value to be set in the compare register.
+ * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt.
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_TIMEOUT If the compare was not set because the request value is behind the current counter
- * value. This error can only be reported if RTCn_CONFIG_RELIABLE = 1.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_TIMEOUT The compare is not set because the request value is behind the
+ * current counter value. This error can only be reported
+ * if the reliable mode is enabled.
*/
nrfx_err_t nrfx_rtc_cc_set(nrfx_rtc_t const * const p_instance,
uint32_t channel,
uint32_t val,
bool enable_irq);
-/**@brief Function for disabling a channel.
+/**
+ * @brief Function for disabling a channel.
*
- * This function disables channel events and channel interrupts. The function asserts if the instance is not
- * initialized or if the channel parameter is wrong.
+ * This function disables channel events and channel interrupts.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] channel One of the instance's channels.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] channel One of the channels of the instance.
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_TIMEOUT If an interrupt was pending on the requested channel.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_TIMEOUT Interrupt is pending on the requested channel.
*/
nrfx_err_t nrfx_rtc_cc_disable(nrfx_rtc_t const * const p_instance, uint32_t channel);
-/**@brief Function for enabling tick.
+/**
+ * @brief Function for enabling the TICK event.
*
- * This function enables the tick event and optionally the interrupt. The function asserts if the instance is not
- * powered on.
+ * This function enables the tick event and optionally the interrupt.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt.
*/
void nrfx_rtc_tick_enable(nrfx_rtc_t const * const p_instance, bool enable_irq);
-/**@brief Function for disabling tick.
+/**
+ * @brief Function for disabling the TICK event.
*
- * This function disables the tick event and interrupt.
+ * This function disables the TICK event and interrupt.
*
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_rtc_tick_disable(nrfx_rtc_t const * const p_instance);
-/**@brief Function for enabling overflow.
+/**
+ * @brief Function for enabling overflow.
*
- * This function enables the overflow event and optionally the interrupt. The function asserts if the instance is
- * not powered on.
+ * This function enables the overflow event and optionally the interrupt.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt.
*/
void nrfx_rtc_overflow_enable(nrfx_rtc_t const * const p_instance, bool enable_irq);
-/**@brief Function for disabling overflow.
+/**
+ * @brief Function for disabling overflow.
*
* This function disables the overflow event and interrupt.
*
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_rtc_overflow_disable(nrfx_rtc_t const * const p_instance);
-/**@brief Function for getting the maximum relative ticks value that can be set in the compare channel.
+/**
+ * @brief Function for getting the maximum relative tick value that can be set in the compare channel.
*
* When a stack (for example SoftDevice) is used and it occupies high priority interrupts,
* the application code can be interrupted at any moment for a certain period of time.
- * If Reliable mode is enabled, the provided maximum latency is taken into account
+ * If the reliable mode is enabled, the provided maximum latency is taken into account
* and the return value is smaller than the RTC counter resolution.
- * If Reliable mode is disabled, the return value equals the counter resolution.
+ * If the reliable mode is disabled, the return value equals the counter resolution.
*
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval ticks Maximum ticks value.
+ * @return Maximum ticks value.
*/
uint32_t nrfx_rtc_max_ticks_get(nrfx_rtc_t const * const p_instance);
-/**@brief Function for disabling all instance interrupts.
+/**
+ * @brief Function for disabling all instance interrupts.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_mask Pointer to the location where the mask is filled.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_mask Pointer to the location where the mask is filled.
*/
__STATIC_INLINE void nrfx_rtc_int_disable(nrfx_rtc_t const * const p_instance,
uint32_t * p_mask);
-/**@brief Function for enabling instance interrupts.
+/**
+ * @brief Function for enabling instance interrupts.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] mask Mask of interrupts to enable.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] mask Mask of interrupts to enable.
*/
__STATIC_INLINE void nrfx_rtc_int_enable(nrfx_rtc_t const * const p_instance, uint32_t mask);
-/**@brief Function for retrieving the current counter value.
+/**
+ * @brief Function for retrieving the current counter value.
*
- * This function asserts if the instance is not powered on or if p_val is NULL.
+ * @param[in] p_instance Pointer to the driver instance structure.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- *
- * @retval value Counter value.
+ * @return Counter value.
*/
__STATIC_INLINE uint32_t nrfx_rtc_counter_get(nrfx_rtc_t const * const p_instance);
-/**@brief Function for clearing the counter value.
+/**
+ * @brief Function for clearing the counter value.
*
- * This function asserts if the instance is not powered on.
- *
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*/
__STATIC_INLINE void nrfx_rtc_counter_clear(nrfx_rtc_t const * const p_instance);
-/**@brief Function for returning a requested task address for the RTC driver instance.
+/**
+ * @brief Function for returning a requested task address for the RTC driver instance.
*
- * This function asserts if the output pointer is NULL. The task address can be used by the PPI module.
+ * The task address can be used by the PPI module.
*
- * @param[in] p_instance Pointer to the instance.
- * @param[in] task One of the peripheral tasks.
+ * @param[in] p_instance Pointer to the instance.
+ * @param[in] task One of the peripheral tasks.
*
- * @retval Address of task register.
+ * @return Address of task register.
*/
__STATIC_INLINE uint32_t nrfx_rtc_task_address_get(nrfx_rtc_t const * const p_instance,
nrf_rtc_task_t task);
-/**@brief Function for returning a requested event address for the RTC driver instance.
+/**
+ * @brief Function for returning a requested event address for the RTC driver instance.
*
- * This function asserts if the output pointer is NULL. The event address can be used by the PPI module.
+ * The event address can be used by the PPI module.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] event One of the peripheral events.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] event One of the peripheral events.
*
- * @retval Address of event register.
+ * @return Address of event register.
*/
__STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * const p_instance,
nrf_rtc_event_t event);
@@ -345,14 +354,14 @@ __STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * const p_i
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
void nrfx_rtc_0_irq_handler(void);
void nrfx_rtc_1_irq_handler(void);
void nrfx_rtc_2_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_saadc.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_saadc.h
index 08135261b..addb97423 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_saadc.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_saadc.h
@@ -46,18 +46,12 @@ extern "C" {
* @brief Successive Approximation Analog-to-Digital Converter (SAADC) peripheral driver.
*/
-/**
- * @brief Value that should be set as high limit to disable limit detection.
- */
+/** @brief Value to be set as high limit to disable limit detection. */
#define NRFX_SAADC_LIMITH_DISABLED (2047)
-/**
- * @brief Value that should be set as low limit to disable limit detection.
- */
+/** @brief Value to be set as low limit to disable limit detection. */
#define NRFX_SAADC_LIMITL_DISABLED (-2048)
-/**
- * @brief Macro for setting @ref nrfx_saadc_config_t to default settings.
- */
+/** @brief Macro for setting @ref nrfx_saadc_config_t to default settings. */
#define NRFX_SAADC_DEFAULT_CONFIG \
{ \
.resolution = (nrf_saadc_resolution_t)NRFX_SAADC_CONFIG_RESOLUTION, \
@@ -68,7 +62,7 @@ extern "C" {
/**
* @brief Macro for setting @ref nrf_saadc_channel_config_t to default settings
- * in single ended mode.
+ * in single-ended mode.
*
* @param PIN_P Analog input.
*/
@@ -100,13 +94,12 @@ extern "C" {
.reference = NRF_SAADC_REFERENCE_INTERNAL, \
.acq_time = NRF_SAADC_ACQTIME_10US, \
.mode = NRF_SAADC_MODE_DIFFERENTIAL, \
+ .burst = NRF_SAADC_BURST_DISABLED, \
.pin_p = (nrf_saadc_input_t)(PIN_P), \
.pin_n = (nrf_saadc_input_t)(PIN_N) \
}
-/**
- * @brief Analog-to-digital converter driver configuration structure.
- */
+/** @brief SAADC driver configuration structure. */
typedef struct
{
nrf_saadc_resolution_t resolution; ///< Resolution configuration.
@@ -115,9 +108,7 @@ typedef struct
bool low_power_mode; ///< Indicates if low power mode is active.
} nrfx_saadc_config_t;
-/**
- * @brief Driver event types.
- */
+/** @brief SAADC driver event types. */
typedef enum
{
NRFX_SAADC_EVT_DONE, ///< Event generated when the buffer is filled with samples.
@@ -125,27 +116,21 @@ typedef enum
NRFX_SAADC_EVT_CALIBRATEDONE ///< Event generated when the calibration is complete.
} nrfx_saadc_evt_type_t;
-/**
- * @brief Analog-to-digital converter driver done event data.
- */
+/** @brief SAADC driver done event data. */
typedef struct
{
nrf_saadc_value_t * p_buffer; ///< Pointer to buffer with converted samples.
uint16_t size; ///< Number of samples in the buffer.
} nrfx_saadc_done_evt_t;
-/**
- * @brief Analog-to-digital converter driver limit event data.
- */
+/** @brief SAADC driver limit event data. */
typedef struct
{
uint8_t channel; ///< Channel on which the limit was detected.
nrf_saadc_limit_t limit_type; ///< Type of limit detected.
} nrfx_saadc_limit_evt_t;
-/**
- * @brief Analog-to-digital converter driver event structure.
- */
+/** @brief SAADC driver event structure. */
typedef struct
{
nrfx_saadc_evt_type_t type; ///< Event type.
@@ -153,15 +138,14 @@ typedef struct
{
nrfx_saadc_done_evt_t done; ///< Data for @ref NRFX_SAADC_EVT_DONE event.
nrfx_saadc_limit_evt_t limit; ///< Data for @ref NRFX_SAADC_EVT_LIMIT event.
- } data;
+ } data; ///< Union to store event data.
} nrfx_saadc_evt_t;
/**
- * @brief ADC event handler.
+ * @brief SAADC driver event handler.
*
- * @param[in] p_event Pointer to an ADC event. The event structure is allocated on
- * the stack, so it is valid only within the context of
- * the event handler.
+ * @param[in] p_event Pointer to an SAADC driver event. The event structure is allocated on
+ * the stack, so it is valid only within the context of the event handler.
*/
typedef void (* nrfx_saadc_event_handler_t)(nrfx_saadc_evt_t const * p_event);
@@ -172,8 +156,8 @@ typedef void (* nrfx_saadc_event_handler_t)(nrfx_saadc_evt_t const * p_event);
* @param[in] event_handler Event handler provided by the user.
* Must not be NULL.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver is already initialized.
*/
nrfx_err_t nrfx_saadc_init(nrfx_saadc_config_t const * p_config,
nrfx_saadc_event_handler_t event_handler);
@@ -189,7 +173,7 @@ void nrfx_saadc_uninit(void);
/**
* @brief Function for getting the address of a SAMPLE SAADC task.
*
- * @return Task address.
+ * @return Task address.
*/
uint32_t nrfx_saadc_sample_task_get(void);
@@ -198,43 +182,47 @@ uint32_t nrfx_saadc_sample_task_get(void);
*
* This function configures and enables the channel.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the ADC was not initialized.
- * @retval NRFX_ERROR_NO_MEM If the specified channel was already allocated.
+ * @param[in] channel Channel index.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ *
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The SAADC was not initialized.
+ * @retval NRFX_ERROR_NO_MEM The specified channel was already allocated.
*/
nrfx_err_t nrfx_saadc_channel_init(uint8_t channel,
nrf_saadc_channel_config_t const * const p_config);
-
/**
* @brief Function for uninitializing an SAADC channel.
*
- * @retval NRFX_SUCCESS If uninitialization was successful.
- * @retval NRFX_ERROR_BUSY If the ADC is busy.
+ * @param[in] channel Channel index.
+ *
+ * @retval NRFX_SUCCESS Uninitialization was successful.
+ * @retval NRFX_ERROR_BUSY The SAADC is busy.
*/
nrfx_err_t nrfx_saadc_channel_uninit(uint8_t channel);
/**
- * @brief Function for starting SAADC sampling.
+ * @brief Function for starting the SAADC sampling.
*
- * @retval NRFX_SUCCESS If ADC sampling was triggered.
- * @retval NRFX_ERROR_INVALID_STATE If ADC is in idle state.
+ * @retval NRFX_SUCCESS The SAADC sampling was triggered.
+ * @retval NRFX_ERROR_INVALID_STATE The SAADC is in idle state.
*/
nrfx_err_t nrfx_saadc_sample(void);
/**
- * @brief Blocking function for executing a single ADC conversion.
+ * @brief Blocking function for executing a single SAADC conversion.
*
* This function selects the desired input, starts a single conversion,
* waits for it to finish, and returns the result.
*
- * The function will fail if ADC is busy.
+ * The function fails if the SAADC is busy.
*
* @param[in] channel Channel.
- * @param[out] p_value Pointer to the location where the result should be placed.
+ * @param[out] p_value Pointer to the location where the result is to be placed.
*
- * @retval NRFX_SUCCESS If conversion was successful.
- * @retval NRFX_ERROR_BUSY If the ADC driver is busy.
+ * @retval NRFX_SUCCESS The conversion was successful.
+ * @retval NRFX_ERROR_BUSY The SAADC driver is busy.
*/
nrfx_err_t nrfx_saadc_sample_convert(uint8_t channel, nrf_saadc_value_t * p_value);
@@ -242,45 +230,47 @@ nrfx_err_t nrfx_saadc_sample_convert(uint8_t channel, nrf_saadc_value_t * p_valu
* @brief Function for issuing conversion of data to the buffer.
*
* This function is non-blocking. The application is notified about filling the buffer by the event
- * handler. Conversion will be done on all enabled channels. If the ADC is in idle state, the
- * function will set up Easy DMA for the conversion. The ADC will be ready for sampling and wait for
- * the SAMPLE task. It can be triggered manually by the @ref nrfx_saadc_sample function or by PPI
- * using the @ref NRF_SAADC_TASK_SAMPLE task. If one buffer is already set and the conversion is
- * ongoing, calling this function will result in queuing the given buffer. The driver will start
- * filling the issued buffer when the first one is completed. If the function is called again before
- * the first buffer is filled or calibration is in progress, it will return with error.
+ * handler. Conversion will be done on all enabled channels. If the SAADC is in idle state, the
+ * function will set up EasyDMA for the conversion. The SAADC will be ready for sampling and wait
+ * for the SAMPLE task. It can be triggered manually by the @ref nrfx_saadc_sample function
+ * or by PPI using the @ref NRF_SAADC_TASK_SAMPLE task. If one buffer is already set and the
+ * conversion is ongoing, calling this function will result in queuing the given buffer.
+ * The driver will start filling the issued buffer when the first one is completed.
+ * If the function is called again before the first buffer is filled or calibration
+ * is in progress, it will return with error.
*
* @param[in] buffer Result buffer.
* @param[in] size Buffer size in words.
*
- * @retval NRFX_SUCCESS If conversion was successful.
- * @retval NRFX_ERROR_BUSY If the driver already has two buffers set or calibration is in progress.
+ * @retval NRFX_SUCCESS The conversion was successful.
+ * @retval NRFX_ERROR_BUSY The driver already has two buffers set or the calibration is in progress.
*/
nrfx_err_t nrfx_saadc_buffer_convert(nrf_saadc_value_t * buffer, uint16_t size);
/**
- * @brief Function for triggering the ADC offset calibration.
+ * @brief Function for triggering the SAADC offset calibration.
*
* This function is non-blocking. The application is notified about completion by the event handler.
* Calibration will also trigger DONE and RESULTDONE events.
*
- * The function will fail if ADC is busy or calibration is already in progress.
+ * The function will fail if the SAADC is busy or calibration is already in progress.
*
- * @retval NRFX_SUCCESS If calibration was started successfully.
- * @retval NRFX_ERROR_BUSY If the ADC driver is busy.
+ * @retval NRFX_SUCCESS The calibration was started successfully.
+ * @retval NRFX_ERROR_BUSY The SAADC driver is busy.
*/
nrfx_err_t nrfx_saadc_calibrate_offset(void);
/**
* @brief Function for retrieving the SAADC state.
*
- * @retval true If the ADC is busy.
- * @retval false If the ADC is ready.
+ * @retval true The SAADC is busy.
+ * @retval false The SAADC is ready.
*/
bool nrfx_saadc_is_busy(void);
/**
- * @brief Function for aborting ongoing and buffered conversions.
+ * @brief Function for aborting the ongoing and buffered conversions.
+ *
* @note @ref NRFX_SAADC_EVT_DONE event will be generated if there is a conversion in progress.
* Event will contain number of words in the sample buffer.
*/
@@ -303,12 +293,12 @@ void nrfx_saadc_abort(void);
*/
void nrfx_saadc_limits_set(uint8_t channel, int16_t limit_low, int16_t limit_high);
+/** @} */
+
void nrfx_saadc_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spi.h
index 91d0b0a3d..9128a2fdb 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spi.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spi.h
@@ -43,16 +43,14 @@ extern "C" {
* @defgroup nrfx_spi SPI driver
* @{
* @ingroup nrf_spi
- * @brief SPI peripheral driver.
+ * @brief Serial Peripheral Interface master (SPI) driver.
*/
-/**
- * @brief SPI master driver instance data structure.
- */
+/** @brief Data structure of the Serial Peripheral Interface master (SPI) driver instance. */
typedef struct
{
NRF_SPI_Type * p_reg; ///< Pointer to a structure with SPI registers.
- uint8_t drv_inst_idx; ///< Driver instance index.
+ uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only.
} nrfx_spi_t;
enum {
@@ -68,9 +66,7 @@ enum {
NRFX_SPI_ENABLED_COUNT
};
-/**
- * @brief Macro for creating an SPI master driver instance.
- */
+/** @brief Macro for creating an instance of the SPI master driver. */
#define NRFX_SPI_INSTANCE(id) \
{ \
.p_reg = NRFX_CONCAT_2(NRF_SPI, id), \
@@ -84,9 +80,7 @@ enum {
*/
#define NRFX_SPI_PIN_NOT_USED 0xFF
-/**
- * @brief SPI master driver instance configuration structure.
- */
+/** @brief Configuration structure of the SPI master driver instance. */
typedef struct
{
uint8_t sck_pin; ///< SCK pin number.
@@ -100,10 +94,10 @@ typedef struct
/**< Set to @ref NRFX_SPI_PIN_NOT_USED
* if this signal is not needed. The driver
* supports only active low for this signal.
- * If the signal should be active high,
+ * If the signal must be active high,
* it must be controlled externally. */
uint8_t irq_priority; ///< Interrupt priority.
- uint8_t orc; ///< Over-run character.
+ uint8_t orc; ///< Overrun character.
/**< This character is used when all bytes from the TX buffer are sent,
but the transfer continues due to RX. */
nrf_spi_frequency_t frequency; ///< SPI frequency.
@@ -111,9 +105,7 @@ typedef struct
nrf_spi_bit_order_t bit_order; ///< SPI bit order.
} nrfx_spi_config_t;
-/**
- * @brief SPI master instance default configuration.
- */
+/** @brief SPI master instance default configuration. */
#define NRFX_SPI_DEFAULT_CONFIG \
{ \
.sck_pin = NRFX_SPI_PIN_NOT_USED, \
@@ -127,45 +119,37 @@ typedef struct
.bit_order = NRF_SPI_BIT_ORDER_MSB_FIRST, \
}
-/**
- * @brief Single transfer descriptor structure.
- */
+/** @brief Single transfer descriptor structure. */
typedef struct
{
uint8_t const * p_tx_buffer; ///< Pointer to TX buffer.
size_t tx_length; ///< TX buffer length.
uint8_t * p_rx_buffer; ///< Pointer to RX buffer.
size_t rx_length; ///< RX buffer length.
-} nrfx_spi_xfer_desc_t;
+}nrfx_spi_xfer_desc_t;
/**
* @brief Macro for setting up single transfer descriptor.
*
* This macro is for internal use only.
*/
-#define NRFX_SPI_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \
- { \
- .p_tx_buffer = (uint8_t const *)(p_tx), \
- .tx_length = (tx_len), \
- .p_rx_buffer = (p_rx), \
- .rx_length = (rx_len), \
- }
+#define NRFX_SPI_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \
+{ \
+ .p_tx_buffer = (uint8_t const *)(p_tx), \
+ .tx_length = (tx_len), \
+ .p_rx_buffer = (p_rx), \
+ .rx_length = (rx_len), \
+}
-/**
- * @brief Macro for setting duplex TX RX transfer.
- */
+/** @brief Macro for setting the duplex TX RX transfer. */
#define NRFX_SPI_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \
NRFX_SPI_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length)
-/**
- * @brief Macro for setting TX transfer.
- */
+/** @brief Macro for setting the TX transfer. */
#define NRFX_SPI_XFER_TX(p_buf, length) \
NRFX_SPI_SINGLE_XFER(p_buf, length, NULL, 0)
-/**
- * @brief Macro for setting RX transfer.
- */
+/** @brief Macro for setting the RX transfer. */
#define NRFX_SPI_XFER_RX(p_buf, length) \
NRFX_SPI_SINGLE_XFER(NULL, 0, p_buf, length)
@@ -178,15 +162,14 @@ typedef enum
NRFX_SPI_EVENT_DONE, ///< Transfer done.
} nrfx_spi_evt_type_t;
+/** @brief SPI master event description with transmission details. */
typedef struct
{
nrfx_spi_evt_type_t type; ///< Event type.
nrfx_spi_xfer_desc_t xfer_desc; ///< Transfer details.
} nrfx_spi_evt_t;
-/**
- * @brief SPI master driver event handler type.
- */
+/** @brief SPI master driver event handler type. */
typedef void (* nrfx_spi_evt_handler_t)(nrfx_spi_evt_t const * p_event,
void * p_context);
@@ -196,15 +179,14 @@ typedef void (* nrfx_spi_evt_handler_t)(nrfx_spi_evt_t const * p_event,
* This function configures and enables the specified peripheral.
*
* @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_config Pointer to the structure with initial configuration.
- *
- * @param handler Event handler provided by the user. If NULL, transfers
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ * @param[in] handler Event handler provided by the user. If NULL, transfers
* will be performed in blocking mode.
- * @param p_context Context passed to event handler.
+ * @param[in] p_context Context passed to the event handler.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized.
- * @retval NRFX_ERROR_BUSY If some other peripheral with the same
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver was already initialized.
+ * @retval NRFX_ERROR_BUSY Some other peripheral with the same
* instance ID is already in use. This is
* possible only if @ref nrfx_prs module
* is enabled.
@@ -219,7 +201,7 @@ nrfx_err_t nrfx_spi_init(nrfx_spi_t const * const p_instance,
*
* @param[in] p_instance Pointer to the driver instance structure.
*/
-void nrfx_spi_uninit(nrfx_spi_t const * const p_instance);
+void nrfx_spi_uninit(nrfx_spi_t const * const p_instance);
/**
* @brief Function for starting the SPI data transfer.
@@ -234,29 +216,29 @@ void nrfx_spi_uninit(nrfx_spi_t const * const p_instance);
* @param flags Transfer options (0 for default settings).
* Currently, no additional flags are available.
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
- * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_BUSY The driver is not ready for a new transfer.
+ * @retval NRFX_ERROR_NOT_SUPPORTED The provided parameters are not supported.
*/
nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * const p_instance,
nrfx_spi_xfer_desc_t const * p_xfer_desc,
uint32_t flags);
/**
- * @brief Function for aborting ongoing transfer.
+ * @brief Function for aborting the ongoing transfer.
*
* @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_spi_abort(nrfx_spi_t const * p_instance);
+/** @} */
+
void nrfx_spi_0_irq_handler(void);
void nrfx_spi_1_irq_handler(void);
void nrfx_spi_2_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spim.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spim.h
index 241f95369..3efd4bdc3 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spim.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spim.h
@@ -43,18 +43,17 @@ extern "C" {
* @defgroup nrfx_spim SPIM driver
* @{
* @ingroup nrf_spim
- * @brief SPIM peripheral driver.
+ * @brief Serial Peripheral Interface Master with EasyDMA (SPIM) driver.
*/
-/**
- * @brief SPIM master driver instance data structure.
- */
+/** @brief Data structure of the Serial Peripheral Interface Master with EasyDMA (SPIM) driver instance. */
typedef struct
{
NRF_SPIM_Type * p_reg; ///< Pointer to a structure with SPIM registers.
- uint8_t drv_inst_idx; ///< Driver instance index.
+ uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only.
} nrfx_spim_t;
+#ifndef __NRFX_DOXYGEN__
enum {
#if NRFX_CHECK(NRFX_SPIM0_ENABLED)
NRFX_SPIM0_INST_IDX,
@@ -70,10 +69,9 @@ enum {
#endif
NRFX_SPIM_ENABLED_COUNT
};
+#endif
-/**
- * @brief Macro for creating an SPIM master driver instance.
- */
+/** @brief Macro for creating an instance of the SPIM driver. */
#define NRFX_SPIM_INSTANCE(id) \
{ \
.p_reg = NRFX_CONCAT_2(NRF_SPIM, id), \
@@ -87,9 +85,7 @@ enum {
*/
#define NRFX_SPIM_PIN_NOT_USED 0xFF
-/**
- * @brief SPIM master driver instance configuration structure.
- */
+/** @brief Configuration structure of the SPIM driver instance. */
typedef struct
{
uint8_t sck_pin; ///< SCK pin number.
@@ -104,44 +100,42 @@ typedef struct
* if this signal is not needed. */
bool ss_active_high; ///< Polarity of the Slave Select pin during transmission.
uint8_t irq_priority; ///< Interrupt priority.
- uint8_t orc; ///< Over-run character.
+ uint8_t orc; ///< Overrun character.
/**< This character is used when all bytes from the TX buffer are sent,
but the transfer continues due to RX. */
- nrf_spim_frequency_t frequency; ///< SPI frequency.
- nrf_spim_mode_t mode; ///< SPI mode.
- nrf_spim_bit_order_t bit_order; ///< SPI bit order.
+ nrf_spim_frequency_t frequency; ///< SPIM frequency.
+ nrf_spim_mode_t mode; ///< SPIM mode.
+ nrf_spim_bit_order_t bit_order; ///< SPIM bit order.
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__)
uint8_t dcx_pin; ///< D/CX pin number (optional).
uint8_t rx_delay; ///< Sample delay for input serial data on MISO.
/**< The value specifies the delay, in number of 64 MHz clock cycles
* (15.625 ns), from the the sampling edge of SCK (leading edge for
* CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until
- * the input serial data is sampled.*/
+ * the input serial data is sampled. */
bool use_hw_ss; ///< Indication to use software or hardware controlled Slave Select pin.
uint8_t ss_duration; ///< Slave Select duration before and after transmission.
/**< Minimum duration between the edge of CSN and the edge of SCK and minimum
* duration of CSN must stay inactive between transactions.
* The value is specified in number of 64 MHz clock cycles (15.625 ns).
- * Supported only for hardware controlled Slave Select.*/
+ * Supported only for hardware-controlled Slave Select. */
#endif
} nrfx_spim_config_t;
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__)
/**
- * @brief SPIM master instance extended default configuration.
+ * @brief Extended default configuration of the SPIM instance.
*/
#define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \
.dcx_pin = NRFX_SPIM_PIN_NOT_USED, \
.rx_delay = 0x02, \
- .ss_duration = 0x02, \
- .use_hw_ss = false,
+ .use_hw_ss = false, \
+ .ss_duration = 0x02,
#else
#define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG
#endif
-/**
- * @brief SPIM master instance default configuration.
- */
+/** @brief The default configuration of the SPIM master instance. */
#define NRFX_SPIM_DEFAULT_CONFIG \
{ \
.sck_pin = NRFX_SPIM_PIN_NOT_USED, \
@@ -157,15 +151,18 @@ typedef struct
NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \
}
-#define NRFX_SPIM_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */
-#define NRFX_SPIM_FLAG_RX_POSTINC (1UL << 1) /**< RX buffer address incremented after transfer. */
-#define NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */
-#define NRFX_SPIM_FLAG_HOLD_XFER (1UL << 3) /**< Set up the transfer but do not start it. */
-#define NRFX_SPIM_FLAG_REPEATED_XFER (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */
+/** @brief Flag indicating that TX buffer address will be incremented after transfer. */
+#define NRFX_SPIM_FLAG_TX_POSTINC (1UL << 0)
+/** @brief Flag indicating that RX buffer address will be incremented after transfer. */
+#define NRFX_SPIM_FLAG_RX_POSTINC (1UL << 1)
+/** @brief Flag indicating that the interrupt after each transfer will be suppressed, and the event handler will not be called. */
+#define NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2)
+/** @brief Flag indicating that the transfer will be set up, but not started. */
+#define NRFX_SPIM_FLAG_HOLD_XFER (1UL << 3)
+/** @brief Flag indicating that the transfer will be executed multiple times. */
+#define NRFX_SPIM_FLAG_REPEATED_XFER (1UL << 4)
-/**
- * @brief Single transfer descriptor structure.
- */
+/** @brief Single transfer descriptor structure. */
typedef struct
{
uint8_t const * p_tx_buffer; ///< Pointer to TX buffer.
@@ -179,29 +176,23 @@ typedef struct
*
* This macro is for internal use only.
*/
-#define NRFX_SPIM_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \
- { \
- .p_tx_buffer = (uint8_t const *)(p_tx), \
- .tx_length = (tx_len), \
- .p_rx_buffer = (p_rx), \
- .rx_length = (rx_len), \
+#define NRFX_SPIM_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \
+ { \
+ .p_tx_buffer = (uint8_t const *)(p_tx), \
+ .tx_length = (tx_len), \
+ .p_rx_buffer = (p_rx), \
+ .rx_length = (rx_len), \
}
-/**
- * @brief Macro for setting duplex TX RX transfer.
- */
-#define NRFX_SPIM_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \
+/** @brief Macro for setting the duplex TX RX transfer. */
+#define NRFX_SPIM_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \
NRFX_SPIM_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length)
-/**
- * @brief Macro for setting TX transfer.
- */
+/** @brief Macro for setting the TX transfer. */
#define NRFX_SPIM_XFER_TX(p_buf, length) \
NRFX_SPIM_SINGLE_XFER(p_buf, length, NULL, 0)
-/**
- * @brief Macro for setting RX transfer.
- */
+/** @brief Macro for setting the RX transfer. */
#define NRFX_SPIM_XFER_RX(p_buf, length) \
NRFX_SPIM_SINGLE_XFER(NULL, 0, p_buf, length)
@@ -214,37 +205,35 @@ typedef enum
NRFX_SPIM_EVENT_DONE, ///< Transfer done.
} nrfx_spim_evt_type_t;
+/** @brief SPIM event description with transmission details. */
typedef struct
{
nrfx_spim_evt_type_t type; ///< Event type.
nrfx_spim_xfer_desc_t xfer_desc; ///< Transfer details.
} nrfx_spim_evt_t;
-/**
- * @brief SPIM master driver event handler type.
- */
+/** @brief SPIM driver event handler type. */
typedef void (* nrfx_spim_evt_handler_t)(nrfx_spim_evt_t const * p_event,
void * p_context);
/**
- * @brief Function for initializing the SPI master driver instance.
+ * @brief Function for initializing the SPIM driver instance.
*
* This function configures and enables the specified peripheral.
*
* @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_config Pointer to the structure with initial configuration.
- *
- * @param handler Event handler provided by the user. If NULL, transfers
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ * @param[in] handler Event handler provided by the user. If NULL, transfers
* will be performed in blocking mode.
- * @param p_context Context passed to event handler.
+ * @param[in] p_context Context passed to event handler.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized.
- * @retval NRFX_ERROR_BUSY If some other peripheral with the same
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver was already initialized.
+ * @retval NRFX_ERROR_BUSY Some other peripheral with the same
* instance ID is already in use. This is
* possible only if @ref nrfx_prs module
* is enabled.
- * @retval NRFX_ERROR_NOT_SUPPORTED If requested configuration is not supported
+ * @retval NRFX_ERROR_NOT_SUPPORTED Requested configuration is not supported
* by the SPIM instance.
*/
nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
@@ -253,30 +242,30 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
void * p_context);
/**
- * @brief Function for uninitializing the SPI master driver instance.
+ * @brief Function for uninitializing the SPIM driver instance.
*
* @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_spim_uninit(nrfx_spim_t const * const p_instance);
/**
- * @brief Function for starting the SPI data transfer.
+ * @brief Function for starting the SPIM data transfer.
*
* Additional options are provided using the @c flags parameter:
*
- * - @ref NRFX_SPIM_FLAG_TX_POSTINC and @ref NRFX_SPIM_FLAG_RX_POSTINC :
- * Post-incrementation of buffer addresses. Supported only by SPIM.
- * - @ref NRFX_SPIM_FLAG_HOLD_XFER : Driver is not starting the transfer. Use this
- * flag if the transfer is triggered externally by PPI. Supported only by SPIM. Use
+ * - @ref NRFX_SPIM_FLAG_TX_POSTINC and @ref NRFX_SPIM_FLAG_RX_POSTINC -
+ * Post-incrementation of buffer addresses.
+ * - @ref NRFX_SPIM_FLAG_HOLD_XFER - Driver is not starting the transfer. Use this
+ * flag if the transfer is triggered externally by PPI. Use
* @ref nrfx_spim_start_task_get to get the address of the start task.
- * - @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER : No user event handler after transfer
- * completion. This also means no interrupt at the end of the transfer. Supported only by SPIM.
+ * - @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER - No user event handler after transfer
+ * completion. This also means no interrupt at the end of the transfer.
* If @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into
* busy state, so you must ensure that the next transfers are set up when SPIM is not active.
* @ref nrfx_spim_end_event_get function can be used to detect end of transfer. Option can be used
* together with @ref NRFX_SPIM_FLAG_REPEATED_XFER to prepare a sequence of SPI transfers
* without interruptions.
- * - @ref NRFX_SPIM_FLAG_REPEATED_XFER : Prepare for repeated transfers. You can set
+ * - @ref NRFX_SPIM_FLAG_REPEATED_XFER - Prepare for repeated transfers. You can set
* up a number of transfers that will be triggered externally (for example by PPI). An example is
* a TXRX transfer with the options @ref NRFX_SPIM_FLAG_RX_POSTINC,
* @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER, and @ref NRFX_SPIM_FLAG_REPEATED_XFER. After the
@@ -285,7 +274,7 @@ void nrfx_spim_uninit(nrfx_spim_t const * const p_instance);
* @ref nrfx_spim_end_event_get can be used to get the address of the END event, which can be
* used to count the number of transfers. If @ref NRFX_SPIM_FLAG_REPEATED_XFER is used,
* the driver does not set the instance into busy state, so you must ensure that the next
- * transfers are set up when SPIM is not active. Supported only by SPIM.
+ * transfers are set up when SPIM is not active.
*
* @note Peripherals using EasyDMA (including SPIM) require the transfer buffers
* to be placed in the Data RAM region. If this condition is not met,
@@ -295,10 +284,10 @@ void nrfx_spim_uninit(nrfx_spim_t const * const p_instance);
* @param p_xfer_desc Pointer to the transfer descriptor.
* @param flags Transfer options (0 for default settings).
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
- * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported.
- * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_BUSY The driver is not ready for a new transfer.
+ * @retval NRFX_ERROR_NOT_SUPPORTED The provided parameters are not supported.
+ * @retval NRFX_ERROR_INVALID_ADDR The provided buffers are not placed in the Data
* RAM region.
*/
nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance,
@@ -307,7 +296,7 @@ nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance,
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__)
/**
- * @brief Function for starting the SPI data transfer with DCX control.
+ * @brief Function for starting the SPIM data transfer with DCX control.
*
* See @ref nrfx_spim_xfer for description of additional options of transfer
* provided by the @c flags parameter.
@@ -328,11 +317,11 @@ nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance,
* @c cmd_length parameter causes all transmitted bytes
* to be marked as command bytes.
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
- * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported.
- * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data
- * RAM region.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_BUSY The driver is not ready for a new transfer.
+ * @retval NRFX_ERROR_NOT_SUPPORTED The provided parameters are not supported.
+ * @retval NRFX_ERROR_INVALID_ADDR The provided buffers are not placed in the Data
+ * RAM region.
*/
nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * const p_instance,
nrfx_spim_xfer_desc_t const * p_xfer_desc,
@@ -343,12 +332,12 @@ nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * const p_instance,
/**
* @brief Function for returning the address of a SPIM start task.
*
- * This function should be used if @ref nrfx_spim_xfer was called with the flag @ref NRFX_SPIM_FLAG_HOLD_XFER.
+ * This function is to be used if @ref nrfx_spim_xfer was called with the flag @ref NRFX_SPIM_FLAG_HOLD_XFER.
* In that case, the transfer is not started by the driver, but it must be started externally by PPI.
*
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*
- * @return Start task address.
+ * @return Start task address.
*/
uint32_t nrfx_spim_start_task_get(nrfx_spim_t const * p_instance);
@@ -367,10 +356,12 @@ uint32_t nrfx_spim_end_event_get(nrfx_spim_t const * p_instance);
/**
* @brief Function for aborting ongoing transfer.
*
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_spim_abort(nrfx_spim_t const * p_instance);
+/** @} */
+
void nrfx_spim_0_irq_handler(void);
void nrfx_spim_1_irq_handler(void);
@@ -378,8 +369,6 @@ void nrfx_spim_2_irq_handler(void);
void nrfx_spim_3_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spis.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spis.h
index 370e12412..aa68ce42d 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spis.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_spis.h
@@ -41,19 +41,20 @@ extern "C" {
#endif
/**
- * @defgroup nrfx_spis SPI slave driver
+ * @defgroup nrfx_spis SPIS driver
* @{
* @ingroup nrf_spis
- * @brief SPI Slave peripheral driver.
+ * @brief Serial Peripheral Interface Slave with EasyDMA (SPIS) driver.
*/
-/** @brief SPI slave driver instance data structure. */
+/** @brief Data structure for the Serial Peripheral Interface Slave with EasyDMA (SPIS) driver instance. */
typedef struct
{
NRF_SPIS_Type * p_reg; //!< Pointer to a structure with SPIS registers.
- uint8_t drv_inst_idx; //!< Driver instance index.
+ uint8_t drv_inst_idx; //!< Index of the driver instance. For internal use only.
} nrfx_spis_t;
+#ifndef __NRFX_DOXYGEN__
enum {
#if NRFX_CHECK(NRFX_SPIS0_ENABLED)
NRFX_SPIS0_INST_IDX,
@@ -69,8 +70,9 @@ enum {
#endif
NRFX_SPIS_ENABLED_COUNT
};
+#endif
-/** @brief Macro for creating an SPI slave driver instance. */
+/** @brief Macro for creating an instance of the SPI slave driver. */
#define NRFX_SPIS_INSTANCE(id) \
{ \
.p_reg = NRFX_CONCAT_2(NRF_SPIS, id), \
@@ -105,12 +107,12 @@ typedef struct
size_t tx_amount; //!< Number of bytes transmitted in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events.
} nrfx_spis_evt_t;
-/** @brief SPI slave instance default configuration. */
+/** @brief The default configuration of the SPI slave instance. */
#define NRFX_SPIS_DEFAULT_CONFIG \
{ \
- .sck_pin = NRFX_SPIS_PIN_NOT_USED, \
- .mosi_pin = NRFX_SPIS_PIN_NOT_USED, \
.miso_pin = NRFX_SPIS_PIN_NOT_USED, \
+ .mosi_pin = NRFX_SPIS_PIN_NOT_USED, \
+ .sck_pin = NRFX_SPIS_PIN_NOT_USED, \
.csn_pin = NRFX_SPIS_PIN_NOT_USED, \
.mode = NRF_SPIS_MODE_0, \
.bit_order = NRF_SPIS_BIT_ORDER_MSB_FIRST, \
@@ -161,15 +163,15 @@ typedef void (*nrfx_spis_event_handler_t)(nrfx_spis_evt_t const * p_event,
* to detect falling edges on CSN pin.
*
* @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] event_handler Function to be called by the SPI slave driver upon event.
* Must not be NULL.
* @param[in] p_context Context passed to the event handler.
*
- * @retval NRFX_SUCCESS If the initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized.
- * @retval NRFX_ERROR_INVALID_PARAM If an invalid parameter is supplied.
- * @retval NRFX_ERROR_BUSY If some other peripheral with the same
+ * @retval NRFX_SUCCESS The initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The instance is already initialized.
+ * @retval NRFX_ERROR_INVALID_PARAM Invalid parameter is supplied.
+ * @retval NRFX_ERROR_BUSY Some other peripheral with the same
* instance ID is already in use. This is
* possible only if @ref nrfx_prs module
* is enabled.
@@ -197,30 +199,30 @@ void nrfx_spis_uninit(nrfx_spis_t const * const p_instance);
*
* When either the memory buffer configuration or the SPI transaction has been
* completed, the event callback function will be called with the appropriate event
- * @ref nrfx_spis_evt_type_t. Note that the callback function can be called before returning from
+ * @ref nrfx_spis_evt_type_t. The callback function can be called before returning from
* this function, because it is called from the SPI slave interrupt context.
*
* @note This function can be called from the callback function context.
*
* @note Client applications must call this function after every @ref NRFX_SPIS_XFER_DONE event if
- * the SPI slave driver should be prepared for a possible new SPI transaction.
+ * the SPI slave driver must be prepared for a possible new SPI transaction.
*
* @note Peripherals using EasyDMA (including SPIS) require the transfer buffers
* to be placed in the Data RAM region. If this condition is not met,
* this function will fail with the error code NRFX_ERROR_INVALID_ADDR.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_tx_buffer Pointer to the TX buffer. Can be NULL when the buffer length is zero.
- * @param[in] p_rx_buffer Pointer to the RX buffer. Can be NULL when the buffer length is zero.
- * @param[in] tx_buffer_length Length of the TX buffer in bytes.
- * @param[in] rx_buffer_length Length of the RX buffer in bytes.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_tx_buffer Pointer to the TX buffer. Can be NULL when the buffer length is zero.
+ * @param[in] p_rx_buffer Pointer to the RX buffer. Can be NULL when the buffer length is zero.
+ * @param[in] tx_buffer_length Length of the TX buffer in bytes.
+ * @param[in] rx_buffer_length Length of the RX buffer in bytes.
*
- * @retval NRFX_SUCCESS If the operation was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the operation failed because the SPI slave device is in an incorrect state.
- * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data
+ * @retval NRFX_SUCCESS The operation was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The operation failed because the SPI slave device is in an incorrect state.
+ * @retval NRFX_ERROR_INVALID_ADDR The provided buffers are not placed in the Data
* RAM region.
- * @retval NRFX_ERROR_INVALID_LENGTH If provided lengths exceed the EasyDMA limits for the peripheral.
- * @retval NRFX_ERROR_INTERNAL If the operation failed because of an internal error.
+ * @retval NRFX_ERROR_INVALID_LENGTH Provided lengths exceed the EasyDMA limits for the peripheral.
+ * @retval NRFX_ERROR_INTERNAL The operation failed because of an internal error.
*/
nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * const p_instance,
uint8_t const * p_tx_buffer,
@@ -228,6 +230,8 @@ nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * const p_instance,
uint8_t * p_rx_buffer,
size_t rx_buffer_length);
+/** @} */
+
void nrfx_spis_0_irq_handler(void);
void nrfx_spis_1_irq_handler(void);
@@ -235,8 +239,6 @@ void nrfx_spis_2_irq_handler(void);
void nrfx_spis_3_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_swi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_swi.h
index 653c3e79d..16778a271 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_swi.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_swi.h
@@ -78,23 +78,22 @@ typedef uint16_t nrfx_swi_flags_t;
*/
typedef void (*nrfx_swi_handler_t)(nrfx_swi_t swi, nrfx_swi_flags_t flags);
-
/**
* @brief Function for allocating the first unused SWI instance and setting a handler.
*
* If provided handler is not NULL, an allocated SWI has its interrupt enabled by default.
* The interrupt can be disabled by @ref nrfx_swi_int_disable.
*
- * @param[out] p_swi Points to a place where the allocated SWI instance
- * number is to be stored.
- * @param[in] event_handler Event handler function.
- * If NULL, no interrupt will be enabled.
- * It can be NULL only if the EGU driver is enabled.
- * For classic SWI, it must be a valid handler pointer.
- * @param[in] irq_priority Interrupt priority.
+ * @param[out] p_swi Points to a place where the allocated SWI instance
+ * number is to be stored.
+ * @param[in] event_handler Event handler function.
+ * If NULL, no interrupt will be enabled.
+ * It can be NULL only if the EGU driver is enabled.
+ * For classic SWI, it must be a valid handler pointer.
+ * @param[in] irq_priority Interrupt priority.
*
- * @retval NRFX_SUCCESS If the SWI was successfully allocated.
- * @retval NRFX_ERROR_NO_MEM If there is no available SWI to be used.
+ * @retval NRFX_SUCCESS The SWI was successfully allocated.
+ * @retval NRFX_ERROR_NO_MEM There is no available SWI to be used.
*/
nrfx_err_t nrfx_swi_alloc(nrfx_swi_t * p_swi,
nrfx_swi_handler_t event_handler,
@@ -105,22 +104,22 @@ nrfx_err_t nrfx_swi_alloc(nrfx_swi_t * p_swi,
*
* Use @ref nrfx_swi_int_enable to re-enable the interrupt.
*
- * @param[in] swi SWI instance.
+ * @param[in] swi SWI instance.
*/
void nrfx_swi_int_disable(nrfx_swi_t swi);
/**
* @brief Function for enabling an allocated SWI interrupt.
*
- * @param[in] swi SWI instance.
+ * @param[in] swi SWI instance.
*/
void nrfx_swi_int_enable(nrfx_swi_t swi);
/**
* @brief Function for freeing a previously allocated SWI.
*
- * @param[in,out] p_swi SWI instance to free. The value is changed to
- * @ref NRFX_SWI_UNALLOCATED on success.
+ * @param[in,out] p_swi SWI instance to free. The value is changed to
+ * @ref NRFX_SWI_UNALLOCATED on success.
*/
void nrfx_swi_free(nrfx_swi_t * p_swi);
@@ -130,8 +129,8 @@ void nrfx_swi_all_free(void);
/**
* @brief Function for triggering the SWI.
*
- * @param[in] swi SWI to trigger.
- * @param[in] flag_number Number of user flag to trigger.
+ * @param[in] swi SWI to trigger.
+ * @param[in] flag_number Number of user flag to trigger.
*/
void nrfx_swi_trigger(nrfx_swi_t swi,
uint8_t flag_number);
@@ -139,10 +138,10 @@ void nrfx_swi_trigger(nrfx_swi_t swi,
/**
* @brief Function for checking if the specified SWI is currently allocated.
*
- * @param[in] swi SWI instance.
+ * @param[in] swi SWI instance.
*
- * @retval true If the SWI instance is allocated.
- * @retval false Otherwise.
+ * @retval true The SWI instance is allocated.
+ * @retval false The SWI instance is not allocated.
*/
bool nrfx_swi_is_allocated(nrfx_swi_t swi);
@@ -152,10 +151,10 @@ bool nrfx_swi_is_allocated(nrfx_swi_t swi);
* @brief Function for returning the base address of the EGU peripheral
* associated with the specified SWI instance.
*
- * @param[in] swi SWI instance.
+ * @param[in] swi SWI instance.
*
- * @returns EGU base address or NULL if the specified SWI instance number
- * is too high.
+ * @return EGU base address or NULL if the specified SWI instance number
+ * is too high.
*/
__STATIC_INLINE NRF_EGU_Type * nrfx_swi_egu_instance_get(nrfx_swi_t swi)
{
@@ -172,10 +171,10 @@ __STATIC_INLINE NRF_EGU_Type * nrfx_swi_egu_instance_get(nrfx_swi_t swi)
/**
* @brief Function for returning the EGU trigger task address.
*
- * @param[in] swi SWI instance.
- * @param[in] channel Number of the EGU channel.
+ * @param[in] swi SWI instance.
+ * @param[in] channel Number of the EGU channel.
*
- * @returns Address of EGU trigger task.
+ * @return Address of the EGU trigger task.
*/
__STATIC_INLINE uint32_t nrfx_swi_task_trigger_address_get(nrfx_swi_t swi,
uint8_t channel)
@@ -194,12 +193,12 @@ __STATIC_INLINE uint32_t nrfx_swi_task_trigger_address_get(nrfx_swi_t swi,
}
/**
- * @brief Function for returning the EGU triggered event address.
+ * @brief Function for returning the EGU-triggered event address.
*
- * @param[in] swi SWI instance.
- * @param[in] channel Number of the EGU channel.
+ * @param[in] swi SWI instance.
+ * @param[in] channel Number of the EGU channel.
*
- * @returns Address of EGU triggered event.
+ * @return Address of the EGU-triggered event.
*/
__STATIC_INLINE uint32_t nrfx_swi_event_triggered_address_get(nrfx_swi_t swi,
uint8_t channel)
@@ -219,6 +218,8 @@ __STATIC_INLINE uint32_t nrfx_swi_event_triggered_address_get(nrfx_swi_t swi,
#endif // NRFX_CHECK(NRFX_EGU_ENABLED) || defined(__NRFX_DOXYGEN__)
+/** @} */
+
void nrfx_swi_0_irq_handler(void);
void nrfx_swi_1_irq_handler(void);
@@ -227,7 +228,6 @@ void nrfx_swi_3_irq_handler(void);
void nrfx_swi_4_irq_handler(void);
void nrfx_swi_5_irq_handler(void);
-/** @} */
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_systick.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_systick.h
index 0da2d6078..5e8feda92 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_systick.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_systick.h
@@ -49,71 +49,71 @@ extern "C" {
* This driver configures ARM(R) SysTick as a free-running timer.
* This timer is used to generate delays and pool for timeouts.
* Only relatively short timeouts are supported.
- * The SysTick works on 64MHz and is 24-bits wide.
- * It means that it overflows around 4 times per second and around 250 ms
- * would be the highest supported time in the library.
- * But it would be really hard to detect if overflow was generated without
- * using interrupts. For safety we would limit the maximum delay range by half.
+ * The SysTick works on 64MHz and is 24-bit wide.
+ * This means that it overflows around 4 times per second and
+ * around 250 microseconds will be the highest supported time in the library.
+ * As it is hard to detect if the overflow is generated without
+ * using interrupts, the maximum delay range is halved for safety reasons.
*/
/**
- * @brief The value type that holds the SysTick state
+ * @brief The value type that holds the SysTick state.
*
* This variable is used to count the requested timeout.
* @sa nrfx_systick_get
*/
typedef struct {
- uint32_t time; //!< Registered time value
+ uint32_t time; //!< Registered time value.
} nrfx_systick_state_t;
/**
- * @brief Configure and start the timer
+ * @brief Function for configuring and starting the timer.
*
* Function configures SysTick as a free-running timer without interrupt.
*/
void nrfx_systick_init(void);
/**
- * @brief Get current SysTick state
+ * @brief Function for getting the current SysTick state.
*
- * Function gets current state of the SysTick timer.
+ * Function gets the current state of the SysTick timer.
* It can be used to check time-out by @ref nrfx_systick_test.
*
- * @param[out] p_state The pointer to the state variable to be filled
+ * @param[out] p_state The pointer to the state variable to be filled.
*/
void nrfx_systick_get(nrfx_systick_state_t * p_state);
/**
- * @brief Test if specified time is up in relation to remembered state
+ * @brief Function for testing if the current time is higher in relation to the remembered state.
*
* @param[in] p_state Remembered state set by @ref nrfx_systick_get
* @param[in] us Required time-out.
*
- * @retval true If current time is higher than specified state plus given time-out.
- * @retval false If current time is lower than specified state plus given time-out
+ * @retval true The current time is higher than the specified state plus the given time-out.
+ * @retval false The current time is lower than the specified state plus the given time-out.
*/
bool nrfx_systick_test(nrfx_systick_state_t const * p_state, uint32_t us);
/**
- * @brief Blocking delay in CPU ticks
+ * @brief Function for delaying the execution for the specified amount of CPU ticks.
*
- * @param[in] ticks Number of CPU ticks to delay.
+ * @param[in] ticks Number of CPU ticks when the execution is blocked.
*/
void nrfx_systick_delay_ticks(uint32_t ticks);
/**
- * @brief Blocking delay in us
+ * @brief Function for delaying the execution for the specified amount of microseconds.
*
- * @param[in] us Number of microseconds to delay.
+ * @param[in] us Number of microseconds when the execution is blocked.
*/
void nrfx_systick_delay_us(uint32_t us);
/**
- * @brief Blocking delay in ms
+ * @brief Function for delaying the execution for the specified amount of milliseconds.
*
* This delay function removes the limits of the highest possible delay value.
*
- * @param[in] ms Number of milliseconds to delay.
+ * @param[in] ms Number of milliseconds when the execution is blocked.
*/
void nrfx_systick_delay_ms(uint32_t ms);
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_temp.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_temp.h
new file mode 100644
index 000000000..e67a9fdac
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_temp.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_TEMP_H__
+#define NRFX_TEMP_H__
+
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfx_temp TEMP driver
+ * @{
+ * @ingroup nrf_temp
+ * @brief Temperature sensor (TEMP) driver.
+ */
+
+/** @brief Structure for TEMP configuration. */
+typedef struct
+{
+ uint8_t interrupt_priority; /**< Interrupt priority. */
+} nrfx_temp_config_t;
+
+/** @brief TEMP default configuration. */
+#define NRFX_TEMP_DEFAULT_CONFIG \
+ { \
+ .interrupt_priority = NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY, \
+ }
+
+/**
+ * @brief TEMP driver data ready handler type.
+ *
+ * @param temperature Raw temperature in a 2's complement signed value
+ * representation. This value can be converted to Celsius
+ * scale using the @ref nrfx_temp_calculate() function.
+ */
+typedef void (* nrfx_temp_data_handler_t)(int32_t raw_temperature);
+
+/**
+ * @brief Function for initializing the TEMP driver.
+ *
+ * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] handler Data handler provided by the user. If not provided,
+ * the driver is initialized in blocking mode.
+ *
+ * @retval NRFX_SUCCESS Driver was successfully initialized.
+ * @retval NRFX_ERROR_ALREADY_INITIALIZED Driver was already initialized.
+ */
+nrfx_err_t nrfx_temp_init(nrfx_temp_config_t const * p_config, nrfx_temp_data_handler_t handler);
+
+/** @brief Function for uninitializing the TEMP driver. */
+void nrfx_temp_uninit(void);
+
+/**
+ * @brief Function for getting the temperature measurement in a 2's complement
+ * signed value representation.
+ *
+ * This function returns the last value prepared by the TEMP peripheral.
+ * In blocking mode, it should be used after calling the @ref nrfx_temp_measure()
+ * function. In non-blocking mode, it is called internally by the driver,
+ * and the value it returns is passed to the data handler.
+ *
+ * @return Temperature measurement result in a 2's complement signed value
+ * representation.
+ */
+__STATIC_INLINE int32_t nrfx_temp_result_get(void);
+
+/**
+ * @brief Function for calculating the temperature value in Celsius scale from raw data.
+ *
+ * The returned temperature value is in Celsius scale, multiplied by 100
+ * For example, the actual temperature of 25.75[C] will be returned as a 2575 signed integer.
+ * Measurement accuracy is 0.25[C].
+ *
+ * @param[in] raw_measurement Temperature value in a 2's complement signed
+ * value representation.
+ *
+ * @return Temperature measurement result.
+ */
+int32_t nrfx_temp_calculate(int32_t raw_measurement);
+
+/**
+ * @brief Function for starting the temperature measurement.
+ *
+ * Non-blocking mode:
+ * This function returns immediately. After a measurement, the handler specified
+ * during initialization is called, with measurement result as the parameter.
+ *
+ * Blocking mode:
+ * This function waits until the measurement is finished. The value should be read
+ * using the @ref nrfx_temp_result_get() function.
+ *
+ * @retval NRFX_SUCCESS In non-blocking mode: Measurement was started.
+ * An interrupt will be generated soon.
+ * In blocking mode:
+ * Measurement was started and finished. Data can
+ * be read using the @ref nrfx_temp_result_get() function.
+ * @retval NRFX_ERROR_INTERNAL In non-blocking mode:
+ * Not applicable.
+ * In blocking mode:
+ * Measurement data ready event did not occur.
+ */
+nrfx_err_t nrfx_temp_measure(void);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE int32_t nrfx_temp_result_get(void)
+{
+ return nrf_temp_result_get(NRF_TEMP);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+/** @} */
+
+void nrfx_temp_irq_handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_TEMP_H__
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_timer.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_timer.h
index 447b98854..057bbd2c4 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_timer.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_timer.h
@@ -52,13 +52,11 @@ extern "C" {
typedef struct
{
NRF_TIMER_Type * p_reg; ///< Pointer to the structure with TIMER peripheral instance registers.
- uint8_t instance_id; ///< Driver instance index.
+ uint8_t instance_id; ///< Index of the driver instance. For internal use only.
uint8_t cc_channel_count; ///< Number of capture/compare channels.
} nrfx_timer_t;
-/**
- * @brief Macro for creating a timer driver instance.
- */
+/** @brief Macro for creating a timer driver instance. */
#define NRFX_TIMER_INSTANCE(id) \
{ \
.p_reg = NRFX_CONCAT_2(NRF_TIMER, id), \
@@ -66,6 +64,7 @@ typedef struct
.cc_channel_count = NRF_TIMER_CC_CHANNEL_COUNT(id), \
}
+#ifndef __NRFX_DOXYGEN__
enum {
#if NRFX_CHECK(NRFX_TIMER0_ENABLED)
NRFX_TIMER0_INST_IDX,
@@ -84,10 +83,9 @@ enum {
#endif
NRFX_TIMER_ENABLED_COUNT
};
+#endif
-/**
- * @brief Timer driver instance configuration structure.
- */
+/** @brief The configuration structure of the timer driver instance. */
typedef struct
{
nrf_timer_frequency_t frequency; ///< Frequency.
@@ -97,9 +95,7 @@ typedef struct
void * p_context; ///< Context passed to interrupt handler.
} nrfx_timer_config_t;
-/**
- * @brief Timer driver instance default configuration.
- */
+/** @brief Timer driver instance default configuration. */
#define NRFX_TIMER_DEFAULT_CONFIG \
{ \
.frequency = (nrf_timer_frequency_t)NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY,\
@@ -125,12 +121,12 @@ typedef void (* nrfx_timer_event_handler_t)(nrf_timer_event_t event_type,
* @brief Function for initializing the timer.
*
* @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] timer_event_handler Event handler provided by the user.
* Must not be NULL.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The instance is already initialized.
*/
nrfx_err_t nrfx_timer_init(nrfx_timer_t const * const p_instance,
nrfx_timer_config_t const * p_config,
@@ -153,7 +149,7 @@ void nrfx_timer_enable(nrfx_timer_t const * const p_instance);
/**
* @brief Function for turning off the timer.
*
- * Note that the timer will allow to enter the lowest possible SYSTEM_ON state
+ * The timer will allow to enter the lowest possible SYSTEM_ON state
* only after this function is called.
*
* @param[in] p_instance Pointer to the driver instance structure.
@@ -165,7 +161,8 @@ void nrfx_timer_disable(nrfx_timer_t const * const p_instance);
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @return True if timer is enabled, false otherwise.
+ * @retval true Timer is enabled.
+ * @retval false Timer is not enabled.
*/
bool nrfx_timer_is_enabled(nrfx_timer_t const * const p_instance);
@@ -198,7 +195,7 @@ void nrfx_timer_clear(nrfx_timer_t const * const p_instance);
void nrfx_timer_increment(nrfx_timer_t const * const p_instance);
/**
- * @brief Function for returning the address of a specific timer task.
+ * @brief Function for returning the address of the specified timer task.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] timer_task Timer task.
@@ -209,7 +206,7 @@ __STATIC_INLINE uint32_t nrfx_timer_task_address_get(nrfx_timer_t const * const
nrf_timer_task_t timer_task);
/**
- * @brief Function for returning the address of a specific timer capture task.
+ * @brief Function for returning the address of the specified timer capture task.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] channel Capture channel number.
@@ -220,7 +217,7 @@ __STATIC_INLINE uint32_t nrfx_timer_capture_task_address_get(nrfx_timer_t const
uint32_t channel);
/**
- * @brief Function for returning the address of a specific timer event.
+ * @brief Function for returning the address of the specified timer event.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] timer_event Timer event.
@@ -231,7 +228,7 @@ __STATIC_INLINE uint32_t nrfx_timer_event_address_get(nrfx_timer_t const * const
nrf_timer_event_t timer_event);
/**
- * @brief Function for returning the address of a specific timer compare event.
+ * @brief Function for returning the address of the specified timer compare event.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] channel Compare channel number.
@@ -253,7 +250,7 @@ uint32_t nrfx_timer_capture(nrfx_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel);
/**
- * @brief Function for returning the capture value from a specific channel.
+ * @brief Function for returning the capture value from the specified channel.
*
* Use this function to read channel values when PPI is used for capturing.
*
@@ -279,15 +276,14 @@ void nrfx_timer_compare(nrfx_timer_t const * const p_instance,
bool enable_int);
/**
- * @brief Function for setting the timer channel in extended compare mode.
+ * @brief Function for setting the timer channel in the extended compare mode.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] cc_channel Compare channel number.
* @param[in] cc_value Compare value.
* @param[in] timer_short_mask Shortcut between the compare event on the channel
* and the timer task (STOP or CLEAR).
- * @param[in] enable_int Enable or disable the interrupt for the compare
- * channel.
+ * @param[in] enable_int Enable or disable the interrupt for the compare channel.
*/
void nrfx_timer_extended_compare(nrfx_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel,
@@ -386,6 +382,8 @@ __STATIC_INLINE uint32_t nrfx_timer_ms_to_ticks(nrfx_timer_t const * const p_ins
#endif // SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
void nrfx_timer_0_irq_handler(void);
void nrfx_timer_1_irq_handler(void);
@@ -394,8 +392,6 @@ void nrfx_timer_3_irq_handler(void);
void nrfx_timer_4_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi.h
index 512e2e357..5e39626f1 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi.h
@@ -33,6 +33,7 @@
#define NRFX_TWI_H__
#include
+#include
#include
#ifdef __cplusplus
@@ -43,7 +44,7 @@ extern "C" {
* @defgroup nrfx_twi TWI driver
* @{
* @ingroup nrf_twi
- * @brief TWI peripheral driver.
+ * @brief Two Wire Interface master (TWI) peripheral driver.
*/
/**
@@ -52,18 +53,17 @@ extern "C" {
typedef struct
{
NRF_TWI_Type * p_twi; ///< Pointer to a structure with TWI registers.
- uint8_t drv_inst_idx; ///< Driver instance index.
+ uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only.
} nrfx_twi_t;
-/**
- * @brief Macro for creating a TWI master driver instance.
- */
+/** @brief Macro for creating a TWI master driver instance. */
#define NRFX_TWI_INSTANCE(id) \
{ \
.p_twi = NRFX_CONCAT_2(NRF_TWI, id), \
.drv_inst_idx = NRFX_CONCAT_3(NRFX_TWI, id, _INST_IDX), \
}
+#ifndef __NRFX_DOXYGEN__
enum {
#if NRFX_CHECK(NRFX_TWI0_ENABLED)
NRFX_TWI0_INST_IDX,
@@ -73,22 +73,19 @@ enum {
#endif
NRFX_TWI_ENABLED_COUNT
};
+#endif
-/**
- * @brief Structure for the TWI master driver instance configuration.
- */
+/** @brief Structure for the configuration of the TWI master driver instance. */
typedef struct
{
- uint32_t scl; ///< SCL pin number.
- uint32_t sda; ///< SDA pin number.
- nrf_twi_frequency_t frequency; ///< TWI frequency.
- uint8_t interrupt_priority; ///< Interrupt priority.
- bool hold_bus_uninit; ///< Hold pull up state on gpio pins after uninit.
+ uint32_t scl; ///< SCL pin number.
+ uint32_t sda; ///< SDA pin number.
+ nrf_twi_frequency_t frequency; ///< TWI frequency.
+ uint8_t interrupt_priority; ///< Interrupt priority.
+ bool hold_bus_uninit; ///< Hold pull up state on GPIO pins after uninit.
} nrfx_twi_config_t;
-/**
- * @brief TWI master driver instance default configuration.
- */
+/** @brief The default configuration of the TWI master driver instance. */
#define NRFX_TWI_DEFAULT_CONFIG \
{ \
.frequency = (nrf_twi_frequency_t)NRFX_TWI_DEFAULT_CONFIG_FREQUENCY, \
@@ -98,33 +95,32 @@ typedef struct
.hold_bus_uninit = NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT, \
}
-#define NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */
-#define NRFX_TWI_FLAG_TX_NO_STOP (1UL << 5) /**< Flag indicating that the TX transfer will not end with a stop condition. */
+/** @brief Flag indicating that the interrupt after each transfer will be suppressed, and the event handler will not be called. */
+#define NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2)
+/** @brief Flag indicating that the TX transfer will not end with a stop condition. */
+#define NRFX_TWI_FLAG_TX_NO_STOP (1UL << 5)
+/** @brief Flag indicating that the transfer will be suspended. */
+#define NRFX_TWI_FLAG_SUSPEND (1UL << 6)
-/**
- * @brief TWI master driver event types.
- */
+/** @brief TWI master driver event types. */
typedef enum
{
NRFX_TWI_EVT_DONE, ///< Transfer completed event.
NRFX_TWI_EVT_ADDRESS_NACK, ///< Error event: NACK received after sending the address.
- NRFX_TWI_EVT_DATA_NACK ///< Error event: NACK received after sending a data byte.
+ NRFX_TWI_EVT_DATA_NACK, ///< Error event: NACK received after sending a data byte.
+ NRFX_TWI_EVT_OVERRUN ///< Error event: The unread data is replaced by new data.
} nrfx_twi_evt_type_t;
-/**
- * @brief TWI master driver transfer types.
- */
+/** @brief TWI master driver transfer types. */
typedef enum
{
- NRFX_TWI_XFER_TX, ///< TX transfer.
- NRFX_TWI_XFER_RX, ///< RX transfer.
- NRFX_TWI_XFER_TXRX, ///< TX transfer followed by RX transfer with repeated start.
- NRFX_TWI_XFER_TXTX ///< TX transfer followed by TX transfer with repeated start.
+ NRFX_TWI_XFER_TX, ///< TX transfer.
+ NRFX_TWI_XFER_RX, ///< RX transfer.
+ NRFX_TWI_XFER_TXRX, ///< TX transfer followed by RX transfer with repeated start.
+ NRFX_TWI_XFER_TXTX ///< TX transfer followed by TX transfer with repeated start.
} nrfx_twi_xfer_type_t;
-/**
- * @brief Structure for a TWI transfer descriptor.
- */
+/** @brief Structure for a TWI transfer descriptor. */
typedef struct
{
nrfx_twi_xfer_type_t type; ///< Type of transfer.
@@ -136,72 +132,72 @@ typedef struct
} nrfx_twi_xfer_desc_t;
-/**@brief Macro for setting the TX transfer descriptor. */
+/** @brief Macro for setting the TX transfer descriptor. */
#define NRFX_TWI_XFER_DESC_TX(addr, p_data, length) \
- { \
- .type = NRFX_TWI_XFER_TX, \
- .address = addr, \
- .primary_length = length, \
- .p_primary_buf = p_data, \
- }
+{ \
+ .type = NRFX_TWI_XFER_TX, \
+ .address = (addr), \
+ .primary_length = (length), \
+ .secondary_length = 0, \
+ .p_primary_buf = (p_data), \
+ .p_secondary_buf = NULL, \
+}
-/**@brief Macro for setting the RX transfer descriptor. */
+/** @brief Macro for setting the RX transfer descriptor. */
#define NRFX_TWI_XFER_DESC_RX(addr, p_data, length) \
- { \
- .type = NRFX_TWI_XFER_RX, \
- .address = addr, \
- .primary_length = length, \
- .p_primary_buf = p_data, \
- }
+{ \
+ .type = NRFX_TWI_XFER_RX, \
+ .address = (addr), \
+ .primary_length = (length), \
+ .secondary_length = 0, \
+ .p_primary_buf = (p_data), \
+ .p_secondary_buf = NULL, \
+}
-/**@brief Macro for setting the TXRX transfer descriptor. */
-#define NRFX_TWI_XFER_DESC_TXRX(addr, p_tx, tx_len, p_rx, rx_len) \
- { \
- .type = NRFX_TWI_XFER_TXRX, \
- .address = addr, \
- .primary_length = tx_len, \
- .secondary_length = rx_len, \
- .p_primary_buf = p_tx, \
- .p_secondary_buf = p_rx, \
- }
+/** @brief Macro for setting the TX-RX transfer descriptor. */
+#define NRFX_TWI_XFER_DESC_TXRX(addr, p_tx, tx_len, p_rx, rx_len) \
+{ \
+ .type = NRFX_TWI_XFER_TXRX, \
+ .address = (addr), \
+ .primary_length = (tx_len), \
+ .secondary_length = (rx_len), \
+ .p_primary_buf = (p_tx), \
+ .p_secondary_buf = (p_rx), \
+}
-/**@brief Macro for setting the TXTX transfer descriptor. */
+/** @brief Macro for setting the TX-TX transfer descriptor. */
#define NRFX_TWI_XFER_DESC_TXTX(addr, p_tx, tx_len, p_tx2, tx_len2) \
- { \
- .type = NRFX_TWI_XFER_TXTX, \
- .address = addr, \
- .primary_length = tx_len, \
- .secondary_length = tx_len2, \
- .p_primary_buf = p_tx, \
- .p_secondary_buf = p_tx2, \
- }
+{ \
+ .type = NRFX_TWI_XFER_TXTX, \
+ .address = (addr), \
+ .primary_length = (tx_len), \
+ .secondary_length = (tx_len2), \
+ .p_primary_buf = (p_tx), \
+ .p_secondary_buf = (p_tx2), \
+}
-/**
- * @brief Structure for a TWI event.
- */
+/** @brief Structure for a TWI event. */
typedef struct
{
nrfx_twi_evt_type_t type; ///< Event type.
nrfx_twi_xfer_desc_t xfer_desc; ///< Transfer details.
} nrfx_twi_evt_t;
-/**
- * @brief TWI event handler prototype.
- */
+/** @brief TWI event handler prototype. */
typedef void (* nrfx_twi_evt_handler_t)(nrfx_twi_evt_t const * p_event,
void * p_context);
/**
* @brief Function for initializing the TWI driver instance.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_config Pointer to the structure with initial configuration.
- * @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled.
- * @param[in] p_context Context passed to event handler.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ * @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled.
+ * @param[in] p_context Context passed to event handler.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver is in invalid state.
- * @retval NRFX_ERROR_BUSY If some other peripheral with the same
+ * @retval NRFX_SUCCESS Initialization is successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver is in invalid state.
+ * @retval NRFX_ERROR_BUSY Some other peripheral with the same
* instance ID is already in use. This is
* possible only if @ref nrfx_prs module
* is enabled.
@@ -238,6 +234,8 @@ void nrfx_twi_disable(nrfx_twi_t const * p_instance);
* The transmission will be stopped when an error occurs. If a transfer is ongoing,
* the function returns the error code @ref NRFX_ERROR_BUSY.
*
+ * @note This function is deprecated. Use @ref nrfx_twi_xfer instead.
+ *
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] address Address of a specific slave device (only 7 LSB).
* @param[in] p_data Pointer to a transmit buffer.
@@ -246,11 +244,14 @@ void nrfx_twi_disable(nrfx_twi_t const * p_instance);
* after the transfer has completed successfully (allowing
* for a repeated start in the next transfer).
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
- * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware.
- * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode.
- * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_BUSY The driver is not ready for a new transfer.
+ * @retval NRFX_ERROR_INTERNAL An error is detected by hardware.
+ * @retval NRFX_ERROR_INVALID_STATE RX transaction is suspended on bus.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK Negative acknowledgement (NACK) is received after sending
+ * the address in polling mode.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK Negative acknowledgement (NACK) is received after sending
+ * a data byte in polling mode.
*/
nrfx_err_t nrfx_twi_tx(nrfx_twi_t const * p_instance,
uint8_t address,
@@ -264,53 +265,64 @@ nrfx_err_t nrfx_twi_tx(nrfx_twi_t const * p_instance,
* The transmission will be stopped when an error occurs. If a transfer is ongoing,
* the function returns the error code @ref NRFX_ERROR_BUSY.
*
+ * @note This function is deprecated. Use @ref nrfx_twi_xfer instead.
+ *
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] address Address of a specific slave device (only 7 LSB).
* @param[in] p_data Pointer to a receive buffer.
* @param[in] length Number of bytes to be received.
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
- * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware.
- * @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN If the unread data was replaced by new data
- * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode.
- * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_BUSY The driver is not ready for a new transfer.
+ * @retval NRFX_ERROR_INTERNAL An error is detected by hardware.
+ * @retval NRFX_ERROR_INVALID_STATE TX transaction is suspended on bus.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN The unread data is replaced by new data.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK Negative acknowledgement (NACK) is received after sending
+ * the address in polling mode.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK Negative acknowledgement (NACK) is received after sending
+ * a data byte in polling mode.
*/
nrfx_err_t nrfx_twi_rx(nrfx_twi_t const * p_instance,
uint8_t address,
uint8_t * p_data,
size_t length);
+
/**
- * @brief Function for preparing a TWI transfer.
+ * @brief Function for performing a TWI transfer.
*
* The following transfer types can be configured (@ref nrfx_twi_xfer_desc_t::type):
- * - @ref NRFX_TWI_XFER_TXRX : Write operation followed by a read operation (without STOP condition in between).
- * - @ref NRFX_TWI_XFER_TXTX : Write operation followed by a write operation (without STOP condition in between).
- * - @ref NRFX_TWI_XFER_TX : Write operation (with or without STOP condition).
- * - @ref NRFX_TWI_XFER_RX : Read operation (with STOP condition).
+ * - @ref NRFX_TWI_XFER_TXRX - Write operation followed by a read operation (without STOP condition in between).
+ * - @ref NRFX_TWI_XFER_TXTX - Write operation followed by a write operation (without STOP condition in between).
+ * - @ref NRFX_TWI_XFER_TX - Write operation (with or without STOP condition).
+ * - @ref NRFX_TWI_XFER_RX - Read operation (with STOP condition).
*
- * @note TXRX and TXTX transfers are supported only in non-blocking mode.
+ * @note TX-RX and TX-TX transfers are supported only in non-blocking mode.
*
* Additional options are provided using the flags parameter:
- * - @ref NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER : No user event handler after transfer completion. In most cases, this also means no interrupt at the end of the transfer.
- * - @ref NRFX_TWI_FLAG_TX_NO_STOP : No stop condition after TX transfer.
+ * - @ref NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER - No user event handler after transfer completion. In most cases, this also means no interrupt at the end of the transfer.
+ * - @ref NRFX_TWI_FLAG_TX_NO_STOP - No stop condition after TX transfer.
+ * - @ref NRFX_TWI_FLAG_SUSPEND - Transfer will be suspended. This allows for combining multiple transfers into one transaction.
+ * Only transactions with the same direction can be combined. To finish the transaction, call the function without this flag.
*
* @note
* Some flag combinations are invalid:
* - @ref NRFX_TWI_FLAG_TX_NO_STOP with @ref nrfx_twi_xfer_desc_t::type different than @ref NRFX_TWI_XFER_TX
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_xfer_desc Pointer to the transfer descriptor.
- * @param[in] flags Transfer options (0 for default settings).
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_xfer_desc Pointer to the transfer descriptor.
+ * @param[in] flags Transfer options (0 for default settings).
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
- * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported.
- * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware.
- * @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN If the unread data was replaced by new data (TXRX and RX)
- * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address.
- * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_BUSY The driver is not ready for a new transfer.
+ * @retval NRFX_ERROR_NOT_SUPPORTED The provided parameters are not supported.
+ * @retval NRFX_ERROR_INTERNAL An error is detected by hardware.
+ * @retval NRFX_ERROR_INVALID_STATE Other direction of transaction is suspended on the bus.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN The unread data is replaced by new data (TXRX and RX)
+ * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK Negative acknowledgement (NACK) is received after sending
+ * the address in polling mode.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK Negative acknowledgement (NACK) is received after sending
+ * a data byte in polling mode.
*/
nrfx_err_t nrfx_twi_xfer(nrfx_twi_t const * p_instance,
nrfx_twi_xfer_desc_t const * p_xfer_desc,
@@ -321,8 +333,8 @@ nrfx_err_t nrfx_twi_xfer(nrfx_twi_t const * p_instance,
*
* @param[in] p_instance TWI instance.
*
- * @retval true If the TWI driver is currently busy performing a transfer.
- * @retval false If the TWI driver is ready for a new transfer.
+ * @retval true The TWI driver is currently busy performing a transfer.
+ * @retval false The TWI driver is ready for a new transfer.
*/
bool nrfx_twi_is_busy(nrfx_twi_t const * p_instance);
@@ -331,7 +343,7 @@ bool nrfx_twi_is_busy(nrfx_twi_t const * p_instance);
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @return Data count.
+ * @return Data count.
*/
size_t nrfx_twi_data_count_get(nrfx_twi_t const * const p_instance);
@@ -341,16 +353,42 @@ size_t nrfx_twi_data_count_get(nrfx_twi_t const * const p_instance);
* A STOPPED event can be used to detect the end of a transfer if the @ref NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER
* option is used.
*
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*
- * @return STOPPED event address.
+ * @return STOPPED event address.
*/
uint32_t nrfx_twi_stopped_event_get(nrfx_twi_t const * p_instance);
+/**
+ * @brief Function for recovering the bus.
+ *
+ * This function checks if the bus is not stuck because of a slave holding the SDA line in the low state,
+ * and if needed it performs required number of pulses on the SCL line to make the slave release the SDA line.
+ * Finally, the function generates a STOP condition on the bus to put it into a known state.
+ *
+ * @note This function can be used only if the TWI driver is uninitialized.
+ *
+ * @param[in] scl_pin SCL pin number.
+ * @param[in] sda_pin SDA pin number.
+ *
+ * @retval NRFX_SUCCESS Bus recovery was successful.
+ * @retval NRFX_ERROR_INTERNAL Bus recovery failed.
+ */
+__STATIC_INLINE nrfx_err_t nrfx_twi_bus_recover(uint32_t scl_pin, uint32_t sda_pin);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE nrfx_err_t nrfx_twi_bus_recover(uint32_t scl_pin, uint32_t sda_pin)
+{
+ return nrfx_twi_twim_bus_recover(scl_pin, sda_pin);
+}
+#endif
+
+/** @} */
+
+
void nrfx_twi_0_irq_handler(void);
void nrfx_twi_1_irq_handler(void);
-/** @} */
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi_twim.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi_twim.h
new file mode 100644
index 000000000..1c6ebcd74
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twi_twim.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_TWI_TWIM_H
+#define NRFX_TWI_TWIM_H
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+nrfx_err_t nrfx_twi_twim_bus_recover(uint32_t scl_pin, uint32_t sda_pin);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_TWI_TWIM_H
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twim.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twim.h
index 73aa4451f..2ef1dfdad 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twim.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twim.h
@@ -33,6 +33,7 @@
#define NRFX_TWIM_H__
#include
+#include
#include
#ifdef __cplusplus
@@ -43,27 +44,24 @@ extern "C" {
* @defgroup nrfx_twim TWIM driver
* @{
* @ingroup nrf_twim
- * @brief TWIM peripheral driver.
+ * @brief Two Wire Interface Master with EasyDMA (TWIM) peripheral driver.
*/
-/**
- * @brief Structure for the TWI master driver instance.
- */
+/** @brief Structure for the TWI master driver instance. */
typedef struct
{
NRF_TWIM_Type * p_twim; ///< Pointer to a structure with TWIM registers.
- uint8_t drv_inst_idx; ///< Driver instance index.
+ uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only.
} nrfx_twim_t;
-/**
- * @brief Macro for creating a TWI master driver instance.
- */
+/** @brief Macro for creating a TWI master driver instance. */
#define NRFX_TWIM_INSTANCE(id) \
{ \
.p_twim = NRFX_CONCAT_2(NRF_TWIM, id), \
.drv_inst_idx = NRFX_CONCAT_3(NRFX_TWIM, id, _INST_IDX), \
}
+#ifndef __NRFX_DOXYGEN__
enum {
#if NRFX_CHECK(NRFX_TWIM0_ENABLED)
NRFX_TWIM0_INST_IDX,
@@ -79,139 +77,138 @@ enum {
#endif
NRFX_TWIM_ENABLED_COUNT
};
+#endif
-/**
- * @brief Structure for the TWI master driver instance configuration.
- */
+/** @brief Structure for the TWI master driver instance configuration. */
typedef struct
{
- uint32_t scl; ///< SCL pin number.
- uint32_t sda; ///< SDA pin number.
- nrf_twim_frequency_t frequency; ///< TWIM frequency.
- uint8_t interrupt_priority; ///< Interrupt priority.
- bool hold_bus_uninit; ///< Hold pull up state on gpio pins after uninit.
+ uint32_t scl; ///< SCL pin number.
+ uint32_t sda; ///< SDA pin number.
+ nrf_twim_frequency_t frequency; ///< TWIM frequency.
+ uint8_t interrupt_priority; ///< Interrupt priority.
+ bool hold_bus_uninit; ///< Hold pull up state on GPIO pins after uninit.
} nrfx_twim_config_t;
-/**
- * @brief TWI master driver instance default configuration.
- */
+/** @brief TWI master driver instance default configuration. */
#define NRFX_TWIM_DEFAULT_CONFIG \
{ \
- .frequency = (nrf_twim_frequency_t)NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY, \
.scl = 31, \
.sda = 31, \
+ .frequency = (nrf_twim_frequency_t)NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY, \
.interrupt_priority = NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY, \
.hold_bus_uninit = NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT, \
}
-#define NRFX_TWIM_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */
-#define NRFX_TWIM_FLAG_RX_POSTINC (1UL << 1) /**< RX buffer address incremented after transfer. */
-#define NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */
-#define NRFX_TWIM_FLAG_HOLD_XFER (1UL << 3) /**< Set up the transfer but do not start it. */
-#define NRFX_TWIM_FLAG_REPEATED_XFER (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */
-#define NRFX_TWIM_FLAG_TX_NO_STOP (1UL << 5) /**< Flag indicating that the TX transfer will not end with a stop condition. */
+/** @brief Flag indicating that TX buffer address will be incremented after the transfer. */
+#define NRFX_TWIM_FLAG_TX_POSTINC (1UL << 0)
+/** @brief Flag indicating that RX buffer address will be incremented after the transfer. */
+#define NRFX_TWIM_FLAG_RX_POSTINC (1UL << 1)
+/** @brief Flag indicating that the interrupt after each transfer will be suppressed, and the event handler will not be called. */
+#define NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2)
+/** @brief Flag indicating that the transfer will be set up, but not started. */
+#define NRFX_TWIM_FLAG_HOLD_XFER (1UL << 3)
+/** @brief Flag indicating that the transfer will be executed multiple times. */
+#define NRFX_TWIM_FLAG_REPEATED_XFER (1UL << 4)
+/** @brief Flag indicating that the TX transfer will not end with a stop condition. */
+#define NRFX_TWIM_FLAG_TX_NO_STOP (1UL << 5)
-/**
- * @brief TWI master driver event types.
- */
+/** @brief TWI master driver event types. */
typedef enum
{
NRFX_TWIM_EVT_DONE, ///< Transfer completed event.
NRFX_TWIM_EVT_ADDRESS_NACK, ///< Error event: NACK received after sending the address.
- NRFX_TWIM_EVT_DATA_NACK ///< Error event: NACK received after sending a data byte.
+ NRFX_TWIM_EVT_DATA_NACK, ///< Error event: NACK received after sending a data byte.
+ NRFX_TWIM_EVT_OVERRUN, ///< Error event: The unread data is replaced by new data.
+ NRFX_TWIM_EVT_BUS_ERROR ///< Error event: An unexpected transition occurred on the bus.
} nrfx_twim_evt_type_t;
-/**
- * @brief TWI master driver transfer types.
- */
+/** @brief TWI master driver transfer types. */
typedef enum
{
- NRFX_TWIM_XFER_TX, ///< TX transfer.
- NRFX_TWIM_XFER_RX, ///< RX transfer.
- NRFX_TWIM_XFER_TXRX, ///< TX transfer followed by RX transfer with repeated start.
- NRFX_TWIM_XFER_TXTX ///< TX transfer followed by TX transfer with repeated start.
+ NRFX_TWIM_XFER_TX, ///< TX transfer.
+ NRFX_TWIM_XFER_RX, ///< RX transfer.
+ NRFX_TWIM_XFER_TXRX, ///< TX transfer followed by RX transfer with repeated start.
+ NRFX_TWIM_XFER_TXTX ///< TX transfer followed by TX transfer with repeated start.
} nrfx_twim_xfer_type_t;
-/**
- * @brief Structure for a TWI transfer descriptor.
- */
+/** @brief Structure for a TWI transfer descriptor. */
typedef struct
{
- nrfx_twim_xfer_type_t type; ///< Type of transfer.
- uint8_t address; ///< Slave address.
- size_t primary_length; ///< Number of bytes transferred.
- size_t secondary_length; ///< Number of bytes transferred.
- uint8_t * p_primary_buf; ///< Pointer to transferred data.
- uint8_t * p_secondary_buf; ///< Pointer to transferred data.
+ nrfx_twim_xfer_type_t type; ///< Type of transfer.
+ uint8_t address; ///< Slave address.
+ size_t primary_length; ///< Number of bytes transferred.
+ size_t secondary_length; ///< Number of bytes transferred.
+ uint8_t * p_primary_buf; ///< Pointer to transferred data.
+ uint8_t * p_secondary_buf; ///< Pointer to transferred data.
} nrfx_twim_xfer_desc_t;
-/**@brief Macro for setting the TX transfer descriptor. */
+/** @brief Macro for setting the TX transfer descriptor. */
#define NRFX_TWIM_XFER_DESC_TX(addr, p_data, length) \
- { \
- .type = NRFX_TWIM_XFER_TX, \
- .address = addr, \
- .primary_length = length, \
- .p_primary_buf = p_data, \
- }
+{ \
+ .type = NRFX_TWIM_XFER_TX, \
+ .address = (addr), \
+ .primary_length = (length), \
+ .secondary_length = 0, \
+ .p_primary_buf = (p_data), \
+ .p_secondary_buf = NULL, \
+}
-/**@brief Macro for setting the RX transfer descriptor. */
+/** @brief Macro for setting the RX transfer descriptor. */
#define NRFX_TWIM_XFER_DESC_RX(addr, p_data, length) \
- { \
- .type = NRFX_TWIM_XFER_RX, \
- .address = addr, \
- .primary_length = length, \
- .p_primary_buf = p_data, \
- }
+{ \
+ .type = NRFX_TWIM_XFER_RX, \
+ .address = (addr), \
+ .primary_length = (length), \
+ .secondary_length = 0, \
+ .p_primary_buf = (p_data), \
+ .p_secondary_buf = NULL, \
+}
-/**@brief Macro for setting the TXRX transfer descriptor. */
+/** @brief Macro for setting the TX-RX transfer descriptor. */
#define NRFX_TWIM_XFER_DESC_TXRX(addr, p_tx, tx_len, p_rx, rx_len) \
- { \
- .type = NRFX_TWIM_XFER_TXRX, \
- .address = addr, \
- .primary_length = tx_len, \
- .secondary_length = rx_len, \
- .p_primary_buf = p_tx, \
- .p_secondary_buf = p_rx, \
- }
+{ \
+ .type = NRFX_TWIM_XFER_TXRX, \
+ .address = (addr), \
+ .primary_length = (tx_len), \
+ .secondary_length = (rx_len), \
+ .p_primary_buf = (p_tx), \
+ .p_secondary_buf = (p_rx), \
+}
-/**@brief Macro for setting the TXTX transfer descriptor. */
+/** @brief Macro for setting the TX-TX transfer descriptor. */
#define NRFX_TWIM_XFER_DESC_TXTX(addr, p_tx, tx_len, p_tx2, tx_len2) \
- { \
- .type = NRFX_TWIM_XFER_TXTX, \
- .address = addr, \
- .primary_length = tx_len, \
- .secondary_length = tx_len2, \
- .p_primary_buf = p_tx, \
- .p_secondary_buf = p_tx2, \
- }
+{ \
+ .type = NRFX_TWIM_XFER_TXTX, \
+ .address = (addr), \
+ .primary_length = (tx_len), \
+ .secondary_length = (tx_len2), \
+ .p_primary_buf = (p_tx), \
+ .p_secondary_buf = (p_tx2), \
+}
-/**
- * @brief Structure for a TWI event.
- */
+/** @brief Structure for a TWI event. */
typedef struct
{
nrfx_twim_evt_type_t type; ///< Event type.
nrfx_twim_xfer_desc_t xfer_desc; ///< Transfer details.
} nrfx_twim_evt_t;
-/**
- * @brief TWI event handler prototype.
- */
+/** @brief TWI event handler prototype. */
typedef void (* nrfx_twim_evt_handler_t)(nrfx_twim_evt_t const * p_event,
void * p_context);
/**
* @brief Function for initializing the TWI driver instance.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_config Pointer to the structure with initial configuration.
- * @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled.
- * @param[in] p_context Context passed to event handler.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ * @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled.
+ * @param[in] p_context Context passed to event handler.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver is in invalid state.
- * @retval NRFX_ERROR_BUSY If some other peripheral with the same
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver is in invalid state.
+ * @retval NRFX_ERROR_BUSY Some other peripheral with the same
* instance ID is already in use. This is
* possible only if @ref nrfx_prs module
* is enabled.
@@ -248,9 +245,11 @@ void nrfx_twim_disable(nrfx_twim_t const * p_instance);
* The transmission will be stopped when an error occurs. If a transfer is ongoing,
* the function returns the error code @ref NRFX_ERROR_BUSY.
*
+ * @note This function is deprecated. Use @ref nrfx_twim_xfer instead.
+ *
* @note Peripherals using EasyDMA (including TWIM) require the transfer buffers
* to be placed in the Data RAM region. If this condition is not met,
- * this function will fail with the error code NRFX_ERROR_INVALID_ADDR.
+ * this function fails with the error code NRFX_ERROR_INVALID_ADDR.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] address Address of a specific slave device (only 7 LSB).
@@ -263,12 +262,12 @@ void nrfx_twim_disable(nrfx_twim_t const * p_instance);
* after the transfer has completed successfully (allowing
* for a repeated start in the next transfer).
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
- * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware.
- * @retval NRFX_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region.
- * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode.
- * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_BUSY The driver is not ready for a new transfer.
+ * @retval NRFX_ERROR_INTERNAL An unexpected transition occurred on the bus.
+ * @retval NRFX_ERROR_INVALID_ADDR The provided buffer is not placed in the Data RAM region.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK NACK is received after sending the address in polling mode.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK NACK is received after sending a data byte in polling mode.
*/
nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance,
uint8_t address,
@@ -282,6 +281,8 @@ nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance,
* The transmission will be stopped when an error occurs. If a transfer is ongoing,
* the function returns the error code @ref NRFX_ERROR_BUSY.
*
+ * @note This function is deprecated. Use @ref nrfx_twim_xfer instead.
+ *
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] address Address of a specific slave device (only 7 LSB).
* @param[in] p_data Pointer to a receive buffer.
@@ -290,11 +291,12 @@ nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance,
* description in the Product Specification). The driver
* checks it with assertion.
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
- * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware.
- * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode.
- * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_BUSY The driver is not ready for a new transfer.
+ * @retval NRFX_ERROR_INTERNAL An unexpected transition occurred on the bus.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN The unread data is replaced by new data.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK NACK is received after sending the address in polling mode.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK NACK is received after sending a data byte in polling mode.
*/
nrfx_err_t nrfx_twim_rx(nrfx_twim_t const * p_instance,
uint8_t address,
@@ -302,29 +304,29 @@ nrfx_err_t nrfx_twim_rx(nrfx_twim_t const * p_instance,
size_t length);
/**
- * @brief Function for preparing a TWI transfer.
+ * @brief Function for performing a TWI transfer.
*
* The following transfer types can be configured (@ref nrfx_twim_xfer_desc_t::type):
- * - @ref NRFX_TWIM_XFER_TXRX : Write operation followed by a read operation (without STOP condition in between).
- * - @ref NRFX_TWIM_XFER_TXTX : Write operation followed by a write operation (without STOP condition in between).
- * - @ref NRFX_TWIM_XFER_TX : Write operation (with or without STOP condition).
- * - @ref NRFX_TWIM_XFER_RX : Read operation (with STOP condition).
+ * - @ref NRFX_TWIM_XFER_TXRX - Write operation followed by a read operation (without STOP condition in between).
+ * - @ref NRFX_TWIM_XFER_TXTX - Write operation followed by a write operation (without STOP condition in between).
+ * - @ref NRFX_TWIM_XFER_TX - Write operation (with or without STOP condition).
+ * - @ref NRFX_TWIM_XFER_RX - Read operation (with STOP condition).
*
- * @note TXRX and TXTX transfers are supported only in non-blocking mode.
+ * @note TX-RX and TX-TX transfers are supported only in non-blocking mode.
*
* Additional options are provided using the flags parameter:
- * - @ref NRFX_TWIM_FLAG_TX_POSTINC and @ref NRFX_TWIM_FLAG_RX_POSTINC : Post-incrementation of buffer addresses. Supported only by TWIM.
- * - @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER : No user event handler after transfer completion. In most cases, this also means no interrupt at the end of the transfer.
- * - @ref NRFX_TWIM_FLAG_HOLD_XFER : Driver is not starting the transfer. Use this flag if the transfer is triggered externally by PPI. Supported only by TWIM.
+ * - @ref NRFX_TWIM_FLAG_TX_POSTINC and @ref NRFX_TWIM_FLAG_RX_POSTINC - Post-incrementation of buffer addresses.
+ * - @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER - No user event handler after the transfer completion. In most cases, this also means no interrupt at the end of the transfer.
+ * - @ref NRFX_TWIM_FLAG_HOLD_XFER - Driver is not starting the transfer. Use this flag if the transfer is triggered externally by PPI.
* Use @ref nrfx_twim_start_task_get to get the address of the start task.
- * - @ref NRFX_TWIM_FLAG_REPEATED_XFER : Prepare for repeated transfers. You can set up a number of transfers that will be triggered externally (for example by PPI).
+ * - @ref NRFX_TWIM_FLAG_REPEATED_XFER - Prepare for repeated transfers. You can set up a number of transfers that will be triggered externally (for example by PPI).
* An example is a TXRX transfer with the options @ref NRFX_TWIM_FLAG_RX_POSTINC, @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER, and @ref NRFX_TWIM_FLAG_REPEATED_XFER.
* After the transfer is set up, a set of transfers can be triggered by PPI that will read, for example, the same register of an
* external component and put it into a RAM buffer without any interrupts. @ref nrfx_twim_stopped_event_get can be used to get the
* address of the STOPPED event, which can be used to count the number of transfers. If @ref NRFX_TWIM_FLAG_REPEATED_XFER is used,
* the driver does not set the driver instance into busy state, so you must ensure that the next transfers are set up
- * when TWIM is not active. Supported only by TWIM.
- * - @ref NRFX_TWIM_FLAG_TX_NO_STOP : No stop condition after TX transfer.
+ * when TWIM is not active.
+ * - @ref NRFX_TWIM_FLAG_TX_NO_STOP - No stop condition after the TX transfer.
*
* @note
* Some flag combinations are invalid:
@@ -339,17 +341,18 @@ nrfx_err_t nrfx_twim_rx(nrfx_twim_t const * p_instance,
* to be placed in the Data RAM region. If this condition is not met,
* this function will fail with the error code NRFX_ERROR_INVALID_ADDR.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_xfer_desc Pointer to the transfer descriptor.
- * @param[in] flags Transfer options (0 for default settings).
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_xfer_desc Pointer to the transfer descriptor.
+ * @param[in] flags Transfer options (0 for default settings).
*
- * @retval NRFX_SUCCESS If the procedure was successful.
- * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
- * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported.
- * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware.
- * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data RAM region.
- * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address.
- * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte.
+ * @retval NRFX_SUCCESS The procedure is successful.
+ * @retval NRFX_ERROR_BUSY The driver is not ready for a new transfer.
+ * @retval NRFX_ERROR_NOT_SUPPORTED The provided parameters are not supported.
+ * @retval NRFX_ERROR_INTERNAL An unexpected transition occurred on the bus.
+ * @retval NRFX_ERROR_INVALID_ADDR The provided buffers are not placed in the Data RAM region.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN The unread data is replaced by new data.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK NACK is received after sending the address.
+ * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK NACK is received after sending a data byte.
*/
nrfx_err_t nrfx_twim_xfer(nrfx_twim_t const * p_instance,
nrfx_twim_xfer_desc_t const * p_xfer_desc,
@@ -360,8 +363,8 @@ nrfx_err_t nrfx_twim_xfer(nrfx_twim_t const * p_instance,
*
* @param[in] p_instance TWI instance.
*
- * @retval true If the TWI driver is currently busy performing a transfer.
- * @retval false If the TWI driver is ready for a new transfer.
+ * @retval true The TWI driver is currently busy performing a transfer.
+ * @retval false The TWI driver is ready for a new transfer.
*/
bool nrfx_twim_is_busy(nrfx_twim_t const * p_instance);
@@ -369,13 +372,13 @@ bool nrfx_twim_is_busy(nrfx_twim_t const * p_instance);
/**
* @brief Function for returning the address of a TWIM start task.
*
- * This function should be used if @ref nrfx_twim_xfer was called with the flag @ref NRFX_TWIM_FLAG_HOLD_XFER.
+ * This function is to be used if @ref nrfx_twim_xfer was called with the flag @ref NRFX_TWIM_FLAG_HOLD_XFER.
* In that case, the transfer is not started by the driver, but it must be started externally by PPI.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] xfer_type Transfer type used in the last call of the @ref nrfx_twim_xfer function.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] xfer_type Transfer type used in the last call of the @ref nrfx_twim_xfer function.
*
- * @return Start task address (TX or RX) depending on the value of xfer_type.
+ * @return Start task address (TX or RX) depending on the value of xfer_type.
*/
uint32_t nrfx_twim_start_task_get(nrfx_twim_t const * p_instance, nrfx_twim_xfer_type_t xfer_type);
@@ -385,12 +388,37 @@ uint32_t nrfx_twim_start_task_get(nrfx_twim_t const * p_instance, nrfx_twim_xfer
* A STOPPED event can be used to detect the end of a transfer if the @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER
* option is used.
*
- * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_instance Pointer to the driver instance structure.
*
- * @return STOPPED event address.
+ * @return STOPPED event address.
*/
uint32_t nrfx_twim_stopped_event_get(nrfx_twim_t const * p_instance);
+/**
+ * @brief Function for recovering the bus.
+ *
+ * This function checks if the bus is not stuck because of a slave holding the SDA line in the low state,
+ * and if needed it performs required number of pulses on the SCL line to make the slave release the SDA line.
+ * Finally, the function generates a STOP condition on the bus to put it into a known state.
+ *
+ * @note This function can be used only if the TWIM driver is uninitialized.
+ *
+ * @param[in] scl_pin SCL pin number.
+ * @param[in] sda_pin SDA pin number.
+ *
+ * @retval NRFX_SUCCESS Bus recovery was successful.
+ * @retval NRFX_ERROR_INTERNAL Bus recovery failed.
+ */
+__STATIC_INLINE nrfx_err_t nrfx_twim_bus_recover(uint32_t scl_pin, uint32_t sda_pin);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE nrfx_err_t nrfx_twim_bus_recover(uint32_t scl_pin, uint32_t sda_pin)
+{
+ return nrfx_twi_twim_bus_recover(scl_pin, sda_pin);
+}
+#endif
+
+/** @} */
void nrfx_twim_0_irq_handler(void);
void nrfx_twim_1_irq_handler(void);
@@ -398,8 +426,6 @@ void nrfx_twim_2_irq_handler(void);
void nrfx_twim_3_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twis.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twis.h
index a9ba5fbae..4c3d0cac3 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twis.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_twis.h
@@ -44,18 +44,17 @@ extern "C" {
* @defgroup nrfx_twis TWIS driver
* @{
* @ingroup nrf_twis
- * @brief Two Wire Slave interface (TWIS) peripheral driver.
+ * @brief Two Wire Interface Slave with EasyDMA (TWIS) peripheral driver.
*/
-/**
- * @brief TWIS driver instance data structure.
- */
+/** @brief TWIS driver instance data structure. */
typedef struct
{
NRF_TWIS_Type * p_reg; ///< Pointer to a structure with TWIS registers.
- uint8_t drv_inst_idx; ///< Driver instance index.
+ uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only.
} nrfx_twis_t;
+#ifndef __NRFX_DOXYGEN__
enum {
#if NRFX_CHECK(NRFX_TWIS0_ENABLED)
NRFX_TWIS0_INST_IDX,
@@ -71,32 +70,29 @@ enum {
#endif
NRFX_TWIS_ENABLED_COUNT
};
+#endif
-/**
- * @brief Macro for creating a TWIS driver instance.
- */
+/** @brief Macro for creating a TWIS driver instance. */
#define NRFX_TWIS_INSTANCE(id) \
{ \
.p_reg = NRFX_CONCAT_2(NRF_TWIS, id), \
.drv_inst_idx = NRFX_CONCAT_3(NRFX_TWIS, id, _INST_IDX), \
}
-/**
- * @brief Event callback function event definitions.
- */
+/** @brief Event callback function event definitions. */
typedef enum
{
NRFX_TWIS_EVT_READ_REQ, ///< Read request detected.
/**< If there is no buffer prepared, buf_req flag in the even will be set.
Call then @ref nrfx_twis_tx_prepare to give parameters for buffer.
*/
- NRFX_TWIS_EVT_READ_DONE, ///< Read request has finished - free any data.
+ NRFX_TWIS_EVT_READ_DONE, ///< Read request finished - free any data.
NRFX_TWIS_EVT_READ_ERROR, ///< Read request finished with error.
NRFX_TWIS_EVT_WRITE_REQ, ///< Write request detected.
/**< If there is no buffer prepared, buf_req flag in the even will be set.
Call then @ref nrfx_twis_rx_prepare to give parameters for buffer.
*/
- NRFX_TWIS_EVT_WRITE_DONE, ///< Write request has finished - process data.
+ NRFX_TWIS_EVT_WRITE_DONE, ///< Write request finished - process data.
NRFX_TWIS_EVT_WRITE_ERROR, ///< Write request finished with error.
NRFX_TWIS_EVT_GENERAL_ERROR ///< Error that happens not inside WRITE or READ transaction.
} nrfx_twis_evt_type_t;
@@ -106,7 +102,7 @@ typedef enum
*
* This is flag enum - values from this enum can be connected using logical or operator.
* @note
- * We could use directly @ref nrf_twis_error_t. Error type enum is redefined here because
+ * You can use directly @ref nrf_twis_error_t. Error type enum is redefined here because
* of possible future extension (eg. supporting timeouts and synchronous mode).
*/
typedef enum
@@ -117,9 +113,7 @@ typedef enum
NRFX_TWIS_ERROR_UNEXPECTED_EVENT = 1 << 8 /**< Unexpected event detected by state machine. */
} nrfx_twis_error_t;
-/**
- * @brief TWIS driver event structure.
- */
+/** @brief TWIS driver event structure. */
typedef struct
{
nrfx_twis_evt_type_t type; ///< Event type.
@@ -130,7 +124,7 @@ typedef struct
uint32_t tx_amount; ///< Data for @ref NRFX_TWIS_EVT_READ_DONE.
uint32_t rx_amount; ///< Data for @ref NRFX_TWIS_EVT_WRITE_DONE.
uint32_t error; ///< Data for @ref NRFX_TWIS_EVT_GENERAL_ERROR.
- } data;
+ } data; ///< Union to store event data.
} nrfx_twis_evt_t;
/**
@@ -140,9 +134,7 @@ typedef struct
*/
typedef void (*nrfx_twis_event_handler_t)(nrfx_twis_evt_t const * p_event);
-/**
- * @brief Structure for TWIS configuration.
- */
+/** @brief Structure for TWIS configuration. */
typedef struct
{
uint32_t addr[2]; //!< Set addresses that this slave should respond. Set 0 to disable.
@@ -150,19 +142,17 @@ typedef struct
uint32_t sda; //!< SDA pin number.
nrf_gpio_pin_pull_t scl_pull; //!< SCL pin pull.
nrf_gpio_pin_pull_t sda_pull; //!< SDA pin pull.
- uint8_t interrupt_priority; //!< The priority of interrupt for the module to set.
+ uint8_t interrupt_priority; //!< The priority of interrupt for the module to be set.
} nrfx_twis_config_t;
-/**
- * @brief Generate default configuration for TWIS driver instance.
- */
-#define NRFX_TWIS_DEFAULT_CONFIG \
-{ \
+/** @brief Generate the default configuration for the TWIS driver instance. */
+#define NRFX_TWIS_DEFAULT_CONFIG \
+{ \
.addr = { NRFX_TWIS_DEFAULT_CONFIG_ADDR0, \
NRFX_TWIS_DEFAULT_CONFIG_ADDR1 }, \
.scl = 31, \
- .scl_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL, \
.sda = 31, \
+ .scl_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL, \
.sda_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL, \
.interrupt_priority = NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY \
}
@@ -170,19 +160,19 @@ typedef struct
/**
* @brief Function for initializing the TWIS driver instance.
*
- * Function initializes and enables TWIS driver.
- * @attention After driver initialization enable it by @ref nrfx_twis_enable.
+ * Function initializes and enables the TWIS driver.
+ * @attention After driver initialization enable it with @ref nrfx_twis_enable.
*
- * @param[in] p_instance Pointer to the driver instance structure.
- * @attention @em p_instance has to be global object.
- * It would be used by interrupts so make it sure that object
- * would not be destroyed when function is leaving.
- * @param[in] p_config Pointer to the structure with initial configuration.
- * @param[in] event_handler Event handler provided by the user.
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @attention @em p_instance has to be global object.
+ * It will be used by interrupts so make it sure that object
+ * is not destroyed when function is leaving.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ * @param[in] event_handler Event handler provided by the user.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized.
- * @retval NRFX_ERROR_BUSY If some other peripheral with the same
+ * @retval NRFX_SUCCESS Initialization is successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver is already initialized.
+ * @retval NRFX_ERROR_BUSY Some other peripheral with the same
* instance ID is already in use. This is
* possible only if NRFX_PRS_ENABLED
* is set to a value other than zero.
@@ -194,24 +184,25 @@ nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance,
/**
* @brief Function for uninitializing the TWIS driver instance.
*
- * Function initializes the peripheral and resets all registers to default values.
+ * Function uninitializes the peripheral and resets all registers to default values.
*
- * @param[in] p_instance Pointer to the driver instance structure.
* @note
* It is safe to call nrfx_twis_uninit even before initialization.
- * Actually @ref nrfx_twis_init function calls this function to
+ * Actually, @ref nrfx_twis_init function calls this function to
* make sure that TWIS state is known.
* @note
* If TWIS driver was in uninitialized state before calling this function,
- * selected pins would not be reset to default configuration.
+ * the selected pins would not be reset to default configuration.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_twis_uninit(nrfx_twis_t const * p_instance);
/**
- * @brief Enable TWIS instance.
+ * @brief Function for enabling the TWIS instance.
*
- * This function enables TWIS instance.
- * Function defined if there is needs for dynamically enabling and disabling the peripheral.
+ * This function enables the TWIS instance.
+ * Function defined if there is need for dynamically enabling and disabling the peripheral.
* Use @ref nrfx_twis_enable and @ref nrfx_twis_disable functions.
* They do not change any configuration registers.
*
@@ -220,9 +211,9 @@ void nrfx_twis_uninit(nrfx_twis_t const * p_instance);
void nrfx_twis_enable(nrfx_twis_t const * p_instance);
/**
- * @brief Disable TWIS instance.
+ * @brief Function for disabling the TWIS instance.
*
- * Disabling TWIS instance gives possibility to turn off the TWIS while
+ * This function disables the TWIS instance, which gives possibility to turn off the TWIS while
* holding configuration done by @ref nrfx_twis_init.
*
* @param p_instance Pointer to the driver instance structure.
@@ -230,47 +221,47 @@ void nrfx_twis_enable(nrfx_twis_t const * p_instance);
void nrfx_twis_disable(nrfx_twis_t const * p_instance);
/**
- * @brief Get and clear last error flags.
+ * @brief Function for getting and clearing the last error flags.
*
- * Function gets information about errors.
- * This is also the only possibility to exit from error substate of the internal state machine.
- *
- * @param[in] p_instance Pointer to the driver instance structure.
- * @return Error flags defined in @ref nrfx_twis_error_t.
+ * This function gets the information about errors.
+ * This is also the only possibility to exit from the error substate of the internal state machine.
* @attention
* This function clears error state and flags.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @return Error flags defined in @ref nrfx_twis_error_t.
*/
uint32_t nrfx_twis_error_get_and_clear(nrfx_twis_t const * p_instance);
-
/**
- * @brief Prepare data for sending.
+ * @brief Function for preparing the data for sending.
*
- * This function should be used in response for @ref NRFX_TWIS_EVT_READ_REQ event.
+ * This function is to be used in response to the @ref NRFX_TWIS_EVT_READ_REQ event.
*
* @note Peripherals using EasyDMA (including TWIS) require the transfer buffers
* to be placed in the Data RAM region. If this condition is not met,
* this function will fail with the error code NRFX_ERROR_INVALID_ADDR.
+ * @attention Transmission buffer must be placed in RAM.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_buf Transmission buffer.
- * @attention Transmission buffer has to be placed in RAM.
- * @param size Maximum number of bytes that master may read from buffer given.
+ * @param[in] size Maximum number of bytes that master may read from buffer given.
*
- * @retval NRFX_SUCCESS Preparation finished properly.
- * @retval NRFX_ERROR_INVALID_ADDR Given @em p_buf is not placed inside the RAM.
- * @retval NRFX_ERROR_INVALID_LENGTH Wrong value in @em size parameter.
- * @retval NRFX_ERROR_INVALID_STATE Module not initialized or not enabled.
+ * @retval NRFX_SUCCESS The preparation finished properly.
+ * @retval NRFX_ERROR_INVALID_ADDR The given @em p_buf is not placed inside the RAM.
+ * @retval NRFX_ERROR_INVALID_LENGTH There is a wrong value in the @em size parameter.
+ * @retval NRFX_ERROR_INVALID_STATE The module is not initialized or not enabled.
*/
nrfx_err_t nrfx_twis_tx_prepare(nrfx_twis_t const * p_instance,
void const * p_buf,
size_t size);
/**
- * @brief Get number of transmitted bytes.
+ * @brief Function for getting the number of transmitted bytes.
*
- * Function returns number of bytes sent.
- * This function may be called after @ref NRFX_TWIS_EVT_READ_DONE or @ref NRFX_TWIS_EVT_READ_ERROR events.
+ * This function returns the number of bytes sent.
+ * This function can be called after @ref NRFX_TWIS_EVT_READ_DONE or @ref NRFX_TWIS_EVT_READ_ERROR events.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
@@ -279,33 +270,32 @@ nrfx_err_t nrfx_twis_tx_prepare(nrfx_twis_t const * p_instance,
__STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance);
/**
- * @brief Prepare data for receiving
+ * @brief Function for preparing the data for receiving.
*
- * This function should be used in response for @ref NRFX_TWIS_EVT_WRITE_REQ event.
+ * This function must be used in response to the @ref NRFX_TWIS_EVT_WRITE_REQ event.
*
* @note Peripherals using EasyDMA (including TWIS) require the transfer buffers
* to be placed in the Data RAM region. If this condition is not met,
- * this function will fail with the error code NRFX_ERROR_INVALID_ADDR.
+ * this function fails with the error code NRFX_ERROR_INVALID_ADDR.
*
* @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_buf Buffer that would be filled with received data.
- * @attention Receiving buffer has to be placed in RAM.
- * @param size Size of the buffer (maximum amount of data to receive).
+ * @param[in] p_buf Buffer that is to be filled with received data.
+ * @param[in] size Size of the buffer (maximum amount of data to receive).
*
- * @retval NRFX_SUCCESS Preparation finished properly.
- * @retval NRFX_ERROR_INVALID_ADDR Given @em p_buf is not placed inside the RAM.
- * @retval NRFX_ERROR_INVALID_LENGTH Wrong value in @em size parameter.
- * @retval NRFX_ERROR_INVALID_STATE Module not initialized or not enabled.
+ * @retval NRFX_SUCCESS The preparation finished properly.
+ * @retval NRFX_ERROR_INVALID_ADDR The given @em p_buf is not placed inside the RAM.
+ * @retval NRFX_ERROR_INVALID_LENGTH There is a wrong value in the @em size parameter.
+ * @retval NRFX_ERROR_INVALID_STATE The module is not initialized or not enabled.
*/
nrfx_err_t nrfx_twis_rx_prepare(nrfx_twis_t const * p_instance,
void * p_buf,
size_t size);
/**
- * @brief Get number of received bytes.
+ * @brief Function for getting the number of received bytes.
*
- * Function returns number of bytes received.
- * This function may be called after @ref NRFX_TWIS_EVT_WRITE_DONE or @ref NRFX_TWIS_EVT_WRITE_ERROR events.
+ * This function returns number of bytes received.
+ * It can be called after @ref NRFX_TWIS_EVT_WRITE_DONE or @ref NRFX_TWIS_EVT_WRITE_ERROR events.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
@@ -314,65 +304,65 @@ nrfx_err_t nrfx_twis_rx_prepare(nrfx_twis_t const * p_instance,
__STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance);
/**
- * @brief Function checks if driver is busy right now.
+ * @brief Function for checking if the driver is busy right now.
*
- * Actual driver substate is tested.
- * If driver is in any other state than IDLE or ERROR this function returns true.
+ * This function tests the actual driver substate.
+ * If the driver is in any other state than IDLE or ERROR, this function returns true.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval true Driver is in state other than ERROR or IDLE.
+ * @retval true The driver is in state other than ERROR or IDLE.
* @retval false There is no transmission pending.
*/
bool nrfx_twis_is_busy(nrfx_twis_t const * p_instance);
/**
- * @brief Function checks if driver is waiting for tx buffer.
+ * @brief Function for checking if the driver is waiting for a TX buffer.
*
- * If this function returns true, it means that driver is stalled expecting
+ * If this function returns true, the driver is stalled expecting
* of the @ref nrfx_twis_tx_prepare function call.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval true Driver waits for @ref nrfx_twis_tx_prepare.
- * @retval false Driver is not in the state where it waits for preparing tx buffer.
+ * @retval true The driver is waiting for @ref nrfx_twis_tx_prepare.
+ * @retval false The driver is not in the state where it is waiting for preparing a TX buffer.
*/
bool nrfx_twis_is_waiting_tx_buff(nrfx_twis_t const * p_instance);
/**
- * @brief Function checks if driver is waiting for rx buffer.
+ * @brief Function for checking if the driver is waiting for an RX buffer.
*
- * If this function returns true, it means that driver is staled expecting
+ * If this function returns true, the driver is stalled expecting
* of the @ref nrfx_twis_rx_prepare function call.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval true Driver waits for @ref nrfx_twis_rx_prepare.
- * @retval false Driver is not in the state where it waits for preparing rx buffer.
+ * @retval true The driver is waiting for @ref nrfx_twis_rx_prepare.
+ * @retval false The driver is not in the state where it is waiting for preparing an RX buffer.
*/
bool nrfx_twis_is_waiting_rx_buff(nrfx_twis_t const * p_instance);
/**
- * @brief Check if driver is sending data.
+ * @brief Function for checking if the driver is sending data.
*
- * If this function returns true, it means that there is ongoing output transmission.
+ * If this function returns true, there is an ongoing output transmission.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval true There is ongoing output transmission.
- * @retval false Driver is in other state.
+ * @retval true There is an ongoing output transmission.
+ * @retval false The driver is in other state.
*/
bool nrfx_twis_is_pending_tx(nrfx_twis_t const * p_instance);
/**
- * @brief Check if driver is receiving data.
+ * @brief Function for checking if the driver is receiving data.
*
- * If this function returns true, it means that there is ongoing input transmission.
+ * If this function returns true, there is an ongoing input transmission.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval true There is ongoing input transmission.
- * @retval false Driver is in other state.
+ * @retval true There is an ongoing input transmission.
+ * @retval false The driver is in other state.
*/
bool nrfx_twis_is_pending_rx(nrfx_twis_t const * p_instance);
@@ -388,6 +378,8 @@ __STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance)
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
void nrfx_twis_0_irq_handler(void);
void nrfx_twis_1_irq_handler(void);
@@ -395,8 +387,6 @@ void nrfx_twis_2_irq_handler(void);
void nrfx_twis_3_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uart.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uart.h
index adbb9d375..a96df3ccb 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uart.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uart.h
@@ -46,34 +46,30 @@ extern "C" {
* @brief UART peripheral driver.
*/
-/**
- * @brief UART driver instance data structure.
- */
+/** @brief Data structure of the UART driver instance. */
typedef struct
{
NRF_UART_Type * p_reg; ///< Pointer to a structure with UART registers.
- uint8_t drv_inst_idx; ///< Driver instance index.
+ uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only.
} nrfx_uart_t;
+#ifndef __NRFX_DOXYGEN__
enum {
#if NRFX_CHECK(NRFX_UART0_ENABLED)
NRFX_UART0_INST_IDX,
#endif
NRFX_UART_ENABLED_COUNT
};
+#endif
-/**
- * @brief Macro for creating a UART driver instance.
- */
+/** @brief Macro for creating a UART driver instance. */
#define NRFX_UART_INSTANCE(id) \
{ \
.p_reg = NRFX_CONCAT_2(NRF_UART, id), \
.drv_inst_idx = NRFX_CONCAT_3(NRFX_UART, id, _INST_IDX), \
}
-/**
- * @brief Types of UART driver events.
- */
+/** @brief Types of UART driver events. */
typedef enum
{
NRFX_UART_EVT_TX_DONE, ///< Requested TX transfer completed.
@@ -81,9 +77,7 @@ typedef enum
NRFX_UART_EVT_ERROR, ///< Error reported by UART peripheral.
} nrfx_uart_evt_type_t;
-/**
- * @brief Structure for UART configuration.
- */
+/** @brief Structure for the UART configuration. */
typedef struct
{
uint32_t pseltxd; ///< TXD pin number.
@@ -93,13 +87,11 @@ typedef struct
void * p_context; ///< Context passed to interrupt handler.
nrf_uart_hwfc_t hwfc; ///< Flow control configuration.
nrf_uart_parity_t parity; ///< Parity configuration.
- nrf_uart_baudrate_t baudrate; ///< Baudrate.
+ nrf_uart_baudrate_t baudrate; ///< Baud rate.
uint8_t interrupt_priority; ///< Interrupt priority.
} nrfx_uart_config_t;
-/**
- * @brief UART default configuration.
- */
+/** @brief UART default configuration. */
#define NRFX_UART_DEFAULT_CONFIG \
{ \
.pseltxd = NRF_UART_PSEL_DISCONNECTED, \
@@ -113,27 +105,21 @@ typedef struct
.interrupt_priority = NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY, \
}
-/**
- * @brief Structure for UART transfer completion event.
- */
+/** @brief Structure for the UART transfer completion event. */
typedef struct
{
uint8_t * p_data; ///< Pointer to memory used for transfer.
uint32_t bytes; ///< Number of bytes transfered.
} nrfx_uart_xfer_evt_t;
-/**
- * @brief Structure for UART error event.
- */
+/** @brief Structure for the UART error event. */
typedef struct
{
- nrfx_uart_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transferred.
+ nrfx_uart_xfer_evt_t rxtx; ///< Transfer details, including number of bytes transferred.
uint32_t error_mask; ///< Mask of error flags that generated the event.
} nrfx_uart_error_evt_t;
-/**
- * @brief Structure for UART event.
- */
+/** @brief Structure for the UART event. */
typedef struct
{
nrfx_uart_evt_type_t type; ///< Event type.
@@ -141,15 +127,15 @@ typedef struct
{
nrfx_uart_xfer_evt_t rxtx; ///< Data provided for transfer completion events.
nrfx_uart_error_evt_t error; ///< Data provided for error event.
- } data;
+ } data; ///< Union to store event data.
} nrfx_uart_event_t;
/**
* @brief UART interrupt event handler.
*
- * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available
- * only within the context of the event handler.
- * @param[in] p_context Context passed to interrupt handler, set on initialization.
+ * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available
+ * only within the context of the event handler.
+ * @param[in] p_context Context passed to the interrupt handler, set on initialization.
*/
typedef void (*nrfx_uart_event_handler_t)(nrfx_uart_event_t const * p_event,
void * p_context);
@@ -160,45 +146,46 @@ typedef void (*nrfx_uart_event_handler_t)(nrfx_uart_event_t const * p_event,
* This function configures and enables UART. After this function GPIO pins are controlled by UART.
*
* @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_config Pointer to the structure with initial configuration.
- * @param[in] event_handler Event handler provided by the user. If not provided driver works in
+ * @param[in] p_config Pointer to the structure with the initial configuration.
+ * @param[in] event_handler Event handler provided by the user. If not provided, the driver works in
* blocking mode.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If driver is already initialized.
- * @retval NRFX_ERROR_BUSY If some other peripheral with the same
- * instance ID is already in use. This is
- * possible only if @ref nrfx_prs module
- * is enabled.
+ * @retval NRFX_SUCCESS Initialization is successful.
+ * @retval NRFX_ERROR_INVALID_STATE The driver is already initialized.
+ * @retval NRFX_ERROR_BUSY Some other peripheral with the same
+ * instance ID is already in use. This is
+ * possible only if @ref nrfx_prs module
+ * is enabled.
*/
nrfx_err_t nrfx_uart_init(nrfx_uart_t const * p_instance,
nrfx_uart_config_t const * p_config,
nrfx_uart_event_handler_t event_handler);
/**
- * @brief Function for uninitializing the UART driver.
+ * @brief Function for uninitializing the UART driver.
+ *
* @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_uart_uninit(nrfx_uart_t const * p_instance);
/**
- * @brief Function for getting the address of a specific UART task.
+ * @brief Function for getting the address of the specified UART task.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] task Task.
*
- * @return Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrfx_uart_task_address_get(nrfx_uart_t const * p_instance,
nrf_uart_task_t task);
/**
- * @brief Function for getting the address of a specific UART event.
+ * @brief Function for getting the address of the specified UART event.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] event Event.
*
- * @return Event address.
+ * @return Event address.
*/
__STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_instance,
nrf_uart_event_t event);
@@ -208,7 +195,7 @@ __STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_insta
*
* If an event handler was provided in nrfx_uart_init() call, this function
* returns immediately and the handler is called when the transfer is done.
- * Otherwise, the transfer is performed in blocking mode, i.e. this function
+ * Otherwise, the transfer is performed in blocking mode, that is this function
* returns when the transfer is finished. Blocking mode is not using interrupt
* so there is no context switching inside the function.
*
@@ -216,10 +203,10 @@ __STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_insta
* @param[in] p_data Pointer to data.
* @param[in] length Number of bytes to send.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_BUSY If driver is already transferring.
- * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context
- * (blocking mode only).
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_BUSY Driver is already transferring.
+ * @retval NRFX_ERROR_FORBIDDEN The transfer was aborted from a different context
+ * (blocking mode only).
*/
nrfx_err_t nrfx_uart_tx(nrfx_uart_t const * p_instance,
uint8_t const * p_data,
@@ -230,15 +217,15 @@ nrfx_err_t nrfx_uart_tx(nrfx_uart_t const * p_instance,
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval true If UART is transmitting.
- * @retval false If UART is not transmitting.
+ * @retval true The UART is transmitting.
+ * @retval false The UART is not transmitting.
*/
bool nrfx_uart_tx_in_progress(nrfx_uart_t const * p_instance);
/**
* @brief Function for aborting any ongoing transmission.
* @note @ref NRFX_UART_EVT_TX_DONE event will be generated in non-blocking mode.
- * It will contain number of bytes sent until abort was called. The event
+ * It will contain number of bytes sent until the abort was called. The event
* handler will be called from the function context.
*
* @param[in] p_instance Pointer to the driver instance structure.
@@ -248,15 +235,14 @@ void nrfx_uart_tx_abort(nrfx_uart_t const * p_instance);
/**
* @brief Function for receiving data over UART.
*
- * If an event handler was provided in the nrfx_uart_init() call, this function
+ * If an event handler is provided in the nrfx_uart_init() call, this function
* returns immediately and the handler is called when the transfer is done.
- * Otherwise, the transfer is performed in blocking mode, meaning that this function
+ * Otherwise, the transfer is performed in blocking mode, that is this function
* returns when the transfer is finished. Blocking mode is not using interrupt so
* there is no context switching inside the function.
- *
- * The receive buffer pointer is double buffered in non-blocking mode. The secondary
+ * The receive buffer pointer is double-buffered in non-blocking mode. The secondary
* buffer can be set immediately after starting the transfer and will be filled
- * when the primary buffer is full. The double buffering feature allows
+ * when the primary buffer is full. The double-buffering feature allows
* receiving data continuously.
*
* If this function is used without a previous call to @ref nrfx_uart_rx_enable, the reception
@@ -272,28 +258,26 @@ void nrfx_uart_tx_abort(nrfx_uart_t const * p_instance);
* @param[in] p_data Pointer to data.
* @param[in] length Number of bytes to receive.
*
- * @retval NRFX_SUCCESS If reception is complete (in case of blocking mode) or it is
+ * @retval NRFX_SUCCESS Reception is complete (in case of blocking mode) or it is
* successfully started (in case of non-blocking mode).
- * @retval NRFX_ERROR_BUSY If the driver is already receiving
+ * @retval NRFX_ERROR_BUSY The driver is already receiving
* (and the secondary buffer has already been set
* in non-blocking mode).
- * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context
+ * @retval NRFX_ERROR_FORBIDDEN The transfer was aborted from a different context
* (blocking mode only, also see @ref nrfx_uart_rx_disable).
- * @retval NRFX_ERROR_INTERNAL If UART peripheral reported an error.
+ * @retval NRFX_ERROR_INTERNAL The UART peripheral reported an error.
*/
nrfx_err_t nrfx_uart_rx(nrfx_uart_t const * p_instance,
uint8_t * p_data,
size_t length);
-
-
/**
* @brief Function for testing the receiver state in blocking mode.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval true If the receiver has at least one byte of data to get.
- * @retval false If the receiver is empty.
+ * @retval true The receiver has at least one byte of data to get.
+ * @retval false The receiver is empty.
*/
bool nrfx_uart_rx_ready(nrfx_uart_t const * p_instance);
@@ -321,7 +305,7 @@ void nrfx_uart_rx_disable(nrfx_uart_t const * p_instance);
/**
* @brief Function for aborting any ongoing reception.
* @note @ref NRFX_UART_EVT_TX_DONE event will be generated in non-blocking mode.
- * It will contain number of bytes received until abort was called. The event
+ * It will contain number of bytes received until the abort was called. The event
* handler will be called from the UART interrupt context.
*
* @param[in] p_instance Pointer to the driver instance structure.
@@ -330,12 +314,12 @@ void nrfx_uart_rx_abort(nrfx_uart_t const * p_instance);
/**
* @brief Function for reading error source mask. Mask contains values from @ref nrf_uart_error_mask_t.
- * @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is
+ * @note Function must be used in blocking mode only. In case of non-blocking mode, an error event is
* generated. Function clears error sources after reading.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval Mask of reported errors.
+ * @return Mask of reported errors.
*/
uint32_t nrfx_uart_errorsrc_get(nrfx_uart_t const * p_instance);
@@ -354,12 +338,12 @@ __STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_insta
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
void nrfx_uart_0_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uarte.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uarte.h
index da767cd28..b5eb109ca 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uarte.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_uarte.h
@@ -46,15 +46,14 @@ extern "C" {
* @brief UARTE peripheral driver.
*/
-/**
- * @brief Structure for the UARTE driver instance.
- */
+/** @brief Structure for the UARTE driver instance. */
typedef struct
{
NRF_UARTE_Type * p_reg; ///< Pointer to a structure with UARTE registers.
- uint8_t drv_inst_idx; ///< Driver instance index.
+ uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only.
} nrfx_uarte_t;
+#ifndef __NRFX_DOXYGEN__
enum {
#if NRFX_CHECK(NRFX_UARTE0_ENABLED)
NRFX_UARTE0_INST_IDX,
@@ -70,19 +69,16 @@ enum {
#endif
NRFX_UARTE_ENABLED_COUNT
};
+#endif
-/**
- * @brief Macro for creating a UARTE driver instance.
- */
+/** @brief Macro for creating a UARTE driver instance. */
#define NRFX_UARTE_INSTANCE(id) \
{ \
.p_reg = NRFX_CONCAT_2(NRF_UARTE, id), \
.drv_inst_idx = NRFX_CONCAT_3(NRFX_UARTE, id, _INST_IDX), \
}
-/**
- * @brief Types of UARTE driver events.
- */
+/** @brief Types of UARTE driver events. */
typedef enum
{
NRFX_UARTE_EVT_TX_DONE, ///< Requested TX transfer completed.
@@ -90,9 +86,7 @@ typedef enum
NRFX_UARTE_EVT_ERROR, ///< Error reported by UART peripheral.
} nrfx_uarte_evt_type_t;
-/**
- * @brief Structure for UARTE configuration.
- */
+/** @brief Structure for the UARTE configuration. */
typedef struct
{
uint32_t pseltxd; ///< TXD pin number.
@@ -102,13 +96,11 @@ typedef struct
void * p_context; ///< Context passed to interrupt handler.
nrf_uarte_hwfc_t hwfc; ///< Flow control configuration.
nrf_uarte_parity_t parity; ///< Parity configuration.
- nrf_uarte_baudrate_t baudrate; ///< Baudrate.
+ nrf_uarte_baudrate_t baudrate; ///< Baud rate.
uint8_t interrupt_priority; ///< Interrupt priority.
} nrfx_uarte_config_t;
-/**
- * @brief UARTE default configuration.
- */
+/** @brief UARTE default configuration. */
#define NRFX_UARTE_DEFAULT_CONFIG \
{ \
.pseltxd = NRF_UARTE_PSEL_DISCONNECTED, \
@@ -122,27 +114,21 @@ typedef struct
.interrupt_priority = NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY, \
}
-/**
- * @brief Structure for UARTE transfer completion event.
- */
+/** @brief Structure for the UARTE transfer completion event. */
typedef struct
{
uint8_t * p_data; ///< Pointer to memory used for transfer.
size_t bytes; ///< Number of bytes transfered.
} nrfx_uarte_xfer_evt_t;
-/**
- * @brief Structure for UARTE error event.
- */
+/** @brief Structure for UARTE error event. */
typedef struct
{
- nrfx_uarte_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transferred.
+ nrfx_uarte_xfer_evt_t rxtx; ///< Transfer details, including number of bytes transferred.
uint32_t error_mask; ///< Mask of error flags that generated the event.
} nrfx_uarte_error_evt_t;
-/**
- * @brief Structure for UARTE event.
- */
+/** @brief Structure for UARTE event. */
typedef struct
{
nrfx_uarte_evt_type_t type; ///< Event type.
@@ -150,15 +136,15 @@ typedef struct
{
nrfx_uarte_xfer_evt_t rxtx; ///< Data provided for transfer completion events.
nrfx_uarte_error_evt_t error; ///< Data provided for error event.
- } data;
+ } data; ///< Union to store event data.
} nrfx_uarte_event_t;
/**
* @brief UARTE interrupt event handler.
*
- * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available
- * only within the context of the event handler.
- * @param[in] p_context Context passed to interrupt handler, set on initialization.
+ * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available
+ * only within the context of the event handler.
+ * @param[in] p_context Context passed to the interrupt handler, set on initialization.
*/
typedef void (*nrfx_uarte_event_handler_t)(nrfx_uarte_event_t const * p_event,
void * p_context);
@@ -169,45 +155,46 @@ typedef void (*nrfx_uarte_event_handler_t)(nrfx_uarte_event_t const * p_event,
* This function configures and enables UARTE. After this function GPIO pins are controlled by UARTE.
*
* @param[in] p_instance Pointer to the driver instance structure.
- * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] event_handler Event handler provided by the user. If not provided driver works in
* blocking mode.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_INVALID_STATE If driver is already initialized.
- * @retval NRFX_ERROR_BUSY If some other peripheral with the same
- * instance ID is already in use. This is
- * possible only if @ref nrfx_prs module
- * is enabled.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_INVALID_STATE Driver is already initialized.
+ * @retval NRFX_ERROR_BUSY Some other peripheral with the same
+ * instance ID is already in use. This is
+ * possible only if @ref nrfx_prs module
+ * is enabled.
*/
nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance,
nrfx_uarte_config_t const * p_config,
nrfx_uarte_event_handler_t event_handler);
/**
- * @brief Function for uninitializing the UARTE driver.
+ * @brief Function for uninitializing the UARTE driver.
+ *
* @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance);
/**
- * @brief Function for getting the address of a specific UARTE task.
+ * @brief Function for getting the address of the specified UARTE task.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] task Task.
*
- * @return Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrfx_uarte_task_address_get(nrfx_uarte_t const * p_instance,
nrf_uarte_task_t task);
/**
- * @brief Function for getting the address of a specific UARTE event.
+ * @brief Function for getting the address of the specified UARTE event.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] event Event.
*
- * @return Event address.
+ * @return Event address.
*/
__STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_instance,
nrf_uarte_event_t event);
@@ -215,9 +202,9 @@ __STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_ins
/**
* @brief Function for sending data over UARTE.
*
- * If an event handler was provided in nrfx_uarte_init() call, this function
+ * If an event handler is provided in nrfx_uarte_init() call, this function
* returns immediately and the handler is called when the transfer is done.
- * Otherwise, the transfer is performed in blocking mode, i.e. this function
+ * Otherwise, the transfer is performed in blocking mode, that is this function
* returns when the transfer is finished. Blocking mode is not using interrupt
* so there is no context switching inside the function.
*
@@ -232,11 +219,11 @@ __STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_ins
* description in the Product Specification). The driver
* checks it with assertion.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_BUSY If driver is already transferring.
- * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context
- * (blocking mode only).
- * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer.
+ * @retval NRFX_SUCCESS Initialization was successful.
+ * @retval NRFX_ERROR_BUSY Driver is already transferring.
+ * @retval NRFX_ERROR_FORBIDDEN The transfer was aborted from a different context
+ * (blocking mode only).
+ * @retval NRFX_ERROR_INVALID_ADDR p_data does not point to RAM buffer.
*/
nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance,
uint8_t const * p_data,
@@ -247,16 +234,16 @@ nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance,
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval true If UARTE is transmitting.
- * @retval false If UARTE is not transmitting.
+ * @retval true The UARTE is transmitting.
+ * @retval false The UARTE is not transmitting.
*/
bool nrfx_uarte_tx_in_progress(nrfx_uarte_t const * p_instance);
/**
* @brief Function for aborting any ongoing transmission.
* @note @ref NRFX_UARTE_EVT_TX_DONE event will be generated in non-blocking mode.
- * It will contain number of bytes sent until abort was called. The event
- * handler will be called from UARTE interrupt context.
+ * It will contain number of bytes sent until the abort was called. The event
+ * handler will be called from the UARTE interrupt context.
*
* @param[in] p_instance Pointer to the driver instance structure.
*/
@@ -265,19 +252,19 @@ void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance);
/**
* @brief Function for receiving data over UARTE.
*
- * If an event handler was provided in the nrfx_uarte_init() call, this function
+ * If an event handler is provided in the nrfx_uarte_init() call, this function
* returns immediately and the handler is called when the transfer is done.
- * Otherwise, the transfer is performed in blocking mode, i.e. this function
+ * Otherwise, the transfer is performed in blocking mode, that is this function
* returns when the transfer is finished. Blocking mode is not using interrupt so
* there is no context switching inside the function.
- * The receive buffer pointer is double buffered in non-blocking mode. The secondary
+ * The receive buffer pointer is double-buffered in non-blocking mode. The secondary
* buffer can be set immediately after starting the transfer and will be filled
- * when the primary buffer is full. The double buffering feature allows
+ * when the primary buffer is full. The double-buffering feature allows
* receiving data continuously.
*
* @note Peripherals using EasyDMA (including UARTE) require the transfer buffers
* to be placed in the Data RAM region. If this condition is not met,
- * this function will fail with the error code NRFX_ERROR_INVALID_ADDR.
+ * this function fails with the error code NRFX_ERROR_INVALID_ADDR.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_data Pointer to data.
@@ -286,14 +273,14 @@ void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance);
* description in the Product Specification). The driver
* checks it with assertion.
*
- * @retval NRFX_SUCCESS If initialization was successful.
- * @retval NRFX_ERROR_BUSY If the driver is already receiving
- * (and the secondary buffer has already been set
- * in non-blocking mode).
- * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context
- * (blocking mode only).
- * @retval NRFX_ERROR_INTERNAL If UARTE peripheral reported an error.
- * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer.
+ * @retval NRFX_SUCCESS Initialization is successful.
+ * @retval NRFX_ERROR_BUSY The driver is already receiving
+ * (and the secondary buffer has already been set
+ * in non-blocking mode).
+ * @retval NRFX_ERROR_FORBIDDEN The transfer is aborted from a different context
+ * (blocking mode only).
+ * @retval NRFX_ERROR_INTERNAL The UARTE peripheral reports an error.
+ * @retval NRFX_ERROR_INVALID_ADDR p_data does not point to RAM buffer.
*/
nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance,
uint8_t * p_data,
@@ -306,16 +293,16 @@ nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance,
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval true If the receiver has at least one byte of data to get.
- * @retval false If the receiver is empty.
+ * @retval true The receiver has at least one byte of data to get.
+ * @retval false The receiver is empty.
*/
bool nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance);
/**
* @brief Function for aborting any ongoing reception.
* @note @ref NRFX_UARTE_EVT_RX_DONE event will be generated in non-blocking mode.
- * It will contain number of bytes received until abort was called. The event
- * handler will be called from UARTE interrupt context.
+ * It will contain number of bytes received until the abort was called. The event
+ * handler will be called from the UARTE interrupt context.
*
* @param[in] p_instance Pointer to the driver instance structure.
*/
@@ -323,12 +310,12 @@ void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance);
/**
* @brief Function for reading error source mask. Mask contains values from @ref nrf_uarte_error_mask_t.
- * @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is
+ * @note Function must be used in the blocking mode only. In case of non-blocking mode, an error event is
* generated. Function clears error sources after reading.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
- * @retval Mask of reported errors.
+ * @return Mask of reported errors.
*/
uint32_t nrfx_uarte_errorsrc_get(nrfx_uarte_t const * p_instance);
@@ -347,13 +334,14 @@ __STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_ins
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
void nrfx_uarte_0_irq_handler(void);
void nrfx_uarte_1_irq_handler(void);
void nrfx_uarte_2_irq_handler(void);
void nrfx_uarte_3_irq_handler(void);
-/** @} */
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_usbd.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_usbd.h
index 0b2aa3f60..ec34c55b2 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_usbd.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_usbd.h
@@ -169,7 +169,7 @@ typedef enum
NRFX_USBD_EP_ABORTED, /**< EP0 transfer can be aborted when new setup comes.
* Any other transfer can be aborted by USB reset or driver stopping.
*/
- NRFX_USBD_EP_BUSY, /**< A transfer is in progress. */
+ NRFX_USBD_EP_BUSY, /**< Transfer is in progress. */
} nrfx_usbd_ep_status_t;
/**
@@ -179,12 +179,12 @@ typedef enum
*/
typedef struct
{
- nrfx_usbd_event_type_t type;
+ nrfx_usbd_event_type_t type; /**< Event type. */
union
{
struct {
- uint16_t framecnt; /**< Current value of frame counter. */
- } sof; /**< Data available for @ref NRFX_USBD_EVT_SOF. */
+ uint16_t framecnt; /**< Current value of frame counter. */
+ } sof; /**< Data available for @ref NRFX_USBD_EVT_SOF. */
struct {
nrfx_usbd_ep_t ep; /**< Endpoint number. */
} isocrc;
@@ -192,7 +192,7 @@ typedef struct
nrfx_usbd_ep_t ep; /**< Endpoint number. */
nrfx_usbd_ep_status_t status; /**< Status for the endpoint. */
} eptransfer;
- } data;
+ } data; /**< Union to store event data. */
} nrfx_usbd_evt_t;
/**
@@ -850,12 +850,12 @@ nrfx_usbd_ep_t nrfx_usbd_last_setup_dir_get(void);
*/
void nrfx_usbd_transfer_out_drop(nrfx_usbd_ep_t ep);
+/** @} */
+
void nrfx_usbd_irq_handler(void);
-/** @} */
-
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_wdt.h b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_wdt.h
index 023ae8b7d..c3d1c6145 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_wdt.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/include/nrfx_wdt.h
@@ -47,9 +47,7 @@ extern "C" {
*/
#if !NRFX_CHECK(NRFX_WDT_CONFIG_NO_IRQ) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief WDT instance interrupt priority configuration.
- */
+/** @brief WDT instance interrupt priority configuration. */
#define NRFX_WDT_IRQ_CONFIG .interrupt_priority = NRFX_WDT_CONFIG_IRQ_PRIORITY
#else
#define NRFX_WDT_IRQ_CONFIG
@@ -65,12 +63,13 @@ typedef struct
#endif
} nrfx_wdt_config_t;
-/**@brief WDT event handler function type. */
+/** @brief WDT event handler function type. */
typedef void (*nrfx_wdt_event_handler_t)(void);
-/**@brief WDT channel id type. */
+/** @brief WDT channel ID type. */
typedef nrf_wdt_rr_register_t nrfx_wdt_channel_id;
+/** @brief WDT driver default configuration. */
#define NRFX_WDT_DEAFULT_CONFIG \
{ \
.behaviour = (nrf_wdt_behaviour_t)NRFX_WDT_CONFIG_BEHAVIOUR, \
@@ -78,80 +77,80 @@ typedef nrf_wdt_rr_register_t nrfx_wdt_channel_id;
NRFX_WDT_IRQ_CONFIG \
}
/**
- * @brief This function initializes watchdog.
+ * @brief This function initializes the watchdog.
*
- * @param[in] p_config Pointer to the structure with initial configuration.
+ * @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] wdt_event_handler Event handler provided by the user. Ignored when
* @ref NRFX_WDT_CONFIG_NO_IRQ option is enabled.
*
- * @return NRFX_SUCCESS on success, otherwise an error code.
+ * @return NRFX_SUCCESS on success, otherwise an error code.
*/
nrfx_err_t nrfx_wdt_init(nrfx_wdt_config_t const * p_config,
nrfx_wdt_event_handler_t wdt_event_handler);
/**
- * @brief This function allocate watchdog channel.
+ * @brief Function for allocating a watchdog channel.
*
* @note This function can not be called after nrfx_wdt_start(void).
*
- * @param[out] p_channel_id ID of granted channel.
+ * @param[out] p_channel_id ID of granted channel.
*
- * @return NRFX_SUCCESS on success, otherwise an error code.
+ * @return NRFX_SUCCESS on success, otherwise an error code.
*/
nrfx_err_t nrfx_wdt_channel_alloc(nrfx_wdt_channel_id * p_channel_id);
/**
- * @brief This function starts watchdog.
+ * @brief Function for starting the watchdog.
*
* @note After calling this function the watchdog is started, so the user needs to feed all allocated
- * watchdog channels to avoid reset. At least one watchdog channel has to be allocated.
+ * watchdog channels to avoid reset. At least one watchdog channel must be allocated.
*/
void nrfx_wdt_enable(void);
/**
- * @brief This function feeds the watchdog.
+ * @brief Function for feeding the watchdog.
*
* @details Function feeds all allocated watchdog channels.
*/
void nrfx_wdt_feed(void);
/**
- * @brief This function feeds the invidual watchdog channel.
+ * @brief Function for feeding an invidual watchdog channel.
*
- * @param[in] channel_id ID of watchdog channel.
+ * @param[in] channel_id ID of watchdog channel.
*/
void nrfx_wdt_channel_feed(nrfx_wdt_channel_id channel_id);
-/**@brief Function for returning a requested task address for the wdt driver module.
+/**
+ * @brief Function for returning a requested task address for the WDT driver module.
*
- * @param[in] task One of the peripheral tasks.
+ * @param[in] task One of the peripheral tasks.
*
- * @retval Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrfx_wdt_ppi_task_addr(nrf_wdt_task_t task)
{
return nrf_wdt_task_address_get(task);
}
-/**@brief Function for returning a requested event address for the wdt driver module.
+/**
+ * @brief Function for returning a requested event address for the wdt driver module.
*
- * @param[in] event One of the peripheral events.
+ * @param[in] event One of the peripheral events.
*
- * @retval Event address
+ * @return Event address.
*/
__STATIC_INLINE uint32_t nrfx_wdt_ppi_event_addr(nrf_wdt_event_t event)
{
return nrf_wdt_event_address_get(event);
}
-
-#if !NRFX_CHECK(NRFX_WDT_CONFIG_NO_IRQ)
-void nrfx_wdt_irq_handler(void);
-#endif
-
-
/** @} */
+
+void nrfx_wdt_irq_handler(void);
+
+
#ifdef __cplusplus
}
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/nrfx_common.h b/third_party/NordicSemiconductor/nrfx/drivers/nrfx_common.h
index e988a7de0..087da5ced 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/nrfx_common.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/nrfx_common.h
@@ -55,7 +55,7 @@ extern "C" {
* a non-zero value.
*
* Normally, preprocessors treat all undefined identifiers as having the value
- * zero. However, some tools, like static code analyzers, may issue a warning
+ * zero. However, some tools, like static code analyzers, can issue a warning
* when such identifier is evaluated. This macro gives the possibility to suppress
* such warnings only in places where this macro is used for evaluation, not in
* the whole analyzed code.
@@ -68,8 +68,8 @@ extern "C" {
* @note This macro is expanded in two steps so that tokens given as macros
* themselves are fully expanded before they are merged.
*
- * @param p1 First token.
- * @param p2 Second token.
+ * @param[in] p1 First token.
+ * @param[in] p2 Second token.
*
* @return The two tokens merged into one, unless they cannot together form
* a valid token (in such case, the preprocessor issues a warning and
@@ -78,10 +78,8 @@ extern "C" {
* @sa NRFX_CONCAT_3
*/
#define NRFX_CONCAT_2(p1, p2) NRFX_CONCAT_2_(p1, p2)
-/**
- * @brief Internal macro used by @ref NRFX_CONCAT_2 to perform the expansion
- * in two steps.
- */
+
+/** @brief Internal macro used by @ref NRFX_CONCAT_2 to perform the expansion in two steps. */
#define NRFX_CONCAT_2_(p1, p2) p1 ## p2
/**
@@ -90,9 +88,9 @@ extern "C" {
* @note This macro is expanded in two steps so that tokens given as macros
* themselves are fully expanded before they are merged.
*
- * @param p1 First token.
- * @param p2 Second token.
- * @param p3 Third token.
+ * @param[in] p1 First token.
+ * @param[in] p2 Second token.
+ * @param[in] p3 Third token.
*
* @return The three tokens merged into one, unless they cannot together form
* a valid token (in such case, the preprocessor issues a warning and
@@ -101,29 +99,29 @@ extern "C" {
* @sa NRFX_CONCAT_2
*/
#define NRFX_CONCAT_3(p1, p2, p3) NRFX_CONCAT_3_(p1, p2, p3)
-/**
- * @brief Internal macro used by @ref NRFX_CONCAT_3 to perform the expansion
- * in two steps.
- */
+
+/** @brief Internal macro used by @ref NRFX_CONCAT_3 to perform the expansion in two steps. */
#define NRFX_CONCAT_3_(p1, p2, p3) p1 ## p2 ## p3
-/**@brief Macro for performing rounded integer division (as opposed to
+/**
+ * @brief Macro for performing rounded integer division (as opposed to
* truncating the result).
*
- * @param a Numerator.
- * @param b Denominator.
+ * @param[in] a Numerator.
+ * @param[in] b Denominator.
*
* @return Rounded (integer) result of dividing @c a by @c b.
*/
#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b))
-/**@brief Macro for performing integer division, making sure the result is rounded up.
+/**
+ * @brief Macro for performing integer division, making sure the result is rounded up.
*
- * @details A typical use case for this macro is to compute the number of objects
+ * @details A typical use case for this macro is to compute the number of objects
* with size @c b required to hold @c a number of bytes.
*
- * @param a Numerator.
- * @param b Denominator.
+ * @param[in] a Numerator.
+ * @param[in] b Denominator.
*
* @return Integer result of dividing @c a by @c b, rounded up.
*/
@@ -132,26 +130,39 @@ extern "C" {
/**
* @brief Macro for getting the number of elements in an array.
*
- * @param array Name of the array.
+ * @param[in] array Name of the array.
*
* @return Array element count.
*/
#define NRFX_ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
+/**
+ * @brief Macro for getting the offset (in bytes) from the beginning of a structure
+ * of the specified type to its specified member.
+ *
+ * @param[in] type Structure type.
+ * @param[in] member Structure member whose offset is searched for.
+ *
+ * @return Member offset in bytes.
+ */
+#define NRFX_OFFSETOF(type, member) ((size_t)&(((type *)0)->member))
+
/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed
* the limit of the specified peripheral.
*
- * @param peripheral Peripheral to check the lengths against.
- * @param length1 First length to be checked.
- * @param length2 Second length to be checked (pass 0 if not needed).
+ * @param[in] peripheral Peripheral to check the lengths against.
+ * @param[in] length1 First length to be checked.
+ * @param[in] length2 Second length to be checked (pass 0 if not needed).
*
- * @return
+ * @retval true The length of buffers does not exceed the limit of the specified peripheral.
+ * @retval false The length of buffers exceeds the limit of the specified peripheral.
*/
#define NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, length1, length2) \
(((length1) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE))) && \
((length2) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE))))
-/**@brief Macro for waiting until condition is met.
+/**
+ * @brief Macro for waiting until condition is met.
*
* @param[in] condition Condition to meet.
* @param[in] attempts Maximum number of condition checks. Must not be 0.
@@ -180,7 +191,7 @@ do { \
* ID numbers and their base addresses. See the chapter "Peripheral interface"
* (section "Peripheral ID") in the Product Specification.
*
- * @param[in] base_addr Peripheral base address or pointer.
+ * @param[in] base_addr Peripheral base address or pointer.
*
* @return ID number associated with the specified peripheral.
*/
@@ -194,20 +205,16 @@ do { \
* equal to its ID number. See the chapter "Peripheral interface" (sections
* "Peripheral ID" and "Interrupts") in the Product Specification.
*
- * @param[in] base_addr Peripheral base address or pointer.
+ * @param[in] base_addr Peripheral base address or pointer.
*
* @return Interrupt number associated with the specified peripheral.
*/
#define NRFX_IRQ_NUMBER_GET(base_addr) NRFX_PERIPHERAL_ID_GET(base_addr)
-/**
- * @brief IRQ handler type.
- */
+/** @brief IRQ handler type. */
typedef void (* nrfx_irq_handler_t)(void);
-/**
- * @brief Driver state.
- */
+/** @brief Driver state. */
typedef enum
{
NRFX_DRV_STATE_UNINITIALIZED, ///< Uninitialized.
@@ -223,14 +230,13 @@ typedef enum
* to be placed in the Data RAM region. This function can be used to check if
* this condition is met.
*
- * @param[in] p_object Pointer to an object whose location is to be checked.
+ * @param[in] p_object Pointer to an object whose location is to be checked.
*
- * @retval true If the pointed object is located in the Data RAM region.
- * @retval false Otherwise.
+ * @retval true The pointed object is located in the Data RAM region.
+ * @retval false The pointed object is not located in the Data RAM region.
*/
__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object);
-
/**
* @brief Function for checking if an object is aligned to a 32-bit word
*
@@ -240,16 +246,15 @@ __STATIC_INLINE bool nrfx_is_in_ram(void const * p_object);
*
* @param[in] p_object Pointer to an object whose location is to be checked.
*
- * @retval true if the pointed object is aligned to a 32-bit word.
- * @retval false otherwise.
+ * @retval true The pointed object is aligned to a 32-bit word.
+ * @retval false The pointed object is not aligned to a 32-bit word.
*/
__STATIC_INLINE bool nrfx_is_word_aligned(void const * p_object);
-
/**
- * @brief Function for getting the interrupt number for a specific peripheral.
+ * @brief Function for getting the interrupt number for the specified peripheral.
*
- * @param[in] p_reg Peripheral base pointer.
+ * @param[in] p_reg Peripheral base pointer.
*
* @return Interrupt number associated with the pointed peripheral.
*/
@@ -262,8 +267,8 @@ __STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg);
* The event identifier is the offset between the event register address and
* the peripheral base address, and is equal (thus, can be directly cast) to
* the corresponding value of the enumerated type from HAL (nrf_*_event_t).
-
- * @param bit INTEN register bit position.
+ *
+ * @param[in] bit INTEN register bit position.
*
* @return Event identifier.
*
@@ -279,7 +284,7 @@ __STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit);
* the peripheral base address, and is equal (thus, can be directly cast) to
* the corresponding value of the enumerated type from HAL (nrf_*_event_t).
*
- * @param event Event identifier.
+ * @param[in] event Event identifier.
*
* @return INTEN register bit position.
*
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/nrfx_errors.h b/third_party/NordicSemiconductor/nrfx/drivers/nrfx_errors.h
index f50322701..35645fa0d 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/nrfx_errors.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/nrfx_errors.h
@@ -39,10 +39,13 @@
* @{
* @ingroup nrfx
*
- * @brief Global error codes definitions.
+ * @brief Global error code definitions.
*/
+/** @brief Base number of error codes. */
#define NRFX_ERROR_BASE_NUM 0x0BAD0000
+
+/** @brief Base number of driver error codes. */
#define NRFX_ERROR_DRIVERS_BASE_NUM (NRFX_ERROR_BASE_NUM + 0x10000)
/** @brief Enumerated type for error codes. */
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_clock.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_clock.c
index 46e38856d..1769c38e5 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_clock.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_clock.c
@@ -58,15 +58,31 @@ extern bool nrfx_power_irq_enabled;
#endif
#endif
-#if defined(NRF52810_XXAA) || \
- defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
- defined(NRF52840_XXAA)
-// Enable workaround for nRF52 anomaly 192 (LFRC oscillator frequency is wrong
-// after calibration, exceeding 500 ppm).
-#define USE_WORKAROUND_FOR_ANOMALY_192
+#if !defined(USE_WORKAROUND_FOR_ANOMALY_132) && \
+ (defined(NRF52832_XXAA) || defined(NRF52832_XXAB))
+ // ANOMALY 132 - LFCLK needs to avoid frame from 66us to 138us after LFCLK stop. This solution
+ // applies delay of 138us before starting LFCLK.
+ #define USE_WORKAROUND_FOR_ANOMALY_132 1
-// Enable workaround for nRF52 anomaly 201 (EVENTS_HFCLKSTARTED might be generated twice).
-#define USE_WORKAROUND_FOR_ANOMALY_201
+ // Convert time to cycles (nRF52832 is clocked with 64 MHz, use delay of 138 us).
+ #define ANOMALY_132_DELAY_CYCLES (64UL * 138)
+#endif
+
+#if !defined(USE_WORKAROUND_FOR_ANOMALY_192) && \
+ (defined(NRF52810_XXAA) || \
+ defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
+ defined(NRF52840_XXAA))
+ // Enable workaround for nRF52 anomaly 192 (LFRC oscillator frequency is wrong
+ // after calibration, exceeding 500 ppm).
+ #define USE_WORKAROUND_FOR_ANOMALY_192 1
+#endif
+
+#if !defined(USE_WORKAROUND_FOR_ANOMALY_201) && \
+ (defined(NRF52810_XXAA) || \
+ defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
+ defined(NRF52840_XXAA))
+ // Enable workaround for nRF52 anomaly 201 (EVENTS_HFCLKSTARTED might be generated twice).
+ #define USE_WORKAROUND_FOR_ANOMALY_201 1
#endif
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
@@ -82,7 +98,7 @@ typedef struct
{
nrfx_clock_event_handler_t event_handler;
bool module_initialized; /*< Indicate the state of module */
-#if defined(USE_WORKAROUND_FOR_ANOMALY_201)
+#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
bool hfclk_started; /*< Anomaly 201 workaround. */
#endif
@@ -101,18 +117,7 @@ static nrfx_clock_cb_t m_clock_cb;
bool nrfx_clock_irq_enabled;
#endif
-#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
-
-// ANOMALY 132 - LFCLK needs to avoid frame from 66us to 138us after LFCLK stop. This solution
-// applies delay of 138us before starting LFCLK.
-#define ANOMALY_132_REQ_DELAY_US 138UL
-
-// nRF52832 is clocked with 64MHz.
-#define ANOMALY_132_NRF52832_FREQ_MHZ 64UL
-
-// Convert time to cycles.
-#define ANOMALY_132_DELAY_CYCLES (ANOMALY_132_REQ_DELAY_US * ANOMALY_132_NRF52832_FREQ_MHZ)
-
+#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)
/**
* @brief Function for applying delay of 138us before starting LFCLK.
*/
@@ -143,8 +148,7 @@ static void nrfx_clock_anomaly_132(void)
DWT->CTRL = dwt_ctrl;
CoreDebug->DEMCR = core_debug;
}
-
-#endif // defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
@@ -162,7 +166,7 @@ nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
#endif
m_clock_cb.event_handler = event_handler;
m_clock_cb.module_initialized = true;
-#if defined(USE_WORKAROUND_FOR_ANOMALY_201)
+#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
m_clock_cb.hfclk_started = false;
#endif
}
@@ -222,7 +226,7 @@ void nrfx_clock_lfclk_start(void)
nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED);
nrf_clock_int_enable(NRF_CLOCK_INT_LF_STARTED_MASK);
-#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)
nrfx_clock_anomaly_132();
#endif
@@ -251,7 +255,7 @@ void nrfx_clock_hfclk_stop(void)
nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP);
while (nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY))
{}
-#if defined(USE_WORKAROUND_FOR_ANOMALY_201)
+#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
m_clock_cb.hfclk_started = false;
#endif
}
@@ -276,7 +280,7 @@ nrfx_err_t nrfx_clock_calibration_start(void)
nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE);
nrf_clock_int_enable(NRF_CLOCK_INT_DONE_MASK);
m_clock_cb.cal_state = CAL_STATE_CAL;
-#if defined(USE_WORKAROUND_FOR_ANOMALY_192)
+#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_192)
*(volatile uint32_t *)0x40000C34 = 0x00000002;
#endif
nrf_clock_task_trigger(NRF_CLOCK_TASK_CAL);
@@ -330,7 +334,7 @@ void nrfx_clock_irq_handler(void)
NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_CLOCK_EVENT_HFCLKSTARTED));
nrf_clock_int_disable(NRF_CLOCK_INT_HF_STARTED_MASK);
-#if defined(USE_WORKAROUND_FOR_ANOMALY_201)
+#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
if (!m_clock_cb.hfclk_started)
{
m_clock_cb.hfclk_started = true;
@@ -361,7 +365,7 @@ void nrfx_clock_irq_handler(void)
if (nrf_clock_event_check(NRF_CLOCK_EVENT_DONE))
{
-#if defined(USE_WORKAROUND_FOR_ANOMALY_192)
+#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_192)
*(volatile uint32_t *)0x40000C34 = 0x00000000;
#endif
nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE);
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_nfct.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_nfct.c
index 5b83becb7..354a8cb26 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_nfct.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_nfct.c
@@ -38,43 +38,44 @@
#define NRFX_LOG_MODULE NFCT
#include
-#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || defined(NRF52840_XXAA)
+#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
+ defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
#define USE_TIMER_WORKAROUND
#endif
-#ifdef USE_TIMER_WORKAROUND
+#if defined(USE_TIMER_WORKAROUND)
#include
typedef struct
{
const nrfx_timer_t timer; /**< Timer instance that supports the correct NFC field detection. */
-#ifdef NRF52840_XXAA
+#if defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
bool fieldevents_filter_active; /**< Flag that indicates that the field events are ignored. */
bool is_hfclk_on; /**< HFCLK has started - one of the NFC activation conditions. */
bool is_delayed; /**< Required time delay has passed - one of the NFC activation conditions. */
#else
uint32_t field_state_cnt; /**< Counter of the FIELDLOST events. */
-#endif // NRF52840_XXAA
+#endif // defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
} nrfx_nfct_timer_workaround_t;
-#ifdef NRF52840_XXAA
+#if defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
#define NRFX_NFCT_ACTIVATE_DELAY 1000 /**< Minimal delay in us between NFC field detection and activation of NFCT. */
#define NRFX_NFCT_TIMER_PERIOD NRFX_NFCT_ACTIVATE_DELAY
#else
#define NRFX_NFCT_FIELDLOST_THR 7
#define NRFX_NFCT_FIELD_TIMER_PERIOD 100 /**< Field polling period in us. */
#define NRFX_NFCT_TIMER_PERIOD NRFX_NFCT_FIELD_TIMER_PERIOD
-#endif // NRF52840_XXAA
+#endif // defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
#define NRFX_NFCT_TIMER_INSTANCE 4 /**< Timer instance used for various workarounds for the NFCT HW issues.*/
static nrfx_nfct_timer_workaround_t m_timer_workaround =
{
.timer = NRFX_TIMER_INSTANCE(NRFX_NFCT_TIMER_INSTANCE),
};
-#endif // USE_TIMER_WORKAROUND
+#endif // defined(USE_TIMER_WORKAROUND)
-#define NRFX_NFCT_FRAMEDELAYMAX_52840S (0xFFFFUL) /**< Bit mask of the FRAMEDELAYMAX field for the first sample of 52840.*/
-#define NRFX_NFCT_FWT_MAX_DIFF 1u /**< The maximal difference between the requested FWT and HW-limited FWT settings.*/
+#define NRFX_NFCT_FWT_MAX_DIFF 1u /**< The maximal difference between the requested FWT and HW-limited FWT settings.*/
+#define NFCT_FRAMEDELAYMAX_DEFAULT (0x00001000UL) /**< Default value of the FRAMEDELAYMAX. */
/* Mask of all possible interrupts that are relevant for data reception. */
#define NRFX_NFCT_RX_INT_MASK (NRF_NFCT_INT_RXFRAMESTART_MASK | \
@@ -123,62 +124,13 @@ typedef enum
NRFX_NFC_FIELD_STATE_UNKNOWN /**< Both NFCT field events have been set - ambiguous state. */
} nrfx_nfct_field_state_t;
-#ifdef NRF52840_XXAA
-/**
- * @brief Internal auxiliary function for checking whether the program is running on the NRF52840 chip.
- *
- * @retval true It is NRF52480 chip.
- * @retval false It is an other chip.
- */
-static inline bool nrfx_nfct_type_52840_check(void)
-{
- return ((((*(uint32_t *)0xF0000FE0) & 0xFF) == 0x08) &&
- (((*(uint32_t *)0xF0000FE4) & 0x0F) == 0x0));
-}
-
-/**
- * @brief Internal auxiliary function for checking whether the program is running on the first sample of
- * the nRF52840 chip.
- *
- * @retval true It is the nRF52480 chip and it is the first sample version.
- * @retval false It is an other chip.
- */
-static inline bool nrfx_nfct_type_52840_sample_check(void)
-{
- return ( nrfx_nfct_type_52840_check() &&
- ( ((*(uint32_t *)0xF0000FE8) & 0xF0) == 0x00 ) &&
- ( ((*(uint32_t *)0xF0000FEC) & 0xF0) == 0x00 ) );
-}
-
-/**
- * @brief Internal auxiliary function for checking whether the program is running on the final version of
- * the nRF52840 chip.
- *
- * @retval true It is the nRF52480 chip and it is the final version.
- * @retval false It is an other chip.
- */
-static inline bool nrfx_nfct_type_52840_final_check(void)
-{
- return ( nrfx_nfct_type_52840_check() &&
- ( ( ((*(uint32_t *)0xF0000FE8) & 0xF0) != 0x00 ) ||
- ( ((*(uint32_t *)0xF0000FEC) & 0xF0) != 0x00 ) ));
-}
-
-typedef struct
-{
- bool eng_a; /**< Engineering sample A of the NRF52840 chip. */
- bool eng_bc; /**< Engineering sample B, C of the NRF52840 chip, or its final version. */
-} nrfx_nfct_nrf52840_ver_t;
-
-static nrfx_nfct_nrf52840_ver_t m_nrf52840;
-#endif // NRF52840_XXAA
-
/**@brief NFCT control block. */
typedef struct
{
nrfx_nfct_config_t config;
nrfx_drv_state_t state;
volatile bool field_on;
+ uint32_t frame_delay_max;
} nrfx_nfct_control_block_t;
static nrfx_nfct_control_block_t m_nfct_cb;
@@ -188,20 +140,6 @@ static nrfx_nfct_control_block_t m_nfct_cb;
*/
static void nrfx_nfct_hw_init_setup(void)
{
-#ifdef NRF52840_XXAA
- if (m_nrf52840.eng_a)
- {
- /* Begin: Bugfix for FTPAN-98 */
- *(volatile uint32_t *) 0x4000568C = 0x00038148;
- /* End: Bugfix for FTPAN-98 */
- /* Begin: Bugfix for FTPAN-144 */
- *(volatile uint32_t *) 0x4000561c = 0x01;
- *(volatile uint32_t *) 0x4000562c = 0x3F;
- *(volatile uint32_t *) 0x4000563c = 0x0;
- /* End: Bugfix for FTPAN-144 */
- }
-#endif // NRF52840_XXAA
-
// Use Window Grid frame delay mode.
nrf_nfct_frame_delay_mode_set(NRF_NFCT_FRAME_DELAY_MODE_WINDOWGRID);
@@ -212,6 +150,18 @@ static void nrfx_nfct_hw_init_setup(void)
/* End: Bugfix for FTPAN-25 (IC-9929) */
}
+static void nrfx_nfct_frame_delay_max_set(bool default_delay)
+{
+ if (default_delay)
+ {
+ nrf_nfct_frame_delay_max_set(NFCT_FRAMEDELAYMAX_DEFAULT);
+ }
+ else
+ {
+ nrf_nfct_frame_delay_max_set(m_nfct_cb.frame_delay_max);
+ }
+}
+
/**@brief Function for evaluating and handling the NFC field events.
*
* @param[in] field_state Current field state.
@@ -220,12 +170,12 @@ static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field
{
nrfx_nfct_evt_t nfct_evt;
-#ifdef NRF52840_XXAA
- if((!m_nrf52840.eng_a) && (m_timer_workaround.fieldevents_filter_active))
+#if defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
+ if(m_timer_workaround.fieldevents_filter_active)
{
return;
}
-#endif // NRF52840_XXAA
+#endif // defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
if (field_state == NRFX_NFC_FIELD_STATE_UNKNOWN)
{
@@ -239,23 +189,20 @@ static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field
case NRFX_NFC_FIELD_STATE_ON:
if (!m_nfct_cb.field_on)
{
-#ifdef NRF52840_XXAA
+#if defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
/* Begin: Bugfix for FTPAN-190 */
- if (!m_nrf52840.eng_a)
- {
- m_timer_workaround.is_hfclk_on = false;
- m_timer_workaround.is_delayed = false;
- m_timer_workaround.fieldevents_filter_active = true;
+ m_timer_workaround.is_hfclk_on = false;
+ m_timer_workaround.is_delayed = false;
+ m_timer_workaround.fieldevents_filter_active = true;
- nrfx_timer_clear(&m_timer_workaround.timer);
- nrfx_timer_enable(&m_timer_workaround.timer);
- }
+ nrfx_timer_clear(&m_timer_workaround.timer);
+ nrfx_timer_enable(&m_timer_workaround.timer);
/* END: Bugfix for FTPAN-190 */
#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
nrfx_timer_clear(&m_timer_workaround.timer);
nrfx_timer_enable(&m_timer_workaround.timer);
m_timer_workaround.field_state_cnt = 0;
-#endif // NRF52840_XXAA
+#endif // defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
m_nfct_cb.field_on = true;
nfct_evt.evt_id = NRFX_NFCT_EVT_FIELD_DETECTED;
@@ -265,18 +212,14 @@ static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field
case NRFX_NFC_FIELD_STATE_OFF:
nrfx_nfct_state_force(NRFX_NFCT_STATE_SENSING);
-#ifdef NRF52840_XXAA
- /* Begin: Bugfix for FTPAN-116 (IC-12886) */
- if (m_nrf52840.eng_a)
- {
- *(volatile uint32_t *)0x40005010 = 1;
- }
- /* END: Bugfix for FTPAN-116 (IC-12886) */
-#endif // NRF52840_XXAA
nrf_nfct_int_disable(NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK);
m_nfct_cb.field_on = false;
nfct_evt.evt_id = NRFX_NFCT_EVT_FIELD_LOST;
+ /* Begin: Bugfix for FTPAN-218 */
+ nrfx_nfct_frame_delay_max_set(true);
+ /* End: Bugfix for FTPAN-218 */
+
NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
break;
@@ -286,9 +229,9 @@ static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field
}
}
-#ifdef USE_TIMER_WORKAROUND
+#if defined(USE_TIMER_WORKAROUND)
-#ifdef NRF52840_XXAA
+#if defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
static void nrfx_nfct_activate_check(void)
{
static bool is_field_validation_pending = false;
@@ -313,7 +256,7 @@ static void nrfx_nfct_activate_check(void)
nrfx_timer_enable(&m_timer_workaround.timer);
}
}
-#endif // NRF52840_XXAA
+#endif // defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
static inline void nrfx_nfct_reset(void)
@@ -346,6 +289,9 @@ static inline void nrfx_nfct_reset(void)
// Restore interrupts.
nrf_nfct_int_enable(int_enabled);
+ // Disable interrupts associated with data exchange.
+ nrf_nfct_int_disable(NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK);
+
NRFX_LOG_INFO("Reinitialize");
}
@@ -363,6 +309,10 @@ static void nrfx_nfct_field_poll(void)
nrfx_timer_disable(&m_timer_workaround.timer);
m_nfct_cb.field_on = false;
+ /* Begin: Bugfix for FTPAN-218 */
+ nrfx_nfct_frame_delay_max_set(true);
+ /* End: Bugfix for FTPAN-218 */
+
/* Begin: Bugfix for FTPAN-116 */
// resume the NFCT to initialized state
nrfx_nfct_reset();
@@ -386,14 +336,14 @@ static void nrfx_nfct_field_timer_handler(nrf_timer_event_t event_type, void * p
return;
}
-#ifdef NRF52840_XXAA
+#if defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
m_timer_workaround.is_delayed = true;
nrfx_timer_disable(&m_timer_workaround.timer);
nrfx_nfct_activate_check();
#else
nrfx_nfct_field_poll();
-#endif //NRF52840_XXAA
+#endif // defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
}
static inline nrfx_err_t nrfx_nfct_field_timer_config(void)
@@ -421,7 +371,7 @@ static inline nrfx_err_t nrfx_nfct_field_timer_config(void)
return err_code;
}
-#endif // USE_TIMER_WORKAROUND
+#endif // defined(USE_TIMER_WORKAROUND)
static inline nrf_nfct_sensres_nfcid1_size_t nrf_nfct_nfcid1_size_to_sensres_size(uint8_t nfcid1_size)
{
@@ -457,11 +407,6 @@ nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config)
return NRFX_ERROR_INVALID_STATE;
}
-#ifdef NRF52840_XXAA
- m_nrf52840.eng_a = nrfx_nfct_type_52840_sample_check();
- m_nrf52840.eng_bc = nrfx_nfct_type_52840_final_check();
-#endif // NRF52840_XXAA
-
m_nfct_cb.config = *p_config;
nrfx_nfct_hw_init_setup();
@@ -469,15 +414,10 @@ nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config)
NRFX_IRQ_PRIORITY_SET(NFCT_IRQn, NRFX_NFCT_CONFIG_IRQ_PRIORITY);
NRFX_IRQ_ENABLE(NFCT_IRQn);
-#ifdef USE_TIMER_WORKAROUND
+#if defined(USE_TIMER_WORKAROUND)
/* Initialize Timer module as the workaround for NFCT HW issues. */
- #ifdef NRF52840_XXAA
- if (!m_nrf52840.eng_a)
- #endif // NRF52840_XXAA
- {
- err_code = nrfx_nfct_field_timer_config();
- }
-#endif // USE_TIMER_WORKAROUND
+ err_code = nrfx_nfct_field_timer_config();
+#endif // defined(USE_TIMER_WORKAROUND)
if (err_code == NRFX_SUCCESS)
{
@@ -491,7 +431,8 @@ nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config)
return err_code;
}
- m_nfct_cb.state = NRFX_DRV_STATE_INITIALIZED;
+ m_nfct_cb.state = NRFX_DRV_STATE_INITIALIZED;
+ m_nfct_cb.frame_delay_max = NFCT_FRAMEDELAYMAX_DEFAULT;
NRFX_LOG_INFO("Initialized");
return err_code;
@@ -504,15 +445,10 @@ void nrfx_nfct_uninit(void)
NRFX_IRQ_DISABLE(NFCT_IRQn);
NRFX_IRQ_PENDING_CLEAR(NFCT_IRQn);
-#ifdef USE_TIMER_WORKAROUND
- /* Initialize Timer module as the workaround for NFCT HW issues. */
- #ifdef NRF52840_XXAA
- if (!m_nrf52840.eng_a)
- #endif // NRF52840_XXAA
- {
+#if defined(USE_TIMER_WORKAROUND)
+ /* De-initialize Timer module as the workaround for NFCT HW issues. */
nrfx_timer_uninit(&m_timer_workaround.timer);
- }
-#endif // USE_TIMER_WORKAROUND
+#endif // defined(USE_TIMER_WORKAROUND)
m_nfct_cb.state = NRFX_DRV_STATE_UNINITIALIZED;
}
@@ -587,16 +523,14 @@ nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data,
void nrfx_nfct_state_force(nrfx_nfct_state_t state)
{
-#ifdef NRF52840_XXAA
- if ((m_nrf52840.eng_bc) && (state == NRFX_NFCT_STATE_ACTIVATED))
+#if defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
+ if (state == NRFX_NFCT_STATE_ACTIVATED)
{
m_timer_workaround.is_hfclk_on = true;
nrfx_nfct_activate_check();
}
-#endif
- {
- nrf_nfct_task_trigger((nrf_nfct_task_t) state);
- }
+#endif // defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
+ nrf_nfct_task_trigger((nrf_nfct_task_t) state);
}
void nrfx_nfct_init_substate_force(nrfx_nfct_active_state_t sub_state)
@@ -623,6 +557,10 @@ void nrfx_nfct_init_substate_force(nrfx_nfct_active_state_t sub_state)
nrf_nfct_task_trigger((nrf_nfct_task_t) sub_state);
}
+ /* Begin: Bugfix for FTPAN-218 */
+ nrfx_nfct_frame_delay_max_set(true);
+ /* End: Bugfix for FTPAN-218 */
+
/* Disable TX/RX here (will be enabled at SELECTED) */
nrf_nfct_int_disable(NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK);
}
@@ -638,10 +576,6 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param)
uint32_t delay = p_param->data.fdt;
uint32_t delay_thr = NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk;
-#ifdef NRF52840_XXAA
- delay_thr = (m_nrf52840.eng_a) ? NRFX_NFCT_FRAMEDELAYMAX_52840S : delay_thr;
-#endif // NRF52840_XXAA
-
// Delay validation.
if (delay > (delay_thr + NRFX_NFCT_FWT_MAX_DIFF))
{
@@ -649,7 +583,7 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param)
}
delay = (delay > delay_thr) ? delay_thr : delay;
- nrf_nfct_frame_delay_max_set(delay);
+ m_nfct_cb.frame_delay_max = delay;
break;
}
@@ -830,6 +764,10 @@ void nrfx_nfct_irq_handler(void)
nrf_nfct_event_clear(NRF_NFCT_EVENT_TXFRAMESTART);
nrf_nfct_event_clear(NRF_NFCT_EVENT_TXFRAMEEND);
+ /* Begin: Bugfix for FTPAN-218 */
+ nrfx_nfct_frame_delay_max_set(false);
+ /* End: Bugfix for FTPAN-218 */
+
/* At this point any previous error status can be ignored. */
nrf_nfct_rx_frame_status_clear(NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK);
nrf_nfct_error_status_clear(NRFX_NFCT_ERROR_STATUS_ALL_MASK);
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_nvmc.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_nvmc.c
new file mode 100644
index 000000000..13e89989a
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_nvmc.c
@@ -0,0 +1,421 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+#if NRFX_CHECK(NRFX_NVMC_ENABLED)
+
+#include
+
+/**
+ * Value representing the number of bytes in a word.
+ *
+ * It is used in loops iterating over bytes contained in a word
+ * or in word-alignment checks.
+ */
+#define NVMC_BYTES_IN_WORD 4
+
+/**
+ * Value representing non-volatile memory (NVM) page count.
+ *
+ * This symbol is needed to determine NVM page count for chips that cannot
+ * always access FICR for this information.
+ */
+#if defined(NRF9160_XXAA)
+ #define NVMC_FLASH_PAGE_COUNT 256
+#endif
+
+/**
+ * Value representing non-volatile memory (NVM) page size in bytes.
+ *
+ * This symbol is needed to determine NVM page size for chips that cannot
+ * always access FICR for this information.
+ */
+#if defined(NRF9160_XXAA)
+ #define NVMC_FLASH_PAGE_SIZE 0x1000 ///< 4 kB
+#endif
+
+#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
+/**
+ * Value representing the page erase time.
+ *
+ * This value is used to determine whether the partial erase is still in progress.
+ */
+#if defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52840_XXAA)
+ #define NVMC_PAGE_ERASE_DURATION_MS 85
+#elif defined(NRF52833_XXAA) || defined(NRF9160_XXAA)
+ #define NVMC_PAGE_ERASE_DURATION_MS 87
+#else
+ #error "Page partial erase present but could not determine its total duration for given SoC"
+#endif
+
+/**
+ * Value representing the invalid page partial erase address.
+ *
+ * This value is used for representing a NULL pointer for
+ * partial erase, as that address 0 can be a valid
+ * memory address in flash.
+ */
+#define NVMC_PARTIAL_ERASE_INVALID_ADDR 0xFFFFFFFF
+
+/** Internal counter for page partial erase. */
+static uint32_t m_partial_erase_time_elapsed;
+
+/** Partial erase page address. */
+static uint32_t m_partial_erase_page_addr = NVMC_PARTIAL_ERASE_INVALID_ADDR;
+
+#endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
+
+static uint32_t flash_page_size_get(void)
+{
+ uint32_t flash_page_size = 0;
+
+#if defined(NRF51) || defined(NRF52_SERIES)
+ flash_page_size = nrf_ficr_codepagesize_get(NRF_FICR);
+#elif defined(NVMC_FLASH_PAGE_SIZE)
+ flash_page_size = NVMC_FLASH_PAGE_SIZE;
+#else
+ #error "Cannot determine flash page size for a given SoC."
+#endif
+
+ return flash_page_size;
+}
+
+static uint32_t flash_page_count_get(void)
+{
+ uint32_t page_count = 0;
+
+#if defined(NRF51) || defined(NRF52_SERIES)
+ page_count = nrf_ficr_codesize_get(NRF_FICR);
+#elif defined(NVMC_FLASH_PAGE_COUNT)
+ page_count = NVMC_FLASH_PAGE_COUNT;
+#else
+ #error "Cannot determine flash page count for a given SoC."
+#endif
+
+ return page_count;
+}
+
+static uint32_t flash_total_size_get(void)
+{
+ return flash_page_size_get() * flash_page_count_get();
+}
+
+
+static bool is_page_aligned_check(uint32_t addr)
+{
+ /* If the modulo operation returns '0', then the address is aligned. */
+ return !(addr % flash_page_size_get());
+}
+
+static uint32_t partial_word_create(uint32_t addr, uint8_t const * bytes, uint32_t bytes_count)
+{
+ uint32_t value32;
+ uint32_t byte_shift;
+
+ byte_shift = addr % NVMC_BYTES_IN_WORD;
+
+ NRFX_ASSERT(bytes_count <= (NVMC_BYTES_IN_WORD - byte_shift));
+
+ value32 = 0xFFFFFFFF;
+ for (uint32_t i = 0; i < bytes_count; i++)
+ {
+ ((uint8_t *)&value32)[byte_shift] = bytes[i];
+ byte_shift++;
+ }
+
+ return value32;
+}
+
+static void nvmc_readonly_mode_set(void)
+{
+#if defined(NRF_TRUSTZONE_NONSECURE)
+ nrf_nvmc_nonsecure_mode_set(NRF_NVMC, NRF_NVMC_NS_MODE_READONLY);
+#else
+ nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY);
+#endif
+}
+
+static void nvmc_write_mode_set(void)
+{
+#if defined(NRF_TRUSTZONE_NONSECURE)
+ nrf_nvmc_nonsecure_mode_set(NRF_NVMC, NRF_NVMC_NS_MODE_WRITE);
+#else
+ nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_WRITE);
+#endif
+}
+
+static void nvmc_erase_mode_set(void)
+{
+#if defined(NRF_TRUSTZONE_NONSECURE)
+ nrf_nvmc_nonsecure_mode_set(NRF_NVMC, NRF_NVMC_NS_MODE_ERASE);
+#else
+ nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_ERASE);
+#endif
+}
+
+static void nvmc_word_write(uint32_t addr, uint32_t value)
+{
+#if defined(NRF9160_XXAA)
+ while (!nrf_nvmc_write_ready_check(NRF_NVMC))
+ {}
+#else
+ while (!nrf_nvmc_ready_check(NRF_NVMC))
+ {}
+#endif
+
+ *(volatile uint32_t *)addr = value;
+ __DMB();
+}
+
+static void nvmc_words_write(uint32_t addr, void const * src, uint32_t num_words)
+{
+ for (uint32_t i = 0; i < num_words; i++)
+ {
+ nvmc_word_write(addr + (NVMC_BYTES_IN_WORD * i), ((uint32_t const *)src)[i]);
+ }
+}
+
+nrfx_err_t nrfx_nvmc_page_erase(uint32_t addr)
+{
+ NRFX_ASSERT(addr < flash_total_size_get());
+
+ if (!is_page_aligned_check(addr))
+ {
+ return NRFX_ERROR_INVALID_ADDR;
+ }
+
+ nvmc_erase_mode_set();
+ nrf_nvmc_page_erase_start(NRF_NVMC, addr);
+ while (!nrf_nvmc_ready_check(NRF_NVMC))
+ {}
+ nvmc_readonly_mode_set();
+
+ return NRFX_SUCCESS;
+}
+
+nrfx_err_t nrfx_nvmc_uicr_erase(void)
+{
+#if defined(NVMC_ERASEUICR_ERASEUICR_Msk)
+ nvmc_erase_mode_set();
+ nrf_nvmc_uicr_erase_start(NRF_NVMC);
+ while (!nrf_nvmc_ready_check(NRF_NVMC))
+ {}
+ nvmc_readonly_mode_set();
+ return NRFX_SUCCESS;
+#else
+ return NRFX_ERROR_NOT_SUPPORTED;
+#endif
+}
+
+void nrfx_nvmc_all_erase(void)
+{
+ nvmc_erase_mode_set();
+ nrf_nvmc_erase_all_start(NRF_NVMC);
+ while (!nrf_nvmc_ready_check(NRF_NVMC))
+ {}
+ nvmc_readonly_mode_set();
+}
+
+#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
+nrfx_err_t nrfx_nvmc_page_partial_erase_init(uint32_t addr, uint32_t duration_ms)
+{
+ NRFX_ASSERT(addr < flash_total_size_get());
+
+ if (!is_page_aligned_check(addr))
+ {
+ return NRFX_ERROR_INVALID_ADDR;
+ }
+
+ m_partial_erase_time_elapsed = 0;
+ m_partial_erase_page_addr = addr;
+ nrf_nvmc_partial_erase_duration_set(NRF_NVMC, duration_ms);
+
+ return NRFX_SUCCESS;
+}
+
+bool nrfx_nvmc_page_partial_erase_continue(void)
+{
+ NRFX_ASSERT(m_partial_erase_page_addr != NVMC_PARTIAL_ERASE_INVALID_ADDR);
+
+ uint32_t duration_ms = nrf_nvmc_partial_erase_duration_get(NRF_NVMC);
+
+#if defined(NVMC_CONFIG_WEN_PEen)
+ nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_PARTIAL_ERASE);
+#else
+ nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_ERASE);
+#endif
+
+ nrf_nvmc_page_partial_erase_start(NRF_NVMC, m_partial_erase_page_addr);
+ while (!nrf_nvmc_ready_check(NRF_NVMC))
+ {}
+ nvmc_readonly_mode_set();
+
+ m_partial_erase_time_elapsed += duration_ms;
+ if (m_partial_erase_time_elapsed < NVMC_PAGE_ERASE_DURATION_MS)
+ {
+ return false;
+ }
+ else
+ {
+ m_partial_erase_page_addr = NVMC_PARTIAL_ERASE_INVALID_ADDR;
+ return true;
+ }
+}
+#endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
+
+bool nrfx_nvmc_byte_writable_check(uint32_t addr, uint8_t val_to_check)
+{
+ NRFX_ASSERT(addr < flash_total_size_get());
+
+ uint8_t val_on_addr = *(uint8_t const *)addr;
+ return (val_to_check & val_on_addr) == val_to_check;
+}
+
+bool nrfx_nvmc_word_writable_check(uint32_t addr, uint32_t val_to_check)
+{
+ NRFX_ASSERT(addr < flash_total_size_get());
+ NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));
+
+ uint32_t val_on_addr = *(uint32_t const *)addr;
+ return (val_to_check & val_on_addr) == val_to_check;
+}
+
+void nrfx_nvmc_byte_write(uint32_t addr, uint8_t value)
+{
+ uint32_t aligned_addr = addr & ~(0x03UL);
+
+ nrfx_nvmc_word_write(aligned_addr, partial_word_create(addr, &value, 1));
+}
+
+void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
+{
+ NRFX_ASSERT(addr < flash_total_size_get());
+ NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));
+
+ nvmc_write_mode_set();
+
+ nvmc_word_write(addr, value);
+
+ nvmc_readonly_mode_set();
+}
+
+void nrfx_nvmc_bytes_write(uint32_t addr, void const * src, uint32_t num_bytes)
+{
+ NRFX_ASSERT(addr < flash_total_size_get());
+
+ nvmc_write_mode_set();
+
+ uint8_t const * bytes_src = (uint8_t const *)src;
+
+ uint32_t unaligned_bytes = addr % NVMC_BYTES_IN_WORD;
+ if (unaligned_bytes != 0)
+ {
+ uint32_t leading_bytes = NVMC_BYTES_IN_WORD - unaligned_bytes;
+ if (leading_bytes > num_bytes)
+ {
+ leading_bytes = num_bytes;
+ }
+
+ nvmc_word_write(addr - unaligned_bytes,
+ partial_word_create(addr, bytes_src, leading_bytes));
+ num_bytes -= leading_bytes;
+ addr += leading_bytes;
+ bytes_src += leading_bytes;
+ }
+
+#if defined(__CORTEX_M) && (__CORTEX_M == 0U)
+ if (!nrfx_is_word_aligned((void const *)bytes_src))
+ {
+ /* Cortex-M0 allows only word-aligned RAM access.
+ If source address is not word-aligned, bytes are combined
+ into words explicitly. */
+ for (uint32_t i = 0; i < num_bytes / NVMC_BYTES_IN_WORD; i++)
+ {
+ uint32_t word = (uint32_t)bytes_src[0]
+ | ((uint32_t)bytes_src[1]) << 8
+ | ((uint32_t)bytes_src[2]) << 16
+ | ((uint32_t)bytes_src[3]) << 24;
+
+ nvmc_word_write(addr, word);
+ bytes_src += NVMC_BYTES_IN_WORD;
+ addr += NVMC_BYTES_IN_WORD;
+ }
+ }
+ else
+#endif
+ {
+ uint32_t word_count = num_bytes / NVMC_BYTES_IN_WORD;
+
+ nvmc_words_write(addr, (uint32_t const *)bytes_src, word_count);
+
+ addr += word_count * NVMC_BYTES_IN_WORD;
+ bytes_src += word_count * NVMC_BYTES_IN_WORD;
+ }
+
+ uint32_t trailing_bytes = num_bytes % NVMC_BYTES_IN_WORD;
+ if (trailing_bytes != 0)
+ {
+ nvmc_word_write(addr, partial_word_create(addr, bytes_src, trailing_bytes));
+ }
+
+ nvmc_readonly_mode_set();
+}
+
+void nrfx_nvmc_words_write(uint32_t addr, void const * src, uint32_t num_words)
+{
+ NRFX_ASSERT(addr < flash_total_size_get());
+ NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));
+ NRFX_ASSERT(nrfx_is_word_aligned(src));
+
+ nvmc_write_mode_set();
+
+ nvmc_words_write(addr, src, num_words);
+
+ nvmc_readonly_mode_set();
+}
+
+uint32_t nrfx_nvmc_flash_size_get(void)
+{
+ return flash_total_size_get();
+}
+
+uint32_t nrfx_nvmc_flash_page_size_get(void)
+{
+ return flash_page_size_get();
+}
+
+uint32_t nrfx_nvmc_flash_page_count_get(void)
+{
+ return flash_page_count_get();
+}
+
+#endif // NRFX_CHECK(NRFX_NVMC_ENABLED)
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power.c
index a12a64e2c..ebfd71067 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_power.c
@@ -106,7 +106,7 @@ nrfx_err_t nrfx_power_init(nrfx_power_config_t const * p_config)
return NRFX_ERROR_ALREADY_INITIALIZED;
}
-#if NRF_POWER_HAS_VDDH
+#if NRF_POWER_HAS_DCDCEN_VDDH
nrf_power_dcdcen_vddh_set(p_config->dcdcenhv);
#endif
#if NRF_POWER_HAS_DCDCEN
@@ -225,6 +225,8 @@ void nrfx_power_sleepevt_uninit(void)
#if NRF_POWER_HAS_USBREG
void nrfx_power_usbevt_init(nrfx_power_usbevt_config_t const * p_config)
{
+ NRFX_ASSERT(p_config != NULL);
+
nrfx_power_usbevt_uninit();
if (p_config->handler != NULL)
{
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qspi.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qspi.c
index 1b339bfb0..458301701 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qspi.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_qspi.c
@@ -35,38 +35,25 @@
#include
-
-/**
- * @brief Command byte used to read status register.
- *
- */
+/** @brief Command byte used to read status register. */
#define QSPI_STD_CMD_RDSR 0x05
-/**
- * @brief Byte used to mask status register and retrieve the write-in-progess bit.
- *
- */
+/** @brief Byte used to mask status register and retrieve the write-in-progess bit. */
#define QSPI_MEM_STATUSREG_WIP_Pos 0x01
-/**
- * @brief Default time used in timeout function.
- */
+/** @brief Default time used in timeout function. */
#define QSPI_DEF_WAIT_TIME_US 10
-/**
- * @brief Default number of tries in timeout function.
- */
+/** @brief Default number of tries in timeout function. */
#define QSPI_DEF_WAIT_ATTEMPTS 100
-/**
- * @brief Control block - driver instance local data.
- */
+/** @brief Control block - driver instance local data. */
typedef struct
{
- nrfx_qspi_handler_t handler; /**< Handler. */
- nrfx_drv_state_t state; /**< Driver state. */
- volatile bool interrupt_driven; /**< Information if the current operation is performed and is interrupt-driven. */
- void * p_context; /**< Driver context used in interrupt. */
+ nrfx_qspi_handler_t handler; /**< Handler. */
+ nrfx_drv_state_t state; /**< Driver state. */
+ volatile bool is_busy; /**< Flag indicating that an operation is currently being performed. */
+ void * p_context; /**< Driver context used in interrupt. */
} qspi_control_block_t;
static qspi_control_block_t m_cb;
@@ -74,7 +61,7 @@ static qspi_control_block_t m_cb;
static nrfx_err_t qspi_task_perform(nrf_qspi_task_t task)
{
// Wait for peripheral
- if (m_cb.interrupt_driven)
+ if (m_cb.is_busy)
{
return NRFX_ERROR_BUSY;
}
@@ -83,7 +70,7 @@ static nrfx_err_t qspi_task_perform(nrf_qspi_task_t task)
if (m_cb.handler)
{
- m_cb.interrupt_driven = true;
+ m_cb.is_busy = true;
nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
}
@@ -113,6 +100,21 @@ static bool qspi_pins_configure(nrf_qspi_pins_t const * p_config)
return true;
}
+static nrfx_err_t qspi_ready_wait(void)
+{
+ bool result;
+ NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY),
+ QSPI_DEF_WAIT_ATTEMPTS,
+ QSPI_DEF_WAIT_TIME_US,
+ result);
+ if (!result)
+ {
+ return NRFX_ERROR_TIMEOUT;
+ }
+
+ return NRFX_SUCCESS;
+}
+
nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config,
nrfx_qspi_handler_t handler,
void * p_context)
@@ -132,7 +134,7 @@ nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config,
nrf_qspi_ifconfig0_set(NRF_QSPI, &p_config->prot_if);
nrf_qspi_ifconfig1_set(NRF_QSPI, &p_config->phy_if);
- m_cb.interrupt_driven = false;
+ m_cb.is_busy = false;
m_cb.handler = handler;
m_cb.p_context = p_context;
@@ -154,18 +156,8 @@ nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config,
nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_ACTIVATE);
// Waiting for the peripheral to activate
- bool result;
- NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY),
- QSPI_DEF_WAIT_ATTEMPTS,
- QSPI_DEF_WAIT_TIME_US,
- result);
- if (!result)
- {
- return NRFX_ERROR_TIMEOUT;
- }
-
- return NRFX_SUCCESS;
+ return qspi_ready_wait();
}
nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config,
@@ -174,7 +166,7 @@ nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config,
{
NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
- if (m_cb.interrupt_driven)
+ if (m_cb.is_busy)
{
return NRFX_ERROR_BUSY;
}
@@ -187,17 +179,12 @@ nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config,
{
nrf_qspi_cinstrdata_set(NRF_QSPI, p_config->length, p_tx_buffer);
}
+
nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
nrf_qspi_cinstr_transfer_start(NRF_QSPI, p_config);
- bool result;
- NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY),
- QSPI_DEF_WAIT_ATTEMPTS,
- QSPI_DEF_WAIT_TIME_US,
- result);
-
- if (!result)
+ if (qspi_ready_wait() == NRFX_ERROR_TIMEOUT)
{
// This timeout should never occur when WIPWAIT is not active, since in this
// case the QSPI peripheral should send the command immediately, without any
@@ -207,7 +194,6 @@ nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config,
return NRFX_ERROR_TIMEOUT;
}
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
- nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
if (p_rx_buffer)
{
@@ -225,6 +211,93 @@ nrfx_err_t nrfx_qspi_cinstr_quick_send(uint8_t opcode,
return nrfx_qspi_cinstr_xfer(&config, p_tx_buffer, NULL);
}
+nrfx_err_t nrfx_qspi_lfm_start(nrf_qspi_cinstr_conf_t const * p_config)
+{
+ NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
+ NRFX_ASSERT(!(nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI)));
+ NRFX_ASSERT(p_config->length == NRF_QSPI_CINSTR_LEN_1B);
+
+ if (m_cb.is_busy)
+ {
+ return NRFX_ERROR_BUSY;
+ }
+
+ nrf_qspi_cinstr_long_transfer_start(NRF_QSPI, p_config);
+
+ if (qspi_ready_wait() == NRFX_ERROR_TIMEOUT)
+ {
+ /* In case of error, abort long frame mode */
+ nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI, NRF_QSPI_CINSTR_LEN_1B, true);
+ return NRFX_ERROR_TIMEOUT;
+ }
+
+ m_cb.is_busy = true;
+ return NRFX_SUCCESS;
+}
+
+nrfx_err_t nrfx_qspi_lfm_xfer(void const * p_tx_buffer,
+ void * p_rx_buffer,
+ size_t transfer_length,
+ bool finalize)
+{
+ NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
+ NRFX_ASSERT(nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI));
+
+ nrfx_err_t status = NRFX_SUCCESS;
+
+ /* Perform transfers in packets of 8 bytes. Last transfer may be shorter. */
+ nrf_qspi_cinstr_len_t length = NRF_QSPI_CINSTR_LEN_9B;
+ for (uint32_t curr_byte = 0; curr_byte < transfer_length; curr_byte += 8)
+ {
+ uint32_t remaining_bytes = transfer_length - curr_byte;
+ if (remaining_bytes < 8)
+ {
+ length = (nrf_qspi_cinstr_len_t)(remaining_bytes + 1);
+ }
+
+ if (p_tx_buffer)
+ {
+ nrf_qspi_cinstrdata_set(NRF_QSPI,
+ length,
+ &((uint8_t const *)p_tx_buffer)[curr_byte]);
+ }
+
+ nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
+
+ if (remaining_bytes <= 8)
+ {
+ nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI, length, finalize);
+ }
+ else
+ {
+ nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI, length, false);
+ }
+
+ if (qspi_ready_wait() == NRFX_ERROR_TIMEOUT)
+ {
+ /* In case of error, abort long frame mode */
+ nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI, NRF_QSPI_CINSTR_LEN_1B, true);
+ status = NRFX_ERROR_TIMEOUT;
+ break;
+ }
+
+ if (p_rx_buffer)
+ {
+ nrf_qspi_cinstrdata_get(NRF_QSPI,
+ length,
+ &((uint8_t *)p_rx_buffer)[curr_byte]);
+ }
+ }
+ nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
+
+ if ((finalize) || (status == NRFX_ERROR_TIMEOUT))
+ {
+ m_cb.is_busy = false;
+ }
+
+ return status;
+}
+
nrfx_err_t nrfx_qspi_mem_busy_check(void)
{
nrfx_err_t ret_code;
@@ -252,6 +325,11 @@ void nrfx_qspi_uninit(void)
{
NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
+ if (nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI))
+ {
+ nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI, NRF_QSPI_CINSTR_LEN_1B, true);
+ }
+
nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_DEACTIVATE);
@@ -271,17 +349,14 @@ nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer,
{
NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
NRFX_ASSERT(p_tx_buffer != NULL);
- NRFX_ASSERT(nrfx_is_in_ram(p_tx_buffer));
- NRFX_ASSERT(nrfx_is_word_aligned(p_tx_buffer));
- if (!nrfx_is_in_ram(p_tx_buffer))
+ if (!nrfx_is_in_ram(p_tx_buffer) || !nrfx_is_word_aligned(p_tx_buffer))
{
return NRFX_ERROR_INVALID_ADDR;
}
nrf_qspi_write_buffer_set(NRF_QSPI, p_tx_buffer, tx_buffer_length, dst_address);
return qspi_task_perform(NRF_QSPI_TASK_WRITESTART);
-
}
nrfx_err_t nrfx_qspi_read(void * p_rx_buffer,
@@ -290,10 +365,8 @@ nrfx_err_t nrfx_qspi_read(void * p_rx_buffer,
{
NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
NRFX_ASSERT(p_rx_buffer != NULL);
- NRFX_ASSERT(nrfx_is_in_ram(p_rx_buffer));
- NRFX_ASSERT(nrfx_is_word_aligned(p_rx_buffer));
- if (!nrfx_is_in_ram(p_rx_buffer))
+ if (!nrfx_is_in_ram(p_rx_buffer) || !nrfx_is_word_aligned(p_rx_buffer))
{
return NRFX_ERROR_INVALID_ADDR;
}
@@ -306,6 +379,12 @@ nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length,
uint32_t start_address)
{
NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
+
+ if (!nrfx_is_word_aligned((void const *)start_address))
+ {
+ return NRFX_ERROR_INVALID_ADDR;
+ }
+
nrf_qspi_erase_ptr_set(NRF_QSPI, start_address, length);
return qspi_task_perform(NRF_QSPI_TASK_ERASESTART);
}
@@ -320,7 +399,7 @@ void nrfx_qspi_irq_handler(void)
// Catch Event ready interrupts
if (nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY))
{
- m_cb.interrupt_driven = false;
+ m_cb.is_busy = false;
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
m_cb.handler(NRFX_QSPI_EVENT_DONE, m_cb.p_context);
}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_temp.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_temp.c
new file mode 100644
index 000000000..a481df71f
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_temp.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+#if NRFX_CHECK(NRFX_TEMP_ENABLED)
+
+#include
+
+#if !defined(USE_WORKAROUND_FOR_TEMP_OFFSET_ANOMALY) && defined(NRF51)
+// Enable workaround for nRF51 series anomaly 28
+// (TEMP: Temperature offset value has to be manually loaded to the TEMP module).
+#define USE_WORKAROUND_FOR_TEMP_OFFSET_ANOMALY 1
+#endif
+
+/** @brief Time of one check attempt.*/
+#define NRFX_TEMP_TIME_US 4
+
+/** @brief Maximum attempts to check whether conversion passed.*/
+#define NRFX_TEMP_ATTEMPTS 10
+
+/** @brief Internal state of TEMP driver. */
+static nrfx_drv_state_t m_temp_state;
+
+/** @brief Pointer to handler to be called from interrupt routine. */
+static nrfx_temp_data_handler_t m_data_handler;
+
+nrfx_err_t nrfx_temp_init(nrfx_temp_config_t const * p_config, nrfx_temp_data_handler_t handler)
+{
+ NRFX_ASSERT(p_config);
+
+ if (m_temp_state != NRFX_DRV_STATE_UNINITIALIZED)
+ {
+ return NRFX_ERROR_ALREADY_INITIALIZED;
+ }
+
+#if NRFX_CHECK(USE_WORKAROUND_FOR_TEMP_OFFSET_ANOMALY)
+ *(uint32_t volatile *)0x4000C504 = 0;
+#endif
+
+ m_data_handler = handler;
+
+ if (m_data_handler)
+ {
+ nrf_temp_int_enable(NRF_TEMP, NRF_TEMP_INT_DATARDY_MASK);
+ NRFX_IRQ_PRIORITY_SET(TEMP_IRQn, p_config->interrupt_priority);
+ NRFX_IRQ_ENABLE(TEMP_IRQn);
+ }
+
+ m_temp_state = NRFX_DRV_STATE_INITIALIZED;
+ return NRFX_SUCCESS;
+}
+
+void nrfx_temp_uninit(void)
+{
+ NRFX_ASSERT(m_temp_state == NRFX_DRV_STATE_INITIALIZED);
+ nrf_temp_task_trigger(NRF_TEMP, NRF_TEMP_TASK_STOP);
+
+ if (m_data_handler)
+ {
+ nrf_temp_int_disable(NRF_TEMP, NRF_TEMP_INT_DATARDY_MASK);
+ NRFX_IRQ_DISABLE(TEMP_IRQn);
+ }
+
+ m_temp_state = NRFX_DRV_STATE_UNINITIALIZED;
+}
+
+int32_t nrfx_temp_calculate(int32_t raw_measurement)
+{
+ /* Raw temperature is a 2's complement signed value. Moreover, it is represented
+ * by 0.25[C] intervals, so division by 4 is needed. To preserve
+ * fractional part, raw value is multiplied by 100 before division.*/
+
+ return (raw_measurement * 100) / 4;
+}
+
+nrfx_err_t nrfx_temp_measure(void)
+{
+ NRFX_ASSERT(m_temp_state == NRFX_DRV_STATE_INITIALIZED);
+
+ nrfx_err_t result = NRFX_SUCCESS;
+ nrf_temp_event_clear(NRF_TEMP, NRF_TEMP_EVENT_DATARDY);
+ nrf_temp_task_trigger(NRF_TEMP, NRF_TEMP_TASK_START);
+
+ if (!m_data_handler)
+ {
+ bool ev_result;
+ NRFX_WAIT_FOR(nrf_temp_event_check(NRF_TEMP, NRF_TEMP_EVENT_DATARDY),
+ NRFX_TEMP_ATTEMPTS,
+ NRFX_TEMP_TIME_US,
+ ev_result);
+ if (!ev_result)
+ {
+ result = NRFX_ERROR_INTERNAL;
+ }
+ else
+ {
+ nrf_temp_event_clear(NRF_TEMP, NRF_TEMP_EVENT_DATARDY);
+ }
+ nrf_temp_task_trigger(NRF_TEMP, NRF_TEMP_TASK_STOP);
+ }
+
+ return result;
+}
+
+void nrfx_temp_irq_handler(void)
+{
+ NRFX_ASSERT(m_data_handler);
+
+ nrf_temp_task_trigger(NRF_TEMP, NRF_TEMP_TASK_STOP);
+ nrf_temp_event_clear(NRF_TEMP, NRF_TEMP_EVENT_DATARDY);
+
+ uint32_t raw_temp = nrfx_temp_result_get();
+
+ m_data_handler(raw_temp);
+}
+
+#endif // NRFX_CHECK(NRFX_TEMP_ENABLED)
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi.c
index a4e85d8ea..556316757 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi.c
@@ -48,7 +48,8 @@
(event == NRFX_TWI_EVT_DONE ? "EVT_DONE" : \
(event == NRFX_TWI_EVT_ADDRESS_NACK ? "EVT_ADDRESS_NACK" : \
(event == NRFX_TWI_EVT_DATA_NACK ? "EVT_DATA_NACK" : \
- "UNKNOWN ERROR")))
+ (event == NRFX_TWI_EVT_OVERRUN ? "EVT_OVERRUN" : \
+ "UNKNOWN ERROR"))))
#define EVT_TO_STR_TWI(event) \
(event == NRF_TWI_EVENT_STOPPED ? "NRF_TWI_EVENT_STOPPED" : \
@@ -73,8 +74,20 @@
NRF_GPIO_PIN_S0D1, \
NRF_GPIO_PIN_NOSENSE)
+#define TWI_FLAG_NO_STOP(flags) (flags & NRFX_TWI_FLAG_TX_NO_STOP)
+#define TWI_FLAG_SUSPEND(flags) (flags & NRFX_TWI_FLAG_SUSPEND)
+#define TWI_FLAG_NO_HANDLER_IN_USE(flags) (flags & NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER)
+
#define HW_TIMEOUT 100000
+/* TWI master driver suspend types. */
+typedef enum
+{
+ TWI_NO_SUSPEND, //< Last transfer was not suspended.
+ TWI_SUSPEND_TX, //< Last transfer was TX and was suspended.
+ TWI_SUSPEND_RX //< Last transfer was RX and was suspended.
+} twi_suspend_t;
+
// Control block - driver instance local data.
typedef struct
{
@@ -85,7 +98,8 @@ typedef struct
uint32_t flags;
uint8_t * p_curr_buf;
size_t curr_length;
- bool curr_no_stop;
+ bool curr_tx_no_stop;
+ twi_suspend_t prev_suspend;
nrfx_drv_state_t state;
bool error;
volatile bool busy;
@@ -162,6 +176,7 @@ nrfx_err_t nrfx_twi_init(nrfx_twi_t const * p_instance,
p_cb->handler = event_handler;
p_cb->p_context = p_context;
p_cb->int_mask = 0;
+ p_cb->prev_suspend = TWI_NO_SUSPEND;
p_cb->repeated = false;
p_cb->busy = false;
p_cb->hold_bus_uninit = p_config->hold_bus_uninit;
@@ -243,24 +258,27 @@ void nrfx_twi_disable(nrfx_twi_t const * p_instance)
NRFX_LOG_INFO("Instance disabled: %d.", p_instance->drv_inst_idx);
}
-static bool twi_send_byte(NRF_TWI_Type * p_twi,
- uint8_t const * p_data,
- size_t length,
- size_t * p_bytes_transferred,
- bool no_stop)
+static bool twi_send_byte(NRF_TWI_Type * p_twi,
+ twi_control_block_t * p_cb)
{
- if (*p_bytes_transferred < length)
+ if (p_cb->bytes_transferred < p_cb->curr_length)
{
- nrf_twi_txd_set(p_twi, p_data[*p_bytes_transferred]);
- ++(*p_bytes_transferred);
+ nrf_twi_txd_set(p_twi, p_cb->p_curr_buf[p_cb->bytes_transferred]);
+ ++(p_cb->bytes_transferred);
}
else
{
- if (no_stop)
+ if (p_cb->curr_tx_no_stop)
{
nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_SUSPEND);
return false;
}
+ else if(TWI_FLAG_SUSPEND(p_cb->flags))
+ {
+ nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_SUSPEND);
+ p_cb->prev_suspend = TWI_SUSPEND_TX;
+ return false;
+ }
else
{
nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
@@ -269,40 +287,40 @@ static bool twi_send_byte(NRF_TWI_Type * p_twi,
return true;
}
-static void twi_receive_byte(NRF_TWI_Type * p_twi,
- uint8_t * p_data,
- size_t length,
- size_t * p_bytes_transferred)
+static bool twi_receive_byte(NRF_TWI_Type * p_twi,
+ twi_control_block_t * p_cb)
{
- if (*p_bytes_transferred < length)
+ if (p_cb->bytes_transferred < p_cb->curr_length)
{
- p_data[*p_bytes_transferred] = nrf_twi_rxd_get(p_twi);
+ p_cb->p_curr_buf[p_cb->bytes_transferred] = nrf_twi_rxd_get(p_twi);
- ++(*p_bytes_transferred);
+ ++(p_cb->bytes_transferred);
- if (*p_bytes_transferred == length - 1)
+ if ((p_cb->bytes_transferred == p_cb->curr_length - 1) && (!TWI_FLAG_SUSPEND(p_cb->flags)))
{
nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_STOP_MASK);
}
- else if (*p_bytes_transferred == length)
+ else if (p_cb->bytes_transferred == p_cb->curr_length && (!TWI_FLAG_SUSPEND(p_cb->flags)))
{
- return;
+ return true;
+ }
+ else if (p_cb->bytes_transferred == p_cb->curr_length && TWI_FLAG_SUSPEND(p_cb->flags))
+ {
+ p_cb->prev_suspend = TWI_SUSPEND_RX;
+ return false;
}
nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);
}
+ return true;
}
-static bool twi_transfer(NRF_TWI_Type * p_twi,
- bool * p_error,
- size_t * p_bytes_transferred,
- uint8_t * p_data,
- size_t length,
- bool no_stop)
+static bool twi_transfer(NRF_TWI_Type * p_twi,
+ twi_control_block_t * p_cb)
{
- bool do_stop_check = ((*p_error) || ((*p_bytes_transferred) == length));
+ bool do_stop_check = ((p_cb->error) || ((p_cb->bytes_transferred) == p_cb->curr_length));
- if (*p_error)
+ if (p_cb->error)
{
nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
@@ -313,7 +331,7 @@ static bool twi_transfer(NRF_TWI_Type * p_twi,
nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_ERROR));
nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
- *p_error = true;
+ p_cb->error = true;
}
else
{
@@ -326,11 +344,11 @@ static bool twi_transfer(NRF_TWI_Type * p_twi,
nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_ERROR));
nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
- *p_error = true;
+ p_cb->error = true;
}
else
{
- if (!twi_send_byte(p_twi, p_data, length, p_bytes_transferred, no_stop))
+ if (!twi_send_byte(p_twi, p_cb))
{
return false;
}
@@ -345,11 +363,14 @@ static bool twi_transfer(NRF_TWI_Type * p_twi,
NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_ERROR));
nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
- *p_error = true;
+ p_cb->error = true;
}
else
{
- twi_receive_byte(p_twi, p_data, length, p_bytes_transferred);
+ if (!twi_receive_byte(p_twi, p_cb))
+ {
+ return false;
+ }
}
}
}
@@ -357,6 +378,7 @@ static bool twi_transfer(NRF_TWI_Type * p_twi,
if (do_stop_check && nrf_twi_event_check(p_twi, NRF_TWI_EVENT_STOPPED))
{
nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED);
+ p_cb->prev_suspend = TWI_NO_SUSPEND;
NRFX_LOG_DEBUG("TWI: Event: %s.", EVT_TO_STR_TWI(NRF_TWI_EVENT_STOPPED));
return false;
}
@@ -364,11 +386,8 @@ static bool twi_transfer(NRF_TWI_Type * p_twi,
return true;
}
-static nrfx_err_t twi_tx_start_transfer(twi_control_block_t * p_cb,
- NRF_TWI_Type * p_twi,
- uint8_t const * p_data,
- size_t length,
- bool no_stop)
+static nrfx_err_t twi_tx_start_transfer(NRF_TWI_Type * p_twi,
+ twi_control_block_t * p_cb)
{
nrfx_err_t ret_code = NRFX_SUCCESS;
volatile int32_t hw_timeout;
@@ -386,9 +405,13 @@ static nrfx_err_t twi_tx_start_transfer(twi_control_block_t * p_cb,
// In case TWI is suspended resume its operation.
nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);
- nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTTX);
- (void)twi_send_byte(p_twi, p_data, length, &p_cb->bytes_transferred, no_stop);
+ if (p_cb->prev_suspend != TWI_SUSPEND_TX)
+ {
+ nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTTX);
+ }
+
+ (void)twi_send_byte(p_twi, p_cb);
if (p_cb->handler)
{
@@ -396,17 +419,13 @@ static nrfx_err_t twi_tx_start_transfer(twi_control_block_t * p_cb,
NRF_TWI_INT_ERROR_MASK |
NRF_TWI_INT_TXDSENT_MASK |
NRF_TWI_INT_RXDREADY_MASK;
+
nrf_twi_int_enable(p_twi, p_cb->int_mask);
}
else
{
while ((hw_timeout > 0) &&
- twi_transfer(p_twi,
- &p_cb->error,
- &p_cb->bytes_transferred,
- (uint8_t *)p_data,
- length,
- no_stop))
+ twi_transfer(p_twi, p_cb))
{
hw_timeout--;
}
@@ -432,10 +451,8 @@ static nrfx_err_t twi_tx_start_transfer(twi_control_block_t * p_cb,
return ret_code;
}
-static nrfx_err_t twi_rx_start_transfer(twi_control_block_t * p_cb,
- NRF_TWI_Type * p_twi,
- uint8_t const * p_data,
- size_t length)
+static nrfx_err_t twi_rx_start_transfer(NRF_TWI_Type * p_twi,
+ twi_control_block_t * p_cb)
{
nrfx_err_t ret_code = NRFX_SUCCESS;
volatile int32_t hw_timeout;
@@ -450,7 +467,7 @@ static nrfx_err_t twi_rx_start_transfer(twi_control_block_t * p_cb,
p_cb->bytes_transferred = 0;
p_cb->error = false;
- if (length == 1)
+ if ((p_cb->curr_length == 1) && (!TWI_FLAG_SUSPEND(p_cb->flags)))
{
nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_STOP_MASK);
}
@@ -460,7 +477,11 @@ static nrfx_err_t twi_rx_start_transfer(twi_control_block_t * p_cb,
}
// In case TWI is suspended resume its operation.
nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);
- nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTRX);
+
+ if (p_cb->prev_suspend != TWI_SUSPEND_RX)
+ {
+ nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTRX);
+ }
if (p_cb->handler)
{
@@ -473,12 +494,7 @@ static nrfx_err_t twi_rx_start_transfer(twi_control_block_t * p_cb,
else
{
while ((hw_timeout > 0) &&
- twi_transfer(p_twi,
- &p_cb->error,
- &p_cb->bytes_transferred,
- (uint8_t*)p_data,
- length,
- false))
+ twi_transfer(p_twi, p_cb))
{
hw_timeout--;
}
@@ -502,14 +518,25 @@ static nrfx_err_t twi_rx_start_transfer(twi_control_block_t * p_cb,
return ret_code;
}
-__STATIC_INLINE nrfx_err_t twi_xfer(twi_control_block_t * p_cb,
- NRF_TWI_Type * p_twi,
+__STATIC_INLINE nrfx_err_t twi_xfer(NRF_TWI_Type * p_twi,
+ twi_control_block_t * p_cb,
nrfx_twi_xfer_desc_t const * p_xfer_desc,
uint32_t flags)
{
nrfx_err_t err_code = NRFX_SUCCESS;
+ if ((p_cb->prev_suspend == TWI_SUSPEND_TX) && (p_xfer_desc->type == NRFX_TWI_XFER_RX))
+ {
+ /* RX is invalid after TX suspend */
+ return NRFX_ERROR_INVALID_STATE;
+ }
+ else if ((p_cb->prev_suspend == TWI_SUSPEND_RX) && (p_xfer_desc->type != NRFX_TWI_XFER_RX))
+ {
+ /* TX, TXRX and TXTX are invalid after RX suspend */
+ return NRFX_ERROR_INVALID_STATE;
+ }
+
/* Block TWI interrupts to ensure that function is not interrupted by TWI interrupt. */
nrf_twi_int_disable(p_twi, NRF_TWI_ALL_INTS_MASK);
@@ -524,7 +551,7 @@ __STATIC_INLINE nrfx_err_t twi_xfer(twi_control_block_t * p_cb,
}
else
{
- p_cb->busy = (NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER & flags) ? false : true;
+ p_cb->busy = (TWI_FLAG_NO_HANDLER_IN_USE(flags)) ? false : true;
}
p_cb->flags = flags;
@@ -535,23 +562,14 @@ __STATIC_INLINE nrfx_err_t twi_xfer(twi_control_block_t * p_cb,
if (p_xfer_desc->type != NRFX_TWI_XFER_RX)
{
- p_cb->curr_no_stop = ((p_xfer_desc->type == NRFX_TWI_XFER_TX) &&
- !(flags & NRFX_TWI_FLAG_TX_NO_STOP)) ? false : true;
+ p_cb->curr_tx_no_stop = ((p_xfer_desc->type == NRFX_TWI_XFER_TX) &&
+ !(flags & NRFX_TWI_FLAG_TX_NO_STOP)) ? false : true;
- err_code = twi_tx_start_transfer(p_cb,
- p_twi,
- p_xfer_desc->p_primary_buf,
- p_xfer_desc->primary_length,
- p_cb->curr_no_stop);
+ err_code = twi_tx_start_transfer(p_twi, p_cb);
}
else
{
- p_cb->curr_no_stop = false;
-
- err_code = twi_rx_start_transfer(p_cb,
- p_twi,
- p_xfer_desc->p_primary_buf,
- p_xfer_desc->primary_length);
+ err_code = twi_rx_start_transfer(p_twi, p_cb);
}
if (p_cb->handler == NULL)
{
@@ -589,7 +607,7 @@ nrfx_err_t nrfx_twi_xfer(nrfx_twi_t const * p_instance,
NRFX_LOG_HEXDUMP_DEBUG(p_xfer_desc->p_secondary_buf,
p_xfer_desc->secondary_length * sizeof(p_xfer_desc->p_secondary_buf[0]));
- err_code = twi_xfer(p_cb, (NRF_TWI_Type *)p_instance->p_twi, p_xfer_desc, flags);
+ err_code = twi_xfer((NRF_TWI_Type *)p_instance->p_twi, p_cb, p_xfer_desc, flags);
NRFX_LOG_WARNING("Function: %s, error code: %s.",
__func__,
NRFX_LOG_ERROR_STRING_GET(err_code));
@@ -603,7 +621,6 @@ nrfx_err_t nrfx_twi_tx(nrfx_twi_t const * p_instance,
bool no_stop)
{
nrfx_twi_xfer_desc_t xfer = NRFX_TWI_XFER_DESC_TX(address, (uint8_t*)p_data, length);
-
return nrfx_twi_xfer(p_instance, &xfer, no_stop ? NRFX_TWI_FLAG_TX_NO_STOP : 0);
}
@@ -630,12 +647,7 @@ static void twi_irq_handler(NRF_TWI_Type * p_twi, twi_control_block_t * p_cb)
{
NRFX_ASSERT(p_cb->handler);
- if (twi_transfer(p_twi,
- &p_cb->error,
- &p_cb->bytes_transferred,
- p_cb->p_curr_buf,
- p_cb->curr_length,
- p_cb->curr_no_stop ))
+ if (twi_transfer(p_twi, p_cb))
{
return;
}
@@ -645,21 +657,18 @@ static void twi_irq_handler(NRF_TWI_Type * p_twi, twi_control_block_t * p_cb)
(p_cb->xfer_desc.type == NRFX_TWI_XFER_TXTX)) &&
p_cb->p_curr_buf == p_cb->xfer_desc.p_primary_buf)
{
- p_cb->p_curr_buf = p_cb->xfer_desc.p_secondary_buf;
- p_cb->curr_length = p_cb->xfer_desc.secondary_length;
- p_cb->curr_no_stop = (p_cb->flags & NRFX_TWI_FLAG_TX_NO_STOP);
+ p_cb->p_curr_buf = p_cb->xfer_desc.p_secondary_buf;
+ p_cb->curr_length = p_cb->xfer_desc.secondary_length;
+ p_cb->curr_tx_no_stop = (p_cb->flags & NRFX_TWI_FLAG_TX_NO_STOP);
+ p_cb->prev_suspend = TWI_NO_SUSPEND;
if (p_cb->xfer_desc.type == NRFX_TWI_XFER_TXTX)
{
- (void)twi_tx_start_transfer(p_cb,
- p_twi,
- p_cb->p_curr_buf,
- p_cb->curr_length,
- p_cb->curr_no_stop);
+ (void)twi_tx_start_transfer(p_twi, p_cb);
}
else
{
- (void)twi_rx_start_transfer(p_cb, p_twi, p_cb->p_curr_buf, p_cb->curr_length);
+ (void)twi_rx_start_transfer(p_twi, p_cb);
}
}
else
@@ -680,6 +689,11 @@ static void twi_irq_handler(NRF_TWI_Type * p_twi, twi_control_block_t * p_cb)
event.type = NRFX_TWI_EVT_DATA_NACK;
NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_DATA_NACK));
}
+ else if (errorsrc & NRF_TWI_ERROR_OVERRUN)
+ {
+ event.type = NRFX_TWI_EVT_OVERRUN;
+ NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_OVERRUN));
+ }
}
else
{
@@ -689,7 +703,7 @@ static void twi_irq_handler(NRF_TWI_Type * p_twi, twi_control_block_t * p_cb)
p_cb->busy = false;
- if (!(NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER & p_cb->flags))
+ if (!(TWI_FLAG_NO_HANDLER_IN_USE(p_cb->flags)))
{
p_cb->handler(&event, p_cb->p_context);
}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi_twim.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi_twim.c
new file mode 100644
index 000000000..ca6fc1643
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twi_twim.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+
+#define TWI_TWIM_PIN_CONFIGURE(_pin) nrf_gpio_cfg((_pin), \
+ NRF_GPIO_PIN_DIR_OUTPUT, \
+ NRF_GPIO_PIN_INPUT_CONNECT, \
+ NRF_GPIO_PIN_PULLUP, \
+ NRF_GPIO_PIN_S0D1, \
+ NRF_GPIO_PIN_NOSENSE)
+
+nrfx_err_t nrfx_twi_twim_bus_recover(uint32_t scl_pin, uint32_t sda_pin)
+{
+ nrf_gpio_pin_set(scl_pin);
+ nrf_gpio_pin_set(sda_pin);
+
+ TWI_TWIM_PIN_CONFIGURE(scl_pin);
+ TWI_TWIM_PIN_CONFIGURE(sda_pin);
+ NRFX_DELAY_US(4);
+
+ for (uint8_t i = 0; i < 9; i++)
+ {
+ if (nrf_gpio_pin_read(sda_pin))
+ {
+ break;
+ }
+ else
+ {
+ // Pulse CLOCK signal
+ nrf_gpio_pin_clear(scl_pin);
+ NRFX_DELAY_US(4);
+ nrf_gpio_pin_set(scl_pin);
+ NRFX_DELAY_US(4);
+ }
+ }
+
+ // Generate a STOP condition on the bus
+ nrf_gpio_pin_clear(sda_pin);
+ NRFX_DELAY_US(4);
+ nrf_gpio_pin_set(sda_pin);
+ NRFX_DELAY_US(4);
+
+ if (nrf_gpio_pin_read(sda_pin))
+ {
+ return NRFX_SUCCESS;
+ }
+ else
+ {
+ return NRFX_ERROR_INTERNAL;
+ }
+}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twim.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twim.c
index 69f1974f5..e6089966f 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twim.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twim.c
@@ -139,6 +139,11 @@ static nrfx_err_t twi_process_error(uint32_t errorsrc)
{
nrfx_err_t ret = NRFX_ERROR_INTERNAL;
+ if (errorsrc & NRF_TWIM_ERROR_OVERRUN)
+ {
+ ret = NRFX_ERROR_DRV_TWI_ERR_OVERRUN;
+ }
+
if (errorsrc & NRF_TWIM_ERROR_ADDRESS_NACK)
{
ret = NRFX_ERROR_DRV_TWI_ERR_ANACK;
@@ -152,6 +157,58 @@ static nrfx_err_t twi_process_error(uint32_t errorsrc)
return ret;
}
+static bool xfer_completeness_check(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb)
+{
+ // If the actual number of transferred bytes is not equal to what was requested,
+ // but there was no error signaled by the peripheral, this means that something
+ // unexpected, like a premature STOP condition, happened on the bus.
+ // In such case the peripheral has to be disabled and re-enabled, so that its
+ // internal state machine is reinitialized.
+
+ bool transfer_complete = true;
+ switch (p_cb->xfer_desc.type)
+ {
+ case NRFX_TWIM_XFER_TXTX:
+ if (((p_cb->int_mask == (NRF_TWIM_INT_SUSPENDED_MASK | NRF_TWIM_INT_ERROR_MASK)) &&
+ (nrf_twim_txd_amount_get(p_twim) != p_cb->xfer_desc.primary_length)) ||
+ ((p_cb->int_mask == (NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK)) &&
+ (nrf_twim_txd_amount_get(p_twim) != p_cb->xfer_desc.secondary_length)))
+ {
+ transfer_complete = false;
+ }
+ break;
+ case NRFX_TWIM_XFER_TXRX:
+ if ((nrf_twim_txd_amount_get(p_twim) != p_cb->xfer_desc.primary_length) ||
+ (nrf_twim_rxd_amount_get(p_twim) != p_cb->xfer_desc.secondary_length))
+ {
+ transfer_complete = false;
+ }
+ break;
+ case NRFX_TWIM_XFER_TX:
+ if (nrf_twim_txd_amount_get(p_twim) != p_cb->xfer_desc.primary_length)
+ {
+ transfer_complete = false;
+ }
+ break;
+ case NRFX_TWIM_XFER_RX:
+ if (nrf_twim_rxd_amount_get(p_twim) != p_cb->xfer_desc.primary_length)
+ {
+ transfer_complete = false;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (!transfer_complete)
+ {
+ nrf_twim_disable(p_twim);
+ nrf_twim_enable(p_twim);
+ }
+
+ return transfer_complete;
+}
+
nrfx_err_t nrfx_twim_init(nrfx_twim_t const * p_instance,
nrfx_twim_config_t const * p_config,
nrfx_twim_evt_handler_t event_handler,
@@ -320,6 +377,7 @@ __STATIC_INLINE nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
nrfx_err_t err_code = NRFX_SUCCESS;
nrf_twim_task_t start_task = NRF_TWIM_TASK_STARTTX;
nrf_twim_event_t evt_to_wait = NRF_TWIM_EVENT_STOPPED;
+ p_cb->error = false;
if (!nrfx_is_in_ram(p_xfer_desc->p_primary_buf))
{
@@ -473,6 +531,13 @@ __STATIC_INLINE nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
{
err_code = twi_process_error(errorsrc);
}
+ else
+ {
+ if (!xfer_completeness_check(p_twim, p_cb))
+ {
+ err_code = NRFX_ERROR_INTERNAL;
+ }
+ }
}
return err_code;
}
@@ -583,6 +648,8 @@ static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb
nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP);
+
+ p_cb->error = true;
return;
}
}
@@ -594,14 +661,9 @@ static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb
NRFX_LOG_DEBUG("TWIM: Event: %s.", EVT_TO_STR_TWIM(NRF_TWIM_EVENT_STOPPED));
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_STOPPED);
event.xfer_desc = p_cb->xfer_desc;
- if (p_cb->error)
+ if (!p_cb->error)
{
-
- event.xfer_desc.primary_length = (p_cb->xfer_desc.type == NRFX_TWIM_XFER_RX) ?
- nrf_twim_rxd_amount_get(p_twim) : nrf_twim_txd_amount_get(p_twim);
- event.xfer_desc.secondary_length = (p_cb->xfer_desc.type == NRFX_TWIM_XFER_TXRX) ?
- nrf_twim_rxd_amount_get(p_twim) : nrf_twim_txd_amount_get(p_twim);
-
+ p_cb->error = !xfer_completeness_check(p_twim, p_cb);
}
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX);
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTRX);
@@ -649,9 +711,21 @@ static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb
event.type = NRFX_TWIM_EVT_DATA_NACK;
NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWIM_EVT_DATA_NACK));
}
+ else if (errorsrc & NRF_TWIM_ERROR_OVERRUN)
+ {
+ event.type = NRFX_TWIM_EVT_DATA_NACK;
+ NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWIM_EVT_DATA_NACK));
+ }
else
{
- event.type = NRFX_TWIM_EVT_DONE;
+ if (p_cb->error)
+ {
+ event.type = NRFX_TWIM_EVT_BUS_ERROR;
+ }
+ else
+ {
+ event.type = NRFX_TWIM_EVT_DONE;
+ }
NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWIM_EVT_DONE));
}
@@ -659,6 +733,7 @@ static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb
{
p_cb->busy = false;
}
+
p_cb->handler(&event, p_cb->p_context);
}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twis.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twis.c
index 09c875c4a..10b827f13 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twis.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_twis.c
@@ -730,7 +730,7 @@ nrfx_err_t nrfx_twis_tx_prepare(nrfx_twis_t const * p_instance,
nrf_twis_tx_prepare(p_instance->p_reg,
(uint8_t const *)p_buf,
- (nrf_twis_amount_t)size);
+ size);
err_code = NRFX_SUCCESS;
NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
@@ -774,7 +774,7 @@ nrfx_err_t nrfx_twis_rx_prepare(nrfx_twis_t const * p_instance,
nrf_twis_rx_prepare(p_instance->p_reg,
(uint8_t *)p_buf,
- (nrf_twis_amount_t)size);
+ size);
err_code = NRFX_SUCCESS;
NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uart.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uart.c
index 8e3c37715..709038c23 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uart.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uart.c
@@ -58,7 +58,7 @@ typedef struct
uint8_t const * p_tx_buffer;
uint8_t * p_rx_buffer;
uint8_t * p_rx_secondary_buffer;
- size_t tx_buffer_length;
+ volatile size_t tx_buffer_length;
size_t rx_buffer_length;
size_t rx_secondary_buffer_length;
volatile size_t tx_counter;
@@ -242,7 +242,10 @@ static void tx_byte(NRF_UART_Type * p_uart, uart_control_block_t * p_cb)
static bool tx_blocking(NRF_UART_Type * p_uart, uart_control_block_t * p_cb)
{
- while (p_cb->tx_counter < p_cb->tx_buffer_length)
+ // Use a local variable to avoid undefined order of accessing two volatile variables
+ // in one statement.
+ size_t const tx_buffer_length = p_cb->tx_buffer_length;
+ while (p_cb->tx_counter < tx_buffer_length)
{
// Wait until the transmitter is ready to accept a new byte.
// Exit immediately if the transfer has been aborted.
@@ -598,8 +601,10 @@ static void uart_irq_handler(NRF_UART_Type * p_uart,
if (nrf_uart_event_check(p_uart, NRF_UART_EVENT_TXDRDY))
{
- if (p_cb->tx_counter < p_cb->tx_buffer_length &&
- !p_cb->tx_abort)
+ // Use a local variable to avoid undefined order of accessing two volatile variables
+ // in one statement.
+ size_t const tx_buffer_length = p_cb->tx_buffer_length;
+ if (p_cb->tx_counter < tx_buffer_length && !p_cb->tx_abort)
{
tx_byte(p_uart, p_cb);
}
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uarte.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uarte.c
index a74ac6e48..8d2d21be5 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uarte.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_uarte.c
@@ -85,7 +85,6 @@
UARTE2_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \
UARTE3_LENGTH_VALIDATE(drv_inst_idx, length, 0))
-
typedef struct
{
void * p_context;
@@ -138,10 +137,12 @@ static void interrupts_enable(nrfx_uarte_t const * p_instance,
nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX);
nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ERROR);
nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_RXTO);
+ nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED);
nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ENDRX_MASK |
NRF_UARTE_INT_ENDTX_MASK |
NRF_UARTE_INT_ERROR_MASK |
- NRF_UARTE_INT_RXTO_MASK);
+ NRF_UARTE_INT_RXTO_MASK |
+ NRF_UARTE_INT_TXSTOPPED_MASK);
NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number((void *)p_instance->p_reg),
interrupt_priority);
NRFX_IRQ_ENABLE(nrfx_get_irq_number((void *)p_instance->p_reg));
@@ -152,7 +153,8 @@ static void interrupts_disable(nrfx_uarte_t const * p_instance)
nrf_uarte_int_disable(p_instance->p_reg, NRF_UARTE_INT_ENDRX_MASK |
NRF_UARTE_INT_ENDTX_MASK |
NRF_UARTE_INT_ERROR_MASK |
- NRF_UARTE_INT_RXTO_MASK);
+ NRF_UARTE_INT_RXTO_MASK |
+ NRF_UARTE_INT_TXSTOPPED_MASK);
NRFX_IRQ_DISABLE(nrfx_get_irq_number((void *)p_instance->p_reg));
}
@@ -257,13 +259,20 @@ void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance)
{
uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
- nrf_uarte_disable(p_instance->p_reg);
-
if (p_cb->handler)
{
interrupts_disable(p_instance);
}
+ // Make sure all transfers are finished before UARTE is disabled
+ // to achieve the lowest power consumption.
+ nrf_uarte_shorts_disable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX);
+ nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX);
+ nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED);
+ nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPTX);
+ while (!nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED))
+ {}
+ nrf_uarte_disable(p_instance->p_reg);
pins_to_default(p_instance);
#if NRFX_CHECK(NRFX_PRS_ENABLED)
@@ -336,6 +345,15 @@ nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance,
{
err_code = NRFX_ERROR_FORBIDDEN;
}
+ else
+ {
+ // Transmitter has to be stopped by triggering the STOPTX task to achieve
+ // the lowest possible level of the UARTE power consumption.
+ nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPTX);
+
+ while (!nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED))
+ {}
+ }
p_cb->tx_buffer_length = 0;
}
@@ -585,6 +603,20 @@ static void uarte_irq_handler(NRF_UARTE_Type * p_uarte,
if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDTX))
{
nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDTX);
+
+ // Transmitter has to be stopped by triggering STOPTX task to achieve
+ // the lowest possible level of the UARTE power consumption.
+ nrf_uarte_task_trigger(p_uarte, NRF_UARTE_TASK_STOPTX);
+
+ if (p_cb->tx_buffer_length != 0)
+ {
+ tx_done_event(p_cb, nrf_uarte_tx_amount_get(p_uarte));
+ }
+ }
+
+ if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_TXSTOPPED))
+ {
+ nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_TXSTOPPED);
if (p_cb->tx_buffer_length != 0)
{
tx_done_event(p_cb, nrf_uarte_tx_amount_get(p_uarte));
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_usbd.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_usbd.c
index 302ae9b44..5827b17d5 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_usbd.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_usbd.c
@@ -1155,6 +1155,25 @@ static void usbd_ep_data_handler(nrfx_usbd_ep_t ep, uint8_t bitpos)
if (NRF_USBD_EPIN_CHECK(ep))
{
/* IN endpoint (Device -> Host) */
+
+ /* Secure against the race condition that occurs when an IN transfer is interrupted
+ * by an OUT transaction, which in turn is interrupted by a process with higher priority.
+ * If the IN events ENDEPIN and EPDATA arrive during that high priority process,
+ * the OUT handler might call usbd_ep_data_handler without calling
+ * nrf_usbd_epin_dma_handler (or nrf_usbd_ep0in_dma_handler) for the IN transaction.
+ */
+ if (nrf_usbd_event_get_and_clear(nrfx_usbd_ep_to_endevent(ep)))
+ {
+ if (ep != NRFX_USBD_EPIN0)
+ {
+ nrf_usbd_epin_dma_handler(ep);
+ }
+ else
+ {
+ nrf_usbd_ep0in_dma_handler();
+ }
+ }
+
if (0 == (m_ep_dma_waiting & (1U << bitpos)))
{
NRFX_LOG_DEBUG("USBD event: EndpointData: In finished");
@@ -1199,7 +1218,7 @@ static void ev_setup_handler(void)
}
m_last_setup_dir =
- ((bmRequestType & USBD_BMREQUESTTYPE_DIRECTION_Msk) ==
+ ((bmRequestType & USBD_BMREQUESTTYPE_DIRECTION_Msk) ==
(USBD_BMREQUESTTYPE_DIRECTION_HostToDevice << USBD_BMREQUESTTYPE_DIRECTION_Pos)) ?
NRFX_USBD_EPOUT0 : NRFX_USBD_EPIN0;
@@ -1466,7 +1485,8 @@ static void usbd_dmareq_process(void)
/* There is a lot of USBD registers that cannot be accessed during EasyDMA transfer.
* This is quick fix to maintain stability of the stack.
* It cost some performance but makes stack stable. */
- while (!nrf_usbd_event_check(nrfx_usbd_ep_to_endevent(ep)))
+ while (!nrf_usbd_event_check(nrfx_usbd_ep_to_endevent(ep)) &&
+ !nrf_usbd_event_check(NRF_USBD_EVENT_USBRESET))
{
/* Empty */
}
@@ -1725,7 +1745,7 @@ void nrfx_usbd_enable(void)
}
NRFX_CRITICAL_SECTION_EXIT();
}
-
+
if (nrfx_usbd_errata_171())
{
NRFX_CRITICAL_SECTION_ENTER();
@@ -1750,7 +1770,7 @@ void nrfx_usbd_enable(void)
/* Empty loop */
}
nrf_usbd_eventcause_clear(NRF_USBD_EVENTCAUSE_READY_MASK);
-
+
if (nrfx_usbd_errata_171())
{
NRFX_CRITICAL_SECTION_ENTER();
@@ -1979,7 +1999,9 @@ void nrfx_usbd_force_bus_wakeup(void)
void nrfx_usbd_ep_max_packet_size_set(nrfx_usbd_ep_t ep, uint16_t size)
{
/* Only power of 2 size allowed */
- NRFX_ASSERT((size != 0) && (size & (size - 1)) == 0);
+ NRFX_ASSERT((size & 0x01) == 0);
+ /* 0 allowed only for ISO endpoints */
+ NRFX_ASSERT((size != 0) || NRF_USBD_EPISO_CHECK(ep));
/* Packet size cannot be higher than maximum buffer size */
NRFX_ASSERT((NRF_USBD_EPISO_CHECK(ep) && (size <= usbd_ep_iso_capacity(ep))) ||
(!NRF_USBD_EPISO_CHECK(ep) && (size <= NRFX_USBD_EPSIZE)));
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_usbd_errata.h b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_usbd_errata.h
index fb2185253..c50d9dec3 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_usbd_errata.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_usbd_errata.h
@@ -45,69 +45,104 @@
static inline bool nrfx_usbd_errata_type_52840(void)
{
- return (*(uint32_t *)0x10000130UL == 0x8UL);
+ return (*(uint32_t const *)0x10000130UL == 0x8UL);
}
-static inline bool nrfx_usbd_errata_type_52840_eng_a(void)
+static inline bool nrfx_usbd_errata_type_52840_eng_a_or_later(void)
{
return nrfx_usbd_errata_type_52840();
}
-static inline bool nrfx_usbd_errata_type_52840_eng_b(void)
+static inline bool nrfx_usbd_errata_type_52840_eng_b_or_later(void)
{
- return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL >= 0x1UL));
+ return (nrfx_usbd_errata_type_52840() && (*(uint32_t const *)0x10000134UL >= 0x1UL));
}
-static inline bool nrfx_usbd_errata_type_52840_eng_c(void)
+static inline bool nrfx_usbd_errata_type_52840_eng_c_or_later(void)
{
- return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL >= 0x2UL));
+ return (nrfx_usbd_errata_type_52840() && (*(uint32_t const *)0x10000134UL >= 0x2UL));
}
-static inline bool nrfx_usbd_errata_type_52840_eng_d(void)
+static inline bool nrfx_usbd_errata_type_52840_eng_d_or_later(void)
{
- return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL >= 0x3UL));
+ return (nrfx_usbd_errata_type_52840() && (*(uint32_t const *)0x10000134UL >= 0x3UL));
}
-/* Errata: USBD: EPDATA event is not always generated. */
+static inline bool nrfx_usbd_errata_type_52833(void)
+{
+ return (*(uint32_t const *)0x10000130UL == 0x0DUL);
+}
+
+static inline bool nrfx_usbd_errata_type_52833_eng_a_or_later(void)
+{
+ return nrfx_usbd_errata_type_52833();
+}
+
+/* Errata: USBD: EPDATA event is not always generated.
+ *
+ * Applies to nRF52840 Engineering A.
+ **/
static inline bool nrfx_usbd_errata_104(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && (!nrfx_usbd_errata_type_52840_eng_b()));
+ return (NRFX_USBD_ERRATA_ENABLE && (nrfx_usbd_errata_type_52840()
+ && !nrfx_usbd_errata_type_52840_eng_b_or_later()));
}
-/* Errata: During setup read/write transfer USBD acknowledges setup stage without SETUP task. */
+/* Errata: During setup read/write transfer USBD acknowledges setup stage without SETUP task.
+ *
+ * Applies to nRF52840 Engineering A.
+ **/
static inline bool nrfx_usbd_errata_154(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && (!nrfx_usbd_errata_type_52840_eng_b()));
+ return (NRFX_USBD_ERRATA_ENABLE && (nrfx_usbd_errata_type_52840()
+ && !nrfx_usbd_errata_type_52840_eng_b_or_later()));
}
-/* Errata: ISO double buffering not functional. */
+/* Errata: ISO double buffering not functional.
+ *
+ * Applies to nRF52840.
+ **/
static inline bool nrfx_usbd_errata_166(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && true);
+ return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840());
}
-/* Errata: USBD might not reach its active state. */
+/* Errata: USBD might not reach its active state.
+ *
+ * Applies to nRF52840.
+ **/
static inline bool nrfx_usbd_errata_171(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && true);
+ return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840());
}
-/* Errata: USB cannot be enabled. */
+/* Errata: USB cannot be enabled.
+ *
+ * Applies to nRF52840 Engineering B or later and nRF52833.
+ **/
static inline bool nrfx_usbd_errata_187(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_b());
+ return (NRFX_USBD_ERRATA_ENABLE && (nrfx_usbd_errata_type_52840_eng_b_or_later()
+ || nrfx_usbd_errata_type_52833()));
}
-/* Errata: USBD cannot receive tasks during DMA. */
+/* Errata: USBD cannot receive tasks during DMA.
+ *
+ * Applies to nRF52840.
+ **/
static inline bool nrfx_usbd_errata_199(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && true);
+ return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840());
}
-/* Errata: SIZE.EPOUT not writable. */
+/* Errata: SIZE.EPOUT not writable.
+ *
+ * Applies to nRF52840 Engineering A.
+ **/
static inline bool nrfx_usbd_errata_200(void)
{
- return (NRFX_USBD_ERRATA_ENABLE && (!nrfx_usbd_errata_type_52840_eng_b()));
+ return (NRFX_USBD_ERRATA_ENABLE && (nrfx_usbd_errata_type_52840()
+ && !nrfx_usbd_errata_type_52840_eng_b_or_later()));
}
#endif // NRFX_USBD_ERRATA_H__
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_wdt.c b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_wdt.c
index feb9a3c33..ffd85b769 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_wdt.c
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/nrfx_wdt.c
@@ -87,7 +87,10 @@ nrfx_err_t nrfx_wdt_init(nrfx_wdt_config_t const * p_config,
nrf_wdt_behaviour_set(p_config->behaviour);
- nrf_wdt_reload_value_set((p_config->reload_value * 32768) / 1000);
+ uint64_t ticks = (p_config->reload_value * 32768ULL) / 1000;
+ NRFX_ASSERT(ticks <= UINT32_MAX);
+
+ nrf_wdt_reload_value_set((uint32_t) ticks);
#if !NRFX_CHECK(NRFX_WDT_CONFIG_NO_IRQ)
NRFX_IRQ_PRIORITY_SET(WDT_IRQn, p_config->interrupt_priority);
diff --git a/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.h b/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.h
index 33003c8af..5641f71b8 100644
--- a/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.h
+++ b/third_party/NordicSemiconductor/nrfx/drivers/src/prs/nrfx_prs.h
@@ -65,18 +65,8 @@ extern "C" {
#define NRFX_PRS_BOX_1_ADDR NRF_SPIM0
// UART0, UARTE0
#define NRFX_PRS_BOX_2_ADDR NRF_UART0
-#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
- // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0
- #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0
- // SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1
- #define NRFX_PRS_BOX_1_ADDR NRF_SPIM1
- // SPIM2, SPIS2, SPI2
- #define NRFX_PRS_BOX_2_ADDR NRF_SPIM2
- // COMP, LPCOMP
- #define NRFX_PRS_BOX_3_ADDR NRF_COMP
- // UARTE0, UART0
- #define NRFX_PRS_BOX_4_ADDR NRF_UARTE0
-#elif defined(NRF52840_XXAA)
+#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
+ defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
// SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0
#define NRFX_PRS_BOX_0_ADDR NRF_SPIM0
// SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1
@@ -133,6 +123,7 @@ nrfx_err_t nrfx_prs_acquire(void const * p_base_addr,
*/
void nrfx_prs_release(void const * p_base_addr);
+/** @} */
void nrfx_prs_box_0_irq_handler(void);
void nrfx_prs_box_1_irq_handler(void);
@@ -140,7 +131,6 @@ void nrfx_prs_box_2_irq_handler(void);
void nrfx_prs_box_3_irq_handler(void);
void nrfx_prs_box_4_irq_handler(void);
-/** @} */
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_aar.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_aar.h
new file mode 100644
index 000000000..3c2af2ccb
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_aar.h
@@ -0,0 +1,376 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRF_AAR_H__
+#define NRF_AAR_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_aar_hal AAR HAL
+ * @{
+ * @ingroup nrf_aar
+ * @brief Hardware access layer for managing the Accelerated Address Resolver (AAR) peripheral.
+ */
+
+/** @brief AAR events. */
+typedef enum
+{
+ NRF_AAR_EVENT_END = offsetof(NRF_AAR_Type, EVENTS_END), ///< Address resolution procedure complete.
+ NRF_AAR_EVENT_RESOLVED = offsetof(NRF_AAR_Type, EVENTS_RESOLVED), ///< Address resolved.
+ NRF_AAR_EVENT_NOTRESOLVED = offsetof(NRF_AAR_Type, EVENTS_NOTRESOLVED), ///< Address not resolved.
+} nrf_aar_event_t;
+
+/** @brief AAR interrupts. */
+typedef enum
+{
+ NRF_AAR_INT_END_MASK = AAR_INTENSET_END_Msk, ///< Interrupt on END event.
+ NRF_AAR_INT_RESOLVED_MASK = AAR_INTENSET_RESOLVED_Msk, ///< Interrupt on RESOLVED event.
+ NRF_AAR_INT_NOTRESOLVED_MASK = AAR_INTENSET_NOTRESOLVED_Msk, ///< Interrupt on NOTRESOLVED event.
+} nrf_aar_int_mask_t;
+
+/** @brief AAR tasks. */
+typedef enum
+{
+ NRF_AAR_TASK_START = offsetof(NRF_AAR_Type, TASKS_START), ///< Start address resolution procedure.
+ NRF_AAR_TASK_STOP = offsetof(NRF_AAR_Type, TASKS_STOP), ///< Stop address resolution procedure.
+} nrf_aar_task_t;
+
+/**
+ * @brief Function for retrieving the state of the AAR event.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
+ *
+ * @retval true Event is set.
+ * @retval false Event is not set.
+ */
+__STATIC_INLINE bool nrf_aar_event_check(NRF_AAR_Type const * p_reg,
+ nrf_aar_event_t event);
+
+/**
+ * @brief Function for clearing the specified AAR event.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be cleared.
+ */
+__STATIC_INLINE void nrf_aar_event_clear(NRF_AAR_Type * p_reg,
+ nrf_aar_event_t event);
+
+/**
+ * @brief Function for getting the address of the specified AAR event register.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to get the address of.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_aar_event_address_get(NRF_AAR_Type const * p_reg,
+ nrf_aar_event_t event);
+
+/**
+ * @brief Function for enabling the specified interrupts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
+ */
+__STATIC_INLINE void nrf_aar_int_enable(NRF_AAR_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for retrieving the state of the specified interrupt.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of the interrupt to be checked.
+ *
+ * @retval true Interrupt is enabled.
+ * @retval false Interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_aar_int_enable_check(NRF_AAR_Type const * p_reg,
+ nrf_aar_int_mask_t mask);
+
+/**
+ * @brief Function for disabling the specified interrupts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
+ */
+__STATIC_INLINE void nrf_aar_int_disable(NRF_AAR_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for starting an AAR task.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param task Task to be activated.
+ */
+__STATIC_INLINE void nrf_aar_task_trigger(NRF_AAR_Type * p_reg, nrf_aar_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific AAR task register.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param task Requested AAR task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_aar_task_address_get(NRF_AAR_Type const * p_reg,
+ nrf_aar_task_t task);
+
+/**
+ * @brief Function for enabling AAR.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ */
+__STATIC_INLINE void nrf_aar_enable(NRF_AAR_Type * p_reg);
+
+/**
+ * @brief Function for disabling AAR.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ */
+__STATIC_INLINE void nrf_aar_disable(NRF_AAR_Type * p_reg);
+
+/**
+ * @brief Function for setting the pointer to the Identity Resolving Keys (IRK) data structure.
+ *
+ * The size of the provided data structure must correspond to the number of keys available.
+ * Each key occupies 16 bytes.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param irk_ptr Pointer to the IRK data structure. Must point to the Data RAM region.
+ *
+ * @sa nrf_aar_irk_number_set
+ */
+__STATIC_INLINE void nrf_aar_irk_pointer_set(NRF_AAR_Type * p_reg, uint8_t const * irk_ptr);
+
+/**
+ * @brief Function for getting the pointer to the Identity Resolving Keys
+ * data structure.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Pointer to the IRK data structure.
+ */
+__STATIC_INLINE uint8_t const * nrf_aar_irk_pointer_get(NRF_AAR_Type const * p_reg);
+
+/**
+ * @brief Function for setting the number of keys available in the Identity Resolving Keys
+ * data structure.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param irk_num Number of keys available in the IRK data structure. Maximum is 16.
+ * Must correspond to the size of the provided IRK data structure.
+ *
+ * @sa nrf_aar_irk_pointer_set
+ */
+__STATIC_INLINE void nrf_aar_irk_number_set(NRF_AAR_Type * p_reg, uint8_t irk_num);
+
+/**
+ * @brief Function for getting the number of keys available in the Identity Resolving Keys
+ * data structure.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Number of keys in the IRK data structure.
+ */
+__STATIC_INLINE uint8_t nrf_aar_irk_number_get(NRF_AAR_Type const * p_reg);
+
+/**
+ * @brief Function for setting the pointer to the resolvable address.
+ *
+ * The resolvable address must consist of 6 bytes.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param addr_ptr Pointer to the address to resolve using the available IRK keys.
+ * Must point to the Data RAM region.
+ */
+__STATIC_INLINE void nrf_aar_addr_pointer_set(NRF_AAR_Type * p_reg, uint8_t const * addr_ptr);
+
+/**
+ * @brief Function for getting the pointer to the resolvable address.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Pointer to the address to resolve.
+ */
+__STATIC_INLINE uint8_t const * nrf_aar_addr_pointer_get(NRF_AAR_Type const * p_reg);
+
+/**
+ * @brief Function for setting the pointer to the scratch data area.
+ *
+ * The scratch data area is used for temporary storage during the address resolution procedure.
+ * A space of minimum 3 bytes must be reserved for the scratch data area.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param scratch_ptr Pointer to the scratch data area. Must point to the Data RAM region.
+ */
+__STATIC_INLINE void nrf_aar_scratch_pointer_set(NRF_AAR_Type * p_reg, uint8_t * scratch_ptr);
+
+/**
+ * @brief Function for getting the pointer to the scratch data area.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Pointer to the scratch data area.
+ */
+__STATIC_INLINE uint8_t * nrf_aar_scratch_pointer_get(NRF_AAR_Type const * p_reg);
+
+/**
+ * @brief Function for getting the index of the Identity Resolving Key that was used
+ * the last time an address was resolved.
+ *
+ * This function can be used to get the IRK index that matched the resolvable address,
+ * provided that @ref NRF_AAR_EVENT_RESOLVED occured. Otherwise, it will return
+ * the index of the last IRK stored in the IRK data structure.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return The index of the IRK that was used the last time an address was resolved.
+ */
+__STATIC_INLINE uint8_t nrf_aar_resolution_status_get(NRF_AAR_Type const * p_reg);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE bool nrf_aar_event_check(NRF_AAR_Type const * p_reg,
+ nrf_aar_event_t aar_event)
+{
+ return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)aar_event);
+}
+
+__STATIC_INLINE void nrf_aar_event_clear(NRF_AAR_Type * p_reg,
+ nrf_aar_event_t aar_event)
+{
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)aar_event)) = 0;
+#if __CORTEX_M == 0x04
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)aar_event));
+ (void)dummy;
+#endif
+}
+
+__STATIC_INLINE uint32_t nrf_aar_event_address_get(NRF_AAR_Type const * p_reg,
+ nrf_aar_event_t aar_event)
+{
+ return (uint32_t)((uint8_t *)p_reg + (uint32_t)aar_event);
+}
+
+__STATIC_INLINE void nrf_aar_int_enable(NRF_AAR_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTENSET = mask;
+}
+
+__STATIC_INLINE bool nrf_aar_int_enable_check(NRF_AAR_Type const * p_reg,
+ nrf_aar_int_mask_t mask)
+{
+ return (bool)(p_reg->INTENSET & mask);
+}
+
+__STATIC_INLINE void nrf_aar_int_disable(NRF_AAR_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTENCLR = mask;
+}
+
+__STATIC_INLINE void nrf_aar_task_trigger(NRF_AAR_Type * p_reg, nrf_aar_task_t task)
+{
+ *(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task) = 1;
+}
+
+__STATIC_INLINE uint32_t nrf_aar_task_address_get(NRF_AAR_Type const * p_reg,
+ nrf_aar_task_t task)
+{
+ return (uint32_t)((uint8_t *)p_reg + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_aar_enable(NRF_AAR_Type * p_reg)
+{
+ p_reg->ENABLE = AAR_ENABLE_ENABLE_Enabled << AAR_ENABLE_ENABLE_Pos;
+}
+
+__STATIC_INLINE void nrf_aar_disable(NRF_AAR_Type * p_reg)
+{
+ p_reg->ENABLE = AAR_ENABLE_ENABLE_Disabled << AAR_ENABLE_ENABLE_Pos;
+}
+
+__STATIC_INLINE void nrf_aar_irk_pointer_set(NRF_AAR_Type * p_reg, uint8_t const * irk_ptr)
+{
+ p_reg->IRKPTR = (uint32_t)irk_ptr;
+}
+
+__STATIC_INLINE uint8_t const * nrf_aar_irk_pointer_get(NRF_AAR_Type const * p_reg)
+{
+ return (uint8_t const *)(p_reg->IRKPTR);
+}
+
+__STATIC_INLINE void nrf_aar_irk_number_set(NRF_AAR_Type * p_reg, uint8_t irk_num)
+{
+ p_reg->NIRK = irk_num;
+}
+
+__STATIC_INLINE uint8_t nrf_aar_irk_number_get(NRF_AAR_Type const * p_reg)
+{
+ return (uint8_t)(p_reg->NIRK);
+}
+
+__STATIC_INLINE void nrf_aar_addr_pointer_set(NRF_AAR_Type * p_reg, uint8_t const * addr_ptr)
+{
+ p_reg->ADDRPTR = (uint32_t)addr_ptr;
+}
+
+__STATIC_INLINE uint8_t const * nrf_aar_addr_pointer_get(NRF_AAR_Type const * p_reg)
+{
+ return (uint8_t const *)(p_reg->ADDRPTR);
+}
+
+__STATIC_INLINE void nrf_aar_scratch_pointer_set(NRF_AAR_Type * p_reg, uint8_t * scratch_ptr)
+{
+ p_reg->SCRATCHPTR = (uint32_t)scratch_ptr;
+}
+
+__STATIC_INLINE uint8_t * nrf_aar_scratch_pointer_get(NRF_AAR_Type const * p_reg)
+{
+ return (uint8_t *)(p_reg->SCRATCHPTR);
+}
+
+__STATIC_INLINE uint8_t nrf_aar_resolution_status_get(NRF_AAR_Type const * p_reg)
+{
+ return (uint8_t)(p_reg->STATUS);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_AAR_H__
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_acl.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_acl.h
index 3c2972484..ca15b54db 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_acl.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_acl.h
@@ -38,6 +38,8 @@
extern "C" {
#endif
+#define NRF_ACL_REGION_SIZE_MAX (512 * 1024UL)
+
/**
* @defgroup nrf_acl_hal ACL HAL
* @{
@@ -45,8 +47,6 @@ extern "C" {
* @brief Hardware access layer for managing the Access Control List (ACL) peripheral.
*/
-#define NRF_ACL_REGION_SIZE_MAX (512 * 1024UL)
-
/** @brief ACL permissions. */
typedef enum
{
@@ -56,11 +56,11 @@ typedef enum
} nrf_acl_perm_t;
/**
- * @brief Function for setting region parameters for given ACL region.
+ * @brief Function for setting region parameters for given ACL region.
*
* Address must be word and page aligned. Size must be page aligned.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] region_id ACL region index.
* @param[in] address Start address.
* @param[in] size Size of region to protect in bytes.
@@ -75,7 +75,7 @@ __STATIC_INLINE void nrf_acl_region_set(NRF_ACL_Type * p_reg,
/**
* @brief Function for getting the configured region address of a specific ACL region.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] region_id ACL region index.
*
* @return Configured region address of given ACL region.
@@ -85,7 +85,7 @@ __STATIC_INLINE uint32_t nrf_acl_region_address_get(NRF_ACL_Type * p_reg, uint32
/**
* @brief Function for getting the configured region size of a specific ACL region.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] region_id ACL region index.
*
* @return Configured region size of given ACL region.
@@ -95,7 +95,7 @@ __STATIC_INLINE size_t nrf_acl_region_size_get(NRF_ACL_Type * p_reg, uint32_t re
/**
* @brief Function for getting the configured region permissions of a specific ACL region.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] region_id ACL region index.
*
* @return Configured region permissions of given ACL region.
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_adc.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_adc.h
index eb3e1a868..3e6048349 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_adc.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_adc.h
@@ -72,9 +72,7 @@ typedef enum
} nrf_adc_config_scaling_t;
-/**
- * @brief External reference selection of the analog-to-digital converter.
- */
+/** @brief External reference selection of the analog-to-digital converter. */
typedef enum
{
NRF_ADC_CONFIG_EXTREFSEL_NONE = ADC_CONFIG_EXTREFSEL_None, /**< Analog reference inputs disabled. */
@@ -82,15 +80,13 @@ typedef enum
NRF_ADC_CONFIG_EXTREFSEL_AREF1 = ADC_CONFIG_EXTREFSEL_AnalogReference1 /**< AREF1 as analog reference. */
} nrf_adc_config_extref_t;
-/**
- * @brief Reference selection of the analog-to-digital converter.
- */
+/** @brief Reference selection of the analog-to-digital converter. */
typedef enum
{
NRF_ADC_CONFIG_REF_VBG = ADC_CONFIG_REFSEL_VBG, /**< 1.2 V reference. */
NRF_ADC_CONFIG_REF_SUPPLY_ONE_HALF = ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling, /**< 1/2 of power supply. */
NRF_ADC_CONFIG_REF_SUPPLY_ONE_THIRD = ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling, /**< 1/3 of power supply. */
- NRF_ADC_CONFIG_REF_EXT = ADC_CONFIG_REFSEL_External /**< External reference. See @ref nrf_adc_config_extref_t for further configuration.*/
+ NRF_ADC_CONFIG_REF_EXT = ADC_CONFIG_REFSEL_External /**< External reference. See @ref nrf_adc_config_extref_t for further configuration. */
} nrf_adc_config_reference_t;
/** @brief Input selection of the analog-to-digital converter. */
@@ -110,21 +106,17 @@ typedef enum
/** @brief Analog-to-digital converter tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_ADC_TASK_START = offsetof(NRF_ADC_Type, TASKS_START), /**< ADC start sampling task. */
NRF_ADC_TASK_STOP = offsetof(NRF_ADC_Type, TASKS_STOP) /**< ADC stop sampling task. */
- /*lint -restore*/
} nrf_adc_task_t;
/** @brief Analog-to-digital converter events. */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+typedef enum
{
- /*lint -save -e30*/
NRF_ADC_EVENT_END = offsetof(NRF_ADC_Type, EVENTS_END) /**< End of a conversion event. */
- /*lint -restore*/
} nrf_adc_event_t;
-/**@brief Analog-to-digital converter configuration. */
+/** @brief Analog-to-digital converter configuration. */
typedef struct
{
nrf_adc_config_resolution_t resolution; /**< ADC resolution. */
@@ -134,13 +126,14 @@ typedef struct
nrf_adc_config_extref_t extref; /**< ADC external reference selection. */
} nrf_adc_config_t;
-/**@brief Analog-to-digital value type. */
+/** @brief Analog-to-digital value type. */
typedef uint16_t nrf_adc_value_t;
+
/**
- * @brief Function for activating a specific ADC task.
+ * @brief Function for activating the specified ADC task.
*
- * @param[in] task Task to activate.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task);
@@ -154,12 +147,12 @@ __STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task);
__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t task);
/**
- * @brief Function for checking the state of an ADC event.
+ * @brief Function for retrieving the state of an ADC event.
*
- * @param[in] event Event to check.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event);
@@ -171,7 +164,7 @@ __STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event);
__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event);
/**
- * @brief Function for getting the address of a specific ADC event register.
+ * @brief Function for getting the address of the specified ADC event register.
*
* @param[in] adc_event ADC event.
*
@@ -182,54 +175,48 @@ __STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event);
/**
* @brief Function for enabling the specified interrupts.
*
- * @param[in] int_mask Interrupts to enable.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
-__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask);
+__STATIC_INLINE void nrf_adc_int_enable(uint32_t mask);
/**
* @brief Function for disabling the specified interrupts.
*
- * @param[in] int_mask Interrupts to disable.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
-__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask);
+__STATIC_INLINE void nrf_adc_int_disable(uint32_t mask);
/**
* @brief Function for retrieving the state of the specified ADC interrupts.
*
- * @param[in] int_mask Interrupts to check.
+ * @param[in] mask Mask of interrupts to be checked.
*
- * @retval true If all specified interrupts are enabled.
- * @retval false If at least one of the given interrupts is not enabled.
+ * @retval true All specified interrupts are enabled.
+ * @retval false At least one of the given interrupts is not enabled.
*/
-__STATIC_INLINE bool nrf_adc_int_enable_check(uint32_t int_mask);
+__STATIC_INLINE bool nrf_adc_int_enable_check(uint32_t mask);
/**
* @brief Function for checking whether the ADC is busy.
*
* This function checks whether the ADC converter is busy with a conversion.
*
- * @retval true If the ADC is busy.
- * @retval false If the ADC is not busy.
+ * @retval true The ADC is busy.
+ * @retval false The ADC is not busy.
*/
__STATIC_INLINE bool nrf_adc_busy_check(void);
-/**
- * @brief Function for enabling the ADC.
- *
- */
+/** @brief Function for enabling the ADC. */
__STATIC_INLINE void nrf_adc_enable(void);
-/**
- * @brief Function for disabling the ADC.
- *
- */
+/** @brief Function for disabling the ADC. */
__STATIC_INLINE void nrf_adc_disable(void);
/**
* @brief Function for checking if the ADC is enabled.
*
- * @retval true If the ADC is enabled.
- * @retval false If the ADC is not enabled.
+ * @retval true The ADC is enabled.
+ * @retval false The ADC is not enabled.
*/
__STATIC_INLINE bool nrf_adc_enable_check(void);
@@ -252,6 +239,7 @@ __STATIC_INLINE nrf_adc_value_t nrf_adc_result_get(void);
*/
__STATIC_INLINE void nrf_adc_init(nrf_adc_config_t const * p_config);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task)
@@ -279,19 +267,19 @@ __STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event)
return (uint32_t)((uint8_t *)NRF_ADC + (uint32_t)adc_event);
}
-__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask)
+__STATIC_INLINE void nrf_adc_int_enable(uint32_t mask)
{
- NRF_ADC->INTENSET = int_mask;
+ NRF_ADC->INTENSET = mask;
}
-__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask)
+__STATIC_INLINE void nrf_adc_int_disable(uint32_t mask)
{
- NRF_ADC->INTENCLR = int_mask;
+ NRF_ADC->INTENCLR = mask;
}
-__STATIC_INLINE bool nrf_adc_int_enable_check(uint32_t int_mask)
+__STATIC_INLINE bool nrf_adc_int_enable_check(uint32_t mask)
{
- return (bool)(NRF_ADC->INTENSET & int_mask);
+ return (bool)(NRF_ADC->INTENSET & mask);
}
__STATIC_INLINE bool nrf_adc_busy_check(void)
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_ccm.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_ccm.h
index 0583ac796..560ced235 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_ccm.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_ccm.h
@@ -45,36 +45,26 @@ extern "C" {
* @brief Hardware access layer for managing the AES CCM peripheral.
*/
-/**
- * @brief CCM tasks.
- */
+/** @brief CCM tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_CCM_TASK_KSGEN = offsetof(NRF_CCM_Type, TASKS_KSGEN), ///< Start generation of key-stream.
NRF_CCM_TASK_CRYPT = offsetof(NRF_CCM_Type, TASKS_CRYPT), ///< Start encryption/decryption.
NRF_CCM_TASK_STOP = offsetof(NRF_CCM_Type, TASKS_STOP), ///< Stop encryption/decryption.
#if defined(CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) || defined(__NRFX_DOXYGEN__)
NRF_CCM_TASK_RATEOVERRIDE = offsetof(NRF_CCM_Type, TASKS_RATEOVERRIDE), ///< Override DATARATE setting in MODE register.
#endif
- /*lint -restore*/
} nrf_ccm_task_t;
-/**
- * @brief CCM events.
- */
+/** @brief CCM events. */
typedef enum
{
- /*lint -save -e30*/
NRF_CCM_EVENT_ENDKSGEN = offsetof(NRF_CCM_Type, EVENTS_ENDKSGEN), ///< Keystream generation complete.
NRF_CCM_EVENT_ENDCRYPT = offsetof(NRF_CCM_Type, EVENTS_ENDCRYPT), ///< Encrypt/decrypt complete.
NRF_CCM_EVENT_ERROR = offsetof(NRF_CCM_Type, EVENTS_ERROR), ///< CCM error event.
- /*lint -restore*/
} nrf_ccm_event_t;
-/**
- * @brief CCM interrupts.
- */
+/** @brief CCM interrupts. */
typedef enum
{
NRF_CCM_INT_ENDKSGEN_MASK = CCM_INTENSET_ENDKSGEN_Msk, ///< Interrupt on ENDKSGEN event.
@@ -82,9 +72,7 @@ typedef enum
NRF_CCM_INT_ERROR_MASK = CCM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
} nrf_ccm_int_mask_t;
-/**
- * @brief CCM modes of operation.
- */
+/** @brief CCM modes of operation. */
typedef enum
{
NRF_CCM_MODE_ENCRYPTION = CCM_MODE_MODE_Encryption, ///< Encryption mode.
@@ -92,9 +80,7 @@ typedef enum
} nrf_ccm_mode_t;
#if defined(CCM_MODE_DATARATE_Pos) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief CCM data rates.
- */
+/** @brief CCM data rates. */
typedef enum
{
NRF_CCM_DATARATE_1M = CCM_MODE_DATARATE_1Mbit, ///< 1 Mbps.
@@ -109,9 +95,7 @@ typedef enum
#endif // defined(CCM_MODE_DATARATE_Pos) || defined(__NRFX_DOXYGEN__)
#if defined(CCM_MODE_LENGTH_Pos) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief CCM packet length options.
- */
+/** @brief CCM packet length options. */
typedef enum
{
NRF_CCM_LENGTH_DEFAULT = CCM_MODE_LENGTH_Default, ///< Default length.
@@ -119,24 +103,22 @@ typedef enum
} nrf_ccm_length_t;
#endif // defined(CCM_MODE_LENGTH_Pos) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief CCM configuration.
- */
+/** @brief CCM configuration. */
typedef struct {
- nrf_ccm_mode_t mode;
+ nrf_ccm_mode_t mode; ///< Operation mode.
#if defined(CCM_MODE_DATARATE_Pos) || defined(__NRFX_DOXYGEN__)
- nrf_ccm_datarate_t datarate;
+ nrf_ccm_datarate_t datarate; ///< Data rate.
#endif
#if defined(CCM_MODE_LENGTH_Pos) || defined(__NRFX_DOXYGEN__)
- nrf_ccm_length_t length;
+ nrf_ccm_length_t length; ///< Lenght of the CCM packet.
#endif
} nrf_ccm_config_t;
/**
* @brief Function for activating a specific CCM task.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] task Task to activate.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_ccm_task_trigger(NRF_CCM_Type * p_reg,
nrf_ccm_task_t task);
@@ -144,7 +126,7 @@ __STATIC_INLINE void nrf_ccm_task_trigger(NRF_CCM_Type * p_reg,
/**
* @brief Function for getting the address of a specific CCM task register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Requested task.
*
* @return Address of the specified task register.
@@ -155,20 +137,20 @@ __STATIC_INLINE uint32_t nrf_ccm_task_address_get(NRF_CCM_Type const * p_reg,
/**
* @brief Function for clearing a specific CCM event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_ccm_event_clear(NRF_CCM_Type * p_reg,
nrf_ccm_event_t event);
/**
- * @brief Function for checking the state of a specific CCM event.
+ * @brief Function for retrieving the state of a specific CCM event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_ccm_event_check(NRF_CCM_Type const * p_reg,
nrf_ccm_event_t event);
@@ -176,7 +158,7 @@ __STATIC_INLINE bool nrf_ccm_event_check(NRF_CCM_Type const * p_reg,
/**
* @brief Function for getting the address of a specific CCM event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Requested event.
*
* @return Address of the specified event register.
@@ -187,27 +169,27 @@ __STATIC_INLINE uint32_t nrf_ccm_event_address_get(NRF_CCM_Type const * p_reg,
/**
* @brief Function for enabling specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Interrupts to be enabled.
*/
__STATIC_INLINE void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask);
/**
* @brief Function for disabling specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Interrupts to be disabled.
*/
__STATIC_INLINE void nrf_ccm_int_disable(NRF_CCM_Type * p_reg, uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] ccm_int Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] ccm_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_ccm_int_enable_check(NRF_CCM_Type const * p_reg,
nrf_ccm_int_mask_t ccm_int);
@@ -215,21 +197,21 @@ __STATIC_INLINE bool nrf_ccm_int_enable_check(NRF_CCM_Type const * p_reg,
/**
* @brief Function for enabling the CCM peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_ccm_enable(NRF_CCM_Type * p_reg);
/**
* @brief Function for disabling the CCM peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_ccm_disable(NRF_CCM_Type * p_reg);
/**
* @brief Function for setting the CCM peripheral configuration.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_config Pointer to the structure with configuration to be set.
*/
__STATIC_INLINE void nrf_ccm_configure(NRF_CCM_Type * p_reg,
@@ -240,7 +222,7 @@ __STATIC_INLINE void nrf_ccm_configure(NRF_CCM_Type * p_reg,
* @brief Function for setting the length of key-stream generated
* when the packet length is configured as extended.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] size Maximum length of the key-stream.
*/
__STATIC_INLINE void nrf_ccm_maxpacketsize_set(NRF_CCM_Type * p_reg,
@@ -250,10 +232,10 @@ __STATIC_INLINE void nrf_ccm_maxpacketsize_set(NRF_CCM_Type * p_reg,
/**
* @brief Function for getting the MIC check result.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @retval true If the MIC check passed.
- * @retval false If the MIC check failed.
+ * @retval true The MIC check passed.
+ * @retval false The MIC check failed.
*/
__STATIC_INLINE bool nrf_ccm_micstatus_get(NRF_CCM_Type const * p_reg);
@@ -261,7 +243,7 @@ __STATIC_INLINE bool nrf_ccm_micstatus_get(NRF_CCM_Type const * p_reg);
* @brief Function for setting the pointer to the data structure
* holding the AES key and the CCM NONCE vector.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_data Pointer to the data structure.
*/
__STATIC_INLINE void nrf_ccm_cnfptr_set(NRF_CCM_Type * p_reg,
@@ -271,7 +253,7 @@ __STATIC_INLINE void nrf_ccm_cnfptr_set(NRF_CCM_Type * p_reg,
* @brief Function for getting the pointer to the data structure
* holding the AES key and the CCM NONCE vector.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Pointer to the data structure.
*/
@@ -280,7 +262,7 @@ __STATIC_INLINE uint32_t * nrf_ccm_cnfptr_get(NRF_CCM_Type const * p_reg);
/**
* @brief Function for setting the input data pointer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_data Input data pointer.
*/
__STATIC_INLINE void nrf_ccm_inptr_set(NRF_CCM_Type * p_reg,
@@ -289,7 +271,7 @@ __STATIC_INLINE void nrf_ccm_inptr_set(NRF_CCM_Type * p_reg,
/**
* @brief Function for getting the input data pointer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Input data pointer.
*/
@@ -298,7 +280,7 @@ __STATIC_INLINE uint32_t * nrf_ccm_inptr_get(NRF_CCM_Type const * p_reg);
/**
* @brief Function for setting the output data pointer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_data Output data pointer.
*/
__STATIC_INLINE void nrf_ccm_outptr_set(NRF_CCM_Type * p_reg,
@@ -307,7 +289,7 @@ __STATIC_INLINE void nrf_ccm_outptr_set(NRF_CCM_Type * p_reg,
/**
* @brief Function for getting the output data pointer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Output data pointer.
*/
@@ -317,7 +299,7 @@ __STATIC_INLINE uint32_t * nrf_ccm_outptr_get(NRF_CCM_Type const * p_reg);
* @brief Function for setting the pointer to the scratch area used for
* temporary storage.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_area Pointer to the scratch area.
*/
__STATIC_INLINE void nrf_ccm_scratchptr_set(NRF_CCM_Type * p_reg,
@@ -326,7 +308,7 @@ __STATIC_INLINE void nrf_ccm_scratchptr_set(NRF_CCM_Type * p_reg,
/**
* @brief Function for getting the pointer to the scratch area.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Pointer to the scratch area.
*/
@@ -336,7 +318,7 @@ __STATIC_INLINE uint32_t * nrf_ccm_stratchptr_get(NRF_CCM_Type const * p_reg);
/**
* @brief Function for setting the data rate override value.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] datarate Override value to be applied when the RATEOVERRIDE task
* is triggered.
*/
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_clock.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_clock.h
index a6941561f..1c8eb6f97 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_clock.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_clock.h
@@ -48,12 +48,7 @@ extern "C" {
* (HFCLK) settings.
*/
-#define NRF_CLOCK_TASK_TRIGGER (1UL)
-#define NRF_CLOCK_EVENT_CLEAR (0UL)
-
-#if defined(NRF52810_XXAA) || \
- defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
- defined(NRF52840_XXAA)
+#if defined(CLOCK_LFCLKSRC_BYPASS_Msk) && defined(CLOCK_LFCLKSRC_EXTERNAL_Msk)
// Enable support for external LFCLK sources. Read more in the Product Specification.
#define NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES
#endif
@@ -107,9 +102,7 @@ typedef enum
#endif // defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__)
} nrf_clock_lfclk_t;
-/**
- * @brief High-frequency clock sources.
- */
+/** @brief High-frequency clock sources. */
typedef enum
{
#if defined(CLOCK_HFCLKSTAT_SRC_RC) || defined(__NRFX_DOXYGEN__)
@@ -132,16 +125,18 @@ typedef enum
NRF_CLOCK_START_TASK_TRIGGERED = CLOCK_LFCLKRUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */
} nrf_clock_start_task_status_t;
-/**
- * @brief Interrupts.
- */
+/** @brief Interrupts. */
typedef enum
{
NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */
NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */
#if (NRF_CLOCK_HAS_CALIBRATION) || defined(__NRFX_DOXYGEN__)
NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */
- NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk /**< Interrupt on CTTO event. */
+ NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk, /**< Interrupt on CTTO event. */
+#endif
+#if defined(CLOCK_INTENSET_CTSTARTED_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_CLOCK_INT_CTSTARTED_MASK = CLOCK_INTENSET_CTSTARTED_Msk, /**< Interrupt on CTSTARTED event. */
+ NRF_CLOCK_INT_CTSTOPPED_MASK = CLOCK_INTENSET_CTSTOPPED_Msk /**< Interrupt on CTSTOPPED event. */
#endif
} nrf_clock_int_mask_t;
@@ -151,7 +146,7 @@ typedef enum
* @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running.
* The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running.
*/
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+typedef enum
{
NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source.*/
NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source.*/
@@ -162,86 +157,88 @@ typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer.*/
NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer.*/
#endif
-} nrf_clock_task_t; /*lint -restore */
+} nrf_clock_task_t;
-/**
- * @brief Events.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief Events. */
+typedef enum
{
NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started.*/
NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started.*/
#if (NRF_CLOCK_HAS_CALIBRATION) || defined(__NRFX_DOXYGEN__)
NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed.*/
- NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO) /**< Calibration timer time-out.*/
+ NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO), /**< Calibration timer time-out.*/
#endif
-} nrf_clock_event_t; /*lint -restore */
+#if defined(CLOCK_INTENSET_CTSTARTED_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_CLOCK_EVENT_CTSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_CTSTARTED), /**< Calibration timer started.*/
+ NRF_CLOCK_EVENT_CTSTOPPED = offsetof(NRF_CLOCK_Type, EVENTS_CTSTOPPED) /**< Calibration timer stopped.*/
+#endif
+} nrf_clock_event_t;
/**
- * @brief Function for enabling a specific interrupt.
+ * @brief Function for enabling the specified interrupt.
*
* @param[in] int_mask Interrupt.
*/
__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask);
/**
- * @brief Function for disabling a specific interrupt.
+ * @brief Function for disabling the specified interrupt.
*
* @param[in] int_mask Interrupt.
*/
__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask);
/**
- * @brief Function for retrieving the state of a specific interrupt.
+ * @brief Function for retrieving the state of the specified interrupt.
*
* @param[in] int_mask Interrupt.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask);
/**
- * @brief Function for retrieving the address of a specific task.
+ * @brief Function for retrieving the address of the specified task.
* @details This function can be used by the PPI module.
*
- * @param[in] task Task.
+ * @param[in] task CLOCK Task.
*
* @return Address of the requested task register.
*/
__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task);
/**
- * @brief Function for setting a specific task.
+ * @brief Function for setting the specified task.
*
- * @param[in] task Task.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task);
/**
- * @brief Function for retrieving the address of a specific event.
+ * @brief Function for retrieving the address of the specified event.
* @details This function can be used by the PPI module.
*
- * @param[in] event Event.
+ * @param[in] event CLOCK Event.
*
- * @return Address of the requested event register.
+ * @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event);
/**
- * @brief Function for clearing a specific event.
+ * @brief Function for clearing the specified event.
*
- * @param[in] event Event.
+ * @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event);
/**
- * @brief Function for retrieving the state of a specific event.
+ * @brief Function for retrieving the state of the specified event.
*
- * @param[in] event Event.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event);
@@ -256,11 +253,11 @@ __STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source);
/**
* @brief Function for retrieving the selected source for the low-frequency clock.
*
- * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator
+ * @retval NRF_CLOCK_LFCLK_RC The internal 32 kHz RC oscillator
* is the selected source for the low-frequency clock.
- * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator
+ * @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator
* is the selected source for the low-frequency clock.
- * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from
+ * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesizer from
* the HFCLK is the selected source for the low-frequency clock.
*/
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void);
@@ -268,11 +265,11 @@ __STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void);
/**
* @brief Function for retrieving the active source of the low-frequency clock.
*
- * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator
+ * @retval NRF_CLOCK_LFCLK_RC The internal 32 kHz RC oscillator
* is the active source of the low-frequency clock.
- * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator
+ * @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator
* is the active source of the low-frequency clock.
- * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from
+ * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesizer from
* the HFCLK is the active source of the low-frequency clock.
*/
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void);
@@ -281,11 +278,11 @@ __STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void);
* @brief Function for retrieving the clock source for the LFCLK clock when
* the task LKCLKSTART is triggered.
*
- * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator
+ * @retval NRF_CLOCK_LFCLK_RC The internal 32 kHz RC oscillator
* is running and generating the LFCLK clock.
- * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator
+ * @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator
* is running and generating the LFCLK clock.
- * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from
+ * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesizer from
* the HFCLK is running and generating the LFCLK clock.
*/
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void);
@@ -293,25 +290,25 @@ __STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void);
/**
* @brief Function for retrieving the state of the LFCLK clock.
*
- * @retval false If the LFCLK clock is not running.
- * @retval true If the LFCLK clock is running.
+ * @retval false The LFCLK clock is not running.
+ * @retval true The LFCLK clock is running.
*/
__STATIC_INLINE bool nrf_clock_lf_is_running(void);
/**
* @brief Function for retrieving the trigger status of the task LFCLKSTART.
*
- * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task LFCLKSTART has not been triggered.
- * @retval NRF_CLOCK_START_TASK_TRIGGERED If the task LFCLKSTART has been triggered.
+ * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED The task LFCLKSTART has not been triggered.
+ * @retval NRF_CLOCK_START_TASK_TRIGGERED The task LFCLKSTART has been triggered.
*/
__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void);
/**
* @brief Function for retrieving the active source of the high-frequency clock.
*
- * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY If the internal RC oscillator is the active
+ * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY The internal RC oscillator is the active
* source of the high-frequency clock.
- * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY If an external crystal oscillator is the active
+ * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY An external crystal oscillator is the active
* source of the high-frequency clock.
*/
__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void);
@@ -321,16 +318,16 @@ __STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void);
*
* @param[in] clk_src Clock source to be checked.
*
- * @retval false If the HFCLK clock is not running.
- * @retval true If the HFCLK clock is running.
+ * @retval false The HFCLK clock is not running.
+ * @retval true The HFCLK clock is running.
*/
__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src);
/**
* @brief Function for retrieving the trigger status of the task HFCLKSTART.
*
- * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task HFCLKSTART has not been triggered.
- * @retval NRF_CLOCK_START_TASK_TRIGGERED If the task HFCLKSTART has been triggered.
+ * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED The task HFCLKSTART has not been triggered.
+ * @retval NRF_CLOCK_START_TASK_TRIGGERED The task HFCLKSTART has been triggered.
*/
__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void);
@@ -406,7 +403,7 @@ __STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task)
__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task)
{
- *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + task)) = NRF_CLOCK_TASK_TRIGGER;
+ *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event)
@@ -416,7 +413,7 @@ __STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event)
__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event)
{
- *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)) = NRF_CLOCK_EVENT_CLEAR;
+ *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)) = 0x0UL;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + (uint32_t)event));
(void)dummy;
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_comp.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_comp.h
index f0725cf85..6a7bc9072 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_comp.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_comp.h
@@ -42,221 +42,174 @@ extern "C" {
* @defgroup nrf_comp_hal COMP HAL
* @{
* @ingroup nrf_comp
- * @brief Hardware access layer for managing the Comparator (COMP) peripheral.
+ * @brief Hardware access layer (HAL) for managing the Comparator (COMP) peripheral.
*/
-/**
- * @enum nrf_comp_input_t
- * @brief COMP analog pin selection.
- */
+/** @brief COMP analog pin selection. */
typedef enum
{
- NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0, /*!< AIN0 selected as analog input. */
- NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1, /*!< AIN1 selected as analog input. */
- NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2, /*!< AIN2 selected as analog input. */
- NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3, /*!< AIN3 selected as analog input. */
- NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */
- NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */
- NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */
+ NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0, /*!< AIN0 selected as analog input. */
+ NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1, /*!< AIN1 selected as analog input. */
+ NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2, /*!< AIN2 selected as analog input. */
+ NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3, /*!< AIN3 selected as analog input. */
+ NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */
+ NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */
+ NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */
#if defined (COMP_PSEL_PSEL_AnalogInput7) || defined (__NRFX_DOXYGEN__)
- NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7, /*!< AIN7 selected as analog input. */
+ NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7, /*!< AIN7 selected as analog input. */
#endif
#if defined (COMP_PSEL_PSEL_VddDiv2) || defined (__NRFX_DOXYGEN__)
- NRF_COMP_VDD_DIV2 = COMP_PSEL_PSEL_VddDiv2, /*!< VDD/2 selected as analog input. */
+ NRF_COMP_VDD_DIV2 = COMP_PSEL_PSEL_VddDiv2, /*!< VDD/2 selected as analog input. */
#endif
-}nrf_comp_input_t;
+} nrf_comp_input_t;
-/**
- * @enum nrf_comp_ref_t
- * @brief COMP reference selection.
- */
+/** @brief COMP reference selection. */
typedef enum
{
- NRF_COMP_REF_Int1V2 = COMP_REFSEL_REFSEL_Int1V2, /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V). */
- NRF_COMP_REF_Int1V8 = COMP_REFSEL_REFSEL_Int1V8, /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V). */
- NRF_COMP_REF_Int2V4 = COMP_REFSEL_REFSEL_Int2V4, /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V). */
- NRF_COMP_REF_VDD = COMP_REFSEL_REFSEL_VDD, /*!< VREF = VDD. */
- NRF_COMP_REF_ARef = COMP_REFSEL_REFSEL_ARef /*!< VREF = AREF (VDD >= VREF >= AREFMIN). */
-}nrf_comp_ref_t;
+ NRF_COMP_REF_Int1V2 = COMP_REFSEL_REFSEL_Int1V2, /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V). */
+ NRF_COMP_REF_Int1V8 = COMP_REFSEL_REFSEL_Int1V8, /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V). */
+ NRF_COMP_REF_Int2V4 = COMP_REFSEL_REFSEL_Int2V4, /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V). */
+ NRF_COMP_REF_VDD = COMP_REFSEL_REFSEL_VDD, /*!< VREF = VDD. */
+ NRF_COMP_REF_ARef = COMP_REFSEL_REFSEL_ARef /*!< VREF = AREF (VDD >= VREF >= AREFMIN). */
+} nrf_comp_ref_t;
-/**
- * @enum nrf_comp_ext_ref_t
- * @brief COMP external analog reference selection.
- */
+/** @brief COMP external analog reference selection. */
typedef enum
{
- NRF_COMP_EXT_REF_0 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference0, /*!< Use AIN0 as external analog reference. */
- NRF_COMP_EXT_REF_1 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 /*!< Use AIN1 as external analog reference. */
-}nrf_comp_ext_ref_t;
+ NRF_COMP_EXT_REF_0 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference0, /*!< Use AIN0 as external analog reference. */
+ NRF_COMP_EXT_REF_1 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 /*!< Use AIN1 as external analog reference. */
+} nrf_comp_ext_ref_t;
-/**
- * @brief COMP THDOWN and THUP values that are used to calculate the threshold voltages VDOWN and VUP.
- */
+/** @brief COMP THDOWN and THUP values that are used to calculate the threshold voltages VDOWN and VUP. */
typedef struct
{
uint8_t th_down; /*!< THDOWN value. */
uint8_t th_up; /*!< THUP value. */
-}nrf_comp_th_t;
+} nrf_comp_th_t;
-/**
- * @enum nrf_comp_main_mode_t
- * @brief COMP main operation mode.
- */
+/** @brief COMP main operation mode. */
typedef enum
{
- NRF_COMP_MAIN_MODE_SE = COMP_MODE_MAIN_SE, /*!< Single ended mode. */
- NRF_COMP_MAIN_MODE_Diff = COMP_MODE_MAIN_Diff /*!< Differential mode. */
-}nrf_comp_main_mode_t;
+ NRF_COMP_MAIN_MODE_SE = COMP_MODE_MAIN_SE, /*!< Single-ended mode. */
+ NRF_COMP_MAIN_MODE_Diff = COMP_MODE_MAIN_Diff /*!< Differential mode. */
+} nrf_comp_main_mode_t;
-/**
- * @enum nrf_comp_sp_mode_t
- * @brief COMP speed and power mode.
- */
+/** @brief COMP speed and power mode. */
typedef enum
{
- NRF_COMP_SP_MODE_Low = COMP_MODE_SP_Low, /*!< Low power mode. */
- NRF_COMP_SP_MODE_Normal = COMP_MODE_SP_Normal, /*!< Normal mode. */
- NRF_COMP_SP_MODE_High = COMP_MODE_SP_High /*!< High speed mode. */
-}nrf_comp_sp_mode_t;
+ NRF_COMP_SP_MODE_Low = COMP_MODE_SP_Low, /*!< Low power mode. */
+ NRF_COMP_SP_MODE_Normal = COMP_MODE_SP_Normal, /*!< Normal mode. */
+ NRF_COMP_SP_MODE_High = COMP_MODE_SP_High /*!< High-speed mode. */
+} nrf_comp_sp_mode_t;
-/**
- * @enum nrf_comp_hyst_t
- * @brief COMP comparator hysteresis.
- */
+/** @brief COMP comparator hysteresis. */
typedef enum
{
- NRF_COMP_HYST_NoHyst = COMP_HYST_HYST_NoHyst, /*!< Comparator hysteresis disabled. */
- NRF_COMP_HYST_50mV = COMP_HYST_HYST_Hyst50mV /*!< Comparator hysteresis enabled. */
-}nrf_comp_hyst_t;
+ NRF_COMP_HYST_NoHyst = COMP_HYST_HYST_NoHyst, /*!< Comparator hysteresis disabled. */
+ NRF_COMP_HYST_50mV = COMP_HYST_HYST_Hyst50mV /*!< Comparator hysteresis enabled. */
+} nrf_comp_hyst_t;
#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__)
-/**
- * @brief COMP current source selection on analog input.
- */
+/** @brief COMP current source selection on analog input. */
typedef enum
{
- NRF_COMP_ISOURCE_Off = COMP_ISOURCE_ISOURCE_Off, /*!< Current source disabled. */
- NRF_COMP_ISOURCE_Ien2uA5 = COMP_ISOURCE_ISOURCE_Ien2mA5, /*!< Current source enabled (+/- 2.5 uA). */
- NRF_COMP_ISOURCE_Ien5uA = COMP_ISOURCE_ISOURCE_Ien5mA, /*!< Current source enabled (+/- 5 uA). */
- NRF_COMP_ISOURCE_Ien10uA = COMP_ISOURCE_ISOURCE_Ien10mA /*!< Current source enabled (+/- 10 uA). */
-}nrf_isource_t;
+ NRF_COMP_ISOURCE_Off = COMP_ISOURCE_ISOURCE_Off, /*!< Current source disabled. */
+ NRF_COMP_ISOURCE_Ien2uA5 = COMP_ISOURCE_ISOURCE_Ien2mA5, /*!< Current source enabled (+/- 2.5 uA). */
+ NRF_COMP_ISOURCE_Ien5uA = COMP_ISOURCE_ISOURCE_Ien5mA, /*!< Current source enabled (+/- 5 uA). */
+ NRF_COMP_ISOURCE_Ien10uA = COMP_ISOURCE_ISOURCE_Ien10mA /*!< Current source enabled (+/- 10 uA). */
+} nrf_isource_t;
#endif
-/**
- * @enum nrf_comp_task_t
- * @brief COMP tasks.
- */
+/** @brief COMP tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_COMP_TASK_START = offsetof(NRF_COMP_Type, TASKS_START), /*!< COMP start sampling task. */
NRF_COMP_TASK_STOP = offsetof(NRF_COMP_Type, TASKS_STOP), /*!< COMP stop sampling task. */
NRF_COMP_TASK_SAMPLE = offsetof(NRF_COMP_Type, TASKS_SAMPLE) /*!< Sample comparator value. */
- /*lint -restore*/
-}nrf_comp_task_t;
+} nrf_comp_task_t;
-/**
- * @enum nrf_comp_event_t
- * @brief COMP events.
- */
+/** @brief COMP events. */
typedef enum
{
- /*lint -save -e30*/
NRF_COMP_EVENT_READY = offsetof(NRF_COMP_Type, EVENTS_READY), /*!< COMP is ready and output is valid. */
NRF_COMP_EVENT_DOWN = offsetof(NRF_COMP_Type, EVENTS_DOWN), /*!< Input voltage crossed the threshold going down. */
NRF_COMP_EVENT_UP = offsetof(NRF_COMP_Type, EVENTS_UP), /*!< Input voltage crossed the threshold going up. */
NRF_COMP_EVENT_CROSS = offsetof(NRF_COMP_Type, EVENTS_CROSS) /*!< Input voltage crossed the threshold in any direction. */
- /*lint -restore*/
-}nrf_comp_event_t;
+} nrf_comp_event_t;
-/**
- * @brief COMP reference configuration.
- */
+/** @brief COMP reference configuration. */
typedef struct
{
- nrf_comp_ref_t reference; /*!< COMP reference selection. */
- nrf_comp_ext_ref_t external; /*!< COMP external analog reference selection. */
-}nrf_comp_ref_conf_t;
+ nrf_comp_ref_t reference; /*!< COMP reference selection. */
+ nrf_comp_ext_ref_t external; /*!< COMP external analog reference selection. */
+} nrf_comp_ref_conf_t;
-/**
- * @brief Function for enabling the COMP peripheral.
- */
+/** @brief Function for enabling the COMP peripheral. */
__STATIC_INLINE void nrf_comp_enable(void);
-
-/**
- * @brief Function for disabling the COMP peripheral.
- */
-
+/** @brief Function for disabling the COMP peripheral. */
__STATIC_INLINE void nrf_comp_disable(void);
/**
* @brief Function for checking if the COMP peripheral is enabled.
*
- * @retval true If the COMP peripheral is enabled.
- * @retval false If the COMP peripheral is not enabled.
+ * @retval true The COMP peripheral is enabled.
+ * @retval false The COMP peripheral is not enabled.
*/
__STATIC_INLINE bool nrf_comp_enable_check(void);
/**
* @brief Function for setting the reference source.
*
- * @param[in] reference COMP reference selection.
+ * @param[in] reference COMP reference selection.
*/
__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference);
-
/**
* @brief Function for setting the external analog reference source.
*
- * @param[in] ext_ref COMP external analog reference selection.
+ * @param[in] ext_ref COMP external analog reference selection.
*/
__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref);
-
/**
* @brief Function for setting threshold voltages.
*
- * @param[in] threshold COMP VDOWN and VUP thresholds.
+ * @param[in] threshold COMP VDOWN and VUP thresholds.
*/
__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold);
-
/**
* @brief Function for setting the main mode.
*
- * @param[in] main_mode COMP main operation mode.
+ * @param[in] main_mode COMP main operation mode.
*/
__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode);
-
/**
* @brief Function for setting the speed mode.
*
- * @param[in] speed_mode COMP speed and power mode.
+ * @param[in] speed_mode COMP speed and power mode.
*/
__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode);
-
/**
* @brief Function for setting the hysteresis.
*
- * @param[in] hyst COMP comparator hysteresis.
+ * @param[in] hyst COMP comparator hysteresis.
*/
__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst);
-
#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__)
/**
* @brief Function for setting the current source on the analog input.
*
- * @param[in] isource COMP current source selection on analog input.
+ * @param[in] isource COMP current source selection on analog input.
*/
__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource);
#endif
-
/**
* @brief Function for selecting the active input of the COMP.
*
@@ -264,110 +217,99 @@ __STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource);
*/
__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input);
-
/**
* @brief Function for getting the last COMP compare result.
*
- * @return The last compare result. If 0, then VIN+ < VIN-. If 1, then VIN+ > VIN-.
- *
* @note If VIN+ == VIN-, the return value depends on the previous result.
+ *
+ * @return The last compare result. If 0, then VIN+ < VIN-. If 1, then VIN+ > VIN-.
*/
__STATIC_INLINE uint32_t nrf_comp_result_get(void);
-
/**
* @brief Function for enabling interrupts from COMP.
*
- * @param[in] comp_int_mask Mask of interrupts to be enabled.
+ * @param[in] mask Mask of interrupts to be enabled.
*
- * @sa nrf_comp_int_enable_check()
+ * @sa nrf_comp_int_enable_check
*/
-__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask);
+__STATIC_INLINE void nrf_comp_int_enable(uint32_t mask);
/**
* @brief Function for disabling interrupts from COMP.
*
- * @param[in] comp_int_mask Mask of interrupts to be disabled.
+ * @param[in] mask Mask of interrupts to be disabled.
*
- * @sa nrf_comp_int_enable_check()
+ * @sa nrf_comp_int_enable_check
*/
-__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask);
-
+__STATIC_INLINE void nrf_comp_int_disable(uint32_t mask);
/**
* @brief Function for getting the enabled interrupts of COMP.
*
- * @param[in] comp_int_mask Mask of interrupts to be checked.
+ * @param[in] mask Mask of interrupts to be checked.
*
- * @retval true If any interrupts of the specified mask are enabled.
+ * @retval true At least one interrupt from the specified mask is enabled.
+ * @retval false No interrupt provided by the specified mask are enabled.
*/
-__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask);
-
-
+__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t mask);
/**
- * @brief Function for getting the address of a specific COMP task register.
+ * @brief Function for getting the address of the specified COMP task register.
*
- * @param[in] comp_task COMP task.
+ * @param[in] task COMP task.
*
* @return Address of the specified COMP task.
*/
-__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task);
-
+__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t task);
/**
- * @brief Function for getting the address of a specific COMP event register.
+ * @brief Function for getting the address of the specified COMP event register.
*
- * @param[in] comp_event COMP event.
+ * @param[in] event COMP event.
*
* @return Address of the specified COMP event.
*/
-__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event);
-
+__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t event);
/**
- * @brief Function for setting COMP shorts.
- *
- * @param[in] comp_short_mask COMP shorts by mask.
+ * @brief Function for setting COMP shortcuts.
*
+ * @param[in] mask Mask of shortcuts.
*/
-__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask);
-
+__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t mask);
/**
- * @brief Function for clearing COMP shorts by mask.
- *
- * @param[in] comp_short_mask COMP shorts to be cleared.
+ * @brief Function for clearing COMP shortcuts by mask.
*
+ * @param[in] mask Mask of shortcuts.
*/
-__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask);
-
+__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t mask);
/**
- * @brief Function for setting a specific COMP task.
- *
- * @param[in] comp_task COMP task to be set.
+ * @brief Function for setting the specified COMP task.
*
+ * @param[in] task Task to be activated.
*/
-__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task);
-
+__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t task);
/**
- * @brief Function for clearing a specific COMP event.
- *
- * @param[in] comp_event COMP event to be cleared.
+ * @brief Function for clearing the specified COMP event.
*
+ * @param[in] event COMP event to be cleared.
*/
-__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event);
-
+__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t event);
/**
- * @brief Function for getting the state of a specific COMP event.
+ * @brief Function for retrieving the state of the UARTE event.
*
- * @retval true If the specified COMP event is active.
+ * @param[in] event Event to be checked.
*
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event);
+__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t event);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
@@ -399,8 +341,8 @@ __STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref)
__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold)
{
NRF_COMP->TH =
- ((threshold.th_down << COMP_TH_THDOWN_Pos) & COMP_TH_THDOWN_Msk) |
- ((threshold.th_up << COMP_TH_THUP_Pos) & COMP_TH_THUP_Msk);
+ (((uint32_t)threshold.th_down << COMP_TH_THDOWN_Pos) & COMP_TH_THDOWN_Msk) |
+ (((uint32_t)threshold.th_up << COMP_TH_THUP_Pos) & COMP_TH_THUP_Msk);
}
__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode)
@@ -435,58 +377,58 @@ __STATIC_INLINE uint32_t nrf_comp_result_get(void)
return (uint32_t)NRF_COMP->RESULT;
}
-__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask)
+__STATIC_INLINE void nrf_comp_int_enable(uint32_t mask)
{
- NRF_COMP->INTENSET = comp_int_mask;
+ NRF_COMP->INTENSET = mask;
}
-__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask)
+__STATIC_INLINE void nrf_comp_int_disable(uint32_t mask)
{
- NRF_COMP->INTENCLR = comp_int_mask;
+ NRF_COMP->INTENCLR = mask;
}
-__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask)
+__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t mask)
{
- return (NRF_COMP->INTENSET & comp_int_mask); // when read this register will return the value of INTEN.
+ return (NRF_COMP->INTENSET & mask); // When read, this register returns the value of INTEN.
}
-__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task)
+__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t task)
{
- return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_task);
+ return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)task);
}
-__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event)
+__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t event)
{
- return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event);
+ return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)event);
}
-__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask)
+__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t mask)
{
- NRF_COMP->SHORTS |= comp_short_mask;
+ NRF_COMP->SHORTS |= mask;
}
-__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask)
+__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t mask)
{
- NRF_COMP->SHORTS &= ~comp_short_mask;
+ NRF_COMP->SHORTS &= ~mask;
}
-__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task)
+__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t task)
{
- *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_task) ) = 1;
+ *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)task) ) = 1;
}
-__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event)
+__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t event)
{
- *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)comp_event) ) = 0;
+ *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)event) ) = 0;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)event));
(void)dummy;
#endif
}
-__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event)
+__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t event)
{
- return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_event));
+ return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)event));
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_dppi.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_dppi.h
index b1ee7da7e..bae9f22fd 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_dppi.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_dppi.h
@@ -78,18 +78,29 @@ typedef enum
* @brief Function for activating a DPPI task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] dppi_task Task to activate.
+ * @param[in] dppi_task Task to be activated.
*/
__STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task);
+/**
+ * @brief Function for getting the address of the specified DPPI task register.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
+ nrf_dppi_task_t task);
+
/**
* @brief Function for checking the state of a specific DPPI channel.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] channel Channel to check.
+ * @param[in] channel Channel to be checked.
*
- * @retval true If the channel is enabled.
- * @retval false If the channel is not enabled.
+ * @retval true The channel is enabled.
+ * @retval false The channel is not enabled.
*/
__STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel);
@@ -200,6 +211,24 @@ __STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,
__STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
nrf_dppi_channel_group_t group);
+/**
+ * @brief Function for getting the ENABLE task associated with the specified channel group.
+ *
+ * @param[in] index Channel group index.
+ *
+ * @return Requested ENABLE task.
+ */
+__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index);
+
+/**
+ * @brief Function for getting the DISABLE task associated with the specified channel group.
+ *
+ * @param[in] index Channel group index.
+ *
+ * @return Requested DISABLE task.
+ */
+__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
@@ -208,6 +237,12 @@ __STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) dppi_task)) = 1;
}
+__STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
+ nrf_dppi_task_t task)
+{
+ return (uint32_t) ((uint8_t *) p_reg + (uint32_t ) task);
+}
+
__STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel)
{
return ((p_reg->CHEN & (DPPIC_CHEN_CH0_Enabled << (DPPIC_CHEN_CH0_Pos + channel))) != 0);
@@ -274,6 +309,18 @@ __STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
p_reg->TASKS_CHG[(uint32_t) group].DIS = 1;
}
+__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index)
+{
+ NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_DPPIC->TASKS_CHG));
+ return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].EN);
+}
+
+__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index)
+{
+ NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_DPPIC->TASKS_CHG));
+ return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].DIS);
+}
+
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.c b/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.c
index 1a196057e..76fbf1eb8 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.c
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.c
@@ -29,8 +29,6 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-//lint -e438
-
#include
#include "nrf_ecb.h"
#include
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.h
index 40064a99d..d22624515 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_ecb.h
@@ -42,7 +42,7 @@ extern "C" {
* @defgroup nrf_ecb_drv AES ECB encryption driver
* @{
* @ingroup nrf_ecb
- * @brief Driver for the AES Electronic Code Book (ECB) peripheral.
+ * @brief Driver for the Advanced Encryption Standard (AES) Electronic Code Book (ECB) peripheral.
*
* To encrypt data, the peripheral must first be powered on
* using @ref nrf_ecb_init. Next, the key must be set using @ref nrf_ecb_set_key.
@@ -52,8 +52,9 @@ extern "C" {
* @brief Function for initializing and powering on the ECB peripheral.
*
* This function allocates memory for the ECBDATAPTR.
- * @retval true If initialization was successful.
- * @retval false If powering on failed.
+ *
+ * @retval true The initialization was successful.
+ * @retval false The power-on failed.
*/
bool nrf_ecb_init(void);
@@ -66,8 +67,8 @@ bool nrf_ecb_init(void);
* @param dst Result of encryption, 16 bytes will be written.
* @param src Source with 16-byte data to be encrypted.
*
- * @retval true If the encryption operation completed.
- * @retval false If the encryption operation did not complete.
+ * @retval true The encryption operation completed.
+ * @retval false The encryption operation did not complete.
*/
bool nrf_ecb_crypt(uint8_t * dst, const uint8_t * src);
@@ -84,34 +85,24 @@ void nrf_ecb_set_key(const uint8_t * key);
* @defgroup nrf_ecb_hal AES ECB encryption HAL
* @{
* @ingroup nrf_ecb
- * @brief Hardware access layer for managing the AES Electronic Codebook (ECB) peripheral.
+ * @brief Hardware access layer (HAL) for managing the Advanced Encryption Standard (AES) Electronic Codebook (ECB) peripheral.
*/
-/**
- * @brief ECB tasks.
- */
+/** @brief ECB tasks. */
typedef enum
{
- /*lint -save -e30 -esym(628,__INTADDR__)*/
- NRF_ECB_TASK_STARTECB = offsetof(NRF_ECB_Type, TASKS_STARTECB), /**< Task for starting ECB block encryption. */
- NRF_ECB_TASK_STOPECB = offsetof(NRF_ECB_Type, TASKS_STOPECB), /**< Task for stopping ECB block encryption. */
- /*lint -restore*/
+ NRF_ECB_TASK_STARTECB = offsetof(NRF_ECB_Type, TASKS_STARTECB), /**< Task for starting the ECB block encryption. */
+ NRF_ECB_TASK_STOPECB = offsetof(NRF_ECB_Type, TASKS_STOPECB), /**< Task for stopping the ECB block encryption. */
} nrf_ecb_task_t;
-/**
- * @brief ECB events.
- */
+/** @brief ECB events. */
typedef enum
{
- /*lint -save -e30*/
NRF_ECB_EVENT_ENDECB = offsetof(NRF_ECB_Type, EVENTS_ENDECB), /**< ECB block encrypt complete. */
NRF_ECB_EVENT_ERRORECB = offsetof(NRF_ECB_Type, EVENTS_ERRORECB), /**< ECB block encrypt aborted because of a STOPECB task or due to an error. */
- /*lint -restore*/
} nrf_ecb_event_t;
-/**
- * @brief ECB interrupts.
- */
+/** @brief ECB interrupts. */
typedef enum
{
NRF_ECB_INT_ENDECB_MASK = ECB_INTENSET_ENDECB_Msk, ///< Interrupt on ENDECB event.
@@ -120,15 +111,15 @@ typedef enum
/**
- * @brief Function for activating a specific ECB task.
+ * @brief Function for activating the specified ECB task.
*
* @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] task Task to activate.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_ecb_task_trigger(NRF_ECB_Type * p_reg, nrf_ecb_task_t task);
/**
- * @brief Function for getting the address of a specific ECB task register.
+ * @brief Function for getting the address of the specified ECB task register.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] task Requested task.
@@ -139,7 +130,7 @@ __STATIC_INLINE uint32_t nrf_ecb_task_address_get(NRF_ECB_Type const * p_reg,
nrf_ecb_task_t task);
/**
- * @brief Function for clearing a specific ECB event.
+ * @brief Function for clearing the specified ECB event.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] event Event to clear.
@@ -147,18 +138,18 @@ __STATIC_INLINE uint32_t nrf_ecb_task_address_get(NRF_ECB_Type const * p_reg,
__STATIC_INLINE void nrf_ecb_event_clear(NRF_ECB_Type * p_reg, nrf_ecb_event_t event);
/**
- * @brief Function for checking the state of a specific ECB event.
+ * @brief Function for retrieving the state of the ECB event.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_ecb_event_check(NRF_ECB_Type const * p_reg, nrf_ecb_event_t event);
/**
- * @brief Function for getting the address of a specific ECB event register.
+ * @brief Function for getting the address of the specified ECB event register.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] event Requested event.
@@ -169,18 +160,18 @@ __STATIC_INLINE uint32_t nrf_ecb_event_address_get(NRF_ECB_Type const * p_reg,
nrf_ecb_event_t event);
/**
- * @brief Function for enabling specified interrupts.
+ * @brief Function for enabling the specified interrupts.
*
* @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] mask Interrupts to enable.
+ * @param[in] mask Interrupts to be enabled.
*/
__STATIC_INLINE void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask);
/**
- * @brief Function for disabling specified interrupts.
+ * @brief Function for disabling the specified interrupts.
*
* @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] mask Interrupts to disable.
+ * @param[in] mask Interrupts to be disabled.
*/
__STATIC_INLINE void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask);
@@ -188,10 +179,10 @@ __STATIC_INLINE void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask);
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] ecb_int Interrupt to check.
+ * @param[in] ecb_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_ecb_int_enable_check(NRF_ECB_Type const * p_reg,
nrf_ecb_int_mask_t ecb_int);
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_egu.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_egu.h
index 5fb9ce677..74744e928 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_egu.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_egu.h
@@ -45,13 +45,9 @@ extern "C" {
* @brief Hardware access layer for managing the Event Generator Unit (EGU) peripheral.
*/
-/**
- * @enum nrf_egu_task_t
- * @brief EGU tasks.
- */
+/** @brief EGU tasks. */
typedef enum
{
- /*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_EGU_TASK_TRIGGER0 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[0]), /**< Trigger 0 for triggering the corresponding TRIGGERED[0] event. */
NRF_EGU_TASK_TRIGGER1 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[1]), /**< Trigger 1 for triggering the corresponding TRIGGERED[1] event. */
NRF_EGU_TASK_TRIGGER2 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[2]), /**< Trigger 2 for triggering the corresponding TRIGGERED[2] event. */
@@ -68,16 +64,11 @@ typedef enum
NRF_EGU_TASK_TRIGGER13 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[13]), /**< Trigger 13 for triggering the corresponding TRIGGERED[13] event. */
NRF_EGU_TASK_TRIGGER14 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[14]), /**< Trigger 14 for triggering the corresponding TRIGGERED[14] event. */
NRF_EGU_TASK_TRIGGER15 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[15]) /**< Trigger 15 for triggering the corresponding TRIGGERED[15] event. */
- /*lint -restore*/
} nrf_egu_task_t;
-/**
- * @enum nrf_egu_event_t
- * @brief EGU events.
- */
+/** @brief EGU events. */
typedef enum
{
- /*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_EGU_EVENT_TRIGGERED0 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[0]), /**< Event number 0 generated by triggering the corresponding TRIGGER[0] task. */
NRF_EGU_EVENT_TRIGGERED1 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[1]), /**< Event number 1 generated by triggering the corresponding TRIGGER[1] task. */
NRF_EGU_EVENT_TRIGGERED2 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[2]), /**< Event number 2 generated by triggering the corresponding TRIGGER[2] task. */
@@ -94,13 +85,9 @@ typedef enum
NRF_EGU_EVENT_TRIGGERED13 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[13]), /**< Event number 13 generated by triggering the corresponding TRIGGER[13] task. */
NRF_EGU_EVENT_TRIGGERED14 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[14]), /**< Event number 14 generated by triggering the corresponding TRIGGER[14] task. */
NRF_EGU_EVENT_TRIGGERED15 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[15]) /**< Event number 15 generated by triggering the corresponding TRIGGER[15] task. */
- /*lint -restore*/
} nrf_egu_event_t;
-/**
- * @enum nrf_egu_int_mask_t
- * @brief EGU interrupts.
- */
+/** @brief EGU interrupts. */
typedef enum
{
NRF_EGU_INT_TRIGGERED0 = EGU_INTENSET_TRIGGERED0_Msk, /**< Interrupt on EVENTS_TRIGGERED[0] event. */
@@ -122,16 +109,18 @@ typedef enum
NRF_EGU_INT_ALL = 0xFFFFuL
} nrf_egu_int_mask_t;
-/**@brief Function for getting max channel number of given EGU.
+
+/**
+ * @brief Function for getting the maximum channel number of the given EGU.
*
* @param NRF_EGUx EGU instance.
*
- * @returns number of available channels.
+ * @return Number of available channels.
*/
__STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx);
/**
- * @brief Function for triggering a specific EGU task.
+ * @brief Function for triggering the specified EGU task.
*
* @param NRF_EGUx EGU instance.
* @param egu_task EGU task.
@@ -139,110 +128,125 @@ __STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx);
__STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task);
/**
- * @brief Function for returning the address of a specific EGU task register.
+ * @brief Function for returning the address of the specified EGU task register.
*
* @param NRF_EGUx EGU instance.
* @param egu_task EGU task.
+ *
+ * @return Address of the specified EGU task register.
*/
__STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx,
nrf_egu_task_t egu_task);
/**
- * @brief Function for returning the address of a specific EGU TRIGGER task register.
+ * @brief Function for returning the address of the specified EGU TRIGGER task register.
*
* @param NRF_EGUx EGU instance.
* @param channel Channel number.
+ *
+ * @return Address of the specified EGU TRIGGER task register.
*/
__STATIC_INLINE uint32_t * nrf_egu_task_trigger_address_get(NRF_EGU_Type * NRF_EGUx,
- uint8_t channel);
+ uint8_t channel);
/**
- * @brief Function for returning the specific EGU TRIGGER task.
+ * @brief Function for returning the specified EGU TRIGGER task.
*
* @param NRF_EGUx EGU instance.
* @param channel Channel number.
+ *
+ * @return The specified EGU TRIGGER task.
*/
__STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel);
/**
- * @brief Function for returning the state of a specific EGU event.
+ * @brief Function for retrieving the state of the UARTE event.
*
* @param NRF_EGUx EGU instance.
- * @param egu_event EGU event to check.
+ * @param egu_event EGU event to be checked.
+ *
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx,
+__STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx,
nrf_egu_event_t egu_event);
/**
- * @brief Function for clearing a specific EGU event.
+ * @brief Function for clearing the specified EGU event.
*
* @param NRF_EGUx EGU instance.
* @param egu_event EGU event to clear.
*/
-__STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx,
+__STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx,
nrf_egu_event_t egu_event);
/**
- * @brief Function for returning the address of a specific EGU event register.
+ * @brief Function for returning the address of the specified EGU event register.
*
* @param NRF_EGUx EGU instance.
* @param egu_event EGU event.
+ *
+ * @return Address of the specified EGU event register.
*/
-__STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx,
+__STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx,
nrf_egu_event_t egu_event);
/**
- * @brief Function for returning the address of a specific EGU TRIGGERED event register.
+ * @brief Function for returning address of the specified EGU TRIGGERED event register.
*
* @param NRF_EGUx EGU instance.
* @param channel Channel number.
+ *
+ * @return Address of the specified EGU TRIGGERED event register.
*/
__STATIC_INLINE uint32_t * nrf_egu_event_triggered_address_get(NRF_EGU_Type * NRF_EGUx,
- uint8_t channel);
+ uint8_t channel);
/**
- * @brief Function for returning the specific EGU TRIGGERED event.
+ * @brief Function for returning the specified EGU TRIGGERED event.
*
* @param NRF_EGUx EGU instance.
* @param channel Channel number.
+ *
+ * @return The specified EGU TRIGGERED event.
*/
__STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_EGUx,
- uint8_t channel);
+ uint8_t channel);
/**
- * @brief Function for enabling one or more specific EGU interrupts.
- *
- * @param NRF_EGUx EGU instance.
- * @param egu_int_mask Interrupts to enable.
- */
-__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask);
-
-/**
- * @brief Function for retrieving the state of one or more EGU interrupts.
+ * @brief Function for enabling one or more of the EGU interrupts.
*
* @param NRF_EGUx EGU instance.
- * @param egu_int_mask Interrupts to check.
- *
- * @retval true If all of the specified interrupts are enabled.
- * @retval false If at least one of the specified interrupts is disabled.
+ * @param mask Mask of interrupts to be enabled.
*/
-__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask);
+__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t mask);
/**
- * @brief Function for disabling one or more specific EGU interrupts.
- *
- * @param NRF_EGUx EGU instance.
- * @param egu_int_mask Interrupts to disable.
- */
-__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask);
-
-/**
- * @brief Function for retrieving one or more specific EGU interrupts.
+ * @brief Function for retrieving the state of one or more of the EGU interrupts.
*
* @param NRF_EGUx EGU instance.
- * @param channel Channel number.
+ * @param mask Mask of interrupts to be checked.
*
- * @returns EGU interrupt mask.
+ * @retval true All of the specified interrupts are enabled.
+ * @retval false At least one of the specified interrupts is disabled.
+ */
+__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t mask);
+
+/**
+ * @brief Function for disabling one or more of the EGU interrupts.
+ *
+ * @param NRF_EGUx EGU instance.
+ * @param mask Mask of interrupts to be disabled.
+ */
+__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t mask);
+
+/**
+ * @brief Function for retrieving one or more of the EGU interrupts.
+ *
+ * @param NRF_EGUx EGU instance.
+ * @param channel Channel number.
+ *
+ * @return EGU interrupt mask.
*/
__STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel);
@@ -388,22 +392,22 @@ __STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_E
return (nrf_egu_event_t)((uint32_t) NRF_EGU_EVENT_TRIGGERED0 + (channel * sizeof(uint32_t)));
}
-__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
+__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t mask)
{
NRFX_ASSERT(NRF_EGUx);
- NRF_EGUx->INTENSET = egu_int_mask;
+ NRF_EGUx->INTENSET = mask;
}
-__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
+__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t mask)
{
NRFX_ASSERT(NRF_EGUx);
- return (bool)(NRF_EGUx->INTENSET & egu_int_mask);
+ return (bool)(NRF_EGUx->INTENSET & mask);
}
-__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
+__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t mask)
{
NRFX_ASSERT(NRF_EGUx);
- NRF_EGUx->INTENCLR = egu_int_mask;
+ NRF_EGUx->INTENCLR = mask;
}
__STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel)
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_ficr.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_ficr.h
new file mode 100644
index 000000000..40b569885
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_ficr.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRF_FICR_H__
+#define NRF_FICR_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_ficr_hal FICR HAL
+ * @{
+ * @ingroup nrf_ficr
+ * @brief Hardware access layer (HAL) for getting data from
+ * the Factory Information Configuration Registers (FICR).
+ */
+
+/**
+ * @brief Function for getting the size of the code memory page.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Code memory page size in bytes.
+ */
+__STATIC_INLINE uint32_t nrf_ficr_codepagesize_get(NRF_FICR_Type const * p_reg);
+
+/**
+ * @brief Function for getting the size of the code memory rendered as number of pages.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Code memory size rendered as number of pages.
+ */
+__STATIC_INLINE uint32_t nrf_ficr_codesize_get(NRF_FICR_Type const * p_reg);
+
+/**
+ * @brief Function for getting the unique device identifier.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] reg_id Register index.
+ *
+ * @return Unique device identifier.
+ */
+__STATIC_INLINE uint32_t nrf_ficr_deviceid_get(NRF_FICR_Type const * p_reg, uint32_t reg_id);
+
+#if defined(FICR_NFC_TAGHEADER0_MFGID_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for getting the default header values for the NFC tag.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] tagheader_id Tag header index.
+ *
+ * @return The default header value of the NFC tag for the specified header index.
+ */
+__STATIC_INLINE uint32_t nrf_ficr_nfc_tagheader_get(NRF_FICR_Type const * p_reg,
+ uint32_t tagheader_id);
+#endif // defined(FICR_NFC_TAGHEADER0_MFGID_Msk) || defined(__NRFX_DOXYGEN__)
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE uint32_t nrf_ficr_codepagesize_get(NRF_FICR_Type const * p_reg)
+{
+#if defined(FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk)
+ return p_reg->INFO.CODEPAGESIZE;
+#else
+ return p_reg->CODEPAGESIZE;
+#endif
+}
+
+__STATIC_INLINE uint32_t nrf_ficr_codesize_get(NRF_FICR_Type const * p_reg)
+{
+#if defined(FICR_INFO_CODESIZE_CODESIZE_Msk)
+ return p_reg->INFO.CODESIZE;
+#else
+ return p_reg->CODESIZE;
+#endif
+}
+
+__STATIC_INLINE uint32_t nrf_ficr_deviceid_get(NRF_FICR_Type const * p_reg, uint32_t reg_id)
+{
+#if defined(FICR_INFO_DEVICEID_DEVICEID_Msk)
+ return p_reg->INFO.DEVICEID[reg_id];
+#else
+ return p_reg->DEVICEID[reg_id];
+#endif
+}
+
+#if defined(FICR_NFC_TAGHEADER0_MFGID_Msk)
+__STATIC_INLINE uint32_t nrf_ficr_nfc_tagheader_get(NRF_FICR_Type const * p_reg,
+ uint32_t tagheader_id)
+{
+ switch(tagheader_id) {
+ case 0:
+ return p_reg->NFC.TAGHEADER0;
+ break;
+ case 1:
+ return p_reg->NFC.TAGHEADER1;
+ break;
+ case 2:
+ return p_reg->NFC.TAGHEADER2;
+ break;
+ case 3:
+ return p_reg->NFC.TAGHEADER3;
+ break;
+ default:
+ return 0;
+ }
+}
+#endif // defined(FICR_NFC_TAGHEADER0_MFGID_Msk)
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_FICR_H__
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_gpio.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_gpio.h
index 7af4c548c..06a643cad 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_gpio.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_gpio.h
@@ -38,13 +38,6 @@
extern "C" {
#endif
-/**
- * @defgroup nrf_gpio_hal GPIO HAL
- * @{
- * @ingroup nrf_gpio
- * @brief Hardware access layer for managing the GPIO peripheral.
- */
-
#ifndef NRF_P0
#define NRF_P0 NRF_GPIO
#endif
@@ -59,24 +52,25 @@ extern "C" {
#error "Not supported."
#endif
-
/**
- * @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions.
+ * @defgroup nrf_gpio_hal GPIO HAL
+ * @{
+ * @ingroup nrf_gpio
+ * @brief Hardware access layer for managing the GPIO peripheral.
*/
+
+/** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */
#define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F))
-/**
- * @brief Pin direction definitions.
- */
+
+/** @brief Pin direction definitions. */
typedef enum
{
NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input.
NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output.
} nrf_gpio_pin_dir_t;
-/**
- * @brief Connection of input buffer.
- */
+/** @brief Connection of input buffer. */
typedef enum
{
NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer.
@@ -84,7 +78,8 @@ typedef enum
} nrf_gpio_pin_input_t;
/**
- * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration.
+ * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin
+ * configuration.
*/
typedef enum
{
@@ -93,9 +88,7 @@ typedef enum
NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled.
} nrf_gpio_pin_pull_t;
-/**
- * @brief Enumerator used for selecting output drive mode.
- */
+/** @brief Enumerator used for selecting output drive mode. */
typedef enum
{
NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'.
@@ -108,9 +101,7 @@ typedef enum
NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'.
} nrf_gpio_pin_drive_t;
-/**
- * @brief Enumerator used for selecting the pin to sense high or low level on the pin input.
- */
+/** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */
typedef enum
{
NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled.
@@ -118,16 +109,16 @@ typedef enum
NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
} nrf_gpio_pin_sense_t;
+
/**
* @brief Function for configuring the GPIO pin range as output pins with normal drive strength.
* This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
*
- * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
- *
- * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
- *
* @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output.
* Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
+ *
+ * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
+ * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
*/
__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
@@ -135,14 +126,12 @@ __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_
* @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details.
* This function can be used to configure pin range as simple input.
*
- * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
- *
- * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
- *
- * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
- *
* @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input.
* Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
+ *
+ * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
+ * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
+ * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
*/
__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
uint32_t pin_range_end,
@@ -153,6 +142,7 @@ __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_star
*
* The main pin configuration function.
* This function allows to set any aspect in PIN_CNF register.
+ *
* @param pin_number Specifies the pin number.
* @param dir Pin direction.
* @param input Connect or disconnect the input buffer.
@@ -172,9 +162,9 @@ __STATIC_INLINE void nrf_gpio_cfg(
* @brief Function for configuring the given GPIO pin number as output, hiding inner details.
* This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
*
- * @param pin_number Specifies the pin number.
- *
* @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
+ *
+ * @param pin_number Specifies the pin number.
*/
__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
@@ -182,10 +172,10 @@ __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
* @brief Function for configuring the given GPIO pin number as input, hiding inner details.
* This function can be used to configure a pin as simple input.
*
- * @param pin_number Specifies the pin number.
- * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
- *
* @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
+ *
+ * @param pin_number Specifies the pin number.
+ * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
*/
__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
@@ -208,7 +198,6 @@ __STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
* @brief Function for disconnecting input for the given GPIO.
*
* @param pin_number Specifies the pin number.
- *
*/
__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
@@ -230,7 +219,6 @@ __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
*
* @param pin_number Specifies the pin number.
* @param sense_config Sense configuration.
- *
*/
__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config);
@@ -238,25 +226,23 @@ __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_se
* @brief Function for setting the direction for a GPIO pin.
*
* @param pin_number Specifies the pin number for which to set the direction.
- *
- * @param direction Specifies the direction.
+ * @param direction Specifies the direction.
*/
__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
/**
* @brief Function for setting a GPIO pin.
*
- * Note that the pin must be configured as an output for this function to have any effect.
+ * For this function to have any effect, the pin must be configured as an output.
*
- * @param pin_number Specifies the pin number to set.
+ * @param pin_number Specifies the pin number to be set.
*/
__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
/**
* @brief Function for clearing a GPIO pin.
*
- * Note that the pin must be configured as an output for this
- * function to have any effect.
+ * For this function to have any effect, the pin must be configured as an output.
*
* @param pin_number Specifies the pin number to clear.
*/
@@ -265,8 +251,7 @@ __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
/**
* @brief Function for toggling a GPIO pin.
*
- * Note that the pin must be configured as an output for this
- * function to have any effect.
+ * For this function to have any effect, the pin must be configured as an output.
*
* @param pin_number Specifies the pin number to toggle.
*/
@@ -275,12 +260,10 @@ __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
/**
* @brief Function for writing a value to a GPIO pin.
*
- * Note that the pin must be configured as an output for this
- * function to have any effect.
+ * For this function to have any effect, the pin must be configured as an output.
*
* @param pin_number Specifies the pin number to write.
- *
- * @param value Specifies the value to be written to the pin.
+ * @param value Specifies the value to be written to the pin.
* @arg 0 Clears the pin.
* @arg >=1 Sets the pin.
*/
@@ -289,8 +272,7 @@ __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
/**
* @brief Function for reading the input level of a GPIO pin.
*
- * Note that the pin must have input connected for the value
- * returned from this function to be valid.
+ * If the value returned by this function is to be valid, the pin's input buffer must be connected.
*
* @param pin_number Specifies the pin number to read.
*
@@ -312,7 +294,7 @@ __STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
*
* @param pin_number Specifies the pin number to read.
*
- * @retval Sense configuration.
+ * @return Sense configuration.
*/
__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
@@ -321,7 +303,7 @@ __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
*
* @param pin_number Specifies the pin number to read.
*
- * @retval Direction configuration.
+ * @return Direction configuration.
*/
__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number);
@@ -344,88 +326,82 @@ __STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number)
__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number);
/**
- * @brief Function for setting output direction on selected pins on a given port.
+ * @brief Function for setting output direction on the selected pins on the given port.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
* @param out_mask Mask specifying the pins to set as output.
- *
*/
__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask);
/**
* @brief Function for setting input direction on selected pins on a given port.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param in_mask Mask specifying the pins to set as input.
- *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param in_mask Mask that specifies the pins to be set as input.
*/
__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask);
/**
- * @brief Function for writing the direction configuration of GPIO pins in a given port.
- *
- * @param p_reg Pointer to the peripheral registers structure.
- * @param dir_mask Mask specifying the direction of pins. Bit set means that the given pin is configured as output.
+ * @brief Function for writing the direction configuration of the GPIO pins in the given port.
*
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param dir_mask Mask that specifies the direction of pins. Bit set means that the given pin is configured as output.
*/
__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask);
/**
* @brief Function for reading the direction configuration of a GPIO port.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*
- * @retval Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
+ * @return Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
*/
__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg);
/**
- * @brief Function for reading the input signals of GPIO pins on a given port.
+ * @brief Function for reading the input signals of the GPIO pins on the given port.
*
* @param p_reg Pointer to the peripheral registers structure.
*
- * @retval Port input values.
+ * @return Port input values.
*/
__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
/**
- * @brief Function for reading the output signals of GPIO pins of a given port.
+ * @brief Function for reading the output signals of the GPIO pins on the given port.
*
* @param p_reg Pointer to the peripheral registers structure.
*
- * @retval Port output values.
+ * @return Port output values.
*/
__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
/**
* @brief Function for writing the GPIO pins output on a given port.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
* @param value Output port mask.
- *
*/
__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value);
/**
- * @brief Function for setting high level on selected GPIO pins of a given port.
- *
- * @param p_reg Pointer to the peripheral registers structure.
- * @param set_mask Mask with pins to set as logical high level.
+ * @brief Function for setting high level on selected the GPIO pins on the given port.
*
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param set_mask Mask with pins to be set as logical high level.
*/
__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask);
/**
- * @brief Function for setting low level on selected GPIO pins of a given port.
- *
- * @param p_reg Pointer to the peripheral registers structure.
- * @param clr_mask Mask with pins to set as logical low level.
+ * @brief Function for setting low level on selected the GPIO pins on the given port.
*
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param clr_mask Mask with pins to be set as logical low level.
*/
__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask);
/**
- * @brief Function for reading pins state of multiple consecutive ports.
+ * @brief Function for reading pin state of multiple consecutive ports.
*
* @param start_port Index of the first port to read.
* @param length Number of ports to read.
@@ -448,8 +424,8 @@ __STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length,
* @brief Function for reading latch state of single pin.
*
* @param pin_number Pin number.
- * @return 0 if latch is not set. Positive value otherwise.
*
+ * @return 0 if latch is not set. Positive value otherwise.
*/
__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
@@ -457,20 +433,19 @@ __STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
* @brief Function for clearing latch state of a single pin.
*
* @param pin_number Pin number.
- *
*/
__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
#endif
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
/**
- * @brief Function for extracting port and relative pin number from absolute pin number.
+ * @brief Function for extracting port and the relative pin number from the absolute pin number.
*
- * @param[inout] Pointer to absolute pin number which is overriden by relative to port pin number.
+ * @param[in,out] p_pin Pointer to the absolute pin number overriden by the pin number that is relative to the port.
*
* @return Pointer to port register set.
- *
*/
__STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
{
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_gpiote.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_gpiote.h
index 346e9505a..294f079e1 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_gpiote.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_gpiote.h
@@ -42,19 +42,18 @@ extern "C" {
* @defgroup nrf_gpiote_hal GPIOTE HAL
* @{
* @ingroup nrf_gpiote
-* @brief Hardware access layer for managing the GPIOTE peripheral.
+* @brief Hardware access layer (HAL) for managing the GPIOTE peripheral.
*/
-#ifdef GPIOTE_CONFIG_PORT_Msk
+#if defined(GPIOTE_CONFIG_PORT_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Mask for covering port and pin bits in registers. */
#define GPIOTE_CONFIG_PORT_PIN_Msk (GPIOTE_CONFIG_PORT_Msk | GPIOTE_CONFIG_PSEL_Msk)
#else
#define GPIOTE_CONFIG_PORT_PIN_Msk GPIOTE_CONFIG_PSEL_Msk
#endif
- /**
- * @enum nrf_gpiote_polarity_t
- * @brief Polarity for the GPIOTE channel.
- */
+
+ /** @brief Polarity for the GPIOTE channel. */
typedef enum
{
NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high.
@@ -62,78 +61,65 @@ typedef enum
NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle ///< Toggle.
} nrf_gpiote_polarity_t;
-
- /**
- * @enum nrf_gpiote_outinit_t
- * @brief Initial output value for the GPIOTE channel.
- */
+/** @brief Initial output value for the GPIOTE channel. */
typedef enum
{
NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high.
NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High ///< High to low.
} nrf_gpiote_outinit_t;
-/**
- * @brief Tasks.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief GPIOTE tasks. */
+typedef enum
{
- NRF_GPIOTE_TASKS_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0.*/
- NRF_GPIOTE_TASKS_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/
- NRF_GPIOTE_TASKS_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/
- NRF_GPIOTE_TASKS_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/
+ NRF_GPIOTE_TASKS_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0. */
+ NRF_GPIOTE_TASKS_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1. */
+ NRF_GPIOTE_TASKS_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2. */
+ NRF_GPIOTE_TASKS_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3. */
#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
- NRF_GPIOTE_TASKS_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/
- NRF_GPIOTE_TASKS_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/
- NRF_GPIOTE_TASKS_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/
- NRF_GPIOTE_TASKS_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/
+ NRF_GPIOTE_TASKS_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4. */
+ NRF_GPIOTE_TASKS_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5. */
+ NRF_GPIOTE_TASKS_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6. */
+ NRF_GPIOTE_TASKS_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7. */
#endif
#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__)
- NRF_GPIOTE_TASKS_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/
- NRF_GPIOTE_TASKS_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/
- NRF_GPIOTE_TASKS_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/
- NRF_GPIOTE_TASKS_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/
- NRF_GPIOTE_TASKS_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/
- NRF_GPIOTE_TASKS_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/
- NRF_GPIOTE_TASKS_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/
- NRF_GPIOTE_TASKS_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/
+ NRF_GPIOTE_TASKS_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0. */
+ NRF_GPIOTE_TASKS_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1. */
+ NRF_GPIOTE_TASKS_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2. */
+ NRF_GPIOTE_TASKS_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3. */
+ NRF_GPIOTE_TASKS_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4. */
+ NRF_GPIOTE_TASKS_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5. */
+ NRF_GPIOTE_TASKS_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6. */
+ NRF_GPIOTE_TASKS_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7. */
#endif
#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__)
- NRF_GPIOTE_TASKS_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/
- NRF_GPIOTE_TASKS_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/
- NRF_GPIOTE_TASKS_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/
- NRF_GPIOTE_TASKS_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/
- NRF_GPIOTE_TASKS_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/
- NRF_GPIOTE_TASKS_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/
- NRF_GPIOTE_TASKS_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/
- NRF_GPIOTE_TASKS_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/
+ NRF_GPIOTE_TASKS_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0. */
+ NRF_GPIOTE_TASKS_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1. */
+ NRF_GPIOTE_TASKS_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2. */
+ NRF_GPIOTE_TASKS_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3. */
+ NRF_GPIOTE_TASKS_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4. */
+ NRF_GPIOTE_TASKS_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5. */
+ NRF_GPIOTE_TASKS_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6. */
+ NRF_GPIOTE_TASKS_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7. */
#endif
- /*lint -restore*/
} nrf_gpiote_tasks_t;
-/**
- * @brief Events.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief GPIOTE events. */
+typedef enum
{
- NRF_GPIOTE_EVENTS_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0.*/
- NRF_GPIOTE_EVENTS_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/
- NRF_GPIOTE_EVENTS_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/
- NRF_GPIOTE_EVENTS_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/
+ NRF_GPIOTE_EVENTS_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0. */
+ NRF_GPIOTE_EVENTS_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1. */
+ NRF_GPIOTE_EVENTS_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2. */
+ NRF_GPIOTE_EVENTS_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3. */
#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
- NRF_GPIOTE_EVENTS_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/
- NRF_GPIOTE_EVENTS_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/
- NRF_GPIOTE_EVENTS_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/
- NRF_GPIOTE_EVENTS_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/
+ NRF_GPIOTE_EVENTS_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4. */
+ NRF_GPIOTE_EVENTS_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5. */
+ NRF_GPIOTE_EVENTS_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6. */
+ NRF_GPIOTE_EVENTS_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7. */
#endif
- NRF_GPIOTE_EVENTS_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event.*/
- /*lint -restore*/
+ NRF_GPIOTE_EVENTS_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event. */
} nrf_gpiote_events_t;
-/**
- * @enum nrf_gpiote_int_t
- * @brief GPIOTE interrupts.
- */
+/** @brief GPIOTE interrupts. */
typedef enum
{
NRF_GPIOTE_INT_IN0_MASK = GPIOTE_INTENSET_IN0_Msk, /**< GPIOTE interrupt from IN0. */
@@ -149,10 +135,11 @@ typedef enum
NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */
} nrf_gpiote_int_t;
+#if (GPIOTE_CH_NUM == 4) || defined(__NRFX_DOXYGEN__)
+/** @brief Mask holding positions of available GPIOTE input interrupts. */
#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK)
-#if (GPIOTE_CH_NUM > 4)
-#undef NRF_GPIOTE_INT_IN_MASK
+#else
#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\
NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\
@@ -160,61 +147,67 @@ typedef enum
#endif
/**
- * @brief Function for activating a specific GPIOTE task.
+ * @brief Function for activating the specified GPIOTE task.
*
- * @param[in] task Task.
+ * @param[in] task Task.
*/
__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task);
/**
- * @brief Function for getting the address of a specific GPIOTE task.
+ * @brief Function for getting the address of the specified GPIOTE task.
*
* @param[in] task Task.
*
- * @returns Address.
+ * @return Address of the specified task.
*/
__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task);
/**
- * @brief Function for getting the state of a specific GPIOTE event.
+ * @brief Function for getting the state of the specified GPIOTE event.
*
* @param[in] event Event.
+ *
+ * @retval true The event is set.
+ * @retval false The event is not set.
*/
__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event);
/**
- * @brief Function for clearing a specific GPIOTE event.
+ * @brief Function for clearing the specified GPIOTE event.
*
* @param[in] event Event.
*/
__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event);
/**
- * @brief Function for getting the address of a specific GPIOTE event.
+ * @brief Function for getting the address of the specified GPIOTE event.
*
* @param[in] event Event.
*
- * @return Address
+ * @return Address of the specified event.
*/
__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event);
-/**@brief Function for enabling interrupts.
+/**
+ * @brief Function for enabling interrupts.
*
- * @param[in] mask Interrupt mask to be enabled.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask);
-/**@brief Function for disabling interrupts.
+/**
+ * @brief Function for disabling interrupts.
*
- * @param[in] mask Interrupt mask to be disabled.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask);
-/**@brief Function for checking if interrupts are enabled.
+/**
+ * @brief Function for checking if interrupts are enabled.
*
- * @param[in] mask Mask of interrupt flags to check.
+ * @param[in] mask Mask of interrupts to be checked.
*
- * @return Mask with enabled interrupts.
+ * @return Mask with enabled interrupts.
*/
__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask);
@@ -256,77 +249,90 @@ __STATIC_INLINE void nrf_gpiote_publish_set(nrf_gpiote_events_t event,
__STATIC_INLINE void nrf_gpiote_publish_clear(nrf_gpiote_events_t event);
#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
-/**@brief Function for enabling a GPIOTE event.
+/**
+ * @brief Function for enabling a GPIOTE event.
*
- * @param[in] idx Task-Event index.
+ * @param[in] idx Task-Event index.
*/
__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx);
-/**@brief Function for disabling a GPIOTE event.
+/**
+ * @brief Function for disabling a GPIOTE event.
*
- * @param[in] idx Task-Event index.
+ * @param[in] idx Task-Event index.
*/
__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx);
-/**@brief Function for configuring a GPIOTE event.
+/**
+ * @brief Function for configuring a GPIOTE event.
*
- * @param[in] idx Task-Event index.
- * @param[in] pin Pin associated with event.
- * @param[in] polarity Transition that should generate an event.
+ * @param[in] idx Task-Event index.
+ * @param[in] pin Pin associated with event.
+ * @param[in] polarity Transition that should generate an event.
*/
-__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin,
+__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx,
+ uint32_t pin,
nrf_gpiote_polarity_t polarity);
-/**@brief Function for getting the pin associated with a GPIOTE event.
+/**
+ * @brief Function for getting the pin associated with a GPIOTE event.
*
- * @param[in] idx Task-Event index.
+ * @param[in] idx Task-Event index.
*
* @return Pin number.
*/
__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx);
-/**@brief Function for getting the polarity associated with a GPIOTE event.
+/**
+ * @brief Function for getting the polarity associated with a GPIOTE event.
*
- * @param[in] idx Task-Event index.
+ * @param[in] idx Task-Event index.
*
* @return Polarity.
*/
__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx);
-/**@brief Function for enabling a GPIOTE task.
+/**
+ * @brief Function for enabling a GPIOTE task.
*
- * @param[in] idx Task-Event index.
+ * @param[in] idx Task-Event index.
*/
__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx);
-/**@brief Function for disabling a GPIOTE task.
+/**
+ * @brief Function for disabling a GPIOTE task.
*
- * @param[in] idx Task-Event index.
+ * @param[in] idx Task-Event index.
*/
__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx);
-/**@brief Function for configuring a GPIOTE task.
+/**
+ * @brief Function for configuring a GPIOTE task.
+ *
* @note Function is not configuring mode field so task is disabled after this function is called.
*
- * @param[in] idx Task-Event index.
- * @param[in] pin Pin associated with event.
- * @param[in] polarity Transition that should generate an event.
- * @param[in] init_val Initial value of the pin.
+ * @param[in] idx Task-Event index.
+ * @param[in] pin Pin associated with event.
+ * @param[in] polarity Transition that should generate an event.
+ * @param[in] init_val Initial value of the pin.
*/
-__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
+__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx,
+ uint32_t pin,
nrf_gpiote_polarity_t polarity,
nrf_gpiote_outinit_t init_val);
-/**@brief Function for forcing a specific state on the pin connected to GPIOTE.
+/**
+ * @brief Function for forcing the specified state on the pin connected to GPIOTE.
*
- * @param[in] idx Task-Event index.
- * @param[in] init_val Pin state.
+ * @param[in] idx Task-Event index.
+ * @param[in] init_val Pin state.
*/
__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val);
-/**@brief Function for resetting a GPIOTE task event configuration to the default state.
+/**
+ * @brief Function for resetting a GPIOTE task event configuration to the default state.
*
- * @param[in] idx Task-Event index.
+ * @param[in] idx Task-Event index.
*/
__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx);
@@ -334,12 +340,53 @@ __STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx);
*
* @param[in] idx Task-Event index.
*
- * @retval true If the Task-Event mode is set to Task or Event.
- * @retval false If the Task-Event mode is set to Disabled.
+ * @retval true The Task-Event mode is set to Task or Event.
+ * @retval false The Task-Event mode is set to Disabled.
*/
__STATIC_INLINE bool nrf_gpiote_te_is_enabled(uint32_t idx);
+/**
+ * @brief Function for getting the OUT task associated with the specified GPIOTE channel.
+ *
+ * @param[in] index Channel index.
+ *
+ * @return Requested OUT task.
+ */
+__STATIC_INLINE nrf_gpiote_tasks_t nrf_gpiote_out_task_get(uint8_t index);
+
+#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for getting the SET task associated with the specified GPIOTE channel.
+ *
+ * @param[in] index Channel index.
+ *
+ * @return Requested SET task.
+ */
+__STATIC_INLINE nrf_gpiote_tasks_t nrf_gpiote_set_task_get(uint8_t index);
+#endif
+
+#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for getting the CLR task associated with the specified GPIOTE channel.
+ *
+ * @param[in] index Channel index.
+ *
+ * @return Requested CLR task.
+ */
+__STATIC_INLINE nrf_gpiote_tasks_t nrf_gpiote_clr_task_get(uint8_t index);
+#endif
+
+/**
+ * @brief Function for getting the IN event associated with the specified GPIOTE channel.
+ *
+ * @param[in] index Channel index.
+ *
+ * @return Requested IN event.
+ */
+__STATIC_INLINE nrf_gpiote_events_t nrf_gpiote_in_event_get(uint8_t index);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task)
{
*(__IO uint32_t *)((uint32_t)NRF_GPIOTE + task) = 0x1UL;
@@ -443,7 +490,7 @@ __STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx)
#ifdef NRF51
/* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the
- correct state in GPIOTE but not in the OUT register. */
+ correct state in GPIOTE, but not in the OUT register. */
/* Configure channel to not existing, not connected to the pin, and configure as a tasks that will set it to proper level */
NRF_GPIOTE->CONFIG[idx] = final_config | (((31) << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk);
__NOP();
@@ -486,6 +533,35 @@ __STATIC_INLINE bool nrf_gpiote_te_is_enabled(uint32_t idx)
{
return (NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_MODE_Msk) != GPIOTE_CONFIG_MODE_Disabled;
}
+
+__STATIC_INLINE nrf_gpiote_tasks_t nrf_gpiote_out_task_get(uint8_t index)
+{
+ NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_GPIOTE->TASKS_OUT));
+ return (nrf_gpiote_tasks_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, TASKS_OUT[index]);
+}
+
+#if defined(GPIOTE_FEATURE_SET_PRESENT)
+__STATIC_INLINE nrf_gpiote_tasks_t nrf_gpiote_set_task_get(uint8_t index)
+{
+ NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_GPIOTE->TASKS_SET));
+ return (nrf_gpiote_tasks_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, TASKS_SET[index]);
+}
+#endif
+
+#if defined(GPIOTE_FEATURE_CLR_PRESENT)
+__STATIC_INLINE nrf_gpiote_tasks_t nrf_gpiote_clr_task_get(uint8_t index)
+{
+ NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_GPIOTE->TASKS_CLR));
+ return (nrf_gpiote_tasks_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, TASKS_CLR[index]);
+}
+#endif
+
+__STATIC_INLINE nrf_gpiote_events_t nrf_gpiote_in_event_get(uint8_t index)
+{
+ NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_GPIOTE->EVENTS_IN));
+ return (nrf_gpiote_events_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
+}
+
#endif //SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_i2s.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_i2s.h
index 4e141ef74..96c8b09de 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_i2s.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_i2s.h
@@ -47,38 +47,28 @@ extern "C" {
/**
* @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set
- * function call to specify that a given I2S signal (SDOUT, SDIN, or MCK)
+ * function call to specify that the given I2S signal (SDOUT, SDIN, or MCK)
* shall not be connected to a physical pin.
*/
#define NRF_I2S_PIN_NOT_CONNECTED 0xFFFFFFFF
-/**
- * @brief I2S tasks.
- */
+/** @brief I2S tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_I2S_TASK_START = offsetof(NRF_I2S_Type, TASKS_START), ///< Starts continuous I2S transfer. Also starts the MCK generator if this is enabled.
NRF_I2S_TASK_STOP = offsetof(NRF_I2S_Type, TASKS_STOP) ///< Stops I2S transfer. Also stops the MCK generator.
- /*lint -restore*/
} nrf_i2s_task_t;
-/**
- * @brief I2S events.
- */
+/** @brief I2S events. */
typedef enum
{
- /*lint -save -e30*/
- NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double-buffers.
- NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double-buffers.
+ NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double buffers.
+ NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double buffers.
NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED) ///< I2S transfer stopped.
- /*lint -restore*/
} nrf_i2s_event_t;
-/**
- * @brief I2S interrupts.
- */
+/** @brief I2S interrupts. */
typedef enum
{
NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event.
@@ -86,18 +76,14 @@ typedef enum
NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk ///< Interrupt on STOPPED event.
} nrf_i2s_int_mask_t;
-/**
- * @brief I2S modes of operation.
- */
+/** @brief I2S modes of operation. */
typedef enum
{
NRF_I2S_MODE_MASTER = I2S_CONFIG_MODE_MODE_Master, ///< Master mode.
NRF_I2S_MODE_SLAVE = I2S_CONFIG_MODE_MODE_Slave ///< Slave mode.
} nrf_i2s_mode_t;
-/**
- * @brief I2S master clock generator settings.
- */
+/** @brief I2S master clock generator settings. */
typedef enum
{
NRF_I2S_MCK_DISABLED = 0, ///< MCK disabled.
@@ -125,15 +111,15 @@ typedef enum
NRF_I2S_MCK_32MDIV16 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16, ///< 32 MHz / 16 = 2.0 MHz.
NRF_I2S_MCK_32MDIV21 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21, ///< 32 MHz / 21 = 1.5238095 MHz.
NRF_I2S_MCK_32MDIV23 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23, ///< 32 MHz / 23 = 1.3913043 MHz.
+ NRF_I2S_MCK_32MDIV30 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30, ///< 32 MHz / 30 = 1.0666667 MHz.
NRF_I2S_MCK_32MDIV31 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31, ///< 32 MHz / 31 = 1.0322581 MHz.
+ NRF_I2S_MCK_32MDIV32 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32, ///< 32 MHz / 32 = 1.0 MHz.
NRF_I2S_MCK_32MDIV42 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42, ///< 32 MHz / 42 = 0.7619048 MHz.
NRF_I2S_MCK_32MDIV63 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63, ///< 32 MHz / 63 = 0.5079365 MHz.
NRF_I2S_MCK_32MDIV125 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 ///< 32 MHz / 125 = 0.256 MHz.
} nrf_i2s_mck_t;
-/**
- * @brief I2S MCK/LRCK ratios.
- */
+/** @brief I2S MCK/LRCK ratios. */
typedef enum
{
NRF_I2S_RATIO_32X = I2S_CONFIG_RATIO_RATIO_32X, ///< LRCK = MCK / 32.
@@ -147,9 +133,7 @@ typedef enum
NRF_I2S_RATIO_512X = I2S_CONFIG_RATIO_RATIO_512X ///< LRCK = MCK / 512.
} nrf_i2s_ratio_t;
-/**
- * @brief I2S sample widths.
- */
+/** @brief I2S sample widths. */
typedef enum
{
NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit.
@@ -157,27 +141,21 @@ typedef enum
NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit ///< 24 bit.
} nrf_i2s_swidth_t;
-/**
- * @brief I2S alignments of sample within a frame.
- */
+/** @brief I2S alignments of sample within a frame. */
typedef enum
{
NRF_I2S_ALIGN_LEFT = I2S_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned.
NRF_I2S_ALIGN_RIGHT = I2S_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned.
} nrf_i2s_align_t;
-/**
- * @brief I2S frame formats.
- */
+/** @brief I2S frame formats. */
typedef enum
{
NRF_I2S_FORMAT_I2S = I2S_CONFIG_FORMAT_FORMAT_I2S, ///< Original I2S format.
- NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left- or right-aligned) format.
+ NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left-aligned or right-aligned) format.
} nrf_i2s_format_t;
-/**
- * @brief I2S enabled channels.
- */
+/** @brief I2S enabled channels. */
typedef enum
{
NRF_I2S_CHANNELS_STEREO = I2S_CONFIG_CHANNELS_CHANNELS_Stereo, ///< Stereo.
@@ -187,19 +165,19 @@ typedef enum
/**
- * @brief Function for activating a specific I2S task.
+ * @brief Function for activating the specified I2S task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] task Task to activate.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_reg,
nrf_i2s_task_t task);
/**
- * @brief Function for getting the address of a specific I2S task register.
+ * @brief Function for getting the address of the specified I2S task register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] task Requested task.
+ * @param[in] task Specified task.
*
* @return Address of the specified task register.
*/
@@ -207,31 +185,31 @@ __STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_reg,
nrf_i2s_task_t task);
/**
- * @brief Function for clearing a specific I2S event.
+ * @brief Function for clearing the specified I2S event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to clear.
*/
-__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_reg,
+__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_reg,
nrf_i2s_event_t event);
/**
- * @brief Function for checking the state of a specific I2S event.
+ * @brief Function for retrieving the state of the I2S event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] event Event to check.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_reg,
nrf_i2s_event_t event);
/**
- * @brief Function for getting the address of a specific I2S event register.
+ * @brief Function for getting the address of the specified I2S event register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] event Requested event.
+ * @param[in] event Specified event.
*
* @return Address of the specified event register.
*/
@@ -242,7 +220,7 @@ __STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_reg,
* @brief Function for enabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] mask Interrupts to enable.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_reg, uint32_t mask);
@@ -250,18 +228,18 @@ __STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_reg, uint32_t mask);
* @brief Function for disabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] mask Interrupts to disable.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_reg, uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] i2s_int Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] i2s_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_reg,
nrf_i2s_int_mask_t i2s_int);
@@ -359,8 +337,8 @@ __STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_reg,
* @param[in] mck_setup Master clock generator setup.
* @param[in] ratio MCK/LRCK ratio.
*
- * @retval true If the configuration has been set successfully.
- * @retval false If the requested configuration is not allowed.
+ * @retval true The configuration has been set successfully.
+ * @retval false The specified configuration is not allowed.
*/
__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_reg,
nrf_i2s_mode_t mode,
@@ -374,8 +352,8 @@ __STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_reg,
/**
* @brief Function for setting up the I2S transfer.
*
- * This function sets up the RX and TX buffers and enables reception and/or
- * transmission accordingly. If the transfer in a given direction is not
+ * This function sets up the RX and TX buffers and enables reception or
+ * transmission (or both) accordingly. If the transfer in a given direction is not
* required, pass NULL instead of the pointer to the corresponding buffer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -550,7 +528,7 @@ __STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_reg,
{
if (mode == NRF_I2S_MODE_MASTER)
{
- // The MCK/LRCK ratio shall be a multiple of 2 * sample width.
+ // The MCK/LRCK ratio must be a multiple of 2 * sample width.
if (((sample_width == NRF_I2S_SWIDTH_16BIT) &&
(ratio == NRF_I2S_RATIO_48X))
||
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_kmu.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_kmu.h
index 3bfbcf415..064820f3e 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_kmu.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_kmu.h
@@ -78,15 +78,15 @@ typedef enum
/**
* @brief Function for activating a specific KMU task.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] task Task to activate.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_kmu_task_trigger(NRF_KMU_Type * p_reg, nrf_kmu_task_t task);
/**
* @brief Function for getting the address of a specific KMU task register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Requested task.
*
* @return Address of the specified task register.
@@ -96,26 +96,26 @@ __STATIC_INLINE uint32_t nrf_kmu_task_address_get(NRF_KMU_Type const * p_reg, nr
/**
* @brief Function for clearing a specific KMU event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_kmu_event_clear(NRF_KMU_Type * p_reg, nrf_kmu_event_t event);
/**
- * @brief Function for checking the state of a specific KMU event.
+ * @brief Function for retrieving the state of the KMU event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_kmu_event_check(NRF_KMU_Type const * p_reg, nrf_kmu_event_t event);
/**
* @brief Function for getting the address of a specific KMU event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Requested event.
*
* @return Address of the specified event register.
@@ -126,27 +126,27 @@ __STATIC_INLINE uint32_t nrf_kmu_event_address_get(NRF_KMU_Type const * p_reg,
/**
* @brief Function for enabling specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Interrupts to be enabled.
*/
__STATIC_INLINE void nrf_kmu_int_enable(NRF_KMU_Type * p_reg, uint32_t mask);
/**
* @brief Function for disabling specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Interrupts to be disabled.
*/
__STATIC_INLINE void nrf_kmu_int_disable(NRF_KMU_Type * p_reg, uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] kmu_int Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] kmu_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_kmu_int_enable_check(NRF_KMU_Type const * p_reg,
nrf_kmu_int_mask_t kmu_int);
@@ -156,7 +156,7 @@ __STATIC_INLINE bool nrf_kmu_int_enable_check(NRF_KMU_Type const * p_reg,
*
* Function returns bitmask. Please use @ref nrf_kmu_int_mask_t to check interrupts status.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Bitmask with pending interrupts bits.
*/
@@ -167,7 +167,7 @@ __STATIC_INLINE uint32_t nrf_kmu_intpend_get(NRF_KMU_Type const * p_reg);
*
* Function returns bitmask. Please use @ref nrf_kmu_status_t to check operations status.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Bitmask with operation status bits.
*/
@@ -176,7 +176,7 @@ __STATIC_INLINE uint32_t nrf_kmu_status_get(NRF_KMU_Type const * p_reg);
/**
* @brief Function for selecting the key slot ID.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] keyslot_id Key slot ID to be read over AHB or pushed over
* secure APB when TASKS_PUSH_KEYSLOT is started.
*/
@@ -185,7 +185,7 @@ __STATIC_INLINE void nrf_kmu_keyslot_set(NRF_KMU_Type * p_reg, uint8_t keyslot_i
/**
* @brief Function for getting the key slot ID.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Key slot ID.
*/
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_lpcomp.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_lpcomp.h
index d1d249cfe..7afdf625b 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_lpcomp.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_lpcomp.h
@@ -45,10 +45,7 @@ extern "C" {
* @brief Hardware access layer for managing the Low Power Comparator (LPCOMP) peripheral.
*/
-/**
- * @enum nrf_lpcomp_ref_t
- * @brief LPCOMP reference selection.
- */
+/** @brief LPCOMP reference selection. */
typedef enum
{
#if (LPCOMP_REFSEL_RESOLUTION == 8) || defined(__NRFX_DOXYGEN__)
@@ -60,32 +57,29 @@ typedef enum
NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling, /**< Use supply with a 6/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling, /**< Use supply with a 7/8 prescaler as reference. */
#elif (LPCOMP_REFSEL_RESOLUTION == 16) || defined(__NRFX_DOXYGEN__)
- NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_Ref1_8Vdd, /**< Use supply with a 1/8 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_Ref2_8Vdd, /**< Use supply with a 2/8 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_Ref3_8Vdd, /**< Use supply with a 3/8 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_Ref4_8Vdd, /**< Use supply with a 4/8 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_Ref5_8Vdd, /**< Use supply with a 5/8 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_Ref6_8Vdd, /**< Use supply with a 6/8 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_Ref7_8Vdd, /**< Use supply with a 7/8 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_1_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 1/16 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_3_16 = LPCOMP_REFSEL_REFSEL_Ref3_16Vdd, /**< Use supply with a 3/16 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_5_16 = LPCOMP_REFSEL_REFSEL_Ref5_16Vdd, /**< Use supply with a 5/16 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_7_16 = LPCOMP_REFSEL_REFSEL_Ref7_16Vdd, /**< Use supply with a 7/16 prescaler as reference. */
- NRF_LPCOMP_REF_SUPPLY_9_16 = LPCOMP_REFSEL_REFSEL_Ref9_16Vdd, /**< Use supply with a 9/16 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_Ref1_8Vdd, /**< Use supply with a 1/8 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_Ref2_8Vdd, /**< Use supply with a 2/8 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_Ref3_8Vdd, /**< Use supply with a 3/8 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_Ref4_8Vdd, /**< Use supply with a 4/8 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_Ref5_8Vdd, /**< Use supply with a 5/8 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_Ref6_8Vdd, /**< Use supply with a 6/8 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_Ref7_8Vdd, /**< Use supply with a 7/8 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_1_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 1/16 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_3_16 = LPCOMP_REFSEL_REFSEL_Ref3_16Vdd, /**< Use supply with a 3/16 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_5_16 = LPCOMP_REFSEL_REFSEL_Ref5_16Vdd, /**< Use supply with a 5/16 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_7_16 = LPCOMP_REFSEL_REFSEL_Ref7_16Vdd, /**< Use supply with a 7/16 prescaler as reference. */
+ NRF_LPCOMP_REF_SUPPLY_9_16 = LPCOMP_REFSEL_REFSEL_Ref9_16Vdd, /**< Use supply with a 9/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_11_16 = LPCOMP_REFSEL_REFSEL_Ref11_16Vdd, /**< Use supply with a 11/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_13_16 = LPCOMP_REFSEL_REFSEL_Ref13_16Vdd, /**< Use supply with a 13/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_15_16 = LPCOMP_REFSEL_REFSEL_Ref15_16Vdd, /**< Use supply with a 15/16 prescaler as reference. */
#endif
NRF_LPCOMP_REF_EXT_REF0 = LPCOMP_REFSEL_REFSEL_ARef |
- (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 << 16), /**< External reference 0. */
+ (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 << 16), /**< External reference 0. */
NRF_LPCOMP_CONFIG_REF_EXT_REF1 = LPCOMP_REFSEL_REFSEL_ARef |
(LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 << 16), /**< External reference 1. */
} nrf_lpcomp_ref_t;
-/**
- * @enum nrf_lpcomp_input_t
- * @brief LPCOMP input selection.
- */
+/** @brief LPCOMP input selection. */
typedef enum
{
NRF_LPCOMP_INPUT_0 = LPCOMP_PSEL_PSEL_AnalogInput0, /**< Input 0. */
@@ -98,10 +92,7 @@ typedef enum
NRF_LPCOMP_INPUT_7 = LPCOMP_PSEL_PSEL_AnalogInput7 /**< Input 7. */
} nrf_lpcomp_input_t;
-/**
- * @enum nrf_lpcomp_detect_t
- * @brief LPCOMP detection type selection.
- */
+/** @brief LPCOMP detection type selection. */
typedef enum
{
NRF_LPCOMP_DETECT_CROSS = LPCOMP_ANADETECT_ANADETECT_Cross, /**< Generate ANADETEC on crossing, both upwards and downwards crossing. */
@@ -109,52 +100,40 @@ typedef enum
NRF_LPCOMP_DETECT_DOWN = LPCOMP_ANADETECT_ANADETECT_Down /**< Generate ANADETEC on downwards crossing only. */
} nrf_lpcomp_detect_t;
-/**
- * @enum nrf_lpcomp_task_t
- * @brief LPCOMP tasks.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief LPCOMP tasks. */
+typedef enum
{
NRF_LPCOMP_TASK_START = offsetof(NRF_LPCOMP_Type, TASKS_START), /**< LPCOMP start sampling task. */
NRF_LPCOMP_TASK_STOP = offsetof(NRF_LPCOMP_Type, TASKS_STOP), /**< LPCOMP stop sampling task. */
NRF_LPCOMP_TASK_SAMPLE = offsetof(NRF_LPCOMP_Type, TASKS_SAMPLE) /**< Sample comparator value. */
-} nrf_lpcomp_task_t; /*lint -restore*/
+} nrf_lpcomp_task_t;
-/**
- * @enum nrf_lpcomp_event_t
- * @brief LPCOMP events.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief LPCOMP events. */
+typedef enum
{
NRF_LPCOMP_EVENT_READY = offsetof(NRF_LPCOMP_Type, EVENTS_READY), /**< LPCOMP is ready and output is valid. */
NRF_LPCOMP_EVENT_DOWN = offsetof(NRF_LPCOMP_Type, EVENTS_DOWN), /**< Input voltage crossed the threshold going down. */
NRF_LPCOMP_EVENT_UP = offsetof(NRF_LPCOMP_Type, EVENTS_UP), /**< Input voltage crossed the threshold going up. */
NRF_LPCOMP_EVENT_CROSS = offsetof(NRF_LPCOMP_Type, EVENTS_CROSS) /**< Input voltage crossed the threshold in any direction. */
-} nrf_lpcomp_event_t; /*lint -restore*/
+} nrf_lpcomp_event_t;
-/**
- * @enum nrf_lpcomp_short_mask_t
- * @brief LPCOMP shorts masks.
- */
+/** @brief LPCOMP shortcut masks. */
typedef enum
{
- NRF_LPCOMP_SHORT_CROSS_STOP_MASK = LPCOMP_SHORTS_CROSS_STOP_Msk, /*!< Short between CROSS event and STOP task. */
- NRF_LPCOMP_SHORT_UP_STOP_MASK = LPCOMP_SHORTS_UP_STOP_Msk, /*!< Short between UP event and STOP task. */
- NRF_LPCOMP_SHORT_DOWN_STOP_MASK = LPCOMP_SHORTS_DOWN_STOP_Msk, /*!< Short between DOWN event and STOP task. */
- NRF_LPCOMP_SHORT_READY_STOP_MASK = LPCOMP_SHORTS_READY_STOP_Msk, /*!< Short between READY event and STOP task. */
- NRF_LPCOMP_SHORT_READY_SAMPLE_MASK = LPCOMP_SHORTS_READY_SAMPLE_Msk /*!< Short between READY event and SAMPLE task. */
+ NRF_LPCOMP_SHORT_CROSS_STOP_MASK = LPCOMP_SHORTS_CROSS_STOP_Msk, /*!< Shortcut between CROSS event and STOP task. */
+ NRF_LPCOMP_SHORT_UP_STOP_MASK = LPCOMP_SHORTS_UP_STOP_Msk, /*!< Shortcut between UP event and STOP task. */
+ NRF_LPCOMP_SHORT_DOWN_STOP_MASK = LPCOMP_SHORTS_DOWN_STOP_Msk, /*!< Shortcut between DOWN event and STOP task. */
+ NRF_LPCOMP_SHORT_READY_STOP_MASK = LPCOMP_SHORTS_READY_STOP_Msk, /*!< Shortcut between READY event and STOP task. */
+ NRF_LPCOMP_SHORT_READY_SAMPLE_MASK = LPCOMP_SHORTS_READY_SAMPLE_Msk /*!< Shortcut between READY event and SAMPLE task. */
} nrf_lpcomp_short_mask_t;
#ifdef LPCOMP_FEATURE_HYST_PRESENT
-/**
- * @enum nrf_lpcomp_hysteresis_t
- * @brief LPCOMP hysteresis.
- */
+/** @brief LPCOMP hysteresis. */
typedef enum
{
NRF_LPCOMP_HYST_NOHYST = LPCOMP_HYST_HYST_NoHyst, /**< Comparator hysteresis disabled. */
- NRF_LPCOMP_HYST_50mV = LPCOMP_HYST_HYST_Hyst50mV /**< Comparator hysteresis enabled (typ. 50 mV). */
+ NRF_LPCOMP_HYST_50mV = LPCOMP_HYST_HYST_Hyst50mV /**< Comparator hysteresis enabled (typically 50 mV). */
}nrf_lpcomp_hysteresis_t;
#endif // LPCOMP_FEATURE_HYST_PRESENT
@@ -168,9 +147,11 @@ typedef struct
#endif // LPCOMP_FEATURE_HYST_PRESENT
} nrf_lpcomp_config_t;
+
/** Default LPCOMP configuration. */
#define NRF_LPCOMP_CONFIG_DEFAULT { NRF_LPCOMP_REF_SUPPLY_FOUR_EIGHT, NRF_LPCOMP_DETECT_DOWN }
+
/**
* @brief Function for configuring LPCOMP.
*
@@ -194,7 +175,6 @@ __STATIC_INLINE void nrf_lpcomp_input_select(nrf_lpcomp_input_t input);
* @brief Function for enabling the Low Power Comparator.
*
* This function enables LPCOMP.
- *
*/
__STATIC_INLINE void nrf_lpcomp_enable(void);
@@ -202,7 +182,6 @@ __STATIC_INLINE void nrf_lpcomp_enable(void);
* @brief Function for disabling the Low Power Comparator.
*
* This function disables LPCOMP.
- *
*/
__STATIC_INLINE void nrf_lpcomp_disable(void);
@@ -216,92 +195,91 @@ __STATIC_INLINE uint32_t nrf_lpcomp_result_get(void);
/**
* @brief Function for enabling interrupts from LPCOMP.
*
- * @param[in] lpcomp_int_mask Mask of interrupts to be enabled.
+ * @param[in] int_mask Mask of interrupts to be enabled.
*
- * @sa nrf_lpcomp_int_disable()
- * @sa nrf_lpcomp_int_enable_check()
+ * @sa nrf_lpcomp_int_disable
+ * @sa nrf_lpcomp_int_enable_check
*/
-__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t lpcomp_int_mask);
+__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t int_mask);
/**
* @brief Function for disabling interrupts from LPCOMP.
*
- * @param[in] lpcomp_int_mask Mask of interrupts to be disabled.
+ * @param[in] int_mask Mask of interrupts to be disabled.
*
- * @sa nrf_lpcomp_int_enable()
- * @sa nrf_lpcomp_int_enable_check()
+ * @sa nrf_lpcomp_int_enable
+ * @sa nrf_lpcomp_int_enable_check
*/
-__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t lpcomp_int_mask);
+__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t int_mask);
/**
* @brief Function for getting the enabled interrupts of LPCOMP.
*
- * @param[in] lpcomp_int_mask Mask of interrupts to be checked.
+ * @param[in] int_mask Mask of interrupts to be checked.
*
- * @retval true If any of interrupts of the specified mask are enabled.
+ * @retval true Any of interrupts of the specified mask are enabled.
+ * @retval false None interrupt specified by the mask are enabled.
*
- * @sa nrf_lpcomp_int_enable()
- * @sa nrf_lpcomp_int_disable()
+ * @sa nrf_lpcomp_int_enable
+ * @sa nrf_lpcomp_int_disable
*/
-__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t lpcomp_int_mask);
+__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t int_mask);
/**
- * @brief Function for getting the address of a specific LPCOMP task register.
+ * @brief Function for getting the address of the specified LPCOMP task register.
*
- * @param[in] lpcomp_task LPCOMP task.
+ * @param[in] task LPCOMP task.
*
* @return The address of the specified LPCOMP task.
*/
-__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t lpcomp_task);
+__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t task);
/**
- * @brief Function for getting the address of a specific LPCOMP event register.
+ * @brief Function for getting the address of the specified LPCOMP event register.
*
- * @param[in] lpcomp_event LPCOMP event.
+ * @param[in] event LPCOMP event.
*
* @return The address of the specified LPCOMP event.
*/
-__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t lpcomp_event);
+__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t event);
/**
* @brief Function for setting LPCOMP shorts.
*
- * @param[in] lpcomp_short_mask LPCOMP shorts by mask.
- *
+ * @param[in] mask Mask of shortcuts.
*/
-__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t lpcomp_short_mask);
+__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t mask);
/**
* @brief Function for clearing LPCOMP shorts by mask.
*
- * @param[in] lpcomp_short_mask LPCOMP shorts to be cleared.
- *
+ * @param[in] mask Mask of shortcuts.
*/
-__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t lpcomp_short_mask);
+__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t mask);
/**
- * @brief Function for setting a specific LPCOMP task.
- *
- * @param[in] lpcomp_task LPCOMP task to be set.
+ * @brief Function for setting the specified LPCOMP task.
*
+ * @param[in] task LPCOMP task to be set.
*/
-__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t lpcomp_task);
+__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t task);
/**
- * @brief Function for clearing a specific LPCOMP event.
- *
- * @param[in] lpcomp_event LPCOMP event to be cleared.
+ * @brief Function for clearing the specified LPCOMP event.
*
+ * @param[in] event LPCOMP event to be cleared.
*/
-__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t lpcomp_event);
+__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t event);
/**
- * @brief Function for getting the state of a specific LPCOMP event.
+ * @brief Function for retrieving the state of the LPCOMP event.
*
- * @retval true If the specified LPCOMP event is active.
+ * @param[in] event Event to be checked.
*
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t lpcomp_event);
+__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t event);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
@@ -316,7 +294,8 @@ __STATIC_INLINE void nrf_lpcomp_configure(const nrf_lpcomp_config_t * p_config)
if ((p_config->reference & LPCOMP_REFSEL_REFSEL_ARef)==LPCOMP_REFSEL_REFSEL_ARef)
{
uint32_t extref = p_config->reference >> 16;
- NRF_LPCOMP->EXTREFSEL = (extref << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) & LPCOMP_EXTREFSEL_EXTREFSEL_Msk;
+ NRF_LPCOMP->EXTREFSEL = (extref << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) &
+ LPCOMP_EXTREFSEL_EXTREFSEL_Msk;
}
NRF_LPCOMP->ANADETECT =
@@ -358,58 +337,58 @@ __STATIC_INLINE uint32_t nrf_lpcomp_result_get(void)
return (uint32_t)NRF_LPCOMP->RESULT;
}
-__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t lpcomp_int_mask)
+__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t int_mask)
{
- NRF_LPCOMP->INTENSET = lpcomp_int_mask;
+ NRF_LPCOMP->INTENSET = int_mask;
}
-__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t lpcomp_int_mask)
+__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t int_mask)
{
- NRF_LPCOMP->INTENCLR = lpcomp_int_mask;
+ NRF_LPCOMP->INTENCLR = int_mask;
}
-__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t lpcomp_int_mask)
+__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t int_mask)
{
- return (NRF_LPCOMP->INTENSET & lpcomp_int_mask); // when read this register will return the value of INTEN.
+ return (NRF_LPCOMP->INTENSET & int_mask); // when read this register will return the value of INTEN.
}
-__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t lpcomp_task)
+__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t task)
{
- return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_task);
+ return (uint32_t *)((uint8_t *)NRF_LPCOMP + task);
}
-__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t lpcomp_event)
+__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t event)
{
- return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event);
+ return (uint32_t *)((uint8_t *)NRF_LPCOMP + event);
}
-__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t lpcomp_short_mask)
+__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t short_mask)
{
- NRF_LPCOMP->SHORTS |= lpcomp_short_mask;
+ NRF_LPCOMP->SHORTS |= short_mask;
}
-__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t lpcomp_short_mask)
+__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t short_mask)
{
- NRF_LPCOMP->SHORTS &= ~lpcomp_short_mask;
+ NRF_LPCOMP->SHORTS &= ~short_mask;
}
-__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t lpcomp_task)
+__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t task)
{
- *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_task) ) = 1;
+ *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + (uint32_t)task) ) = 1;
}
-__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t lpcomp_event)
+__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t event)
{
- *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event) ) = 0;
+ *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + (uint32_t)event) ) = 0;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_LPCOMP + (uint32_t)event));
(void)dummy;
#endif
}
-__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t lpcomp_event)
+__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t event)
{
- return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event));
+ return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + (uint32_t)event));
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_mwu.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_mwu.h
index 6495468e4..8312269d1 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_mwu.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_mwu.h
@@ -82,57 +82,57 @@ typedef enum
/** @brief MWU region watch masks. */
typedef enum
{
- NRF_MWU_WATCH_REGION0_WRITE = MWU_REGIONEN_RGN0WA_Msk, ///< Region 0 write access watch mask
- NRF_MWU_WATCH_REGION0_READ = MWU_REGIONEN_RGN0RA_Msk, ///< Region 0 read access watch mask
- NRF_MWU_WATCH_REGION1_WRITE = MWU_REGIONEN_RGN1WA_Msk, ///< Region 1 write access watch mask
- NRF_MWU_WATCH_REGION1_READ = MWU_REGIONEN_RGN1RA_Msk, ///< Region 1 read access watch mask
- NRF_MWU_WATCH_REGION2_WRITE = MWU_REGIONEN_RGN2WA_Msk, ///< Region 2 write access watch mask
- NRF_MWU_WATCH_REGION2_READ = MWU_REGIONEN_RGN2RA_Msk, ///< Region 2 read access watch mask
- NRF_MWU_WATCH_REGION3_WRITE = MWU_REGIONEN_RGN3WA_Msk, ///< Region 3 write access watch mask
- NRF_MWU_WATCH_REGION3_READ = MWU_REGIONEN_RGN3RA_Msk, ///< Region 3 read access watch mask
- NRF_MWU_WATCH_PREGION0_WRITE = MWU_REGIONEN_PRGN0WA_Msk, ///< Peripheral region 0 write access watch mask
- NRF_MWU_WATCH_PREGION0_READ = MWU_REGIONEN_PRGN0RA_Msk, ///< Peripheral region 0 read access watch mask
- NRF_MWU_WATCH_PREGION1_WRITE = MWU_REGIONEN_PRGN1WA_Msk, ///< Peripheral region 1 write access watch mask
- NRF_MWU_WATCH_PREGION1_READ = MWU_REGIONEN_PRGN1RA_Msk, ///< Peripheral region 1 read access watch mask
+ NRF_MWU_WATCH_REGION0_WRITE = MWU_REGIONEN_RGN0WA_Msk, ///< Region 0 write access watch mask.
+ NRF_MWU_WATCH_REGION0_READ = MWU_REGIONEN_RGN0RA_Msk, ///< Region 0 read access watch mask.
+ NRF_MWU_WATCH_REGION1_WRITE = MWU_REGIONEN_RGN1WA_Msk, ///< Region 1 write access watch mask.
+ NRF_MWU_WATCH_REGION1_READ = MWU_REGIONEN_RGN1RA_Msk, ///< Region 1 read access watch mask.
+ NRF_MWU_WATCH_REGION2_WRITE = MWU_REGIONEN_RGN2WA_Msk, ///< Region 2 write access watch mask.
+ NRF_MWU_WATCH_REGION2_READ = MWU_REGIONEN_RGN2RA_Msk, ///< Region 2 read access watch mask.
+ NRF_MWU_WATCH_REGION3_WRITE = MWU_REGIONEN_RGN3WA_Msk, ///< Region 3 write access watch mask.
+ NRF_MWU_WATCH_REGION3_READ = MWU_REGIONEN_RGN3RA_Msk, ///< Region 3 read access watch mask.
+ NRF_MWU_WATCH_PREGION0_WRITE = MWU_REGIONEN_PRGN0WA_Msk, ///< Peripheral region 0 write access watch mask.
+ NRF_MWU_WATCH_PREGION0_READ = MWU_REGIONEN_PRGN0RA_Msk, ///< Peripheral region 0 read access watch mask.
+ NRF_MWU_WATCH_PREGION1_WRITE = MWU_REGIONEN_PRGN1WA_Msk, ///< Peripheral region 1 write access watch mask.
+ NRF_MWU_WATCH_PREGION1_READ = MWU_REGIONEN_PRGN1RA_Msk, ///< Peripheral region 1 read access watch mask.
} nrf_mwu_region_watch_t;
/**
- * @brief Function for checking the state of a specific MWU event.
+ * @brief Function for retrieving the state of the MWU event.
*
- * @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] mwu_event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_mwu_event_check(NRF_MWU_Type const * p_reg,
- nrf_mwu_event_t mwu_event);
+ nrf_mwu_event_t event);
/**
* @brief Function for clearing a specific MWU event.
*
- * @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] mwu_event Event to clear.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_mwu_event_clear(NRF_MWU_Type * p_reg,
- nrf_mwu_event_t mwu_event);
+ nrf_mwu_event_t event);
/**
* @brief Function for getting the address of a specific MWU event register.
*
- * @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] mwu_event Requested event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Requested event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_mwu_event_address_get(NRF_MWU_Type const * p_reg,
- nrf_mwu_event_t mwu_event);
+ nrf_mwu_event_t event);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] int_mask Interrupts to enable.
+ * @param[in] int_mask Interrupts to be enabled.
*/
__STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t int_mask);
@@ -140,10 +140,10 @@ __STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t int_mask)
* @brief Function for retrieving the state of a specific interrupt.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] mwu_int Interrupt to check.
+ * @param[in] mwu_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_mwu_int_enable_check(NRF_MWU_Type const * p_reg,
nrf_mwu_int_mask_t mwu_int);
@@ -152,7 +152,7 @@ __STATIC_INLINE bool nrf_mwu_int_enable_check(NRF_MWU_Type const * p_reg,
* @brief Function for disabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] int_mask Interrupts to disable.
+ * @param[in] int_mask Interrupts to be disabled.
*/
__STATIC_INLINE void nrf_mwu_int_disable(NRF_MWU_Type * p_reg, uint32_t int_mask);
@@ -160,7 +160,7 @@ __STATIC_INLINE void nrf_mwu_int_disable(NRF_MWU_Type * p_reg, uint32_t int_mask
* @brief Function for enabling specified non-maskable interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] int_mask Interrupts to enable.
+ * @param[in] int_mask Interrupts to be enabled.
*/
__STATIC_INLINE void nrf_mwu_nmi_enable(NRF_MWU_Type * p_reg, uint32_t int_mask);
@@ -168,10 +168,10 @@ __STATIC_INLINE void nrf_mwu_nmi_enable(NRF_MWU_Type * p_reg, uint32_t int_mask)
* @brief Function for retrieving the state of a specific non-maskable interrupt.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] mwu_int Interrupt to check.
+ * @param[in] mwu_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_mwu_nmi_enable_check(NRF_MWU_Type const * p_reg,
nrf_mwu_int_mask_t mwu_int);
@@ -180,7 +180,7 @@ __STATIC_INLINE bool nrf_mwu_nmi_enable_check(NRF_MWU_Type const * p_reg,
* @brief Function for disabling specified non-maskable interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] int_mask Interrupts to disable.
+ * @param[in] int_mask Interrupts to be disabled.
*/
__STATIC_INLINE void nrf_mwu_nmi_disable(NRF_MWU_Type * p_reg, uint32_t int_mask);
@@ -239,7 +239,7 @@ __STATIC_INLINE void nrf_mwu_subregions_configure(NRF_MWU_Type * p_reg,
* @brief Function for getting the mask of the write access flags of peripheral subregions
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] per_reg_idx Peripheral region containing subregions to check.
+ * @param[in] per_reg_idx Peripheral region containing subregions to be checked.
*
* @return Mask specifying subregions that were write accessed.
*/
@@ -261,7 +261,7 @@ __STATIC_INLINE void nrf_mwu_subregions_write_accesses_clear(NRF_MWU_Type * p_re
* @brief Function for getting the mask of the read access flags of peripheral subregions
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] per_reg_idx Peripheral region containing subregions to check.
+ * @param[in] per_reg_idx Peripheral region containing subregions to be checked.
*
* @return Mask specifying subregions that were read accessed.
*/
@@ -282,25 +282,25 @@ __STATIC_INLINE void nrf_mwu_subregions_read_accesses_clear(NRF_MWU_Type * p_reg
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE bool nrf_mwu_event_check(NRF_MWU_Type const * p_reg,
- nrf_mwu_event_t mwu_event)
+ nrf_mwu_event_t event)
{
- return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)mwu_event);
+ return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE void nrf_mwu_event_clear(NRF_MWU_Type * p_reg,
- nrf_mwu_event_t mwu_event)
+ nrf_mwu_event_t event)
{
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)mwu_event)) = 0;
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)mwu_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
(void)dummy;
#endif
}
__STATIC_INLINE uint32_t nrf_mwu_event_address_get(NRF_MWU_Type const * p_reg,
- nrf_mwu_event_t mwu_event)
+ nrf_mwu_event_t event)
{
- return (uint32_t)((uint8_t *)p_reg + (uint32_t)mwu_event);
+ return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t int_mask)
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_nfct.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_nfct.h
index e6f44db91..278affeaf 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_nfct.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_nfct.h
@@ -49,10 +49,8 @@ extern "C" {
#define NRF_NFCT_CRC_SIZE 2 /**< CRC size in bytes. */
#define NRF_NFCT_DISABLE_ALL_INT 0xFFFFFFFF /**< Value to disable all interrupts. */
-/**
- * @brief NFCT tasks
- */
-typedef enum /*lint -save -e30 */
+/** @brief NFCT tasks. */
+typedef enum
{
NRF_NFCT_TASK_ACTIVATE = offsetof(NRF_NFCT_Type, TASKS_ACTIVATE), /**< Activate the NFCT peripheral for the incoming and outgoing frames, change state to activated. */
NRF_NFCT_TASK_DISABLE = offsetof(NRF_NFCT_Type, TASKS_DISABLE), /**< Disable the NFCT peripheral. */
@@ -61,12 +59,10 @@ typedef enum /*lint -save -e30 */
NRF_NFCT_TASK_ENABLERXDATA = offsetof(NRF_NFCT_Type, TASKS_ENABLERXDATA), /**< Initialize EasyDMA for receive. */
NRF_NFCT_TASK_GOIDLE = offsetof(NRF_NFCT_Type, TASKS_GOIDLE), /**< Force state machine to the IDLE state. */
NRF_NFCT_TASK_GOSLEEP = offsetof(NRF_NFCT_Type, TASKS_GOSLEEP), /**< Force state machine to the SLEEP_A state. */
-} nrf_nfct_task_t; /*lint -restore */
+} nrf_nfct_task_t;
-/**
- * @brief NFCT events
- */
-typedef enum /*lint -save -e30 */
+/** @brief NFCT events. */
+typedef enum
{
NRF_NFCT_EVENT_READY = offsetof(NRF_NFCT_Type, EVENTS_READY), /**< The NFCT peripheral is ready to receive and send frames. */
NRF_NFCT_EVENT_FIELDDETECTED = offsetof(NRF_NFCT_Type, EVENTS_FIELDDETECTED), /**< Remote NFC field is detected. */
@@ -83,11 +79,9 @@ typedef enum /*lint -save -e30 */
NRF_NFCT_EVENT_COLLISION = offsetof(NRF_NFCT_Type, EVENTS_COLLISION), /**< NFC auto collision resolution error reported. */
NRF_NFCT_EVENT_SELECTED = offsetof(NRF_NFCT_Type, EVENTS_SELECTED), /**< NFC auto collision resolution successfully completed. */
NRF_NFCT_EVENT_STARTED = offsetof(NRF_NFCT_Type, EVENTS_STARTED), /**< EasyDMA is ready to receive or send frames. */
-} nrf_nfct_event_t; /*lint -restore */
+} nrf_nfct_event_t;
-/**
- * @brief NFCT shorts
- */
+/** @brief NFCT shortcuts. */
typedef enum
{
NRF_NFCT_SHORT_FIELDDETECTED_ACTIVATE_MASK = NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk, /**< Shortcut between the FIELDDETECTED event and the ACTIVATE task. */
@@ -97,9 +91,7 @@ typedef enum
#endif // defined(NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk) || defined(__NRFX_DOXYGEN__)
} nrf_nfct_short_mask_t;
-/**
- * @brief NFCT interrupts
- */
+/** @brief NFCT interrupts. */
typedef enum
{
NRF_NFCT_INT_READY_MASK = NFCT_INTEN_READY_Msk, /**< Interrupt on READY event. */
@@ -119,9 +111,7 @@ typedef enum
NRF_NFCT_INT_STARTED_MASK = NFCT_INTEN_STARTED_Msk, /**< Interrupt on STARTED event. */
} nrf_nfct_int_mask_t;
-/**
- * @brief NFC error status bit masks.
- */
+/** @brief NFC error status bit masks. */
typedef enum
{
NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK = NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk, /**< Timeout of the Frame Delay Timer (no frame transmission started in the FDT window). */
@@ -133,9 +123,7 @@ typedef enum
#endif // defined(NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk) || defined(__NRFX_DOXYGEN__)
} nrf_nfct_error_status_t;
-/**
- * @brief NFC received frame status bit masks.
- */
+/** @brief NFC received frame status bit masks. */
typedef enum
{
NRF_NFCT_RX_FRAME_STATUS_CRC_MASK = NFCT_FRAMESTATUS_RX_CRCERROR_Msk, /**< CRC status mask. */
@@ -144,9 +132,7 @@ typedef enum
} nrf_nfct_rx_frame_status_t;
#if defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief NFC tag state.
- */
+/** @brief NFC tag state. */
typedef enum
{
NRF_NFCT_TAG_STATE_DISABLED = NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled, /**< Disabled or sensing NFC field. */
@@ -172,18 +158,14 @@ typedef enum
} nrf_nfct_sleep_state_t;
#endif // defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief NFC field state bit masks.
- */
+/** @brief NFC field state bit masks. */
typedef enum
{
NRF_NFCT_FIELD_STATE_PRESENT_MASK = NFCT_FIELDPRESENT_FIELDPRESENT_Msk, /**< Field presence mask. */
NRF_NFCT_FIELD_STATE_LOCK_MASK = NFCT_FIELDPRESENT_LOCKDETECT_Msk /**< Field lock mask. */
} nrf_nfct_field_state_t;
-/**
- * @brief NFC frame delay mode for data transmission.
- */
+/** @brief NFC frame delay mode for data transmission. */
typedef enum
{
NRF_NFCT_FRAME_DELAY_MODE_FREERUN = NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun, /**< Frame transmission starts when @ref NRF_NFCT_TASK_STARTTX is set (delay timer is not used). */
@@ -192,9 +174,7 @@ typedef enum
NRF_NFCT_FRAME_DELAY_MODE_WINDOWGRID = NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid /**< Frame transmission starts in a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX. */
} nrf_nfct_frame_delay_mode_t;
-/**
- * @brief Bit masks for NFC transmission frame configuration.
- */
+/** @brief Bit masks for NFC transmission frame configuration. */
typedef enum
{
NRF_NFCT_TX_FRAME_CONFIG_PARITY = NFCT_TXD_FRAMECONFIG_PARITY_Msk, /**< Indicates whether parity is added in the transmitted frames. */
@@ -203,9 +183,7 @@ typedef enum
NRF_NFCT_TX_FRAME_CONFIG_CRC16 = NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk /**< Indicates whether CRC is added in the transmitted frames. */
} nrf_nfct_tx_frame_config_t;
-/**
- * @brief Bit masks for NFC reception frame configuration.
- */
+/** @brief Bit masks for NFC reception frame configuration. */
typedef enum
{
NRF_NFCT_RX_FRAME_CONFIG_PARITY = NFCT_RXD_FRAMECONFIG_PARITY_Msk, /**< Indicates whether parity is expected in the received frames. */
@@ -214,7 +192,8 @@ typedef enum
} nrf_nfct_rx_frame_config_t;
/**
- * @brief 'NFCI1 size' NFC field configuration for the SENS_RES frame according to the NFC Forum Digital Protocol Technical Specification.
+ * @brief 'NFCI1 size' NFC field configuration for the SENS_RES frame according to the NFC Forum
+ * Digital Protocol Technical Specification.
*/
typedef enum
{
@@ -229,7 +208,8 @@ typedef enum
} nrf_nfct_sensres_nfcid1_size_t;
/**
- * @brief 'Bit frame SDD' NFC field configuration for the SENS_RES frame according to the NFC Forum Digital Protocol Technical Specification.
+ * @brief 'Bit frame SDD' NFC field configuration for the SENS_RES frame according to the NFC
+ * Forum Digital Protocol Technical Specification.
*/
typedef enum
{
@@ -248,7 +228,8 @@ typedef enum
} nrf_nfct_sensres_bit_frame_sdd_t;
/**
- * @brief 'Platofrm Config' NFC field configuration for the SENS_RES frame according to the NFC Forum Digital Protocol Technical Specification.
+ * @brief 'Platofrm Config' NFC field configuration for the SENS_RES frame according to the NFC
+ * Forum Digital Protocol Technical Specification.
*/
typedef enum
{
@@ -258,9 +239,7 @@ typedef enum
NRF_NFCT_SENSRES_PLATFORM_CONFIG_OTHER = 0 << NFCT_SENSRES_PLATFCONFIG_Pos
} nrf_nfct_sensres_platform_config_t;
-/**
- * @brief Bit masks for SEL_RES NFC frame configuration.
- */
+/** @brief Bit masks for SEL_RES NFC frame configuration. */
typedef enum
{
NRF_NFCT_SELRES_CASCADE_MASK = NFCT_SELRES_CASCADE_Msk, /**< SEL_RES Cascade field bit mask. */
@@ -268,7 +247,8 @@ typedef enum
} nrf_nfct_selres_t;
/**
- * @brief Protocol NFC field (bits b7 and b6) configuration for the SEL_RES frame according to the NFC Forum Digital Protocol Technical Specification.
+ * @brief Protocol NFC field (bits b7 and b6) configuration for the SEL_RES frame according to
+ * the NFC Forum Digital Protocol Technical Specification.
*/
typedef enum
{
@@ -281,7 +261,7 @@ typedef enum
/**
* @brief Function for activating a specific NFCT task.
*
- * @param[in] task Task.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_nfct_task_trigger(nrf_nfct_task_t task);
@@ -302,12 +282,12 @@ __STATIC_INLINE uint32_t nrf_nfct_task_address_get(nrf_nfct_task_t task);
__STATIC_INLINE void nrf_nfct_event_clear(nrf_nfct_event_t event);
/**
- * @brief Function for returning the state of a specific event.
+ * @brief Function for retrieving the state of the NFCT event.
*
- * @param[in] event Event.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_nfct_event_check(nrf_nfct_event_t event);
@@ -323,14 +303,14 @@ __STATIC_INLINE uint32_t nrf_nfct_event_address_get(nrf_nfct_event_t event);
/**
* @brief Function for enabling selected shortcuts.
*
- * @param[in] short_mask Shortcut mask.
+ * @param[in] short_mask Mask of shortcuts.
*/
__STATIC_INLINE void nrf_nfct_shorts_enable(uint32_t short_mask);
/**
* @brief Function for disabling selected shortcuts.
*
- * @param[in] short_mask Shortcut mask.
+ * @param[in] short_mask Mask of shortcuts.
*/
__STATIC_INLINE void nrf_nfct_shorts_disable(uint32_t short_mask);
@@ -360,8 +340,8 @@ __STATIC_INLINE void nrf_nfct_int_enable(uint32_t int_mask);
*
* @param[in] int_mask Interrupt mask.
*
- * @retval true If any of the selected interrupts is enabled.
- * @retval false If none of the selected interrupts is enabled.
+ * @retval true Any of the selected interrupts is enabled.
+ * @retval false None of the selected interrupts is enabled.
*/
__STATIC_INLINE bool nrf_nfct_int_enable_check(uint32_t int_mask);
@@ -403,7 +383,8 @@ __STATIC_INLINE uint32_t nrf_nfct_rx_frame_status_get(void);
/**
* @brief Function for clearing the NFC frame reception status.
*
- * @param[in] framestatus_flags Status flags to be cleared, defined in @ref nrf_nfct_rx_frame_status_t.
+ * @param[in] framestatus_flags Status flags to be cleared, defined in
+ * @ref nrf_nfct_rx_frame_status_t.
*/
__STATIC_INLINE void nrf_nfct_rx_frame_status_clear(uint32_t framestatus_flags);
@@ -428,8 +409,10 @@ __STATIC_INLINE nrf_nfct_tag_state_t nrf_nfct_tag_state_get(void);
*
* @details The returned value is the last state before the autimatic collision resolution started.
*
- * @retval NRF_NFCT_SLEEP_STATE_IDLE NFC tag was in IDLE state before the automatic collision resolution started.
- * @retval NRF_NFCT_SLEEP_STATE_SLEEP_A NFC tag was in SLEEP_A state before the automatic collision resolution started.
+ * @retval NRF_NFCT_SLEEP_STATE_IDLE NFC tag was in IDLE state before the automatic
+ * collision resolution started.
+ * @retval NRF_NFCT_SLEEP_STATE_SLEEP_A NFC tag was in SLEEP_A state before the automatic
+ * collision resolution started.
*/
__STATIC_INLINE nrf_nfct_sleep_state_t nrf_nfct_sleep_state_get(void);
#endif // defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__)
@@ -437,7 +420,8 @@ __STATIC_INLINE nrf_nfct_sleep_state_t nrf_nfct_sleep_state_get(void);
/**
* @brief Function for getting the status of the external NFC field detection.
*
- * @return The NFC field detection status. Status bits can be checked by using @ref nrf_nfct_field_state_t.
+ * @return The NFC field detection status. Status bits can be checked by using
+ * @ref nrf_nfct_field_state_t.
*/
__STATIC_INLINE uint8_t nrf_nfct_field_status_get(void);
@@ -445,8 +429,8 @@ __STATIC_INLINE uint8_t nrf_nfct_field_status_get(void);
* @brief Function for getting the minimum Frame Delay Time value.
*
* @details This is the minimum value for Frame Delay Timer. It controls the shortest time between
- * the last symbol of the last received frame and the start of the transmission of a new TX frame.
- *
+ * the last symbol of the last received frame and the start of the transmission of a new
+ * TX frame.
*
* @return The minimum Frame Delay Time value in 13.56-MHz clock ticks.
*/
@@ -456,7 +440,8 @@ __STATIC_INLINE uint16_t nrf_nfct_frame_delay_min_get(void);
* @brief Function for setting the minimum Frame Delay Time value.
*
* @details This is the minimum value for Frame Delay Timer. It controls the shortest time between
- * the last symbol of the last received frame and the start of the transmission of a new TX frame.
+ * the last symbol of the last received frame and the start of the transmission of a new
+ * TX frame.
*
* @param[in] frame_delay_min Minimum Frame Delay Time value in 13.56-MHz clock ticks.
*/
@@ -466,8 +451,8 @@ __STATIC_INLINE void nrf_nfct_frame_delay_min_set(uint16_t frame_delay_min);
* @brief Function for getting the maximum Frame Delay Time value.
*
* @details This is the maximum value for Frame Delay Timer. It controls the longest time between
- * the last symbol of the last received frame and the start of the transmission of a new TX frame.
- * If no transmission starts before the Frame Delay Timer timeout,
+ * the last symbol of the last received frame and the start of the transmission of a new
+ * TX frame. If no transmission starts before the Frame Delay Timer timeout,
* @ref NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK is set.
*
* @return The maximum Frame Delay Time value in 13.56-MHz clock ticks.
@@ -478,8 +463,8 @@ __STATIC_INLINE uint32_t nrf_nfct_frame_delay_max_get(void);
* @brief Function for setting the maximum Frame Delay Time value.
*
* @details This is the maximum value for Frame Delay Timer. It controls the longest time between
- * the last symbol of the last received frame and the start of the transmission of a new TX frame.
- * If no transmission starts before the Frame Delay Timer timeout,
+ * the last symbol of the last received frame and the start of the transmission of a new
+ * TX frame. If no transmission starts before the Frame Delay Timer timeout,
* @ref NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK is set.
*
* @param[in] frame_delay_max Maximum Frame Delay Time value in 13.56-MHz clock ticks.
@@ -513,7 +498,8 @@ __STATIC_INLINE uint8_t * nrf_nfct_rxtx_buffer_get(void);
* @note Buffer for the NFC RX/TX data is used by EasyDMA and must be located in RAM.
*
* @param[in] p_rxtx_buf Pointer to the receive or transmit buffer.
- * @param[in] max_txrx_len Maximum receive or transmit length in bytes (size of the RAM buffer for EasyDMA).
+ * @param[in] max_txrx_len Maximum receive or transmit length in bytes (size of the RAM
+ * buffer for EasyDMA).
*/
__STATIC_INLINE void nrf_nfct_rxtx_buffer_set(uint8_t * p_rxtx_buf,
uint16_t max_txrx_len);
@@ -521,29 +507,32 @@ __STATIC_INLINE void nrf_nfct_rxtx_buffer_set(uint8_t * p_rxtx_buf,
/**
* @brief Function for getting the NFCT RX/TX maximum buffer length.
*
- * @return The configured maximum receive or transmit length in bytes (size of the RX/TX buffer for EasyDMA).
+ * @return The configured maximum receive or transmit length in bytes (size of the RX/TX
+ * buffer for EasyDMA).
*/
__STATIC_INLINE uint16_t nrf_nfct_max_rxtx_length_get(void);
/**
* @brief Function for getting the flags for NFC frame transmission configuration.
*
- * @return The flags of the NFCT frame transmission configuration, defined in @ref nrf_nfct_tx_frame_config_t.
+ * @return The flags of the NFCT frame transmission configuration, defined in
+ * @ref nrf_nfct_tx_frame_config_t.
*/
__STATIC_INLINE uint8_t nrf_nfct_tx_frame_config_get(void);
/**
* @brief Function for setting up the flags of the NFC frame transmission configuration.
*
- * @param[in] flags Flags for NFCT TX configuration. Use @ref nrf_nfct_tx_frame_config_t for setting.
+ * @param[in] flags Flags for NFCT TX configuration. Use @ref nrf_nfct_tx_frame_config_t for
+ * setting.
*/
__STATIC_INLINE void nrf_nfct_tx_frame_config_set(uint8_t flags);
/**
* @brief Function for getting the length of the configured transmission frame.
*
- * @note NFC frames do not have to consist of full bytes only, therefore data amount for transmission
- * is configured in number of bits.
+ * @note NFC frames do not have to consist of full bytes only, therefore data amount
+ * for transmission is configured in number of bits.
*
* @return Number of bits to be sent excluding CRC, parity, SoF, and EoF.
*/
@@ -555,8 +544,8 @@ __STATIC_INLINE uint16_t nrf_nfct_tx_bits_get(void);
* @details Set the number of TX bits excluding CRC, parity, SoF, and EoF.
*
* @note Source of data for transmission is set by using @ref nrf_nfct_rxtx_buffer_set.
- * @note NFC frames do not have to consist of full bytes only, therefore data amount for transmission
- * is configured in number of bits.
+ * @note NFC frames do not have to consist of full bytes only, therefore data amount
+ * for transmission is configured in number of bits.
*
* @param[in] tx_bits Overall number of bits to be sent.
*/
@@ -565,7 +554,8 @@ __STATIC_INLINE void nrf_nfct_tx_bits_set(uint16_t tx_bits);
/**
* @brief Function for getting the flags of the NFC frame reception configuration.
*
- * @return The flags for NFCT frame reception configuration, defined in @ref nrf_nfct_rx_frame_config_t.
+ * @return The flags for NFCT frame reception configuration, defined in
+ * @ref nrf_nfct_rx_frame_config_t.
*/
__STATIC_INLINE uint8_t nrf_nfct_rx_frame_config_get(void);
@@ -584,19 +574,21 @@ __STATIC_INLINE void nrf_nfct_rx_frame_config_set(uint8_t flags);
*
* @param[in] crc_excluded Flag for excluding CRC size from calculation.
*
- * @return Number of received bits including or excluding CRC, and excluding parity and SoF/EoF framing.
+ * @return Number of received bits including or excluding CRC, and excluding parity
+ * and SoF/EoF framing.
*/
__STATIC_INLINE uint16_t nrf_nfct_rx_bits_get(bool crc_excluded);
/**
* @brief Function for getting the NFCID1 (NFC tag identifier).
*
- * @note This function always returns the full configuration of the NFCID1 setting (10 bytes), regardless
- * of the NFCID1 size. The NFCID1 size can be configured using @ref nrf_nfct_sensres_nfcid1_size_set or
- * @ref nrf_nfct_nfcid1_set.
+ * @note This function always returns the full configuration of the NFCID1 setting (10 bytes),
+ * regardless of the NFCID1 size. The NFCID1 size can be configured using
+ * @ref nrf_nfct_sensres_nfcid1_size_set or @ref nrf_nfct_nfcid1_set.
*
- * @param[out] p_nfcid1_buf Pointer to a buffer for the NDFCID1 parameter. The NFCID1 values are in
- * little endian order, that is: |NFCID1_3RD_LAST|NFCID1_2ND_LAST|NFCID1_LAST|.
+ * @param[out] p_nfcid1_buf Pointer to a buffer for the NDFCID1 parameter.
+ * The NFCID1 values are in little endian order,
+ * that is: |NFCID1_3RD_LAST|NFCID1_2ND_LAST|NFCID1_LAST|.
*
* @return Configured NFCID1 length
*/
@@ -605,7 +597,8 @@ __STATIC_INLINE nrf_nfct_sensres_nfcid1_size_t nrf_nfct_nfcid1_get(uint8_t * p_n
/**
* @brief Function for setting the NFCID1 (NFC tag identifier).
*
- * @note This function also configures the NFCIDSIZE field in the SENSRES register of the NRF_NFCT peripheral.
+ * @note This function also configures the NFCIDSIZE field in the SENSRES
+ * register of the NRF_NFCT peripheral.
*
* @param[in] p_nfcid1_buf Pointer to the buffer with NDFCID1 bytes.
* @param[in] nfcid1_size Size of the NFCID1 in bytes.
@@ -1001,7 +994,7 @@ __STATIC_INLINE bool nrf_nfct_autocolres_is_enabled(void)
__STATIC_INLINE void nrf_nfct_autocolres_enable(void)
{
- NRF_NFCT->AUTOCOLRESCONFIG =
+ NRF_NFCT->AUTOCOLRESCONFIG =
(NRF_NFCT->AUTOCOLRESCONFIG & ~NFCT_AUTOCOLRESCONFIG_MODE_Msk) |
(NFCT_AUTOCOLRESCONFIG_MODE_Enabled << NFCT_AUTOCOLRESCONFIG_MODE_Pos);
}
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.h
index 506f35850..3575e5f96 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_nvmc.h
@@ -38,49 +38,42 @@
extern "C" {
#endif
-
/**
- * @defgroup nrf_nvmc_hal NVMC HAL
+ * @defgroup nrf_nvmc_hal_deprecated NVMC HAL (deprecated)
* @{
* @ingroup nrf_nvmc
- * @brief Hardware access layer for managing the Non-Volatile Memory Controller (NVMC) peripheral.
+ * @brief Hardware access layer (HAL) for managing the Non-Volatile Memory Controller (NVMC) peripheral.
*
* This driver allows writing to the non-volatile memory (NVM) regions
- * of the chip. In order to write to NVM the controller must be powered
+ * of the chip. To write to NVM, the controller must be powered
* on and the relevant page must be erased.
- *
*/
-
/**
- * @brief Erase a page in flash. This is required before writing to any
- * address in the page.
+ * @brief Erase a page in flash. This is required before writing to any address in the page.
*
* @param address Start address of the page.
*/
void nrf_nvmc_page_erase(uint32_t address);
-
/**
* @brief Write a single byte to flash.
*
- * The function reads the word containing the byte, and then
- * rewrites the entire word.
+ * The function reads the word containing the byte, and then rewrites the entire word.
*
* @param address Address to write to.
* @param value Value to write.
*/
void nrf_nvmc_write_byte(uint32_t address , uint8_t value);
-
/**
* @brief Write a 32-bit word to flash.
+ *
* @param address Address to write to.
* @param value Value to write.
*/
void nrf_nvmc_write_word(uint32_t address, uint32_t value);
-
/**
* @brief Write consecutive bytes to flash.
*
@@ -90,7 +83,6 @@ void nrf_nvmc_write_word(uint32_t address, uint32_t value);
*/
void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes);
-
/**
* @brief Write consecutive words to flash.
*
@@ -100,6 +92,355 @@ void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_b
*/
void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words);
+/** @} */
+
+/**
+ * @defgroup nrf_nvmc_hal NVMC HAL
+ * @{
+ * @ingroup nrf_nvmc
+ * @brief Hardware access layer (HAL) for managing the Non-Volatile Memory Controller (NVMC) peripheral.
+ */
+
+#if defined(NVMC_ICACHECNF_CACHEEN_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether Instruction Cache (ICache) is present. */
+#define NRF_NVMC_ICACHE_PRESENT
+#endif
+
+#if defined(NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether the option of page partial erase is present. */
+#define NRF_NVMC_PARTIAL_ERASE_PRESENT
+#endif
+
+/** @brief NVMC modes. */
+typedef enum
+{
+ NRF_NVMC_MODE_READONLY = NVMC_CONFIG_WEN_Ren, ///< NVMC in read-only mode.
+ NRF_NVMC_MODE_WRITE = NVMC_CONFIG_WEN_Wen, ///< NVMC in read and write mode.
+ NRF_NVMC_MODE_ERASE = NVMC_CONFIG_WEN_Een, ///< NVMC in read and erase mode.
+#if defined(NVMC_CONFIG_WEN_PEen)
+ NRF_NVMC_MODE_PARTIAL_ERASE = NVMC_CONFIG_WEN_PEen ///< NVMC in read and partial erase mode.
+#endif
+} nrf_nvmc_mode_t;
+
+#if defined(NVMC_CONFIGNS_WEN_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Non-secure NVMC modes. */
+typedef enum
+{
+ NRF_NVMC_NS_MODE_READONLY = NVMC_CONFIGNS_WEN_Ren, ///< Non-secure NVMC in read-only mode.
+ NRF_NVMC_NS_MODE_WRITE = NVMC_CONFIGNS_WEN_Wen, ///< Non-secure NVMC in read and write mode.
+ NRF_NVMC_NS_MODE_ERASE = NVMC_CONFIGNS_WEN_Een, ///< Non-secure NVMC in read and erase mode.
+} nrf_nvmc_ns_mode_t;
+#endif
+
+#if defined(NRF_NVMC_ICACHE_PRESENT)
+/** @brief NVMC ICache configuration. */
+typedef enum
+{
+ NRF_NVMC_ICACHE_DISABLE = NVMC_ICACHECNF_CACHEEN_Disabled, ///< Instruction Cache disabled.
+ NRF_NVMC_ICACHE_ENABLE = NVMC_ICACHECNF_CACHEEN_Enabled, ///< Instruction Cache enabled.
+ NRF_NVMC_ICACHE_ENABLE_WITH_PROFILING = NVMC_ICACHECNF_CACHEEN_Enabled | ///< Instruction Cache with cache profiling enabled.
+ NVMC_ICACHECNF_CACHEPROFEN_Msk
+} nrf_nvmc_icache_config_t;
+#endif // defined(NRF_NVMC_ICACHE_PRESENT)
+
+/**
+ * @brief Function for checking if NVMC is ready to perform write or erase operation.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval true NVMC can perform write or erase.
+ * @retval false NVMC is busy and cannot perform next operation yet.
+ */
+__STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg);
+
+#if defined(NVMC_READYNEXT_READYNEXT_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for checking if NVMC is ready to accept the next write operation.
+ *
+ * NVM writing time can be reduced by using this function.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval true NVMC can accept the next write. It will be buffered and will be taken
+ * into account as soon as the ongoing write operation is completed.
+ * @retval false NVMC is busy and cannot accept the next write yet.
+ */
+__STATIC_INLINE bool nrf_nvmc_write_ready_check(NRF_NVMC_Type const * p_reg);
+#endif // defined(NVMC_READYNEXT_READYNEXT_Msk) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief Function for setting the NVMC mode.
+ *
+ * Only activate erase and write modes when they are actively used.
+ * If Instruction Cache (ICache) is present, enabling write or erase will
+ * invalidate the cache and keep it invalidated.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mode Desired operating mode for NVMC.
+ */
+__STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg,
+ nrf_nvmc_mode_t mode);
+
+#if defined(NVMC_CONFIGNS_WEN_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for setting the NVMC mode for non-secure Flash page operations.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mode Desired operating mode for NVMC.
+ */
+__STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg,
+ nrf_nvmc_ns_mode_t mode);
+#endif
+
+/**
+ * @brief Function for starting a single page erase in the Flash memory.
+ *
+ * The NVMC mode must be correctly configured with @ref nrf_nvmc_mode_set
+ * before starting the erase operation.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] page_addr Address of the first word of the page to erase.
+ */
+__STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg,
+ uint32_t page_addr);
+
+#if defined(NVMC_ERASEUICR_ERASEUICR_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for starting the user information configuration registers (UICR) erase.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ */
+__STATIC_INLINE void nrf_nvmc_uicr_erase_start(NRF_NVMC_Type * p_reg);
+#endif
+
+/**
+ * @brief Function for starting the erase of the whole NVM, including UICR.
+ *
+ * This function purges all user code.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ */
+__STATIC_INLINE void nrf_nvmc_erase_all_start(NRF_NVMC_Type * p_reg);
+
+#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
+/**
+ * @brief Function for configuring the page partial erase duration in milliseconds.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] duration_ms Page partial erase duration in milliseconds.
+ */
+__STATIC_INLINE void nrf_nvmc_partial_erase_duration_set(NRF_NVMC_Type * p_reg,
+ uint32_t duration_ms);
+
+/**
+ * @brief Function for getting the current setting for the page partial erase duration.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval Interval duration setting in milliseconds.
+ */
+__STATIC_INLINE uint32_t nrf_nvmc_partial_erase_duration_get(NRF_NVMC_Type const * p_reg);
+
+/**
+ * @brief Function for starting a partial erase operation.
+ *
+ * It must be called successively until the page erase time is reached.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] page_addr Address of the first word of the page to erase.
+ */
+__STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg,
+ uint32_t page_addr);
+#endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
+
+#if defined(NRF_NVMC_ICACHE_PRESENT)
+/**
+ * @brief Function for applying the Instruction Cache (ICache) configuration.
+ *
+ * Enabling the cache can increase CPU performance and reduce power
+ * consumption by reducing the number of wait cycles and the number
+ * of flash accesses.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] config ICache configuration.
+ */
+__STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg,
+ nrf_nvmc_icache_config_t config);
+
+/**
+ * @brief Function for checking if ICache is enabled.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval true ICache enabled.
+ * @retval false ICache disabled.
+ */
+__STATIC_INLINE bool nrf_nvmc_icache_enable_check(NRF_NVMC_Type const * p_reg);
+
+/**
+ * @brief Function for checking if the ICache profiling option is enabled.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval true ICache profiling enabled.
+ * @retval false ICache profiling disabled.
+ */
+__STATIC_INLINE bool nrf_nvmc_icache_profiling_enable_check(NRF_NVMC_Type const * p_reg);
+
+/**
+ * @brief Function for getting the number of ICache hits.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval Number of the ICache hits.
+ */
+__STATIC_INLINE uint32_t nrf_nvmc_icache_hit_get(NRF_NVMC_Type const * p_reg);
+
+/**
+ * @brief Function for getting the number of ICache misses.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval Number of the ICache misses.
+ */
+__STATIC_INLINE uint32_t nrf_nvmc_icache_miss_get(NRF_NVMC_Type const * p_reg);
+
+/**
+ * @brief Function for resetting the ICache hit and miss counters.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ */
+ __STATIC_INLINE void nrf_nvmc_icache_hit_miss_reset(NRF_NVMC_Type * p_reg);
+#endif // defined(NRF_NVMC_ICACHE_PRESENT)
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg)
+{
+ return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
+}
+
+#if defined(NVMC_READYNEXT_READYNEXT_Msk)
+__STATIC_INLINE bool nrf_nvmc_write_ready_check(NRF_NVMC_Type const * p_reg)
+{
+ return (bool)(p_reg->READYNEXT & NVMC_READYNEXT_READYNEXT_Msk);
+}
+#endif
+
+__STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg,
+ nrf_nvmc_mode_t mode)
+{
+ p_reg->CONFIG = (uint32_t)mode;
+}
+
+#if defined(NVMC_CONFIGNS_WEN_Msk)
+__STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg,
+ nrf_nvmc_ns_mode_t mode)
+{
+ p_reg->CONFIGNS = (uint32_t)mode;
+}
+#endif
+
+__STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg,
+ uint32_t page_addr)
+{
+#if defined(NRF51)
+ /* On nRF51, the code area can be divided into two regions: CR0 and CR1.
+ * The length of CR0 is specified in the CLENR0 register of UICR.
+ * If CLENR0 contains the 0xFFFFFFFF value, CR0 is not set.
+ * Moreover, the page from CR0 can be written or erased only from code
+ * running in CR0.*/
+ uint32_t cr0_len = NRF_UICR->CLENR0 == 0xFFFFFFFF ? 0 : NRF_UICR->CLENR0;
+ if (page_addr < cr0_len)
+ {
+ p_reg->ERASEPCR0 = page_addr;
+ }
+ else
+ {
+ p_reg->ERASEPCR1 = page_addr;
+ }
+#elif defined(NRF52_SERIES)
+ p_reg->ERASEPAGE = page_addr;
+#elif defined(NRF9160_XXAA)
+ *(volatile uint32_t *)page_addr = 0xFFFFFFFF;
+ (void)p_reg;
+#else
+ #error "Unknown device."
+#endif
+}
+
+#if defined(NVMC_ERASEUICR_ERASEUICR_Msk)
+__STATIC_INLINE void nrf_nvmc_uicr_erase_start(NRF_NVMC_Type * p_reg)
+{
+ p_reg->ERASEUICR = 1;
+}
+#endif
+
+__STATIC_INLINE void nrf_nvmc_erase_all_start(NRF_NVMC_Type * p_reg)
+{
+ p_reg->ERASEALL = 1;
+}
+
+#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
+__STATIC_INLINE void nrf_nvmc_partial_erase_duration_set(NRF_NVMC_Type * p_reg,
+ uint32_t duration_ms)
+{
+ p_reg->ERASEPAGEPARTIALCFG = duration_ms;
+}
+
+__STATIC_INLINE uint32_t nrf_nvmc_partial_erase_duration_get(NRF_NVMC_Type const * p_reg)
+{
+ return p_reg->ERASEPAGEPARTIALCFG;
+}
+
+__STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg,
+ uint32_t page_addr)
+{
+#if defined(NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk)
+ p_reg->ERASEPAGEPARTIAL = page_addr;
+#elif defined(NRF9160_XXAA)
+ nrf_nvmc_page_erase_start(p_reg, page_addr);
+#else
+ #error "Unknown device."
+#endif
+}
+#endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
+
+#if defined(NRF_NVMC_ICACHE_PRESENT)
+__STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg,
+ nrf_nvmc_icache_config_t config)
+{
+ p_reg->ICACHECNF = (uint32_t)config;
+}
+
+__STATIC_INLINE bool nrf_nvmc_icache_enable_check(NRF_NVMC_Type const * p_reg)
+{
+ return (bool)(p_reg->ICACHECNF & NVMC_ICACHECNF_CACHEEN_Msk);
+}
+
+__STATIC_INLINE bool nrf_nvmc_icache_profiling_enable_check(NRF_NVMC_Type const * p_reg)
+{
+ return (bool)(p_reg->ICACHECNF & NVMC_ICACHECNF_CACHEPROFEN_Msk);
+}
+
+__STATIC_INLINE uint32_t nrf_nvmc_icache_hit_get(NRF_NVMC_Type const * p_reg)
+{
+ return p_reg->IHIT;
+}
+
+__STATIC_INLINE uint32_t nrf_nvmc_icache_miss_get(NRF_NVMC_Type const * p_reg)
+{
+ return p_reg->IMISS;
+}
+
+__STATIC_INLINE void nrf_nvmc_icache_hit_miss_reset(NRF_NVMC_Type * p_reg)
+{
+ p_reg->IHIT = 0;
+ p_reg->IMISS = 0;
+}
+#endif // defined(NRF_NVMC_ICACHE_PRESENT)
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_pdm.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_pdm.h
index 3e726c06e..63105ad86 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_pdm.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_pdm.h
@@ -44,68 +44,56 @@ extern "C" {
* @brief Hardware access layer for managing the Pulse Density Modulation (PDM) peripheral.
*/
+/** @brief Minimum value of PDM gain. */
#define NRF_PDM_GAIN_MINIMUM 0x00
+/** @brief Default value of PDM gain. */
#define NRF_PDM_GAIN_DEFAULT 0x28
+/** @brief Maximum value of PDM gain. */
#define NRF_PDM_GAIN_MAXIMUM 0x50
+
+/** @brief PDM gain type. */
typedef uint8_t nrf_pdm_gain_t;
-
-/**
- * @brief PDM tasks.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief PDM tasks. */
+typedef enum
{
- NRF_PDM_TASK_START = offsetof(NRF_PDM_Type, TASKS_START), ///< Starts continuous PDM transfer.
- NRF_PDM_TASK_STOP = offsetof(NRF_PDM_Type, TASKS_STOP) ///< Stops PDM transfer.
+ NRF_PDM_TASK_START = offsetof(NRF_PDM_Type, TASKS_START), ///< Starts continuous PDM transfer.
+ NRF_PDM_TASK_STOP = offsetof(NRF_PDM_Type, TASKS_STOP) ///< Stops PDM transfer.
} nrf_pdm_task_t;
-
-/**
- * @brief PDM events.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief PDM events. */
+typedef enum
{
- NRF_PDM_EVENT_STARTED = offsetof(NRF_PDM_Type, EVENTS_STARTED), ///< PDM transfer has started.
- NRF_PDM_EVENT_STOPPED = offsetof(NRF_PDM_Type, EVENTS_STOPPED), ///< PDM transfer has finished.
- NRF_PDM_EVENT_END = offsetof(NRF_PDM_Type, EVENTS_END) ///< The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM.
+ NRF_PDM_EVENT_STARTED = offsetof(NRF_PDM_Type, EVENTS_STARTED), ///< PDM transfer is started.
+ NRF_PDM_EVENT_STOPPED = offsetof(NRF_PDM_Type, EVENTS_STOPPED), ///< PDM transfer is finished.
+ NRF_PDM_EVENT_END = offsetof(NRF_PDM_Type, EVENTS_END) ///< The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM.
} nrf_pdm_event_t;
-
-/**
- * @brief PDM interrupt masks.
- */
+/** @brief PDM interrupt masks. */
typedef enum
{
- NRF_PDM_INT_STARTED = PDM_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
- NRF_PDM_INT_STOPPED = PDM_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
- NRF_PDM_INT_END = PDM_INTENSET_END_Msk ///< Interrupt on EVENTS_END event.
+ NRF_PDM_INT_STARTED = PDM_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
+ NRF_PDM_INT_STOPPED = PDM_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
+ NRF_PDM_INT_END = PDM_INTENSET_END_Msk ///< Interrupt on EVENTS_END event.
} nrf_pdm_int_mask_t;
-/**
- * @brief PDM clock frequency.
- */
+/** @brief PDM clock frequency. */
typedef enum
{
- NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K, ///< PDM_CLK = 1.000 MHz.
- NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default, ///< PDM_CLK = 1.032 MHz.
- NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K ///< PDM_CLK = 1.067 MHz.
+ NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K, ///< PDM_CLK = 1.000 MHz.
+ NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default, ///< PDM_CLK = 1.032 MHz.
+ NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K ///< PDM_CLK = 1.067 MHz.
} nrf_pdm_freq_t;
-
-/**
- * @brief PDM operation mode.
- */
+/** @brief PDM operation mode. */
typedef enum
{
NRF_PDM_MODE_STEREO = PDM_MODE_OPERATION_Stereo, ///< Sample and store one pair (Left + Right) of 16-bit samples per RAM word.
NRF_PDM_MODE_MONO = PDM_MODE_OPERATION_Mono ///< Sample and store two successive Left samples (16 bit each) per RAM word.
} nrf_pdm_mode_t;
-
-/**
- * @brief PDM sampling mode.
- */
+/** @brief PDM sampling mode. */
typedef enum
{
NRF_PDM_EDGE_LEFTFALLING = PDM_MODE_EDGE_LeftFalling, ///< Left (or mono) is sampled on falling edge of PDM_CLK.
@@ -116,67 +104,68 @@ typedef enum
/**
* @brief Function for triggering a PDM task.
*
- * @param[in] pdm_task PDM task.
+ * @param[in] task PDM task.
*/
-__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t pdm_task);
+__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t task);
/**
* @brief Function for getting the address of a PDM task register.
*
- * @param[in] pdm_task PDM task.
+ * @param[in] task PDM task.
*
* @return Address of the specified PDM task.
*/
-__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t pdm_task);
+__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t task);
/**
- * @brief Function for getting the state of a PDM event.
+ * @brief Function for retrieving the state of the PDM event.
*
- * @param[in] pdm_event PDM event.
+ * @param[in] event Event to be checked.
*
- * @return State of the specified PDM event.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t pdm_event);
+__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t event);
/**
* @brief Function for clearing a PDM event.
*
- * @param[in] pdm_event PDM event.
+ * @param[in] event PDM event.
*/
-__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t pdm_event);
+__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t event);
/**
* @brief Function for getting the address of a PDM event register.
*
- * @param[in] pdm_event PDM event.
+ * @param[in] event PDM event.
*
* @return Address of the specified PDM event.
*/
-__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t pdm_event);
+__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t event);
/**
* @brief Function for enabling PDM interrupts.
*
- * @param[in] pdm_int_mask Interrupts to enable.
+ * @param[in] int_mask Mask of interrupts to be enabled.
*/
-__STATIC_INLINE void nrf_pdm_int_enable(uint32_t pdm_int_mask);
+__STATIC_INLINE void nrf_pdm_int_enable(uint32_t int_mask);
/**
* @brief Function for retrieving the state of PDM interrupts.
*
- * @param[in] pdm_int_mask Interrupts to check.
+ * @param[in] int_mask Mask of interrupts to be checked.
*
- * @retval true If all specified interrupts are enabled.
- * @retval false If at least one of the given interrupts is not enabled.
+ * @retval true All specified interrupts are enabled.
+ * @retval false At least one of the given interrupts is not enabled.
*/
-__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t pdm_int_mask);
+__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t int_mask);
/**
* @brief Function for disabling interrupts.
*
- * @param pdm_int_mask Interrupts to disable.
+ * @param[in] int_mask Mask of interrupts to be disabled.
*/
-__STATIC_INLINE void nrf_pdm_int_disable(uint32_t pdm_int_mask);
+__STATIC_INLINE void nrf_pdm_int_disable(uint32_t int_mask);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
@@ -193,7 +182,7 @@ __STATIC_INLINE void nrf_pdm_subscribe_set(nrf_pdm_task_t task,
* @brief Function for clearing the subscribe configuration for a given
* PDM task.
*
- * @param[in] task Task for which to clear the configuration.
+ * @param[in] task Task for which to clear the configuration.
*/
__STATIC_INLINE void nrf_pdm_subscribe_clear(nrf_pdm_task_t task);
@@ -223,16 +212,14 @@ __STATIC_INLINE void nrf_pdm_publish_clear(nrf_pdm_event_t event);
*/
__STATIC_INLINE void nrf_pdm_enable(void);
-/**
- * @brief Function for disabling the PDM peripheral.
- */
+/** @brief Function for disabling the PDM peripheral. */
__STATIC_INLINE void nrf_pdm_disable(void);
/**
* @brief Function for checking if the PDM peripheral is enabled.
*
- * @retval true If the PDM peripheral is enabled.
- * @retval false If the PDM peripheral is not enabled.
+ * @retval true The PDM peripheral is enabled.
+ * @retval false The PDM peripheral is not enabled.
*/
__STATIC_INLINE bool nrf_pdm_enable_check(void);
@@ -261,6 +248,8 @@ __STATIC_INLINE void nrf_pdm_clock_set(nrf_pdm_freq_t pdm_freq);
/**
* @brief Function for getting the PDM clock frequency.
+ *
+ * @return PDM clock frequency.
*/
__STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void);
@@ -272,9 +261,7 @@ __STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void);
*/
__STATIC_INLINE void nrf_pdm_psel_connect(uint32_t psel_clk, uint32_t psel_din);
-/**
- * @brief Function for disconnecting the PDM pins.
- */
+/** @brief Function for disconnecting the PDM pins. */
__STATIC_INLINE void nrf_pdm_psel_disconnect(void);
/**
@@ -296,12 +283,12 @@ __STATIC_INLINE void nrf_pdm_gain_get(nrf_pdm_gain_t * p_gain_l, nrf_pdm_gain_t
/**
* @brief Function for setting the PDM sample buffer.
*
- * @param[in] p_buffer Pointer to the RAM address where samples should be written with EasyDMA.
- * @param[in] num Number of samples to allocate memory for in EasyDMA mode.
- *
* The amount of allocated RAM depends on the operation mode.
* - For stereo mode: N 32-bit words.
* - For mono mode: Ceil(N/2) 32-bit words.
+ *
+ * @param[in] p_buffer Pointer to the RAM address where samples are to be written with EasyDMA.
+ * @param[in] num Number of samples to allocate memory for in EasyDMA mode.
*/
__STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num);
@@ -313,48 +300,48 @@ __STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num);
__STATIC_INLINE uint32_t * nrf_pdm_buffer_get(void);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
-__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t pdm_task)
+__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t task)
{
- *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_task)) = 0x1UL;
+ *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)task)) = 0x1UL;
}
-__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t pdm_task)
+__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t task)
{
- return (uint32_t)((uint8_t *)NRF_PDM + (uint32_t)pdm_task);
+ return (uint32_t)((uint8_t *)NRF_PDM + (uint32_t)task);
}
-__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t pdm_event)
+__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t event)
{
- return (bool)*(volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event);
+ return (bool)*(volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)event);
}
-__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t pdm_event)
+__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t event)
{
- *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event)) = 0x0UL;
+ *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)event)) = 0x0UL;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)event));
(void)dummy;
#endif
}
-__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t pdm_event)
+__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t event)
{
- return (volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event);
+ return (volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)event);
}
-__STATIC_INLINE void nrf_pdm_int_enable(uint32_t pdm_int_mask)
+__STATIC_INLINE void nrf_pdm_int_enable(uint32_t int_mask)
{
- NRF_PDM->INTENSET = pdm_int_mask;
+ NRF_PDM->INTENSET = int_mask;
}
-__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t pdm_int_mask)
+__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t int_mask)
{
- return (bool)(NRF_PDM->INTENSET & pdm_int_mask);
+ return (bool)(NRF_PDM->INTENSET & int_mask);
}
-__STATIC_INLINE void nrf_pdm_int_disable(uint32_t pdm_int_mask)
+__STATIC_INLINE void nrf_pdm_int_disable(uint32_t int_mask)
{
- NRF_PDM->INTENCLR = pdm_int_mask;
+ NRF_PDM->INTENCLR = int_mask;
}
#if defined(DPPI_PRESENT)
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_power.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_power.h
index 9e4d16253..f56626b1a 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_power.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_power.h
@@ -46,78 +46,85 @@ extern "C" {
*/
#if defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__)
-/** @brief Auxiliary definition to mark the fact that sleep events are present */
+/** @brief Symbol indicating whether sleep events are present. */
#define NRF_POWER_HAS_SLEEPEVT 1
#else
#define NRF_POWER_HAS_SLEEPEVT 0
#endif // defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__)
#if defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__)
-/** @brief Auxiliary definition to mark the fact that power module manages USB regulator */
+/** @brief Symbol indicating whether the POWER peripheral controls the USB regulator. */
#define NRF_POWER_HAS_USBREG 1
#else
#define NRF_POWER_HAS_USBREG 0
#endif // defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__)
#if defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
-/** @brief Auxiliary definition to mark the fact that VDDH is present */
+/** @brief Symbol indicating whether VDDH is present. */
#define NRF_POWER_HAS_VDDH 1
#else
#define NRF_POWER_HAS_VDDH 0
#endif // defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
+#if defined(POWER_DCDCEN0_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether DCDCEN for REG0 is present. */
+#define NRF_POWER_HAS_DCDCEN_VDDH 1
+#else
+#define NRF_POWER_HAS_DCDCEN_VDDH 0
+#endif
+
#if defined(POWER_DCDCEN_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
-/** @brief Auxiliary definition to mark the fact that DCDCEN is present */
+/** @brief Symbol indicating whether DCDCEN for REG1 is present. */
#define NRF_POWER_HAS_DCDCEN 1
#else
#define NRF_POWER_HAS_DCDCEN 0
#endif
#if defined(POWER_POFCON_THRESHOLD_Msk) || defined(__NRFX_DOXYGEN__)
-/** @brief Auxiliary definition to mark the fact that POFCON is present */
+/** @brief Symbol indicating whether POFCON is present. */
#define NRF_POWER_HAS_POFCON 1
#else
#define NRF_POWER_HAS_POFCON 0
#endif
/** @brief POWER tasks. */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+typedef enum
{
- NRF_POWER_TASK_CONSTLAT = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), /**< Enable constant latency mode */
- NRF_POWER_TASK_LOWPWR = offsetof(NRF_POWER_Type, TASKS_LOWPWR ), /**< Enable low power mode (variable latency) */
-} nrf_power_task_t; /*lint -restore */
+ NRF_POWER_TASK_CONSTLAT = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), /**< Enable constant latency mode. */
+ NRF_POWER_TASK_LOWPWR = offsetof(NRF_POWER_Type, TASKS_LOWPWR ), /**< Enable low-power mode (variable latency). */
+} nrf_power_task_t;
/** @brief POWER events. */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+typedef enum
{
#if NRF_POWER_HAS_POFCON
- NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN ), /**< Power failure warning */
+ NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN ), /**< Power failure warning. */
#endif
#if NRF_POWER_HAS_SLEEPEVT
- NRF_POWER_EVENT_SLEEPENTER = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER ), /**< CPU entered WFI/WFE sleep */
- NRF_POWER_EVENT_SLEEPEXIT = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT ), /**< CPU exited WFI/WFE sleep */
+ NRF_POWER_EVENT_SLEEPENTER = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER ), /**< CPU entered WFI/WFE sleep. */
+ NRF_POWER_EVENT_SLEEPEXIT = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT ), /**< CPU exited WFI/WFE sleep. */
#endif
#if NRF_POWER_HAS_USBREG
- NRF_POWER_EVENT_USBDETECTED = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), /**< Voltage supply detected on VBUS */
- NRF_POWER_EVENT_USBREMOVED = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED ), /**< Voltage supply removed from VBUS */
- NRF_POWER_EVENT_USBPWRRDY = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY ), /**< USB 3.3 V supply ready */
+ NRF_POWER_EVENT_USBDETECTED = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), /**< Voltage supply detected on VBUS. */
+ NRF_POWER_EVENT_USBREMOVED = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED ), /**< Voltage supply removed from VBUS. */
+ NRF_POWER_EVENT_USBPWRRDY = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY ), /**< USB 3.3 V supply ready. */
#endif
-} nrf_power_event_t; /*lint -restore */
+} nrf_power_event_t;
/** @brief POWER interrupts. */
typedef enum
{
#if NRF_POWER_HAS_POFCON
- NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk , /**< Write '1' to Enable interrupt for POFWARN event */
+ NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk , /**< Write '1' to Enable interrupt for POFWARN event. */
#endif
#if NRF_POWER_HAS_SLEEPEVT
- NRF_POWER_INT_SLEEPENTER_MASK = POWER_INTENSET_SLEEPENTER_Msk , /**< Write '1' to Enable interrupt for SLEEPENTER event */
- NRF_POWER_INT_SLEEPEXIT_MASK = POWER_INTENSET_SLEEPEXIT_Msk , /**< Write '1' to Enable interrupt for SLEEPEXIT event */
+ NRF_POWER_INT_SLEEPENTER_MASK = POWER_INTENSET_SLEEPENTER_Msk , /**< Write '1' to Enable interrupt for SLEEPENTER event. */
+ NRF_POWER_INT_SLEEPEXIT_MASK = POWER_INTENSET_SLEEPEXIT_Msk , /**< Write '1' to Enable interrupt for SLEEPEXIT event. */
#endif
#if NRF_POWER_HAS_USBREG
- NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, /**< Write '1' to Enable interrupt for USBDETECTED event */
- NRF_POWER_INT_USBREMOVED_MASK = POWER_INTENSET_USBREMOVED_Msk , /**< Write '1' to Enable interrupt for USBREMOVED event */
- NRF_POWER_INT_USBPWRRDY_MASK = POWER_INTENSET_USBPWRRDY_Msk , /**< Write '1' to Enable interrupt for USBPWRRDY event */
+ NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, /**< Write '1' to Enable interrupt for USBDETECTED event. */
+ NRF_POWER_INT_USBREMOVED_MASK = POWER_INTENSET_USBREMOVED_Msk , /**< Write '1' to Enable interrupt for USBREMOVED event. */
+ NRF_POWER_INT_USBPWRRDY_MASK = POWER_INTENSET_USBPWRRDY_Msk , /**< Write '1' to Enable interrupt for USBPWRRDY event. */
#endif
} nrf_power_int_mask_t;
@@ -149,22 +156,21 @@ typedef enum
*/
typedef enum
{
- NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, /**< USB detected or removed */
- NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK = POWER_USBREGSTATUS_OUTPUTRDY_Msk /**< USB 3.3 V supply ready */
+ NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, /**< USB detected or removed. */
+ NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK = POWER_USBREGSTATUS_OUTPUTRDY_Msk /**< USB 3.3 V supply ready. */
} nrf_power_usbregstatus_mask_t;
#endif // NRF_POWER_HAS_USBREG
#if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
/**
- * @brief RAM blocks numbers
+ * @brief Numbers of RAM blocks
*
* @sa nrf_power_ramblock_mask_t
* @note
- * Ram blocks has to been used in nrf51.
- * In new CPU ram is divided into segments and this functionality is depreciated.
- * For the newer MCU see the PS for mapping between internal RAM and RAM blocks,
- * because this mapping is not 1:1, and functions related to old style blocks
- * should not be used.
+ * RAM blocks must be used in nRF51.
+ * In newer SoCs, RAM is divided into segments and this functionality is not supported.
+ * See the PS for mapping between the internal RAM and RAM blocks, because this
+ * mapping is not 1:1, and functions related to old style blocks must not be used.
*/
typedef enum
{
@@ -175,7 +181,7 @@ typedef enum
} nrf_power_ramblock_t;
/**
- * @brief RAM blocks masks
+ * @brief Masks of RAM blocks.
*
* @sa nrf_power_ramblock_t
*/
@@ -195,15 +201,15 @@ typedef enum
*/
typedef enum
{
- NRF_POWER_ONRAM0, /**< Keep RAM block 0 on or off in system ON Mode */
- NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched off */
- NRF_POWER_ONRAM1, /**< Keep RAM block 1 on or off in system ON Mode */
- NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched off */
- NRF_POWER_ONRAM2, /**< Keep RAM block 2 on or off in system ON Mode */
- NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched off */
- NRF_POWER_ONRAM3, /**< Keep RAM block 3 on or off in system ON Mode */
- NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched off */
-} nrf_power_onoffram_t;
+ NRF_POWER_ONRAM0, /**< Keep RAM block 0 ON or OFF in System ON mode. */
+ NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched OFF. */
+ NRF_POWER_ONRAM1, /**< Keep RAM block 1 ON or OFF in System ON mode. */
+ NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched OFF. */
+ NRF_POWER_ONRAM2, /**< Keep RAM block 2 ON or OFF in System ON mode. */
+ NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched OFF. */
+ NRF_POWER_ONRAM3, /**< Keep RAM block 3 ON or OFF in System ON mode. */
+ NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched OFF. */
+}nrf_power_onoffram_t;
/**
* @brief RAM power state bit masks
@@ -212,33 +218,33 @@ typedef enum
*/
typedef enum
{
- NRF_POWER_ONRAM0_MASK = 1U << NRF_POWER_ONRAM0, /**< Keep RAM block 0 on or off in system ON Mode */
- NRF_POWER_OFFRAM0_MASK = 1U << NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched off */
- NRF_POWER_ONRAM1_MASK = 1U << NRF_POWER_ONRAM1, /**< Keep RAM block 1 on or off in system ON Mode */
- NRF_POWER_OFFRAM1_MASK = 1U << NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched off */
- NRF_POWER_ONRAM2_MASK = 1U << NRF_POWER_ONRAM2, /**< Keep RAM block 2 on or off in system ON Mode */
- NRF_POWER_OFFRAM2_MASK = 1U << NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched off */
- NRF_POWER_ONRAM3_MASK = 1U << NRF_POWER_ONRAM3, /**< Keep RAM block 3 on or off in system ON Mode */
- NRF_POWER_OFFRAM3_MASK = 1U << NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched off */
-} nrf_power_onoffram_mask_t;
+ NRF_POWER_ONRAM0_MASK = 1U << NRF_POWER_ONRAM0, /**< Keep RAM block 0 ON or OFF in System ON mode. */
+ NRF_POWER_OFFRAM0_MASK = 1U << NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched OFF. */
+ NRF_POWER_ONRAM1_MASK = 1U << NRF_POWER_ONRAM1, /**< Keep RAM block 1 ON or OFF in System ON mode. */
+ NRF_POWER_OFFRAM1_MASK = 1U << NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched OFF. */
+ NRF_POWER_ONRAM2_MASK = 1U << NRF_POWER_ONRAM2, /**< Keep RAM block 2 ON or OFF in System ON mode. */
+ NRF_POWER_OFFRAM2_MASK = 1U << NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched OFF. */
+ NRF_POWER_ONRAM3_MASK = 1U << NRF_POWER_ONRAM3, /**< Keep RAM block 3 ON or OFF in System ON mode. */
+ NRF_POWER_OFFRAM3_MASK = 1U << NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched OFF. */
+}nrf_power_onoffram_mask_t;
#if NRF_POWER_HAS_POFCON
/** @brief Power failure comparator thresholds. */
typedef enum
{
- NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, /**< Set threshold to 2.1 V */
- NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, /**< Set threshold to 2.3 V */
- NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, /**< Set threshold to 2.5 V */
- NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, /**< Set threshold to 2.7 V */
+ NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, /**< Set threshold to 2.1 V. */
+ NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, /**< Set threshold to 2.3 V. */
+ NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, /**< Set threshold to 2.5 V. */
+ NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, /**< Set threshold to 2.7 V. */
#if defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__)
- NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, /**< Set threshold to 1.7 V */
- NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, /**< Set threshold to 1.8 V */
- NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, /**< Set threshold to 1.9 V */
- NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, /**< Set threshold to 2.0 V */
- NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, /**< Set threshold to 2.2 V */
- NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, /**< Set threshold to 2.4 V */
- NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, /**< Set threshold to 2.6 V */
- NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, /**< Set threshold to 2.8 V */
+ NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, /**< Set threshold to 1.7 V. */
+ NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, /**< Set threshold to 1.8 V. */
+ NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, /**< Set threshold to 1.9 V. */
+ NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, /**< Set threshold to 2.0 V. */
+ NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, /**< Set threshold to 2.2 V. */
+ NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, /**< Set threshold to 2.4 V. */
+ NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, /**< Set threshold to 2.6 V. */
+ NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, /**< Set threshold to 2.8 V. */
#endif // defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__)
} nrf_power_pof_thr_t;
#endif // NRF_POWER_HAS_POFCON
@@ -247,22 +253,22 @@ typedef enum
/** @brief Power failure comparator thresholds for VDDH. */
typedef enum
{
- NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, /**< Set threshold to 2.7 V */
- NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, /**< Set threshold to 2.8 V */
- NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, /**< Set threshold to 2.9 V */
- NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, /**< Set threshold to 3.0 V */
- NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, /**< Set threshold to 3.1 V */
- NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, /**< Set threshold to 3.2 V */
- NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, /**< Set threshold to 3.3 V */
- NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, /**< Set threshold to 3.4 V */
- NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, /**< Set threshold to 3.5 V */
- NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, /**< Set threshold to 3.6 V */
- NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, /**< Set threshold to 3.7 V */
- NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, /**< Set threshold to 3.8 V */
- NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, /**< Set threshold to 3.9 V */
- NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, /**< Set threshold to 4.0 V */
- NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1 V */
- NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2 V */
+ NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, /**< Set threshold to 2.7 V. */
+ NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, /**< Set threshold to 2.8 V. */
+ NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, /**< Set threshold to 2.9 V. */
+ NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, /**< Set threshold to 3.0 V. */
+ NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, /**< Set threshold to 3.1 V. */
+ NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, /**< Set threshold to 3.2 V. */
+ NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, /**< Set threshold to 3.3 V. */
+ NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, /**< Set threshold to 3.4 V. */
+ NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, /**< Set threshold to 3.5 V. */
+ NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, /**< Set threshold to 3.6 V. */
+ NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, /**< Set threshold to 3.7 V. */
+ NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, /**< Set threshold to 3.8 V. */
+ NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, /**< Set threshold to 3.9 V. */
+ NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, /**< Set threshold to 4.0 V. */
+ NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1 V. */
+ NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2 V. */
} nrf_power_pof_thrvddh_t;
/** @brief Main regulator status. */
@@ -284,39 +290,39 @@ typedef enum
{
/** Keep RAM section S0 ON in System ON mode */
NRF_POWER_RAMPOWER_S0POWER = POWER_RAM_POWER_S0POWER_Pos,
- NRF_POWER_RAMPOWER_S1POWER, /**< Keep RAM section S1 ON in System ON mode */
- NRF_POWER_RAMPOWER_S2POWER, /**< Keep RAM section S2 ON in System ON mode */
- NRF_POWER_RAMPOWER_S3POWER, /**< Keep RAM section S3 ON in System ON mode */
- NRF_POWER_RAMPOWER_S4POWER, /**< Keep RAM section S4 ON in System ON mode */
- NRF_POWER_RAMPOWER_S5POWER, /**< Keep RAM section S5 ON in System ON mode */
- NRF_POWER_RAMPOWER_S6POWER, /**< Keep RAM section S6 ON in System ON mode */
- NRF_POWER_RAMPOWER_S7POWER, /**< Keep RAM section S7 ON in System ON mode */
- NRF_POWER_RAMPOWER_S8POWER, /**< Keep RAM section S8 ON in System ON mode */
- NRF_POWER_RAMPOWER_S9POWER, /**< Keep RAM section S9 ON in System ON mode */
- NRF_POWER_RAMPOWER_S10POWER, /**< Keep RAM section S10 ON in System ON mode */
- NRF_POWER_RAMPOWER_S11POWER, /**< Keep RAM section S11 ON in System ON mode */
- NRF_POWER_RAMPOWER_S12POWER, /**< Keep RAM section S12 ON in System ON mode */
- NRF_POWER_RAMPOWER_S13POWER, /**< Keep RAM section S13 ON in System ON mode */
- NRF_POWER_RAMPOWER_S14POWER, /**< Keep RAM section S14 ON in System ON mode */
- NRF_POWER_RAMPOWER_S15POWER, /**< Keep RAM section S15 ON in System ON mode */
+ NRF_POWER_RAMPOWER_S1POWER, /**< Keep RAM section S1 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S2POWER, /**< Keep RAM section S2 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S3POWER, /**< Keep RAM section S3 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S4POWER, /**< Keep RAM section S4 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S5POWER, /**< Keep RAM section S5 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S6POWER, /**< Keep RAM section S6 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S7POWER, /**< Keep RAM section S7 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S8POWER, /**< Keep RAM section S8 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S9POWER, /**< Keep RAM section S9 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S10POWER, /**< Keep RAM section S10 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S11POWER, /**< Keep RAM section S11 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S12POWER, /**< Keep RAM section S12 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S13POWER, /**< Keep RAM section S13 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S14POWER, /**< Keep RAM section S14 ON in System ON mode. */
+ NRF_POWER_RAMPOWER_S15POWER, /**< Keep RAM section S15 ON in System ON mode. */
/** Keep section retention in OFF mode when section is OFF */
NRF_POWER_RAMPOWER_S0RETENTION = POWER_RAM_POWER_S0RETENTION_Pos,
- NRF_POWER_RAMPOWER_S1RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S2RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S3RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S4RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S5RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S6RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S7RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S8RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S9RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S10RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S11RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S12RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S13RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S14RETENTION, /**< Keep section retention in OFF mode when section is OFF */
- NRF_POWER_RAMPOWER_S15RETENTION, /**< Keep section retention in OFF mode when section is OFF */
+ NRF_POWER_RAMPOWER_S1RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S2RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S3RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S4RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S5RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S6RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S7RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S8RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S9RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S10RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S11RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S12RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S13RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S14RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
+ NRF_POWER_RAMPOWER_S15RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
} nrf_power_rampower_t;
/**
@@ -384,12 +390,12 @@ __STATIC_INLINE uint32_t nrf_power_task_address_get(nrf_power_task_t task);
__STATIC_INLINE void nrf_power_event_clear(nrf_power_event_t event);
/**
- * @brief Function for returning the state of a specific event.
+ * @brief Function for retrieving the state of the POWER event.
*
- * @param[in] event Event.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_power_event_check(nrf_power_event_t event);
@@ -400,8 +406,8 @@ __STATIC_INLINE bool nrf_power_event_check(nrf_power_event_t event);
*
* @param[in] event Event.
*
- * @retval true If the event was set.
- * @retval false If the event was not set.
+ * @retval true The event was set.
+ * @retval false The event was not set.
*/
__STATIC_INLINE bool nrf_power_event_get_and_clear(nrf_power_event_t event);
@@ -426,8 +432,8 @@ __STATIC_INLINE void nrf_power_int_enable(uint32_t int_mask);
*
* @param[in] int_mask Interrupts mask.
*
- * @retval true If any of selected interrupts is enabled.
- * @retval false If none of selected interrupts is enabled.
+ * @retval true Any of selected interrupts is enabled.
+ * @retval false None of selected interrupts is enabled.
*/
__STATIC_INLINE bool nrf_power_int_enable_check(uint32_t int_mask);
@@ -484,13 +490,13 @@ __STATIC_INLINE void nrf_power_publish_clear(nrf_power_event_t event);
#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
- * @brief Get reset reason mask
+ * @brief Function for getting the reset reason bitmask.
*
- * Function returns the reset reason.
+ * This function returns the reset reason bitmask.
* Unless cleared, the RESETREAS register is cumulative.
* A field is cleared by writing '1' to it (see @ref nrf_power_resetreas_clear).
- * If none of the reset sources are flagged,
- * this indicates that the chip was reset from the on-chip reset generator,
+ * If none of the reset sources is flagged,
+ * the chip was reset from the on-chip reset generator,
* which indicates a power-on-reset or a brown out reset.
*
* @return The mask of reset reasons constructed with @ref nrf_power_resetreas_mask_t.
@@ -498,9 +504,9 @@ __STATIC_INLINE void nrf_power_publish_clear(nrf_power_event_t event);
__STATIC_INLINE uint32_t nrf_power_resetreas_get(void);
/**
- * @brief Clear selected reset reason field
+ * @brief Function for clearing the selected reset reason field.
*
- * Function clears selected reset reason fields.
+ * This function clears the selected reset reason field.
*
* @param[in] mask The mask constructed from @ref nrf_power_resetreas_mask_t enumerator values.
* @sa nrf_power_resetreas_get
@@ -511,28 +517,26 @@ __STATIC_INLINE void nrf_power_resetreas_clear(uint32_t mask);
/**
* @brief Function for getting power status of the LTE Modem domain.
*
- * @retval true If the LTE Modem domain is powered on.
- * @retval false If the LTE Modem domain is powered off.
+ * @retval true The LTE Modem domain is powered on.
+ * @retval false The LTE Modem domain is powered off.
*/
__STATIC_INLINE bool nrf_power_powerstatus_get(void);
#endif
#if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
/**
- * @brief Get RAMSTATUS register
+ * @brief Function for getting the RAMSTATUS register.
*
- * Returns the masks of RAM blocks that are powered ON.
- *
- * @return Value with bits sets according to masks in @ref nrf_power_ramblock_mask_t.
+ * @return Value with bits set according to the masks in @ref nrf_power_ramblock_mask_t.
*/
__STATIC_INLINE uint32_t nrf_power_ramstatus_get(void);
#endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
#if defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
/**
- * @brief Go to system OFF
+ * @brief Function for going into System OFF mode.
*
- * This function puts the CPU into system off mode.
+ * This function puts the CPU in System OFF mode.
* The only way to wake up the CPU is by reset.
*
* @note This function never returns.
@@ -542,80 +546,78 @@ __STATIC_INLINE void nrf_power_system_off(void);
#if NRF_POWER_HAS_POFCON
/**
- * @brief Set power failure comparator configuration
- *
- * Sets power failure comparator threshold and enable/disable flag.
- *
- * @param[in] enabled Set to true if power failure comparator should be enabled.
- * @param[in] thr Set the voltage threshold value.
+ * @brief Function for setting the power failure comparator configuration.
*
+ * This function sets the power failure comparator threshold and enables or disables flag.
* @note
- * If VDDH settings is present in the device, this function would
- * clear it settings (set to the lowest voltage).
+ * If VDDH settings are present in the device, this function will
+ * clear its settings (set to the lowest voltage).
* Use @ref nrf_power_pofcon_vddh_set function to set new value.
+ *
+ * @param enabled Sets to true if power failure comparator is to be enabled.
+ * @param thr Sets the voltage threshold value.
+ *
*/
__STATIC_INLINE void nrf_power_pofcon_set(bool enabled, nrf_power_pof_thr_t thr);
/**
- * @brief Get power failure comparator configuration
+ * @brief Function for getting the power failure comparator configuration.
*
- * Get power failure comparator threshold and enable bit.
- *
- * @param[out] p_enabled Function would set this boolean variable to true
+ * @param[out] p_enabled Function sets this boolean variable to true
* if power failure comparator is enabled.
* The pointer can be NULL if we do not need this information.
*
- * @return Threshold setting for power failure comparator
+ * @return Threshold setting for power failure comparator.
*/
__STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(bool * p_enabled);
#endif // NRF_POWER_HAS_POFCON
#if NRF_POWER_HAS_VDDH
/**
- * @brief Set VDDH power failure comparator threshold
+ * @brief Function for setting the VDDH power failure comparator threshold.
*
- * @param[in] thr Threshold to be set
+ * @param thr Threshold to be set.
*/
__STATIC_INLINE void nrf_power_pofcon_vddh_set(nrf_power_pof_thrvddh_t thr);
/**
- * @brief Get VDDH power failure comparator threshold
+ * @brief Function for getting the VDDH power failure comparator threshold.
*
- * @return VDDH threshold currently configured
+ * @return VDDH threshold currently configured.
*/
__STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(void);
#endif // NRF_POWER_HAS_VDDH
/**
- * @brief Set general purpose retention register
+ * @brief Function for setting the general purpose retention register.
*
- * @param[in] val Value to be set in the register
+ * @param[in] val Value to be set in the register.
*/
__STATIC_INLINE void nrf_power_gpregret_set(uint8_t val);
/**
- * @brief Get general purpose retention register
+ * @brief Function for getting general purpose retention register.
*
- * @return The value from the register
+ * @return The value from the register.
*/
__STATIC_INLINE uint8_t nrf_power_gpregret_get(void);
#if defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__)
/**
- * @brief Set general purpose retention register 2
+ * @brief Function for setting the general purpose retention register 2.
*
- * @note This register is not available in nrf51 MCU family
+ * @note This register is not available in the nRF51 MCU family.
*
- * @param[in] val Value to be set in the register
+ * @param[in] val Value to be set in the register.
*/
__STATIC_INLINE void nrf_power_gpregret2_set(uint8_t val);
/**
- * @brief Get general purpose retention register 2
+ * @brief Function for getting the general purpose retention register 2.
*
* @note This register is not available in all MCUs.
*
- * @return The value from the register
+ * @return The value from the register.
*/
__STATIC_INLINE uint8_t nrf_power_gpregret2_get(void);
#endif // defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__)
@@ -643,31 +645,31 @@ __STATIC_INLINE void nrf_power_gpregret_ext_set(uint8_t reg_num,
* @brief Enable or disable DCDC converter
*
* @note
- * If the device consist of high voltage power input (VDDH) this setting
- * would relate to the converter on low voltage side (1.3 V output).
+ * If the device consist of high voltage power input (VDDH), this setting
+ * will relate to the converter on low voltage side (1.3 V output).
*
- * @param[in] enable Set true to enable or false to disable DCDC converter.
+ * @param[in] enable Set true to enable the DCDC converter or false to disable the DCDC converter.
*/
__STATIC_INLINE void nrf_power_dcdcen_set(bool enable);
/**
- * @brief Get the state of DCDC converter
+ * @brief Function for getting the state of the DCDC converter.
*
* @note
- * If the device consist of high voltage power input (VDDH) this setting
- * would relate to the converter on low voltage side (1.3 V output).
+ * If the device consist of high voltage power input (VDDH), this setting
+ * will relate to the converter on low voltage side (1.3 V output).
*
- * @retval true Converter is enabled
- * @retval false Converter is disabled
+ * @retval true Converter is enabled.
+ * @retval false Converter is disabled.
*/
__STATIC_INLINE bool nrf_power_dcdcen_get(void);
#endif // NRF_POWER_HAS_DCDCEN
#if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
/**
- * @brief Turn ON sections in selected RAM block.
+ * @brief Turn ON sections in the selected RAM block.
*
- * This function turns ON sections in block and also block retention.
+ * This function turns ON several sections in one block and also block retention.
*
* @sa nrf_power_rampower_mask_t
* @sa nrf_power_rampower_mask_off
@@ -679,9 +681,9 @@ __STATIC_INLINE bool nrf_power_dcdcen_get(void);
__STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_mask);
/**
- * @brief Turn ON sections in selected RAM block.
+ * @brief Turn ON sections in the selected RAM block.
*
- * This function turns OFF sections in block and also block retention.
+ * This function turns OFF several sections in one block and also block retention.
*
* @sa nrf_power_rampower_mask_t
* @sa nrf_power_rampower_mask_off
@@ -693,7 +695,7 @@ __STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_
__STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section_mask);
/**
- * @brief Get the mask of ON and retention sections in selected RAM block.
+ * @brief Function for getting the ON mask and retention sections in the selected RAM block.
*
* @param[in] block RAM block index.
*
@@ -702,33 +704,35 @@ __STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section
__STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block);
#endif /* defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__) */
-#if NRF_POWER_HAS_VDDH
+#if NRF_POWER_HAS_DCDCEN_VDDH
/**
- * @brief Enable of disable DCDC converter on VDDH
+ * @brief Function for enabling or disabling the DCDC converter on VDDH.
*
- * @param[in] enable Set true to enable or false to disable DCDC converter.
+ * @param enable Set true to enable the DCDC converter or false to disable the DCDC converter.
*/
__STATIC_INLINE void nrf_power_dcdcen_vddh_set(bool enable);
/**
- * @brief Get the state of DCDC converter on VDDH
+ * @brief Function for getting the state of DCDC converter on VDDH.
*
- * @retval true Converter is enabled
- * @retval false Converter is disabled
+ * @retval true Converter is enabled.
+ * @retval false Converter is disabled.
*/
__STATIC_INLINE bool nrf_power_dcdcen_vddh_get(void);
+#endif // NRF_POWER_HAS_DCDCEN_VDDH
+#if NRF_POWER_HAS_VDDH
/**
- * @brief Get main supply status
+ * @brief Function for getting the main supply status.
*
- * @return Current main supply status
+ * @return The current main supply status.
*/
__STATIC_INLINE nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void);
#endif // NRF_POWER_HAS_VDDH
#if NRF_POWER_HAS_USBREG
/**
- * @brief Get the whole USBREGSTATUS register
+ * @brief Function for getting the whole USBREGSTATUS register.
*
* @return The USBREGSTATUS register value.
* Use @ref nrf_power_usbregstatus_mask_t values for bit masking.
@@ -739,23 +743,23 @@ __STATIC_INLINE nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void);
__STATIC_INLINE uint32_t nrf_power_usbregstatus_get(void);
/**
- * @brief VBUS input detection status
+ * @brief Function for getting the VBUS input detection status.
*
* USBDETECTED and USBREMOVED events are derived from this information
*
- * @retval false VBUS voltage below valid threshold
- * @retval true VBUS voltage above valid threshold
+ * @retval false VBUS voltage below valid threshold.
+ * @retval true VBUS voltage above valid threshold.
*
* @sa nrf_power_usbregstatus_get
*/
__STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(void);
/**
- * @brief USB supply output settling time elapsed
+ * @brief Function for getting the state of the elapsed time for the USB supply output settling.
*
- * @retval false USBREG output settling time not elapsed
+ * @retval false USBREG output settling time not elapsed.
* @retval true USBREG output settling time elapsed
- * (same information as USBPWRRDY event)
+ * (same information as USBPWRRDY event).
*
* @sa nrf_power_usbregstatus_get
*/
@@ -1035,7 +1039,7 @@ __STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block)
}
#endif /* defined(POWER_RAM_POWER_S0POWER_Msk) */
-#if NRF_POWER_HAS_VDDH
+#if NRF_POWER_HAS_DCDCEN_VDDH
__STATIC_INLINE void nrf_power_dcdcen_vddh_set(bool enable)
{
NRF_POWER->DCDCEN0 = (enable ?
@@ -1049,7 +1053,9 @@ __STATIC_INLINE bool nrf_power_dcdcen_vddh_get(void)
==
(POWER_DCDCEN0_DCDCEN_Enabled << POWER_DCDCEN0_DCDCEN_Pos);
}
+#endif // NRF_POWER_HAS_DCDCEN_VDDH
+#if NRF_POWER_HAS_VDDH
__STATIC_INLINE nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void)
{
return (nrf_power_mainregstatus_t)(((NRF_POWER->MAINREGSTATUS) &
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_ppi.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_ppi.h
index c87c7edac..16a52bf81 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_ppi.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_ppi.h
@@ -42,16 +42,11 @@ extern "C" {
* @defgroup nrf_ppi_hal PPI HAL
* @{
* @ingroup nrf_ppi
- * @brief Hardware access layer for managing the Programmable Peripheral Interconnect (PPI)
+ * @brief Hardware access layer (HAL) for managing the Programmable Peripheral Interconnect (PPI)
* channels.
*/
-#define NRF_PPI_TASK_SET (1UL)
-
-/**
- * @enum nrf_ppi_channel_t
- * @brief PPI channels.
- */
+/** @brief PPI channels. */
typedef enum
{
NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */
@@ -90,10 +85,7 @@ typedef enum
NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos /**< Channel 31. */
} nrf_ppi_channel_t;
-/**
- * @enum nrf_ppi_channel_group_t
- * @brief PPI channel groups.
- */
+/** @brief PPI channel groups. */
typedef enum
{
NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
@@ -106,58 +98,47 @@ typedef enum
#endif
} nrf_ppi_channel_group_t;
-/**
- * @enum nrf_ppi_channel_include_t
- * @brief Definition of which PPI channels belong to a group.
- */
+/** @brief Definition of whether a PPI channel belongs to a group. */
typedef enum
{
NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */
NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included /**< Channel included in a group. */
} nrf_ppi_channel_include_t;
-/**
- * @enum nrf_ppi_channel_enable_t
- * @brief Definition if a PPI channel is enabled.
- */
+/** @brief Definition of whether a PPI channel is enabled. */
typedef enum
{
NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */
NRF_PPI_CHANNEL_ENABLED = PPI_CHEN_CH0_Enabled /**< Channel enabled. */
} nrf_ppi_channel_enable_t;
-/**
- * @enum nrf_ppi_task_t
- * @brief PPI tasks.
- */
+/** @brief PPI tasks. */
typedef enum
{
- /*lint -save -e30 -esym(628,__INTADDR__)*/
- NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0 */
- NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0 */
- NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1 */
- NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1 */
- NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2 */
- NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */
- NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3 */
- NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */
+ NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0. */
+ NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0. */
+ NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1. */
+ NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1. */
+ NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2. */
+ NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2. */
+ NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3. */
+ NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3. */
#if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__)
- NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4 */
- NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */
- NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5 */
- NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5 */
+ NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4. */
+ NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4. */
+ NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5. */
+ NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5. */
#endif
- /*lint -restore*/
} nrf_ppi_task_t;
+
/**
* @brief Function for enabling a given PPI channel.
*
* @details This function enables only one channel.
*
- * @param[in] channel Channel to enable.
- *
- * */
+ * @param[in] channel Channel to be enabled.
+ */
__STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel);
/**
@@ -165,7 +146,7 @@ __STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel);
*
* @details This function disables only one channel.
*
- * @param[in] channel Channel to disable.
+ * @param[in] channel Channel to be disabled.
*/
__STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel);
@@ -174,17 +155,15 @@ __STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel);
*
* @details This function checks only one channel.
*
- * @param[in] channel Channel to check.
+ * @param[in] channel Channel to be checked.
*
- * @retval NRF_PPI_CHANNEL_ENABLED If the channel is enabled.
- * @retval NRF_PPI_CHANNEL_DISABLED If the channel is not enabled.
+ * @retval NRF_PPI_CHANNEL_ENABLED The channel is enabled.
+ * @retval NRF_PPI_CHANNEL_DISABLED The channel is not enabled.
*
*/
__STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel);
-/**
- * @brief Function for disabling all PPI channels.
- */
+/** @brief Function for disabling all PPI channels. */
__STATIC_INLINE void nrf_ppi_channel_disable_all(void);
/**
@@ -204,10 +183,8 @@ __STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask);
/**
* @brief Function for setting up event and task endpoints for a given PPI channel.
*
- * @param[in] eep Event register address.
- *
- * @param[in] tep Task register address.
- *
+ * @param[in] eep Event register address.
+ * @param[in] tep Task register address.
* @param[in] channel Channel to which the given endpoints are assigned.
*/
__STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
@@ -217,7 +194,7 @@ __STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
/**
* @brief Function for setting up the event endpoint for a given PPI channel.
*
- * @param[in] eep Event register address.
+ * @param[in] eep Event register address.
* @param[in] channel Channel to which the given endpoint is assigned.
*/
__STATIC_INLINE void nrf_ppi_event_endpoint_setup(nrf_ppi_channel_t channel,
@@ -226,7 +203,7 @@ __STATIC_INLINE void nrf_ppi_event_endpoint_setup(nrf_ppi_channel_t channel,
/**
* @brief Function for setting up the task endpoint for a given PPI channel.
*
- * @param[in] tep Task register address.
+ * @param[in] tep Task register address.
* @param[in] channel Channel to which the given endpoint is assigned.
*/
__STATIC_INLINE void nrf_ppi_task_endpoint_setup(nrf_ppi_channel_t channel,
@@ -238,8 +215,7 @@ __STATIC_INLINE void nrf_ppi_task_endpoint_setup(nrf_ppi_channel_t channel,
* @brief Function for setting up task endpoint for a given PPI fork.
*
* @param[in] fork_tep Task register address.
- *
- * @param[in] channel Channel to which the given fork endpoint is assigned.
+ * @param[in] channel Channel to which the given fork endpoint is assigned.
*/
__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
uint32_t fork_tep);
@@ -247,13 +223,10 @@ __STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
/**
* @brief Function for setting up event and task endpoints for a given PPI channel and fork.
*
- * @param[in] eep Event register address.
- *
- * @param[in] tep Task register address.
- *
+ * @param[in] eep Event register address.
+ * @param[in] tep Task register address.
* @param[in] fork_tep Fork task register address (register value).
- *
- * @param[in] channel Channel to which the given endpoints are assigned.
+ * @param[in] channel Channel to which the given endpoints are assigned.
*/
__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel,
uint32_t eep,
@@ -267,9 +240,7 @@ __STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t c
* @details This function adds only one channel to the group.
*
* @param[in] channel Channel to be included in the group.
- *
* @param[in] channel_group Channel group.
- *
*/
__STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel,
nrf_ppi_channel_group_t channel_group);
@@ -280,9 +251,7 @@ __STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t ch
* @details This function adds all specified channels to the group.
*
* @param[in] channel_mask Channels to be included in the group.
- *
* @param[in] channel_group Channel group.
- *
*/
__STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask,
nrf_ppi_channel_group_t channel_group);
@@ -293,7 +262,6 @@ __STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t c
* @details This function removes only one channel from the group.
*
* @param[in] channel Channel to be removed from the group.
- *
* @param[in] channel_group Channel group.
*/
__STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel,
@@ -305,7 +273,6 @@ __STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t c
* @details This function removes all specified channels from the group.
*
* @param[in] channel_mask Channels to be removed from the group.
- *
* @param[in] channel_group Channel group.
*/
__STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask,
@@ -315,7 +282,6 @@ __STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t
* @brief Function for removing all PPI channels from a channel group.
*
* @param[in] group Channel group.
- *
*/
__STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group);
@@ -323,7 +289,6 @@ __STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group);
* @brief Function for enabling a channel group.
*
* @param[in] group Channel group.
- *
*/
__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group);
@@ -331,38 +296,61 @@ __STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group);
* @brief Function for disabling a channel group.
*
* @param[in] group Channel group.
- *
*/
__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group);
/**
* @brief Function for setting a PPI task.
*
- * @param[in] ppi_task PPI task to set.
+ * @param[in] ppi_task PPI task to be set.
*/
__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task);
/**
- * @brief Function for returning the address of a specific PPI task register.
+ * @brief Function for getting the address of the specified PPI task register.
*
* @param[in] ppi_task PPI task.
+ *
+ * @return Address of the requested PPI task register.
*/
__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task);
/**
- * @brief Function for returning the PPI enable task address of a specific group.
+ * @brief Function for getting the PPI enable task address of the specified group.
*
- * @param[in] group PPI group.
+ * @param[in] group PPI group.
+ *
+ * @return PPI enable task address of the specified group.
*/
__STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group);
/**
- * @brief Function for returning the PPI disable task address of a specific group.
+ * @brief Function for getting the PPI disable task address of the specified group.
*
- * @param[in] group PPI group.
+ * @param[in] group PPI group.
+ *
+ * @return PPI disable task address of the specified group.
*/
__STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group);
+/**
+ * @brief Function for getting the ENABLE task associated with the specified channel group.
+ *
+ * @param[in] index Channel group index.
+ *
+ * @return Requested ENABLE task.
+ */
+__STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_enable_task_get(uint8_t index);
+
+/**
+ * @brief Function for getting the DISABLE task associated with the specified channel group.
+ *
+ * @param[in] index Channel group index.
+ *
+ * @return Requested DISABLE task.
+ */
+__STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_disable_task_get(uint8_t index);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
@@ -476,17 +464,17 @@ __STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group)
__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group)
{
- NRF_PPI->TASKS_CHG[(uint32_t) group].EN = NRF_PPI_TASK_SET;
+ NRF_PPI->TASKS_CHG[(uint32_t) group].EN = 1UL;
}
__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group)
{
- NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = NRF_PPI_TASK_SET;
+ NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = 1UL;
}
__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task)
{
- *((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = NRF_PPI_TASK_SET;
+ *((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = 1UL;
}
__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task)
@@ -504,6 +492,18 @@ __STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channe
return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].DIS;
}
+__STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_enable_task_get(uint8_t index)
+{
+ NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_PPI->TASKS_CHG));
+ return (nrf_ppi_task_t)NRFX_OFFSETOF(NRF_PPI_Type, TASKS_CHG[index].EN);
+}
+
+__STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_disable_task_get(uint8_t index)
+{
+ NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_PPI->TASKS_CHG));
+ return (nrf_ppi_task_t)NRFX_OFFSETOF(NRF_PPI_Type, TASKS_CHG[index].DIS);
+}
+
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_pwm.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_pwm.h
index a85216404..55a74b549 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_pwm.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_pwm.h
@@ -50,46 +50,40 @@ extern "C" {
* function call to specify that a given output channel shall not be
* connected to a physical pin.
*/
-#define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
+#define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
+
+/** @brief Number of channels in each PWM instance. */
+#define NRF_PWM_CHANNEL_COUNT 4
/**
- * @brief Number of channels in each Pointer to the peripheral registers structure.
+ * @brief Helper macro for calculating the number of 16-bit values in the specified
+ * array of duty cycle values.
*/
-#define NRF_PWM_CHANNEL_COUNT 4
+#define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / sizeof(uint16_t))
-/**
- * @brief PWM tasks.
- */
+/** @brief PWM tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
- /*lint -restore*/
} nrf_pwm_task_t;
-/**
- * @brief PWM events.
- */
+/** @brief PWM events. */
typedef enum
{
- /*lint -save -e30*/
NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated.
NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period.
- NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the requested number of times.
- /*lint -restore*/
+ NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the specified number of times.
} nrf_pwm_event_t;
-/**
- * @brief PWM interrupts.
- */
+/** @brief PWM interrupts. */
typedef enum
{
NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
@@ -101,9 +95,7 @@ typedef enum
NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event.
} nrf_pwm_int_mask_t;
-/**
- * @brief PWM shortcuts.
- */
+/** @brief PWM shortcuts. */
typedef enum
{
NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task.
@@ -113,18 +105,14 @@ typedef enum
NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task.
} nrf_pwm_short_mask_t;
-/**
- * @brief PWM modes of operation.
- */
+/** @brief PWM modes of operation. */
typedef enum
{
NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
} nrf_pwm_mode_t;
-/**
- * @brief PWM base clock frequencies.
- */
+/** @brief PWM base clock frequencies. */
typedef enum
{
NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz.
@@ -163,7 +151,6 @@ typedef enum
NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
} nrf_pwm_dec_step_t;
-
/**
* @brief Type used for defining duty cycle values for a sequence
* loaded in @ref NRF_PWM_LOAD_COMMON mode.
@@ -219,11 +206,11 @@ typedef union {
*
* When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
* provided duty cycle values are not copied. The @p values pointer is stored
- * in the peripheral's internal register, and the values are loaded from RAM
+ * in the internal register of the peripheral, and the values are loaded from RAM
* during the sequence playback. Therefore, you must ensure that the values
* do not change before and during the sequence playback (for example,
* the values cannot be placed in a local variable that is allocated on stack).
- * If the sequence is played in a loop and the values should be updated
+ * If the sequence is played in a loop and the values are to be updated
* before the next iteration, it is safe to modify them when the corresponding
* event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
* or @ref NRF_PWM_EVENT_SEQEND1, respectively).
@@ -246,134 +233,128 @@ typedef struct
* others (14-0) compose the 15-bit value to be
* compared with the pulse generator counter. */
uint16_t length; ///< Number of 16-bit values in the array pointed by @p values.
- uint32_t repeats; ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
+ uint32_t repeats; ///< Number of times that each duty cycle is to be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
} nrf_pwm_sequence_t;
-/**
- * @brief Helper macro for calculating the number of 16-bit values in specified
- * array of duty cycle values.
- */
-#define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / sizeof(uint16_t))
-
/**
- * @brief Function for activating a specific PWM task.
+ * @brief Function for activating the specified PWM task.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] task Task to activate.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
nrf_pwm_task_t task);
/**
- * @brief Function for getting the address of a specific PWM task register.
+ * @brief Function for getting the address of the specified PWM task register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] task Requested task.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task PWM task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
- nrf_pwm_task_t task);
+ nrf_pwm_task_t task);
/**
- * @brief Function for clearing a specific PWM event.
+ * @brief Function for clearing the specified PWM event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to clear.
*/
-__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
+__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
nrf_pwm_event_t event);
/**
- * @brief Function for checking the state of a specific PWM event.
+ * @brief Function for retrieving the state of the PWM event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
- nrf_pwm_event_t event);
+ nrf_pwm_event_t event);
/**
- * @brief Function for getting the address of a specific PWM event register.
+ * @brief Function for getting the address of the specified PWM event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Requested event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event PWM event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
- nrf_pwm_event_t event);
+ nrf_pwm_event_t event);
/**
- * @brief Function for enabling specified shortcuts.
+ * @brief Function for enabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] pwm_shorts_mask Shortcuts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of shortcuts to be enabled.
*/
__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
- uint32_t pwm_shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified shortcuts.
+ * @brief Function for disabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] pwm_shorts_mask Shortcuts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of shortcuts to be disabled.
*/
__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
- uint32_t pwm_shorts_mask);
+ uint32_t mask);
/**
* @brief Function for setting the configuration of PWM shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] pwm_shorts_mask Shortcuts configuration to set.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts configuration to be set.
*/
__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
- uint32_t pwm_shorts_mask);
+ uint32_t mask);
/**
* @brief Function for enabling specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] pwm_int_mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
- uint32_t pwm_int_mask);
+ uint32_t mask);
/**
* @brief Function for disabling specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] pwm_int_mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
- uint32_t pwm_int_mask);
+ uint32_t mask);
/**
* @brief Function for setting the configuration of PWM interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] pwm_int_mask Interrupts configuration to set.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be set.
*/
__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
- uint32_t pwm_int_mask);
+ uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] pwm_int Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] pwm_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
- nrf_pwm_int_mask_t pwm_int);
+ nrf_pwm_int_mask_t pwm_int);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
@@ -424,14 +405,14 @@ __STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
/**
* @brief Function for enabling the PWM peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
/**
* @brief Function for disabling the PWM peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
@@ -442,16 +423,16 @@ __STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
* needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
* number.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] out_pins Array with pin numbers for individual PWM output channels.
*/
__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
- uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
+ uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
/**
* @brief Function for configuring the PWM peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] base_clock Base clock frequency.
* @param[in] mode Operating mode of the pulse generator counter.
* @param[in] top_value Value up to which the pulse generator counter counts.
@@ -464,11 +445,11 @@ __STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
/**
* @brief Function for defining a sequence of PWM duty cycles.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] p_seq Pointer to the sequence definition.
*/
-__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
+__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
uint8_t seq_id,
nrf_pwm_sequence_t const * p_seq);
@@ -476,11 +457,11 @@ __STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
* @brief Function for modifying the pointer to the duty cycle values
* in the specified sequence.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] p_values Pointer to an array with duty cycle values.
*/
-__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
+__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
uint8_t seq_id,
uint16_t const * p_values);
@@ -488,47 +469,47 @@ __STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
* @brief Function for modifying the total number of duty cycle values
* in the specified sequence.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] length Number of duty cycle values.
*/
__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint16_t length);
+ uint8_t seq_id,
+ uint16_t length);
/**
* @brief Function for modifying the additional number of PWM periods spent
* on each duty cycle value in the specified sequence.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] refresh Number of additional PWM periods for each duty cycle value.
*/
__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint32_t refresh);
+ uint8_t seq_id,
+ uint32_t refresh);
/**
* @brief Function for modifying the additional time added after the sequence
* is played.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] seq_id Identifier of the sequence (0 or 1).
* @param[in] end_delay Number of PWM periods added at the end of the sequence.
*/
__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint32_t end_delay);
+ uint8_t seq_id,
+ uint32_t end_delay);
/**
* @brief Function for setting the mode of loading sequence data from RAM
* and advancing the sequence.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] dec_load Mode of loading sequence data from RAM.
* @param[in] dec_step Mode of advancing the active sequence.
*/
-__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
+__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
nrf_pwm_dec_load_t dec_load,
nrf_pwm_dec_step_t dec_step);
@@ -539,11 +520,11 @@ __STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
* This function applies to two-sequence playback (concatenated sequence 0 and 1).
* A single sequence can be played back only once.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] loop_count Number of times to perform the sequence playback.
*/
__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
- uint16_t loop_count);
+ uint16_t loop_count);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
@@ -583,39 +564,39 @@ __STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
}
__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
- uint32_t pwm_shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS |= pwm_shorts_mask;
+ p_reg->SHORTS |= mask;
}
__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
- uint32_t pwm_shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS &= ~(pwm_shorts_mask);
+ p_reg->SHORTS &= ~(mask);
}
__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
- uint32_t pwm_shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS = pwm_shorts_mask;
+ p_reg->SHORTS = mask;
}
__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
- uint32_t pwm_int_mask)
+ uint32_t mask)
{
- p_reg->INTENSET = pwm_int_mask;
+ p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
- uint32_t pwm_int_mask)
+ uint32_t mask)
{
- p_reg->INTENCLR = pwm_int_mask;
+ p_reg->INTENCLR = mask;
}
__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
- uint32_t pwm_int_mask)
+ uint32_t mask)
{
- p_reg->INTEN = pwm_int_mask;
+ p_reg->INTEN = mask;
}
__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_qdec.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_qdec.h
index bd95f18db..ee8f5f19a 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_qdec.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_qdec.h
@@ -51,42 +51,30 @@ extern "C" {
*/
#define NRF_QDEC_LED_NOT_CONNECTED 0xFFFFFFFF
-/**
- * @enum nrf_qdec_task_t
- * @brief QDEC tasks.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief QDEC tasks. */
+typedef enum
{
NRF_QDEC_TASK_START = offsetof(NRF_QDEC_Type, TASKS_START), /**< Starting the quadrature decoder. */
NRF_QDEC_TASK_STOP = offsetof(NRF_QDEC_Type, TASKS_STOP), /**< Stopping the quadrature decoder. */
NRF_QDEC_TASK_READCLRACC = offsetof(NRF_QDEC_Type, TASKS_READCLRACC) /**< Reading and clearing ACC and ACCDBL registers. */
} nrf_qdec_task_t;
-/**
- * @enum nrf_qdec_event_t
- * @brief QDEC events.
- */
+/** @brief QDEC events. */
typedef enum
{
NRF_QDEC_EVENT_SAMPLERDY = offsetof(NRF_QDEC_Type, EVENTS_SAMPLERDY), /**< Event generated for every new sample. */
NRF_QDEC_EVENT_REPORTRDY = offsetof(NRF_QDEC_Type, EVENTS_REPORTRDY), /**< Event generated for every new report. */
NRF_QDEC_EVENT_ACCOF = offsetof(NRF_QDEC_Type, EVENTS_ACCOF) /**< Event generated for every accumulator overflow. */
-} nrf_qdec_event_t; /*lint -restore */
+} nrf_qdec_event_t;
-/**
- * @enum nrf_qdec_short_mask_t
- * @brief QDEC shortcuts.
- */
+/** @brief QDEC shortcuts. */
typedef enum
{
NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK = QDEC_SHORTS_REPORTRDY_READCLRACC_Msk, /**< Shortcut between REPORTRDY event and READCLRACC task. */
NRF_QDEC_SHORT_SAMPLERDY_STOP_MASK = QDEC_SHORTS_SAMPLERDY_STOP_Msk /**< Shortcut between SAMPLERDY event and STOP task. */
} nrf_qdec_short_mask_t;
-/**
- * @enum nrf_qdec_int_mask_t
- * @brief QDEC interrupts.
- */
+/** @brief QDEC interrupts. */
typedef enum
{
NRF_QDEC_INT_SAMPLERDY_MASK = QDEC_INTENSET_SAMPLERDY_Msk, /**< Mask for enabling or disabling an interrupt on SAMPLERDY event. */
@@ -94,42 +82,28 @@ typedef enum
NRF_QDEC_INT_ACCOF_MASK = QDEC_INTENSET_ACCOF_Msk /**< Mask for enabling or disabling an interrupt on ACCOF event. */
} nrf_qdec_int_mask_t;
-/**
- * @enum nrf_qdec_enable_t
- * @brief States of the enable bit.
- */
+/** @brief States of the enable bit. */
typedef enum
{
NRF_QDEC_DISABLE = QDEC_ENABLE_ENABLE_Disabled, /**< Mask for disabling the QDEC periperal. When disabled, the QDEC decoder pins are not active. */
NRF_QDEC_ENABLE = QDEC_ENABLE_ENABLE_Enabled /**< Mask for enabling the QDEC periperal. When enabled, the QDEC pins are active. */
} nrf_qdec_enable_t;
-
-/**
- * @enum nrf_qdec_dbfen_t
- * @brief States of the debounce filter enable bit.
- */
+/** @brief States of the debounce filter enable bit. */
typedef enum
{
NRF_QDEC_DBFEN_DISABLE = QDEC_DBFEN_DBFEN_Disabled, /**< Mask for disabling the debounce filter. */
NRF_QDEC_DBFEN_ENABLE = QDEC_DBFEN_DBFEN_Enabled /**< Mask for enabling the debounce filter. */
} nrf_qdec_dbfen_t;
-/**
- * @enum nrf_qdec_ledpol_t
- * @brief Active LED polarity.
- */
+/** @brief Active LED polarity. */
typedef enum
{
NRF_QDEC_LEPOL_ACTIVE_LOW = QDEC_LEDPOL_LEDPOL_ActiveLow, /**< QDEC LED active on output pin low. */
NRF_QDEC_LEPOL_ACTIVE_HIGH = QDEC_LEDPOL_LEDPOL_ActiveHigh /**< QDEC LED active on output pin high. */
} nrf_qdec_ledpol_t;
-
-/**
- * @enum nrf_qdec_sampleper_t
- * @brief Available sampling periods.
- */
+/** @brief Available sampling periods. */
typedef enum
{
NRF_QDEC_SAMPLEPER_128us = QDEC_SAMPLEPER_SAMPLEPER_128us, /**< QDEC sampling period 128 microseconds. */
@@ -142,10 +116,7 @@ typedef enum
NRF_QDEC_SAMPLEPER_16384us = QDEC_SAMPLEPER_SAMPLEPER_16384us /**< QDEC sampling period 16384 microseconds. */
} nrf_qdec_sampleper_t;
-/**
- * @enum nrf_qdec_reportper_t
- * @brief Available report periods.
- */
+/** @brief Available report periods. */
typedef enum
{
NRF_QDEC_REPORTPER_10 = QDEC_REPORTPER_REPORTPER_10Smpl, /**< QDEC report period 10 samples. */
@@ -159,59 +130,59 @@ typedef enum
NRF_QDEC_REPORTPER_DISABLED /**< QDEC reporting disabled. */
} nrf_qdec_reportper_t;
-/**
- * @brief Function for enabling QDEC.
- */
+/** @brief Function for enabling QDEC. */
__STATIC_INLINE void nrf_qdec_enable(void);
-/**
- * @brief Function for disabling QDEC.
- */
+/** @brief Function for disabling QDEC. */
__STATIC_INLINE void nrf_qdec_disable(void);
/**
* @brief Function for returning the enable state of QDEC.
+ *
* @return State of the register.
*/
__STATIC_INLINE uint32_t nrf_qdec_enable_get(void);
/**
* @brief Function for enabling QDEC interrupts by mask.
- * @param[in] qdec_int_mask Sources of the interrupts to enable.
+ *
+ * @param[in] mask Mask of interrupts to be enabled.
*/
-__STATIC_INLINE void nrf_qdec_int_enable(uint32_t qdec_int_mask);
+__STATIC_INLINE void nrf_qdec_int_enable(uint32_t mask);
/**
* @brief Function for disabling QDEC interrupts by mask.
- * @param[in] qdec_int_mask Sources of the interrupts to disable.
*
+ * @param[in] mask Mask of interrupts to be disabled.
*/
-__STATIC_INLINE void nrf_qdec_int_disable(uint32_t qdec_int_mask);
+__STATIC_INLINE void nrf_qdec_int_disable(uint32_t mask);
/**
* @brief Function for getting the enabled interrupts of the QDEC.
+ *
+ * @param[in] mask Mask of interrupts to be checked.
+ *
+ * @return Bitfield with enabled interrupts.
*/
-__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t qdec_int_mask);
+__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t mask);
-/**
- * @brief Function for enabling the debouncing filter of the QED.
- */
+/** @brief Function for enabling the QDEC debouncing filter. */
__STATIC_INLINE void nrf_qdec_dbfen_enable(void);
-/**
- * @brief Function for disabling the debouncing filter of the QED.
- */
+/** @brief Function for disabling the QDEC debouncing filter. */
__STATIC_INLINE void nrf_qdec_dbfen_disable(void);
/**
- * @brief Function for getting the state of the QDEC's debouncing filter.
- * @retval NRF_QDEC_DBFEN_DISABLE If the debouncing filter is disabled.
- * @retval NRF_QDEC_DBFEN_ENABLE If the debouncing filter is enabled.
+ * @brief Function for getting the state of the QDEC debouncing filter.
+ *
+ * @retval NRF_QDEC_DBFEN_DISABLE The debouncing filter is disabled.
+ * @retval NRF_QDEC_DBFEN_ENABLE The debouncing filter is enabled.
*/
__STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void);
/**
* @brief Function for assigning QDEC pins.
+ *
* @param[in] psela Pin number.
* @param[in] pselb Pin number.
* @param[in] pselled Pin number.
@@ -219,139 +190,174 @@ __STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void);
__STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled);
/**
- * @brief Function for setting a specific QDEC task.
- * @param[in] qdec_task QDEC task to be set.
+ * @brief Function for setting the specified QDEC task.
+ *
+ * @param[in] task QDEC task to be triggered.
*/
-__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t qdec_task);
+__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t task);
/**
* @brief Function for retrieving the address of a QDEC task register.
- * @param[in] qdec_task QDEC task.
+ *
+ * @param[in] task QDEC task to get its address.
+ *
+ * @return Address of the specified QDEC task.
*/
-__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t qdec_task);
+__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t task);
/**
- * @brief Function for clearing a specific QDEC event.
- * @param[in] qdec_event QDEC event to clear.
+ * @brief Function for clearing the specified QDEC event.
+ *
+ * @param[in] event QDEC event to be cleared.
*/
-__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t qdec_event);
+__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t event);
/**
- * @brief Function for retrieving the state of a specific QDEC event.
- * @return State of the QDEC event.
+ * @brief Function for getting the state of the specified QDEC event.
+ *
+ * @param[in] event QDEC event to be checked.
+ *
+ * @return State of the specified QDEC event.
*/
-__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t qdec_event);
+__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t event);
/**
- * @brief Function for retrieving the address of a specific QDEC event register.
- * @param[in] qdec_event QDEC event.
+ * @brief Function for retrieving the address of the specified QDEC event register.
+ *
+ * @param[in] event QDEC event to get its address.
+ *
* @return Address of the specified QDEC event.
*/
-__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t qdec_event);
+__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t event);
/**
- * @brief Function for setting QDEC shortcuts.
- * @param[in] qdec_short_mask QDEC shortcut by mask.
+ * @brief Function for setting QDEC shortcuts.
+ *
+ * @param[in] mask Mask of QDEC shortcuts to be set.
*/
-__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t qdec_short_mask);
+__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t mask);
/**
* @brief Function for clearing shortcuts of the QDEC by mask.
- * @param[in] qdec_short_mask QDEC shortcute to be cleared.
+ *
+ * @param[in] mask Mask of QDEC shortcuts to be cleared.
*/
-__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t qdec_short_mask);
+__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t mask);
/**
- * @brief Function for retrieving the value of QDEC's SAMPLEPER register.
- * @return Value of the SAMPLEPER register.
+ * @brief Function for retrieving value of the sampling period.
+ *
+ * @return Sample period @ref nrf_qdec_sampleper_t.
*/
__STATIC_INLINE int32_t nrf_qdec_sampleper_reg_get(void);
/**
- * @brief Function for converting the value of QDEC's SAMPLE PERIOD to microseconds.
- * @retval sampling period in microseconds.
+ * @brief Function for converting return value of the @p nrf_qdec_sampleper_reg_get() function
+ * to microseconds.
+ *
+ * @param[in] sampleper The sampling period.
+ *
+ * @return Period in microseconds.
*/
__STATIC_INLINE uint32_t nrf_qdec_sampleper_to_value(uint32_t sampleper);
/**
- * @brief Function for setting the value of QDEC's SAMPLEPER register.
- * @param[in] sample_per Sampling period.
+ * @brief Function for setting value of the QDEC sampling period.
+ *
+ * @param[in] sample_per The sampling period.
*/
__STATIC_INLINE void nrf_qdec_sampleper_set(nrf_qdec_sampleper_t sample_per);
/**
- * @brief Function for retrieving the value of QDEC's SAMPLE register.
+ * @brief Function for retrieving value of the QDEC SAMPLE register.
+ *
* @return Value of the SAMPLE register.
*/
__STATIC_INLINE int32_t nrf_qdec_sample_get(void);
/**
- * @brief Function for retrieving the value of QDEC's ACC register.
+ * @brief Function for retrieving value of the QDEC ACC register.
+ *
* @return Value of the ACC register.
*/
__STATIC_INLINE int32_t nrf_qdec_acc_get(void);
/**
- * @brief Function for retrieving the value of QDEC's ACCREAD register.
+ * @brief Function for retrieving value of the QDEC ACCREAD register.
+ *
* @return Value of the ACCREAD register.
*/
__STATIC_INLINE int32_t nrf_qdec_accread_get(void);
/**
- * @brief Function for retrieving the value of QDEC's ACCDBL register.
+ * @brief Function for retrieving value of the QDEC ACCDBL register.
+ *
* @return Value of the ACCDBL register.
*/
__STATIC_INLINE uint32_t nrf_qdec_accdbl_get(void);
/**
- * @brief Function for retrieving the value of QDEC's ACCDBLREAD register.
+ * @brief Function for retrieving value of the QDEC ACCDBLREAD register.
+ *
* @return Value of the ACCDBLREAD register.
*/
__STATIC_INLINE uint32_t nrf_qdec_accdblread_get(void);
/**
- * @brief Function for setting how long the LED is switched on before sampling.
- * @param[in] time_us Time (in microseconds) how long the LED is switched on before sampling.
+ * @brief Function for setting delay time between setting LED active state and start sampling.
+ *
+ * @param[in] time_us Delay time (in microseconds) between setting LED active state
+ * and start sampling.
*/
__STATIC_INLINE void nrf_qdec_ledpre_set(uint32_t time_us);
/**
* @brief Function for retrieving how long the LED is switched on before sampling.
- * @retval time_us Time (in microseconds) how long the LED is switched on before sampling.
+ *
+ * @return The gap in time in microseconds between switched LED to active state and start sampling.
*/
__STATIC_INLINE uint32_t nrf_qdec_ledpre_get(void);
/**
* @brief Function for setting the report period (in samples).
- * @param[in] reportper Number of samples.
+ *
+ * @param[in] reportper The number of samples.
*/
__STATIC_INLINE void nrf_qdec_reportper_set(nrf_qdec_reportper_t reportper);
/**
* @brief Function for retrieving the report period.
- * @retval reportper Number of samples as encoded in the register.
+ *
+ * @return The report period.
*/
__STATIC_INLINE uint32_t nrf_qdec_reportper_reg_get(void);
/**
- * @brief Function for retrieving the value of QDEC's SAMPLEPER register.
- * @param [in] reportper Reportper to be converted to amount of samples per report.
+ * @brief Function for retrieving the value of QDEC SAMPLEPER register.
+ *
+ * @param [in] reportper Reportper to be converted to amount of samples per report.
+ *
+ * @return Number of samples per report.
*/
__STATIC_INLINE uint32_t nrf_qdec_reportper_to_value(uint32_t reportper);
/**
* @brief Function for setting the active level for the LED.
- * @param[in] pol Active level for the LED.
+ *
+ * @param[in] pol Level of the active signal of the LED.
*/
__STATIC_INLINE void nrf_qdec_ledpol_set(nrf_qdec_ledpol_t pol);
/**
* @brief Function for retrieving the active level for the LED.
- * @return Active level for the LED.
+ *
+ * @return Level of the active signal of the LED.
*/
__STATIC_INLINE uint32_t nrf_qdec_ledpol_get(void);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
__STATIC_INLINE void nrf_qdec_enable(void)
{
NRF_QDEC->ENABLE = NRF_QDEC_ENABLE;
@@ -367,19 +373,19 @@ __STATIC_INLINE uint32_t nrf_qdec_enable_get(void)
return NRF_QDEC->ENABLE;
}
-__STATIC_INLINE void nrf_qdec_int_enable(uint32_t qdec_int_mask)
+__STATIC_INLINE void nrf_qdec_int_enable(uint32_t mask)
{
- NRF_QDEC->INTENSET = qdec_int_mask; // writing 0 has no effect
+ NRF_QDEC->INTENSET = mask; // writing 0 has no effect
}
-__STATIC_INLINE void nrf_qdec_int_disable(uint32_t qdec_int_mask)
+__STATIC_INLINE void nrf_qdec_int_disable(uint32_t mask)
{
- NRF_QDEC->INTENCLR = qdec_int_mask; // writing 0 has no effect
+ NRF_QDEC->INTENCLR = mask; // writing 0 has no effect
}
-__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t qdec_int_mask)
+__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t mask)
{
- return NRF_QDEC->INTENSET & qdec_int_mask; // when read this register will return the value of INTEN.
+ return NRF_QDEC->INTENSET & mask; // when read this register will return the value of INTEN.
}
__STATIC_INLINE void nrf_qdec_dbfen_enable(void)
@@ -418,43 +424,43 @@ __STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32
#endif
}
-__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t qdec_task)
+__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t task)
{
- *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task) ) = 1;
+ *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + (uint32_t)task) ) = 1;
}
-__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t qdec_task)
+__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t task)
{
- return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task);
+ return (uint32_t *)( (uint8_t *)NRF_QDEC + (uint32_t)task);
}
-__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t qdec_event)
+__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t event)
{
- *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event) ) = 0;
+ *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + (uint32_t)event) ) = 0;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_QDEC + qdec_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_QDEC + event));
(void)dummy;
#endif
}
-__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t qdec_event)
+__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t event)
{
- return *(volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event);
+ return *(volatile uint32_t *)( (uint8_t *)NRF_QDEC + (uint32_t)event);
}
-__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t qdec_event)
+__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t event)
{
- return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event);
+ return (uint32_t *)( (uint8_t *)NRF_QDEC + (uint32_t)event);
}
-__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t qdec_short_mask)
+__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t mask)
{
- NRF_QDEC->SHORTS |= qdec_short_mask;
+ NRF_QDEC->SHORTS |= mask;
}
-__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t qdec_short_mask)
+__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t mask)
{
- NRF_QDEC->SHORTS &= ~qdec_short_mask;
+ NRF_QDEC->SHORTS &= ~mask;
}
__STATIC_INLINE int32_t nrf_qdec_sampleper_reg_get(void)
@@ -533,6 +539,7 @@ __STATIC_INLINE uint32_t nrf_qdec_ledpol_get(void)
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
/** @} */
#ifdef __cplusplus
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_qspi.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_qspi.h
index c7982bd8b..5761b1dde 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_qspi.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_qspi.h
@@ -52,47 +52,33 @@ extern "C" {
*/
#define NRF_QSPI_PIN_NOT_CONNECTED 0xFF
-/**
- * @brief Macro for setting proper values to pin registers.
- */
-
+/** @brief Macro for setting proper values to pin registers. */
#define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin)
-/**
- * @brief QSPI tasks.
- */
+
+/** @brief QSPI tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE), /**< Activate the QSPI interface. */
NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */
NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */
NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */
NRF_QSPI_TASK_DEACTIVATE = offsetof(NRF_QSPI_Type, TASKS_DEACTIVATE), /**< Deactivate the QSPI interface. */
- /*lint -restore*/
} nrf_qspi_task_t;
-/**
- * @brief QSPI events.
- */
+/** @brief QSPI events. */
typedef enum
{
- /*lint -save -e30*/
NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY) /**< QSPI peripheral is ready after it executes any task. */
- /*lint -restore*/
} nrf_qspi_event_t;
-/**
- * @brief QSPI interrupts.
- */
+/** @brief QSPI interrupts. */
typedef enum
{
NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */
} nrf_qspi_int_mask_t;
-/**
- * @brief QSPI frequency divider values.
- */
+/** @brief QSPI frequency divider values. */
typedef enum
{
NRF_QSPI_FREQ_32MDIV1, /**< 32.0 MHz. */
@@ -113,9 +99,7 @@ typedef enum
NRF_QSPI_FREQ_32MDIV16, /**< 2.00 MHz. */
} nrf_qspi_frequency_t;
-/**
- * @brief Interface configuration for a read operation.
- */
+/** @brief Interface configuration for a read operation. */
typedef enum
{
NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD, /**< Single data line SPI. FAST_READ (opcode 0x0B). */
@@ -125,9 +109,7 @@ typedef enum
NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO /**< Quad data line SPI. READ4IO (opcode 0xEB). */
} nrf_qspi_readoc_t;
-/**
- * @brief Interface configuration for a write operation.
- */
+/** @brief Interface configuration for a write operation. */
typedef enum
{
NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP, /**< Single data line SPI. PP (opcode 0x02). */
@@ -136,27 +118,21 @@ typedef enum
NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO, /**< Quad data line SPI. READ4O (opcode 0x38). */
} nrf_qspi_writeoc_t;
-/**
- * @brief Interface configuration for addressing mode.
- */
+/** @brief Interface configuration for addressing mode. */
typedef enum
{
NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT, /**< 24-bit addressing. */
NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT /**< 32-bit addressing. */
} nrf_qspi_addrmode_t;
-/**
- * @brief QSPI SPI mode. Polarization and phase configuration.
- */
+/** @brief QSPI SPI mode. Polarization and phase configuration. */
typedef enum
{
NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */
NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */
} nrf_qspi_spi_mode_t;
-/**
- * @brief Addressing configuration mode.
- */
+/** @brief Addressing configuration mode. */
typedef enum
{
NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr, /**< Do not send any instruction. */
@@ -165,9 +141,7 @@ typedef enum
NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All /**< Send opcode, byte0, byte1. */
} nrf_qspi_addrconfig_mode_t;
-/**
- * @brief Erasing data length.
- */
+/** @brief Erasing data length. */
typedef enum
{
NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB, /**< Erase 4 kB block (flash command 0x20). */
@@ -175,9 +149,7 @@ typedef enum
NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All /**< Erase all (flash command 0xC7). */
} nrf_qspi_erase_len_t;
-/**
- * @brief Custom instruction length.
- */
+/** @brief Custom instruction length. */
typedef enum
{
NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B, /**< Send opcode only. */
@@ -191,9 +163,7 @@ typedef enum
NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */
} nrf_qspi_cinstr_len_t;
-/**
- * @brief Pins configuration.
- */
+/** @brief Pin configuration. */
typedef struct
{
uint8_t sck_pin; /**< SCK pin number. */
@@ -208,9 +178,7 @@ typedef struct
*/
} nrf_qspi_pins_t;
-/**
- * @brief Custom instruction configuration.
- */
+/** @brief Custom instruction configuration. */
typedef struct
{
uint8_t opcode; /**< Opcode used in custom instruction transmission. */
@@ -221,22 +189,18 @@ typedef struct
bool wren; /**< Send write enable before instruction. */
} nrf_qspi_cinstr_conf_t;
-/**
- * @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set
- */
+/** @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set */
typedef struct
{
- uint8_t opcode; /**< Opcode used to enter proper addressing mode. */
+ uint8_t opcode; /**< Opcode used to enter the proper addressing mode. */
uint8_t byte0; /**< Byte following the opcode. */
uint8_t byte1; /**< Byte following byte0. */
nrf_qspi_addrconfig_mode_t mode; /**< Extended addresing mode. */
- bool wipwait; /**< Enable/disable waiting for complete operation execution. */
+ bool wipwait; /**< Enable or disable waiting for complete operation execution. */
bool wren; /**< Send write enable before instruction. */
} nrf_qspi_addrconfig_conf_t;
-/**
- * @brief Structure with QSPI protocol interface configuration.
- */
+/** @brief Structure with QSPI protocol interface configuration. */
typedef struct
{
nrf_qspi_readoc_t readoc; /**< Read operation code. */
@@ -245,9 +209,7 @@ typedef struct
bool dpmconfig; /**< Enable the Deep Power-down Mode (DPM) feature. */
} nrf_qspi_prot_conf_t;
-/**
- * @brief QSPI physical interface configuration.
- */
+/** @brief QSPI physical interface configuration. */
typedef struct
{
uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */
@@ -256,19 +218,20 @@ typedef struct
nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as enum @ref nrf_qspi_frequency_t. */
} nrf_qspi_phy_conf_t;
+
/**
- * @brief Function for activating a specific QSPI task.
+ * @brief Function for activating the specified QSPI task.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] task Task to activate.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task);
/**
- * @brief Function for getting the address of a specific QSPI task register.
+ * @brief Function for getting the address of the specified QSPI task register.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] task Requested task.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task QSPI task.
*
* @return Address of the specified task register.
*/
@@ -276,59 +239,59 @@ __STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_task_t task);
/**
- * @brief Function for clearing a specific QSPI event.
+ * @brief Function for clearing the specified QSPI event.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] qspi_event Event to clear.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be cleared.
*/
-__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event);
+__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event);
/**
- * @brief Function for checking the state of a specific SPI event.
+ * @brief Function for retrieving the state of the QSPI event.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] qspi_event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event);
+__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event);
/**
- * @brief Function for getting the address of a specific QSPI event register.
+ * @brief Function for getting the address of the specified QSPI event register.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] qspi_event Requested event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event The specified event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
- nrf_qspi_event_t qspi_event);
+ nrf_qspi_event_t event);
/**
* @brief Function for enabling specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] qspi_int_mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
-__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask);
+__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask);
/**
* @brief Function for disabling specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] qspi_int_mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
-__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask);
+__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] qspi_int Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] qspi_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
nrf_qspi_int_mask_t qspi_int);
@@ -336,14 +299,14 @@ __STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
/**
* @brief Function for enabling the QSPI peripheral.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg);
/**
* @brief Function for disabling the QSPI peripheral.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg);
@@ -353,7 +316,7 @@ __STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg);
* If a given signal is not needed, pass the @ref NRF_QSPI_PIN_NOT_CONNECTED
* value instead of its pin number.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_pins Pointer to the pins configuration structure. See @ref nrf_qspi_pins_t.
*/
__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,
@@ -362,7 +325,7 @@ __STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,
/**
* @brief Function for setting the QSPI XIPOFFSET register.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] xip_offset Address offset in the external memory for Execute in Place operation.
*/
__STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
@@ -371,8 +334,9 @@ __STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
/**
* @brief Function for setting the QSPI IFCONFIG0 register.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] p_config Pointer to the QSPI protocol interface configuration structure. See @ref nrf_qspi_prot_conf_t.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_config Pointer to the QSPI protocol interface configuration structure.
+ * See @ref nrf_qspi_prot_conf_t.
*/
__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_prot_conf_t * p_config);
@@ -380,8 +344,9 @@ __STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
/**
* @brief Function for setting the QSPI IFCONFIG1 register.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] p_config Pointer to the QSPI physical interface configuration structure. See @ref nrf_qspi_phy_conf_t.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_config Pointer to the QSPI physical interface configuration structure.
+ * See @ref nrf_qspi_phy_conf_t.
*/
__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_phy_conf_t * p_config);
@@ -389,7 +354,7 @@ __STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
/**
* @brief Function for setting the QSPI ADDRCONF register.
*
- * Function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure
+ * This function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure
* is sent during the start of the peripheral. Remember that the reset instruction can set
* addressing mode to default in the memory device. If memory reset is necessary before configuring
* the addressing mode, use custom instruction feature instead of this function.
@@ -397,8 +362,9 @@ __STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
* using a custom instruction feature (reset enable and then reset), set proper addressing mode
* using the custom instruction feature.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] p_config Pointer to the addressing mode configuration structure. See @ref nrf_qspi_addrconfig_conf_t.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_config Pointer to the addressing mode configuration structure.
+ * See @ref nrf_qspi_addrconfig_conf_t.
*/
__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_addrconfig_conf_t * p_config);
@@ -406,7 +372,7 @@ __STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type *
/**
* @brief Function for setting write data into the peripheral register (without starting the process).
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buffer Pointer to the writing buffer.
* @param[in] length Lenght of the writing data.
* @param[in] dest_addr Address in memory to write to.
@@ -419,7 +385,7 @@ __STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
/**
* @brief Function for setting read data into the peripheral register (without starting the process).
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[out] p_buffer Pointer to the reading buffer.
* @param[in] length Length of the read data.
* @param[in] src_addr Address in memory to read from.
@@ -432,7 +398,7 @@ __STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
/**
* @brief Function for setting erase data into the peripheral register (without starting the process).
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] erase_addr Start address to erase. Address must have padding set to 4 bytes.
* @param[in] len Size of erasing area.
*/
@@ -443,7 +409,7 @@ __STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
/**
* @brief Function for getting the peripheral status register.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Peripheral status register.
*/
@@ -452,7 +418,7 @@ __STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg);
/**
* @brief Function for getting the device status register stored in the peripheral status register.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Device status register (lower byte).
*/
@@ -461,10 +427,10 @@ __STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg);
/**
* @brief Function for checking if the peripheral is busy or not.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @retval true If QSPI is busy.
- * @retval false If QSPI is ready.
+ * @retval true The QSPI is busy.
+ * @retval false The QSPI is ready.
*/
__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg);
@@ -474,7 +440,7 @@ __STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg);
* This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument
* (sending only opcode without data).
*
- * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] length Length of the custom instruction data.
* @param[in] p_tx_data Pointer to the data to send with the custom instruction.
*/
@@ -484,7 +450,8 @@ __STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
/**
* @brief Function for getting data from register after custom instruction transmission.
- * @param[in] p_reg Pointer to the peripheral register structure.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] length Length of the custom instruction data.
* @param[in] p_rx_data Pointer to the reading buffer.
*/
@@ -495,13 +462,46 @@ __STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
/**
* @brief Function for sending custom instruction to external memory.
*
- * @param[in] p_reg Pointer to the peripheral register structure.
- * @param[in] p_config Pointer to the custom instruction configuration structure. See @ref nrf_qspi_cinstr_conf_t.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_config Pointer to the custom instruction configuration structure.
+ * See @ref nrf_qspi_cinstr_conf_t.
*/
__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
const nrf_qspi_cinstr_conf_t * p_config);
+/**
+ * @brief Function for starting a custom instruction long transfer.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_config Pointer to the custom instruction configuration structure.
+ * See @ref nrf_qspi_cinstr_conf_t.
+ */
+__STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
+ const nrf_qspi_cinstr_conf_t * p_config);
+
+/**
+ * @brief Function for checking whether a custom instruction long transfer is ongoing.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval true Custom instruction long transfer is ongoing.
+ * @retval false Custom instruction long transfer is not ongoing.
+ */
+__STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg);
+
+/**
+ * @brief Function for continuing a custom instruction long transfer.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] length Length of the custom instruction data.
+ * @param[in] finalize True if the custom instruction long transfer is to be finalized.
+ * False if the custom instruction long transfer is to be continued.
+ */
+__STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
+ nrf_qspi_cinstr_len_t length,
+ bool finalize);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task)
@@ -515,30 +515,30 @@ __STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
return ((uint32_t)p_reg + (uint32_t)task);
}
-__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event)
+__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event)
{
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event)) = 0x0UL;
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
}
-__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event)
+__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event)
{
- return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event);
+ return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
- nrf_qspi_event_t qspi_event)
+ nrf_qspi_event_t event)
{
- return (uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event);
+ return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
-__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask)
+__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask)
{
- p_reg->INTENSET = qspi_int_mask;
+ p_reg->INTENSET = mask;
}
-__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask)
+__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask)
{
- p_reg->INTENCLR = qspi_int_mask;
+ p_reg->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
@@ -755,6 +755,34 @@ __STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type *
((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos));
}
+__STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
+ const nrf_qspi_cinstr_conf_t * p_config)
+{
+ p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
+ ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
+ ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
+ ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
+ ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
+ ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos) |
+ (QSPI_CINSTRCONF_LFEN_Msk));
+}
+
+__STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg)
+{
+ return (bool)((p_reg->CINSTRCONF & (QSPI_CINSTRCONF_LFEN_Msk | QSPI_CINSTRCONF_LFSTOP_Msk))
+ == QSPI_CINSTRCONF_LFEN_Msk);
+}
+
+__STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
+ nrf_qspi_cinstr_len_t length,
+ bool finalize)
+{
+ uint32_t mask = (((uint32_t)length << QSPI_CINSTRCONF_LENGTH_Pos) | (QSPI_CINSTRCONF_LFEN_Msk));
+ mask |= (finalize ? QSPI_CINSTRCONF_LFSTOP_Msk : 0);
+
+ p_reg->CINSTRCONF = mask;
+}
+
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_radio.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_radio.h
index d42a71f4c..071fd71fd 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_radio.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_radio.h
@@ -45,12 +45,9 @@ extern "C" {
* @brief Hardware access layer for managing the RADIO peripheral.
*/
-/**
- * @brief RADIO tasks.
- */
+/** @brief RADIO tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_RADIO_TASK_TXEN = offsetof(NRF_RADIO_Type, TASKS_TXEN), /**< Enable RADIO in TX mode. */
NRF_RADIO_TASK_RXEN = offsetof(NRF_RADIO_Type, TASKS_RXEN), /**< Enable RADIO in RX mode. */
NRF_RADIO_TASK_START = offsetof(NRF_RADIO_Type, TASKS_START), /**< Start RADIO. */
@@ -72,15 +69,11 @@ typedef enum
#if defined(RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk) || defined(__NRFX_DOXYGEN__)
NRF_RADIO_TASK_CCASTOP = offsetof(NRF_RADIO_Type, TASKS_CCASTOP), /**< Stop the Clear Channel Assessment. */
#endif
- /*lint -restore*/
} nrf_radio_task_t;
-/**
- * @brief RADIO events.
- */
+/** @brief RADIO events. */
typedef enum
{
- /*lint -save -e30*/
NRF_RADIO_EVENT_READY = offsetof(NRF_RADIO_Type, EVENTS_READY), /**< Radio has ramped up and is ready to be started. */
NRF_RADIO_EVENT_ADDRESS = offsetof(NRF_RADIO_Type, EVENTS_ADDRESS), /**< Address sent or received. */
NRF_RADIO_EVENT_PAYLOAD = offsetof(NRF_RADIO_Type, EVENTS_PAYLOAD), /**< Packet payload sent or received. */
@@ -131,12 +124,9 @@ typedef enum
and BleIeee802154_250Kbit modes when last
bit is sent on the air. */
#endif
- /*lint -restore*/
} nrf_radio_event_t;
-/**
- * @brief RADIO interrupts.
- */
+/** @brief RADIO interrupts. */
typedef enum
{
NRF_RADIO_INT_READY_MASK = RADIO_INTENSET_READY_Msk, /**< Interrupt on READY event. */
@@ -189,9 +179,7 @@ typedef enum
#endif
} nrf_radio_int_mask_t;
-/**
- * @brief RADIO shortcuts.
- */
+/** @brief RADIO shortcuts. */
typedef enum
{
NRF_RADIO_SHORT_READY_START_MASK = RADIO_SHORTS_READY_START_Msk, /**< Shortcut between READY event and START task. */
@@ -238,9 +226,7 @@ typedef enum
} nrf_radio_short_mask_t;
#if defined(RADIO_CCACTRL_CCAMODE_Msk) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief RADIO Clear Channel Assessment modes.
- */
+/** @brief RADIO Clear Channel Assessment modes. */
typedef enum
{
NRF_RADIO_CCA_MODE_ED = RADIO_CCACTRL_CCAMODE_EdMode, /**< Energy Above Threshold. Will report busy whenever energy is detected above set threshold. */
@@ -251,9 +237,7 @@ typedef enum
} nrf_radio_cca_mode_t;
#endif // defined(RADIO_CCACTRL_CCAMODE_Msk) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief Types of RADIO States.
- */
+/** @brief Types of RADIO states. */
typedef enum
{
NRF_RADIO_STATE_DISABLED = RADIO_STATE_STATE_Disabled, /**< No operations are going on inside the radio and the power consumption is at a minimum. */
@@ -267,9 +251,7 @@ typedef enum
NRF_RADIO_STATE_TXDISABLE = RADIO_STATE_STATE_TxDisable, /**< The radio is disabling the transmitter. */
} nrf_radio_state_t;
-/**
- * @brief Types of RADIO TX power.
- */
+/** @brief Types of RADIO TX power. */
typedef enum
{
#if defined(RADIO_TXPOWER_TXPOWER_Pos8dBm) || defined(__NRFX_DOXYGEN__)
@@ -303,9 +285,7 @@ typedef enum
#endif
} nrf_radio_txpower_t;
-/**
- * @brief Types of RADIO modes (data rate and modulation).
- */
+/** @brief Types of RADIO modes (data rate and modulation). */
typedef enum
{
NRF_RADIO_MODE_NRF_1MBIT = RADIO_MODE_MODE_Nrf_1Mbit, /**< 1Mbit/s Nordic proprietary radio mode. */
@@ -329,9 +309,7 @@ typedef enum
} nrf_radio_mode_t;
#if defined(RADIO_PCNF0_PLEN_Msk) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief Types of preamble length.
- */
+/** @brief Types of preamble length. */
typedef enum
{
NRF_RADIO_PREAMBLE_LENGTH_8BIT = RADIO_PCNF0_PLEN_8bit, /**< 8-bit preamble. */
@@ -345,9 +323,7 @@ typedef enum
} nrf_radio_preamble_length_t;
#endif // defined(RADIO_PCNF0_PLEN_Msk) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief Types of CRC calculatons regarding address.
- */
+/** @brief Types of CRC calculatons regarding address. */
typedef enum
{
NRF_RADIO_CRC_ADDR_INCLUDE = RADIO_CRCCNF_SKIPADDR_Include, /**< CRC calculation includes address field. */
@@ -357,9 +333,7 @@ typedef enum
#endif
} nrf_radio_crc_addr_t;
-/**
- * @brief Packet configuration.
- */
+/** @brief Packet configuration. */
typedef struct
{
uint8_t lflen; /**< Length on air of LENGTH field in number of bits. */
@@ -390,70 +364,69 @@ typedef struct
/**
* @brief Function for activating a specific RADIO task.
*
- * @param[in] radio_task Task to activate.
+ * @param[in] task Task to be activated.
*/
-__STATIC_INLINE void nrf_radio_task_trigger(nrf_radio_task_t radio_task);
+__STATIC_INLINE void nrf_radio_task_trigger(nrf_radio_task_t task);
/**
* @brief Function for getting the address of a specific RADIO task register.
*
* This function can be used by the PPI module.
*
- * @param[in] radio_task Requested task.
+ * @param[in] task Requested task.
*
* @return Address of the specified task register.
*/
-__STATIC_INLINE uint32_t nrf_radio_task_address_get(nrf_radio_task_t radio_task);
+__STATIC_INLINE uint32_t nrf_radio_task_address_get(nrf_radio_task_t task);
/**
* @brief Function for clearing a specific RADIO event.
*
- * @param[in] radio_event Event to clean.
+ * @param[in] event Event to clean.
*/
-__STATIC_INLINE void nrf_radio_event_clear(nrf_radio_event_t radio_event);
+__STATIC_INLINE void nrf_radio_event_clear(nrf_radio_event_t event);
/**
- * @brief Function for checking the state of a specific RADIO event.
+ * @brief Function for retrieving the state of the RADIO event.
*
- * @param[in] radio_event Event to check.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_radio_event_check(nrf_radio_event_t radio_event);
+__STATIC_INLINE bool nrf_radio_event_check(nrf_radio_event_t event);
/**
* @brief Function for getting the address of a specific RADIO event register.
*
* This function can be used by the PPI module.
*
- * @param[in] radio_event Requested Event.
+ * @param[in] event Requested Event.
*
* @return Address of the specified event register.
*/
-__STATIC_INLINE uint32_t nrf_radio_event_address_get(nrf_radio_event_t radio_event);
+__STATIC_INLINE uint32_t nrf_radio_event_address_get(nrf_radio_event_t event);
/**
* @brief Function for enabling specified RADIO shortcuts.
*
- * @param[in] radio_shorts_mask Mask of shortcuts.
- *
+ * @param[in] shorts_mask Mask of shortcuts.
*/
-__STATIC_INLINE void nrf_radio_shorts_enable(uint32_t radio_shorts_mask);
+__STATIC_INLINE void nrf_radio_shorts_enable(uint32_t shorts_mask);
/**
* @brief Function for disabling specified RADIO shortcuts.
*
- * @param[in] radio_shorts_mask Mask of shortcuts.
+ * @param[in] shorts_mask Mask of shortcuts.
*/
-__STATIC_INLINE void nrf_radio_shorts_disable(uint32_t radio_shorts_mask);
+__STATIC_INLINE void nrf_radio_shorts_disable(uint32_t shorts_mask);
/**
* @brief Function for setting the configuration of RADIO shortcuts.
*
- * @param[in] radio_shorts_mask Shortcuts configuration to set.
+ * @param[in] shorts_mask Shortcuts configuration to set.
*/
-__STATIC_INLINE void nrf_radio_shorts_set(uint32_t radio_shorts_mask);
+__STATIC_INLINE void nrf_radio_shorts_set(uint32_t shorts_mask);
/**
* @brief Function for getting the configuration of RADIO shortcuts.
@@ -465,32 +438,32 @@ __STATIC_INLINE uint32_t nrf_radio_shorts_get(void);
/**
* @brief Function for enabling specified RADIO interrupts.
*
- * @param[in] radio_int_mask Mask of interrupts.
+ * @param[in] int_mask Mask of interrupts.
*/
-__STATIC_INLINE void nrf_radio_int_enable(uint32_t radio_int_mask);
+__STATIC_INLINE void nrf_radio_int_enable(uint32_t int_mask);
/**
* @brief Function for disabling specified RADIO interrupts.
*
- * @param[in] radio_int_mask Mask of interrupts.
+ * @param[in] int_mask Mask of interrupts.
*/
-__STATIC_INLINE void nrf_radio_int_disable(uint32_t radio_int_mask);
+__STATIC_INLINE void nrf_radio_int_disable(uint32_t int_mask);
/**
* @brief Function for getting the state of a specific interrupt.
*
- * @param[in] radio_int_mask Interrupt to check.
+ * @param[in] int_mask Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
-__STATIC_INLINE bool nrf_radio_int_enable_check(nrf_radio_int_mask_t radio_int_mask);
+__STATIC_INLINE bool nrf_radio_int_enable_check(nrf_radio_int_mask_t int_mask);
/**
* @brief Function for getting CRC status of last received packet.
*
- * @retval true If the packet was received without CRC error .
- * @retval false If the packet was received with CRC error.
+ * @retval true The packet was received without CRC error.
+ * @retval false The packet was received with CRC error.
*/
__STATIC_INLINE bool nrf_radio_crc_status_check(void);
@@ -519,16 +492,16 @@ __STATIC_INLINE uint8_t nrf_radio_dai_get(void);
/**
* @brief Function for getting status on payload length.
*
- * @retval 0 If the payload is lesser than PCNF1.MAXLEN.
- * @retval 1 If the payload is greater than PCNF1.MAXLEN.
+ * @retval 0 The payload is lesser than PCNF1.MAXLEN.
+ * @retval 1 The payload is greater than PCNF1.MAXLEN.
*/
__STATIC_INLINE uint8_t nrf_radio_pdustat_get(void);
/**
* @brief Function for getting status on what rate packet is received with in Long Range.
*
- * @retval 0 If the frame is received at 125kbps.
- * @retval 1 If the frame is received at 500kbps.
+ * @retval 0 The frame is received at 125kbps.
+ * @retval 1 The frame is received at 500kbps.
*/
__STATIC_INLINE uint8_t nrf_radio_cistat_get(void);
#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk) || defined(__NRFX_DOXYGEN__)
@@ -940,48 +913,48 @@ __STATIC_INLINE void nrf_radio_power_set(bool radio_power);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
-__STATIC_INLINE void nrf_radio_task_trigger(nrf_radio_task_t radio_task)
+__STATIC_INLINE void nrf_radio_task_trigger(nrf_radio_task_t task)
{
- *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_task)) = 0x1UL;
+ *((volatile uint32_t *)((uint8_t *)NRF_RADIO + (uint32_t)task)) = 0x1UL;
}
-__STATIC_INLINE uint32_t nrf_radio_task_address_get(nrf_radio_task_t radio_task)
+__STATIC_INLINE uint32_t nrf_radio_task_address_get(nrf_radio_task_t task)
{
- return ((uint32_t)NRF_RADIO + (uint32_t)radio_task);
+ return ((uint32_t)NRF_RADIO + (uint32_t)task);
}
-__STATIC_INLINE void nrf_radio_event_clear(nrf_radio_event_t radio_event)
+__STATIC_INLINE void nrf_radio_event_clear(nrf_radio_event_t event)
{
- *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_event)) = 0x0UL;
+ *((volatile uint32_t *)((uint8_t *)NRF_RADIO + (uint32_t)event)) = 0x0UL;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RADIO + (uint32_t)event));
(void)dummy;
#endif
}
-__STATIC_INLINE bool nrf_radio_event_check(nrf_radio_event_t radio_event)
+__STATIC_INLINE bool nrf_radio_event_check(nrf_radio_event_t event)
{
- return (bool) *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_event));
+ return (bool) *((volatile uint32_t *)((uint8_t *)NRF_RADIO + (uint32_t)event));
}
-__STATIC_INLINE uint32_t nrf_radio_event_address_get(nrf_radio_event_t radio_event)
+__STATIC_INLINE uint32_t nrf_radio_event_address_get(nrf_radio_event_t event)
{
- return ((uint32_t)NRF_RADIO + (uint32_t)radio_event);
+ return ((uint32_t)NRF_RADIO + (uint32_t)event);
}
-__STATIC_INLINE void nrf_radio_shorts_enable(uint32_t radio_shorts_mask)
+__STATIC_INLINE void nrf_radio_shorts_enable(uint32_t shorts_mask)
{
- NRF_RADIO->SHORTS |= radio_shorts_mask;
+ NRF_RADIO->SHORTS |= shorts_mask;
}
-__STATIC_INLINE void nrf_radio_shorts_disable(uint32_t radio_shorts_mask)
+__STATIC_INLINE void nrf_radio_shorts_disable(uint32_t shorts_mask)
{
- NRF_RADIO->SHORTS &= ~radio_shorts_mask;
+ NRF_RADIO->SHORTS &= ~shorts_mask;
}
-__STATIC_INLINE void nrf_radio_shorts_set(uint32_t radio_shorts_mask)
+__STATIC_INLINE void nrf_radio_shorts_set(uint32_t shorts_mask)
{
- NRF_RADIO->SHORTS = radio_shorts_mask;
+ NRF_RADIO->SHORTS = shorts_mask;
}
__STATIC_INLINE uint32_t nrf_radio_shorts_get(void)
@@ -989,19 +962,19 @@ __STATIC_INLINE uint32_t nrf_radio_shorts_get(void)
return NRF_RADIO->SHORTS;
}
-__STATIC_INLINE void nrf_radio_int_enable(uint32_t radio_int_mask)
+__STATIC_INLINE void nrf_radio_int_enable(uint32_t int_mask)
{
- NRF_RADIO->INTENSET = radio_int_mask;
+ NRF_RADIO->INTENSET = int_mask;
}
-__STATIC_INLINE void nrf_radio_int_disable(uint32_t radio_int_mask)
+__STATIC_INLINE void nrf_radio_int_disable(uint32_t int_mask)
{
- NRF_RADIO->INTENCLR = radio_int_mask;
+ NRF_RADIO->INTENCLR = int_mask;
}
-__STATIC_INLINE bool nrf_radio_int_enable_check(nrf_radio_int_mask_t radio_int_mask)
+__STATIC_INLINE bool nrf_radio_int_enable_check(nrf_radio_int_mask_t int_mask)
{
- return (bool)(NRF_RADIO->INTENSET & radio_int_mask);
+ return (bool)(NRF_RADIO->INTENSET & int_mask);
}
__STATIC_INLINE bool nrf_radio_crc_status_check(void)
@@ -1069,7 +1042,7 @@ __STATIC_INLINE void nrf_radio_frequency_set(uint16_t radio_frequency)
NRF_RADIO->FREQUENCY = delta;
#else
NRFX_ASSERT(radio_frequency >= 2400);
- NRF_RADIO->FREQUENCY = (uint32_t)(2400 - radio_frequency);
+ NRF_RADIO->FREQUENCY = (uint32_t)(radio_frequency - 2400);
#endif //defined(RADIO_FREQUENCY_MAP_Msk)
}
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_regulators.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_regulators.h
index 6af58bfc5..c2a18a704 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_regulators.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_regulators.h
@@ -48,7 +48,7 @@ extern "C" {
/**
* @brief Function for enabling or disabling DCDC converter.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] enable Set true to enable or false to disable DCDC converter.
*/
__STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool enable);
@@ -61,7 +61,7 @@ __STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool
*
* @note This function never returns.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_regulators_system_off(NRF_REGULATORS_Type * p_reg);
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_rng.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_rng.h
index 07b285812..4bed21a81 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_rng.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_rng.h
@@ -42,201 +42,187 @@ extern "C" {
* @defgroup nrf_rng_hal RNG HAL
* @{
* @ingroup nrf_rng
- * @brief Hardware access layer for managing the Random Number Generator (RNG) peripheral.
+ * @brief Hardware access layer (HAL) for managing the Random Number Generator (RNG) peripheral.
*/
-#define NRF_RNG_TASK_SET (1UL)
-#define NRF_RNG_EVENT_CLEAR (0UL)
-/**
- * @enum nrf_rng_task_t
- * @brief RNG tasks.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief RNG tasks. */
+typedef enum
{
NRF_RNG_TASK_START = offsetof(NRF_RNG_Type, TASKS_START), /**< Start the random number generator. */
NRF_RNG_TASK_STOP = offsetof(NRF_RNG_Type, TASKS_STOP) /**< Stop the random number generator. */
-} nrf_rng_task_t; /*lint -restore */
+} nrf_rng_task_t;
-/**
- * @enum nrf_rng_event_t
- * @brief RNG events.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief RNG events. */
+typedef enum
{
NRF_RNG_EVENT_VALRDY = offsetof(NRF_RNG_Type, EVENTS_VALRDY) /**< New random number generated event. */
-} nrf_rng_event_t; /*lint -restore */
+} nrf_rng_event_t;
-/**
- * @enum nrf_rng_int_mask_t
- * @brief RNG interrupts.
- */
+/** @brief RNG interrupts. */
typedef enum
{
- NRF_RNG_INT_VALRDY_MASK = RNG_INTENSET_VALRDY_Msk /**< Mask for enabling or disabling an interrupt on VALRDY event. */
+ NRF_RNG_INT_VALRDY_MASK = RNG_INTENSET_VALRDY_Msk /**< Mask for enabling or disabling an interrupt on VALRDY event. */
} nrf_rng_int_mask_t;
-/**
- * @enum nrf_rng_short_mask_t
- * @brief Types of RNG shortcuts.
- */
+/** @brief Types of RNG shortcuts. */
typedef enum
{
- NRF_RNG_SHORT_VALRDY_STOP_MASK = RNG_SHORTS_VALRDY_STOP_Msk /**< Mask for setting shortcut between EVENT_VALRDY and TASK_STOP. */
+ NRF_RNG_SHORT_VALRDY_STOP_MASK = RNG_SHORTS_VALRDY_STOP_Msk /**< Mask for setting shortcut between EVENT_VALRDY and TASK_STOP. */
} nrf_rng_short_mask_t;
+
/**
* @brief Function for enabling interrupts.
*
- * @param[in] rng_int_mask Mask of interrupts.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
-__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask);
+__STATIC_INLINE void nrf_rng_int_enable(uint32_t mask);
/**
* @brief Function for disabling interrupts.
*
- * @param[in] rng_int_mask Mask of interrupts.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
-__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask);
+__STATIC_INLINE void nrf_rng_int_disable(uint32_t mask);
/**
- * @brief Function for getting the state of a specific interrupt.
+ * @brief Function for getting the state of the specified interrupt.
*
- * @param[in] rng_int_mask Interrupt.
+ * @param[in] mask Interrupts to be checked.
*
- * @retval true If the interrupt is not enabled.
- * @retval false If the interrupt is enabled.
+ * @retval true The interrupt is not enabled.
+ * @retval false The interrupt is enabled.
*/
-__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask);
+__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t mask);
/**
- * @brief Function for getting the address of a specific task.
+ * @brief Function for getting the address of the specified task.
*
* This function can be used by the PPI module.
*
- * @param[in] rng_task Task.
+ * @param[in] rng_task The specified task.
+ *
+ * @return Address of the specified task.
*/
__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task);
/**
- * @brief Function for setting a specific task.
+ * @brief Function for triggering the specified task.
*
- * @param[in] rng_task Task.
+ * @param[in] rng_task The specified Task.
*/
__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task);
/**
- * @brief Function for getting address of a specific event.
+ * @brief Function for getting address of the specified event.
*
* This function can be used by the PPI module.
*
- * @param[in] rng_event Event.
+ * @param[in] rng_event The specified event.
+ *
+ * @return Address of the specified event.
*/
__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event);
/**
- * @brief Function for clearing a specific event.
+ * @brief Function for clearing the specified event.
*
- * @param[in] rng_event Event.
+ * @param[in] rng_event The specified event.
*/
__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event);
/**
- * @brief Function for getting the state of a specific event.
+ * @brief Function for getting the state of the specified event.
*
- * @param[in] rng_event Event.
+ * @param[in] rng_event The specified event.
*
- * @retval true If the event is not set.
- * @retval false If the event is set.
+ * @retval true The event is not set.
+ * @retval false The event is set.
*/
__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event);
/**
* @brief Function for setting shortcuts.
*
- * @param[in] rng_short_mask Mask of shortcuts.
- *
+ * @param[in] mask Mask of shortcuts.
*/
-__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask);
+__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t mask);
/**
* @brief Function for clearing shortcuts.
*
- * @param[in] rng_short_mask Mask of shortcuts.
- *
+ * @param[in] mask Mask of shortcuts.
*/
-__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask);
+__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t mask);
/**
* @brief Function for getting the previously generated random value.
*
- * @return Previously generated random value.
+ * @return Previously generated random value.
*/
__STATIC_INLINE uint8_t nrf_rng_random_value_get(void);
-/**
- * @brief Function for enabling digital error correction.
- */
+/** @brief Function for enabling digital error correction. */
__STATIC_INLINE void nrf_rng_error_correction_enable(void);
-/**
- * @brief Function for disabling digital error correction.
- */
+/** @brief Function for disabling digital error correction. */
__STATIC_INLINE void nrf_rng_error_correction_disable(void);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
-__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask)
+__STATIC_INLINE void nrf_rng_int_enable(uint32_t mask)
{
- NRF_RNG->INTENSET = rng_int_mask;
+ NRF_RNG->INTENSET = mask;
}
-__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask)
+__STATIC_INLINE void nrf_rng_int_disable(uint32_t mask)
{
- NRF_RNG->INTENCLR = rng_int_mask;
+ NRF_RNG->INTENCLR = mask;
}
-__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask)
+__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t mask)
{
- return (bool)(NRF_RNG->INTENCLR & rng_int_mask);
+ return (bool)(NRF_RNG->INTENCLR & mask);
}
__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task)
{
- return (uint32_t *)((uint8_t *)NRF_RNG + rng_task);
+ return (uint32_t *)((uint8_t *)NRF_RNG + (uint32_t)rng_task);
}
__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task)
{
- *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_task)) = NRF_RNG_TASK_SET;
+ *((volatile uint32_t *)((uint8_t *)NRF_RNG + (uint32_t)rng_task)) = 0x1UL;
}
__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event)
{
- return (uint32_t *)((uint8_t *)NRF_RNG + rng_event);
+ return (uint32_t *)((uint8_t *)NRF_RNG + (uint32_t)rng_event);
}
__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event)
{
- *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)) = NRF_RNG_EVENT_CLEAR;
+ *((volatile uint32_t *)((uint8_t *)NRF_RNG + (uint32_t)rng_event)) = 0x0UL;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RNG + (uint32_t)rng_event));
(void)dummy;
#endif
}
__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event)
{
- return (bool) * ((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event));
+ return (bool) * ((volatile uint32_t *)((uint8_t *)NRF_RNG + (uint32_t)rng_event));
}
-__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask)
+__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t mask)
{
- NRF_RNG->SHORTS |= rng_short_mask;
+ NRF_RNG->SHORTS |= mask;
}
-__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask)
+__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t mask)
{
- NRF_RNG->SHORTS &= ~rng_short_mask;
+ NRF_RNG->SHORTS &= ~mask;
}
__STATIC_INLINE uint8_t nrf_rng_random_value_get(void)
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_rtc.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_rtc.h
index 079898c67..1987ea507 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_rtc.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_rtc.h
@@ -46,44 +46,42 @@ extern "C" {
*/
/** @brief Macro for getting the number of compare channels available in a given RTC instance. */
-#define NRF_RTC_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(RTC, id, _CC_NUM)
+#define NRF_RTC_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(RTC, id, _CC_NUM)
-#define RTC_INPUT_FREQ 32768 /**< Input frequency of the RTC instance. */
+/** @brief Input frequency of the RTC instance. */
+#define RTC_INPUT_FREQ 32768
/** @brief Macro for converting expected frequency to prescaler setting. */
#define RTC_FREQ_TO_PRESCALER(FREQ) (uint16_t)(((RTC_INPUT_FREQ) / (FREQ)) - 1)
-/**< Macro for wrapping values to RTC capacity. */
+/** @brief Macro for trimming values to the RTC bit width. */
#define RTC_WRAP(val) ((val) & RTC_COUNTER_COUNTER_Msk)
-#define RTC_CHANNEL_INT_MASK(ch) \
- ((uint32_t)(NRF_RTC_INT_COMPARE0_MASK) << (ch))
+/** @brief Macro for creating the interrupt bitmask for the specified compare channel. */
+#define RTC_CHANNEL_INT_MASK(ch) ((uint32_t)(NRF_RTC_INT_COMPARE0_MASK) << (ch))
+
+/** @brief Macro for obtaining the compare event for the specified channel. */
+#define RTC_CHANNEL_EVENT_ADDR(ch) (nrf_rtc_event_t)((NRF_RTC_EVENT_COMPARE_0) + (ch) * sizeof(uint32_t))
-#define RTC_CHANNEL_EVENT_ADDR(ch) \
- (nrf_rtc_event_t)((NRF_RTC_EVENT_COMPARE_0) + (ch) * sizeof(uint32_t))
/** @brief RTC tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_RTC_TASK_START = offsetof(NRF_RTC_Type,TASKS_START), /**< Start. */
NRF_RTC_TASK_STOP = offsetof(NRF_RTC_Type,TASKS_STOP), /**< Stop. */
NRF_RTC_TASK_CLEAR = offsetof(NRF_RTC_Type,TASKS_CLEAR), /**< Clear. */
NRF_RTC_TASK_TRIGGER_OVERFLOW = offsetof(NRF_RTC_Type,TASKS_TRIGOVRFLW),/**< Trigger overflow. */
- /*lint -restore*/
} nrf_rtc_task_t;
/** @brief RTC events. */
typedef enum
{
- /*lint -save -e30*/
NRF_RTC_EVENT_TICK = offsetof(NRF_RTC_Type,EVENTS_TICK), /**< Tick event. */
NRF_RTC_EVENT_OVERFLOW = offsetof(NRF_RTC_Type,EVENTS_OVRFLW), /**< Overflow event. */
NRF_RTC_EVENT_COMPARE_0 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[0]), /**< Compare 0 event. */
NRF_RTC_EVENT_COMPARE_1 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[1]), /**< Compare 1 event. */
NRF_RTC_EVENT_COMPARE_2 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[2]), /**< Compare 2 event. */
NRF_RTC_EVENT_COMPARE_3 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[3]) /**< Compare 3 event. */
- /*lint -restore*/
} nrf_rtc_event_t;
/** @brief RTC interrupts. */
@@ -97,12 +95,13 @@ typedef enum
NRF_RTC_INT_COMPARE3_MASK = RTC_INTENSET_COMPARE3_Msk /**< RTC interrupt from compare event on channel 3. */
} nrf_rtc_int_t;
+
/**
* @brief Function for setting a compare value for a channel.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] ch Channel.
- * @param[in] cc_val Compare value to set.
+ * @param[in] cc_val Compare value to be set.
*/
__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_reg, uint32_t ch, uint32_t cc_val);
@@ -136,7 +135,7 @@ __STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_reg, uint32_t mask);
* @brief Function for checking if interrupts are enabled.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] mask Mask of interrupt flags to check.
+ * @param[in] mask Mask of interrupt flags to be checked.
*
* @return Mask with enabled interrupts.
*/
@@ -211,7 +210,7 @@ __STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_reg, nrf_rtc_eve
* @brief Function for clearing an event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] event Event to clear.
+ * @param[in] event Event to be cleared.
*/
__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_reg, nrf_rtc_event_t event);
@@ -264,7 +263,7 @@ __STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_reg, nrf_rtc_task_t t
* @brief Function for enabling events.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] mask Mask of event flags to enable.
+ * @param[in] mask Mask of event flags to be enabled.
*/
__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask);
@@ -276,6 +275,15 @@ __STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask);
*/
__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t event);
+/**
+ * @brief Function for getting the COMPARE event associated with the specified compare channel.
+ *
+ * @param[in] index Compare channel index.
+ *
+ * @return Requested COMPARE event.
+ */
+__STATIC_INLINE nrf_rtc_event_t nrf_rtc_compare_event_get(uint8_t index);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
@@ -387,10 +395,17 @@ __STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
p_reg->EVTENSET = mask;
}
+
__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
p_reg->EVTENCLR = mask;
}
+
+__STATIC_INLINE nrf_rtc_event_t nrf_rtc_compare_event_get(uint8_t index)
+{
+ return (nrf_rtc_event_t)NRFX_OFFSETOF(NRF_RTC_Type, EVENTS_COMPARE[index]);
+}
+
#endif
/** @} */
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_saadc.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_saadc.h
index c63bb211e..1bb00f932 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_saadc.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_saadc.h
@@ -45,11 +45,11 @@ extern "C" {
* @brief Hardware access layer for managing the SAADC peripheral.
*/
+/** @brief Number of available SAADC channels. */
#define NRF_SAADC_CHANNEL_COUNT 8
-/**
- * @brief Resolution of the analog-to-digital converter.
- */
+
+/** @brief Resolution of the analog-to-digital converter. */
typedef enum
{
NRF_SAADC_RESOLUTION_8BIT = SAADC_RESOLUTION_VAL_8bit, ///< 8 bit resolution.
@@ -58,10 +58,7 @@ typedef enum
NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit ///< 14 bit resolution.
} nrf_saadc_resolution_t;
-
-/**
- * @brief Input selection for the analog-to-digital converter.
- */
+/** @brief Input selection for the analog-to-digital converter. */
typedef enum
{
NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC, ///< Not connected.
@@ -76,10 +73,7 @@ typedef enum
NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD ///< VDD as input.
} nrf_saadc_input_t;
-
-/**
- * @brief Analog-to-digital converter oversampling mode.
- */
+/** @brief Analog-to-digital converter oversampling mode. */
typedef enum
{
NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass, ///< No oversampling.
@@ -93,10 +87,7 @@ typedef enum
NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x.
} nrf_saadc_oversample_t;
-
-/**
- * @brief Analog-to-digital converter channel resistor control.
- */
+/** @brief Analog-to-digital converter channel resistor control. */
typedef enum
{
NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass, ///< Bypass resistor ladder.
@@ -105,10 +96,7 @@ typedef enum
NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDD1_2 ///< Set input at VDD/2.
} nrf_saadc_resistor_t;
-
-/**
- * @brief Gain factor of the analog-to-digital converter input.
- */
+/** @brief Gain factor of the analog-to-digital converter input. */
typedef enum
{
NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6.
@@ -121,20 +109,14 @@ typedef enum
NRF_SAADC_GAIN4 = SAADC_CH_CONFIG_GAIN_Gain4, ///< Gain factor 4.
} nrf_saadc_gain_t;
-
-/**
- * @brief Reference selection for the analog-to-digital converter.
- */
+/** @brief Reference selection for the analog-to-digital converter. */
typedef enum
{
NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference (0.6 V).
NRF_SAADC_REFERENCE_VDD4 = SAADC_CH_CONFIG_REFSEL_VDD1_4 ///< VDD/4 as reference.
} nrf_saadc_reference_t;
-
-/**
- * @brief Analog-to-digital converter acquisition time.
- */
+/** @brief Analog-to-digital converter acquisition time. */
typedef enum
{
NRF_SAADC_ACQTIME_3US = SAADC_CH_CONFIG_TACQ_3us, ///< 3 us.
@@ -145,43 +127,31 @@ typedef enum
NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us ///< 40 us.
} nrf_saadc_acqtime_t;
-
-/**
- * @brief Analog-to-digital converter channel mode.
- */
+/** @brief Analog-to-digital converter channel mode. */
typedef enum
{
- NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single ended, PSELN will be ignored, negative input to ADC shorted to GND.
+ NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single-ended mode. PSELN will be ignored, negative input to ADC shorted to GND.
NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode.
} nrf_saadc_mode_t;
-
-/**
- * @brief Analog-to-digital converter channel burst mode.
- */
+/** @brief Analog-to-digital converter channel burst mode. */
typedef enum
{
NRF_SAADC_BURST_DISABLED = SAADC_CH_CONFIG_BURST_Disabled, ///< Burst mode is disabled (normal operation).
NRF_SAADC_BURST_ENABLED = SAADC_CH_CONFIG_BURST_Enabled ///< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.
} nrf_saadc_burst_t;
-
-/**
- * @brief Analog-to-digital converter tasks.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief Analog-to-digital converter tasks. */
+typedef enum
{
NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM.
NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled.
- NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any on-going conversion.
+ NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any ongoing conversion.
NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration.
} nrf_saadc_task_t;
-
-/**
- * @brief Analog-to-digital converter events.
- */
-typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+/** @brief Analog-to-digital converter events. */
+typedef enum
{
NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started.
NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer.
@@ -207,10 +177,7 @@ typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW.
} nrf_saadc_event_t;
-
-/**
- * @brief Analog-to-digital converter interrupt masks.
- */
+/** @brief Analog-to-digital converter interrupt masks. */
typedef enum
{
NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
@@ -238,88 +205,81 @@ typedef enum
NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts.
} nrf_saadc_int_mask_t;
-
-/**
- * @brief Analog-to-digital converter value limit type.
- */
+/** @brief Analog-to-digital converter value limit type. */
typedef enum
{
- NRF_SAADC_LIMIT_LOW = 0,
- NRF_SAADC_LIMIT_HIGH = 1
+ NRF_SAADC_LIMIT_LOW = 0, ///< Low limit type.
+ NRF_SAADC_LIMIT_HIGH = 1 ///< High limit type.
} nrf_saadc_limit_t;
+/** @brief Type of a single ADC conversion result. */
+typedef int16_t nrf_saadc_value_t;
-typedef int16_t nrf_saadc_value_t; ///< Type of a single ADC conversion result.
-
-
-/**
- * @brief Analog-to-digital converter configuration structure.
- */
+/** @brief Analog-to-digital converter configuration structure. */
typedef struct
{
- nrf_saadc_resolution_t resolution;
- nrf_saadc_oversample_t oversample;
- nrf_saadc_value_t * buffer;
- uint32_t buffer_size;
+ nrf_saadc_resolution_t resolution; ///< Resolution of samples.
+ nrf_saadc_oversample_t oversample; ///< Oversampling configuration.
+ nrf_saadc_value_t * buffer; ///< Pointer to sample buffer.
+ uint32_t buffer_size; ///< Size of the sample buffer.
} nrf_saadc_config_t;
-
-/**
- * @brief Analog-to-digital converter channel configuration structure.
- */
+/** @brief Analog-to-digital converter channel configuration structure. */
typedef struct
{
- nrf_saadc_resistor_t resistor_p;
- nrf_saadc_resistor_t resistor_n;
- nrf_saadc_gain_t gain;
- nrf_saadc_reference_t reference;
- nrf_saadc_acqtime_t acq_time;
- nrf_saadc_mode_t mode;
- nrf_saadc_burst_t burst;
- nrf_saadc_input_t pin_p;
- nrf_saadc_input_t pin_n;
+ nrf_saadc_resistor_t resistor_p; ///< Resistor value on positive input.
+ nrf_saadc_resistor_t resistor_n; ///< Resistor value on negative input.
+ nrf_saadc_gain_t gain; ///< Gain control value.
+ nrf_saadc_reference_t reference; ///< Reference control value.
+ nrf_saadc_acqtime_t acq_time; ///< Acquisition time.
+ nrf_saadc_mode_t mode; ///< SAADC mode. Single-ended or differential.
+ nrf_saadc_burst_t burst; ///< Burst mode configuration.
+ nrf_saadc_input_t pin_p; ///< Input positive pin selection.
+ nrf_saadc_input_t pin_n; ///< Input negative pin selection.
} nrf_saadc_channel_config_t;
-/**
- * @brief Function for triggering a specific SAADC task.
- *
- * @param[in] saadc_task SAADC task.
- */
-__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task);
/**
- * @brief Function for getting the address of a specific SAADC task register.
+ * @brief Function for triggering the specified SAADC task.
*
- * @param[in] saadc_task SAADC task.
+ * @param[in] task SAADC task.
+ */
+__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t task);
+
+/**
+ * @brief Function for getting the address of the specified SAADC task register.
+ *
+ * @param[in] task SAADC task.
*
* @return Address of the specified SAADC task.
*/
-__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task);
+__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t task);
/**
- * @brief Function for getting the state of a specific SAADC event.
+ * @brief Function for retrieving the state of the UARTE event.
*
- * @param[in] saadc_event SAADC event.
+ * @param[in] event Event to be checked.
*
- * @return State of the specified SAADC event.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event);
+__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t event);
/**
* @brief Function for clearing the specific SAADC event.
*
- * @param[in] saadc_event SAADC event.
+ * @param[in] event SAADC event.
*/
-__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event);
+__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t event);
/**
- * @brief Function for getting the address of a specific SAADC event register.
+ * @brief Function for getting the address of the specified SAADC event register.
*
- * @param[in] saadc_event SAADC event.
+ * @param[in] event SAADC event.
*
* @return Address of the specified SAADC event.
*/
-__STATIC_INLINE uint32_t nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event);
+__STATIC_INLINE uint32_t nrf_saadc_event_address_get(nrf_saadc_event_t event);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
@@ -360,25 +320,30 @@ __STATIC_INLINE void nrf_saadc_publish_clear(nrf_saadc_event_t event);
#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
- * @brief Function for getting the address of a specific SAADC limit event register.
+ * @brief Function for getting the address of the SAADC limit event register,
+ * as specified by the channel and the limit type.
*
- * @param[in] channel Channel number.
+ * @param[in] channel Channel number.
* @param[in] limit_type Low limit or high limit.
*
* @return Address of the specified SAADC limit event.
*/
-__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type);
+__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel,
+ nrf_saadc_limit_t limit_type);
/**
* @brief Function for getting the SAADC channel monitoring limit events.
*
* @param[in] channel Channel number.
* @param[in] limit_type Low limit or high limit.
+ *
+ * @return The SAADC channel monitoring limit event.
*/
-__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type);
+__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel,
+ nrf_saadc_limit_t limit_type);
/**
- * @brief Function for configuring the input pins for a specific SAADC channel.
+ * @brief Function for configuring the input pins for the specified SAADC channel.
*
* @param[in] channel Channel number.
* @param[in] pselp Positive input.
@@ -389,7 +354,7 @@ __STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
nrf_saadc_input_t pseln);
/**
- * @brief Function for configuring the positive input pin for a specific SAADC channel.
+ * @brief Function for configuring the positive input pin for the specified SAADC channel.
*
* @param[in] channel Channel number.
* @param[in] pselp Positive input.
@@ -409,24 +374,24 @@ __STATIC_INLINE void nrf_saadc_channel_limits_set(uint8_t channel, int16_t low,
/**
* @brief Function for enabling specified SAADC interrupts.
*
- * @param[in] saadc_int_mask Interrupt(s) to enable.
+ * @param[in] saadc_int_mask Interrupt(s) to be enabled.
*/
__STATIC_INLINE void nrf_saadc_int_enable(uint32_t saadc_int_mask);
/**
* @brief Function for retrieving the state of specified SAADC interrupts.
*
- * @param[in] saadc_int_mask Interrupt(s) to check.
+ * @param[in] saadc_int_mask Interrupt(s) to be checked.
*
- * @retval true If all specified interrupts are enabled.
- * @retval false If at least one of the given interrupts is not enabled.
+ * @retval true All specified interrupts are enabled.
+ * @retval false At least one of the given interrupts is not enabled.
*/
__STATIC_INLINE bool nrf_saadc_int_enable_check(uint32_t saadc_int_mask);
/**
* @brief Function for disabling specified interrupts.
*
- * @param saadc_int_mask Interrupt(s) to disable.
+ * @param saadc_int_mask Interrupt(s) to be disabled.
*/
__STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask);
@@ -436,7 +401,7 @@ __STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask);
* @param[in] channel SAADC channel number.
* @param[in] limit_type Limit type.
*
- * @returns Interrupt mask.
+ * @return Interrupt mask.
*/
__STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type);
@@ -445,8 +410,8 @@ __STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limi
*
* This function checks whether the analog-to-digital converter is busy with a conversion.
*
- * @retval true If the SAADC is busy.
- * @retval false If the SAADC is not busy.
+ * @retval true The SAADC is busy.
+ * @retval false The SAADC is not busy.
*/
__STATIC_INLINE bool nrf_saadc_busy_check(void);
@@ -465,8 +430,8 @@ __STATIC_INLINE void nrf_saadc_disable(void);
/**
* @brief Function for checking if the SAADC is enabled.
*
- * @retval true If the SAADC is enabled.
- * @retval false If the SAADC is not enabled.
+ * @retval true The SAADC is enabled.
+ * @retval false The SAADC is not enabled.
*/
__STATIC_INLINE bool nrf_saadc_enable_check(void);
@@ -563,33 +528,33 @@ __STATIC_INLINE void nrf_saadc_burst_set(uint8_t channel,
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
-__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task)
+__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t task)
{
- *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task)) = 0x1UL;
+ *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)task)) = 0x1UL;
}
-__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task)
+__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t task)
{
- return (uint32_t)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task);
+ return (uint32_t)((uint8_t *)NRF_SAADC + (uint32_t)task);
}
-__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event)
+__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t event)
{
- return (bool)*(volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
+ return (bool)*(volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)event);
}
-__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event)
+__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t event)
{
- *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)) = 0x0UL;
+ *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)event)) = 0x0UL;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)event));
(void)dummy;
#endif
}
-__STATIC_INLINE uint32_t nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event)
+__STATIC_INLINE uint32_t nrf_saadc_event_address_get(nrf_saadc_event_t event)
{
- return (uint32_t )((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
+ return (uint32_t )((uint8_t *)NRF_SAADC + (uint32_t)event);
}
#if defined(DPPI_PRESENT)
@@ -618,7 +583,8 @@ __STATIC_INLINE void nrf_saadc_publish_clear(nrf_saadc_event_t event)
}
#endif // defined(DPPI_PRESENT)
-__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type)
+__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel,
+ nrf_saadc_limit_t limit_type)
{
NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
if (limit_type == NRF_SAADC_LIMIT_HIGH)
@@ -631,7 +597,8 @@ __STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t ch
}
}
-__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type)
+__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel,
+ nrf_saadc_limit_t limit_type)
{
if (limit_type == NRF_SAADC_LIMIT_HIGH)
{
@@ -647,7 +614,7 @@ __STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf
}
}
-__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
+__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
nrf_saadc_input_t pselp,
nrf_saadc_input_t pseln)
{
@@ -655,7 +622,7 @@ __STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
NRF_SAADC->CH[channel].PSELP = pselp;
}
-__STATIC_INLINE void nrf_saadc_channel_pos_input_set(uint8_t channel,
+__STATIC_INLINE void nrf_saadc_channel_pos_input_set(uint8_t channel,
nrf_saadc_input_t pselp)
{
NRF_SAADC->CH[channel].PSELP = pselp;
@@ -686,7 +653,8 @@ __STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask)
__STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type)
{
NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
- uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ? NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH;
+ uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ?
+ NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH;
return mask << (channel * 2);
}
@@ -776,7 +744,7 @@ __STATIC_INLINE void nrf_saadc_channel_init(uint8_t
nrf_saadc_channel_input_set(channel, config->pin_p, config->pin_n);
}
-__STATIC_INLINE void nrf_saadc_burst_set(uint8_t channel,
+__STATIC_INLINE void nrf_saadc_burst_set(uint8_t channel,
nrf_saadc_burst_t burst)
{
NRF_SAADC->CH[channel].CONFIG =
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_spi.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_spi.h
index 8366deb85..88b6b6b8e 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_spi.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_spi.h
@@ -53,28 +53,20 @@ extern "C" {
#define NRF_SPI_PIN_NOT_CONNECTED 0xFFFFFFFF
-/**
- * @brief SPI events.
- */
+/** @brief SPI events. */
typedef enum
{
- /*lint -save -e30*/
NRF_SPI_EVENT_READY = offsetof(NRF_SPI_Type, EVENTS_READY) ///< TXD byte sent and RXD byte received.
- /*lint -restore*/
} nrf_spi_event_t;
-/**
- * @brief SPI interrupts.
- */
+/** @brief SPI interrupts. */
typedef enum
{
NRF_SPI_INT_READY_MASK = SPI_INTENSET_READY_Msk, ///< Interrupt on READY event.
NRF_SPI_ALL_INTS_MASK = SPI_INTENSET_READY_Msk ///< All SPI interrupts.
} nrf_spi_int_mask_t;
-/**
- * @brief SPI data rates.
- */
+/** @brief SPI data rates. */
typedef enum
{
NRF_SPI_FREQ_125K = SPI_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
@@ -88,9 +80,7 @@ typedef enum
NRF_SPI_FREQ_8M = (int)SPI_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps.
} nrf_spi_frequency_t;
-/**
- * @brief SPI modes.
- */
+/** @brief SPI modes. */
typedef enum
{
NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock.
@@ -99,9 +89,7 @@ typedef enum
NRF_SPI_MODE_3 ///< SCK active low, sample on trailing edge of clock.
} nrf_spi_mode_t;
-/**
- * @brief SPI bit orders.
- */
+/** @brief SPI bit orders. */
typedef enum
{
NRF_SPI_BIT_ORDER_MSB_FIRST = SPI_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
@@ -110,78 +98,78 @@ typedef enum
/**
- * @brief Function for clearing a specific SPI event.
+ * @brief Function for clearing the specified SPI event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spi_event Event to clear.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be cleared.
*/
-__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg,
- nrf_spi_event_t spi_event);
+__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg,
+ nrf_spi_event_t event);
/**
- * @brief Function for checking the state of a specific SPI event.
+ * @brief Function for retrieving the state of the SPI event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spi_event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg,
- nrf_spi_event_t spi_event);
+__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg,
+ nrf_spi_event_t event);
/**
- * @brief Function for getting the address of a specific SPI event register.
+ * @brief Function for getting the address of the specified SPI event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spi_event Requested event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event The specified event.
*
* @return Address of the specified event register.
*/
-__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg,
- nrf_spi_event_t spi_event);
+__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg,
+ nrf_spi_event_t event);
/**
- * @brief Function for enabling specified interrupts.
+ * @brief Function for enabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spi_int_mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg,
- uint32_t spi_int_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified interrupts.
+ * @brief Function for disabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spi_int_mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg,
- uint32_t spi_int_mask);
+ uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spi_int Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] spi_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
-__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg,
+__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg,
nrf_spi_int_mask_t spi_int);
/**
* @brief Function for enabling the SPI peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg);
/**
* @brief Function for disabling the SPI peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg);
@@ -191,20 +179,20 @@ __STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg);
* If a given signal is not needed, pass the @ref NRF_SPI_PIN_NOT_CONNECTED
* value instead of its pin number.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] sck_pin SCK pin number.
- * @param[in] mosi_pin MOSI pin number.
- * @param[in] miso_pin MISO pin number.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] sck_pin SCK pin number.
+ * @param[in] mosi_pin MOSI pin number.
+ * @param[in] miso_pin MISO pin number.
*/
__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg,
- uint32_t sck_pin,
- uint32_t mosi_pin,
- uint32_t miso_pin);
+ uint32_t sck_pin,
+ uint32_t mosi_pin,
+ uint32_t miso_pin);
/**
* @brief Function for writing data to the SPI transmitter register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] data TX data to send.
*/
__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data);
@@ -212,7 +200,7 @@ __STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data);
/**
* @brief Function for reading data from the SPI receiver register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return RX data received.
*/
@@ -221,61 +209,61 @@ __STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg);
/**
* @brief Function for setting the SPI master data rate.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] frequency SPI frequency.
*/
-__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg,
+__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg,
nrf_spi_frequency_t frequency);
/**
* @brief Function for setting the SPI configuration.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] spi_mode SPI mode.
* @param[in] spi_bit_order SPI bit order.
*/
-__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg,
- nrf_spi_mode_t spi_mode,
+__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg,
+ nrf_spi_mode_t spi_mode,
nrf_spi_bit_order_t spi_bit_order);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
-__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg,
- nrf_spi_event_t spi_event)
+__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg,
+ nrf_spi_event_t event)
{
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event)) = 0x0UL;
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
(void)dummy;
#endif
}
-__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg,
- nrf_spi_event_t spi_event)
+__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg,
+ nrf_spi_event_t event)
{
- return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event);
+ return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
-__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg,
- nrf_spi_event_t spi_event)
+__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg,
+ nrf_spi_event_t event)
{
- return (uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event);
+ return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg,
- uint32_t spi_int_mask)
+ uint32_t mask)
{
- p_reg->INTENSET = spi_int_mask;
+ p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg,
- uint32_t spi_int_mask)
+ uint32_t mask)
{
- p_reg->INTENCLR = spi_int_mask;
+ p_reg->INTENCLR = mask;
}
-__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg,
+__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg,
nrf_spi_int_mask_t spi_int)
{
return (bool)(p_reg->INTENSET & spi_int);
@@ -292,9 +280,9 @@ __STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg)
}
__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg,
- uint32_t sck_pin,
- uint32_t mosi_pin,
- uint32_t miso_pin)
+ uint32_t sck_pin,
+ uint32_t mosi_pin,
+ uint32_t miso_pin)
{
#if defined(SPI_PSEL_SCK_CONNECT_Pos)
p_reg->PSEL.SCK = sck_pin;
@@ -325,14 +313,14 @@ __STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg)
return p_reg->RXD;
}
-__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg,
+__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg,
nrf_spi_frequency_t frequency)
{
p_reg->FREQUENCY = frequency;
}
-__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg,
- nrf_spi_mode_t spi_mode,
+__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg,
+ nrf_spi_mode_t spi_mode,
nrf_spi_bit_order_t spi_bit_order)
{
uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ?
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_spim.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_spim.h
index d49cb941b..261f64f0c 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_spim.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_spim.h
@@ -63,37 +63,31 @@ extern "C" {
#define NRF_SPIM_DCX_CNT_ALL_CMD 0xF
#endif
+/** @brief Macro for checking if the hardware chip select function is available. */
#define NRF_SPIM_HW_CSN_PRESENT \
(NRFX_CHECK(SPIM0_FEATURE_HARDWARE_CSN_PRESENT) || \
NRFX_CHECK(SPIM1_FEATURE_HARDWARE_CSN_PRESENT) || \
NRFX_CHECK(SPIM2_FEATURE_HARDWARE_CSN_PRESENT) || \
NRFX_CHECK(SPIM3_FEATURE_HARDWARE_CSN_PRESENT))
-/**
- * @brief SPIM tasks.
- */
+
+/** @brief SPIM tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction.
NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction.
NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction.
NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME) ///< Resume SPI transaction.
- /*lint -restore*/
} nrf_spim_task_t;
-/**
- * @brief SPIM events.
- */
+/** @brief SPIM events. */
typedef enum
{
- /*lint -save -e30*/
NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped.
NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached.
NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END), ///< End of RXD buffer and TXD buffer reached.
NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached.
NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED) ///< Transaction started.
- /*lint -restore*/
} nrf_spim_event_t;
/**
@@ -105,9 +99,7 @@ typedef enum
NRF_SPIM_ALL_SHORTS_MASK = SPIM_SHORTS_END_START_Msk ///< All SPIM shortcuts.
} nrf_spim_short_mask_t;
-/**
- * @brief SPIM interrupts.
- */
+/** @brief SPIM interrupts. */
typedef enum
{
NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
@@ -122,9 +114,7 @@ typedef enum
SPIM_INTENSET_STARTED_Msk ///< All SPIM interrupts.
} nrf_spim_int_mask_t;
-/**
- * @brief SPI master data rates.
- */
+/** @brief SPI master data rates. */
typedef enum
{
NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
@@ -144,9 +134,7 @@ typedef enum
#endif
} nrf_spim_frequency_t;
-/**
- * @brief SPI modes.
- */
+/** @brief SPI modes. */
typedef enum
{
NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
@@ -155,9 +143,7 @@ typedef enum
NRF_SPIM_MODE_3 ///< SCK active low, sample on trailing edge of clock.
} nrf_spim_mode_t;
-/**
- * @brief SPI bit orders.
- */
+/** @brief SPI bit orders. */
typedef enum
{
NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
@@ -165,9 +151,7 @@ typedef enum
} nrf_spim_bit_order_t;
#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief SPI CSN pin polarity.
- */
+/** @brief SPI CSN pin polarity. */
typedef enum
{
NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL_LOW, ///< Active low (idle state high).
@@ -175,110 +159,113 @@ typedef enum
} nrf_spim_csn_pol_t;
#endif // (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
-/**
- * @brief Function for activating a specific SPIM task.
- *
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spim_task Task to activate.
- */
-__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t spim_task);
/**
- * @brief Function for getting the address of a specific SPIM task register.
+ * @brief Function for activating the specified SPIM task.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spim_task Requested task.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
+ */
+__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
+ nrf_spim_task_t task);
+
+/**
+ * @brief Function for getting the address of the specified SPIM task register.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task The specified task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t spim_task);
+ nrf_spim_task_t task);
/**
- * @brief Function for clearing a specific SPIM event.
+ * @brief Function for clearing the specified SPIM event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spim_event Event to clear.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be cleared.
*/
-__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t spim_event);
+__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
+ nrf_spim_event_t event);
/**
- * @brief Function for checking the state of a specific SPIM event.
+ * @brief Function for retrieving the state of the SPIM event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spim_event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t spim_event);
+__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
+ nrf_spim_event_t event);
/**
- * @brief Function for getting the address of a specific SPIM event register.
+ * @brief Function for getting the address of the specified SPIM event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spim_event Requested event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event The specified event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t spim_event);
+ nrf_spim_event_t event);
/**
- * @brief Function for enabling specified shortcuts.
+ * @brief Function for enabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spim_shorts_mask Shortcuts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be enabled.
*/
__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
- uint32_t spim_shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified shortcuts.
+ * @brief Function for disabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spim_shorts_mask Shortcuts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be disabled.
*/
__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
- uint32_t spim_shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for getting shorts setting.
+ * @brief Function for getting the shortcut setting.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Current shortcut configuration.
*/
__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg);
/**
- * @brief Function for enabling specified interrupts.
+ * @brief Function for enabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spim_int_mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
- uint32_t spim_int_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified interrupts.
+ * @brief Function for disabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spim_int_mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
- uint32_t spim_int_mask);
+ uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spim_int Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] spim_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
-__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
+__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
nrf_spim_int_mask_t spim_int);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
@@ -314,7 +301,7 @@ __STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,
*/
__STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg,
nrf_spim_event_t event,
- uint8_t channel);
+ uint8_t channel);
/**
* @brief Function for clearing the publish configuration for a given
@@ -330,14 +317,14 @@ __STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,
/**
* @brief Function for enabling the SPIM peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg);
/**
* @brief Function for disabling the SPIM peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg);
@@ -347,15 +334,15 @@ __STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg);
* If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
* value instead of its pin number.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] sck_pin SCK pin number.
* @param[in] mosi_pin MOSI pin number.
* @param[in] miso_pin MISO pin number.
*/
__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
- uint32_t sck_pin,
- uint32_t mosi_pin,
- uint32_t miso_pin);
+ uint32_t sck_pin,
+ uint32_t mosi_pin,
+ uint32_t miso_pin);
#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
@@ -364,17 +351,17 @@ __STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
* If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
* value instead of its pin number.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] pin CSN pin number.
* @param[in] polarity CSN pin polarity.
* @param[in] duration Minimum duration between the edge of CSN and the edge of SCK
* and minimum duration of CSN must stay unselected between transactions.
* The value is specified in number of 64 MHz clock cycles (15.625 ns).
*/
-__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
- uint32_t pin,
+__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
+ uint32_t pin,
nrf_spim_csn_pol_t polarity,
- uint32_t duration);
+ uint32_t duration);
#endif // (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
#if defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__)
@@ -384,11 +371,11 @@ __STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
* If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
* value instead of its pin number.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] dcx_pin DCX pin number.
*/
__STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
- uint32_t dcx_pin);
+ uint32_t dcx_pin);
/**
* @brief Function for configuring the number of command bytes.
@@ -398,36 +385,37 @@ __STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
* The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the @c count parameter
* causes all transmitted bytes to be marked as command bytes.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] count Number of command bytes preceding the data bytes.
*/
__STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
- uint32_t count);
+ uint32_t count);
#endif // defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__)
#if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for configuring the extended SPIM interface.
- * @param p_reg Pointer to the peripheral registers structure.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
* @param rxdelay Sample delay for input serial data on MISO,
* specified in 64 MHz clock cycles (15.625 ns) from the sampling edge of SCK.
*/
__STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
- uint32_t rxdelay);
+ uint32_t rxdelay);
#endif // defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__)
#if defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for clearing stall status for RX EasyDMA RAM accesses.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg);
/**
* @brief Function for getting stall status for RX EasyDMA RAM accesses.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*
* @return Stall status of RX EasyDMA RAM accesses.
*/
@@ -438,14 +426,14 @@ __STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg);
/**
* @brief Function for clearing stall status for TX EasyDMA RAM accesses.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg);
/**
* @brief Function for getting stall status for TX EasyDMA RAM accesses.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*
* @return Stall status of TX EasyDMA RAM accesses.
*/
@@ -455,16 +443,16 @@ __STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg);
/**
* @brief Function for setting the SPI master data rate.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] frequency SPI frequency.
*/
-__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
+__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
nrf_spim_frequency_t frequency);
/**
* @brief Function for setting the transmit buffer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buffer Pointer to the buffer with data to send.
* @param[in] length Maximum number of data bytes to transmit.
*/
@@ -475,109 +463,110 @@ __STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
/**
* @brief Function for setting the receive buffer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buffer Pointer to the buffer for received data.
* @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
- uint8_t * p_buffer,
- size_t length);
+ uint8_t * p_buffer,
+ size_t length);
/**
* @brief Function for setting the SPI configuration.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] spi_mode SPI mode.
* @param[in] spi_bit_order SPI bit order.
*/
-__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
- nrf_spim_mode_t spi_mode,
+__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
+ nrf_spim_mode_t spi_mode,
nrf_spim_bit_order_t spi_bit_order);
/**
* @brief Function for setting the over-read character.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] orc Over-read character that is clocked out in case of
- * an over-read of the TXD buffer.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] orc Over-read character that is clocked out in case of
+ * an over-read of the TXD buffer.
*/
__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
- uint8_t orc);
+ uint8_t orc);
/**
* @brief Function for enabling the TX list feature.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg);
/**
* @brief Function for disabling the TX list feature.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg);
/**
* @brief Function for enabling the RX list feature.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg);
/**
* @brief Function for disabling the RX list feature.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t spim_task)
+ nrf_spim_task_t task)
{
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_task)) = 0x1UL;
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t spim_task)
+ nrf_spim_task_t task)
{
- return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_task);
+ return (uint32_t)((uint8_t *)p_reg + (uint32_t)task);
}
-__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t spim_event)
+__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
+ nrf_spim_event_t event)
{
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event)) = 0x0UL;
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
(void)dummy;
#endif
}
-__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t spim_event)
+__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
+ nrf_spim_event_t event)
{
- return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event);
+ return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
-__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t spim_event)
+__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg,
+ nrf_spim_event_t event)
{
- return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_event);
+ return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
- uint32_t spim_shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS |= spim_shorts_mask;
+ p_reg->SHORTS |= mask;
}
__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
- uint32_t spim_shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS &= ~(spim_shorts_mask);
+ p_reg->SHORTS &= ~(mask);
}
__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg)
@@ -586,18 +575,18 @@ __STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg)
}
__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
- uint32_t spim_int_mask)
+ uint32_t mask)
{
- p_reg->INTENSET = spim_int_mask;
+ p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
- uint32_t spim_int_mask)
+ uint32_t mask)
{
- p_reg->INTENCLR = spim_int_mask;
+ p_reg->INTENCLR = mask;
}
-__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
+__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
nrf_spim_int_mask_t spim_int)
{
return (bool)(p_reg->INTENSET & spim_int);
@@ -644,9 +633,9 @@ __STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg)
}
__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
- uint32_t sck_pin,
- uint32_t mosi_pin,
- uint32_t miso_pin)
+ uint32_t sck_pin,
+ uint32_t mosi_pin,
+ uint32_t miso_pin)
{
p_reg->PSEL.SCK = sck_pin;
p_reg->PSEL.MOSI = mosi_pin;
@@ -654,10 +643,10 @@ __STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
}
#if (NRF_SPIM_HW_CSN_PRESENT)
-__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
- uint32_t pin,
+__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
+ uint32_t pin,
nrf_spim_csn_pol_t polarity,
- uint32_t duration)
+ uint32_t duration)
{
p_reg->PSEL.CSN = pin;
p_reg->CSNPOL = polarity;
@@ -667,13 +656,13 @@ __STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
#if defined(SPIM_PSELDCX_CONNECT_Msk)
__STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
- uint32_t dcx_pin)
+ uint32_t dcx_pin)
{
p_reg->PSELDCX = dcx_pin;
}
__STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
- uint32_t dcx_cnt)
+ uint32_t dcx_cnt)
{
p_reg->DCXCNT = dcx_cnt;
}
@@ -681,7 +670,7 @@ __STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
#if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk)
__STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
- uint32_t rxdelay)
+ uint32_t rxdelay)
{
p_reg->IFTIMING.RXDELAY = rxdelay;
}
@@ -711,10 +700,10 @@ __STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg)
}
#endif // defined(SPIM_STALLSTAT_TX_Msk)
-__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
+__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
nrf_spim_frequency_t frequency)
{
- p_reg->FREQUENCY = frequency;
+ p_reg->FREQUENCY = (uint32_t)frequency;
}
__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
@@ -733,8 +722,8 @@ __STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
p_reg->RXD.MAXCNT = length;
}
-__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
- nrf_spim_mode_t spi_mode,
+__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
+ nrf_spim_mode_t spi_mode,
nrf_spim_bit_order_t spi_bit_order)
{
uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
@@ -766,7 +755,7 @@ __STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
}
__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
- uint8_t orc)
+ uint8_t orc)
{
p_reg->ORC = orc;
}
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_spis.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_spis.h
index 5896bb263..c9578a6f6 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_spis.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_spis.h
@@ -53,48 +53,34 @@ extern "C" {
#define NRF_SPIS_PIN_NOT_CONNECTED 0xFFFFFFFF
-/**
- * @brief SPIS tasks.
- */
+/** @brief SPIS tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore.
NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it.
- /*lint -restore*/
} nrf_spis_task_t;
-/**
- * @brief SPIS events.
- */
+/** @brief SPIS events. */
typedef enum
{
- /*lint -save -e30*/
NRF_SPIS_EVENT_END = offsetof(NRF_SPIS_Type, EVENTS_END), ///< Granted transaction completed.
NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired.
- /*lint -restore*/
} nrf_spis_event_t;
-/**
- * @brief SPIS shortcuts.
- */
+/** @brief SPIS shortcuts. */
typedef enum
{
NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk ///< Shortcut between END event and ACQUIRE task.
} nrf_spis_short_mask_t;
-/**
- * @brief SPIS interrupts.
- */
+/** @brief SPIS interrupts. */
typedef enum
{
NRF_SPIS_INT_END_MASK = SPIS_INTENSET_END_Msk, ///< Interrupt on END event.
NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk ///< Interrupt on ACQUIRED event.
} nrf_spis_int_mask_t;
-/**
- * @brief SPI modes.
- */
+/** @brief SPI modes. */
typedef enum
{
NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock.
@@ -103,18 +89,14 @@ typedef enum
NRF_SPIS_MODE_3 ///< SCK active low, sample on trailing edge of clock.
} nrf_spis_mode_t;
-/**
- * @brief SPI bit orders.
- */
+/** @brief SPI bit orders. */
typedef enum
{
NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
} nrf_spis_bit_order_t;
-/**
- * @brief SPI semaphore status.
- */
+/** @brief SPI semaphore status. */
typedef enum
{
NRF_SPIS_SEMSTAT_FREE = 0, ///< Semaphore is free.
@@ -123,114 +105,113 @@ typedef enum
NRF_SPIS_SEMSTAT_CPUPENDING = 3 ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending.
} nrf_spis_semstat_t;
-/**
- * @brief SPIS status.
- */
+/** @brief SPIS status. */
typedef enum
{
NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented.
NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk ///< RX buffer overflow detected and prevented.
} nrf_spis_status_mask_t;
-/**
- * @brief Function for activating a specific SPIS task.
- *
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spis_task Task to activate.
- */
-__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
- nrf_spis_task_t spis_task);
/**
- * @brief Function for getting the address of a specific SPIS task register.
+ * @brief Function for activating the specified SPIS task.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spis_task Requested task.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
+ */
+__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
+ nrf_spis_task_t task);
+
+/**
+ * @brief Function for getting the address of the specified SPIS task register.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task The specified task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
- nrf_spis_task_t spis_task);
+ nrf_spis_task_t task);
/**
- * @brief Function for clearing a specific SPIS event.
+ * @brief Function for clearing the specified SPIS event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spis_event Event to clear.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be cleared.
*/
-__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
- nrf_spis_event_t spis_event);
+__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
+ nrf_spis_event_t event);
/**
- * @brief Function for checking the state of a specific SPIS event.
+ * @brief Function for retrieving the state of the SPIS event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spis_event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
- nrf_spis_event_t spis_event);
+ nrf_spis_event_t event);
/**
- * @brief Function for getting the address of a specific SPIS event register.
+ * @brief Function for getting the address of the specified SPIS event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spis_event Requested event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event The specified event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
- nrf_spis_event_t spis_event);
+ nrf_spis_event_t event);
/**
- * @brief Function for enabling specified shortcuts.
+ * @brief Function for enabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spis_shorts_mask Shortcuts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be enabled.
*/
__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
- uint32_t spis_shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified shortcuts.
+ * @brief Function for disabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spis_shorts_mask Shortcuts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be disabled.
*/
__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
- uint32_t spis_shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for enabling specified interrupts.
+ * @brief Function for enabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spis_int_mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
- uint32_t spis_int_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified interrupts.
+ * @brief Function for disabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spis_int_mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
- uint32_t spis_int_mask);
+ uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spis_int Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] spis_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,
- nrf_spis_int_mask_t spis_int);
+ nrf_spis_int_mask_t spis_int);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
@@ -281,21 +262,21 @@ __STATIC_INLINE void nrf_spis_publish_clear(NRF_SPIS_Type * p_reg,
/**
* @brief Function for enabling the SPIS peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg);
/**
* @brief Function for disabling the SPIS peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg);
/**
* @brief Function for retrieving the SPIS semaphore status.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @returns Current semaphore status.
*/
@@ -304,7 +285,7 @@ __STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type *
/**
* @brief Function for retrieving the SPIS status.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @returns Current SPIS status.
*/
@@ -316,24 +297,24 @@ __STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg
* If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED
* value instead of its pin number.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] sck_pin SCK pin number.
- * @param[in] mosi_pin MOSI pin number.
- * @param[in] miso_pin MISO pin number.
- * @param[in] csn_pin CSN pin number.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] sck_pin SCK pin number.
+ * @param[in] mosi_pin MOSI pin number.
+ * @param[in] miso_pin MISO pin number.
+ * @param[in] csn_pin CSN pin number.
*/
__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
- uint32_t sck_pin,
- uint32_t mosi_pin,
- uint32_t miso_pin,
- uint32_t csn_pin);
+ uint32_t sck_pin,
+ uint32_t mosi_pin,
+ uint32_t miso_pin,
+ uint32_t csn_pin);
/**
* @brief Function for setting the transmit buffer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] p_buffer Pointer to the buffer that contains the data to send.
- * @param[in] length Maximum number of data bytes to transmit.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_buffer Pointer to the buffer that contains the data to send.
+ * @param[in] length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
uint8_t const * p_buffer,
@@ -342,19 +323,19 @@ __STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
/**
* @brief Function for setting the receive buffer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buffer Pointer to the buffer for received data.
* @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
- uint8_t * p_buffer,
- size_t length);
+ uint8_t * p_buffer,
+ size_t length);
/**
* @brief Function for getting the number of bytes transmitted
* in the last granted transaction.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @returns Number of bytes transmitted.
*/
@@ -364,7 +345,7 @@ __STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg);
* @brief Function for getting the number of bytes received
* in the last granted transaction.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @returns Number of bytes received.
*/
@@ -373,97 +354,97 @@ __STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg);
/**
* @brief Function for setting the SPI configuration.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] spi_mode SPI mode.
* @param[in] spi_bit_order SPI bit order.
*/
-__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
- nrf_spis_mode_t spi_mode,
+__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
+ nrf_spis_mode_t spi_mode,
nrf_spis_bit_order_t spi_bit_order);
/**
* @brief Function for setting the default character.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] def Default character that is clocked out in case of
- * an overflow of the RXD buffer.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] def Default character that is clocked out in case of
+ * an overflow of the RXD buffer.
*/
__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
- uint8_t def);
+ uint8_t def);
/**
* @brief Function for setting the over-read character.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] orc Over-read character that is clocked out in case of
- * an over-read of the TXD buffer.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] orc Over-read character that is clocked out in case of
+ * an over-read of the TXD buffer.
*/
__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
- uint8_t orc);
+ uint8_t orc);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
- nrf_spis_task_t spis_task)
+ nrf_spis_task_t task)
{
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_task)) = 0x1UL;
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
- nrf_spis_task_t spis_task)
+ nrf_spis_task_t task)
{
- return (uint32_t)p_reg + (uint32_t)spis_task;
+ return (uint32_t)p_reg + (uint32_t)task;
}
__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
- nrf_spis_event_t spis_event)
+ nrf_spis_event_t event)
{
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event)) = 0x0UL;
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event));
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
(void)dummy;
#endif
}
__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
- nrf_spis_event_t spis_event)
+ nrf_spis_event_t event)
{
- return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event);
+ return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
- nrf_spis_event_t spis_event)
+ nrf_spis_event_t event)
{
- return (uint32_t)p_reg + (uint32_t)spis_event;
+ return (uint32_t)p_reg + (uint32_t)event;
}
__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
- uint32_t spis_shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS |= spis_shorts_mask;
+ p_reg->SHORTS |= mask;
}
__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
- uint32_t spis_shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS &= ~(spis_shorts_mask);
+ p_reg->SHORTS &= ~(mask);
}
__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
- uint32_t spis_int_mask)
+ uint32_t mask)
{
- p_reg->INTENSET = spis_int_mask;
+ p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
- uint32_t spis_int_mask)
+ uint32_t mask)
{
- p_reg->INTENCLR = spis_int_mask;
+ p_reg->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,
- nrf_spis_int_mask_t spis_int)
+ nrf_spis_int_mask_t spis_int)
{
return (bool)(p_reg->INTENSET & spis_int);
}
@@ -471,7 +452,7 @@ __STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,
#if defined(DPPI_PRESENT)
__STATIC_INLINE void nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg,
nrf_spis_task_t task,
- uint8_t channel)
+ uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
((uint32_t)channel | SPIS_SUBSCRIBE_ACQUIRE_EN_Msk);
@@ -485,7 +466,7 @@ __STATIC_INLINE void nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg,
__STATIC_INLINE void nrf_spis_publish_set(NRF_SPIS_Type * p_reg,
nrf_spis_event_t event,
- uint8_t channel)
+ uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
((uint32_t)channel | SPIS_PUBLISH_END_EN_Msk);
@@ -520,10 +501,10 @@ __STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg
}
__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
- uint32_t sck_pin,
- uint32_t mosi_pin,
- uint32_t miso_pin,
- uint32_t csn_pin)
+ uint32_t sck_pin,
+ uint32_t mosi_pin,
+ uint32_t miso_pin,
+ uint32_t csn_pin)
{
#if defined (NRF51)
p_reg->PSELSCK = sck_pin;
@@ -552,8 +533,8 @@ __STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
}
__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
- uint8_t * p_buffer,
- size_t length)
+ uint8_t * p_buffer,
+ size_t length)
{
#if defined (NRF51)
p_reg->RXDPTR = (uint32_t)p_buffer;
@@ -582,8 +563,8 @@ __STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg)
#endif
}
-__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
- nrf_spis_mode_t spi_mode,
+__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
+ nrf_spis_mode_t spi_mode,
nrf_spis_bit_order_t spi_bit_order)
{
uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ?
@@ -616,13 +597,13 @@ __STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
}
__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
- uint8_t orc)
+ uint8_t orc)
{
p_reg->ORC = orc;
}
__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
- uint8_t def)
+ uint8_t def)
{
p_reg->DEF = def;
}
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_spu.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_spu.h
index e188e076d..823dedbbb 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_spu.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_spu.h
@@ -86,20 +86,20 @@ typedef enum
/**
* @brief Function for clearing a specific SPU event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_spu_event_clear(NRF_SPU_Type * p_reg,
nrf_spu_event_t event);
/**
- * @brief Function for checking the state of a specific SPU event.
+ * @brief Function for retrieving the state of the SPU event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_spu_event_check(NRF_SPU_Type const * p_reg,
nrf_spu_event_t event);
@@ -107,8 +107,8 @@ __STATIC_INLINE bool nrf_spu_event_check(NRF_SPU_Type const * p_reg,
/**
* @brief Function for enabling specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Interrupts to be enabled.
*/
__STATIC_INLINE void nrf_spu_int_enable(NRF_SPU_Type * p_reg,
uint32_t mask);
@@ -116,8 +116,8 @@ __STATIC_INLINE void nrf_spu_int_enable(NRF_SPU_Type * p_reg,
/**
* @brief Function for disabling specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Interrupts to be disabled.
*/
__STATIC_INLINE void nrf_spu_int_disable(NRF_SPU_Type * p_reg,
uint32_t mask);
@@ -125,11 +125,11 @@ __STATIC_INLINE void nrf_spu_int_disable(NRF_SPU_Type * p_reg,
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] spu_int Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] spu_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg,
uint32_t spu_int);
@@ -137,7 +137,7 @@ __STATIC_INLINE bool nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg,
/**
* @brief Function for setting up publication configuration of a given SPU event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to configure.
* @param[in] channel Channel to connect with published event.
*/
@@ -148,7 +148,7 @@ __STATIC_INLINE void nrf_spu_publish_set(NRF_SPU_Type * p_reg,
/**
* @brief Function for clearing publication configuration of a given SPU event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_spu_publish_clear(NRF_SPU_Type * p_reg,
@@ -157,10 +157,10 @@ __STATIC_INLINE void nrf_spu_publish_clear(NRF_SPU_Type * p_reg,
/**
* @brief Function for retrieving the capabilities of the current device.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @retval true If ARM TrustZone support is available.
- * @retval false If ARM TrustZone support is not available.
+ * @retval true ARM TrustZone support is available.
+ * @retval false ARM TrustZone support is not available.
*/
__STATIC_INLINE bool nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg);
@@ -170,7 +170,7 @@ __STATIC_INLINE bool nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg);
* Channels are configured as bitmask. Set one in bitmask to make channels available only in secure
* domain. Set zero to make it available in secure and non-secure domains.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] dppi_id DPPI peripheral id.
* @param[in] channels_mask Bitmask with channels configuration.
* @param[in] lock_conf Lock configuration until next SoC reset.
@@ -186,7 +186,7 @@ __STATIC_INLINE void nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,
* GPIO pins are configured as bitmask. Set one in bitmask to make particular pin available only
* in secure domain. Set zero to make it available in secure and non-secure domains.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] gpio_port Port number.
* @param[in] gpio_mask Bitmask with gpio configuration.
* @param[in] lock_conf Lock configuration until next SoC reset.
@@ -199,7 +199,7 @@ __STATIC_INLINE void nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,
/**
* @brief Function for configuring non-secure callable flash region.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] flash_nsc_id Non-secure callable flash region ID.
* @param[in] flash_nsc_size Non-secure callable flash region size.
* @param[in] region_number Flash region number.
@@ -214,7 +214,7 @@ __STATIC_INLINE void nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,
/**
* @brief Function for configuring non-secure callable RAM region.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] ram_nsc_id Non-secure callable RAM region ID.
* @param[in] ram_nsc_size Non-secure callable RAM region size.
* @param[in] region_number RAM region number.
@@ -231,7 +231,7 @@ __STATIC_INLINE void nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,
*
* Permissions parameter must be set by using the logical OR on the @ref nrf_spu_mem_perm_t values.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] region_id Flash region index.
* @param[in] secure_attr Set region attribute to secure.
* @param[in] permissions Flash region permissions.
@@ -248,7 +248,7 @@ __STATIC_INLINE void nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,
*
* Permissions parameter must be set by using the logical OR on the @ref nrf_spu_mem_perm_t values.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] region_id RAM region index.
* @param[in] secure_attr Set region attribute to secure.
* @param[in] permissions RAM region permissions.
@@ -263,7 +263,7 @@ __STATIC_INLINE void nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,
/**
* @brief Function for configuring access permissions of the peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] peripheral_id ID number of a particular peripheral.
* @param[in] secure_attr Peripheral registers accessible only from secure domain.
* @param[in] secure_dma DMA transfers possible only from RAM memory in secure domain.
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_systick.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_systick.h
index d99e6145e..9b13858d1 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_systick.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_systick.h
@@ -42,18 +42,18 @@ extern "C" {
* @defgroup nrf_systick_hal SYSTICK HAL
* @{
* @ingroup nrf_systick
- * @brief Hardware access layer for managing the SYSTICK peripheral.
+ * @brief Hardware access layer (HAL) for managing the SYSTICK peripheral.
*
- * SYSTICK is ARM peripheral, not Nordic design.
- * It means that it has no Nordic-typical interface with Tasks and Events.
+ * SYSTICK is a peripheral designed by ARM.
+ * This means that it does not feature the typical Nordic interface with Tasks and Events.
*
- * Its usage is limited here to implement simple delays.
- * Also keep in mind that this timer would be stopped when CPU is sleeping
+ * Its usage is limited here to the implementation of simple delays.
+ * Moreover, keep in mind that this timer will be stopped when CPU is sleeping
* (WFE/WFI instruction is successfully executed).
*/
/**
- * @brief Mask of usable bits in the SysTick value
+ * @brief Mask of usable bits in the SysTick value.
*/
#define NRF_SYSTICK_VAL_MASK SysTick_VAL_CURRENT_Msk
@@ -80,36 +80,36 @@ typedef enum {
} nrf_systick_csr_flags_t;
/**
- * @brief Get Configuration and Status Register
+ * @brief Function for getting Configuration and Status Register.
*
- * @return Values composed by @ref nrf_systick_csr_flags_t.
* @note The @ref NRF_SYSTICK_CSR_COUNTFLAG_MASK value is cleared when CSR register is read.
+ * @return Values composed by @ref nrf_systick_csr_flags_t.
*/
__STATIC_INLINE uint32_t nrf_systick_csr_get(void);
/**
- * @brief Set Configuration and Status Register
+ * @brief Function for setting Configuration and Status Register.
*
* @param[in] val The value composed from @ref nrf_systick_csr_flags_t.
*/
__STATIC_INLINE void nrf_systick_csr_set(uint32_t val);
/**
- * @brief Get the current reload value.
+ * @brief Function for getting the current reload value.
*
* @return The reload register value.
*/
__STATIC_INLINE uint32_t nrf_systick_load_get(void);
/**
- * @brief Configure the reload value.
+ * @brief Function for configuring the reload value.
*
- * @param[in] val The value to set in the reload register.
+ * @param[in] val The value to be set in the reload register.
*/
__STATIC_INLINE void nrf_systick_load_set(uint32_t val);
/**
- * @brief Read the SysTick current value
+ * @brief Function for reading the SysTick current value.
*
* @return The current SysTick value
* @sa NRF_SYSTICK_VAL_MASK
@@ -117,7 +117,7 @@ __STATIC_INLINE void nrf_systick_load_set(uint32_t val);
__STATIC_INLINE uint32_t nrf_systick_val_get(void);
/**
- * @brief Clear the SysTick current value
+ * @brief Function for clearing the SysTick current value.
*
* @note The SysTick does not allow setting current value.
* Any write to VAL register would clear the timer.
@@ -125,14 +125,13 @@ __STATIC_INLINE uint32_t nrf_systick_val_get(void);
__STATIC_INLINE void nrf_systick_val_clear(void);
/**
- * @brief Read the calibration register
+ * @brief Function for reading the calibration register.
*
- * @return The calibration register value
+ * @return The calibration register value.
*/
__STATIC_INLINE uint32_t nrf_systick_calib_get(void);
-
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE uint32_t nrf_systick_csr_get(void)
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_temp.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_temp.h
index c39c2e0b3..2fcc699ba 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_temp.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_temp.h
@@ -39,17 +39,20 @@ extern "C" {
#endif
/**
-* @defgroup nrf_temp_hal TEMP HAL
+* @defgroup nrf_temp_hal_deprecated TEMP HAL (deprecated)
* @{
-* @ingroup nrf_temp temperature_example
+* @ingroup nrf_temp
* @brief Temperature module init and read functions.
*/
+/** @brief Workaround specific define - sign mask.*/
#define MASK_SIGN (0x00000200UL)
+
+/** @brief Workaround specific define - sign extension mask.*/
#define MASK_SIGN_EXTENSION (0xFFFFFC00UL)
/**
- * @brief Function for preparing the temp module for temperature measurement.
+ * @brief Function for preparing the TEMP module for temperature measurement.
*
* This function initializes the TEMP module and writes to the hidden configuration register.
*/
@@ -62,18 +65,201 @@ static __INLINE void nrf_temp_init(void)
/**
* @brief Function for reading temperature measurement.
*
- * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value.
+ * The function reads the 10-bit 2's complement value and transforms it to a 32-bit 2's complement value.
*/
static __INLINE int32_t nrf_temp_read(void)
{
/**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */
- return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (int32_t)(NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP);
+ return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ?
+ (int32_t)(NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP);
}
/** @} */
+/**
+* @defgroup nrf_temp_hal TEMP HAL
+* @{
+* @ingroup nrf_temp
+* @brief Hardware access layer for managing the Temperature sensor (TEMP).
+*/
+
+/** @brief TEMP tasks. */
+typedef enum
+{
+ NRF_TEMP_TASK_START = offsetof(NRF_TEMP_Type, TASKS_START), /**< Start temperature measurement. */
+ NRF_TEMP_TASK_STOP = offsetof(NRF_TEMP_Type, TASKS_STOP) /**< Stop temperature measurement. */
+} nrf_temp_task_t;
+
+/** @brief TEMP events. */
+typedef enum
+{
+ NRF_TEMP_EVENT_DATARDY = offsetof(NRF_TEMP_Type, EVENTS_DATARDY) /**< Temperature measurement complete, data ready. */
+} nrf_temp_event_t;
+
+/** @brief TEMP interrupts. */
+typedef enum
+{
+ NRF_TEMP_INT_DATARDY_MASK = TEMP_INTENSET_DATARDY_Msk /**< Interrupt on DATARDY event. */
+} nrf_temp_int_mask_t;
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
+ */
+__STATIC_INLINE void nrf_temp_int_enable(NRF_TEMP_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
+ */
+__STATIC_INLINE void nrf_temp_int_disable(NRF_TEMP_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] temp_int Interrupt to be checked.
+ *
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_temp_int_enable_check(NRF_TEMP_Type const * p_reg,
+ nrf_temp_int_mask_t temp_int);
+
+/**
+ * @brief Function for getting the address of the specified TEMP task register.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Requested task.
+ *
+ * @return Address of the requested task register.
+ */
+__STATIC_INLINE uint32_t nrf_temp_task_address_get(NRF_TEMP_Type const * p_reg,
+ nrf_temp_task_t task);
+
+/**
+ * @brief Function for activating the specified TEMP task.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
+ */
+__STATIC_INLINE void nrf_temp_task_trigger(NRF_TEMP_Type * p_reg, nrf_temp_task_t task);
+
+/**
+ * @brief Function for getting the address of the specified TEMP event register.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Requested event.
+ *
+ * @return Address of the requested event register.
+ */
+__STATIC_INLINE uint32_t nrf_temp_event_address_get(NRF_TEMP_Type const * p_reg,
+ nrf_temp_event_t event);
+
+/**
+ * @brief Function for clearing the specified TEMP event.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to clear.
+ */
+__STATIC_INLINE void nrf_temp_event_clear(NRF_TEMP_Type * p_reg, nrf_temp_event_t event);
+
+/**
+ * @brief Function for getting the state of a specific event.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
+ *
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
+ */
+__STATIC_INLINE bool nrf_temp_event_check(NRF_TEMP_Type const * p_reg, nrf_temp_event_t event);
+
+/**
+ * @brief Function for getting the result of temperature measurement.
+ *
+ * @note Returned value is in 2's complement format, 0.25 °C steps
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Temperature value register contents.
+ */
+__STATIC_INLINE int32_t nrf_temp_result_get(NRF_TEMP_Type const * p_reg);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_temp_int_enable(NRF_TEMP_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTENSET = mask;
+}
+
+__STATIC_INLINE void nrf_temp_int_disable(NRF_TEMP_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTENCLR = mask;
+}
+
+__STATIC_INLINE bool nrf_temp_int_enable_check(NRF_TEMP_Type const * p_reg,
+ nrf_temp_int_mask_t temp_int)
+{
+ return (bool)(p_reg->INTENSET & temp_int);
+}
+
+__STATIC_INLINE uint32_t nrf_temp_task_address_get(NRF_TEMP_Type const * p_reg,
+ nrf_temp_task_t task)
+{
+ return (uint32_t)((uint8_t *)p_reg + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_temp_task_trigger(NRF_TEMP_Type * p_reg, nrf_temp_task_t task)
+{
+ *(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task) = 1;
+}
+
+__STATIC_INLINE uint32_t nrf_temp_event_address_get(NRF_TEMP_Type const * p_reg,
+ nrf_temp_event_t event)
+{
+ return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_temp_event_clear(NRF_TEMP_Type * p_reg, nrf_temp_event_t event)
+{
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
+#if __CORTEX_M == 0x04
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+ (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_temp_event_check(NRF_TEMP_Type const * p_reg, nrf_temp_event_t event)
+{
+ return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+}
+
+__STATIC_INLINE int32_t nrf_temp_result_get(NRF_TEMP_Type const * p_reg)
+{
+ int32_t raw_measurement = p_reg->TEMP;
+
+#if defined(NRF51)
+ /* Apply workaround for the nRF51 series anomaly 28 - TEMP: Negative measured values are not represented correctly. */
+ if ((raw_measurement & 0x00000200) != 0)
+ {
+ raw_measurement |= 0xFFFFFC00UL;
+ }
+#endif
+
+ return raw_measurement;
+}
+
+#endif
+
+/** @} */
+
#ifdef __cplusplus
}
#endif
-#endif
+#endif // NRF_TEMP_H__
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_timer.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_timer.h
index 7f2e7bc09..477bb3aad 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_timer.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_timer.h
@@ -46,11 +46,23 @@ extern "C" {
*/
/**
- * @brief Macro for validating the correctness of the BIT_WIDTH setting.
+ * @brief Macro for getting the maximum bit resolution of the specified timer instance.
+ *
+ * @param[in] id Index of the specified timer instance.
+ *
+ * @retval Maximum bit resolution of the specified timer instance.
*/
-
#define TIMER_MAX_SIZE(id) NRFX_CONCAT_3(TIMER, id, _MAX_SIZE)
+/**
+ * @brief Macro for validating the correctness of the bit width resolution setting.
+ *
+ * @param[in] id Index of the specified timer instance.
+ * @param[in] bit_width Bit width resolution value to be checked.
+ *
+ * @retval true Timer instance supports the specified bit width resolution value.
+ * @retval false Timer instance does not support the specified bit width resolution value.
+ */
#define TIMER_BIT_WIDTH_MAX(id, bit_width) \
(TIMER_MAX_SIZE(id) == 8 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) : \
(TIMER_MAX_SIZE(id) == 16 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \
@@ -64,7 +76,16 @@ extern "C" {
(bit_width == NRF_TIMER_BIT_WIDTH_32) : \
false))))
-#if TIMER_COUNT > 3
+#if (TIMER_COUNT > 3) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Macro for checking correctness of bit width configuration for the specified timer.
+ *
+ * @param[in] p_reg Timer instance register.
+ * @param[in] bit_width Bit width resolution value to be checked.
+ *
+ * @retval true Timer instance supports the specified bit width resolution value.
+ * @retval false Timer instance does not support the specified bit width resolution value.
+ */
#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
((p_reg == NRF_TIMER0) && (TIMER_BIT_WIDTH_MAX(0, bit_width))) \
|| ((p_reg == NRF_TIMER1) && (TIMER_BIT_WIDTH_MAX(1, bit_width))) \
@@ -83,15 +104,15 @@ extern "C" {
/**
* @brief Macro for getting the number of capture/compare channels available
* in a given timer instance.
+ *
+ * @param[in] id Index of the specified timer instance.
*/
#define NRF_TIMER_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(TIMER, id, _CC_NUM)
-/**
- * @brief Timer tasks.
- */
+
+/** @brief Timer tasks. */
typedef enum
{
- /*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_TIMER_TASK_START = offsetof(NRF_TIMER_Type, TASKS_START), ///< Task for starting the timer.
NRF_TIMER_TASK_STOP = offsetof(NRF_TIMER_Type, TASKS_STOP), ///< Task for stopping the timer.
NRF_TIMER_TASK_COUNT = offsetof(NRF_TIMER_Type, TASKS_COUNT), ///< Task for incrementing the timer (in counter mode).
@@ -107,15 +128,11 @@ typedef enum
#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5.
#endif
- /*lint -restore*/
} nrf_timer_task_t;
-/**
- * @brief Timer events.
- */
+/** @brief Timer events. */
typedef enum
{
- /*lint -save -e30*/
NRF_TIMER_EVENT_COMPARE0 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[0]), ///< Event from compare channel 0.
NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1.
NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2.
@@ -126,12 +143,9 @@ typedef enum
#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5.
#endif
- /*lint -restore*/
} nrf_timer_event_t;
-/**
- * @brief Types of timer shortcuts.
- */
+/** @brief Types of timer shortcuts. */
typedef enum
{
NRF_TIMER_SHORT_COMPARE0_STOP_MASK = TIMER_SHORTS_COMPARE0_STOP_Msk, ///< Shortcut for stopping the timer based on compare 0.
@@ -156,9 +170,7 @@ typedef enum
#endif
} nrf_timer_short_mask_t;
-/**
- * @brief Timer modes.
- */
+/** @brief Timer modes. */
typedef enum
{
NRF_TIMER_MODE_TIMER = TIMER_MODE_MODE_Timer, ///< Timer mode: timer.
@@ -168,9 +180,7 @@ typedef enum
#endif
} nrf_timer_mode_t;
-/**
- * @brief Timer bit width.
- */
+/** @brief Timer bit width. */
typedef enum
{
NRF_TIMER_BIT_WIDTH_8 = TIMER_BITMODE_BITMODE_08Bit, ///< Timer bit width 8 bit.
@@ -179,9 +189,7 @@ typedef enum
NRF_TIMER_BIT_WIDTH_32 = TIMER_BITMODE_BITMODE_32Bit ///< Timer bit width 32 bit.
} nrf_timer_bit_width_t;
-/**
- * @brief Timer prescalers.
- */
+/** @brief Timer prescalers. */
typedef enum
{
NRF_TIMER_FREQ_16MHz = 0, ///< Timer frequency 16 MHz.
@@ -196,9 +204,7 @@ typedef enum
NRF_TIMER_FREQ_31250Hz ///< Timer frequency 31250 Hz.
} nrf_timer_frequency_t;
-/**
- * @brief Timer capture/compare channels.
- */
+/** @brief Timer capture/compare channels. */
typedef enum
{
NRF_TIMER_CC_CHANNEL0 = 0, ///< Timer capture/compare channel 0.
@@ -213,9 +219,7 @@ typedef enum
#endif
} nrf_timer_cc_channel_t;
-/**
- * @brief Timer interrupts.
- */
+/** @brief Timer interrupts. */
typedef enum
{
NRF_TIMER_INT_COMPARE0_MASK = TIMER_INTENSET_COMPARE0_Msk, ///< Timer interrupt from compare event on channel 0.
@@ -232,19 +236,19 @@ typedef enum
/**
- * @brief Function for activating a specific timer task.
+ * @brief Function for activating the specified timer task.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] task Task to activate.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg,
nrf_timer_task_t task);
/**
- * @brief Function for getting the address of a specific timer task register.
+ * @brief Function for getting the address of the specified timer task register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] task Requested task.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task The specified task.
*
* @return Address of the specified task register.
*/
@@ -252,84 +256,84 @@ __STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg,
nrf_timer_task_t task);
/**
- * @brief Function for clearing a specific timer event.
+ * @brief Function for clearing the specified timer event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to clear.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to clear.
*/
-__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg,
+__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg,
nrf_timer_event_t event);
/**
- * @brief Function for checking the state of a specific timer event.
+ * @brief Function for retrieving the state of the TIMER event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg,
+__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg,
nrf_timer_event_t event);
/**
- * @brief Function for getting the address of a specific timer event register.
+ * @brief Function for getting the address of the specified timer event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Requested event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event The specified event.
*
* @return Address of the specified event register.
*/
-__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg,
+__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg,
nrf_timer_event_t event);
/**
- * @brief Function for enabling specified shortcuts.
+ * @brief Function for enabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] timer_shorts_mask Shortcuts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be enabled.
*/
__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg,
- uint32_t timer_shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified shortcuts.
+ * @brief Function for disabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] timer_shorts_mask Shortcuts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be disabled.
*/
__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg,
- uint32_t timer_shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for enabling specified interrupts.
+ * @brief Function for enabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] timer_int_mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg,
- uint32_t timer_int_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified interrupts.
+ * @brief Function for disabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] timer_int_mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg,
- uint32_t timer_int_mask);
+ uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] timer_int Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] timer_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg,
- uint32_t timer_int);
+ uint32_t timer_int);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
@@ -380,8 +384,8 @@ __STATIC_INLINE void nrf_timer_publish_clear(NRF_TIMER_Type * p_reg,
/**
* @brief Function for setting the timer mode.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] mode Timer mode.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mode Timer mode.
*/
__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg,
nrf_timer_mode_t mode);
@@ -389,7 +393,7 @@ __STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg,
/**
* @brief Function for retrieving the timer mode.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Timer mode.
*/
@@ -398,16 +402,16 @@ __STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg);
/**
* @brief Function for setting the timer bit width.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] bit_width Timer bit width.
*/
-__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg,
+__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg,
nrf_timer_bit_width_t bit_width);
/**
* @brief Function for retrieving the timer bit width.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Timer bit width.
*/
@@ -416,45 +420,45 @@ __STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p
/**
* @brief Function for setting the timer frequency.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] frequency Timer frequency.
*/
-__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg,
+__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg,
nrf_timer_frequency_t frequency);
/**
* @brief Function for retrieving the timer frequency.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Timer frequency.
*/
__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg);
/**
- * @brief Function for writing the capture/compare register for a specified channel.
+ * @brief Function for writing the capture/compare register for the specified channel.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] cc_channel Requested capture/compare channel.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] cc_channel The specified capture/compare channel.
* @param[in] cc_value Value to write to the capture/compare register.
*/
-__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg,
+__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg,
nrf_timer_cc_channel_t cc_channel,
uint32_t cc_value);
/**
* @brief Function for retrieving the capture/compare value for a specified channel.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] cc_channel Requested capture/compare channel.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] cc_channel The specified capture/compare channel.
*
- * @return Value from the requested capture/compare register.
+ * @return Value from the specified capture/compare register.
*/
-__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg,
+__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg,
nrf_timer_cc_channel_t cc_channel);
/**
- * @brief Function for getting a specific timer capture task.
+ * @brief Function for getting the specified timer capture task.
*
* @param[in] channel Capture channel.
*
@@ -463,7 +467,7 @@ __STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg,
__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel);
/**
- * @brief Function for getting a specific timer compare event.
+ * @brief Function for getting the specified timer compare event.
*
* @param[in] channel Compare channel.
*
@@ -472,7 +476,7 @@ __STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel);
__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel);
/**
- * @brief Function for getting a specific timer compare interrupt.
+ * @brief Function for getting the specified timer compare interrupt.
*
* @param[in] channel Compare channel.
*
@@ -489,7 +493,7 @@ __STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel)
*
* @return Number of timer ticks.
*/
-__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
+__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
nrf_timer_frequency_t frequency);
/**
@@ -501,7 +505,7 @@ __STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
*
* @return Number of timer ticks.
*/
-__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
+__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
nrf_timer_frequency_t frequency);
@@ -542,27 +546,27 @@ __STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg,
}
__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg,
- uint32_t timer_shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS |= timer_shorts_mask;
+ p_reg->SHORTS |= mask;
}
__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg,
- uint32_t timer_shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS &= ~(timer_shorts_mask);
+ p_reg->SHORTS &= ~(mask);
}
__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg,
- uint32_t timer_int_mask)
+ uint32_t mask)
{
- p_reg->INTENSET = timer_int_mask;
+ p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg,
- uint32_t timer_int_mask)
+ uint32_t mask)
{
- p_reg->INTENCLR = timer_int_mask;
+ p_reg->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg,
@@ -654,14 +658,12 @@ __STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg,
__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel)
{
- return (nrf_timer_task_t)
- ((uint32_t)NRF_TIMER_TASK_CAPTURE0 + (channel * sizeof(uint32_t)));
+ return (nrf_timer_task_t)NRFX_OFFSETOF(NRF_TIMER_Type, TASKS_CAPTURE[channel]);
}
__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel)
{
- return (nrf_timer_event_t)
- ((uint32_t)NRF_TIMER_EVENT_COMPARE0 + (channel * sizeof(uint32_t)));
+ return (nrf_timer_event_t)NRFX_OFFSETOF(NRF_TIMER_Type, EVENTS_COMPARE[channel]);
}
__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel)
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_twi.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_twi.h
index d668e3f9c..81411cb77 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_twi.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_twi.h
@@ -45,38 +45,28 @@ extern "C" {
* @brief Hardware access layer for managing the TWI peripheral.
*/
-/**
- * @brief TWI tasks.
- */
+/** @brief TWI tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_TWI_TASK_STARTRX = offsetof(NRF_TWI_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
NRF_TWI_TASK_STARTTX = offsetof(NRF_TWI_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
NRF_TWI_TASK_STOP = offsetof(NRF_TWI_Type, TASKS_STOP), ///< Stop TWI transaction.
NRF_TWI_TASK_SUSPEND = offsetof(NRF_TWI_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
NRF_TWI_TASK_RESUME = offsetof(NRF_TWI_Type, TASKS_RESUME) ///< Resume TWI transaction.
- /*lint -restore*/
} nrf_twi_task_t;
-/**
- * @brief TWI events.
- */
+/** @brief TWI events. */
typedef enum
{
- /*lint -save -e30*/
NRF_TWI_EVENT_STOPPED = offsetof(NRF_TWI_Type, EVENTS_STOPPED), ///< TWI stopped.
NRF_TWI_EVENT_RXDREADY = offsetof(NRF_TWI_Type, EVENTS_RXDREADY), ///< TWI RXD byte received.
NRF_TWI_EVENT_TXDSENT = offsetof(NRF_TWI_Type, EVENTS_TXDSENT), ///< TWI TXD byte sent.
NRF_TWI_EVENT_ERROR = offsetof(NRF_TWI_Type, EVENTS_ERROR), ///< TWI error.
NRF_TWI_EVENT_BB = offsetof(NRF_TWI_Type, EVENTS_BB), ///< TWI byte boundary, generated before each byte that is sent or received.
NRF_TWI_EVENT_SUSPENDED = offsetof(NRF_TWI_Type, EVENTS_SUSPENDED) ///< TWI entered the suspended state.
- /*lint -restore*/
} nrf_twi_event_t;
-/**
- * @brief TWI shortcuts.
- */
+/** @brief TWI shortcuts. */
typedef enum
{
NRF_TWI_SHORT_BB_SUSPEND_MASK = TWI_SHORTS_BB_SUSPEND_Msk, ///< Shortcut between BB event and SUSPEND task.
@@ -85,9 +75,7 @@ typedef enum
TWI_SHORTS_BB_STOP_Msk ///< All TWI shortcuts.
} nrf_twi_short_mask_t;
-/**
- * @brief TWI interrupts.
- */
+/** @brief TWI interrupts. */
typedef enum
{
NRF_TWI_INT_STOPPED_MASK = TWI_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
@@ -104,9 +92,7 @@ typedef enum
TWI_INTENSET_SUSPENDED_Msk ///< All TWI interrupts.
} nrf_twi_int_mask_t;
-/**
- * @brief TWI error source.
- */
+/** @brief TWI error source. */
typedef enum
{
NRF_TWI_ERROR_ADDRESS_NACK = TWI_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
@@ -116,9 +102,7 @@ typedef enum
* from the RXD register (previous data is lost). */
} nrf_twi_error_t;
-/**
- * @brief TWI master clock frequency.
- */
+/** @brief TWI master clock frequency. */
typedef enum
{
NRF_TWI_FREQ_100K = TWI_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
@@ -128,19 +112,19 @@ typedef enum
/**
- * @brief Function for activating a specific TWI task.
+ * @brief Function for activating the specified TWI task.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] task Task to activate.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg,
nrf_twi_task_t task);
/**
- * @brief Function for getting the address of a specific TWI task register.
+ * @brief Function for getting the address of the specified TWI task register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] task Requested task.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task The specified task.
*
* @return Address of the specified task register.
*/
@@ -148,31 +132,31 @@ __STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg,
nrf_twi_task_t task);
/**
- * @brief Function for clearing a specific TWI event.
+ * @brief Function for clearing the specified TWI event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to clear.
*/
-__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg,
+__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg,
nrf_twi_event_t event);
/**
- * @brief Function for checking the state of a specific event.
+ * @brief Function for retrieving the state of the TWI event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_reg,
nrf_twi_event_t event);
/**
- * @brief Function for getting the address of a specific TWI event register.
+ * @brief Function for getting the address of the specified TWI event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Requested event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event The specified event.
*
* @return Address of the specified event register.
*/
@@ -180,71 +164,71 @@ __STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_reg,
nrf_twi_event_t event);
/**
- * @brief Function for enabling specified shortcuts.
+ * @brief Function for enabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] shorts_mask Shortcuts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be enabled.
*/
__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg,
- uint32_t shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified shortcuts.
+ * @brief Function for disabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] shorts_mask Shortcuts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be disabled.
*/
__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg,
- uint32_t shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for enabling specified interrupts.
+ * @brief Function for enabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] int_mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg,
- uint32_t int_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified interrupts.
+ * @brief Function for disabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] int_mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg,
- uint32_t int_mask);
+ uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] int_mask Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] twi_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg,
- nrf_twi_int_mask_t int_mask);
+ nrf_twi_int_mask_t twi_int);
/**
* @brief Function for enabling the TWI peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg);
/**
* @brief Function for disabling the TWI peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg);
/**
* @brief Function for configuring TWI pins.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] scl_pin SCL pin number.
* @param[in] sda_pin SDA pin number.
*/
@@ -255,25 +239,25 @@ __STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg,
/**
* @brief Function for retrieving the SCL pin number.
*
- * @param[in] p_reg Pointer to the peripheral registers structure
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @retval pin SCL pin number.
+ * @return SCL pin number.
*/
__STATIC_INLINE uint32_t nrf_twi_scl_pin_get(NRF_TWI_Type * p_reg);
/**
* @brief Function for retrieving the SDA pin number.
*
- * @param[in] p_reg Pointer to the peripheral registers structure
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @retval pin SDA pin number.
+ * @return SDA pin number.
*/
__STATIC_INLINE uint32_t nrf_twi_sda_pin_get(NRF_TWI_Type * p_reg);
/**
* @brief Function for setting the TWI master clock frequency.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] frequency TWI frequency.
*/
__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg,
@@ -284,7 +268,7 @@ __STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg,
*
* The error flags are cleared after reading.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Mask with error source flags.
*/
@@ -293,7 +277,7 @@ __STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg);
/**
* @brief Function for setting the address to be used in TWI transfers.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] address Address to be used in transfers.
*/
__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address);
@@ -301,7 +285,7 @@ __STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address);
/**
* @brief Function for reading data received by TWI.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Received data.
*/
@@ -310,13 +294,19 @@ __STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg);
/**
* @brief Function for writing data to be transmitted by TWI.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] data Data to be transmitted.
*/
__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data);
+/**
+ * @brief Function for setting the specified shortcuts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be set.
+ */
__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg,
- uint32_t shorts_mask);
+ uint32_t mask);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
@@ -355,33 +345,33 @@ __STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_reg,
}
__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg,
- uint32_t shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS |= shorts_mask;
+ p_reg->SHORTS |= mask;
}
__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg,
- uint32_t shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS &= ~(shorts_mask);
+ p_reg->SHORTS &= ~(mask);
}
__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg,
- uint32_t int_mask)
+ uint32_t mask)
{
- p_reg->INTENSET = int_mask;
+ p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg,
- uint32_t int_mask)
+ uint32_t mask)
{
- p_reg->INTENCLR = int_mask;
+ p_reg->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg,
- nrf_twi_int_mask_t int_mask)
+ nrf_twi_int_mask_t twi_int)
{
- return (bool)(p_reg->INTENSET & int_mask);
+ return (bool)(p_reg->INTENSET & twi_int);
}
__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg)
@@ -461,9 +451,9 @@ __STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data)
}
__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg,
- uint32_t shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS = shorts_mask;
+ p_reg->SHORTS = mask;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_twim.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_twim.h
index ffe18f0b2..437281d9e 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_twim.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_twim.h
@@ -45,26 +45,19 @@ extern "C" {
* @brief Hardware access layer for managing the TWIM peripheral.
*/
-/**
- * @brief TWIM tasks.
- */
+/** @brief TWIM tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
NRF_TWIM_TASK_STOP = offsetof(NRF_TWIM_Type, TASKS_STOP), ///< Stop TWI transaction.
NRF_TWIM_TASK_SUSPEND = offsetof(NRF_TWIM_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
NRF_TWIM_TASK_RESUME = offsetof(NRF_TWIM_Type, TASKS_RESUME) ///< Resume TWI transaction.
- /*lint -restore*/
} nrf_twim_task_t;
-/**
- * @brief TWIM events.
- */
+/** @brief TWIM events. */
typedef enum
{
- /*lint -save -e30*/
NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped.
NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error.
NRF_TWIM_EVENT_SUSPENDED = 0x148, ///< TWI suspended.
@@ -72,12 +65,9 @@ typedef enum
NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started.
NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte.
NRF_TWIM_EVENT_LASTTX = offsetof(NRF_TWIM_Type, EVENTS_LASTTX) ///< Byte boundary, starting to transmit the last byte.
- /*lint -restore*/
} nrf_twim_event_t;
-/**
- * @brief TWIM shortcuts.
- */
+/** @brief TWIM shortcuts. */
typedef enum
{
NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk, ///< Shortcut between LASTTX event and STARTRX task.
@@ -92,9 +82,7 @@ typedef enum
TWIM_SHORTS_LASTRX_STOP_Msk ///< All TWIM shortcuts.
} nrf_twim_short_mask_t;
-/**
- * @brief TWIM interrupts.
- */
+/** @brief TWIM interrupts. */
typedef enum
{
NRF_TWIM_INT_STOPPED_MASK = TWIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
@@ -103,19 +91,17 @@ typedef enum
NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
NRF_TWIM_INT_LASTRX_MASK = TWIM_INTENSET_LASTRX_Msk, ///< Interrupt on LASTRX event.
- NRF_TWIM_INT_LASTTX_MASK = TWIM_INTENSET_LASTTX_Msk, ///< Interrupt on LASTTX event.
+ NRF_TWIM_INT_LASTTX_MASK = TWIM_INTENSET_LASTTX_Msk, ///< Interrupt on LASTTX event.
NRF_TWIM_ALL_INTS_MASK = TWIM_INTENSET_STOPPED_Msk |
TWIM_INTENSET_ERROR_Msk |
TWIM_INTENSET_SUSPENDED_Msk |
TWIM_INTENSET_RXSTARTED_Msk |
TWIM_INTENSET_TXSTARTED_Msk |
TWIM_INTENSET_LASTRX_Msk |
- TWIM_INTENSET_LASTTX_Msk ///< Interrupt on LASTTX event.
+ TWIM_INTENSET_LASTTX_Msk ///< All TWIM interrupts.
} nrf_twim_int_mask_t;
-/**
- * @brief TWIM master clock frequency.
- */
+/** @brief TWIM master clock frequency. */
typedef enum
{
NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
@@ -123,30 +109,31 @@ typedef enum
NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400 ///< 400 kbps.
} nrf_twim_frequency_t;
-/**
- * @brief TWIM error source.
- */
+/** @brief TWIM error source. */
typedef enum
{
- NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
- NRF_TWIM_ERROR_DATA_NACK = TWIM_ERRORSRC_DNACK_Msk ///< NACK received after sending a data byte.
+ NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
+ NRF_TWIM_ERROR_DATA_NACK = TWIM_ERRORSRC_DNACK_Msk, ///< NACK received after sending a data byte.
+ NRF_TWIM_ERROR_OVERRUN = TWIM_ERRORSRC_OVERRUN_Msk ///< Overrun error.
+ /**< A new byte was received before the previous byte was
+ * handled by peripheral. (previous data is lost). */
} nrf_twim_error_t;
/**
- * @brief Function for activating a specific TWIM task.
+ * @brief Function for activating the specified TWIM task.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] task Task to activate.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
nrf_twim_task_t task);
/**
- * @brief Function for getting the address of a specific TWIM task register.
+ * @brief Function for getting the address of the specified TWIM task register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] task Requested task.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task The specified task.
*
* @return Address of the specified task register.
*/
@@ -154,31 +141,31 @@ __STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg,
nrf_twim_task_t task);
/**
- * @brief Function for clearing a specific TWIM event.
+ * @brief Function for clearing the specified TWIM event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to clear.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to clear.
*/
-__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
+__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
nrf_twim_event_t event);
/**
- * @brief Function for checking the state of a specific TWIM event.
+ * @brief Function for retrieving the state of the TWIM event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg,
+__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg,
nrf_twim_event_t event);
/**
- * @brief Function for getting the address of a specific TWIM event register.
+ * @brief Function for getting the address of the specified TWIM event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Requested event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event The specified event.
*
* @return Address of the specified event register.
*/
@@ -186,52 +173,52 @@ __STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_reg,
nrf_twim_event_t event);
/**
- * @brief Function for enabling specified shortcuts.
+ * @brief Function for enabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] shorts_mask Shortcuts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be enabled.
*/
__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
- uint32_t shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified shortcuts.
+ * @brief Function for disabling the specified shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] shorts_mask Shortcuts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be disabled.
*/
__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
- uint32_t shorts_mask);
+ uint32_t mask);
/**
- * @brief Function for enabling specified interrupts.
+ * @brief Function for enabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] int_mask Interrupts to enable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
- uint32_t int_mask);
+ uint32_t mask);
/**
- * @brief Function for disabling specified interrupts.
+ * @brief Function for disabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] int_mask Interrupts to disable.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
- uint32_t int_mask);
+ uint32_t mask);
/**
* @brief Function for checking the state of a given interrupt.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] int_mask Interrupt to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] twim_int Interrupt to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
-__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg,
- nrf_twim_int_mask_t int_mask);
+__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg,
+ nrf_twim_int_mask_t twim_int);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
@@ -282,36 +269,35 @@ __STATIC_INLINE void nrf_twim_publish_clear(NRF_TWIM_Type * p_reg,
/**
* @brief Function for enabling the TWIM peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg);
/**
* @brief Function for disabling the TWIM peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg);
/**
* @brief Function for configuring TWI pins.
*
- *
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] scl_pin SCL pin number.
* @param[in] sda_pin SDA pin number.
*/
__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
- uint32_t scl_pin,
- uint32_t sda_pin);
+ uint32_t scl_pin,
+ uint32_t sda_pin);
/**
* @brief Function for setting the TWI master clock frequency.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] frequency TWI frequency.
*/
-__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
+__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
nrf_twim_frequency_t frequency);
/**
@@ -319,7 +305,7 @@ __STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
*
* The error flags are cleared after reading.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Mask with error source flags.
*/
@@ -328,18 +314,18 @@ __STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg);
/**
* @brief Function for setting the address to be used in TWI transfers.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] address Address to be used in transfers.
*/
__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
- uint8_t address);
+ uint8_t address);
/**
* @brief Function for setting the transmit buffer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] p_buffer Pointer to the buffer with data to send.
- * @param[in] length Maximum number of data bytes to transmit.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_buffer Pointer to the buffer with data to send.
+ * @param[in] length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
uint8_t const * p_buffer,
@@ -348,49 +334,70 @@ __STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
/**
* @brief Function for setting the receive buffer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buffer Pointer to the buffer for received data.
* @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
- uint8_t * p_buffer,
- size_t length);
+ uint8_t * p_buffer,
+ size_t length);
+/**
+ * @brief Function for setting the specified shortcuts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be set.
+ */
__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
- uint32_t shorts_mask);
+ uint32_t mask);
+/**
+ * @brief Function for getting the amount of transmitted bytes.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Amount of transmitted bytes.
+ */
__STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg);
+/**
+ * @brief Function for getting the amount of received bytes.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Amount of received bytes.
+ */
__STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg);
/**
* @brief Function for enabling the TX list feature.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg);
/**
* @brief Function for disabling the TX list feature.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg);
/**
* @brief Function for enabling the RX list feature.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg);
/**
* @brief Function for disabling the RX list feature.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
@@ -428,33 +435,33 @@ __STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_reg,
}
__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
- uint32_t shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS |= shorts_mask;
+ p_reg->SHORTS |= mask;
}
__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
- uint32_t shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS &= ~(shorts_mask);
+ p_reg->SHORTS &= ~(mask);
}
__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
- uint32_t int_mask)
+ uint32_t mask)
{
- p_reg->INTENSET = int_mask;
+ p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
- uint32_t int_mask)
+ uint32_t mask)
{
- p_reg->INTENCLR = int_mask;
+ p_reg->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg,
- nrf_twim_int_mask_t int_mask)
+ nrf_twim_int_mask_t twim_int)
{
- return (bool)(p_reg->INTENSET & int_mask);
+ return (bool)(p_reg->INTENSET & twim_int);
}
#if defined(DPPI_PRESENT)
@@ -544,9 +551,9 @@ __STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
}
__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
- uint32_t shorts_mask)
+ uint32_t mask)
{
- p_reg->SHORTS = shorts_mask;
+ p_reg->SHORTS = mask;
}
__STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg)
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_twis.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_twis.h
index 1b4701446..bc9f04079 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_twis.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_twis.h
@@ -46,221 +46,200 @@ extern "C" {
* (TWIS) peripheral.
*/
-/**
- * @brief TWIS tasks
- */
+/** @brief TWIS tasks. */
typedef enum
{
- /*lint -save -e30*/
- NRF_TWIS_TASK_STOP = offsetof(NRF_TWIS_Type, TASKS_STOP), /**< Stop TWIS transaction */
- NRF_TWIS_TASK_SUSPEND = offsetof(NRF_TWIS_Type, TASKS_SUSPEND), /**< Suspend TWIS transaction */
- NRF_TWIS_TASK_RESUME = offsetof(NRF_TWIS_Type, TASKS_RESUME), /**< Resume TWIS transaction */
- NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command */
- NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX) /**< Prepare the TWIS slave to respond to a read command */
- /*lint -restore*/
+ NRF_TWIS_TASK_STOP = offsetof(NRF_TWIS_Type, TASKS_STOP), /**< Stop TWIS transaction. */
+ NRF_TWIS_TASK_SUSPEND = offsetof(NRF_TWIS_Type, TASKS_SUSPEND), /**< Suspend TWIS transaction. */
+ NRF_TWIS_TASK_RESUME = offsetof(NRF_TWIS_Type, TASKS_RESUME), /**< Resume TWIS transaction. */
+ NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command. */
+ NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX) /**< Prepare the TWIS slave to respond to a read command. */
} nrf_twis_task_t;
-/**
- * @brief TWIS events
- */
+/** @brief TWIS events. */
typedef enum
{
- /*lint -save -e30*/
- NRF_TWIS_EVENT_STOPPED = offsetof(NRF_TWIS_Type, EVENTS_STOPPED), /**< TWIS stopped */
- NRF_TWIS_EVENT_ERROR = offsetof(NRF_TWIS_Type, EVENTS_ERROR), /**< TWIS error */
- NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started */
- NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started */
- NRF_TWIS_EVENT_WRITE = offsetof(NRF_TWIS_Type, EVENTS_WRITE), /**< Write command received */
- NRF_TWIS_EVENT_READ = offsetof(NRF_TWIS_Type, EVENTS_READ) /**< Read command received */
- /*lint -restore*/
+ NRF_TWIS_EVENT_STOPPED = offsetof(NRF_TWIS_Type, EVENTS_STOPPED), /**< TWIS stopped. */
+ NRF_TWIS_EVENT_ERROR = offsetof(NRF_TWIS_Type, EVENTS_ERROR), /**< TWIS error. */
+ NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started. */
+ NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started. */
+ NRF_TWIS_EVENT_WRITE = offsetof(NRF_TWIS_Type, EVENTS_WRITE), /**< Write command received. */
+ NRF_TWIS_EVENT_READ = offsetof(NRF_TWIS_Type, EVENTS_READ) /**< Read command received. */
} nrf_twis_event_t;
-/**
- * @brief TWIS shortcuts
- */
+/** @brief TWIS shortcuts. */
typedef enum
{
- NRF_TWIS_SHORT_WRITE_SUSPEND_MASK = TWIS_SHORTS_WRITE_SUSPEND_Msk, /**< Shortcut between WRITE event and SUSPEND task */
- NRF_TWIS_SHORT_READ_SUSPEND_MASK = TWIS_SHORTS_READ_SUSPEND_Msk, /**< Shortcut between READ event and SUSPEND task */
+ NRF_TWIS_SHORT_WRITE_SUSPEND_MASK = TWIS_SHORTS_WRITE_SUSPEND_Msk, /**< Shortcut between WRITE event and SUSPEND task. */
+ NRF_TWIS_SHORT_READ_SUSPEND_MASK = TWIS_SHORTS_READ_SUSPEND_Msk, /**< Shortcut between READ event and SUSPEND task. */
} nrf_twis_short_mask_t;
-/**
- * @brief TWIS interrupts
- */
+/** @brief TWIS interrupts. */
typedef enum
{
- NRF_TWIS_INT_STOPPED_MASK = TWIS_INTEN_STOPPED_Msk, /**< Interrupt on STOPPED event */
- NRF_TWIS_INT_ERROR_MASK = TWIS_INTEN_ERROR_Msk, /**< Interrupt on ERROR event */
- NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event */
- NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event */
- NRF_TWIS_INT_WRITE_MASK = TWIS_INTEN_WRITE_Msk, /**< Interrupt on WRITE event */
- NRF_TWIS_INT_READ_MASK = TWIS_INTEN_READ_Msk, /**< Interrupt on READ event */
+ NRF_TWIS_INT_STOPPED_MASK = TWIS_INTEN_STOPPED_Msk, /**< Interrupt on STOPPED event. */
+ NRF_TWIS_INT_ERROR_MASK = TWIS_INTEN_ERROR_Msk, /**< Interrupt on ERROR event. */
+ NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event. */
+ NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event. */
+ NRF_TWIS_INT_WRITE_MASK = TWIS_INTEN_WRITE_Msk, /**< Interrupt on WRITE event. */
+ NRF_TWIS_INT_READ_MASK = TWIS_INTEN_READ_Msk, /**< Interrupt on READ event. */
} nrf_twis_int_mask_t;
-/**
- * @brief TWIS error source
- */
+/** @brief TWIS error source. */
typedef enum
{
- NRF_TWIS_ERROR_OVERFLOW = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented */
- NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk, /**< NACK sent after receiving a data byte */
- NRF_TWIS_ERROR_OVERREAD = TWIS_ERRORSRC_OVERREAD_Msk /**< TX buffer over-read detected, and prevented */
+ NRF_TWIS_ERROR_OVERFLOW = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented. */
+ NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk, /**< NACK sent after receiving a data byte. */
+ NRF_TWIS_ERROR_OVERREAD = TWIS_ERRORSRC_OVERREAD_Msk /**< TX buffer over-read detected, and prevented. */
} nrf_twis_error_t;
-/**
- * @brief TWIS address matching configuration
- */
+/** @brief TWIS address matching configuration. */
typedef enum
{
- NRF_TWIS_CONFIG_ADDRESS0_MASK = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0] */
- NRF_TWIS_CONFIG_ADDRESS1_MASK = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1] */
- NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching */
+ NRF_TWIS_CONFIG_ADDRESS0_MASK = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0]. */
+ NRF_TWIS_CONFIG_ADDRESS1_MASK = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1]. */
+ NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching. */
} nrf_twis_config_addr_mask_t;
/**
- * @brief Variable type to hold amount of data for EasyDMA
+ * @brief Variable type to hold the amount of data for EasyDMA.
*
* Variable of the minimum size that can hold the amount of data to transfer.
*
- * @note
- * Defined to make it simple to change if EasyDMA would be updated to support more data in
- * the future devices to.
+ * @note Defined to make it simple to change if EasyDMA is updated to support more data in
+ * the future devices.
*/
typedef uint8_t nrf_twis_amount_t;
/**
- * @brief Smallest variable type to hold TWI address
+ * @brief Smallest variable type to hold the TWI address.
*
- * Variable of the minimum size that can hold single TWI address.
+ * Variable of the minimum size that can hold a single TWI address.
*
- * @note
- * Defined to make it simple to change if new TWI would support for example
- * 10 bit addressing mode.
+ * @note Defined to make it simple to change if the new TWI supports for example
+ * 10 bit addressing mode.
*/
typedef uint8_t nrf_twis_address_t;
/**
- * @brief Function for activating a specific TWIS task.
+ * @brief Function for activating the specified TWIS task.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param task Task.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task Task to be activated.
*/
-__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task);
+__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_t task);
/**
- * @brief Function for returning the address of a specific TWIS task register.
+ * @brief Function for returning the address of the specified TWIS task register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param task Task.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] task The specified task.
*
* @return Task address.
*/
-__STATIC_INLINE uint32_t nrf_twis_task_address_get(
- NRF_TWIS_Type const * const p_reg,
- nrf_twis_task_t task);
+__STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg,
+ nrf_twis_task_t task);
/**
- * @brief Function for clearing a specific event.
+ * @brief Function for clearing the specified event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param event Event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event The specified event.
*/
-__STATIC_INLINE void nrf_twis_event_clear(
- NRF_TWIS_Type * const p_reg,
- nrf_twis_event_t event);
+__STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg,
+ nrf_twis_event_t event);
+
/**
- * @brief Function for returning the state of a specific event.
+ * @brief Function for retrieving the state of the TWIS event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param event Event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
-__STATIC_INLINE bool nrf_twis_event_check(
- NRF_TWIS_Type const * const p_reg,
- nrf_twis_event_t event);
-
+__STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg,
+ nrf_twis_event_t event);
/**
- * @brief Function for getting and clearing the state of specific event
+ * @brief Function for getting and clearing the state of the specified event.
*
* This function checks the state of the event and clears it.
- * @param[in,out] p_reg Pointer to the peripheral registers structure.
- * @param event Event.
*
- * @retval true If the event was set.
- * @retval false If the event was not set.
+ * @param[in,out] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event.
+ *
+ * @retval true The event was set.
+ * @retval false The event was not set.
*/
-__STATIC_INLINE bool nrf_twis_event_get_and_clear(
- NRF_TWIS_Type * const p_reg,
- nrf_twis_event_t event);
-
+__STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg,
+ nrf_twis_event_t event);
/**
- * @brief Function for returning the address of a specific TWIS event register.
+ * @brief Function for returning the address of the specified TWIS event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param event Event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event.
*
* @return Address.
*/
-__STATIC_INLINE uint32_t nrf_twis_event_address_get(
- NRF_TWIS_Type const * const p_reg,
- nrf_twis_event_t event);
+__STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg,
+ nrf_twis_event_t event);
/**
* @brief Function for setting a shortcut.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param short_mask Shortcuts mask.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of shortcuts to be enabled.
*/
-__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask);
+__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask);
/**
* @brief Function for clearing shortcuts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param short_mask Shortcuts mask.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of shortcuts to be disabled.
*/
-__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask);
+__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mask);
/**
- * @brief Get the shorts mask
+ * @brief Function for getting the shorts mask.
*
* Function returns shorts register.
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
* @return Flags of currently enabled shortcuts
*/
-__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg);
+__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg);
/**
- * @brief Function for enabling selected interrupts.
+ * @brief Function for enabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param int_mask Interrupts mask.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be enabled.
*/
-__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask);
+__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * p_reg, uint32_t mask);
/**
- * @brief Function for retrieving the state of selected interrupts.
+ * @brief Function for retrieving the state of the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param int_mask Interrupts mask.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be checked.
*
- * @retval true If any of selected interrupts is enabled.
- * @retval false If none of selected interrupts is enabled.
+ * @retval true Any of the specified interrupts is enabled.
+ * @retval false None of the specified interrupts is enabled.
*/
-__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask);
+__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint32_t mask);
/**
- * @brief Function for disabling selected interrupts.
+ * @brief Function for disabling the specified interrupts.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param int_mask Interrupts mask.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Mask of interrupts to be disabled.
*/
-__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask);
+__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * p_reg, uint32_t mask);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
@@ -312,177 +291,182 @@ __STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg,
* @brief Function for retrieving and clearing the TWIS error source.
*
* @attention Error sources are cleared after read.
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
* @return Error source mask with values from @ref nrf_twis_error_t.
*/
__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg);
/**
- * @brief Get information which of addresses matched
+ * @brief Function for getting information about which of the addresses matched.
*
* Function returns index in the address table
* that points to the address that already matched.
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @return Index of matched address
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Index of matched address.
*/
__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg);
/**
* @brief Function for enabling TWIS.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
-__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * const p_reg);
+__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * p_reg);
/**
* @brief Function for disabling TWIS.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
-__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * const p_reg);
+__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg);
/**
* @brief Function for configuring TWIS pins.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param scl SCL pin number.
- * @param sda SDA pin number.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] scl SCL pin number.
+ * @param[in] sda SDA pin number.
*/
-__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda);
+__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda);
/**
* @brief Function for setting the receive buffer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param p_buf Pointer to the buffer for received data.
- * @param length Maximum number of data bytes to receive.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_buf Pointer to the buffer for received data.
+ * @param[in] length Maximum number of data bytes to receive.
*/
-__STATIC_INLINE void nrf_twis_rx_buffer_set(
- NRF_TWIS_Type * const p_reg,
- uint8_t * p_buf,
- nrf_twis_amount_t length);
+__STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg,
+ uint8_t * p_buf,
+ size_t length);
/**
* @brief Function that prepares TWIS for receiving
*
* This function sets receive buffer and then sets NRF_TWIS_TASK_PREPARERX task.
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param p_buf Pointer to the buffer for received data.
- * @param length Maximum number of data bytes to receive.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_buf Pointer to the buffer for received data.
+ * @param[in] length Maximum number of data bytes to receive.
*/
-__STATIC_INLINE void nrf_twis_rx_prepare(
- NRF_TWIS_Type * const p_reg,
- uint8_t * p_buf,
- nrf_twis_amount_t length);
+__STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg,
+ uint8_t * p_buf,
+ size_t length);
/**
* @brief Function for getting number of bytes received in the last transaction.
*
* @param[in] p_reg TWIS instance.
+ *
* @return Amount of bytes received.
* */
-__STATIC_INLINE nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg);
+__STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg);
/**
* @brief Function for setting the transmit buffer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param p_buf Pointer to the buffer with data to send.
- * @param length Maximum number of data bytes to transmit.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_buf Pointer to the buffer with data to send.
+ * @param[in] length Maximum number of data bytes to transmit.
*/
-__STATIC_INLINE void nrf_twis_tx_buffer_set(
- NRF_TWIS_Type * const p_reg,
- uint8_t const * p_buf,
- nrf_twis_amount_t length);
+__STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg,
+ uint8_t const * p_buf,
+ size_t length);
/**
- * @brief Function that prepares TWIS for transmitting
+ * @brief Function for preparing TWIS for transmitting.
*
* This function sets transmit buffer and then sets NRF_TWIS_TASK_PREPARETX task.
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param p_buf Pointer to the buffer with data to send.
- * @param length Maximum number of data bytes to transmit.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_buf Pointer to the buffer with data to send.
+ * @param[in] length Maximum number of data bytes to transmit.
*/
-__STATIC_INLINE void nrf_twis_tx_prepare(
- NRF_TWIS_Type * const p_reg,
- uint8_t const * p_buf,
- nrf_twis_amount_t length);
+__STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg,
+ uint8_t const * p_buf,
+ size_t length);
/**
- * @brief Function for getting number of bytes transmitted in the last transaction.
+ * @brief Function for getting the number of bytes transmitted in the last transaction.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
* @return Amount of bytes transmitted.
*/
-__STATIC_INLINE nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg);
+__STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg);
/**
- * @brief Function for setting slave address
+ * @brief Function for setting the slave address.
*
* Function sets the selected address for this TWI interface.
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param n Index of address to set
- * @param addr Addres to set
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] n Index of address to be set.
+ * @param[in] addr Addres to be set.
+ *
* @sa nrf_twis_config_address_set
* @sa nrf_twis_config_address_get
*/
-__STATIC_INLINE void nrf_twis_address_set(
- NRF_TWIS_Type * const p_reg,
- uint_fast8_t n,
- nrf_twis_address_t addr);
+__STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg,
+ uint_fast8_t n,
+ nrf_twis_address_t addr);
/**
- * @brief Function for retrieving configured slave address
+ * @brief Function for retrieving configured slave address.
*
* Function gets the selected address for this TWI interface.
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param n Index of address to get
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] n Index of address to get.
+ *
+ * @return Configured slave address.
*/
-__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(
- NRF_TWIS_Type const * const p_reg,
- uint_fast8_t n);
+__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_reg,
+ uint_fast8_t n);
/**
* @brief Function for setting the device address configuration.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param addr_mask Mask of address indexes of what device should answer to.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] addr_mask Mask of address indexes of what device should answer to.
*
* @sa nrf_twis_address_set
*/
-__STATIC_INLINE void nrf_twis_config_address_set(
- NRF_TWIS_Type * const p_reg,
- nrf_twis_config_addr_mask_t addr_mask);
+__STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_reg,
+ nrf_twis_config_addr_mask_t addr_mask);
/**
* @brief Function for retrieving the device address configuration.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Mask of address indexes of what device should answer to.
*/
__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get(
- NRF_TWIS_Type const * const p_reg);
+ NRF_TWIS_Type const * p_reg);
/**
* @brief Function for setting the over-read character.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] orc Over-read character. Character clocked out in case of
- * over-read of the TXD buffer.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] orc Over-read character. Character clocked out in case of
+ * over-read of the TXD buffer.
*/
-__STATIC_INLINE void nrf_twis_orc_set(
- NRF_TWIS_Type * const p_reg,
- uint8_t orc);
+__STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg,
+ uint8_t orc);
/**
* @brief Function for setting the over-read character.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Over-read character configured for selected instance.
*/
-__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg);
+__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg);
/** @} */ /* End of nrf_twis_hal */
@@ -495,30 +479,31 @@ __STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg);
/**
* @internal
- * @brief Internal function for getting task/event register address
+ * @brief Internal function for getting task or event register address.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @oaram offset Offset of the register from the instance beginning
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] offset Offset of the register from the beginning of the instance.
*
- * @attention offset has to be modulo 4 value. In other case we can get hardware fault.
- * @return Pointer to the register
+ * @attention Offset must be modulo 4 value. In other case, hardware fault can occur.
+ * @return Pointer to the register.
*/
-__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type * const p_reg, uint32_t offset)
+__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type const * p_reg, uint32_t offset)
{
return (volatile uint32_t*)((uint8_t *)p_reg + (uint32_t)offset);
}
/**
* @internal
- * @brief Internal function for getting task/event register address - constant version
+ * @brief Internal function for getting task/event register address - constant version.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @oaram offset Offset of the register from the instance beginning
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] offset Offset of the register from the beginning of the instance.
*
- * @attention offset has to be modulo 4 value. In other case we can get hardware fault.
- * @return Pointer to the register
+ * @attention Offset must be modulo 4 value. In other case, hardware fault can occur.
+ * @return Pointer to the register.
*/
-__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * const p_reg, uint32_t offset)
+__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * p_reg,
+ uint32_t offset)
{
return (volatile const uint32_t*)((uint8_t *)p_reg + (uint32_t)offset);
}
@@ -529,21 +514,18 @@ __STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type cons
*/
-void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task)
+__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_t task)
{
*(nrf_twis_getRegPtr(p_reg, (uint32_t)task)) = 1UL;
}
-uint32_t nrf_twis_task_address_get(
- NRF_TWIS_Type const * const p_reg,
- nrf_twis_task_t task)
+__STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg,
+ nrf_twis_task_t task)
{
return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)task);
}
-void nrf_twis_event_clear(
- NRF_TWIS_Type * const p_reg,
- nrf_twis_event_t event)
+__STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event)
{
*(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL;
#if __CORTEX_M == 0x04
@@ -552,16 +534,12 @@ void nrf_twis_event_clear(
#endif
}
-bool nrf_twis_event_check(
- NRF_TWIS_Type const * const p_reg,
- nrf_twis_event_t event)
+__STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, nrf_twis_event_t event)
{
return (bool)*nrf_twis_getRegPtr_c(p_reg, (uint32_t)event);
}
-bool nrf_twis_event_get_and_clear(
- NRF_TWIS_Type * const p_reg,
- nrf_twis_event_t event)
+__STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event)
{
bool ret = nrf_twis_event_check(p_reg, event);
if (ret)
@@ -571,55 +549,54 @@ bool nrf_twis_event_get_and_clear(
return ret;
}
-uint32_t nrf_twis_event_address_get(
- NRF_TWIS_Type const * const p_reg,
- nrf_twis_event_t event)
+__STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg,
+ nrf_twis_event_t event)
{
return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)event);
}
-void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask)
+__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask)
{
- p_reg->SHORTS |= short_mask;
+ p_reg->SHORTS |= mask;
}
-void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask)
+__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mask)
{
- if (~0U == short_mask)
+ if (~0U == mask)
{
/* Optimized version for "disable all" */
p_reg->SHORTS = 0;
}
else
{
- p_reg->SHORTS &= ~short_mask;
+ p_reg->SHORTS &= ~mask;
}
}
-uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg)
+__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg)
{
return p_reg->SHORTS;
}
-void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask)
+__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * p_reg, uint32_t mask)
{
- p_reg->INTENSET = int_mask;
+ p_reg->INTENSET = mask;
}
-bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask)
+__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint32_t mask)
{
- return (bool)(p_reg->INTENSET & int_mask);
+ return (bool)(p_reg->INTENSET & mask);
}
-void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask)
+__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t mask)
{
- p_reg->INTENCLR = int_mask;
+ p_reg->INTENCLR = mask;
}
#if defined(DPPI_PRESENT)
__STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg,
nrf_twis_task_t task,
- uint8_t channel)
+ uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
((uint32_t)channel | TWIS_SUBSCRIBE_STOP_EN_Msk);
@@ -633,7 +610,7 @@ __STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg,
__STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type * p_reg,
nrf_twis_event_t event,
- uint8_t channel)
+ uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
((uint32_t)channel | TWIS_PUBLISH_STOPPED_EN_Msk);
@@ -646,115 +623,105 @@ __STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg,
}
#endif // defined(DPPI_PRESENT)
-uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg)
+__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * p_reg)
{
uint32_t ret = p_reg->ERRORSRC;
p_reg->ERRORSRC = ret;
return ret;
}
-uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg)
+__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg)
{
return (uint_fast8_t)p_reg->MATCH;
}
-void nrf_twis_enable(NRF_TWIS_Type * const p_reg)
+__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * p_reg)
{
p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos);
}
-void nrf_twis_disable(NRF_TWIS_Type * const p_reg)
+__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg)
{
p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos);
}
-void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda)
+__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda)
{
p_reg->PSEL.SCL = scl;
p_reg->PSEL.SDA = sda;
}
-void nrf_twis_rx_buffer_set(
- NRF_TWIS_Type * const p_reg,
- uint8_t * p_buf,
- nrf_twis_amount_t length)
+__STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg,
+ uint8_t * p_buf,
+ size_t length)
{
p_reg->RXD.PTR = (uint32_t)p_buf;
p_reg->RXD.MAXCNT = length;
}
-__STATIC_INLINE void nrf_twis_rx_prepare(
- NRF_TWIS_Type * const p_reg,
- uint8_t * p_buf,
- nrf_twis_amount_t length)
+__STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg,
+ uint8_t * p_buf,
+ size_t length)
{
nrf_twis_rx_buffer_set(p_reg, p_buf, length);
nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARERX);
}
-nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg)
+__STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg)
{
- return (nrf_twis_amount_t)p_reg->RXD.AMOUNT;
+ return p_reg->RXD.AMOUNT;
}
-void nrf_twis_tx_buffer_set(
- NRF_TWIS_Type * const p_reg,
- uint8_t const * p_buf,
- nrf_twis_amount_t length)
+__STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg,
+ uint8_t const * p_buf,
+ size_t length)
{
p_reg->TXD.PTR = (uint32_t)p_buf;
p_reg->TXD.MAXCNT = length;
}
-__STATIC_INLINE void nrf_twis_tx_prepare(
- NRF_TWIS_Type * const p_reg,
- uint8_t const * p_buf,
- nrf_twis_amount_t length)
+__STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg,
+ uint8_t const * p_buf,
+ size_t length)
{
nrf_twis_tx_buffer_set(p_reg, p_buf, length);
nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARETX);
}
-nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg)
+__STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg)
{
- return (nrf_twis_amount_t)p_reg->TXD.AMOUNT;
+ return p_reg->TXD.AMOUNT;
}
-void nrf_twis_address_set(
- NRF_TWIS_Type * const p_reg,
- uint_fast8_t n,
- nrf_twis_address_t addr)
+__STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg,
+ uint_fast8_t n,
+ nrf_twis_address_t addr)
{
p_reg->ADDRESS[n] = addr;
}
-nrf_twis_address_t nrf_twis_address_get(
- NRF_TWIS_Type const * const p_reg,
- uint_fast8_t n)
+__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_reg, uint_fast8_t n)
{
return (nrf_twis_address_t)p_reg->ADDRESS[n];
}
-void nrf_twis_config_address_set(
- NRF_TWIS_Type * const p_reg,
- nrf_twis_config_addr_mask_t addr_mask)
+__STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_reg,
+ nrf_twis_config_addr_mask_t addr_mask)
{
/* This is the only configuration in TWIS - just write it without masking */
p_reg->CONFIG = addr_mask;
}
-nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * const p_reg)
+__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * p_reg)
{
return (nrf_twis_config_addr_mask_t)(p_reg->CONFIG & TWIS_ADDRESS_ADDRESS_Msk);
}
-void nrf_twis_orc_set(
- NRF_TWIS_Type * const p_reg,
- uint8_t orc)
+__STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg, uint8_t orc)
{
p_reg->ORC = orc;
}
-uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg)
+__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg)
{
return (uint8_t)p_reg->ORC;
}
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_uart.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_uart.h
index cd894eaf7..afd9c791b 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_uart.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_uart.h
@@ -45,59 +45,42 @@ extern "C" {
* @brief Hardware access layer for managing the UART peripheral.
*/
+/** @brief Pin disconnected value. */
#define NRF_UART_PSEL_DISCONNECTED 0xFFFFFFFF
-/**
- * @enum nrf_uart_task_t
- * @brief UART tasks.
- */
+/** @brief UART tasks. */
typedef enum
{
- /*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_UART_TASK_STARTRX = offsetof(NRF_UART_Type, TASKS_STARTRX), /**< Task for starting reception. */
NRF_UART_TASK_STOPRX = offsetof(NRF_UART_Type, TASKS_STOPRX), /**< Task for stopping reception. */
NRF_UART_TASK_STARTTX = offsetof(NRF_UART_Type, TASKS_STARTTX), /**< Task for starting transmission. */
NRF_UART_TASK_STOPTX = offsetof(NRF_UART_Type, TASKS_STOPTX), /**< Task for stopping transmission. */
NRF_UART_TASK_SUSPEND = offsetof(NRF_UART_Type, TASKS_SUSPEND), /**< Task for suspending UART. */
- /*lint -restore*/
} nrf_uart_task_t;
-/**
- * @enum nrf_uart_event_t
- * @brief UART events.
- */
+/** @brief UART events. */
typedef enum
{
- /*lint -save -e30*/
NRF_UART_EVENT_CTS = offsetof(NRF_UART_Type, EVENTS_CTS), /**< Event from CTS line activation. */
NRF_UART_EVENT_NCTS = offsetof(NRF_UART_Type, EVENTS_NCTS), /**< Event from CTS line deactivation. */
NRF_UART_EVENT_RXDRDY = offsetof(NRF_UART_Type, EVENTS_RXDRDY),/**< Event from data ready in RXD. */
NRF_UART_EVENT_TXDRDY = offsetof(NRF_UART_Type, EVENTS_TXDRDY),/**< Event from data sent from TXD. */
NRF_UART_EVENT_ERROR = offsetof(NRF_UART_Type, EVENTS_ERROR), /**< Event from error detection. */
NRF_UART_EVENT_RXTO = offsetof(NRF_UART_Type, EVENTS_RXTO) /**< Event from receiver timeout. */
- /*lint -restore*/
} nrf_uart_event_t;
-/**
- * @enum nrf_uart_int_mask_t
- * @brief UART interrupts.
- */
+/** @brief UART interrupts. */
typedef enum
{
- /*lint -save -e30*/
NRF_UART_INT_MASK_CTS = UART_INTENCLR_CTS_Msk, /**< CTS line activation interrupt. */
NRF_UART_INT_MASK_NCTS = UART_INTENCLR_NCTS_Msk, /**< CTS line deactivation interrupt. */
NRF_UART_INT_MASK_RXDRDY = UART_INTENCLR_RXDRDY_Msk, /**< Data ready in RXD interrupt. */
- NRF_UART_INT_MASK_TXDRDY = UART_INTENCLR_TXDRDY_Msk, /**< Data sent from TXD interrupt. */
+ NRF_UART_INT_MASK_TXDRDY = UART_INTENCLR_TXDRDY_Msk, /**< Data sent from TXD interrupt. */
NRF_UART_INT_MASK_ERROR = UART_INTENCLR_ERROR_Msk, /**< Error detection interrupt. */
NRF_UART_INT_MASK_RXTO = UART_INTENCLR_RXTO_Msk /**< Receiver timeout interrupt. */
- /*lint -restore*/
} nrf_uart_int_mask_t;
-/**
- * @enum nrf_uart_baudrate_t
- * @brief Baudrates supported by UART.
- */
+/** @brief Baudrates supported by UART. */
typedef enum
{
NRF_UART_BAUDRATE_1200 = UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
@@ -120,10 +103,7 @@ typedef enum
NRF_UART_BAUDRATE_1000000 = UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
} nrf_uart_baudrate_t;
-/**
- * @enum nrf_uart_error_mask_t
- * @brief Types of UART error masks.
- */
+/** @brief Types of UART error masks. */
typedef enum
{
NRF_UART_ERROR_OVERRUN_MASK = UART_ERRORSRC_OVERRUN_Msk, /**< Overrun error. */
@@ -132,155 +112,158 @@ typedef enum
NRF_UART_ERROR_BREAK_MASK = UART_ERRORSRC_BREAK_Msk, /**< Break error. */
} nrf_uart_error_mask_t;
-/**
- * @enum nrf_uart_parity_t
- * @brief Types of UART parity modes.
- */
+/** @brief Types of UART parity modes. */
typedef enum
{
NRF_UART_PARITY_EXCLUDED = UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos, /**< Parity excluded. */
NRF_UART_PARITY_INCLUDED = UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos, /**< Parity included. */
} nrf_uart_parity_t;
-/**
- * @enum nrf_uart_hwfc_t
- * @brief Types of UART flow control modes.
- */
+/** @brief Types of UART flow control modes. */
typedef enum
{
- NRF_UART_HWFC_DISABLED = UART_CONFIG_HWFC_Disabled, /**< HW flow control disabled. */
- NRF_UART_HWFC_ENABLED = UART_CONFIG_HWFC_Enabled, /**< HW flow control enabled. */
+ NRF_UART_HWFC_DISABLED = UART_CONFIG_HWFC_Disabled, /**< Hardware flow control disabled. */
+ NRF_UART_HWFC_ENABLED = UART_CONFIG_HWFC_Enabled, /**< Hardware flow control enabled. */
} nrf_uart_hwfc_t;
/**
- * @brief Function for clearing a specific UART event.
+ * @brief Function for clearing the specified UART event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to clear.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event);
/**
- * @brief Function for checking the state of a specific UART event.
+ * @brief Function for retrieving the state of the UART event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval True if event is set, False otherwise.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event);
/**
- * @brief Function for returning the address of a specific UART event register.
+ * @brief Function for returning the address of the specified UART event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Desired event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Desired event.
*
- * @retval Address of specified event register.
+ * @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg,
- nrf_uart_event_t event);
+ nrf_uart_event_t event);
/**
- * @brief Function for enabling a specific interrupt.
+ * @brief Function for enabling the specified interrupt.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param int_mask Interrupts to enable.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param mask Mask of interrupts to be enabled.
*/
-__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask);
+__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param int_mask Mask of interrupt to check.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param mask Mask of interrupts to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
-__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask);
+__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t mask);
/**
- * @brief Function for disabling specific interrupts.
+ * @brief Function for disabling the specified interrupts.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param int_mask Interrupts to disable.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param mask Mask of interrupts to be disabled.
*/
-__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask);
+__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t mask);
/**
* @brief Function for getting error source mask. Function is clearing error source flags after reading.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @return Mask with error source flags.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Mask with error source flags.
*/
__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg);
/**
* @brief Function for enabling UART.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg);
/**
* @brief Function for disabling UART.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg);
/**
* @brief Function for configuring TX/RX pins.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param pseltxd TXD pin number.
- * @param pselrxd RXD pin number.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param pseltxd TXD pin number.
+ * @param pselrxd RXD pin number.
*/
__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd);
/**
* @brief Function for disconnecting TX/RX pins.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg);
/**
* @brief Function for getting TX pin.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return TX pin number.
*/
__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg);
/**
* @brief Function for getting RX pin.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return RX pin number.
*/
__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg);
/**
* @brief Function for getting RTS pin.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return RTS pin number.
*/
__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg);
/**
* @brief Function for getting CTS pin.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return CTS pin number.
*/
__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg);
-
/**
* @brief Function for configuring flow control pins.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param pselrts RTS pin number.
- * @param pselcts CTS pin number.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param pselrts RTS pin number.
+ * @param pselcts CTS pin number.
*/
__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg,
uint32_t pselrts,
@@ -289,64 +272,67 @@ __STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg,
/**
* @brief Function for disconnecting flow control pins.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg);
/**
* @brief Function for reading RX data.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @return Received byte.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Received byte.
*/
__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg);
/**
* @brief Function for setting Tx data.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param txd Byte.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param txd Byte.
*/
__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd);
/**
* @brief Function for starting an UART task.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param task Task.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param task Task.
*/
__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task);
/**
- * @brief Function for returning the address of a specific task register.
+ * @brief Function for returning the address of the specified task register.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
* @param task Task.
*
- * @return Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task);
/**
* @brief Function for configuring UART.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
* @param hwfc Hardware flow control. Enabled if true.
* @param parity Parity. Included if true.
*/
__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg,
- nrf_uart_parity_t parity,
- nrf_uart_hwfc_t hwfc);
+ nrf_uart_parity_t parity,
+ nrf_uart_hwfc_t hwfc);
/**
- * @brief Function for setting UART baudrate.
+ * @brief Function for setting UART baud rate.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param baudrate Baudrate.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param baudrate Baud rate.
*/
-__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate);
+__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
@@ -354,7 +340,6 @@ __STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
(void)dummy;
#endif
-
}
__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event)
@@ -363,24 +348,24 @@ __STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_
}
__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg,
- nrf_uart_event_t event)
+ nrf_uart_event_t event)
{
return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
}
-__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask)
+__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t mask)
{
- p_reg->INTENSET = int_mask;
+ p_reg->INTENSET = mask;
}
-__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask)
+__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t mask)
{
- return (bool)(p_reg->INTENSET & int_mask);
+ return (bool)(p_reg->INTENSET & mask);
}
-__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask)
+__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t mask)
{
- p_reg->INTENCLR = int_mask;
+ p_reg->INTENCLR = mask;
}
__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg)
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_uarte.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_uarte.h
index b1e2feb1d..19a38c753 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_uarte.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_uarte.h
@@ -47,28 +47,19 @@ extern "C" {
* @brief Hardware access layer for managing the UARTE peripheral.
*/
-/**
- * @enum nrf_uarte_task_t
- * @brief UARTE tasks.
- */
+/** @brief UARTE tasks. */
typedef enum
{
- /*lint -save -e30*/
NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver.
NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter.
NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
- /*lint -restore*/
} nrf_uarte_task_t;
-/**
- * @enum nrf_uarte_event_t
- * @brief UARTE events.
- */
+/** @brief UARTE events. */
typedef enum
{
- /*lint -save -e30*/
NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM).
@@ -80,12 +71,9 @@ typedef enum
NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started.
NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started.
NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped.
- /*lint -restore*/
} nrf_uarte_event_t;
-/**
- * @brief Types of UARTE shortcuts.
- */
+/** @brief Types of UARTE shortcuts. */
typedef enum
{
NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk, ///< Shortcut between ENDRX event and STARTRX task.
@@ -93,10 +81,7 @@ typedef enum
} nrf_uarte_short_t;
-/**
- * @enum nrf_uarte_int_mask_t
- * @brief UARTE interrupts.
- */
+/** @brief UARTE interrupts. */
typedef enum
{
NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
@@ -112,10 +97,7 @@ typedef enum
NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event.
} nrf_uarte_int_mask_t;
-/**
- * @enum nrf_uarte_baudrate_t
- * @brief Baudrates supported by UARTE.
- */
+/** @brief Baudrates supported by UARTE. */
typedef enum
{
NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
@@ -138,10 +120,7 @@ typedef enum
NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M ///< 1000000 baud.
} nrf_uarte_baudrate_t;
-/**
- * @enum nrf_uarte_error_mask_t
- * @brief Types of UARTE error masks.
- */
+/** @brief Types of UARTE error masks. */
typedef enum
{
NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error.
@@ -150,98 +129,93 @@ typedef enum
NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk ///< Break error.
} nrf_uarte_error_mask_t;
-/**
- * @enum nrf_uarte_parity_t
- * @brief Types of UARTE parity modes.
- */
+/** @brief Types of UARTE parity modes. */
typedef enum
{
NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded.
NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos ///< Parity included.
} nrf_uarte_parity_t;
-/**
- * @enum nrf_uarte_hwfc_t
- * @brief Types of UARTE flow control modes.
- */
+/** @brief Types of UARTE flow control modes. */
typedef enum
{
- NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control disabled.
- NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< HW flow control enabled.
+ NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< Hardware flow control disabled.
+ NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< Hardware flow control enabled.
} nrf_uarte_hwfc_t;
/**
- * @brief Function for clearing a specific UARTE event.
+ * @brief Function for clearing the specified UARTE event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to clear.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
/**
- * @brief Function for checking the state of a specific UARTE event.
+ * @brief Function for retrieving the state of the UARTE event.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Event to check.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event Event to be checked.
*
- * @retval True if event is set, False otherwise.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
/**
- * @brief Function for returning the address of a specific UARTE event register.
+ * @brief Function for returning the address of the specified UARTE event register.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] event Desired event.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] event The specified event.
*
- * @retval Address of specified event register.
+ * @return Address of specified event register.
*/
-__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
- nrf_uarte_event_t event);
+__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
+ nrf_uarte_event_t event);
/**
* @brief Function for enabling UARTE shortcuts.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param shorts_mask Shortcuts to enable.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param mask Shortcuts to be enabled.
*/
-__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask);
+__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
/**
* @brief Function for disabling UARTE shortcuts.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param shorts_mask Shortcuts to disable.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param mask Shortcuts to be disabled.
*/
-__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask);
+__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
/**
* @brief Function for enabling UARTE interrupts.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param int_mask Interrupts to enable.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param mask Mask of interrupts to be enabled.
*/
-__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask);
+__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
/**
- * @brief Function for retrieving the state of a given interrupt.
+ * @brief Function for retrieving the state of the specified interrupt.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param int_mask Mask of interrupt to check.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param mask Mask of interrupts to be checked.
*
- * @retval true If the interrupt is enabled.
- * @retval false If the interrupt is not enabled.
+ * @retval true The interrupt is enabled.
+ * @retval false The interrupt is not enabled.
*/
-__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask);
+__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t mask);
/**
- * @brief Function for disabling specific interrupts.
+ * @brief Function for disabling the specified interrupts.
*
- * @param p_reg Instance.
- * @param int_mask Interrupts to disable.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param mask Mask of interrupts to be disabled.
*/
-__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask);
+__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
@@ -292,132 +266,141 @@ __STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
/**
* @brief Function for getting error source mask. Function is clearing error source flags after reading.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @return Mask with error source flags.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Mask with error source flags.
*/
__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg);
/**
* @brief Function for enabling UARTE.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg);
/**
* @brief Function for disabling UARTE.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg);
/**
* @brief Function for configuring TX/RX pins.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param pseltxd TXD pin number.
- * @param pselrxd RXD pin number.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param pseltxd TXD pin number.
+ * @param pselrxd RXD pin number.
*/
-__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd);
+__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
+ uint32_t pseltxd,
+ uint32_t pselrxd);
/**
* @brief Function for disconnecting TX/RX pins.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
/**
* @brief Function for getting TX pin.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return TX pin number.
*/
__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg);
/**
* @brief Function for getting RX pin.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return RX pin number.
*/
__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg);
/**
* @brief Function for getting RTS pin.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return RTS pin number.
*/
__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg);
/**
* @brief Function for getting CTS pin.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return CTS pin number.
*/
__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg);
-
/**
* @brief Function for configuring flow control pins.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param pselrts RTS pin number.
- * @param pselcts CTS pin number.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param pselrts RTS pin number.
+ * @param pselcts CTS pin number.
*/
__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
- uint32_t pselrts,
- uint32_t pselcts);
+ uint32_t pselrts,
+ uint32_t pselcts);
/**
* @brief Function for disconnecting flow control pins.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg);
/**
* @brief Function for starting an UARTE task.
*
- * @param p_reg Pointer to the peripheral registers structure.
- * @param task Task.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param task Task.
*/
__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
/**
- * @brief Function for returning the address of a specific task register.
+ * @brief Function for returning the address of the specified task register.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
* @param task Task.
*
- * @return Task address.
+ * @return Task address.
*/
__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
/**
* @brief Function for configuring UARTE.
*
- * @param p_reg Pointer to the peripheral registers structure.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
* @param hwfc Hardware flow control. Enabled if true.
* @param parity Parity. Included if true.
*/
__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
- nrf_uarte_parity_t parity,
- nrf_uarte_hwfc_t hwfc);
-
+ nrf_uarte_parity_t parity,
+ nrf_uarte_hwfc_t hwfc);
/**
- * @brief Function for setting UARTE baudrate.
+ * @brief Function for setting UARTE baud rate.
*
- * @param p_reg Instance.
- * @param baudrate Baudrate.
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param baudrate Baud rate.
*/
__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate);
/**
* @brief Function for setting the transmit buffer.
*
- * @param[in] p_reg Instance.
- * @param[in] p_buffer Pointer to the buffer with data to send.
- * @param[in] length Maximum number of data bytes to transmit.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_buffer Pointer to the buffer with data to send.
+ * @param[in] length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t const * p_buffer,
@@ -426,7 +409,7 @@ __STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
/**
* @brief Function for getting number of bytes transmitted in the last transaction.
*
- * @param[in] p_reg Instance.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @retval Amount of bytes transmitted.
*/
@@ -435,18 +418,18 @@ __STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg);
/**
* @brief Function for setting the receive buffer.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
- * @param[in] p_buffer Pointer to the buffer for received data.
- * @param[in] length Maximum number of data bytes to receive.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] p_buffer Pointer to the buffer for received data.
+ * @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
- uint8_t * p_buffer,
- size_t length);
+ uint8_t * p_buffer,
+ size_t length);
/**
* @brief Function for getting number of bytes received in the last transaction.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @retval Amount of bytes received.
*/
@@ -460,7 +443,6 @@ __STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_eve
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
(void)dummy;
#endif
-
}
__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
@@ -474,29 +456,29 @@ __STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
}
-__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask)
+__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
{
- p_reg->SHORTS |= shorts_mask;
+ p_reg->SHORTS |= mask;
}
-__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask)
+__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
{
- p_reg->SHORTS &= ~(shorts_mask);
+ p_reg->SHORTS &= ~(mask);
}
-__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask)
+__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
{
- p_reg->INTENSET = int_mask;
+ p_reg->INTENSET = mask;
}
-__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask)
+__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t mask)
{
- return (bool)(p_reg->INTENSET & int_mask);
+ return (bool)(p_reg->INTENSET & mask);
}
-__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask)
+__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
{
- p_reg->INTENCLR = int_mask;
+ p_reg->INTENCLR = mask;
}
#if defined(DPPI_PRESENT)
@@ -599,8 +581,8 @@ __STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_
}
__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
- nrf_uarte_parity_t parity,
- nrf_uarte_hwfc_t hwfc)
+ nrf_uarte_parity_t parity,
+ nrf_uarte_hwfc_t hwfc)
{
p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc;
}
@@ -624,8 +606,8 @@ __STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg)
}
__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
- uint8_t * p_buffer,
- size_t length)
+ uint8_t * p_buffer,
+ size_t length)
{
p_reg->RXD.PTR = (uint32_t)p_buffer;
p_reg->RXD.MAXCNT = length;
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_usbd.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_usbd.h
index 1f87cc78c..99dde35f7 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_usbd.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_usbd.h
@@ -46,46 +46,39 @@ extern "C" {
* peripheral.
*/
-/**
- * @brief USBD tasks
- */
+/** @brief USBD tasks. */
typedef enum
{
- /*lint -save -e30*/
- NRF_USBD_TASK_STARTEPIN0 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[0] ), /**< Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables control endpoint IN 0 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPIN1 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[1] ), /**< Captures the EPIN[1].PTR, EPIN[1].MAXCNT and EPIN[1].CONFIG registers values, and enables data endpoint IN 1 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPIN2 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[2] ), /**< Captures the EPIN[2].PTR, EPIN[2].MAXCNT and EPIN[2].CONFIG registers values, and enables data endpoint IN 2 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPIN3 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[3] ), /**< Captures the EPIN[3].PTR, EPIN[3].MAXCNT and EPIN[3].CONFIG registers values, and enables data endpoint IN 3 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPIN4 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[4] ), /**< Captures the EPIN[4].PTR, EPIN[4].MAXCNT and EPIN[4].CONFIG registers values, and enables data endpoint IN 4 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPIN5 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[5] ), /**< Captures the EPIN[5].PTR, EPIN[5].MAXCNT and EPIN[5].CONFIG registers values, and enables data endpoint IN 5 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPIN6 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[6] ), /**< Captures the EPIN[6].PTR, EPIN[6].MAXCNT and EPIN[6].CONFIG registers values, and enables data endpoint IN 6 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPIN7 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[7] ), /**< Captures the EPIN[7].PTR, EPIN[7].MAXCNT and EPIN[7].CONFIG registers values, and enables data endpoint IN 7 to respond to traffic from host */
- NRF_USBD_TASK_STARTISOIN = offsetof(NRF_USBD_Type, TASKS_STARTISOIN ), /**< Captures the ISOIN.PTR, ISOIN.MAXCNT and ISOIN.CONFIG registers values, and enables sending data on iso endpoint 8 */
- NRF_USBD_TASK_STARTEPOUT0 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[0]), /**< Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables control endpoint 0 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPOUT1 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[1]), /**< Captures the EPOUT[1].PTR, EPOUT[1].MAXCNT and EPOUT[1].CONFIG registers values, and enables data endpoint 1 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPOUT2 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[2]), /**< Captures the EPOUT[2].PTR, EPOUT[2].MAXCNT and EPOUT[2].CONFIG registers values, and enables data endpoint 2 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPOUT3 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[3]), /**< Captures the EPOUT[3].PTR, EPOUT[3].MAXCNT and EPOUT[3].CONFIG registers values, and enables data endpoint 3 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPOUT4 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[4]), /**< Captures the EPOUT[4].PTR, EPOUT[4].MAXCNT and EPOUT[4].CONFIG registers values, and enables data endpoint 4 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPOUT5 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[5]), /**< Captures the EPOUT[5].PTR, EPOUT[5].MAXCNT and EPOUT[5].CONFIG registers values, and enables data endpoint 5 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPOUT6 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[6]), /**< Captures the EPOUT[6].PTR, EPOUT[6].MAXCNT and EPOUT[6].CONFIG registers values, and enables data endpoint 6 to respond to traffic from host */
- NRF_USBD_TASK_STARTEPOUT7 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[7]), /**< Captures the EPOUT[7].PTR, EPOUT[7].MAXCNT and EPOUT[7].CONFIG registers values, and enables data endpoint 7 to respond to traffic from host */
- NRF_USBD_TASK_STARTISOOUT = offsetof(NRF_USBD_Type, TASKS_STARTISOOUT ), /**< Captures the ISOOUT.PTR, ISOOUT.MAXCNT and ISOOUT.CONFIG registers values, and enables receiving of data on iso endpoint 8 */
- NRF_USBD_TASK_EP0RCVOUT = offsetof(NRF_USBD_Type, TASKS_EP0RCVOUT ), /**< Allows OUT data stage on control endpoint 0 */
- NRF_USBD_TASK_EP0STATUS = offsetof(NRF_USBD_Type, TASKS_EP0STATUS ), /**< Allows status stage on control endpoint 0 */
- NRF_USBD_TASK_EP0STALL = offsetof(NRF_USBD_Type, TASKS_EP0STALL ), /**< STALLs data and status stage on control endpoint 0 */
- NRF_USBD_TASK_DRIVEDPDM = offsetof(NRF_USBD_Type, TASKS_DPDMDRIVE ), /**< Forces D+ and D-lines to the state defined in the DPDMVALUE register */
- NRF_USBD_TASK_NODRIVEDPDM = offsetof(NRF_USBD_Type, TASKS_DPDMNODRIVE ), /**< Stops forcing D+ and D- lines to any state (USB engine takes control) */
- /*lint -restore*/
+ NRF_USBD_TASK_STARTEPIN0 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[0] ), /**< Captures the EPIN[0].PTR, EPIN[0].MAXCNT, and EPIN[0].CONFIG registers values, and enables control endpoint IN 0 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPIN1 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[1] ), /**< Captures the EPIN[1].PTR, EPIN[1].MAXCNT, and EPIN[1].CONFIG registers values, and enables data endpoint IN 1 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPIN2 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[2] ), /**< Captures the EPIN[2].PTR, EPIN[2].MAXCNT, and EPIN[2].CONFIG registers values, and enables data endpoint IN 2 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPIN3 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[3] ), /**< Captures the EPIN[3].PTR, EPIN[3].MAXCNT, and EPIN[3].CONFIG registers values, and enables data endpoint IN 3 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPIN4 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[4] ), /**< Captures the EPIN[4].PTR, EPIN[4].MAXCNT, and EPIN[4].CONFIG registers values, and enables data endpoint IN 4 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPIN5 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[5] ), /**< Captures the EPIN[5].PTR, EPIN[5].MAXCNT, and EPIN[5].CONFIG registers values, and enables data endpoint IN 5 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPIN6 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[6] ), /**< Captures the EPIN[6].PTR, EPIN[6].MAXCNT, and EPIN[6].CONFIG registers values, and enables data endpoint IN 6 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPIN7 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[7] ), /**< Captures the EPIN[7].PTR, EPIN[7].MAXCNT, and EPIN[7].CONFIG registers values, and enables data endpoint IN 7 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTISOIN = offsetof(NRF_USBD_Type, TASKS_STARTISOIN ), /**< Captures the ISOIN.PTR, ISOIN.MAXCNT, and ISOIN.CONFIG registers values, and enables sending data on ISO endpoint 8. */
+ NRF_USBD_TASK_STARTEPOUT0 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[0]), /**< Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT, and EPOUT[0].CONFIG registers values, and enables control endpoint 0 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPOUT1 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[1]), /**< Captures the EPOUT[1].PTR, EPOUT[1].MAXCNT, and EPOUT[1].CONFIG registers values, and enables data endpoint 1 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPOUT2 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[2]), /**< Captures the EPOUT[2].PTR, EPOUT[2].MAXCNT, and EPOUT[2].CONFIG registers values, and enables data endpoint 2 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPOUT3 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[3]), /**< Captures the EPOUT[3].PTR, EPOUT[3].MAXCNT, and EPOUT[3].CONFIG registers values, and enables data endpoint 3 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPOUT4 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[4]), /**< Captures the EPOUT[4].PTR, EPOUT[4].MAXCNT, and EPOUT[4].CONFIG registers values, and enables data endpoint 4 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPOUT5 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[5]), /**< Captures the EPOUT[5].PTR, EPOUT[5].MAXCNT, and EPOUT[5].CONFIG registers values, and enables data endpoint 5 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPOUT6 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[6]), /**< Captures the EPOUT[6].PTR, EPOUT[6].MAXCNT, and EPOUT[6].CONFIG registers values, and enables data endpoint 6 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTEPOUT7 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[7]), /**< Captures the EPOUT[7].PTR, EPOUT[7].MAXCNT, and EPOUT[7].CONFIG registers values, and enables data endpoint 7 to respond to traffic from host. */
+ NRF_USBD_TASK_STARTISOOUT = offsetof(NRF_USBD_Type, TASKS_STARTISOOUT ), /**< Captures the ISOOUT.PTR, ISOOUT.MAXCNT, and ISOOUT.CONFIG registers values, and enables receiving of data on ISO endpoint 8. */
+ NRF_USBD_TASK_EP0RCVOUT = offsetof(NRF_USBD_Type, TASKS_EP0RCVOUT ), /**< Allows OUT data stage on the control endpoint 0. */
+ NRF_USBD_TASK_EP0STATUS = offsetof(NRF_USBD_Type, TASKS_EP0STATUS ), /**< Allows status stage on the control endpoint 0. */
+ NRF_USBD_TASK_EP0STALL = offsetof(NRF_USBD_Type, TASKS_EP0STALL ), /**< STALLs data and status stage on the control endpoint 0. */
+ NRF_USBD_TASK_DRIVEDPDM = offsetof(NRF_USBD_Type, TASKS_DPDMDRIVE ), /**< Forces D+ and D-lines to the state defined in the DPDMVALUE register. */
+ NRF_USBD_TASK_NODRIVEDPDM = offsetof(NRF_USBD_Type, TASKS_DPDMNODRIVE ), /**< Stops forcing D+ and D- lines to any state (USB engine takes control). */
}nrf_usbd_task_t;
-/**
- * @brief USBD events
- */
+/** @brief USBD events. */
typedef enum
{
- /*lint -save -e30*/
- NRF_USBD_EVENT_USBRESET = offsetof(NRF_USBD_Type, EVENTS_USBRESET ), /**< Signals that a USB reset condition has been detected on the USB lines */
- NRF_USBD_EVENT_STARTED = offsetof(NRF_USBD_Type, EVENTS_STARTED ), /**< Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG, or EPOUT[n].PTR, EPOUT[n].MAXCNT and EPOUT[n].CONFIG registers have been captured on all endpoints reported in the EPSTATUS register */
+ NRF_USBD_EVENT_USBRESET = offsetof(NRF_USBD_Type, EVENTS_USBRESET ), /**< Signals that a USB reset condition is detected on the USB lines. */
+ NRF_USBD_EVENT_STARTED = offsetof(NRF_USBD_Type, EVENTS_STARTED ), /**< Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG, or EPOUT[n].PTR, EPOUT[n].MAXCNT, and EPOUT[n].CONFIG registers have been captured on all endpoints reported in the EPSTATUS register. */
NRF_USBD_EVENT_ENDEPIN0 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[0] ), /**< The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software. */
NRF_USBD_EVENT_ENDEPIN1 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[1] ), /**< The whole EPIN[1] buffer has been consumed. The RAM buffer can be accessed safely by software. */
NRF_USBD_EVENT_ENDEPIN2 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[2] ), /**< The whole EPIN[2] buffer has been consumed. The RAM buffer can be accessed safely by software. */
@@ -94,7 +87,7 @@ typedef enum
NRF_USBD_EVENT_ENDEPIN5 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[5] ), /**< The whole EPIN[5] buffer has been consumed. The RAM buffer can be accessed safely by software. */
NRF_USBD_EVENT_ENDEPIN6 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[6] ), /**< The whole EPIN[6] buffer has been consumed. The RAM buffer can be accessed safely by software. */
NRF_USBD_EVENT_ENDEPIN7 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[7] ), /**< The whole EPIN[7] buffer has been consumed. The RAM buffer can be accessed safely by software. */
- NRF_USBD_EVENT_EP0DATADONE = offsetof(NRF_USBD_Type, EVENTS_EP0DATADONE), /**< An acknowledged data transfer has taken place on the control endpoint */
+ NRF_USBD_EVENT_EP0DATADONE = offsetof(NRF_USBD_Type, EVENTS_EP0DATADONE), /**< An acknowledged data transfer has taken place on the control endpoint. */
NRF_USBD_EVENT_ENDISOIN0 = offsetof(NRF_USBD_Type, EVENTS_ENDISOIN ), /**< The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */
NRF_USBD_EVENT_ENDEPOUT0 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[0]), /**< The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software. */
NRF_USBD_EVENT_ENDEPOUT1 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[1]), /**< The whole EPOUT[1] buffer has been consumed. The RAM buffer can be accessed safely by software. */
@@ -105,67 +98,62 @@ typedef enum
NRF_USBD_EVENT_ENDEPOUT6 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[6]), /**< The whole EPOUT[6] buffer has been consumed. The RAM buffer can be accessed safely by software. */
NRF_USBD_EVENT_ENDEPOUT7 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[7]), /**< The whole EPOUT[7] buffer has been consumed. The RAM buffer can be accessed safely by software. */
NRF_USBD_EVENT_ENDISOOUT0 = offsetof(NRF_USBD_Type, EVENTS_ENDISOOUT ), /**< The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */
- NRF_USBD_EVENT_SOF = offsetof(NRF_USBD_Type, EVENTS_SOF ), /**< Signals that a SOF (start of frame) condition has been detected on the USB lines */
- NRF_USBD_EVENT_USBEVENT = offsetof(NRF_USBD_Type, EVENTS_USBEVENT ), /**< An event or an error not covered by specific events has occurred, check EVENTCAUSE register to find the cause */
- NRF_USBD_EVENT_EP0SETUP = offsetof(NRF_USBD_Type, EVENTS_EP0SETUP ), /**< A valid SETUP token has been received (and acknowledged) on the control endpoint */
- NRF_USBD_EVENT_DATAEP = offsetof(NRF_USBD_Type, EVENTS_EPDATA ), /**< A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
- /*lint -restore*/
+ NRF_USBD_EVENT_SOF = offsetof(NRF_USBD_Type, EVENTS_SOF ), /**< Signals that a SOF (start of frame) condition has been detected on the USB lines. */
+ NRF_USBD_EVENT_USBEVENT = offsetof(NRF_USBD_Type, EVENTS_USBEVENT ), /**< An event or an error not covered by the specified events has occurred, check EVENTCAUSE register to find the cause. */
+ NRF_USBD_EVENT_EP0SETUP = offsetof(NRF_USBD_Type, EVENTS_EP0SETUP ), /**< A valid SETUP token has been received (and acknowledged) on the control endpoint. */
+ NRF_USBD_EVENT_DATAEP = offsetof(NRF_USBD_Type, EVENTS_EPDATA ), /**< A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register. */
}nrf_usbd_event_t;
-/**
- * @brief USBD shorts
- */
+/** @brief USBD shorts. */
typedef enum
{
- NRF_USBD_SHORT_EP0DATADONE_STARTEPIN0_MASK = USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk , /**< Shortcut between EP0DATADONE event and STARTEPIN0 task */
- NRF_USBD_SHORT_EP0DATADONE_STARTEPOUT0_MASK = USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk, /**< Shortcut between EP0DATADONE event and STARTEPOUT0 task */
- NRF_USBD_SHORT_EP0DATADONE_EP0STATUS_MASK = USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk , /**< Shortcut between EP0DATADONE event and EP0STATUS task */
- NRF_USBD_SHORT_ENDEPOUT0_EP0STATUS_MASK = USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk , /**< Shortcut between ENDEPOUT[0] event and EP0STATUS task */
- NRF_USBD_SHORT_ENDEPOUT0_EP0RCVOUT_MASK = USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk , /**< Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */
+ NRF_USBD_SHORT_EP0DATADONE_STARTEPIN0_MASK = USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk , /**< Shortcut between EP0DATADONE event and STARTEPIN0 task. */
+ NRF_USBD_SHORT_EP0DATADONE_STARTEPOUT0_MASK = USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk, /**< Shortcut between EP0DATADONE event and STARTEPOUT0 task. */
+ NRF_USBD_SHORT_EP0DATADONE_EP0STATUS_MASK = USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk , /**< Shortcut between EP0DATADONE event and EP0STATUS task. */
+ NRF_USBD_SHORT_ENDEPOUT0_EP0STATUS_MASK = USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk , /**< Shortcut between ENDEPOUT[0] event and EP0STATUS task. */
+ NRF_USBD_SHORT_ENDEPOUT0_EP0RCVOUT_MASK = USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk , /**< Shortcut between ENDEPOUT[0] event and EP0RCVOUT task. */
}nrf_usbd_short_mask_t;
-/**
- * @brief USBD interrupts
- */
+/** @brief USBD interrupts. */
typedef enum
{
- NRF_USBD_INT_USBRESET_MASK = USBD_INTEN_USBRESET_Msk , /**< Enable or disable interrupt for USBRESET event */
- NRF_USBD_INT_STARTED_MASK = USBD_INTEN_STARTED_Msk , /**< Enable or disable interrupt for STARTED event */
- NRF_USBD_INT_ENDEPIN0_MASK = USBD_INTEN_ENDEPIN0_Msk , /**< Enable or disable interrupt for ENDEPIN[0] event */
- NRF_USBD_INT_ENDEPIN1_MASK = USBD_INTEN_ENDEPIN1_Msk , /**< Enable or disable interrupt for ENDEPIN[1] event */
- NRF_USBD_INT_ENDEPIN2_MASK = USBD_INTEN_ENDEPIN2_Msk , /**< Enable or disable interrupt for ENDEPIN[2] event */
- NRF_USBD_INT_ENDEPIN3_MASK = USBD_INTEN_ENDEPIN3_Msk , /**< Enable or disable interrupt for ENDEPIN[3] event */
- NRF_USBD_INT_ENDEPIN4_MASK = USBD_INTEN_ENDEPIN4_Msk , /**< Enable or disable interrupt for ENDEPIN[4] event */
- NRF_USBD_INT_ENDEPIN5_MASK = USBD_INTEN_ENDEPIN5_Msk , /**< Enable or disable interrupt for ENDEPIN[5] event */
- NRF_USBD_INT_ENDEPIN6_MASK = USBD_INTEN_ENDEPIN6_Msk , /**< Enable or disable interrupt for ENDEPIN[6] event */
- NRF_USBD_INT_ENDEPIN7_MASK = USBD_INTEN_ENDEPIN7_Msk , /**< Enable or disable interrupt for ENDEPIN[7] event */
- NRF_USBD_INT_EP0DATADONE_MASK = USBD_INTEN_EP0DATADONE_Msk, /**< Enable or disable interrupt for EP0DATADONE event */
- NRF_USBD_INT_ENDISOIN0_MASK = USBD_INTEN_ENDISOIN_Msk , /**< Enable or disable interrupt for ENDISOIN[0] event */
- NRF_USBD_INT_ENDEPOUT0_MASK = USBD_INTEN_ENDEPOUT0_Msk , /**< Enable or disable interrupt for ENDEPOUT[0] event */
- NRF_USBD_INT_ENDEPOUT1_MASK = USBD_INTEN_ENDEPOUT1_Msk , /**< Enable or disable interrupt for ENDEPOUT[1] event */
- NRF_USBD_INT_ENDEPOUT2_MASK = USBD_INTEN_ENDEPOUT2_Msk , /**< Enable or disable interrupt for ENDEPOUT[2] event */
- NRF_USBD_INT_ENDEPOUT3_MASK = USBD_INTEN_ENDEPOUT3_Msk , /**< Enable or disable interrupt for ENDEPOUT[3] event */
- NRF_USBD_INT_ENDEPOUT4_MASK = USBD_INTEN_ENDEPOUT4_Msk , /**< Enable or disable interrupt for ENDEPOUT[4] event */
- NRF_USBD_INT_ENDEPOUT5_MASK = USBD_INTEN_ENDEPOUT5_Msk , /**< Enable or disable interrupt for ENDEPOUT[5] event */
- NRF_USBD_INT_ENDEPOUT6_MASK = USBD_INTEN_ENDEPOUT6_Msk , /**< Enable or disable interrupt for ENDEPOUT[6] event */
- NRF_USBD_INT_ENDEPOUT7_MASK = USBD_INTEN_ENDEPOUT7_Msk , /**< Enable or disable interrupt for ENDEPOUT[7] event */
- NRF_USBD_INT_ENDISOOUT0_MASK = USBD_INTEN_ENDISOOUT_Msk , /**< Enable or disable interrupt for ENDISOOUT[0] event */
- NRF_USBD_INT_SOF_MASK = USBD_INTEN_SOF_Msk , /**< Enable or disable interrupt for SOF event */
- NRF_USBD_INT_USBEVENT_MASK = USBD_INTEN_USBEVENT_Msk , /**< Enable or disable interrupt for USBEVENT event */
- NRF_USBD_INT_EP0SETUP_MASK = USBD_INTEN_EP0SETUP_Msk , /**< Enable or disable interrupt for EP0SETUP event */
- NRF_USBD_INT_DATAEP_MASK = USBD_INTEN_EPDATA_Msk , /**< Enable or disable interrupt for EPDATA event */
+ NRF_USBD_INT_USBRESET_MASK = USBD_INTEN_USBRESET_Msk , /**< Enable or disable interrupt for USBRESET event. */
+ NRF_USBD_INT_STARTED_MASK = USBD_INTEN_STARTED_Msk , /**< Enable or disable interrupt for STARTED event. */
+ NRF_USBD_INT_ENDEPIN0_MASK = USBD_INTEN_ENDEPIN0_Msk , /**< Enable or disable interrupt for ENDEPIN[0] event. */
+ NRF_USBD_INT_ENDEPIN1_MASK = USBD_INTEN_ENDEPIN1_Msk , /**< Enable or disable interrupt for ENDEPIN[1] event. */
+ NRF_USBD_INT_ENDEPIN2_MASK = USBD_INTEN_ENDEPIN2_Msk , /**< Enable or disable interrupt for ENDEPIN[2] event. */
+ NRF_USBD_INT_ENDEPIN3_MASK = USBD_INTEN_ENDEPIN3_Msk , /**< Enable or disable interrupt for ENDEPIN[3] event. */
+ NRF_USBD_INT_ENDEPIN4_MASK = USBD_INTEN_ENDEPIN4_Msk , /**< Enable or disable interrupt for ENDEPIN[4] event. */
+ NRF_USBD_INT_ENDEPIN5_MASK = USBD_INTEN_ENDEPIN5_Msk , /**< Enable or disable interrupt for ENDEPIN[5] event. */
+ NRF_USBD_INT_ENDEPIN6_MASK = USBD_INTEN_ENDEPIN6_Msk , /**< Enable or disable interrupt for ENDEPIN[6] event. */
+ NRF_USBD_INT_ENDEPIN7_MASK = USBD_INTEN_ENDEPIN7_Msk , /**< Enable or disable interrupt for ENDEPIN[7] event. */
+ NRF_USBD_INT_EP0DATADONE_MASK = USBD_INTEN_EP0DATADONE_Msk, /**< Enable or disable interrupt for EP0DATADONE event. */
+ NRF_USBD_INT_ENDISOIN0_MASK = USBD_INTEN_ENDISOIN_Msk , /**< Enable or disable interrupt for ENDISOIN[0] event. */
+ NRF_USBD_INT_ENDEPOUT0_MASK = USBD_INTEN_ENDEPOUT0_Msk , /**< Enable or disable interrupt for ENDEPOUT[0] event. */
+ NRF_USBD_INT_ENDEPOUT1_MASK = USBD_INTEN_ENDEPOUT1_Msk , /**< Enable or disable interrupt for ENDEPOUT[1] event. */
+ NRF_USBD_INT_ENDEPOUT2_MASK = USBD_INTEN_ENDEPOUT2_Msk , /**< Enable or disable interrupt for ENDEPOUT[2] event. */
+ NRF_USBD_INT_ENDEPOUT3_MASK = USBD_INTEN_ENDEPOUT3_Msk , /**< Enable or disable interrupt for ENDEPOUT[3] event. */
+ NRF_USBD_INT_ENDEPOUT4_MASK = USBD_INTEN_ENDEPOUT4_Msk , /**< Enable or disable interrupt for ENDEPOUT[4] event. */
+ NRF_USBD_INT_ENDEPOUT5_MASK = USBD_INTEN_ENDEPOUT5_Msk , /**< Enable or disable interrupt for ENDEPOUT[5] event. */
+ NRF_USBD_INT_ENDEPOUT6_MASK = USBD_INTEN_ENDEPOUT6_Msk , /**< Enable or disable interrupt for ENDEPOUT[6] event. */
+ NRF_USBD_INT_ENDEPOUT7_MASK = USBD_INTEN_ENDEPOUT7_Msk , /**< Enable or disable interrupt for ENDEPOUT[7] event. */
+ NRF_USBD_INT_ENDISOOUT0_MASK = USBD_INTEN_ENDISOOUT_Msk , /**< Enable or disable interrupt for ENDISOOUT[0] event. */
+ NRF_USBD_INT_SOF_MASK = USBD_INTEN_SOF_Msk , /**< Enable or disable interrupt for SOF event. */
+ NRF_USBD_INT_USBEVENT_MASK = USBD_INTEN_USBEVENT_Msk , /**< Enable or disable interrupt for USBEVENT event. */
+ NRF_USBD_INT_EP0SETUP_MASK = USBD_INTEN_EP0SETUP_Msk , /**< Enable or disable interrupt for EP0SETUP event. */
+ NRF_USBD_INT_DATAEP_MASK = USBD_INTEN_EPDATA_Msk , /**< Enable or disable interrupt for EPDATA event. */
}nrf_usbd_int_mask_t;
/**
- * @brief Function for activating a specific USBD task.
+ * @brief Function for activating the specified USBD task.
*
- * @param task Task.
+ * @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_usbd_task_trigger(nrf_usbd_task_t task);
/**
- * @brief Function for returning the address of a specific USBD task register.
+ * @brief Function for returning the address of the specified USBD task register.
*
* @param task Task.
*
@@ -174,96 +162,96 @@ __STATIC_INLINE void nrf_usbd_task_trigger(nrf_usbd_task_t task);
__STATIC_INLINE uint32_t nrf_usbd_task_address_get(nrf_usbd_task_t task);
/**
- * @brief Function for clearing a specific event.
+ * @brief Function for clearing the specified event.
*
* @param event Event.
*/
__STATIC_INLINE void nrf_usbd_event_clear(nrf_usbd_event_t event);
/**
- * @brief Function for returning the state of a specific event.
+ * @brief Function for retrieving the state of the USBD event.
*
- * @param event Event.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_usbd_event_check(nrf_usbd_event_t event);
/**
- * @brief Function for getting and clearing the state of specific event
+ * @brief Function for getting and clearing the state of the specified event.
*
* This function checks the state of the event and clears it.
*
- * @param event Event.
+ * @param event Event.
*
- * @retval true If the event was set.
- * @retval false If the event was not set.
+ * @retval true The event was set.
+ * @retval false The event was not set.
*/
__STATIC_INLINE bool nrf_usbd_event_get_and_clear(nrf_usbd_event_t event);
/**
- * @brief Function for returning the address of a specific USBD event register.
+ * @brief Function for returning the address of the specified USBD event register.
*
- * @param event Event.
+ * @param event Event.
*
* @return Address.
*/
__STATIC_INLINE uint32_t nrf_usbd_event_address_get(nrf_usbd_event_t event);
/**
- * @brief Function for setting a shortcut.
+ * @brief Function for setting shortcuts.
*
- * @param short_mask Shortcuts mask.
+ * @param mask Shortcut mask.
*/
-__STATIC_INLINE void nrf_usbd_shorts_enable(uint32_t short_mask);
+__STATIC_INLINE void nrf_usbd_shorts_enable(uint32_t mask);
/**
* @brief Function for clearing shortcuts.
*
- * @param short_mask Shortcuts mask.
+ * @param mask Shortcut mask.
*/
-__STATIC_INLINE void nrf_usbd_shorts_disable(uint32_t short_mask);
+__STATIC_INLINE void nrf_usbd_shorts_disable(uint32_t mask);
/**
- * @brief Get the shorts mask
+ * @brief Function for getting the shortcut mask.
*
- * Function returns shorts register.
+ * Function returns shortcut register.
*
- * @return Flags of currently enabled shortcuts
+ * @return Flags of the currently enabled shortcuts.
*/
__STATIC_INLINE uint32_t nrf_usbd_shorts_get(void);
/**
- * @brief Function for enabling selected interrupts.
+ * @brief Function for enabling the selected interrupts.
*
- * @param int_mask Interrupts mask.
+ * @param mask Mask of interrupts to be enabled.
*/
-__STATIC_INLINE void nrf_usbd_int_enable(uint32_t int_mask);
+__STATIC_INLINE void nrf_usbd_int_enable(uint32_t mask);
/**
- * @brief Function for retrieving the state of selected interrupts.
+ * @brief Function for retrieving the state of the selected interrupts.
*
- * @param int_mask Interrupts mask.
+ * @param mask Mask of interrupts to be checked.
*
- * @retval true If any of selected interrupts is enabled.
- * @retval false If none of selected interrupts is enabled.
+ * @retval true Any of selected interrupts is enabled.
+ * @retval false None of selected interrupts is enabled.
*/
-__STATIC_INLINE bool nrf_usbd_int_enable_check(uint32_t int_mask);
+__STATIC_INLINE bool nrf_usbd_int_enable_check(uint32_t mask);
/**
- * @brief Function for retrieving the information about enabled interrupts.
+ * @brief Function for retrieving the information about the enabled interrupts.
*
- * @return The flags of enabled interrupts.
+ * @return The flags of the enabled interrupts.
*/
__STATIC_INLINE uint32_t nrf_usbd_int_enable_get(void);
/**
- * @brief Function for disabling selected interrupts.
+ * @brief Function for disabling the selected interrupts.
*
- * @param int_mask Interrupts mask.
+ * @param mask Mask of interrupts to be disabled.
*/
-__STATIC_INLINE void nrf_usbd_int_disable(uint32_t int_mask);
+__STATIC_INLINE void nrf_usbd_int_disable(uint32_t mask);
/** @} */ /* End of nrf_usbd_hal */
@@ -277,12 +265,12 @@ __STATIC_INLINE void nrf_usbd_int_disable(uint32_t int_mask);
/**
* @internal
- * @brief Internal function for getting task/event register address
+ * @brief Internal function for getting the register address of task or event.
*
- * @oaram offset Offset of the register from the instance beginning
+ * @param[in] offset Offset of the register from the beginning of the instance.
*
- * @attention offset has to be modulo 4 value. In other case we can get hardware fault.
- * @return Pointer to the register
+ * @attention The offset must be aligned to 4. In other case, hardware fault can occur.
+ * @return Pointer to the register.
*/
__STATIC_INLINE volatile uint32_t* nrf_usbd_getRegPtr(uint32_t offset)
{
@@ -291,12 +279,12 @@ __STATIC_INLINE volatile uint32_t* nrf_usbd_getRegPtr(uint32_t offset)
/**
* @internal
- * @brief Internal function for getting task/event register address - constant version
+ * @brief Internal function for getting the register address of task or event - constant version.
*
- * @oaram offset Offset of the register from the instance beginning
+ * @param[in] offset Offset of the register from the beginning of the instance.
*
- * @attention offset has to be modulo 4 value. In other case we can get hardware fault.
- * @return Pointer to the register
+ * @attention The offset must be aligned to 4. In other case, hardware fault can occur.
+ * @return Pointer to the register.
*/
__STATIC_INLINE volatile const uint32_t* nrf_usbd_getRegPtr_c(uint32_t offset)
{
@@ -346,21 +334,21 @@ uint32_t nrf_usbd_event_address_get(nrf_usbd_event_t event)
return (uint32_t)nrf_usbd_getRegPtr_c((uint32_t)event);
}
-void nrf_usbd_shorts_enable(uint32_t short_mask)
+void nrf_usbd_shorts_enable(uint32_t mask)
{
- NRF_USBD->SHORTS |= short_mask;
+ NRF_USBD->SHORTS |= mask;
}
-void nrf_usbd_shorts_disable(uint32_t short_mask)
+void nrf_usbd_shorts_disable(uint32_t mask)
{
- if (~0U == short_mask)
+ if (~0U == mask)
{
/* Optimized version for "disable all" */
NRF_USBD->SHORTS = 0;
}
else
{
- NRF_USBD->SHORTS &= ~short_mask;
+ NRF_USBD->SHORTS &= ~mask;
}
}
@@ -369,14 +357,14 @@ uint32_t nrf_usbd_shorts_get(void)
return NRF_USBD->SHORTS;
}
-void nrf_usbd_int_enable(uint32_t int_mask)
+void nrf_usbd_int_enable(uint32_t mask)
{
- NRF_USBD->INTENSET = int_mask;
+ NRF_USBD->INTENSET = mask;
}
-bool nrf_usbd_int_enable_check(uint32_t int_mask)
+bool nrf_usbd_int_enable_check(uint32_t mask)
{
- return !!(NRF_USBD->INTENSET & int_mask);
+ return !!(NRF_USBD->INTENSET & mask);
}
uint32_t nrf_usbd_int_enable_get(void)
@@ -384,9 +372,9 @@ uint32_t nrf_usbd_int_enable_get(void)
return NRF_USBD->INTENSET;
}
-void nrf_usbd_int_disable(uint32_t int_mask)
+void nrf_usbd_int_disable(uint32_t mask)
{
- NRF_USBD->INTENCLR = int_mask;
+ NRF_USBD->INTENCLR = mask;
}
#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
@@ -401,9 +389,9 @@ void nrf_usbd_int_disable(uint32_t int_mask)
*/
/**
- * @brief Frame counter size
+ * @brief Frame counter size.
*
- * The number of counts that can be fitted into frame counter
+ * The number of counts that can be fitted into frame counter.
*/
#define NRF_USBD_FRAMECNTR_SIZE \
( (USBD_FRAMECNTR_FRAMECNTR_Msk >> USBD_FRAMECNTR_FRAMECNTR_Pos) + 1UL )
@@ -412,103 +400,105 @@ void nrf_usbd_int_disable(uint32_t int_mask)
#endif
/**
- * @brief First isochronous endpoint number
+ * @brief First isochronous endpoint number.
*
- * The number of the first isochronous endpoint
+ * The number of the first isochronous endpoint.
*/
#define NRF_USBD_EPISO_FIRST 8
/**
- * @brief Total number of IN endpoints
+ * @brief Total number of IN endpoints.
*
* Total number of IN endpoint (including ISOCHRONOUS).
*/
#define NRF_USBD_EPIN_CNT 9
/**
- * @brief Total number of OUT endpoints
+ * @brief Total number of OUT endpoints.
*
* Total number of OUT endpoint (including ISOCHRONOUS).
*/
#define NRF_USBD_EPOUT_CNT 9
-/**
- * @brief Mask of the direction bit in endpoint number
- */
+/** @brief Mask of the direction bit in an endpoint number. */
#define NRF_USBD_EP_DIR_Msk (1U << 7)
-/**
- * @brief The value of direction bit for IN endpoint direction
- */
+/** @brief The value of direction bit for the IN endpoint direction. */
#define NRF_USBD_EP_DIR_IN (1U << 7)
-/**
- * @brief The value of direction bit for OUT endpoint direction
- */
+/** @brief The value of direction bit for the OUT endpoint direction. */
#define NRF_USBD_EP_DIR_OUT (0U << 7)
/**
- * @brief Macro for making IN endpoint identifier from endpoint number
+ * @brief Macro for making the IN endpoint identifier from endpoint number.
*
- * Macro that sets direction bit to make IN endpoint
- * @param[in] epnr Endpoint number
- * @return IN Endpoint identifier
+ * Macro that sets direction bit to make IN endpoint.
+ * @param[in] epnr Endpoint number.
+ * @return IN Endpoint identifier.
*/
#define NRF_USBD_EPIN(epnr) (((uint8_t)(epnr)) | NRF_USBD_EP_DIR_IN)
/**
- * @brief Macro for making OUT endpoint identifier from endpoint number
+ * @brief Macro for making the OUT endpoint identifier from endpoint number.
*
- * Macro that sets direction bit to make OUT endpoint
- * @param[in] epnr Endpoint number
- * @return OUT Endpoint identifier
+ * Macro that sets direction bit to make OUT endpoint.
+ * @param[in] epnr Endpoint number.
+ * @return OUT Endpoint identifier.
*/
#define NRF_USBD_EPOUT(epnr) (((uint8_t)(epnr)) | NRF_USBD_EP_DIR_OUT)
/**
- * @brief Macro for extracting the endpoint number from endpoint identifier
+ * @brief Macro for extracting the endpoint number from the specified endpoint identifier.
*
* Macro that strips out the information about endpoint direction.
- * @param[in] ep Endpoint identifier
- * @return Endpoint number
+ *
+ * @param[in] ep Endpoint identifier.
+ *
+ * @return Endpoint number.
*/
#define NRF_USBD_EP_NR_GET(ep) ((uint8_t)(((uint8_t)(ep)) & 0xFU))
/**
- * @brief Macro for checking endpoint direction
+ * @brief Macro for checking the endpoint direction.
*
- * This macro checks if given endpoint has IN direction
- * @param ep Endpoint identifier
- * @retval true If the endpoint direction is IN
- * @retval false If the endpoint direction is OUT
+ * This macro checks if the specified endpoint has the IN direction.
+ *
+ * @param ep Endpoint identifier.
+ *
+ * @retval true The endpoint direction is IN.
+ * @retval false The endpoint direction is OUT.
*/
#define NRF_USBD_EPIN_CHECK(ep) ( (((uint8_t)(ep)) & NRF_USBD_EP_DIR_Msk) == NRF_USBD_EP_DIR_IN )
/**
- * @brief Macro for checking endpoint direction
+ * @brief Macro for checking endpoint direction.
+ *
+ * This macro checks if given endpoint has OUT direction.
*
- * This macro checks if given endpoint has OUT direction
* @param ep Endpoint identifier
- * @retval true If the endpoint direction is OUT
- * @retval false If the endpoint direction is IN
+ *
+ * @retval true The endpoint direction is OUT
+ * @retval false The endpoint direction is IN
*/
#define NRF_USBD_EPOUT_CHECK(ep) ( (((uint8_t)(ep)) & NRF_USBD_EP_DIR_Msk) == NRF_USBD_EP_DIR_OUT )
/**
- * @brief Macro for checking if endpoint is isochronous
+ * @brief Macro for checking if endpoint is isochronous.
*
- * @param ep It can be endpoint identifier or just endpoint number to check
- * @retval true The endpoint is isochronous type
- * @retval false The endpoint is bulk of interrupt type
+ * @param ep It can be endpoint identifier or just endpoint number to be checked.
+ *
+ * @retval true The endpoint is isochronous type.
+ * @retval false The endpoint is bulk of interrupt type.
*/
#define NRF_USBD_EPISO_CHECK(ep) (NRF_USBD_EP_NR_GET(ep) >= NRF_USBD_EPISO_FIRST)
/**
- * @brief Macro for checking if given number is valid endpoint number
+ * @brief Macro for checking if given number is valid endpoint number.
*
- * @param ep Endpoint number to check
- * @retval true The endpoint is valid
- * @retval false The endpoint is not valid
+ * @param ep Endpoint number to be checked.
+ *
+ * @retval true The endpoint is valid.
+ * @retval false The endpoint is not valid.
*/
#define NRF_USBD_EP_VALIDATE(ep) ( \
(NRF_USBD_EPIN_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < NRF_USBD_EPIN_CNT)) \
@@ -517,7 +507,7 @@ void nrf_usbd_int_disable(uint32_t int_mask)
)
/**
- * @brief Not isochronous data frame received
+ * @brief Not isochronous data frame received.
*
* Special value returned by @ref nrf_usbd_episoout_size_get function that means that
* data frame was not received at all.
@@ -526,25 +516,21 @@ void nrf_usbd_int_disable(uint32_t int_mask)
*/
#define NRF_USBD_EPISOOUT_NO_DATA ((size_t)(-1))
-/**
- * @brief EVENTCAUSE register bit masks
- */
+/** @brief EVENTCAUSE register bit masks. */
typedef enum
{
NRF_USBD_EVENTCAUSE_ISOOUTCRC_MASK = USBD_EVENTCAUSE_ISOOUTCRC_Msk, /**< CRC error was detected on isochronous OUT endpoint 8. */
NRF_USBD_EVENTCAUSE_SUSPEND_MASK = USBD_EVENTCAUSE_SUSPEND_Msk, /**< Signals that the USB lines have been seen idle long enough for the device to enter suspend. */
NRF_USBD_EVENTCAUSE_RESUME_MASK = USBD_EVENTCAUSE_RESUME_Msk, /**< Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. */
- NRF_USBD_EVENTCAUSE_WUREQ_MASK = USBD_EVENTCAUSE_USBWUALLOWED_Msk, /**< The USBD peripheral has exited Low Power mode */
- NRF_USBD_EVENTCAUSE_READY_MASK = USBD_EVENTCAUSE_READY_Msk, /**< MAC is ready for normal operation, rised few us after USBD enabling */
+ NRF_USBD_EVENTCAUSE_WUREQ_MASK = USBD_EVENTCAUSE_USBWUALLOWED_Msk, /**< The USBD peripheral has exited Low Power mode. */
+ NRF_USBD_EVENTCAUSE_READY_MASK = USBD_EVENTCAUSE_READY_Msk, /**< MAC is ready for normal operation, rised few us after USBD enabling. */
}nrf_usbd_eventcause_mask_t;
-/**
- * @brief DPDMVALUE register
- */
+/** @brief DPDMVALUE register. */
typedef enum
{
- /**Generate Resume signal. Signal is generated for 50 us or 5 ms,
- * depending on bus state */
+ /** Generate RESUME signal. Signal is generated for 50 us or 5 ms,
+ * depending on bus state. */
NRF_USBD_DPDMVALUE_RESUME = USBD_DPDMVALUE_STATE_Resume,
/** D+ Forced high, D- forced low (J state) */
NRF_USBD_DPDMVALUE_J = USBD_DPDMVALUE_STATE_J,
@@ -552,19 +538,15 @@ typedef enum
NRF_USBD_DPMVALUE_K = USBD_DPDMVALUE_STATE_K
}nrf_usbd_dpdmvalue_t;
-/**
- * @brief Dtoggle value or operation
- */
+/** @brief Data toggle value or operation. */
typedef enum
{
- NRF_USBD_DTOGGLE_NOP = USBD_DTOGGLE_VALUE_Nop, /**< No operation - do not change current data toggle on selected endpoint */
- NRF_USBD_DTOGGLE_DATA0 = USBD_DTOGGLE_VALUE_Data0,/**< Data toggle is DATA0 on selected endpoint */
- NRF_USBD_DTOGGLE_DATA1 = USBD_DTOGGLE_VALUE_Data1 /**< Data toggle is DATA1 on selected endpoint */
+ NRF_USBD_DTOGGLE_NOP = USBD_DTOGGLE_VALUE_Nop, /**< No operation - do not change the current data toggle on the selected endpoint. */
+ NRF_USBD_DTOGGLE_DATA0 = USBD_DTOGGLE_VALUE_Data0,/**< Data toggle is DATA0 on the selected endpoint. */
+ NRF_USBD_DTOGGLE_DATA1 = USBD_DTOGGLE_VALUE_Data1 /**< Data toggle is DATA1 on the selected endpoint. */
}nrf_usbd_dtoggle_t;
-/**
- * @brief EPSTATUS bit masks
- */
+/** @brief EPSTATUS bit masks. */
typedef enum
{
NRF_USBD_EPSTATUS_EPIN0_MASK = USBD_EPSTATUS_EPIN0_Msk,
@@ -586,9 +568,7 @@ typedef enum
NRF_USBD_EPSTATUS_EPOUT7_MASK = USBD_EPSTATUS_EPOUT7_Msk,
}nrf_usbd_epstatus_mask_t;
-/**
- * @brief DATAEPSTATUS bit masks
- */
+/** @brief DATAEPSTATUS bit masks. */
typedef enum
{
NRF_USBD_EPDATASTATUS_EPIN1_MASK = USBD_EPDATASTATUS_EPIN1_Msk,
@@ -608,50 +588,42 @@ typedef enum
NRF_USBD_EPDATASTATUS_EPOUT7_MASK = USBD_EPDATASTATUS_EPOUT7_Msk,
}nrf_usbd_dataepstatus_mask_t;
-/**
- * @brief ISOSPLIT configurations
- */
+/** @brief ISOSPLIT configurations. */
typedef enum
{
- NRF_USBD_ISOSPLIT_ONEDIR = USBD_ISOSPLIT_SPLIT_OneDir, /**< Full buffer dedicated to either iso IN or OUT */
- NRF_USBD_ISOSPLIT_HALF = USBD_ISOSPLIT_SPLIT_HalfIN, /**< Buffer divided in half */
+ NRF_USBD_ISOSPLIT_ONEDIR = USBD_ISOSPLIT_SPLIT_OneDir, /**< Full buffer dedicated to either ISO IN or OUT. */
+ NRF_USBD_ISOSPLIT_HALF = USBD_ISOSPLIT_SPLIT_HalfIN, /**< Buffer divided in half. */
}nrf_usbd_isosplit_t;
-/**
- * @brief ISOINCONFIG configurations
- */
+/** @brief ISOINCONFIG configurations. */
typedef enum
{
- NRF_USBD_ISOINCONFIG_NORESP = USBD_ISOINCONFIG_RESPONSE_NoResp, /**< Endpoint does not respond to an ISO IN token when no data is ready */
- NRF_USBD_ISOINCONFIG_ZERODATA = USBD_ISOINCONFIG_RESPONSE_ZeroData, /**< Endpoint responds with a zero-length data packet to an ISO IN token when no data is ready */
+ NRF_USBD_ISOINCONFIG_NORESP = USBD_ISOINCONFIG_RESPONSE_NoResp, /**< Endpoint does not respond to an ISO IN token when no data is ready. */
+ NRF_USBD_ISOINCONFIG_ZERODATA = USBD_ISOINCONFIG_RESPONSE_ZeroData, /**< Endpoint responds with a zero-length data packet to an ISO IN token when no data is ready. */
}nrf_usbd_isoinconfig_t;
-/**
- * @brief Function for enabling USBD
- */
+/** @brief Function for enabling the USBD. */
__STATIC_INLINE void nrf_usbd_enable(void);
-/**
- * @brief Function for disabling USBD
- */
+/** @brief Function for disabling the USBD. */
__STATIC_INLINE void nrf_usbd_disable(void);
/**
- * @brief Function for getting EVENTCAUSE register
+ * @brief Function for getting the EVENTCAUSE register.
*
- * @return Flag values defined in @ref nrf_usbd_eventcause_mask_t
+ * @return Flag values defined in @ref nrf_usbd_eventcause_mask_t.
*/
__STATIC_INLINE uint32_t nrf_usbd_eventcause_get(void);
/**
- * @brief Function for clearing EVENTCAUSE flags
+ * @brief Function for clearing the EVENTCAUSE flags.
*
- * @param flags Flags defined in @ref nrf_usbd_eventcause_mask_t
+ * @param flags Flags defined in @ref nrf_usbd_eventcause_mask_t.
*/
__STATIC_INLINE void nrf_usbd_eventcause_clear(uint32_t flags);
/**
- * @brief Function for getting EVENTCAUSE register and clear flags that are set
+ * @brief Function for getting the EVENTCAUSE register and clearing flags that are set.
*
* The safest way to return current EVENTCAUSE register.
* All the flags that are returned would be cleared inside EVENTCAUSE register.
@@ -661,276 +633,278 @@ __STATIC_INLINE void nrf_usbd_eventcause_clear(uint32_t flags);
__STATIC_INLINE uint32_t nrf_usbd_eventcause_get_and_clear(void);
/**
- * @brief Function for getting HALTEDEPIN register value
+ * @brief Function for getting the HALTEDEPIN register value.
*
- * @param ep Endpoint number with IN/OUT flag
+ * @note Use this function for the response for GetStatus() request to endpoint.
+ * To check whether the endpoint is stalled in the code, use @ref nrf_usbd_ep_is_stall.
*
- * @return The value of HALTEDEPIN or HALTEDOUT register for selected endpoint
+ * @param ep Endpoint number with IN or OUT flag.
*
- * @note
- * Use this function for the response for GetStatus() request to endpoint.
- * To check if endpoint is stalled in the code use @ref nrf_usbd_ep_is_stall.
+ * @return The value of the HALTEDEPIN or HALTEDOUT register for the selected endpoint.
*/
__STATIC_INLINE uint32_t nrf_usbd_haltedep(uint8_t ep);
/**
- * @brief Function for checking if selected endpoint is stalled
+ * @brief Function for checking whether the selected endpoint is stalled.
*
* Function to be used as a syntax sweeter for @ref nrf_usbd_haltedep.
*
* Also as the isochronous endpoint cannot be halted - it returns always false
* if isochronous endpoint is checked.
*
- * @param ep Endpoint number with IN/OUT flag
+ * @param ep Endpoint number with IN or OUT flag.
*
- * @return The information if the enepoint is halted.
+ * @retval true The endpoint is halted.
+ * @retval false The endpoint is not halted.
*/
__STATIC_INLINE bool nrf_usbd_ep_is_stall(uint8_t ep);
/**
- * @brief Function for getting EPSTATUS register value
+ * @brief Function for getting EPSTATUS register value.
*
- * @return Flag values defined in @ref nrf_usbd_epstatus_mask_t
+ * @return Flag values defined in @ref nrf_usbd_epstatus_mask_t.
*/
__STATIC_INLINE uint32_t nrf_usbd_epstatus_get(void);
/**
- * @brief Function for clearing EPSTATUS register value
+ * @brief Function for clearing EPSTATUS register value.
*
- * @param flags Flags defined in @ref nrf_usbd_epstatus_mask_t
+ * @param flags Flags defined in @ref nrf_usbd_epstatus_mask_t.
*/
__STATIC_INLINE void nrf_usbd_epstatus_clear(uint32_t flags);
/**
- * @brief Function for getting and clearing EPSTATUS register value
+ * @brief Function for getting and clearing EPSTATUS register value.
*
* Function clears all flags in register set before returning its value.
- * @return Flag values defined in @ref nrf_usbd_epstatus_mask_t
+ *
+ * @return Flag values defined in @ref nrf_usbd_epstatus_mask_t.
*/
__STATIC_INLINE uint32_t nrf_usbd_epstatus_get_and_clear(void);
/**
- * @brief Function for getting DATAEPSTATUS register value
+ * @brief Function for getting DATAEPSTATUS register value.
*
- * @return Flag values defined in @ref nrf_usbd_dataepstatus_mask_t
+ * @return Flag values defined in @ref nrf_usbd_dataepstatus_mask_t.
*/
__STATIC_INLINE uint32_t nrf_usbd_epdatastatus_get(void);
/**
- * @brief Function for clearing DATAEPSTATUS register value
+ * @brief Function for clearing DATAEPSTATUS register value.
*
- * @param flags Flags defined in @ref nrf_usbd_dataepstatus_mask_t
+ * @param flags Flags defined in @ref nrf_usbd_dataepstatus_mask_t.
*/
__STATIC_INLINE void nrf_usbd_epdatastatus_clear(uint32_t flags);
/**
- * @brief Function for getting and clearing DATAEPSTATUS register value
+ * @brief Function for getting and clearing DATAEPSTATUS register value.
*
* Function clears all flags in register set before returning its value.
- * @return Flag values defined in @ref nrf_usbd_dataepstatus_mask_t
+ * @return Flag values defined in @ref nrf_usbd_dataepstatus_mask_t.
*/
__STATIC_INLINE uint32_t nrf_usbd_epdatastatus_get_and_clear(void);
/**
- * @name Setup command frame functions
+ * @name Setup command frame functions.
*
- * Functions for setup command frame parts access
+ * Functions for setting up command frame part access.
* @{
*/
/**
- * @brief Function for reading BMREQUESTTYPE - part of SETUP packet
+ * @brief Function for reading BMREQUESTTYPE - part of the SETUP packet.
*
- * @return the value of BREQUESTTYPE on last received SETUP frame
+ * @return Value of BREQUESTTYPE on the last received SETUP frame.
*/
__STATIC_INLINE uint8_t nrf_usbd_setup_bmrequesttype_get(void);
/**
- * @brief Function for reading BMREQUEST - part of SETUP packet
+ * @brief Function for reading BMREQUEST - part of the SETUP packet.
*
- * @return the value of BREQUEST on last received SETUP frame
+ * @return Value of BREQUEST on the last received SETUP frame.
*/
__STATIC_INLINE uint8_t nrf_usbd_setup_brequest_get(void);
/**
- * @brief Function for reading WVALUE - part of SETUP packet
+ * @brief Function for reading WVALUE - part of the SETUP packet.
*
- * @return the value of WVALUE on last received SETUP frame
+ * @return Value of WVALUE on the last received SETUP frame.
*/
__STATIC_INLINE uint16_t nrf_usbd_setup_wvalue_get(void);
/**
- * @brief Function for reading WINDEX - part of SETUP packet
+ * @brief Function for reading WINDEX - part of the SETUP packet.
*
- * @return the value of WINDEX on last received SETUP frame
+ * @return Value of WINDEX on the last received SETUP frame.
*/
__STATIC_INLINE uint16_t nrf_usbd_setup_windex_get(void);
/**
- * @brief Function for reading WLENGTH - part of SETUP packet
+ * @brief Function for reading WLENGTH - part of the SETUP packet.
*
- * @return the value of WLENGTH on last received SETUP frame
+ * @return Value of WLENGTH on the last received SETUP frame.
*/
__STATIC_INLINE uint16_t nrf_usbd_setup_wlength_get(void);
/** @} */
/**
- * @brief Function for getting number of received bytes on selected endpoint
+ * @brief Function for getting the number of received bytes on the selected endpoint.
+ *
+ * @note This function can be used on bulk, interrupt, and isochronous endpoints.
+ * @note For the function that returns different value for the ISOOUT zero
+ * transfer or no transfer at all, see the @ref nrf_usbd_episoout_size_get
+ * function. This function will return 0 for both cases.
*
* @param ep Endpoint identifier.
*
* @return Number of received bytes.
- *
- * @note This function may be used on Bulk/Interrupt and Isochronous endpoints.
- * @note For the function that returns different value for ISOOUT zero transfer or no transfer at all,
- * see @ref nrf_usbd_episoout_size_get function. This function would return 0 for both cases.
*/
__STATIC_INLINE size_t nrf_usbd_epout_size_get(uint8_t ep);
/**
- * @brief Function for getting number of received bytes on isochronous endpoint.
+ * @brief Function for getting number of the received bytes on isochronous endpoint.
*
- * @param ep Endpoint identifier, has to be isochronous out endpoint.
+ * @param ep Endpoint identifier, must be an isochronous OUT endpoint.
*
- * @return Number of bytes received or @ref NRF_USBD_EPISOOUT_NO_DATA
+ * @return Number of bytes received or @ref NRF_USBD_EPISOOUT_NO_DATA.
*/
__STATIC_INLINE size_t nrf_usbd_episoout_size_get(uint8_t ep);
/**
- * @brief Function for clearing out endpoint to accept any new incoming traffic
+ * @brief Function for clearing OUT endpoint to accept any new incoming traffic.
*
- * @param ep ep Endpoint identifier. Only OUT Interrupt/Bulk endpoints are accepted.
+ * @param ep ep Endpoint identifier. Only OUT interrupt/bulk endpoints are accepted.
*/
__STATIC_INLINE void nrf_usbd_epout_clear(uint8_t ep);
-/**
- * @brief Function for enabling USB pullup
- */
+/** @brief Function for enabling the USB pullup. */
__STATIC_INLINE void nrf_usbd_pullup_enable(void);
-/**
- * @brief Function for disabling USB pullup
- */
+/** @brief Function for disabling the USB pullup. */
__STATIC_INLINE void nrf_usbd_pullup_disable(void);
/**
- * @brief Function for returning current USB pullup state
+ * @brief Function for returning the current the USB pullup state.
*
- * @retval true USB pullup is enabled
- * @retval false USB pullup is disabled
+ * @retval true The USB pullup is enabled.
+ * @retval false The USB pullup is disabled.
*/
__STATIC_INLINE bool nrf_usbd_pullup_check(void);
/**
- * @brief Function for configuring the value to be forced on the bus on DRIVEDPDM task
+ * @brief Function for configuring the value to be forced on the bus on the DRIVEDPDM task.
*
- * Selected state would be forced on the bus when @ref NRF_USBD_TASK_DRIVEDPDM is set.
- * The state would be removed from the bus on @ref NRF_USBD_TASK_NODRIVEDPDM and
- * the control would be returned to the USBD peripheral.
- * @param val State to be set
+ * The selected state will be forced on the bus when @ref NRF_USBD_TASK_DRIVEDPDM is set.
+ * The state will be removed from the bus on @ref NRF_USBD_TASK_NODRIVEDPDM and
+ * the control will be returned to the USBD peripheral.
+ * @param val State to be set.
*/
__STATIC_INLINE void nrf_usbd_dpdmvalue_set(nrf_usbd_dpdmvalue_t val);
/**
- * @brief Function for setting data toggle
+ * @brief Function for setting the data toggle.
*
- * Configuration of current state of data toggling
- * @param ep Endpoint number with the information about its direction
- * @param op Operation to execute
+ * Configuration of the current state of data toggling.
+ * @param ep Endpoint number with the information about its direction.
+ * @param op Operation to execute.
*/
__STATIC_INLINE void nrf_usbd_dtoggle_set(uint8_t ep, nrf_usbd_dtoggle_t op);
/**
- * @brief Function for getting data toggle
+ * @brief Function for getting the data toggle.
*
- * Get the current state of data toggling
- * @param ep Endpoint number to return the information about current data toggling
- * @retval NRF_USBD_DTOGGLE_DATA0 Data toggle is DATA0 on selected endpoint
- * @retval NRF_USBD_DTOGGLE_DATA1 Data toggle is DATA1 on selected endpoint
+ * Get the current state of data toggling.
+ *
+ * @param ep Endpoint number to return the information about current data toggling.
+ *
+ * @retval NRF_USBD_DTOGGLE_DATA0 Data toggle is DATA0 on selected endpoint.
+ * @retval NRF_USBD_DTOGGLE_DATA1 Data toggle is DATA1 on selected endpoint.
*/
__STATIC_INLINE nrf_usbd_dtoggle_t nrf_usbd_dtoggle_get(uint8_t ep);
/**
- * @brief Function for checking if endpoint is enabled
+ * @brief Function for checking whether the endpoint is enabled.
*
- * @param ep Endpoint id to check
+ * @param ep Endpoint ID to be checked.
*
- * @retval true Endpoint is enabled
- * @retval false Endpoint is disabled
+ * @retval true Endpoint is enabled.
+ * @retval false Endpoint is disabled.
*/
__STATIC_INLINE bool nrf_usbd_ep_enable_check(uint8_t ep);
/**
- * @brief Function for enabling selected endpoint
+ * @brief Function for enabling the selected endpoint.
*
- * Enabled endpoint responds for the tokens on the USB bus
+ * The enabled endpoint responds for the tokens on the USB bus.
*
- * @param ep Endpoint id to enable
+ * @param ep Endpoint ID to be enabled.
*/
__STATIC_INLINE void nrf_usbd_ep_enable(uint8_t ep);
/**
- * @brief Function for disabling selected endpoint
+ * @brief Function for disabling the selected endpoint.
*
- * Disabled endpoint does not respond for the tokens on the USB bus
+ * The disabled endpoint does not respond for the tokens on the USB bus.
*
- * @param ep Endpoint id to disable
+ * @param ep Endpoint ID to be disabled.
*/
__STATIC_INLINE void nrf_usbd_ep_disable(uint8_t ep);
/**
- * @brief Function for disabling all endpoints
+ * @brief Function for disabling all endpoints.
*
- * Auxiliary function to simply disable all aviable endpoints.
- * It lefts only EP0 IN and OUT enabled.
+ * An auxiliary function to disable all aviable endpoints.
+ * It leaves only EP0 IN and OUT enabled.
*/
__STATIC_INLINE void nrf_usbd_ep_all_disable(void);
/**
- * @brief Function for stalling selected endpoint
+ * @brief Function for stalling the selected endpoint.
*
- * @param ep Endpoint identifier
- * @note This function cannot be called on isochronous endpoint
+ * @note This function cannot be called on isochronous endpoint.
+ *
+ * @param ep Endpoint identifier.
*/
__STATIC_INLINE void nrf_usbd_ep_stall(uint8_t ep);
/**
- * @brief Function for unstalling selected endpoint
+ * @brief Function for unstalling the selected endpoint.
+ *
+ * @note This function cannot be called on isochronous endpoint.
*
* @param ep Endpoint identifier
- * @note This function cannot be called on isochronous endpoint
*/
__STATIC_INLINE void nrf_usbd_ep_unstall(uint8_t ep);
/**
- * @brief Function for configuration of isochronous buffer splitting
+ * @brief Function for configuring the isochronous buffer splitting.
*
- * Configure isochronous buffer splitting between IN and OUT endpoints.
+ * This function configures isochronous buffer splitting between IN and OUT endpoints.
*
- * @param split Required configuration
+ * @param split Required configuration.
*/
__STATIC_INLINE void nrf_usbd_isosplit_set(nrf_usbd_isosplit_t split);
/**
- * @brief Function for getting the isochronous buffer splitting configuration
+ * @brief Function for getting the isochronous buffer splitting configuration.
*
- * Get the current isochronous buffer splitting configuration.
+ * This function gets the current isochronous buffer splitting configuration.
*
- * @return Current configuration
+ * @return Current configuration.
*/
__STATIC_INLINE nrf_usbd_isosplit_t nrf_usbd_isosplit_get(void);
/**
- * @brief Function for getting current frame counter
+ * @brief Function for getting current frame counter.
*
- * @return Current frame counter
+ * @return Current frame counter.
*/
__STATIC_INLINE uint32_t nrf_usbd_framecntr_get(void);
/**
- * @brief Function for entering into low power mode
+ * @brief Function for entering into the USB low power mode.
*
- * After this function is called the clock source from the USBD is disconnected internally.
- * After this function is called most of the USBD registers cannot be accessed anymore.
+ * After this function is called, the clock source from the USBD is disconnected internally.
+ * After this function is called, most of the USBD registers cannot be accessed anymore.
*
* @sa nrf_usbd_lowpower_disable
* @sa nrf_usbd_lowpower_check
@@ -938,11 +912,11 @@ __STATIC_INLINE uint32_t nrf_usbd_framecntr_get(void);
__STATIC_INLINE void nrf_usbd_lowpower_enable(void);
/**
- * @brief Function for exiting from low power mode
+ * @brief Function for exiting from the USB low power mode.
*
- * After this function is called the clock source for the USBD is connected internally.
- * The @ref NRF_USBD_EVENTCAUSE_WUREQ_MASK event would be generated and
- * then the USBD registers may be accessed.
+ * After this function is called, the clock source for the USBD is connected internally.
+ * The @ref NRF_USBD_EVENTCAUSE_WUREQ_MASK event will be generated and
+ * then the USBD registers can be accessed.
*
* @sa nrf_usbd_lowpower_enable
* @sa nrf_usbd_lowpower_check
@@ -950,46 +924,46 @@ __STATIC_INLINE void nrf_usbd_lowpower_enable(void);
__STATIC_INLINE void nrf_usbd_lowpower_disable(void);
/**
- * @brief Function for checking the state of the low power mode
+ * @brief Function for checking the state of the low power mode.
*
- * @retval true USBD is in low power mode
- * @retval false USBD is not in low power mode
+ * @retval true The USBD is in low power mode.
+ * @retval false The USBD is not in low power mode.
*/
__STATIC_INLINE bool nrf_usbd_lowpower_check(void);
/**
* @brief Function for configuring ISO IN endpoint response to an IN token when no data is ready to be sent.
*
- * @param config Required configuration
+ * @param config Required configuration.
*/
__STATIC_INLINE void nrf_usbd_isoinconfig_set(nrf_usbd_isoinconfig_t config);
/**
* @brief Function for getting the cofiguration of ISO IN endpoint response to an IN token when no data is ready to be sent.
*
- * @return Current configuration
+ * @return Current configuration.
*/
__STATIC_INLINE nrf_usbd_isoinconfig_t nrf_usbd_isoinconfig_get(void);
/**
- * @brief Function for configuring EasyDMA channel
+ * @brief Function for configuring the EasyDMA channel.
*
* Configures EasyDMA for the transfer.
*
- * @param ep Endpoint identifier (with direction)
- * @param ptr Pointer to the data
- * @param maxcnt Number of bytes to transfer
+ * @param ep Endpoint identifier (with direction).
+ * @param ptr Pointer to the data.
+ * @param maxcnt Number of bytes to transfer.
*/
__STATIC_INLINE void nrf_usbd_ep_easydma_set(uint8_t ep, uint32_t ptr, uint32_t maxcnt);
/**
- * @brief Function for getting number of transferred bytes
+ * @brief Function for getting number of transferred bytes.
*
- * Get number of transferred bytes in the last transaction
+ * This function gets the number of transferred bytes in the last transaction.
*
- * @param ep Endpoint identifier
+ * @param ep Endpoint identifier.
*
- * @return The content of the AMOUNT register
+ * @return The content of the AMOUNT register.
*/
__STATIC_INLINE uint32_t nrf_usbd_ep_amount_get(uint8_t ep);
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_vmc.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_vmc.h
index 957baa44d..5f1487492 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_vmc.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_vmc.h
@@ -68,7 +68,7 @@ typedef enum
*
* @note Overrides current configuration.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] ram_block_num RAM block number.
* @param[in] power_mask Bitmask with sections configuration of particular RAM block.
* @ref nrf_vmc_power_t should be use to prepare this bitmask.
@@ -83,7 +83,7 @@ __STATIC_INLINE void nrf_vmc_ram_block_config(NRF_VMC_Type * p_reg,
/**
* @brief Function for clearing power configuration for the particular RAM block.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] ram_block_num RAM block number.
*/
__STATIC_INLINE void nrf_vmc_ram_block_clear(NRF_VMC_Type * p_reg, uint8_t ram_block_num);
@@ -91,7 +91,7 @@ __STATIC_INLINE void nrf_vmc_ram_block_clear(NRF_VMC_Type * p_reg, uint8_t ram_b
/**
* @brief Function for setting power configuration for the particular RAM block.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] ram_block_num RAM block number.
* @param[in] sect_power Paricular section of the RAM block.
*/
@@ -102,7 +102,7 @@ __STATIC_INLINE void nrf_vmc_ram_block_power_set(NRF_VMC_Type * p_reg,
/**
* @brief Function for clearing power configuration for the particular RAM block.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] ram_block_num RAM block number.
* @param[in] sect_power Paricular section of the RAM block.
*/
@@ -113,7 +113,7 @@ __STATIC_INLINE void nrf_vmc_ram_block_power_clear(NRF_VMC_Type * p_reg,
/**
* @brief Function for getting power configuration of the particular RAM block.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] ram_block_num RAM block number.
*
* @return Bitmask with power configuration of sections of particular RAM block.
@@ -124,7 +124,7 @@ __STATIC_INLINE uint32_t nrf_vmc_ram_block_power_mask_get(NRF_VMC_Type const * p
/**
* @brief Function for setting retention configuration for the particular RAM block.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] ram_block_num RAM block number.
* @param[in] sect_retention Paricular section of the RAM block.
*/
@@ -135,7 +135,7 @@ __STATIC_INLINE void nrf_vmc_ram_block_retention_set(NRF_VMC_Type * p_reg,
/**
* @brief Function for clearing retention configuration for the particular RAM block.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] ram_block_num RAM block number.
* @param[in] sect_retention Paricular section of the RAM block.
*/
@@ -146,7 +146,7 @@ __STATIC_INLINE void nrf_vmc_ram_block_retention_clear(NRF_VMC_Type * p_reg
/**
* @brief Function for getting retention configuration of the particular RAM block.
*
- * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] ram_block_num RAM block number.
*
* @return Bitmask with retention configuration of sections of particular RAM block
diff --git a/third_party/NordicSemiconductor/nrfx/hal/nrf_wdt.h b/third_party/NordicSemiconductor/nrfx/hal/nrf_wdt.h
index 4f1dfcc57..9adb590fc 100644
--- a/third_party/NordicSemiconductor/nrfx/hal/nrf_wdt.h
+++ b/third_party/NordicSemiconductor/nrfx/hal/nrf_wdt.h
@@ -45,38 +45,26 @@ extern "C" {
* @brief Hardware access layer for managing the Watchdog Timer (WDT) peripheral.
*/
+/** @brief Number of WDT channels. */
#define NRF_WDT_CHANNEL_NUMBER 0x8UL
-#define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value, shouldn't be modified.*/
-#define NRF_WDT_TASK_SET 1UL
-#define NRF_WDT_EVENT_CLEAR 0UL
+/** @brief WDT register reload value. */
+#define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value; should not be modified. */
-/**
- * @enum nrf_wdt_task_t
- * @brief WDT tasks.
- */
+
+/** @brief WDT tasks. */
typedef enum
{
- /*lint -save -e30 -esym(628,__INTADDR__)*/
NRF_WDT_TASK_START = offsetof(NRF_WDT_Type, TASKS_START), /**< Task for starting WDT. */
- /*lint -restore*/
} nrf_wdt_task_t;
-/**
- * @enum nrf_wdt_event_t
- * @brief WDT events.
- */
+/** @brief WDT events. */
typedef enum
{
- /*lint -save -e30*/
NRF_WDT_EVENT_TIMEOUT = offsetof(NRF_WDT_Type, EVENTS_TIMEOUT), /**< Event from WDT time-out. */
- /*lint -restore*/
} nrf_wdt_event_t;
-/**
- * @enum nrf_wdt_behaviour_t
- * @brief WDT behavior in CPU SLEEP or HALT mode.
- */
+/** @brief WDT behavior in the SLEEP or HALT CPU modes. */
typedef enum
{
NRF_WDT_BEHAVIOUR_RUN_SLEEP = WDT_CONFIG_SLEEP_Msk, /**< WDT will run when CPU is in SLEEP mode. */
@@ -85,10 +73,7 @@ typedef enum
NRF_WDT_BEHAVIOUR_PAUSE_SLEEP_HALT = 0, /**< WDT will be paused when CPU is in SLEEP or HALT mode. */
} nrf_wdt_behaviour_t;
-/**
- * @enum nrf_wdt_rr_register_t
- * @brief WDT reload request registers.
- */
+/** @brief WDT reload request registers. */
typedef enum
{
NRF_WDT_RR0 = 0, /**< Reload request register 0. */
@@ -101,15 +86,13 @@ typedef enum
NRF_WDT_RR7 /**< Reload request register 7. */
} nrf_wdt_rr_register_t;
-/**
- * @enum nrf_wdt_int_mask_t
- * @brief WDT interrupts.
- */
+/** @brief WDT interrupts. */
typedef enum
{
NRF_WDT_INT_TIMEOUT_MASK = WDT_INTENSET_TIMEOUT_Msk, /**< WDT interrupt from time-out event. */
} nrf_wdt_int_mask_t;
+
/**
* @brief Function for configuring the watchdog behavior when the CPU is sleeping or halted.
*
@@ -120,48 +103,48 @@ __STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour);
/**
* @brief Function for starting the WDT task.
*
- * @param[in] task Task.
+ * @param[in] task Task.
*/
__STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task);
/**
- * @brief Function for clearing the WDT event.
+ * @brief Function for clearing the WDT event register.
*
- * @param[in] event Event.
+ * @param[in] event Event.
*/
__STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event);
/**
* @brief Function for retrieving the state of the WDT event.
*
- * @param[in] event Event.
+ * @param[in] event Event to be checked.
*
- * @retval true If the event is set.
- * @retval false If the event is not set.
+ * @retval true The event has been generated.
+ * @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event);
/**
- * @brief Function for enabling a specific interrupt.
+ * @brief Function for enabling the specified interrupt.
*
- * @param[in] int_mask Interrupt.
+ * @param[in] int_mask Interrupt.
*/
__STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask);
/**
* @brief Function for retrieving the state of given interrupt.
*
- * @param[in] int_mask Interrupt.
+ * @param[in] int_mask Interrupt.
*
- * @retval true Interrupt is enabled.
- * @retval false Interrupt is not enabled.
+ * @retval true Interrupt is enabled.
+ * @retval false Interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_wdt_int_enable_check(uint32_t int_mask);
/**
* @brief Function for disabling a specific interrupt.
*
- * @param[in] int_mask Interrupt.
+ * @param[in] int_mask Interrupt.
*/
__STATIC_INLINE void nrf_wdt_int_disable(uint32_t int_mask);
@@ -206,72 +189,72 @@ __STATIC_INLINE void nrf_wdt_publish_clear(nrf_wdt_event_t event);
/**
* @brief Function for returning the address of a specific WDT task register.
*
- * @param[in] task Task.
+ * @param[in] task Task.
*/
__STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task);
/**
* @brief Function for returning the address of a specific WDT event register.
*
- * @param[in] event Event.
+ * @param[in] event Event.
*
- * @retval address of requested event register
+ * @return Address of requested event register
*/
__STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event);
/**
* @brief Function for retrieving the watchdog status.
*
- * @retval true If the watchdog is started.
- * @retval false If the watchdog is not started.
+ * @retval true The watchdog is started.
+ * @retval false The watchdog is not started.
*/
__STATIC_INLINE bool nrf_wdt_started(void);
/**
* @brief Function for retrieving the watchdog reload request status.
*
- * @param[in] rr_register Reload request register to check.
+ * @param[in] rr_register Reload request register to be checked.
*
- * @retval true If a reload request is running.
- * @retval false If no reload request is running.
+ * @retval true Reload request is running.
+ * @retval false No reload requests are running.
*/
__STATIC_INLINE bool nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register);
/**
* @brief Function for setting the watchdog reload value.
*
- * @param[in] reload_value Watchdog counter initial value.
+ * @param[in] reload_value Watchdog counter initial value.
*/
__STATIC_INLINE void nrf_wdt_reload_value_set(uint32_t reload_value);
/**
* @brief Function for retrieving the watchdog reload value.
*
- * @retval Reload value.
+ * @return Reload value.
*/
__STATIC_INLINE uint32_t nrf_wdt_reload_value_get(void);
/**
* @brief Function for enabling a specific reload request register.
*
- * @param[in] rr_register Reload request register to enable.
+ * @param[in] rr_register Reload request register to be enabled.
*/
__STATIC_INLINE void nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register);
/**
* @brief Function for disabling a specific reload request register.
*
- * @param[in] rr_register Reload request register to disable.
+ * @param[in] rr_register Reload request register to be disabled.
*/
__STATIC_INLINE void nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register);
/**
* @brief Function for retrieving the status of a specific reload request register.
*
- * @param[in] rr_register Reload request register to check.
+ * @param[in] rr_register Reload request register to be checked.
*
- * @retval true If the reload request register is enabled.
- * @retval false If the reload request register is not enabled.
+ * @retval true The reload request register is enabled.
+ * @retval false The reload request register is not enabled.
*/
__STATIC_INLINE bool nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register);
@@ -291,12 +274,12 @@ __STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour)
__STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task)
{
- *((volatile uint32_t *)((uint8_t *)NRF_WDT + task)) = NRF_WDT_TASK_SET;
+ *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)task)) = 0x01UL;
}
__STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event)
{
- *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)) = NRF_WDT_EVENT_CLEAR;
+ *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)) = 0x0UL;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event));
(void)dummy;
@@ -305,7 +288,7 @@ __STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event)
__STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event)
{
- return (bool)*((volatile uint32_t *)((uint8_t *)NRF_WDT + event));
+ return (bool)*((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event));
}
__STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask)
@@ -351,12 +334,12 @@ __STATIC_INLINE void nrf_wdt_publish_clear(nrf_wdt_event_t event)
__STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task)
{
- return ((uint32_t)NRF_WDT + task);
+ return ((uint32_t)NRF_WDT + (uint32_t)task);
}
__STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event)
{
- return ((uint32_t)NRF_WDT + event);
+ return ((uint32_t)NRF_WDT + (uint32_t)event);
}
__STATIC_INLINE bool nrf_wdt_started(void)
diff --git a/third_party/NordicSemiconductor/nrfx/helpers/nrfx_gppi/nrfx_gppi.h b/third_party/NordicSemiconductor/nrfx/helpers/nrfx_gppi/nrfx_gppi.h
new file mode 100644
index 000000000..a98858b0f
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/helpers/nrfx_gppi/nrfx_gppi.h
@@ -0,0 +1,577 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_GPPI_H
+#define NRFX_GPPI_H
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfx_gppi Generic PPI layer
+ * @{
+ * @ingroup nrfx
+ * @ingroup nrf_dppi
+ * @ingroup nrf_ppi
+ *
+ * @brief Helper layer that provides the common functionality of PPI and DPPI drivers.
+ *
+ * Use PPI and DPPI drivers directly.
+ * This layer is provided only to help create generic code that can be built
+ * for SoCs equipped with either of these peripherals. When using this layer,
+ * take into account that there are significant differences between the PPI and DPPI
+ * interfaces that affect the behavior of this layer.
+ *
+ * One difference is that PPI allows associating of one task or event with
+ * more than one channel, whereas DPPI does not allow this. In DPPI, the second
+ * association overwrites the first one. Consequently, this helper layer cannot
+ * be used in applications that need to connect a task or event to multiple
+ * channels.
+ *
+ * Another difference is that in DPPI one channel can be associated with
+ * multiple tasks and multiple events, while in PPI this is not possible (with
+ * the exception of the association of a second task as a fork). Because of
+ * this difference, it is important to clear the previous endpoints of the channel that
+ * is to be reused with some different ones. Otherwise, the behavior of this
+ * helper layer will be different, depending on the actual interface used:
+ * in DPPI the channel configuration will be extended with the new endpoints, and
+ * in PPI the new endpoints will replace the previous ones.
+ */
+
+#if defined(PPI_PRESENT)
+#include
+
+typedef enum
+{
+ NRFX_GPPI_CHANNEL_GROUP0 = NRF_PPI_CHANNEL_GROUP0,
+ NRFX_GPPI_CHANNEL_GROUP1 = NRF_PPI_CHANNEL_GROUP1,
+ NRFX_GPPI_CHANNEL_GROUP2 = NRF_PPI_CHANNEL_GROUP2,
+ NRFX_GPPI_CHANNEL_GROUP3 = NRF_PPI_CHANNEL_GROUP3,
+#if (PPI_GROUP_NUM > 4)
+ NRFX_GPPI_CHANNEL_GROUP4 = NRF_PPI_CHANNEL_GROUP4,
+ NRFX_GPPI_CHANNEL_GROUP5 = NRF_PPI_CHANNEL_GROUP5,
+#endif
+} nrfx_gppi_channel_group_t;
+
+typedef enum
+{
+ NRFX_GPPI_TASK_CHG0_EN = NRF_PPI_TASK_CHG0_EN,
+ NRFX_GPPI_TASK_CHG0_DIS = NRF_PPI_TASK_CHG0_DIS,
+ NRFX_GPPI_TASK_CHG1_EN = NRF_PPI_TASK_CHG1_EN,
+ NRFX_GPPI_TASK_CHG1_DIS = NRF_PPI_TASK_CHG1_DIS,
+ NRFX_GPPI_TASK_CHG2_EN = NRF_PPI_TASK_CHG2_EN,
+ NRFX_GPPI_TASK_CHG2_DIS = NRF_PPI_TASK_CHG2_DIS,
+ NRFX_GPPI_TASK_CHG3_EN = NRF_PPI_TASK_CHG3_EN,
+ NRFX_GPPI_TASK_CHG3_DIS = NRF_PPI_TASK_CHG3_DIS,
+#if (PPI_GROUP_NUM > 4)
+ NRFX_GPPI_TASK_CHG4_EN = NRF_PPI_TASK_CHG4_EN,
+ NRFX_GPPI_TASK_CHG4_DIS = NRF_PPI_TASK_CHG4_DIS,
+ NRFX_GPPI_TASK_CHG5_EN = NRF_PPI_TASK_CHG5_EN,
+ NRFX_GPPI_TASK_CHG5_DIS = NRF_PPI_TASK_CHG5_DIS
+#endif
+} nrfx_gppi_task_t;
+
+#elif defined(DPPI_PRESENT)
+#include
+
+typedef enum
+{
+ NRFX_GPPI_CHANNEL_GROUP0 = NRF_DPPI_CHANNEL_GROUP0,
+ NRFX_GPPI_CHANNEL_GROUP1 = NRF_DPPI_CHANNEL_GROUP1,
+ NRFX_GPPI_CHANNEL_GROUP2 = NRF_DPPI_CHANNEL_GROUP2,
+ NRFX_GPPI_CHANNEL_GROUP3 = NRF_DPPI_CHANNEL_GROUP3,
+ NRFX_GPPI_CHANNEL_GROUP4 = NRF_DPPI_CHANNEL_GROUP4,
+ NRFX_GPPI_CHANNEL_GROUP5 = NRF_DPPI_CHANNEL_GROUP5,
+} nrfx_gppi_channel_group_t;
+
+typedef enum
+{
+ NRFX_GPPI_TASK_CHG0_EN = NRF_DPPI_TASK_CHG0_EN,
+ NRFX_GPPI_TASK_CHG0_DIS = NRF_DPPI_TASK_CHG0_DIS,
+ NRFX_GPPI_TASK_CHG1_EN = NRF_DPPI_TASK_CHG1_EN,
+ NRFX_GPPI_TASK_CHG1_DIS = NRF_DPPI_TASK_CHG1_DIS,
+ NRFX_GPPI_TASK_CHG2_EN = NRF_DPPI_TASK_CHG2_EN,
+ NRFX_GPPI_TASK_CHG2_DIS = NRF_DPPI_TASK_CHG2_DIS,
+ NRFX_GPPI_TASK_CHG3_EN = NRF_DPPI_TASK_CHG3_EN,
+ NRFX_GPPI_TASK_CHG3_DIS = NRF_DPPI_TASK_CHG3_DIS,
+ NRFX_GPPI_TASK_CHG4_EN = NRF_DPPI_TASK_CHG4_EN,
+ NRFX_GPPI_TASK_CHG4_DIS = NRF_DPPI_TASK_CHG4_DIS,
+ NRFX_GPPI_TASK_CHG5_EN = NRF_DPPI_TASK_CHG5_EN,
+ NRFX_GPPI_TASK_CHG5_DIS = NRF_DPPI_TASK_CHG5_DIS
+} nrfx_gppi_task_t;
+
+#elif defined(__NRFX_DOXYGEN__)
+
+/** @brief Generic PPI channel groups. */
+typedef enum
+{
+ NRFX_GPPI_CHANNEL_GROUP0, /**< Channel group 0.*/
+ NRFX_GPPI_CHANNEL_GROUP1, /**< Channel group 1.*/
+ NRFX_GPPI_CHANNEL_GROUP2, /**< Channel group 2.*/
+ NRFX_GPPI_CHANNEL_GROUP3, /**< Channel group 3.*/
+ NRFX_GPPI_CHANNEL_GROUP4, /**< Channel group 4.*/
+ NRFX_GPPI_CHANNEL_GROUP5, /**< Channel group 5.*/
+} nrfx_gppi_channel_group_t;
+
+/** @brief Generic PPI tasks. */
+typedef enum
+{
+ NRFX_GPPI_TASK_CHG0_EN, /**< Task for enabling channel group 0 */
+ NRFX_GPPI_TASK_CHG0_DIS, /**< Task for disabling channel group 0 */
+ NRFX_GPPI_TASK_CHG1_EN, /**< Task for enabling channel group 1 */
+ NRFX_GPPI_TASK_CHG1_DIS, /**< Task for disabling channel group 1 */
+ NRFX_GPPI_TASK_CHG2_EN, /**< Task for enabling channel group 2 */
+ NRFX_GPPI_TASK_CHG2_DIS, /**< Task for disabling channel group 2 */
+ NRFX_GPPI_TASK_CHG3_EN, /**< Task for enabling channel group 3 */
+ NRFX_GPPI_TASK_CHG3_DIS, /**< Task for disabling channel group 3 */
+ NRFX_GPPI_TASK_CHG4_EN, /**< Task for enabling channel group 4 */
+ NRFX_GPPI_TASK_CHG4_DIS, /**< Task for disabling channel group 4 */
+ NRFX_GPPI_TASK_CHG5_EN, /**< Task for enabling channel group 5 */
+ NRFX_GPPI_TASK_CHG5_DIS, /**< Task for disabling channel group 5 */
+} nrfx_gppi_task_t;
+#endif // defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief Function for checking if a given channel is enabled.
+ *
+ * @param[in] channel Channel to check.
+ *
+ * @retval true The channel is enabled.
+ * @retval false The channel is not enabled.
+ */
+__STATIC_INLINE bool nrfx_gppi_channel_check(uint8_t channel);
+
+/** @brief Function for disabling all channels. */
+__STATIC_INLINE void nrfx_gppi_channels_disable_all(void);
+
+/**
+ * @brief Function for enabling multiple channels.
+ *
+ * The bits in @c mask value correspond to particular channels. This means that
+ * writing 1 to bit 0 enables channel 0, writing 1 to bit 1 enables channel 1, etc.
+ *
+ * @param[in] mask Channel mask.
+ */
+__STATIC_INLINE void nrfx_gppi_channels_enable(uint32_t mask);
+
+/**
+ * @brief Function for disabling multiple channels.
+ *
+ * The bits in @c mask value correspond to particular channels. This means that
+ * writing 1 to bit 0 disables channel 0, writing 1 to bit 1 disables channel 1, etc.
+ *
+ * @param[in] mask Channel mask.
+ */
+__STATIC_INLINE void nrfx_gppi_channels_disable(uint32_t mask);
+
+/**
+ * @brief Function for associating a given channel with the specified event register.
+ *
+ * This function sets the DPPI publish configuration for a given event
+ * or sets the PPI event endpoint register.
+ *
+ * @param[in] channel Channel to which to assign the event.
+ * @param[in] eep Address of the event register.
+ */
+__STATIC_INLINE void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep);
+
+/**
+ * @brief Function for associating a given channel with the specified task register.
+ *
+ * This function sets the DPPI subscribe configuration for a given task
+ * or sets the PPI task endpoint register.
+ *
+ * @param[in] channel Channel to which to assign the task.
+ * @param[in] tep Address of the task register.
+ */
+__STATIC_INLINE void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep);
+
+/**
+ * @brief Function for setting up the event and task endpoints for a given channel.
+ *
+ * @param[in] channel Channel to which the given endpoints are assigned.
+ * @param[in] eep Address of the event register.
+ * @param[in] tep Address of the task register.
+ */
+__STATIC_INLINE void nrfx_gppi_channel_endpoints_setup(uint8_t channel,
+ uint32_t eep,
+ uint32_t tep);
+
+/**
+ * @brief Function for clearing the DPPI publish configuration for a given event
+ * register or for clearing the PPI event endpoint register.
+ *
+ * @param[in] channel Channel for which to clear the event endpoint. Not used in DPPI.
+ * @param[in] eep Address of the event register. Not used in PPI.
+ */
+__STATIC_INLINE void nrfx_gppi_event_endpoint_clear(uint8_t channel, uint32_t eep);
+
+/**
+ * @brief Function for clearing the DPPI subscribe configuration for a given task
+ * register or for clearing the PPI task endpoint register.
+ *
+ * @param[in] channel Channel from which to disconnect the task enpoint. Not used in DPPI.
+ * @param[in] tep Address of the task register. Not used in PPI.
+ */
+__STATIC_INLINE void nrfx_gppi_task_endpoint_clear(uint8_t channel, uint32_t tep);
+
+
+#if defined(PPI_FEATURE_FORKS_PRESENT) || defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for setting up the task endpoint for a given PPI fork or for
+ * associating the DPPI channel with an additional task register.
+ *
+ * @param[in] channel Channel to which the given fork endpoint is assigned.
+ * @param[in] fork_tep Address of the task register.
+ */
+__STATIC_INLINE void nrfx_gppi_fork_endpoint_setup(uint8_t channel, uint32_t fork_tep);
+
+/**
+ * @brief Function for clearing the task endpoint for a given PPI fork or for clearing
+ * the DPPI subscribe register.
+ *
+ * @param[in] channel Channel for which to clear the fork endpoint. Not used in DPPI.
+ * @param[in] fork_tep Address of the task register. Not used in PPI.
+ */
+__STATIC_INLINE void nrfx_gppi_fork_endpoint_clear(uint8_t channel, uint32_t fork_tep);
+#endif // defined(PPI_FEATURE_FORKS_PRESENT) || defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief Function for including multiple channels in a channel group.
+ *
+ * @param[in] channel_mask Channels to be included in the group.
+ * @param[in] channel_group Channel group.
+ */
+__STATIC_INLINE void nrfx_gppi_channels_include_in_group(uint32_t channel_mask,
+ nrfx_gppi_channel_group_t channel_group);
+
+/**
+ * @brief Function for removing multiple channels from a channel group.
+ *
+ * @param[in] channel_mask Channels to be removed from the group.
+ * @param[in] channel_group Channel group.
+ */
+__STATIC_INLINE void nrfx_gppi_channels_remove_from_group(uint32_t channel_mask,
+ nrfx_gppi_channel_group_t channel_group);
+
+/**
+ * @brief Function for removing all channels from a channel group.
+ *
+ * @param[in] channel_group Channel group.
+ */
+__STATIC_INLINE void nrfx_gppi_group_clear(nrfx_gppi_channel_group_t channel_group);
+
+/**
+ * @brief Function for enabling a channel group.
+ *
+ * @param[in] channel_group Channel group.
+ */
+__STATIC_INLINE void nrfx_gppi_group_enable(nrfx_gppi_channel_group_t channel_group);
+
+/**
+ * @brief Function for disabling a group.
+ *
+ * @param[in] channel_group Channel group.
+ */
+__STATIC_INLINE void nrfx_gppi_group_disable(nrfx_gppi_channel_group_t channel_group);
+
+/**
+ * @brief Function for activating a task.
+ *
+ * @param[in] task Task to be activated.
+ */
+__STATIC_INLINE void nrfx_gppi_task_trigger(nrfx_gppi_task_t task);
+
+/**
+ * @brief Function for returning the address of a specific task register.
+ *
+ * @param[in] task PPI or DPPI task.
+ *
+ * @return Address of the requested task register.
+ */
+__STATIC_INLINE uint32_t nrfx_gppi_task_address_get(nrfx_gppi_task_t task);
+
+/**
+ * @brief Function for returning the address of a channel group disable task.
+ *
+ * @param[in] group Channel group.
+ *
+ * @return Disable task address of the specified group.
+ */
+__STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_disable_task_get(nrfx_gppi_channel_group_t group);
+
+/**
+ * @brief Function for returning the address of a channel group enable task.
+ *
+ * @param[in] group Channel group.
+ *
+ * @return Enable task address of the specified group.
+ */
+__STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_enable_task_get(nrfx_gppi_channel_group_t group);
+
+/** @} */
+
+#if defined(PPI_PRESENT)
+
+__STATIC_INLINE bool nrfx_gppi_channel_check(uint8_t channel)
+{
+ return (nrf_ppi_channel_enable_get((nrf_ppi_channel_t)channel) == NRF_PPI_CHANNEL_ENABLED);
+}
+
+__STATIC_INLINE void nrfx_gppi_channels_disable_all(void)
+{
+ nrf_ppi_channel_disable_all();
+}
+
+__STATIC_INLINE void nrfx_gppi_channels_enable(uint32_t mask)
+{
+ nrf_ppi_channels_enable(mask);
+}
+
+__STATIC_INLINE void nrfx_gppi_channels_disable(uint32_t mask)
+{
+ nrf_ppi_channels_disable(mask);
+}
+
+__STATIC_INLINE void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep)
+{
+ nrf_ppi_event_endpoint_setup((nrf_ppi_channel_t)channel, eep);
+}
+
+__STATIC_INLINE void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep)
+{
+ nrf_ppi_task_endpoint_setup((nrf_ppi_channel_t)channel, tep);
+}
+
+__STATIC_INLINE void nrfx_gppi_channel_endpoints_setup(uint8_t channel,
+ uint32_t eep,
+ uint32_t tep)
+{
+ nrf_ppi_channel_endpoint_setup((nrf_ppi_channel_t)channel, eep, tep);
+}
+
+__STATIC_INLINE void nrfx_gppi_event_endpoint_clear(uint8_t channel, uint32_t eep)
+{
+ (void)eep;
+ nrf_ppi_event_endpoint_setup((nrf_ppi_channel_t)channel, 0);
+}
+
+__STATIC_INLINE void nrfx_gppi_task_endpoint_clear(uint8_t channel, uint32_t tep)
+{
+ (void)tep;
+ nrf_ppi_task_endpoint_setup((nrf_ppi_channel_t)channel, 0);
+}
+
+#if defined(PPI_FEATURE_FORKS_PRESENT)
+__STATIC_INLINE void nrfx_gppi_fork_endpoint_setup(uint8_t channel, uint32_t fork_tep)
+{
+ nrf_ppi_fork_endpoint_setup((nrf_ppi_channel_t)channel, fork_tep);
+}
+
+__STATIC_INLINE void nrfx_gppi_fork_endpoint_clear(uint8_t channel, uint32_t fork_tep)
+{
+ (void)fork_tep;
+ nrf_ppi_fork_endpoint_setup((nrf_ppi_channel_t)channel, 0);
+}
+#endif
+
+__STATIC_INLINE void nrfx_gppi_channels_include_in_group(uint32_t channel_mask,
+ nrfx_gppi_channel_group_t channel_group)
+{
+ nrf_ppi_channels_include_in_group(channel_mask, channel_group);
+}
+
+__STATIC_INLINE void nrfx_gppi_channels_remove_from_group(uint32_t channel_mask,
+ nrfx_gppi_channel_group_t channel_group)
+{
+ nrf_ppi_channels_remove_from_group(channel_mask, channel_group);
+}
+
+__STATIC_INLINE void nrfx_gppi_group_clear(nrfx_gppi_channel_group_t channel_group)
+{
+ nrf_ppi_channel_group_clear(channel_group);
+}
+
+__STATIC_INLINE void nrfx_gppi_group_enable(nrfx_gppi_channel_group_t channel_group)
+{
+ nrf_ppi_group_enable(channel_group);
+}
+
+__STATIC_INLINE void nrfx_gppi_group_disable(nrfx_gppi_channel_group_t channel_group)
+{
+ nrf_ppi_group_disable(channel_group);
+}
+
+__STATIC_INLINE void nrfx_gppi_task_trigger(nrfx_gppi_task_t task)
+{
+ nrf_ppi_task_trigger(task);
+}
+
+__STATIC_INLINE uint32_t nrfx_gppi_task_address_get(nrfx_gppi_task_t task)
+{
+ return (uint32_t)nrf_ppi_task_address_get(task);
+}
+
+__STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_disable_task_get(nrfx_gppi_channel_group_t group)
+{
+ return (nrfx_gppi_task_t)nrf_ppi_group_disable_task_get((uint8_t)group);
+}
+
+__STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_enable_task_get(nrfx_gppi_channel_group_t group)
+{
+ return (nrfx_gppi_task_t)nrf_ppi_group_enable_task_get((uint8_t)group);
+}
+
+#elif defined(DPPI_PRESENT)
+
+__STATIC_INLINE bool nrfx_gppi_channel_check(uint8_t channel)
+{
+ return nrf_dppi_channel_check(NRF_DPPIC, channel);
+}
+
+__STATIC_INLINE void nrfx_gppi_channels_disable_all(void)
+{
+ nrf_dppi_channels_disable_all(NRF_DPPIC);
+}
+
+__STATIC_INLINE void nrfx_gppi_channels_enable(uint32_t mask)
+{
+ nrf_dppi_channels_enable(NRF_DPPIC, mask);
+}
+
+__STATIC_INLINE void nrfx_gppi_channels_disable(uint32_t mask)
+{
+ nrf_dppi_channels_disable(NRF_DPPIC, mask);
+}
+
+__STATIC_INLINE void nrfx_gppi_task_trigger(nrfx_gppi_task_t task)
+{
+ nrf_dppi_task_trigger(NRF_DPPIC, task);
+}
+
+__STATIC_INLINE void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep)
+{
+ NRFX_ASSERT(eep);
+ *((volatile uint32_t *)(eep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
+}
+
+__STATIC_INLINE void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep)
+{
+ NRFX_ASSERT(tep);
+ *((volatile uint32_t *)(tep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
+}
+
+__STATIC_INLINE void nrfx_gppi_channel_endpoints_setup(uint8_t channel,
+ uint32_t eep,
+ uint32_t tep)
+{
+ nrfx_gppi_event_endpoint_setup(channel, eep);
+ nrfx_gppi_task_endpoint_setup(channel, tep);
+}
+
+__STATIC_INLINE void nrfx_gppi_event_endpoint_clear(uint8_t channel, uint32_t eep)
+{
+ NRFX_ASSERT(eep);
+ (void)channel;
+ *((volatile uint32_t *)(eep + 0x80uL)) = 0;
+}
+
+__STATIC_INLINE void nrfx_gppi_task_endpoint_clear(uint8_t channel, uint32_t tep)
+{
+ NRFX_ASSERT(tep);
+ (void)channel;
+ *((volatile uint32_t *)(tep + 0x80uL)) = 0;
+}
+
+__STATIC_INLINE void nrfx_gppi_fork_endpoint_setup(uint8_t channel, uint32_t fork_tep)
+{
+ nrfx_gppi_task_endpoint_setup(channel, fork_tep);
+}
+
+__STATIC_INLINE void nrfx_gppi_fork_endpoint_clear(uint8_t channel, uint32_t fork_tep)
+{
+ nrfx_gppi_task_endpoint_clear(channel, fork_tep);
+}
+
+__STATIC_INLINE void nrfx_gppi_channels_include_in_group(uint32_t channel_mask,
+ nrfx_gppi_channel_group_t channel_group)
+{
+ nrf_dppi_channels_include_in_group(NRF_DPPIC, channel_mask, channel_group);
+}
+
+__STATIC_INLINE void nrfx_gppi_channels_remove_from_group(uint32_t channel_mask,
+ nrfx_gppi_channel_group_t channel_group)
+{
+ nrf_dppi_channels_remove_from_group(NRF_DPPIC, channel_mask, channel_group);
+}
+
+__STATIC_INLINE void nrfx_gppi_group_clear(nrfx_gppi_channel_group_t channel_group)
+{
+ nrf_dppi_group_clear(NRF_DPPIC, channel_group);
+}
+
+__STATIC_INLINE void nrfx_gppi_group_enable(nrfx_gppi_channel_group_t channel_group)
+{
+ nrf_dppi_group_enable(NRF_DPPIC, channel_group);
+}
+
+__STATIC_INLINE void nrfx_gppi_group_disable(nrfx_gppi_channel_group_t channel_group)
+{
+ nrf_dppi_group_disable(NRF_DPPIC, channel_group);
+}
+
+__STATIC_INLINE uint32_t nrfx_gppi_task_address_get(nrfx_gppi_task_t gppi_task)
+{
+ return (uint32_t) ((uint8_t *) NRF_DPPIC + (uint32_t) gppi_task);
+}
+
+__STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_disable_task_get(nrfx_gppi_channel_group_t group)
+{
+ return (nrfx_gppi_task_t) nrf_dppi_group_disable_task_get((uint8_t)group);
+}
+
+__STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_enable_task_get(nrfx_gppi_channel_group_t group)
+{
+ return (nrfx_gppi_task_t) nrf_dppi_group_enable_task_get((uint8_t)group);
+}
+
+#else
+#error "Neither PPI nor DPPI is present in the SoC currently in use."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_GPPI_H
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/arm_startup_nrf52805.s b/third_party/NordicSemiconductor/nrfx/mdk/arm_startup_nrf52805.s
new file mode 100644
index 000000000..2a5c5ff78
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/arm_startup_nrf52805.s
@@ -0,0 +1,343 @@
+; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the License); you may
+; not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+; NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+ IF :DEF: __STARTUP_CONFIG
+#ifdef __STARTUP_CONFIG
+#include "startup_config.h"
+#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
+#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+#endif
+#endif
+ ENDIF
+
+ IF :DEF: __STARTUP_CONFIG
+Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
+ ELIF :DEF: __STACK_SIZE
+Stack_Size EQU __STACK_SIZE
+ ELSE
+Stack_Size EQU 2048
+ ENDIF
+
+ IF :DEF: __STARTUP_CONFIG
+Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
+ ELSE
+Stack_Align EQU 3
+ ENDIF
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+ IF :DEF: __STARTUP_CONFIG
+Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
+ ELIF :DEF: __HEAP_SIZE
+Heap_Size EQU __HEAP_SIZE
+ ELSE
+Heap_Size EQU 2048
+ ENDIF
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemoryManagement_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD POWER_CLOCK_IRQHandler
+ DCD RADIO_IRQHandler
+ DCD UARTE0_UART0_IRQHandler
+ DCD TWIM0_TWIS0_TWI0_IRQHandler
+ DCD SPIM0_SPIS0_SPI0_IRQHandler
+ DCD 0 ; Reserved
+ DCD GPIOTE_IRQHandler
+ DCD SAADC_IRQHandler
+ DCD TIMER0_IRQHandler
+ DCD TIMER1_IRQHandler
+ DCD TIMER2_IRQHandler
+ DCD RTC0_IRQHandler
+ DCD TEMP_IRQHandler
+ DCD RNG_IRQHandler
+ DCD ECB_IRQHandler
+ DCD CCM_AAR_IRQHandler
+ DCD WDT_IRQHandler
+ DCD RTC1_IRQHandler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SWI0_EGU0_IRQHandler
+ DCD SWI1_EGU1_IRQHandler
+ DCD SWI2_IRQHandler
+ DCD SWI3_IRQHandler
+ DCD SWI4_IRQHandler
+ DCD SWI5_IRQHandler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemoryManagement_Handler\
+ PROC
+ EXPORT MemoryManagement_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT POWER_CLOCK_IRQHandler [WEAK]
+ EXPORT RADIO_IRQHandler [WEAK]
+ EXPORT UARTE0_UART0_IRQHandler [WEAK]
+ EXPORT TWIM0_TWIS0_TWI0_IRQHandler [WEAK]
+ EXPORT SPIM0_SPIS0_SPI0_IRQHandler [WEAK]
+ EXPORT GPIOTE_IRQHandler [WEAK]
+ EXPORT SAADC_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT RTC0_IRQHandler [WEAK]
+ EXPORT TEMP_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT ECB_IRQHandler [WEAK]
+ EXPORT CCM_AAR_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC1_IRQHandler [WEAK]
+ EXPORT SWI0_EGU0_IRQHandler [WEAK]
+ EXPORT SWI1_EGU1_IRQHandler [WEAK]
+ EXPORT SWI2_IRQHandler [WEAK]
+ EXPORT SWI3_IRQHandler [WEAK]
+ EXPORT SWI4_IRQHandler [WEAK]
+ EXPORT SWI5_IRQHandler [WEAK]
+POWER_CLOCK_IRQHandler
+RADIO_IRQHandler
+UARTE0_UART0_IRQHandler
+TWIM0_TWIS0_TWI0_IRQHandler
+SPIM0_SPIS0_SPI0_IRQHandler
+GPIOTE_IRQHandler
+SAADC_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+RTC0_IRQHandler
+TEMP_IRQHandler
+RNG_IRQHandler
+ECB_IRQHandler
+CCM_AAR_IRQHandler
+WDT_IRQHandler
+RTC1_IRQHandler
+SWI0_EGU0_IRQHandler
+SWI1_EGU1_IRQHandler
+SWI2_IRQHandler
+SWI3_IRQHandler
+SWI4_IRQHandler
+SWI5_IRQHandler
+ B .
+ ENDP
+ ALIGN
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+
+ LDR R0, = Heap_Mem
+ LDR R1, = (Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/arm_startup_nrf52810.s b/third_party/NordicSemiconductor/nrfx/mdk/arm_startup_nrf52810.s
index 7f7545961..2f0984af8 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/arm_startup_nrf52810.s
+++ b/third_party/NordicSemiconductor/nrfx/mdk/arm_startup_nrf52810.s
@@ -211,6 +211,29 @@ Reset_Handler PROC
IMPORT SystemInit
IMPORT __main
+ ; Workaround for Errata 185 RAM: RAM corruption at extreme corners
+ ; found at the Errata document for your device located
+ ; at https://infocenter.nordicsemi.com/index.jsp
+
+ LDR R0, =0x10000130
+ LDR R0, [R0]
+ LDR R1, =0x10000134
+ LDR R1, [R1]
+
+ CMP R0, #0xA
+ BNE skip
+ CMP R1, #0x0
+ BNE skip
+
+ LDR R0, =0x40000EE4
+ LDR R2, [R0]
+ LDR R3, =0xFFFFFF8F
+ ANDS R2, R2, R3
+ LDR R3, =0x00000040
+ ORRS R2, R2, R3
+ STR R2, [R0]
+
+skip
LDR R0, =SystemInit
BLX R0
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/arm_startup_nrf52833.s b/third_party/NordicSemiconductor/nrfx/mdk/arm_startup_nrf52833.s
new file mode 100644
index 000000000..a6209962d
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/arm_startup_nrf52833.s
@@ -0,0 +1,379 @@
+; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the License); you may
+; not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+; NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+ IF :DEF: __STARTUP_CONFIG
+#ifdef __STARTUP_CONFIG
+#include "startup_config.h"
+#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
+#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+#endif
+#endif
+ ENDIF
+
+ IF :DEF: __STARTUP_CONFIG
+Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
+ ELIF :DEF: __STACK_SIZE
+Stack_Size EQU __STACK_SIZE
+ ELSE
+Stack_Size EQU 8192
+ ENDIF
+
+ IF :DEF: __STARTUP_CONFIG
+Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
+ ELSE
+Stack_Align EQU 3
+ ENDIF
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+ IF :DEF: __STARTUP_CONFIG
+Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
+ ELIF :DEF: __HEAP_SIZE
+Heap_Size EQU __HEAP_SIZE
+ ELSE
+Heap_Size EQU 8192
+ ENDIF
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemoryManagement_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD POWER_CLOCK_IRQHandler
+ DCD RADIO_IRQHandler
+ DCD UARTE0_UART0_IRQHandler
+ DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ DCD NFCT_IRQHandler
+ DCD GPIOTE_IRQHandler
+ DCD SAADC_IRQHandler
+ DCD TIMER0_IRQHandler
+ DCD TIMER1_IRQHandler
+ DCD TIMER2_IRQHandler
+ DCD RTC0_IRQHandler
+ DCD TEMP_IRQHandler
+ DCD RNG_IRQHandler
+ DCD ECB_IRQHandler
+ DCD CCM_AAR_IRQHandler
+ DCD WDT_IRQHandler
+ DCD RTC1_IRQHandler
+ DCD QDEC_IRQHandler
+ DCD COMP_LPCOMP_IRQHandler
+ DCD SWI0_EGU0_IRQHandler
+ DCD SWI1_EGU1_IRQHandler
+ DCD SWI2_EGU2_IRQHandler
+ DCD SWI3_EGU3_IRQHandler
+ DCD SWI4_EGU4_IRQHandler
+ DCD SWI5_EGU5_IRQHandler
+ DCD TIMER3_IRQHandler
+ DCD TIMER4_IRQHandler
+ DCD PWM0_IRQHandler
+ DCD PDM_IRQHandler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD MWU_IRQHandler
+ DCD PWM1_IRQHandler
+ DCD PWM2_IRQHandler
+ DCD SPIM2_SPIS2_SPI2_IRQHandler
+ DCD RTC2_IRQHandler
+ DCD I2S_IRQHandler
+ DCD FPU_IRQHandler
+ DCD USBD_IRQHandler
+ DCD UARTE1_IRQHandler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PWM3_IRQHandler
+ DCD 0 ; Reserved
+ DCD SPIM3_IRQHandler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemoryManagement_Handler\
+ PROC
+ EXPORT MemoryManagement_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT POWER_CLOCK_IRQHandler [WEAK]
+ EXPORT RADIO_IRQHandler [WEAK]
+ EXPORT UARTE0_UART0_IRQHandler [WEAK]
+ EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
+ EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
+ EXPORT NFCT_IRQHandler [WEAK]
+ EXPORT GPIOTE_IRQHandler [WEAK]
+ EXPORT SAADC_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT RTC0_IRQHandler [WEAK]
+ EXPORT TEMP_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT ECB_IRQHandler [WEAK]
+ EXPORT CCM_AAR_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC1_IRQHandler [WEAK]
+ EXPORT QDEC_IRQHandler [WEAK]
+ EXPORT COMP_LPCOMP_IRQHandler [WEAK]
+ EXPORT SWI0_EGU0_IRQHandler [WEAK]
+ EXPORT SWI1_EGU1_IRQHandler [WEAK]
+ EXPORT SWI2_EGU2_IRQHandler [WEAK]
+ EXPORT SWI3_EGU3_IRQHandler [WEAK]
+ EXPORT SWI4_EGU4_IRQHandler [WEAK]
+ EXPORT SWI5_EGU5_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT TIMER4_IRQHandler [WEAK]
+ EXPORT PWM0_IRQHandler [WEAK]
+ EXPORT PDM_IRQHandler [WEAK]
+ EXPORT MWU_IRQHandler [WEAK]
+ EXPORT PWM1_IRQHandler [WEAK]
+ EXPORT PWM2_IRQHandler [WEAK]
+ EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
+ EXPORT RTC2_IRQHandler [WEAK]
+ EXPORT I2S_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT USBD_IRQHandler [WEAK]
+ EXPORT UARTE1_IRQHandler [WEAK]
+ EXPORT PWM3_IRQHandler [WEAK]
+ EXPORT SPIM3_IRQHandler [WEAK]
+POWER_CLOCK_IRQHandler
+RADIO_IRQHandler
+UARTE0_UART0_IRQHandler
+SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+NFCT_IRQHandler
+GPIOTE_IRQHandler
+SAADC_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+RTC0_IRQHandler
+TEMP_IRQHandler
+RNG_IRQHandler
+ECB_IRQHandler
+CCM_AAR_IRQHandler
+WDT_IRQHandler
+RTC1_IRQHandler
+QDEC_IRQHandler
+COMP_LPCOMP_IRQHandler
+SWI0_EGU0_IRQHandler
+SWI1_EGU1_IRQHandler
+SWI2_EGU2_IRQHandler
+SWI3_EGU3_IRQHandler
+SWI4_EGU4_IRQHandler
+SWI5_EGU5_IRQHandler
+TIMER3_IRQHandler
+TIMER4_IRQHandler
+PWM0_IRQHandler
+PDM_IRQHandler
+MWU_IRQHandler
+PWM1_IRQHandler
+PWM2_IRQHandler
+SPIM2_SPIS2_SPI2_IRQHandler
+RTC2_IRQHandler
+I2S_IRQHandler
+FPU_IRQHandler
+USBD_IRQHandler
+UARTE1_IRQHandler
+PWM3_IRQHandler
+SPIM3_IRQHandler
+ B .
+ ENDP
+ ALIGN
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+
+ LDR R0, = Heap_Mem
+ LDR R1, = (Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52805.S b/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52805.S
new file mode 100644
index 000000000..d72562209
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52805.S
@@ -0,0 +1,390 @@
+/*
+
+Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: Apache-2.0
+
+Licensed under the Apache License, Version 2.0 (the License); you may
+not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an AS IS BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+*/
+
+ .syntax unified
+ .arch armv7e-m
+
+#ifdef __STARTUP_CONFIG
+#include "startup_config.h"
+#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
+#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+#endif
+#endif
+
+ .section .stack
+#if defined(__STARTUP_CONFIG)
+ .align __STARTUP_CONFIG_STACK_ALIGNEMENT
+ .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
+#elif defined(__STACK_SIZE)
+ .align 3
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .align 3
+ .equ Stack_Size, 2048
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#if defined(__STARTUP_CONFIG)
+ .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
+#elif defined(__HEAP_SIZE)
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 2048
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler
+ .long NMI_Handler
+ .long HardFault_Handler
+ .long MemoryManagement_Handler
+ .long BusFault_Handler
+ .long UsageFault_Handler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long SVC_Handler
+ .long DebugMon_Handler
+ .long 0 /*Reserved */
+ .long PendSV_Handler
+ .long SysTick_Handler
+
+ /* External Interrupts */
+ .long POWER_CLOCK_IRQHandler
+ .long RADIO_IRQHandler
+ .long UARTE0_UART0_IRQHandler
+ .long TWIM0_TWIS0_TWI0_IRQHandler
+ .long SPIM0_SPIS0_SPI0_IRQHandler
+ .long 0 /*Reserved */
+ .long GPIOTE_IRQHandler
+ .long SAADC_IRQHandler
+ .long TIMER0_IRQHandler
+ .long TIMER1_IRQHandler
+ .long TIMER2_IRQHandler
+ .long RTC0_IRQHandler
+ .long TEMP_IRQHandler
+ .long RNG_IRQHandler
+ .long ECB_IRQHandler
+ .long CCM_AAR_IRQHandler
+ .long WDT_IRQHandler
+ .long RTC1_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long SWI0_EGU0_IRQHandler
+ .long SWI1_EGU1_IRQHandler
+ .long SWI2_IRQHandler
+ .long SWI3_IRQHandler
+ .long SWI4_IRQHandler
+ .long SWI5_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+
+/* Loop to copy data from read only memory to RAM.
+ * The ranges of copy from/to are specified by following symbols:
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to.
+ * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
+ * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__bss_start__
+
+ subs r3, r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define __STARTUP_CLEAR_BSS to enable it in this startup. This section
+ * clears the RAM where BSS data is located.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+#ifdef __STARTUP_CLEAR_BSS
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS */
+
+/* Execute SystemInit function. */
+ bl SystemInit
+
+/* Call _start function provided by libraries.
+ * If those libraries are not accessible, define __START as your entry point.
+ */
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ b .
+ .size NMI_Handler, . - NMI_Handler
+
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ b .
+ .size HardFault_Handler, . - HardFault_Handler
+
+
+ .weak MemoryManagement_Handler
+ .type MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+ b .
+ .size MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ b .
+ .size BusFault_Handler, . - BusFault_Handler
+
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ b .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ b .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak DebugMon_Handler
+ .type DebugMon_Handler, %function
+DebugMon_Handler:
+ b .
+ .size DebugMon_Handler, . - DebugMon_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ b .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ b .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ POWER_CLOCK_IRQHandler
+ IRQ RADIO_IRQHandler
+ IRQ UARTE0_UART0_IRQHandler
+ IRQ TWIM0_TWIS0_TWI0_IRQHandler
+ IRQ SPIM0_SPIS0_SPI0_IRQHandler
+ IRQ GPIOTE_IRQHandler
+ IRQ SAADC_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ RTC0_IRQHandler
+ IRQ TEMP_IRQHandler
+ IRQ RNG_IRQHandler
+ IRQ ECB_IRQHandler
+ IRQ CCM_AAR_IRQHandler
+ IRQ WDT_IRQHandler
+ IRQ RTC1_IRQHandler
+ IRQ SWI0_EGU0_IRQHandler
+ IRQ SWI1_EGU1_IRQHandler
+ IRQ SWI2_IRQHandler
+ IRQ SWI3_IRQHandler
+ IRQ SWI4_IRQHandler
+ IRQ SWI5_IRQHandler
+
+ .end
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52810.S b/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52810.S
index ab01718a8..4980201e4 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52810.S
+++ b/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52810.S
@@ -216,6 +216,29 @@ __isr_vector:
.type Reset_Handler, %function
Reset_Handler:
+ /* Workaround for Errata 185 RAM: RAM corruption at extreme corners
+ * found at the Errata document for your device located
+ * at https://infocenter.nordicsemi.com/index.jsp */
+
+ LDR R0, =0x10000130
+ LDR R0, [R0]
+ LDR R1, =0x10000134
+ LDR R1, [R1]
+
+ CMP R0, #0xA
+ BNE skip
+ CMP R1, #0x0
+ BNE skip
+
+ LDR R0, =0x40000EE4
+ LDR R2, [R0]
+ LDR R3, =0xFFFFFF8F
+ ANDS R2, R2, R3
+ LDR R3, =0x00000040
+ ORRS R2, R2, R3
+ STR R2, [R0]
+
+skip:
/* Loop to copy data from read only memory to RAM.
* The ranges of copy from/to are specified by following symbols:
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52833.S b/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52833.S
new file mode 100644
index 000000000..e7817790f
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/gcc_startup_nrf52833.S
@@ -0,0 +1,408 @@
+/*
+
+Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: Apache-2.0
+
+Licensed under the Apache License, Version 2.0 (the License); you may
+not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an AS IS BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+*/
+
+ .syntax unified
+ .arch armv7e-m
+
+#ifdef __STARTUP_CONFIG
+#include "startup_config.h"
+#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
+#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+#endif
+#endif
+
+ .section .stack
+#if defined(__STARTUP_CONFIG)
+ .align __STARTUP_CONFIG_STACK_ALIGNEMENT
+ .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
+#elif defined(__STACK_SIZE)
+ .align 3
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .align 3
+ .equ Stack_Size, 8192
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#if defined(__STARTUP_CONFIG)
+ .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
+#elif defined(__HEAP_SIZE)
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 8192
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler
+ .long NMI_Handler
+ .long HardFault_Handler
+ .long MemoryManagement_Handler
+ .long BusFault_Handler
+ .long UsageFault_Handler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long SVC_Handler
+ .long DebugMon_Handler
+ .long 0 /*Reserved */
+ .long PendSV_Handler
+ .long SysTick_Handler
+
+ /* External Interrupts */
+ .long POWER_CLOCK_IRQHandler
+ .long RADIO_IRQHandler
+ .long UARTE0_UART0_IRQHandler
+ .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ .long NFCT_IRQHandler
+ .long GPIOTE_IRQHandler
+ .long SAADC_IRQHandler
+ .long TIMER0_IRQHandler
+ .long TIMER1_IRQHandler
+ .long TIMER2_IRQHandler
+ .long RTC0_IRQHandler
+ .long TEMP_IRQHandler
+ .long RNG_IRQHandler
+ .long ECB_IRQHandler
+ .long CCM_AAR_IRQHandler
+ .long WDT_IRQHandler
+ .long RTC1_IRQHandler
+ .long QDEC_IRQHandler
+ .long COMP_LPCOMP_IRQHandler
+ .long SWI0_EGU0_IRQHandler
+ .long SWI1_EGU1_IRQHandler
+ .long SWI2_EGU2_IRQHandler
+ .long SWI3_EGU3_IRQHandler
+ .long SWI4_EGU4_IRQHandler
+ .long SWI5_EGU5_IRQHandler
+ .long TIMER3_IRQHandler
+ .long TIMER4_IRQHandler
+ .long PWM0_IRQHandler
+ .long PDM_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long MWU_IRQHandler
+ .long PWM1_IRQHandler
+ .long PWM2_IRQHandler
+ .long SPIM2_SPIS2_SPI2_IRQHandler
+ .long RTC2_IRQHandler
+ .long I2S_IRQHandler
+ .long FPU_IRQHandler
+ .long USBD_IRQHandler
+ .long UARTE1_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long PWM3_IRQHandler
+ .long 0 /*Reserved */
+ .long SPIM3_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+
+/* Loop to copy data from read only memory to RAM.
+ * The ranges of copy from/to are specified by following symbols:
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to.
+ * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
+ * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__bss_start__
+
+ subs r3, r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define __STARTUP_CLEAR_BSS to enable it in this startup. This section
+ * clears the RAM where BSS data is located.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+#ifdef __STARTUP_CLEAR_BSS
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS */
+
+/* Execute SystemInit function. */
+ bl SystemInit
+
+/* Call _start function provided by libraries.
+ * If those libraries are not accessible, define __START as your entry point.
+ */
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ b .
+ .size NMI_Handler, . - NMI_Handler
+
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ b .
+ .size HardFault_Handler, . - HardFault_Handler
+
+
+ .weak MemoryManagement_Handler
+ .type MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+ b .
+ .size MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ b .
+ .size BusFault_Handler, . - BusFault_Handler
+
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ b .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ b .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak DebugMon_Handler
+ .type DebugMon_Handler, %function
+DebugMon_Handler:
+ b .
+ .size DebugMon_Handler, . - DebugMon_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ b .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ b .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ POWER_CLOCK_IRQHandler
+ IRQ RADIO_IRQHandler
+ IRQ UARTE0_UART0_IRQHandler
+ IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ IRQ NFCT_IRQHandler
+ IRQ GPIOTE_IRQHandler
+ IRQ SAADC_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ RTC0_IRQHandler
+ IRQ TEMP_IRQHandler
+ IRQ RNG_IRQHandler
+ IRQ ECB_IRQHandler
+ IRQ CCM_AAR_IRQHandler
+ IRQ WDT_IRQHandler
+ IRQ RTC1_IRQHandler
+ IRQ QDEC_IRQHandler
+ IRQ COMP_LPCOMP_IRQHandler
+ IRQ SWI0_EGU0_IRQHandler
+ IRQ SWI1_EGU1_IRQHandler
+ IRQ SWI2_EGU2_IRQHandler
+ IRQ SWI3_EGU3_IRQHandler
+ IRQ SWI4_EGU4_IRQHandler
+ IRQ SWI5_EGU5_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ TIMER4_IRQHandler
+ IRQ PWM0_IRQHandler
+ IRQ PDM_IRQHandler
+ IRQ MWU_IRQHandler
+ IRQ PWM1_IRQHandler
+ IRQ PWM2_IRQHandler
+ IRQ SPIM2_SPIS2_SPI2_IRQHandler
+ IRQ RTC2_IRQHandler
+ IRQ I2S_IRQHandler
+ IRQ FPU_IRQHandler
+ IRQ USBD_IRQHandler
+ IRQ UARTE1_IRQHandler
+ IRQ PWM3_IRQHandler
+ IRQ SPIM3_IRQHandler
+
+ .end
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/iar_startup_nrf52805.s b/third_party/NordicSemiconductor/nrfx/mdk/iar_startup_nrf52805.s
new file mode 100644
index 000000000..4b1200c71
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/iar_startup_nrf52805.s
@@ -0,0 +1,386 @@
+; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the License); you may
+; not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+; NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+
+ MODULE ?cstartup
+
+#if defined(__STARTUP_CONFIG)
+
+ #include "startup_config.h"
+
+ #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
+ #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+ #endif
+
+ SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
+ DS8 __STARTUP_CONFIG_STACK_SIZE
+
+ SECTION HEAP:DATA:NOROOT(3)
+ DS8 __STARTUP_CONFIG_HEAP_SIZE
+
+#else
+
+ ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
+ ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+#endif
+
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemoryManagement_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD POWER_CLOCK_IRQHandler
+ DCD RADIO_IRQHandler
+ DCD UARTE0_UART0_IRQHandler
+ DCD TWIM0_TWIS0_TWI0_IRQHandler
+ DCD SPIM0_SPIS0_SPI0_IRQHandler
+ DCD 0 ; Reserved
+ DCD GPIOTE_IRQHandler
+ DCD SAADC_IRQHandler
+ DCD TIMER0_IRQHandler
+ DCD TIMER1_IRQHandler
+ DCD TIMER2_IRQHandler
+ DCD RTC0_IRQHandler
+ DCD TEMP_IRQHandler
+ DCD RNG_IRQHandler
+ DCD ECB_IRQHandler
+ DCD CCM_AAR_IRQHandler
+ DCD WDT_IRQHandler
+ DCD RTC1_IRQHandler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SWI0_EGU0_IRQHandler
+ DCD SWI1_EGU1_IRQHandler
+ DCD SWI2_IRQHandler
+ DCD SWI3_IRQHandler
+ DCD SWI4_IRQHandler
+ DCD SWI5_IRQHandler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+
+__Vectors_End
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+; Default handlers.
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ ; Dummy exception handlers
+
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B .
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B .
+
+ PUBWEAK MemoryManagement_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemoryManagement_Handler
+ B .
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B .
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B .
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B .
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B .
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B .
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B .
+
+
+ ; Dummy interrupt handlers
+
+ PUBWEAK POWER_CLOCK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+POWER_CLOCK_IRQHandler
+ B .
+
+ PUBWEAK RADIO_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RADIO_IRQHandler
+ B .
+
+ PUBWEAK UARTE0_UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UARTE0_UART0_IRQHandler
+ B .
+
+ PUBWEAK TWIM0_TWIS0_TWI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TWIM0_TWIS0_TWI0_IRQHandler
+ B .
+
+ PUBWEAK SPIM0_SPIS0_SPI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPIM0_SPIS0_SPI0_IRQHandler
+ B .
+
+ PUBWEAK GPIOTE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIOTE_IRQHandler
+ B .
+
+ PUBWEAK SAADC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SAADC_IRQHandler
+ B .
+
+ PUBWEAK TIMER0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER0_IRQHandler
+ B .
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER1_IRQHandler
+ B .
+
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER2_IRQHandler
+ B .
+
+ PUBWEAK RTC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+ B .
+
+ PUBWEAK TEMP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TEMP_IRQHandler
+ B .
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RNG_IRQHandler
+ B .
+
+ PUBWEAK ECB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ECB_IRQHandler
+ B .
+
+ PUBWEAK CCM_AAR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CCM_AAR_IRQHandler
+ B .
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+ B .
+
+ PUBWEAK RTC1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+ B .
+
+ PUBWEAK SWI0_EGU0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI0_EGU0_IRQHandler
+ B .
+
+ PUBWEAK SWI1_EGU1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI1_EGU1_IRQHandler
+ B .
+
+ PUBWEAK SWI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI2_IRQHandler
+ B .
+
+ PUBWEAK SWI3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI3_IRQHandler
+ B .
+
+ PUBWEAK SWI4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI4_IRQHandler
+ B .
+
+ PUBWEAK SWI5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI5_IRQHandler
+ B .
+
+ END
+
+
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/iar_startup_nrf52810.s b/third_party/NordicSemiconductor/nrfx/mdk/iar_startup_nrf52810.s
index e22585821..43fe6ec2b 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/iar_startup_nrf52810.s
+++ b/third_party/NordicSemiconductor/nrfx/mdk/iar_startup_nrf52810.s
@@ -209,6 +209,29 @@ __Vectors_Size EQU __Vectors_End - __Vectors
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
+ /* Workaround for Errata 185 RAM: RAM corruption at extreme corners
+ * found at the Errata document for your device located
+ * at https://infocenter.nordicsemi.com/index.jsp */
+
+ LDR R0, =0x10000130
+ LDR R0, [R0]
+ LDR R1, =0x10000134
+ LDR R1, [R1]
+
+ CMP R0, #0xA
+ BNE skip
+ CMP R1, #0x0
+ BNE skip
+
+ LDR R0, =0x40000EE4
+ LDR R2, [R0]
+ LDR R3, =0xFFFFFF8F
+ ANDS R2, R2, R3
+ LDR R3, =0x00000040
+ ORRS R2, R2, R3
+ STR R2, [R0]
+
+skip
LDR R0, =SystemInit
BLX R0
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/iar_startup_nrf52833.s b/third_party/NordicSemiconductor/nrfx/mdk/iar_startup_nrf52833.s
new file mode 100644
index 000000000..417014f2d
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/iar_startup_nrf52833.s
@@ -0,0 +1,476 @@
+; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the License); you may
+; not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+; NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+
+ MODULE ?cstartup
+
+#if defined(__STARTUP_CONFIG)
+
+ #include "startup_config.h"
+
+ #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
+ #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+ #endif
+
+ SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
+ DS8 __STARTUP_CONFIG_STACK_SIZE
+
+ SECTION HEAP:DATA:NOROOT(3)
+ DS8 __STARTUP_CONFIG_HEAP_SIZE
+
+#else
+
+ ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
+ ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+#endif
+
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemoryManagement_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD POWER_CLOCK_IRQHandler
+ DCD RADIO_IRQHandler
+ DCD UARTE0_UART0_IRQHandler
+ DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ DCD NFCT_IRQHandler
+ DCD GPIOTE_IRQHandler
+ DCD SAADC_IRQHandler
+ DCD TIMER0_IRQHandler
+ DCD TIMER1_IRQHandler
+ DCD TIMER2_IRQHandler
+ DCD RTC0_IRQHandler
+ DCD TEMP_IRQHandler
+ DCD RNG_IRQHandler
+ DCD ECB_IRQHandler
+ DCD CCM_AAR_IRQHandler
+ DCD WDT_IRQHandler
+ DCD RTC1_IRQHandler
+ DCD QDEC_IRQHandler
+ DCD COMP_LPCOMP_IRQHandler
+ DCD SWI0_EGU0_IRQHandler
+ DCD SWI1_EGU1_IRQHandler
+ DCD SWI2_EGU2_IRQHandler
+ DCD SWI3_EGU3_IRQHandler
+ DCD SWI4_EGU4_IRQHandler
+ DCD SWI5_EGU5_IRQHandler
+ DCD TIMER3_IRQHandler
+ DCD TIMER4_IRQHandler
+ DCD PWM0_IRQHandler
+ DCD PDM_IRQHandler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD MWU_IRQHandler
+ DCD PWM1_IRQHandler
+ DCD PWM2_IRQHandler
+ DCD SPIM2_SPIS2_SPI2_IRQHandler
+ DCD RTC2_IRQHandler
+ DCD I2S_IRQHandler
+ DCD FPU_IRQHandler
+ DCD USBD_IRQHandler
+ DCD UARTE1_IRQHandler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PWM3_IRQHandler
+ DCD 0 ; Reserved
+ DCD SPIM3_IRQHandler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+
+__Vectors_End
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+; Default handlers.
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ ; Dummy exception handlers
+
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B .
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B .
+
+ PUBWEAK MemoryManagement_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemoryManagement_Handler
+ B .
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B .
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B .
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B .
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B .
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B .
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B .
+
+
+ ; Dummy interrupt handlers
+
+ PUBWEAK POWER_CLOCK_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+POWER_CLOCK_IRQHandler
+ B .
+
+ PUBWEAK RADIO_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RADIO_IRQHandler
+ B .
+
+ PUBWEAK UARTE0_UART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UARTE0_UART0_IRQHandler
+ B .
+
+ PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ B .
+
+ PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ B .
+
+ PUBWEAK NFCT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NFCT_IRQHandler
+ B .
+
+ PUBWEAK GPIOTE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIOTE_IRQHandler
+ B .
+
+ PUBWEAK SAADC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SAADC_IRQHandler
+ B .
+
+ PUBWEAK TIMER0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER0_IRQHandler
+ B .
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER1_IRQHandler
+ B .
+
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER2_IRQHandler
+ B .
+
+ PUBWEAK RTC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+ B .
+
+ PUBWEAK TEMP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TEMP_IRQHandler
+ B .
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RNG_IRQHandler
+ B .
+
+ PUBWEAK ECB_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ECB_IRQHandler
+ B .
+
+ PUBWEAK CCM_AAR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CCM_AAR_IRQHandler
+ B .
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+ B .
+
+ PUBWEAK RTC1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+ B .
+
+ PUBWEAK QDEC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+QDEC_IRQHandler
+ B .
+
+ PUBWEAK COMP_LPCOMP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+COMP_LPCOMP_IRQHandler
+ B .
+
+ PUBWEAK SWI0_EGU0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI0_EGU0_IRQHandler
+ B .
+
+ PUBWEAK SWI1_EGU1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI1_EGU1_IRQHandler
+ B .
+
+ PUBWEAK SWI2_EGU2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI2_EGU2_IRQHandler
+ B .
+
+ PUBWEAK SWI3_EGU3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI3_EGU3_IRQHandler
+ B .
+
+ PUBWEAK SWI4_EGU4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI4_EGU4_IRQHandler
+ B .
+
+ PUBWEAK SWI5_EGU5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SWI5_EGU5_IRQHandler
+ B .
+
+ PUBWEAK TIMER3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER3_IRQHandler
+ B .
+
+ PUBWEAK TIMER4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER4_IRQHandler
+ B .
+
+ PUBWEAK PWM0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PWM0_IRQHandler
+ B .
+
+ PUBWEAK PDM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PDM_IRQHandler
+ B .
+
+ PUBWEAK MWU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MWU_IRQHandler
+ B .
+
+ PUBWEAK PWM1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PWM1_IRQHandler
+ B .
+
+ PUBWEAK PWM2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PWM2_IRQHandler
+ B .
+
+ PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPIM2_SPIS2_SPI2_IRQHandler
+ B .
+
+ PUBWEAK RTC2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTC2_IRQHandler
+ B .
+
+ PUBWEAK I2S_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2S_IRQHandler
+ B .
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FPU_IRQHandler
+ B .
+
+ PUBWEAK USBD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USBD_IRQHandler
+ B .
+
+ PUBWEAK UARTE1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UARTE1_IRQHandler
+ B .
+
+ PUBWEAK PWM3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PWM3_IRQHandler
+ B .
+
+ PUBWEAK SPIM3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPIM3_IRQHandler
+ B .
+
+ END
+
+
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf.h
index 8649d0bfe..becee3d87 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf.h
@@ -34,9 +34,27 @@ POSSIBILITY OF SUCH DAMAGE.
#define NRF_H
/* MDK version */
-#define MDK_MAJOR_VERSION 8
-#define MDK_MINOR_VERSION 23
-#define MDK_MICRO_VERSION 1
+#define MDK_MAJOR_VERSION 8
+#define MDK_MINOR_VERSION 27
+#define MDK_MICRO_VERSION 0
+
+/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */
+#if defined (NRF51422_XXAA) ||\
+ defined (NRF51422_XXAB) ||\
+ defined (NRF51422_XXAC) ||\
+ defined (NRF51801_XXAB) ||\
+ defined (NRF51802_XXAA) ||\
+ defined (NRF51822_XXAA) ||\
+ defined (NRF51822_XXAB) ||\
+ defined (NRF51822_XXAC) ||\
+ defined (NRF51824_XXAA)
+ #ifndef NRF51_SERIES
+ #define NRF51_SERIES
+ #endif
+ #ifndef NRF51
+ #define NRF51
+ #endif
+#endif
/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */
#if defined (NRF52)
@@ -46,7 +64,7 @@ POSSIBILITY OF SUCH DAMAGE.
#endif
/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */
-#if defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52840_XXAA)
+#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA)
#ifndef NRF52_SERIES
#define NRF52_SERIES
#endif
@@ -58,7 +76,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define NRF91_SERIES
#endif
#endif
-
+
+
#if defined(_WIN32)
/* Do not include nrf specific files when building for PC host */
#elif defined(__unix)
@@ -72,36 +91,49 @@ POSSIBILITY OF SUCH DAMAGE.
#include "nrf51.h"
#include "nrf51_bitfields.h"
#include "nrf51_deprecated.h"
-
+
+ #elif defined (NRF52805_XXAA)
+ #include "nrf52805.h"
+ #include "nrf52805_bitfields.h"
+ #include "nrf51_to_nrf52810.h"
+ #include "nrf52_to_nrf52810.h"
+ #include "nrf52810_to_nrf52811.h"
#elif defined (NRF52810_XXAA)
#include "nrf52810.h"
#include "nrf52810_bitfields.h"
#include "nrf51_to_nrf52810.h"
#include "nrf52_to_nrf52810.h"
+ #include "nrf52810_name_change.h"
#elif defined (NRF52811_XXAA)
#include "nrf52811.h"
#include "nrf52811_bitfields.h"
#include "nrf51_to_nrf52810.h"
- #include "nrf52_to_nrf52810.h"
- #include "nrf52810_to_nrf52811.h"
+ #include "nrf52_to_nrf52810.h"
+ #include "nrf52810_to_nrf52811.h"
#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
#include "nrf52.h"
#include "nrf52_bitfields.h"
#include "nrf51_to_nrf52.h"
#include "nrf52_name_change.h"
+ #elif defined (NRF52833_XXAA)
+ #include "nrf52833.h"
+ #include "nrf52833_bitfields.h"
+ #include "nrf52_to_nrf52833.h"
+ #include "nrf51_to_nrf52.h"
#elif defined (NRF52840_XXAA)
#include "nrf52840.h"
#include "nrf52840_bitfields.h"
#include "nrf51_to_nrf52840.h"
#include "nrf52_to_nrf52840.h"
-
+
#elif defined (NRF9160_XXAA)
#include "nrf9160.h"
#include "nrf9160_bitfields.h"
+ #include "nrf9160_name_change.h"
#else
#error "Device must be defined. See nrf.h."
- #endif /* NRF51, NRF52810_XXAA, NRF52811_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52840_XXAA, NRF9160_XXAA */
+ #endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF9160_XXAA */
#include "compiler_abstraction.h"
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf51.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf51.h
index 903423952..d8c101edd 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf51.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf51.h
@@ -30,10 +30,10 @@
* @file nrf51.h
* @brief CMSIS HeaderFile
* @version 522
- * @date 17. January 2019
- * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39
+ * @date 23. August 2019
+ * @note Generated by SVDConv V3.3.25 on Friday, 23.08.2019 12:15:12
* from File 'nrf51.svd',
- * last modified on Thursday, 17.01.2019 16:25:34
+ * last modified on Friday, 23.08.2019 10:15:08
*/
@@ -111,10 +111,11 @@ typedef enum {
/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */
#define __CM0_REV 0x0301U /*!< CM0 Core Revision */
#define __DSP_PRESENT 0 /*!< DSP present or not */
-#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __VTOR_PRESENT 0 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 0 /*!< MPU present */
+#define __FPU_PRESENT 0 /*!< FPU present */
/** @} */ /* End of group Configuration_of_CMSIS */
@@ -1278,7 +1279,7 @@ typedef struct { /*!< (@ 0x50000000) GPIO Structu
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
-#elif (__ARMCC_VERSION >= 6010050)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52.h
index 5e67f0b1d..7496083b9 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52.h
@@ -30,10 +30,10 @@
* @file nrf52.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 17. January 2019
- * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39
+ * @date 23. August 2019
+ * @note Generated by SVDConv V3.3.25 on Friday, 23.08.2019 12:15:13
* from File 'nrf52.svd',
- * last modified on Thursday, 17.01.2019 16:25:35
+ * last modified on Friday, 23.08.2019 10:15:08
*/
@@ -132,8 +132,8 @@ typedef enum {
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __MPU_PRESENT 1 /*!< MPU present */
+#define __FPU_PRESENT 1 /*!< FPU present */
/** @} */ /* End of group Configuration_of_CMSIS */
@@ -2418,7 +2418,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
-#elif (__ARMCC_VERSION >= 6010050)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52805.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52805.h
new file mode 100644
index 000000000..e1f2b5484
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52805.h
@@ -0,0 +1,1766 @@
+/*
+ * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @file nrf52805.h
+ * @brief CMSIS HeaderFile
+ * @version 1
+ * @date 23. August 2019
+ * @note Generated by SVDConv V3.3.25 on Friday, 23.08.2019 12:15:13
+ * from File 'nrf52805.svd',
+ * last modified on Friday, 23.08.2019 10:15:08
+ */
+
+
+
+/** @addtogroup Nordic Semiconductor
+ * @{
+ */
+
+
+/** @addtogroup nrf52805
+ * @{
+ */
+
+
+#ifndef NRF52805_H
+#define NRF52805_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+typedef enum {
+/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+/* ========================================== nrf52805 Specific Interrupt Numbers ========================================== */
+ POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
+ RADIO_IRQn = 1, /*!< 1 RADIO */
+ UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */
+ TWIM0_TWIS0_TWI0_IRQn = 3, /*!< 3 TWIM0_TWIS0_TWI0 */
+ SPIM0_SPIS0_SPI0_IRQn = 4, /*!< 4 SPIM0_SPIS0_SPI0 */
+ GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
+ SAADC_IRQn = 7, /*!< 7 SAADC */
+ TIMER0_IRQn = 8, /*!< 8 TIMER0 */
+ TIMER1_IRQn = 9, /*!< 9 TIMER1 */
+ TIMER2_IRQn = 10, /*!< 10 TIMER2 */
+ RTC0_IRQn = 11, /*!< 11 RTC0 */
+ TEMP_IRQn = 12, /*!< 12 TEMP */
+ RNG_IRQn = 13, /*!< 13 RNG */
+ ECB_IRQn = 14, /*!< 14 ECB */
+ CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
+ WDT_IRQn = 16, /*!< 16 WDT */
+ RTC1_IRQn = 17, /*!< 17 RTC1 */
+ SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
+ SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
+ SWI2_IRQn = 22, /*!< 22 SWI2 */
+ SWI3_IRQn = 23, /*!< 23 SWI3 */
+ SWI4_IRQn = 24, /*!< 24 SWI4 */
+ SWI5_IRQn = 25 /*!< 25 SWI5 */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
+#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __DSP_PRESENT 0 /*!< DSP present or not */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 1 /*!< MPU present */
+#define __FPU_PRESENT 0 /*!< FPU present */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
+#include "system_nrf52805.h" /*!< nrf52805 System */
+
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+#endif
+
+
+/* ======================================== Start of section using anonymous unions ======================================== */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+ #pragma clang diagnostic ignored "-Wnested-anon-types"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Cluster Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+
+/**
+ * @brief FICR_INFO [INFO] (Device info)
+ */
+typedef struct {
+ __IM uint32_t PART; /*!< (@ 0x00000000) Part code */
+ __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part variant, hardware version and production
+ configuration */
+ __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */
+ __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */
+ __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */
+} FICR_INFO_Type; /*!< Size = 20 (0x14) */
+
+
+/**
+ * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients)
+ */
+typedef struct {
+ __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */
+ __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */
+ __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */
+ __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */
+ __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */
+ __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */
+ __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */
+ __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */
+ __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */
+ __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */
+ __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */
+ __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */
+ __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */
+ __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */
+ __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */
+ __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */
+ __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */
+} FICR_TEMP_Type; /*!< Size = 68 (0x44) */
+
+
+/**
+ * @brief POWER_RAM [RAM] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register.
+ The RAM size will vary depending on product
+ variant, and the RAMn register will only
+ be present if the corresponding RAM AHB
+ slave is present on the device. */
+ __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */
+ __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear
+ register */
+ __IM uint32_t RESERVED;
+} POWER_RAM_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief UART_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */
+ __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */
+ __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */
+ __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */
+} UART_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief UARTE_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */
+ __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */
+ __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */
+ __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */
+} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief UARTE_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} UARTE_RXD_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief UARTE_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} UARTE_TXD_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief TWI_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */
+} TWI_PSEL_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief TWIM_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */
+} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief TWIM_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIM_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWIM_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIM_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWIS_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */
+} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief TWIS_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIS_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWIS_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIS_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPI_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */
+ __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */
+} SPI_PSEL_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief SPIM_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */
+ __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */
+} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief SPIM_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIM_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIM_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIM_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIS_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */
+ __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */
+} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIS_RXD [RXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIS_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIS_TXD [TXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIS_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.)
+ */
+typedef struct {
+ __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or
+ above CH[n].LIMIT.HIGH */
+ __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or
+ below CH[n].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SAADC_CH [CH] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection
+ for CH[n] */
+ __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection
+ for CH[n] */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for
+ CH[n] */
+ __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event
+ monitoring a channel */
+} SAADC_CH_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last
+ START */
+} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks)
+ */
+typedef struct {
+ __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */
+ __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */
+} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief PPI_CH [CH] (PPI Channel)
+ */
+typedef struct {
+ __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */
+ __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */
+} PPI_CH_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief PPI_FORK [FORK] (Fork)
+ */
+typedef struct {
+ __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */
+} PPI_FORK_Type; /*!< Size = 4 (0x4) */
+
+
+/** @} */ /* End of group Device_Peripheral_clusters */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ FICR ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Factory information configuration registers (FICR)
+ */
+
+typedef struct { /*!< (@ 0x10000000) FICR Structure */
+ __IM uint32_t RESERVED[4];
+ __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */
+ __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */
+ __IM uint32_t RESERVED1[18];
+ __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */
+ __IM uint32_t RESERVED2[6];
+ __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word
+ n */
+ __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity root, word n */
+ __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */
+ __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */
+ __IM uint32_t RESERVED3[21];
+ __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */
+ __IM uint32_t RESERVED4[188];
+ __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization
+ coefficients */
+} NRF_FICR_Type; /*!< Size = 1096 (0x448) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UICR ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief User information configuration registers (UICR)
+ */
+
+typedef struct { /*!< (@ 0x10001000) UICR Structure */
+ __IM uint32_t RESERVED[5];
+ __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware
+ design */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware
+ design */
+ __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET
+ function (see POWER chapter for details) */
+ __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */
+} NRF_UICR_Type; /*!< Size = 524 (0x20c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ BPROT ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Block Protect (BPROT)
+ */
+
+typedef struct { /*!< (@ 0x40000000) BPROT Structure */
+ __IM uint32_t RESERVED[384];
+ __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */
+ __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */
+ __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */
+} NRF_BPROT_Type; /*!< Size = 1548 (0x60c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CLOCK ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Clock control (CLOCK)
+ */
+
+typedef struct { /*!< (@ 0x40000000) CLOCK Structure */
+ __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */
+ __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */
+ __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */
+ __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */
+ __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */
+ __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */
+ __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */
+ __IM uint32_t RESERVED[57];
+ __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */
+ __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */
+ __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */
+ __IM uint32_t RESERVED2[124];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[63];
+ __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been
+ triggered */
+ __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */
+ __IM uint32_t RESERVED4;
+ __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been
+ triggered */
+ __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */
+ __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART
+ task was triggered */
+ __IM uint32_t RESERVED5[62];
+ __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */
+ __IM uint32_t RESERVED6[7];
+ __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */
+} NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ POWER ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Power control (POWER)
+ */
+
+typedef struct { /*!< (@ 0x40000000) POWER Structure */
+ __IM uint32_t RESERVED[30];
+ __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */
+ __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */
+ __IM uint32_t RESERVED1[34];
+ __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */
+ __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */
+ __IM uint32_t RESERVED3[122];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[61];
+ __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */
+ __IM uint32_t RESERVED5[63];
+ __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */
+ __IM uint32_t RESERVED6[3];
+ __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */
+ __IM uint32_t RESERVED7[2];
+ __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */
+ __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */
+ __IM uint32_t RESERVED8[21];
+ __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */
+ __IM uint32_t RESERVED9[225];
+ __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */
+} NRF_POWER_Type; /*!< Size = 2432 (0x980) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ P0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIO Port (P0)
+ */
+
+typedef struct { /*!< (@ 0x50000000) P0 Structure */
+ __IM uint32_t RESERVED[321];
+ __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */
+ __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */
+ __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */
+ __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */
+ __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */
+ __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */
+ __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */
+ __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that
+ have met the criteria set in the PIN_CNF[n].SENSE
+ registers */
+ __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour
+ and LDETECT mode */
+ __IM uint32_t RESERVED1[118];
+ __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO
+ pins */
+} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RADIO ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief 2.4 GHz radio (RADIO)
+ */
+
+typedef struct { /*!< (@ 0x40001000) RADIO Structure */
+ __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */
+ __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */
+ __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */
+ __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of
+ the receive signal strength */
+ __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */
+ __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */
+ __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */
+ __IM uint32_t RESERVED[55];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */
+ __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */
+ __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */
+ __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */
+ __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received
+ packet */
+ __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last
+ received packet */
+ __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */
+ __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */
+ __IM uint32_t RESERVED3[7];
+ __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started
+ TX path */
+ __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started
+ RX path */
+ __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */
+ __IM uint32_t RESERVED4[3];
+ __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air */
+ __IM uint32_t RESERVED5[36];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED6[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED7[61];
+ __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */
+ __IM uint32_t RESERVED8;
+ __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */
+ __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */
+ __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */
+ __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */
+ __IM uint32_t RESERVED9[59];
+ __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */
+ __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */
+ __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */
+ __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */
+ __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */
+ __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */
+ __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */
+ __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */
+ __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */
+ __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */
+ __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */
+ __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */
+ __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */
+ __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */
+ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */
+ __IM uint32_t RESERVED11;
+ __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */
+ __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */
+ __IM uint32_t RESERVED12[2];
+ __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */
+ __IM uint32_t RESERVED13[39];
+ __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment
+ n */
+ __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix
+ n */
+ __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */
+ __IM uint32_t RESERVED14[3];
+ __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */
+ __IM uint32_t RESERVED15[618];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */
+} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Universal Asynchronous Receiver/Transmitter (UART0)
+ */
+
+typedef struct { /*!< (@ 0x40002000) UART0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */
+ __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */
+ __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */
+ __IM uint32_t RESERVED[3];
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */
+ __IM uint32_t RESERVED1[56];
+ __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */
+ __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */
+ __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */
+ __IM uint32_t RESERVED2[4];
+ __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */
+ __IM uint32_t RESERVED5[46];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED6[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED7[93];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */
+ __IM uint32_t RESERVED8[31];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
+ __IM uint32_t RESERVED9;
+ __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
+ selected. */
+ __IM uint32_t RESERVED11[17];
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */
+} NRF_UART_Type; /*!< Size = 1392 (0x570) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UARTE0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART with EasyDMA (UARTE0)
+ */
+
+typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */
+ __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */
+ __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */
+ __IM uint32_t RESERVED[7];
+ __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */
+ __IM uint32_t RESERVED1[52];
+ __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */
+ __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */
+ __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet
+ transferred to Data RAM) */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */
+ __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */
+ __IM uint32_t RESERVED7[41];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED8[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[93];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write
+ one to clear. */
+ __IM uint32_t RESERVED10[31];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
+ __IM uint32_t RESERVED11;
+ __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[3];
+ __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
+ selected. */
+ __IM uint32_t RESERVED13[3];
+ __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IM uint32_t RESERVED14;
+ __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED15[7];
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */
+} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Interface (TWI0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) TWI0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */
+ __IM uint32_t RESERVED2;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */
+ __IM uint32_t RESERVED4[4];
+ __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte
+ that is sent or received */
+ __IM uint32_t RESERVED7[3];
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */
+ __IM uint32_t RESERVED8[45];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED9[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED10[110];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */
+ __IM uint32_t RESERVED11[14];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */
+ __IM uint32_t RESERVED12;
+ __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED13[2];
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED15[24];
+ __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */
+} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWIM0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the
+ TWI master is not suspended. */
+ __IM uint32_t RESERVED2;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED5[8];
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND
+ task has been issued, TWI traffic is now
+ suspended. */
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */
+ __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last
+ byte */
+ __IM uint32_t RESERVED7[39];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED8[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[110];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */
+ __IM uint32_t RESERVED10[14];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */
+ __IM uint32_t RESERVED11;
+ __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[5];
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED13[3];
+ __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED14[13];
+ __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */
+} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWIS0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */
+ __IM uint32_t RESERVED[5];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */
+ __IM uint32_t RESERVED1;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED2[3];
+ __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */
+ __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */
+ __IM uint32_t RESERVED3[51];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED5[9];
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */
+ __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */
+ __IM uint32_t RESERVED7[37];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED8[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[113];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */
+ __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had
+ a match */
+ __IM uint32_t RESERVED10[10];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */
+ __IM uint32_t RESERVED11;
+ __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[9];
+ __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED13[13];
+ __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match
+ mechanism */
+ __IM uint32_t RESERVED15[10];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case
+ of an over-read of the transmit buffer. */
+} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Serial Peripheral Interface (SPI0)
+ */
+
+typedef struct { /*!< (@ 0x40004000) SPI0 Structure */
+ __IM uint32_t RESERVED[66];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */
+ __IM uint32_t RESERVED1[126];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */
+ __IM uint32_t RESERVED3;
+ __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED4;
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED6[11];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+} NRF_SPI_Type; /*!< Size = 1368 (0x558) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPIM0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Serial Peripheral Interface Master with EasyDMA (SPIM0)
+ */
+
+typedef struct { /*!< (@ 0x40004000) SPIM0 Structure */
+ __IM uint32_t RESERVED[4];
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */
+ __IM uint32_t RESERVED1;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */
+ __IM uint32_t RESERVED2[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */
+ __IM uint32_t RESERVED6[10];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */
+ __IM uint32_t RESERVED7[44];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED8[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */
+ __IM uint32_t RESERVED10;
+ __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED11[4];
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED12[3];
+ __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+ __IM uint32_t RESERVED13[26];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in
+ case and over-read of the TXD buffer. */
+} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPIS0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI Slave (SPIS0)
+ */
+
+typedef struct { /*!< (@ 0x40004000) SPIS0 Structure */
+ __IM uint32_t RESERVED[9];
+ __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */
+ __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave
+ to acquire it */
+ __IM uint32_t RESERVED1[54];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */
+ __IM uint32_t RESERVED3[5];
+ __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */
+ __IM uint32_t RESERVED4[53];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED5[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED6[61];
+ __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */
+ __IM uint32_t RESERVED7[15];
+ __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */
+ __IM uint32_t RESERVED8[47];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */
+ __IM uint32_t RESERVED9;
+ __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED10[7];
+ __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */
+ __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case
+ of an ignored transaction. */
+ __IM uint32_t RESERVED12[24];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */
+} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOTE ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIO Tasks and Events (GPIOTE)
+ */
+
+typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */
+ __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is configured in CONFIG[n].POLARITY. */
+ __IM uint32_t RESERVED[4];
+ __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is to set it high. */
+ __IM uint32_t RESERVED1[4];
+ __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is to set it low. */
+ __IM uint32_t RESERVED2[32];
+ __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from
+ pin specified in CONFIG[n].PSEL */
+ __IM uint32_t RESERVED3[23];
+ __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins
+ with SENSE mechanism enabled */
+ __IM uint32_t RESERVED4[97];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED5[129];
+ __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n],
+ SET[n] and CLR[n] tasks and IN[n] event */
+} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SAADC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Analog to Digital Converter (SAADC)
+ */
+
+typedef struct { /*!< (@ 0x40007000) SAADC Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in
+ RAM */
+ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels
+ are sampled */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */
+ __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */
+ __IM uint32_t RESERVED[60];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */
+ __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending
+ on the mode, multiple conversions might
+ be needed for a result to be transferred
+ to RAM. */
+ __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */
+ __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */
+ __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */
+ __IM uint32_t RESERVED1[106];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[61];
+ __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */
+ __IM uint32_t RESERVED4[3];
+ __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */
+ __IM uint32_t RESERVED5[24];
+ __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */
+ __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should
+ not be combined with SCAN. The RESOLUTION
+ is applied before averaging, thus for high
+ OVERSAMPLE a higher RESOLUTION should be
+ used. */
+ __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */
+ __IM uint32_t RESERVED6[12];
+ __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */
+} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Timer/Counter 0 (TIMER0)
+ */
+
+typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */
+ __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */
+ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */
+ __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */
+ __IM uint32_t RESERVED[11];
+ __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to
+ CC[n] register */
+ __IM uint32_t RESERVED1[58];
+ __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
+ match */
+ __IM uint32_t RESERVED2[42];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED3[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[126];
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */
+ __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */
+ __IM uint32_t RESERVED6[11];
+ __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register
+ n */
+} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RTC0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Real time counter 0 (RTC0)
+ */
+
+typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */
+ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */
+ __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */
+ __IM uint32_t RESERVED[60];
+ __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */
+ __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */
+ __IM uint32_t RESERVED1[14];
+ __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
+ match */
+ __IM uint32_t RESERVED2[109];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[13];
+ __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */
+ __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */
+ __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */
+ __IM uint32_t RESERVED4[110];
+ __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */
+ __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu
+ t be written when RTC is stopped */
+ __IM uint32_t RESERVED5[13];
+ __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */
+} NRF_RTC_Type; /*!< Size = 1360 (0x550) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TEMP ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Temperature Sensor (TEMP)
+ */
+
+typedef struct { /*!< (@ 0x4000C000) TEMP Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */
+ __IM uint32_t RESERVED1[128];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[127];
+ __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */
+ __IM uint32_t RESERVED3[5];
+ __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */
+ __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */
+ __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */
+ __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */
+ __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */
+ __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */
+ __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */
+ __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */
+ __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */
+ __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */
+ __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */
+ __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */
+ __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */
+ __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */
+ __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */
+} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RNG ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Random Number Generator (RNG)
+ */
+
+typedef struct { /*!< (@ 0x4000D000) RNG Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number
+ written to the VALUE register */
+ __IM uint32_t RESERVED1[63];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[126];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */
+ __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */
+} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ECB ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief AES ECB Mode Encryption (ECB)
+ */
+
+typedef struct { /*!< (@ 0x4000E000) ECB Structure */
+ __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */
+ __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */
+ __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB
+ task or due to an error */
+ __IM uint32_t RESERVED1[127];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[126];
+ __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */
+} NRF_ECB_Type; /*!< Size = 1288 (0x508) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ AAR ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Accelerated Address Resolver (AAR)
+ */
+
+typedef struct { /*!< (@ 0x4000F000) AAR Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified
+ in the IRK data structure */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */
+ __IM uint32_t RESERVED1[61];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */
+ __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */
+ __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */
+ __IM uint32_t RESERVED2[126];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */
+ __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */
+ __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */
+ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
+} NRF_AAR_Type; /*!< Size = 1304 (0x518) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CCM ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief AES CCM Mode Encryption (CCM)
+ */
+
+typedef struct { /*!< (@ 0x4000F000) CCM Structure */
+ __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation
+ will stop by itself when completed. */
+ __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will
+ stop by itself when completed. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */
+ __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with
+ the contents of the RATEOVERRIDE register
+ for any ongoing encryption/decryption */
+ __IM uint32_t RESERVED[60];
+ __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */
+ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */
+ __IM uint32_t RESERVED1[61];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */
+ __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and
+ NONCE vector */
+ __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */
+ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */
+ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
+ __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH
+ = Extended. */
+ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */
+} NRF_CCM_Type; /*!< Size = 1312 (0x520) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ WDT ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Watchdog Timer (WDT)
+ */
+
+typedef struct { /*!< (@ 0x40010000) WDT Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */
+ __IM uint32_t RESERVED[63];
+ __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */
+ __IM uint32_t RESERVED1[128];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[61];
+ __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */
+ __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */
+ __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */
+ __IM uint32_t RESERVED4[60];
+ __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */
+} NRF_WDT_Type; /*!< Size = 1568 (0x620) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ EGU0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Event Generator Unit 0 (EGU0)
+ */
+
+typedef struct { /*!< (@ 0x40014000) EGU0 Structure */
+ __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering
+ the corresponding TRIGGERED[n] event */
+ __IM uint32_t RESERVED[48];
+ __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated
+ by triggering the corresponding TRIGGER[n]
+ task */
+ __IM uint32_t RESERVED1[112];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+} NRF_EGU_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SWI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Software interrupt 0 (SWI0)
+ */
+
+typedef struct { /*!< (@ 0x40014000) SWI0 Structure */
+ __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */
+} NRF_SWI_Type; /*!< Size = 4 (0x4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ NVMC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Non-volatile memory controller (NVMC)
+ */
+
+typedef struct { /*!< (@ 0x4001E000) NVMC Structure */
+ __IM uint32_t RESERVED[256];
+ __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */
+ __IM uint32_t RESERVED1[64];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */
+
+ union {
+ __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */
+ __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a
+ page in code area. Equivalent to ERASEPAGE. */
+ };
+ __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */
+ __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a
+ page in code area. Equivalent to ERASEPAGE. */
+ __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration
+ registers */
+ __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code
+ area */
+ __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */
+} NRF_NVMC_Type; /*!< Size = 1312 (0x520) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PPI ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Programmable Peripheral Interconnect (PPI)
+ */
+
+typedef struct { /*!< (@ 0x4001F000) PPI Structure */
+ __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */
+ __IM uint32_t RESERVED[308];
+ __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */
+ __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */
+ __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */
+ __IM uint32_t RESERVED1;
+ __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */
+ __IM uint32_t RESERVED2[148];
+ __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */
+ __IM uint32_t RESERVED3[62];
+ __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */
+} NRF_PPI_Type; /*!< Size = 2448 (0x990) */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+#define NRF_FICR_BASE 0x10000000UL
+#define NRF_UICR_BASE 0x10001000UL
+#define NRF_BPROT_BASE 0x40000000UL
+#define NRF_CLOCK_BASE 0x40000000UL
+#define NRF_POWER_BASE 0x40000000UL
+#define NRF_P0_BASE 0x50000000UL
+#define NRF_RADIO_BASE 0x40001000UL
+#define NRF_UART0_BASE 0x40002000UL
+#define NRF_UARTE0_BASE 0x40002000UL
+#define NRF_TWI0_BASE 0x40003000UL
+#define NRF_TWIM0_BASE 0x40003000UL
+#define NRF_TWIS0_BASE 0x40003000UL
+#define NRF_SPI0_BASE 0x40004000UL
+#define NRF_SPIM0_BASE 0x40004000UL
+#define NRF_SPIS0_BASE 0x40004000UL
+#define NRF_GPIOTE_BASE 0x40006000UL
+#define NRF_SAADC_BASE 0x40007000UL
+#define NRF_TIMER0_BASE 0x40008000UL
+#define NRF_TIMER1_BASE 0x40009000UL
+#define NRF_TIMER2_BASE 0x4000A000UL
+#define NRF_RTC0_BASE 0x4000B000UL
+#define NRF_TEMP_BASE 0x4000C000UL
+#define NRF_RNG_BASE 0x4000D000UL
+#define NRF_ECB_BASE 0x4000E000UL
+#define NRF_AAR_BASE 0x4000F000UL
+#define NRF_CCM_BASE 0x4000F000UL
+#define NRF_WDT_BASE 0x40010000UL
+#define NRF_RTC1_BASE 0x40011000UL
+#define NRF_EGU0_BASE 0x40014000UL
+#define NRF_SWI0_BASE 0x40014000UL
+#define NRF_EGU1_BASE 0x40015000UL
+#define NRF_SWI1_BASE 0x40015000UL
+#define NRF_SWI2_BASE 0x40016000UL
+#define NRF_SWI3_BASE 0x40017000UL
+#define NRF_SWI4_BASE 0x40018000UL
+#define NRF_SWI5_BASE 0x40019000UL
+#define NRF_NVMC_BASE 0x4001E000UL
+#define NRF_PPI_BASE 0x4001F000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE)
+#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE)
+#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE)
+#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE)
+#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE)
+#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE)
+#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE)
+#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE)
+#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE)
+#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE)
+#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE)
+#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE)
+#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE)
+#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE)
+#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE)
+#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE)
+#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE)
+#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE)
+#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE)
+#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE)
+#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE)
+#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE)
+#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE)
+#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE)
+#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE)
+#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE)
+#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE)
+#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE)
+#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE)
+#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE)
+#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE)
+#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE)
+#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE)
+#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE)
+#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE)
+#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE)
+#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE)
+#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+
+/* ========================================= End of section using anonymous unions ========================================= */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF52805_H */
+
+
+/** @} */ /* End of group nrf52805 */
+
+/** @} */ /* End of group Nordic Semiconductor */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52805.svd b/third_party/NordicSemiconductor/nrfx/mdk/nrf52805.svd
new file mode 100644
index 000000000..6a631c1cb
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52805.svd
@@ -0,0 +1,32763 @@
+
+
+
+ Nordic Semiconductor
+ Nordic
+ nrf52805
+ nrf52
+ 1
+ nRF52805 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller
+
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.\n
+\n
+Redistribution and use in source and binary forms, with or without\n
+modification, are permitted provided that the following conditions are met:\n
+\n
+1. Redistributions of source code must retain the above copyright notice, this\n
+ list of conditions and the following disclaimer.\n
+\n
+2. Redistributions in binary form must reproduce the above copyright\n
+ notice, this list of conditions and the following disclaimer in the\n
+ documentation and/or other materials provided with the distribution.\n
+\n
+3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
+ contributors may be used to endorse or promote products derived from this\n
+ software without specific prior written permission.\n
+\n
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
+POSSIBILITY OF SUCH DAMAGE.\n
+
+ 8
+ 32
+ 32
+ 0x00000000
+ 0xFFFFFFFF
+
+ CM4
+ r0p1
+ little
+ 1
+ 0
+ 3
+ 0
+
+ system_nrf52805
+ NRF_
+
+ 2048
+ 2048
+ 112
+
+
+
+ FICR
+ Factory information configuration registers
+ 0x10000000
+
+ 0
+ 0x1000
+ registers
+
+ FICR
+ 0x20
+
+
+ CODEPAGESIZE
+ Code memory page size
+ 0x010
+ read-only
+ 0x00001000
+
+
+ CODEPAGESIZE
+ Code memory page size
+ 0
+ 31
+
+
+
+
+ CODESIZE
+ Code memory size
+ 0x014
+ read-only
+ 0x00000030
+
+
+ CODESIZE
+ Code memory size in number of pages
+ 0
+ 31
+
+
+
+
+ 0x2
+ 0x4
+ DEVICEID[%s]
+ Description collection: Device identifier
+ 0x060
+ read-only
+ 0xFFFFFFFF
+
+
+ DEVICEID
+ 64 bit unique device identifier
+ 0
+ 31
+
+
+
+
+ 0x4
+ 0x4
+ ER[%s]
+ Description collection: Encryption root, word n
+ 0x080
+ read-only
+ 0xFFFFFFFF
+
+
+ ER
+ Encryption root, word n
+ 0
+ 31
+
+
+
+
+ 0x4
+ 0x4
+ IR[%s]
+ Description collection: Identity root, word n
+ 0x090
+ read-only
+ 0xFFFFFFFF
+
+
+ IR
+ Identity root, word n
+ 0
+ 31
+
+
+
+
+ DEVICEADDRTYPE
+ Device address type
+ 0x0A0
+ read-only
+ 0xFFFFFFFF
+
+
+ DEVICEADDRTYPE
+ Device address type
+ 0
+ 0
+
+
+ Public
+ Public address
+ 0
+
+
+ Random
+ Random address
+ 1
+
+
+
+
+
+
+ 0x2
+ 0x4
+ DEVICEADDR[%s]
+ Description collection: Device address n
+ 0x0A4
+ read-only
+ 0xFFFFFFFF
+
+
+ DEVICEADDR
+ 48 bit device address
+ 0
+ 31
+
+
+
+
+ INFO
+ Device info
+ FICR_INFO
+ read-only
+ 0x100
+
+ PART
+ Part code
+ 0x000
+ read-only
+ 0x00052805
+
+
+ PART
+ Part code
+ 0
+ 31
+
+
+ N52805
+ nRF52805
+ 0x52805
+
+
+ N52810
+ nRF52810
+ 0x52810
+
+
+ N52811
+ nRF52811
+ 0x52811
+
+
+ N52832
+ nRF52832
+ 0x52832
+
+
+ Unspecified
+ Unspecified
+ 0xFFFFFFFF
+
+
+
+
+
+
+ VARIANT
+ Part variant, hardware version and production configuration
+ 0x004
+ read-only
+ 0xFFFFFFFF
+
+
+ VARIANT
+ Part variant, hardware version and production configuration, encoded as ASCII
+ 0
+ 31
+
+
+ AAAA
+ AAAA
+ 0x41414141
+
+
+ AAA0
+ AAA0
+ 0x41414130
+
+
+ AABA
+ AABA
+ 0x41414241
+
+
+ AABB
+ AABB
+ 0x41414242
+
+
+ AAB0
+ AAB0
+ 0x41414230
+
+
+ AACA
+ AACA
+ 0x41414341
+
+
+ AACB
+ AACB
+ 0x41414342
+
+
+ AAC0
+ AAC0
+ 0x41414330
+
+
+ Unspecified
+ Unspecified
+ 0xFFFFFFFF
+
+
+
+
+
+
+ PACKAGE
+ Package option
+ 0x008
+ read-only
+ 0xFFFFFFFF
+
+
+ PACKAGE
+ Package option
+ 0
+ 31
+
+
+ CA
+ CAxx - WLCSP
+ 0x2004
+
+
+ Unspecified
+ Unspecified
+ 0xFFFFFFFF
+
+
+
+
+
+
+ RAM
+ RAM variant
+ 0x00C
+ read-only
+ 0x00000018
+
+
+ RAM
+ RAM variant
+ 0
+ 31
+
+
+ K24
+ 24 kByte RAM
+ 0x18
+
+
+ Unspecified
+ Unspecified
+ 0xFFFFFFFF
+
+
+
+
+
+
+ FLASH
+ Flash variant
+ 0x010
+ read-only
+ 0x000000C0
+
+
+ FLASH
+ Flash variant
+ 0
+ 31
+
+
+ K192
+ 192 kByte flash
+ 0xC0
+
+
+ Unspecified
+ Unspecified
+ 0xFFFFFFFF
+
+
+
+
+
+
+
+ TEMP
+ Registers storing factory TEMP module linearization coefficients
+ FICR_TEMP
+ read-only
+ 0x404
+
+ A0
+ Slope definition A0
+ 0x000
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register
+ 0
+ 11
+
+
+
+
+ A1
+ Slope definition A1
+ 0x004
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register
+ 0
+ 11
+
+
+
+
+ A2
+ Slope definition A2
+ 0x008
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register
+ 0
+ 11
+
+
+
+
+ A3
+ Slope definition A3
+ 0x00C
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register
+ 0
+ 11
+
+
+
+
+ A4
+ Slope definition A4
+ 0x010
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register
+ 0
+ 11
+
+
+
+
+ A5
+ Slope definition A5
+ 0x014
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register
+ 0
+ 11
+
+
+
+
+ B0
+ Y-intercept B0
+ 0x018
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ B1
+ Y-intercept B1
+ 0x01C
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ B2
+ Y-intercept B2
+ 0x020
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ B3
+ Y-intercept B3
+ 0x024
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ B4
+ Y-intercept B4
+ 0x028
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ B5
+ Y-intercept B5
+ 0x02C
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ T0
+ Segment end T0
+ 0x030
+ read-only
+ 0xFFFFFFFF
+
+
+ T
+ T (segment end) register
+ 0
+ 7
+
+
+
+
+ T1
+ Segment end T1
+ 0x034
+ read-only
+ 0xFFFFFFFF
+
+
+ T
+ T (segment end) register
+ 0
+ 7
+
+
+
+
+ T2
+ Segment end T2
+ 0x038
+ read-only
+ 0xFFFFFFFF
+
+
+ T
+ T (segment end) register
+ 0
+ 7
+
+
+
+
+ T3
+ Segment end T3
+ 0x03C
+ read-only
+ 0xFFFFFFFF
+
+
+ T
+ T (segment end) register
+ 0
+ 7
+
+
+
+
+ T4
+ Segment end T4
+ 0x040
+ read-only
+ 0xFFFFFFFF
+
+
+ T
+ T (segment end) register
+ 0
+ 7
+
+
+
+
+
+
+
+ UICR
+ User information configuration registers
+ 0x10001000
+
+ 0
+ 0x1000
+ registers
+
+ UICR
+ 0x20
+
+
+ 0xD
+ 0x4
+ NRFFW[%s]
+ Description collection: Reserved for Nordic firmware design
+ 0x014
+ read-write
+ 0xFFFFFFFF
+
+
+ NRFFW
+ Reserved for Nordic firmware design
+ 0
+ 31
+
+
+
+
+ 0xC
+ 0x4
+ NRFHW[%s]
+ Description collection: Reserved for Nordic hardware design
+ 0x050
+ read-write
+ 0xFFFFFFFF
+
+
+ NRFHW
+ Reserved for Nordic hardware design
+ 0
+ 31
+
+
+
+
+ 0x20
+ 0x4
+ CUSTOMER[%s]
+ Description collection: Reserved for customer
+ 0x080
+ read-write
+ 0xFFFFFFFF
+
+
+ CUSTOMER
+ Reserved for customer
+ 0
+ 31
+
+
+
+
+ 0x2
+ 0x4
+ PSELRESET[%s]
+ Description collection: Mapping of the nRESET function (see POWER chapter for details)
+ 0x200
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ GPIO pin number onto which nRESET is exposed
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ APPROTECT
+ Access port protection
+ 0x208
+ read-write
+ 0xFFFFFFFF
+
+
+ PALL
+ Enable or disable access port protection.
+ 0
+ 7
+
+
+ Disabled
+ Disable
+ 0xFF
+
+
+ Enabled
+ Enable
+ 0x00
+
+
+
+
+
+
+
+
+ BPROT
+ Block Protect
+ 0x40000000
+
+ 0
+ 0x1000
+ registers
+
+ BPROT
+ 0x20
+
+
+ CONFIG0
+ Block protect configuration register 0
+ 0x600
+ read-write
+
+
+ REGION0
+ Enable protection for region 0. Write '0' has no effect.
+ 0
+ 0
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION1
+ Enable protection for region 1. Write '0' has no effect.
+ 1
+ 1
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION2
+ Enable protection for region 2. Write '0' has no effect.
+ 2
+ 2
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION3
+ Enable protection for region 3. Write '0' has no effect.
+ 3
+ 3
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION4
+ Enable protection for region 4. Write '0' has no effect.
+ 4
+ 4
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION5
+ Enable protection for region 5. Write '0' has no effect.
+ 5
+ 5
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION6
+ Enable protection for region 6. Write '0' has no effect.
+ 6
+ 6
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION7
+ Enable protection for region 7. Write '0' has no effect.
+ 7
+ 7
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION8
+ Enable protection for region 8. Write '0' has no effect.
+ 8
+ 8
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION9
+ Enable protection for region 9. Write '0' has no effect.
+ 9
+ 9
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION10
+ Enable protection for region 10. Write '0' has no effect.
+ 10
+ 10
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION11
+ Enable protection for region 11. Write '0' has no effect.
+ 11
+ 11
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION12
+ Enable protection for region 12. Write '0' has no effect.
+ 12
+ 12
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION13
+ Enable protection for region 13. Write '0' has no effect.
+ 13
+ 13
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION14
+ Enable protection for region 14. Write '0' has no effect.
+ 14
+ 14
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION15
+ Enable protection for region 15. Write '0' has no effect.
+ 15
+ 15
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION16
+ Enable protection for region 16. Write '0' has no effect.
+ 16
+ 16
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION17
+ Enable protection for region 17. Write '0' has no effect.
+ 17
+ 17
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION18
+ Enable protection for region 18. Write '0' has no effect.
+ 18
+ 18
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION19
+ Enable protection for region 19. Write '0' has no effect.
+ 19
+ 19
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION20
+ Enable protection for region 20. Write '0' has no effect.
+ 20
+ 20
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION21
+ Enable protection for region 21. Write '0' has no effect.
+ 21
+ 21
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION22
+ Enable protection for region 22. Write '0' has no effect.
+ 22
+ 22
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION23
+ Enable protection for region 23. Write '0' has no effect.
+ 23
+ 23
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION24
+ Enable protection for region 24. Write '0' has no effect.
+ 24
+ 24
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION25
+ Enable protection for region 25. Write '0' has no effect.
+ 25
+ 25
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION26
+ Enable protection for region 26. Write '0' has no effect.
+ 26
+ 26
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION27
+ Enable protection for region 27. Write '0' has no effect.
+ 27
+ 27
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION28
+ Enable protection for region 28. Write '0' has no effect.
+ 28
+ 28
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION29
+ Enable protection for region 29. Write '0' has no effect.
+ 29
+ 29
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION30
+ Enable protection for region 30. Write '0' has no effect.
+ 30
+ 30
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION31
+ Enable protection for region 31. Write '0' has no effect.
+ 31
+ 31
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+
+
+ CONFIG1
+ Block protect configuration register 1
+ 0x604
+ read-write
+
+
+ REGION32
+ Enable protection for region 32. Write '0' has no effect.
+ 0
+ 0
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION33
+ Enable protection for region 33. Write '0' has no effect.
+ 1
+ 1
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION34
+ Enable protection for region 34. Write '0' has no effect.
+ 2
+ 2
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION35
+ Enable protection for region 35. Write '0' has no effect.
+ 3
+ 3
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION36
+ Enable protection for region 36. Write '0' has no effect.
+ 4
+ 4
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION37
+ Enable protection for region 37. Write '0' has no effect.
+ 5
+ 5
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION38
+ Enable protection for region 38. Write '0' has no effect.
+ 6
+ 6
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION39
+ Enable protection for region 39. Write '0' has no effect.
+ 7
+ 7
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION40
+ Enable protection for region 40. Write '0' has no effect.
+ 8
+ 8
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION41
+ Enable protection for region 41. Write '0' has no effect.
+ 9
+ 9
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION42
+ Enable protection for region 42. Write '0' has no effect.
+ 10
+ 10
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION43
+ Enable protection for region 43. Write '0' has no effect.
+ 11
+ 11
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION44
+ Enable protection for region 44. Write '0' has no effect.
+ 12
+ 12
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION45
+ Enable protection for region 45. Write '0' has no effect.
+ 13
+ 13
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION46
+ Enable protection for region 46. Write '0' has no effect.
+ 14
+ 14
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+ REGION47
+ Enable protection for region 47. Write '0' has no effect.
+ 15
+ 15
+
+
+ Disabled
+ Protection disabled
+ 0
+
+
+ Enabled
+ Protection enabled
+ 1
+
+
+
+
+
+
+ DISABLEINDEBUG
+ Disable protection mechanism in debug mode
+ 0x608
+ read-write
+ 0x00000001
+
+
+ DISABLEINDEBUG
+ Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode.
+ 0
+ 0
+
+
+ Disabled
+ Disabled in debug
+ 1
+
+
+ Enabled
+ Enabled in debug
+ 0
+
+
+
+
+
+
+
+
+ CLOCK
+ Clock control
+ 0x40000000
+ BPROT
+
+ 0
+ 0x1000
+ registers
+
+
+ POWER_CLOCK
+ 0
+
+ CLOCK
+ 0x20
+
+
+ TASKS_HFCLKSTART
+ Start HFCLK crystal oscillator
+ 0x000
+ write-only
+
+
+ TASKS_HFCLKSTART
+ Start HFCLK crystal oscillator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_HFCLKSTOP
+ Stop HFCLK crystal oscillator
+ 0x004
+ write-only
+
+
+ TASKS_HFCLKSTOP
+ Stop HFCLK crystal oscillator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_LFCLKSTART
+ Start LFCLK source
+ 0x008
+ write-only
+
+
+ TASKS_LFCLKSTART
+ Start LFCLK source
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_LFCLKSTOP
+ Stop LFCLK source
+ 0x00C
+ write-only
+
+
+ TASKS_LFCLKSTOP
+ Stop LFCLK source
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CAL
+ Start calibration of LFRC oscillator
+ 0x010
+ write-only
+
+
+ TASKS_CAL
+ Start calibration of LFRC oscillator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CTSTART
+ Start calibration timer
+ 0x014
+ write-only
+
+
+ TASKS_CTSTART
+ Start calibration timer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CTSTOP
+ Stop calibration timer
+ 0x018
+ write-only
+
+
+ TASKS_CTSTOP
+ Stop calibration timer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_HFCLKSTARTED
+ HFCLK oscillator started
+ 0x100
+ read-write
+
+
+ EVENTS_HFCLKSTARTED
+ HFCLK oscillator started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_LFCLKSTARTED
+ LFCLK started
+ 0x104
+ read-write
+
+
+ EVENTS_LFCLKSTARTED
+ LFCLK started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DONE
+ Calibration of LFCLK RC oscillator complete event
+ 0x10C
+ read-write
+
+
+ EVENTS_DONE
+ Calibration of LFCLK RC oscillator complete event
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CTTO
+ Calibration timer timeout
+ 0x110
+ read-write
+
+
+ EVENTS_CTTO
+ Calibration timer timeout
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ HFCLKSTARTED
+ Write '1' to enable interrupt for event HFCLKSTARTED
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ LFCLKSTARTED
+ Write '1' to enable interrupt for event LFCLKSTARTED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DONE
+ Write '1' to enable interrupt for event DONE
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CTTO
+ Write '1' to enable interrupt for event CTTO
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ HFCLKSTARTED
+ Write '1' to disable interrupt for event HFCLKSTARTED
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ LFCLKSTARTED
+ Write '1' to disable interrupt for event LFCLKSTARTED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DONE
+ Write '1' to disable interrupt for event DONE
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CTTO
+ Write '1' to disable interrupt for event CTTO
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ HFCLKRUN
+ Status indicating that HFCLKSTART task has been triggered
+ 0x408
+ read-only
+
+
+ STATUS
+ HFCLKSTART task triggered or not
+ 0
+ 0
+
+
+ NotTriggered
+ Task not triggered
+ 0
+
+
+ Triggered
+ Task triggered
+ 1
+
+
+
+
+
+
+ HFCLKSTAT
+ HFCLK status
+ 0x40C
+ read-only
+
+
+ SRC
+ Source of HFCLK
+ 0
+ 0
+
+
+ RC
+ 64 MHz internal oscillator (HFINT)
+ 0
+
+
+ Xtal
+ 64 MHz crystal oscillator (HFXO)
+ 1
+
+
+
+
+ STATE
+ HFCLK state
+ 16
+ 16
+
+
+ NotRunning
+ HFCLK not running
+ 0
+
+
+ Running
+ HFCLK running
+ 1
+
+
+
+
+
+
+ LFCLKRUN
+ Status indicating that LFCLKSTART task has been triggered
+ 0x414
+ read-only
+
+
+ STATUS
+ LFCLKSTART task triggered or not
+ 0
+ 0
+
+
+ NotTriggered
+ Task not triggered
+ 0
+
+
+ Triggered
+ Task triggered
+ 1
+
+
+
+
+
+
+ LFCLKSTAT
+ LFCLK status
+ 0x418
+ read-only
+
+
+ SRC
+ Source of LFCLK
+ 0
+ 1
+
+
+ RC
+ 32.768 kHz RC oscillator
+ 0
+
+
+ Xtal
+ 32.768 kHz crystal oscillator
+ 1
+
+
+ Synth
+ 32.768 kHz synthesized from HFCLK
+ 2
+
+
+
+
+ STATE
+ LFCLK state
+ 16
+ 16
+
+
+ NotRunning
+ LFCLK not running
+ 0
+
+
+ Running
+ LFCLK running
+ 1
+
+
+
+
+
+
+ LFCLKSRCCOPY
+ Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
+ 0x41C
+ read-only
+
+
+ SRC
+ Clock source
+ 0
+ 1
+
+
+ RC
+ 32.768 kHz RC oscillator
+ 0
+
+
+ Xtal
+ 32.768 kHz crystal oscillator
+ 1
+
+
+ Synth
+ 32.768 kHz synthesized from HFCLK
+ 2
+
+
+
+
+
+
+ LFCLKSRC
+ Clock source for the LFCLK
+ 0x518
+ read-write
+
+
+ SRC
+ Clock source
+ 0
+ 1
+
+
+ RC
+ 32.768 kHz RC oscillator
+ 0
+
+
+ Xtal
+ 32.768 kHz crystal oscillator
+ 1
+
+
+ Synth
+ 32.768 kHz synthesized from HFCLK
+ 2
+
+
+
+
+ BYPASS
+ Enable or disable bypass of LFCLK crystal oscillator with external clock source
+ 16
+ 16
+
+
+ Disabled
+ Disable (use with Xtal or low-swing external source)
+ 0
+
+
+ Enabled
+ Enable (use with rail-to-rail external source)
+ 1
+
+
+
+
+ EXTERNAL
+ Enable or disable external source for LFCLK
+ 17
+ 17
+
+
+ Disabled
+ Disable external source (use with Xtal)
+ 0
+
+
+ Enabled
+ Enable use of external source instead of Xtal (SRC needs to be set to Xtal)
+ 1
+
+
+
+
+
+
+ CTIV
+ Calibration timer interval
+ 0x538
+ read-write
+
+
+ CTIV
+ Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.
+ 0
+ 6
+
+
+
+
+
+
+ POWER
+ Power control
+ 0x40000000
+ BPROT
+
+ 0
+ 0x1000
+ registers
+
+
+ POWER_CLOCK
+ 0
+
+ POWER
+ 0x20
+
+
+ TASKS_CONSTLAT
+ Enable Constant Latency mode
+ 0x078
+ write-only
+
+
+ TASKS_CONSTLAT
+ Enable Constant Latency mode
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_LOWPWR
+ Enable Low-power mode (variable latency)
+ 0x07C
+ write-only
+
+
+ TASKS_LOWPWR
+ Enable Low-power mode (variable latency)
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_POFWARN
+ Power failure warning
+ 0x108
+ read-write
+
+
+ EVENTS_POFWARN
+ Power failure warning
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_SLEEPENTER
+ CPU entered WFI/WFE sleep
+ 0x114
+ read-write
+
+
+ EVENTS_SLEEPENTER
+ CPU entered WFI/WFE sleep
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_SLEEPEXIT
+ CPU exited WFI/WFE sleep
+ 0x118
+ read-write
+
+
+ EVENTS_SLEEPEXIT
+ CPU exited WFI/WFE sleep
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ POFWARN
+ Write '1' to enable interrupt for event POFWARN
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SLEEPENTER
+ Write '1' to enable interrupt for event SLEEPENTER
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SLEEPEXIT
+ Write '1' to enable interrupt for event SLEEPEXIT
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ POFWARN
+ Write '1' to disable interrupt for event POFWARN
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SLEEPENTER
+ Write '1' to disable interrupt for event SLEEPENTER
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SLEEPEXIT
+ Write '1' to disable interrupt for event SLEEPEXIT
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ RESETREAS
+ Reset reason
+ 0x400
+ read-write
+
+
+ RESETPIN
+ Reset from pin-reset detected
+ 0
+ 0
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ DOG
+ Reset from watchdog detected
+ 1
+ 1
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ SREQ
+ Reset from soft reset detected
+ 2
+ 2
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ LOCKUP
+ Reset from CPU lock-up detected
+ 3
+ 3
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ OFF
+ Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO
+ 16
+ 16
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ DIF
+ Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode
+ 18
+ 18
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+
+
+ SYSTEMOFF
+ System OFF register
+ 0x500
+ write-only
+
+
+ SYSTEMOFF
+ Enable System OFF mode
+ 0
+ 0
+
+
+ Enter
+ Enable System OFF mode
+ 1
+
+
+
+
+
+
+ POFCON
+ Power failure comparator configuration
+ 0x510
+ read-write
+
+
+ POF
+ Enable or disable power failure comparator
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ THRESHOLD
+ Power failure comparator threshold setting
+ 1
+ 4
+
+
+ V17
+ Set threshold to 1.7 V
+ 4
+
+
+ V18
+ Set threshold to 1.8 V
+ 5
+
+
+ V19
+ Set threshold to 1.9 V
+ 6
+
+
+ V20
+ Set threshold to 2.0 V
+ 7
+
+
+ V21
+ Set threshold to 2.1 V
+ 8
+
+
+ V22
+ Set threshold to 2.2 V
+ 9
+
+
+ V23
+ Set threshold to 2.3 V
+ 10
+
+
+ V24
+ Set threshold to 2.4 V
+ 11
+
+
+ V25
+ Set threshold to 2.5 V
+ 12
+
+
+ V26
+ Set threshold to 2.6 V
+ 13
+
+
+ V27
+ Set threshold to 2.7 V
+ 14
+
+
+ V28
+ Set threshold to 2.8 V
+ 15
+
+
+
+
+
+
+ GPREGRET
+ General purpose retention register
+ 0x51C
+ read-write
+
+
+ GPREGRET
+ General purpose retention register
+ 0
+ 7
+
+
+
+
+ GPREGRET2
+ General purpose retention register
+ 0x520
+ read-write
+
+
+ GPREGRET
+ General purpose retention register
+ 0
+ 7
+
+
+
+
+ DCDCEN
+ DC/DC enable register
+ 0x578
+ read-write
+
+
+ DCDCEN
+ Enable or disable DC/DC converter
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ 8
+ 0x010
+ RAM[%s]
+ Unspecified
+ POWER_RAM
+ read-write
+ 0x900
+
+ POWER
+ Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device.
+ 0x000
+ read-write
+ 0x0000FFFF
+
+
+ S0POWER
+ Keep RAM section S0 ON or OFF in System ON mode.
+ 0
+ 0
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S1POWER
+ Keep RAM section S1 ON or OFF in System ON mode.
+ 1
+ 1
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S0RETENTION
+ Keep retention on RAM section S0 when RAM section is in OFF
+ 16
+ 16
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S1RETENTION
+ Keep retention on RAM section S1 when RAM section is in OFF
+ 17
+ 17
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+
+
+ POWERSET
+ Description cluster: RAMn power control set register
+ 0x004
+ write-only
+ 0x0000FFFF
+
+
+ S0POWER
+ Keep RAM section S0 of RAMn on or off in System ON mode
+ 0
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S1POWER
+ Keep RAM section S1 of RAMn on or off in System ON mode
+ 1
+ 1
+
+
+ On
+ On
+ 1
+
+
+
+
+ S0RETENTION
+ Keep retention on RAM section S0 when RAM section is switched off
+ 16
+ 16
+
+
+ On
+ On
+ 1
+
+
+
+
+ S1RETENTION
+ Keep retention on RAM section S1 when RAM section is switched off
+ 17
+ 17
+
+
+ On
+ On
+ 1
+
+
+
+
+
+
+ POWERCLR
+ Description cluster: RAMn power control clear register
+ 0x008
+ write-only
+ 0x0000FFFF
+
+
+ S0POWER
+ Keep RAM section S0 of RAMn on or off in System ON mode
+ 0
+ 0
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S1POWER
+ Keep RAM section S1 of RAMn on or off in System ON mode
+ 1
+ 1
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S0RETENTION
+ Keep retention on RAM section S0 when RAM section is switched off
+ 16
+ 16
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S1RETENTION
+ Keep retention on RAM section S1 when RAM section is switched off
+ 17
+ 17
+
+
+ Off
+ Off
+ 1
+
+
+
+
+
+
+
+
+
+ P0
+ GPIO Port
+ 0x50000000
+ GPIO
+
+ 0
+ 0x1000
+ registers
+
+ GPIO
+ 0x20
+
+
+ OUT
+ Write GPIO port
+ 0x504
+ read-write
+
+
+ PIN0
+ Pin 0
+ 0
+ 0
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN1
+ Pin 1
+ 1
+ 1
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN2
+ Pin 2
+ 2
+ 2
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN3
+ Pin 3
+ 3
+ 3
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN4
+ Pin 4
+ 4
+ 4
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN5
+ Pin 5
+ 5
+ 5
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN6
+ Pin 6
+ 6
+ 6
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN7
+ Pin 7
+ 7
+ 7
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN8
+ Pin 8
+ 8
+ 8
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN9
+ Pin 9
+ 9
+ 9
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN10
+ Pin 10
+ 10
+ 10
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN11
+ Pin 11
+ 11
+ 11
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN12
+ Pin 12
+ 12
+ 12
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN13
+ Pin 13
+ 13
+ 13
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN14
+ Pin 14
+ 14
+ 14
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN15
+ Pin 15
+ 15
+ 15
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN16
+ Pin 16
+ 16
+ 16
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN17
+ Pin 17
+ 17
+ 17
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN18
+ Pin 18
+ 18
+ 18
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN19
+ Pin 19
+ 19
+ 19
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN20
+ Pin 20
+ 20
+ 20
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN21
+ Pin 21
+ 21
+ 21
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN22
+ Pin 22
+ 22
+ 22
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN23
+ Pin 23
+ 23
+ 23
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN24
+ Pin 24
+ 24
+ 24
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN25
+ Pin 25
+ 25
+ 25
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN26
+ Pin 26
+ 26
+ 26
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN27
+ Pin 27
+ 27
+ 27
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN28
+ Pin 28
+ 28
+ 28
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN29
+ Pin 29
+ 29
+ 29
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN30
+ Pin 30
+ 30
+ 30
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN31
+ Pin 31
+ 31
+ 31
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+
+
+ OUTSET
+ Set individual bits in GPIO port
+ 0x508
+ read-write
+ oneToSet
+
+
+ PIN0
+ Pin 0
+ 0
+ 0
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN1
+ Pin 1
+ 1
+ 1
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN2
+ Pin 2
+ 2
+ 2
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN3
+ Pin 3
+ 3
+ 3
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN4
+ Pin 4
+ 4
+ 4
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN5
+ Pin 5
+ 5
+ 5
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN6
+ Pin 6
+ 6
+ 6
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN7
+ Pin 7
+ 7
+ 7
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN8
+ Pin 8
+ 8
+ 8
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN9
+ Pin 9
+ 9
+ 9
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN10
+ Pin 10
+ 10
+ 10
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN11
+ Pin 11
+ 11
+ 11
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN12
+ Pin 12
+ 12
+ 12
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN13
+ Pin 13
+ 13
+ 13
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN14
+ Pin 14
+ 14
+ 14
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN15
+ Pin 15
+ 15
+ 15
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN16
+ Pin 16
+ 16
+ 16
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN17
+ Pin 17
+ 17
+ 17
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN18
+ Pin 18
+ 18
+ 18
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN19
+ Pin 19
+ 19
+ 19
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN20
+ Pin 20
+ 20
+ 20
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN21
+ Pin 21
+ 21
+ 21
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN22
+ Pin 22
+ 22
+ 22
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN23
+ Pin 23
+ 23
+ 23
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN24
+ Pin 24
+ 24
+ 24
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN25
+ Pin 25
+ 25
+ 25
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN26
+ Pin 26
+ 26
+ 26
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN27
+ Pin 27
+ 27
+ 27
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN28
+ Pin 28
+ 28
+ 28
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN29
+ Pin 29
+ 29
+ 29
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN30
+ Pin 30
+ 30
+ 30
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN31
+ Pin 31
+ 31
+ 31
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+
+
+ OUTCLR
+ Clear individual bits in GPIO port
+ 0x50C
+ read-write
+ oneToClear
+
+
+ PIN0
+ Pin 0
+ 0
+ 0
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN1
+ Pin 1
+ 1
+ 1
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN2
+ Pin 2
+ 2
+ 2
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN3
+ Pin 3
+ 3
+ 3
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN4
+ Pin 4
+ 4
+ 4
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN5
+ Pin 5
+ 5
+ 5
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN6
+ Pin 6
+ 6
+ 6
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN7
+ Pin 7
+ 7
+ 7
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN8
+ Pin 8
+ 8
+ 8
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN9
+ Pin 9
+ 9
+ 9
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN10
+ Pin 10
+ 10
+ 10
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN11
+ Pin 11
+ 11
+ 11
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN12
+ Pin 12
+ 12
+ 12
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN13
+ Pin 13
+ 13
+ 13
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN14
+ Pin 14
+ 14
+ 14
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN15
+ Pin 15
+ 15
+ 15
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN16
+ Pin 16
+ 16
+ 16
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN17
+ Pin 17
+ 17
+ 17
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN18
+ Pin 18
+ 18
+ 18
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN19
+ Pin 19
+ 19
+ 19
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN20
+ Pin 20
+ 20
+ 20
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN21
+ Pin 21
+ 21
+ 21
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN22
+ Pin 22
+ 22
+ 22
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN23
+ Pin 23
+ 23
+ 23
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN24
+ Pin 24
+ 24
+ 24
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN25
+ Pin 25
+ 25
+ 25
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN26
+ Pin 26
+ 26
+ 26
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN27
+ Pin 27
+ 27
+ 27
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN28
+ Pin 28
+ 28
+ 28
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN29
+ Pin 29
+ 29
+ 29
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN30
+ Pin 30
+ 30
+ 30
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN31
+ Pin 31
+ 31
+ 31
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+
+
+ IN
+ Read GPIO port
+ 0x510
+ read-only
+
+
+ PIN0
+ Pin 0
+ 0
+ 0
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN1
+ Pin 1
+ 1
+ 1
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN2
+ Pin 2
+ 2
+ 2
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN3
+ Pin 3
+ 3
+ 3
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN4
+ Pin 4
+ 4
+ 4
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN5
+ Pin 5
+ 5
+ 5
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN6
+ Pin 6
+ 6
+ 6
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN7
+ Pin 7
+ 7
+ 7
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN8
+ Pin 8
+ 8
+ 8
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN9
+ Pin 9
+ 9
+ 9
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN10
+ Pin 10
+ 10
+ 10
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN11
+ Pin 11
+ 11
+ 11
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN12
+ Pin 12
+ 12
+ 12
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN13
+ Pin 13
+ 13
+ 13
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN14
+ Pin 14
+ 14
+ 14
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN15
+ Pin 15
+ 15
+ 15
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN16
+ Pin 16
+ 16
+ 16
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN17
+ Pin 17
+ 17
+ 17
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN18
+ Pin 18
+ 18
+ 18
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN19
+ Pin 19
+ 19
+ 19
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN20
+ Pin 20
+ 20
+ 20
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN21
+ Pin 21
+ 21
+ 21
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN22
+ Pin 22
+ 22
+ 22
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN23
+ Pin 23
+ 23
+ 23
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN24
+ Pin 24
+ 24
+ 24
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN25
+ Pin 25
+ 25
+ 25
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN26
+ Pin 26
+ 26
+ 26
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN27
+ Pin 27
+ 27
+ 27
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN28
+ Pin 28
+ 28
+ 28
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN29
+ Pin 29
+ 29
+ 29
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN30
+ Pin 30
+ 30
+ 30
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN31
+ Pin 31
+ 31
+ 31
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+
+
+ DIR
+ Direction of GPIO pins
+ 0x514
+ read-write
+
+
+ PIN0
+ Pin 0
+ 0
+ 0
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN1
+ Pin 1
+ 1
+ 1
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN2
+ Pin 2
+ 2
+ 2
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN3
+ Pin 3
+ 3
+ 3
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN4
+ Pin 4
+ 4
+ 4
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN5
+ Pin 5
+ 5
+ 5
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN6
+ Pin 6
+ 6
+ 6
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN7
+ Pin 7
+ 7
+ 7
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN8
+ Pin 8
+ 8
+ 8
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN9
+ Pin 9
+ 9
+ 9
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN10
+ Pin 10
+ 10
+ 10
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN11
+ Pin 11
+ 11
+ 11
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN12
+ Pin 12
+ 12
+ 12
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN13
+ Pin 13
+ 13
+ 13
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN14
+ Pin 14
+ 14
+ 14
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN15
+ Pin 15
+ 15
+ 15
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN16
+ Pin 16
+ 16
+ 16
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN17
+ Pin 17
+ 17
+ 17
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN18
+ Pin 18
+ 18
+ 18
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN19
+ Pin 19
+ 19
+ 19
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN20
+ Pin 20
+ 20
+ 20
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN21
+ Pin 21
+ 21
+ 21
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN22
+ Pin 22
+ 22
+ 22
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN23
+ Pin 23
+ 23
+ 23
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN24
+ Pin 24
+ 24
+ 24
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN25
+ Pin 25
+ 25
+ 25
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN26
+ Pin 26
+ 26
+ 26
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN27
+ Pin 27
+ 27
+ 27
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN28
+ Pin 28
+ 28
+ 28
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN29
+ Pin 29
+ 29
+ 29
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN30
+ Pin 30
+ 30
+ 30
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN31
+ Pin 31
+ 31
+ 31
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+
+
+ DIRSET
+ DIR set register
+ 0x518
+ read-write
+ oneToSet
+
+
+ PIN0
+ Set as output pin 0
+ 0
+ 0
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN1
+ Set as output pin 1
+ 1
+ 1
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN2
+ Set as output pin 2
+ 2
+ 2
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN3
+ Set as output pin 3
+ 3
+ 3
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN4
+ Set as output pin 4
+ 4
+ 4
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN5
+ Set as output pin 5
+ 5
+ 5
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN6
+ Set as output pin 6
+ 6
+ 6
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN7
+ Set as output pin 7
+ 7
+ 7
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN8
+ Set as output pin 8
+ 8
+ 8
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN9
+ Set as output pin 9
+ 9
+ 9
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN10
+ Set as output pin 10
+ 10
+ 10
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN11
+ Set as output pin 11
+ 11
+ 11
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN12
+ Set as output pin 12
+ 12
+ 12
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN13
+ Set as output pin 13
+ 13
+ 13
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN14
+ Set as output pin 14
+ 14
+ 14
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN15
+ Set as output pin 15
+ 15
+ 15
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN16
+ Set as output pin 16
+ 16
+ 16
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN17
+ Set as output pin 17
+ 17
+ 17
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN18
+ Set as output pin 18
+ 18
+ 18
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN19
+ Set as output pin 19
+ 19
+ 19
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN20
+ Set as output pin 20
+ 20
+ 20
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN21
+ Set as output pin 21
+ 21
+ 21
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN22
+ Set as output pin 22
+ 22
+ 22
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN23
+ Set as output pin 23
+ 23
+ 23
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN24
+ Set as output pin 24
+ 24
+ 24
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN25
+ Set as output pin 25
+ 25
+ 25
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN26
+ Set as output pin 26
+ 26
+ 26
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN27
+ Set as output pin 27
+ 27
+ 27
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN28
+ Set as output pin 28
+ 28
+ 28
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN29
+ Set as output pin 29
+ 29
+ 29
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN30
+ Set as output pin 30
+ 30
+ 30
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN31
+ Set as output pin 31
+ 31
+ 31
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+
+
+ DIRCLR
+ DIR clear register
+ 0x51C
+ read-write
+ oneToClear
+
+
+ PIN0
+ Set as input pin 0
+ 0
+ 0
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN1
+ Set as input pin 1
+ 1
+ 1
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN2
+ Set as input pin 2
+ 2
+ 2
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN3
+ Set as input pin 3
+ 3
+ 3
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN4
+ Set as input pin 4
+ 4
+ 4
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN5
+ Set as input pin 5
+ 5
+ 5
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN6
+ Set as input pin 6
+ 6
+ 6
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN7
+ Set as input pin 7
+ 7
+ 7
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN8
+ Set as input pin 8
+ 8
+ 8
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN9
+ Set as input pin 9
+ 9
+ 9
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN10
+ Set as input pin 10
+ 10
+ 10
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN11
+ Set as input pin 11
+ 11
+ 11
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN12
+ Set as input pin 12
+ 12
+ 12
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN13
+ Set as input pin 13
+ 13
+ 13
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN14
+ Set as input pin 14
+ 14
+ 14
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN15
+ Set as input pin 15
+ 15
+ 15
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN16
+ Set as input pin 16
+ 16
+ 16
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN17
+ Set as input pin 17
+ 17
+ 17
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN18
+ Set as input pin 18
+ 18
+ 18
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN19
+ Set as input pin 19
+ 19
+ 19
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN20
+ Set as input pin 20
+ 20
+ 20
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN21
+ Set as input pin 21
+ 21
+ 21
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN22
+ Set as input pin 22
+ 22
+ 22
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN23
+ Set as input pin 23
+ 23
+ 23
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN24
+ Set as input pin 24
+ 24
+ 24
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN25
+ Set as input pin 25
+ 25
+ 25
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN26
+ Set as input pin 26
+ 26
+ 26
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN27
+ Set as input pin 27
+ 27
+ 27
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN28
+ Set as input pin 28
+ 28
+ 28
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN29
+ Set as input pin 29
+ 29
+ 29
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN30
+ Set as input pin 30
+ 30
+ 30
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN31
+ Set as input pin 31
+ 31
+ 31
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+
+
+ LATCH
+ Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers
+ 0x520
+ read-write
+
+
+ PIN0
+ Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.
+ 0
+ 0
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN1
+ Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.
+ 1
+ 1
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN2
+ Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.
+ 2
+ 2
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN3
+ Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.
+ 3
+ 3
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN4
+ Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.
+ 4
+ 4
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN5
+ Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.
+ 5
+ 5
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN6
+ Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.
+ 6
+ 6
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN7
+ Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.
+ 7
+ 7
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN8
+ Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.
+ 8
+ 8
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN9
+ Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.
+ 9
+ 9
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN10
+ Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.
+ 10
+ 10
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN11
+ Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.
+ 11
+ 11
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN12
+ Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.
+ 12
+ 12
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN13
+ Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.
+ 13
+ 13
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN14
+ Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.
+ 14
+ 14
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN15
+ Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.
+ 15
+ 15
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN16
+ Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.
+ 16
+ 16
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN17
+ Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.
+ 17
+ 17
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN18
+ Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.
+ 18
+ 18
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN19
+ Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.
+ 19
+ 19
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN20
+ Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.
+ 20
+ 20
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN21
+ Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.
+ 21
+ 21
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN22
+ Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.
+ 22
+ 22
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN23
+ Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.
+ 23
+ 23
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN24
+ Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.
+ 24
+ 24
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN25
+ Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.
+ 25
+ 25
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN26
+ Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.
+ 26
+ 26
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN27
+ Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.
+ 27
+ 27
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN28
+ Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.
+ 28
+ 28
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN29
+ Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.
+ 29
+ 29
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN30
+ Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.
+ 30
+ 30
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN31
+ Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.
+ 31
+ 31
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+
+
+ DETECTMODE
+ Select between default DETECT signal behaviour and LDETECT mode
+ 0x524
+ read-write
+
+
+ DETECTMODE
+ Select between default DETECT signal behaviour and LDETECT mode
+ 0
+ 0
+
+
+ Default
+ DETECT directly connected to PIN DETECT signals
+ 0
+
+
+ LDETECT
+ Use the latched LDETECT behaviour
+ 1
+
+
+
+
+
+
+ 0x20
+ 0x4
+ PIN_CNF[%s]
+ Description collection: Configuration of GPIO pins
+ 0x700
+ read-write
+ 0x00000002
+
+
+ DIR
+ Pin direction. Same physical register as DIR register
+ 0
+ 0
+
+
+ Input
+ Configure pin as an input pin
+ 0
+
+
+ Output
+ Configure pin as an output pin
+ 1
+
+
+
+
+ INPUT
+ Connect or disconnect input buffer
+ 1
+ 1
+
+
+ Connect
+ Connect input buffer
+ 0
+
+
+ Disconnect
+ Disconnect input buffer
+ 1
+
+
+
+
+ PULL
+ Pull configuration
+ 2
+ 3
+
+
+ Disabled
+ No pull
+ 0
+
+
+ Pulldown
+ Pull down on pin
+ 1
+
+
+ Pullup
+ Pull up on pin
+ 3
+
+
+
+
+ DRIVE
+ Drive configuration
+ 8
+ 10
+
+
+ S0S1
+ Standard '0', standard '1'
+ 0
+
+
+ H0S1
+ High drive '0', standard '1'
+ 1
+
+
+ S0H1
+ Standard '0', high drive '1'
+ 2
+
+
+ H0H1
+ High drive '0', high 'drive '1''
+ 3
+
+
+ D0S1
+ Disconnect '0' standard '1' (normally used for wired-or connections)
+ 4
+
+
+ D0H1
+ Disconnect '0', high drive '1' (normally used for wired-or connections)
+ 5
+
+
+ S0D1
+ Standard '0'. disconnect '1' (normally used for wired-and connections)
+ 6
+
+
+ H0D1
+ High drive '0', disconnect '1' (normally used for wired-and connections)
+ 7
+
+
+
+
+ SENSE
+ Pin sensing mechanism
+ 16
+ 17
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ High
+ Sense for high level
+ 2
+
+
+ Low
+ Sense for low level
+ 3
+
+
+
+
+
+
+
+
+ RADIO
+ 2.4 GHz radio
+ 0x40001000
+
+ 0
+ 0x1000
+ registers
+
+
+ RADIO
+ 1
+
+ RADIO
+ 0x20
+
+
+ TASKS_TXEN
+ Enable RADIO in TX mode
+ 0x000
+ write-only
+
+
+ TASKS_TXEN
+ Enable RADIO in TX mode
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RXEN
+ Enable RADIO in RX mode
+ 0x004
+ write-only
+
+
+ TASKS_RXEN
+ Enable RADIO in RX mode
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_START
+ Start RADIO
+ 0x008
+ write-only
+
+
+ TASKS_START
+ Start RADIO
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop RADIO
+ 0x00C
+ write-only
+
+
+ TASKS_STOP
+ Stop RADIO
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_DISABLE
+ Disable RADIO
+ 0x010
+ write-only
+
+
+ TASKS_DISABLE
+ Disable RADIO
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RSSISTART
+ Start the RSSI and take one single sample of the receive signal strength
+ 0x014
+ write-only
+
+
+ TASKS_RSSISTART
+ Start the RSSI and take one single sample of the receive signal strength
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RSSISTOP
+ Stop the RSSI measurement
+ 0x018
+ write-only
+
+
+ TASKS_RSSISTOP
+ Stop the RSSI measurement
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_BCSTART
+ Start the bit counter
+ 0x01C
+ write-only
+
+
+ TASKS_BCSTART
+ Start the bit counter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_BCSTOP
+ Stop the bit counter
+ 0x020
+ write-only
+
+
+ TASKS_BCSTOP
+ Stop the bit counter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_READY
+ RADIO has ramped up and is ready to be started
+ 0x100
+ read-write
+
+
+ EVENTS_READY
+ RADIO has ramped up and is ready to be started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ADDRESS
+ Address sent or received
+ 0x104
+ read-write
+
+
+ EVENTS_ADDRESS
+ Address sent or received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_PAYLOAD
+ Packet payload sent or received
+ 0x108
+ read-write
+
+
+ EVENTS_PAYLOAD
+ Packet payload sent or received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ Packet sent or received
+ 0x10C
+ read-write
+
+
+ EVENTS_END
+ Packet sent or received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DISABLED
+ RADIO has been disabled
+ 0x110
+ read-write
+
+
+ EVENTS_DISABLED
+ RADIO has been disabled
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DEVMATCH
+ A device address match occurred on the last received packet
+ 0x114
+ read-write
+
+
+ EVENTS_DEVMATCH
+ A device address match occurred on the last received packet
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DEVMISS
+ No device address match occurred on the last received packet
+ 0x118
+ read-write
+
+
+ EVENTS_DEVMISS
+ No device address match occurred on the last received packet
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RSSIEND
+ Sampling of receive signal strength complete
+ 0x11C
+ read-write
+
+
+ EVENTS_RSSIEND
+ Sampling of receive signal strength complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_BCMATCH
+ Bit counter reached bit count value
+ 0x128
+ read-write
+
+
+ EVENTS_BCMATCH
+ Bit counter reached bit count value
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CRCOK
+ Packet received with CRC ok
+ 0x130
+ read-write
+
+
+ EVENTS_CRCOK
+ Packet received with CRC ok
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CRCERROR
+ Packet received with CRC error
+ 0x134
+ read-write
+
+
+ EVENTS_CRCERROR
+ Packet received with CRC error
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXREADY
+ RADIO has ramped up and is ready to be started TX path
+ 0x154
+ read-write
+
+
+ EVENTS_TXREADY
+ RADIO has ramped up and is ready to be started TX path
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXREADY
+ RADIO has ramped up and is ready to be started RX path
+ 0x158
+ read-write
+
+
+ EVENTS_RXREADY
+ RADIO has ramped up and is ready to be started RX path
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_MHRMATCH
+ MAC header match found
+ 0x15C
+ read-write
+
+
+ EVENTS_MHRMATCH
+ MAC header match found
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_PHYEND
+ Generated when last bit is sent on air
+ 0x16C
+ read-write
+
+
+ EVENTS_PHYEND
+ Generated when last bit is sent on air
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ READY_START
+ Shortcut between event READY and task START
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ END_DISABLE
+ Shortcut between event END and task DISABLE
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ DISABLED_TXEN
+ Shortcut between event DISABLED and task TXEN
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ DISABLED_RXEN
+ Shortcut between event DISABLED and task RXEN
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ ADDRESS_RSSISTART
+ Shortcut between event ADDRESS and task RSSISTART
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ END_START
+ Shortcut between event END and task START
+ 5
+ 5
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ ADDRESS_BCSTART
+ Shortcut between event ADDRESS and task BCSTART
+ 6
+ 6
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ DISABLED_RSSISTOP
+ Shortcut between event DISABLED and task RSSISTOP
+ 8
+ 8
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ TXREADY_START
+ Shortcut between event TXREADY and task START
+ 18
+ 18
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ RXREADY_START
+ Shortcut between event RXREADY and task START
+ 19
+ 19
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ PHYEND_DISABLE
+ Shortcut between event PHYEND and task DISABLE
+ 20
+ 20
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ PHYEND_START
+ Shortcut between event PHYEND and task START
+ 21
+ 21
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ READY
+ Write '1' to enable interrupt for event READY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ADDRESS
+ Write '1' to enable interrupt for event ADDRESS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PAYLOAD
+ Write '1' to enable interrupt for event PAYLOAD
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DISABLED
+ Write '1' to enable interrupt for event DISABLED
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DEVMATCH
+ Write '1' to enable interrupt for event DEVMATCH
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DEVMISS
+ Write '1' to enable interrupt for event DEVMISS
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RSSIEND
+ Write '1' to enable interrupt for event RSSIEND
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ BCMATCH
+ Write '1' to enable interrupt for event BCMATCH
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CRCOK
+ Write '1' to enable interrupt for event CRCOK
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CRCERROR
+ Write '1' to enable interrupt for event CRCERROR
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXREADY
+ Write '1' to enable interrupt for event TXREADY
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXREADY
+ Write '1' to enable interrupt for event RXREADY
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ MHRMATCH
+ Write '1' to enable interrupt for event MHRMATCH
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PHYEND
+ Write '1' to enable interrupt for event PHYEND
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ READY
+ Write '1' to disable interrupt for event READY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ADDRESS
+ Write '1' to disable interrupt for event ADDRESS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PAYLOAD
+ Write '1' to disable interrupt for event PAYLOAD
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DISABLED
+ Write '1' to disable interrupt for event DISABLED
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DEVMATCH
+ Write '1' to disable interrupt for event DEVMATCH
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DEVMISS
+ Write '1' to disable interrupt for event DEVMISS
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RSSIEND
+ Write '1' to disable interrupt for event RSSIEND
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ BCMATCH
+ Write '1' to disable interrupt for event BCMATCH
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CRCOK
+ Write '1' to disable interrupt for event CRCOK
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CRCERROR
+ Write '1' to disable interrupt for event CRCERROR
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXREADY
+ Write '1' to disable interrupt for event TXREADY
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXREADY
+ Write '1' to disable interrupt for event RXREADY
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ MHRMATCH
+ Write '1' to disable interrupt for event MHRMATCH
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PHYEND
+ Write '1' to disable interrupt for event PHYEND
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ CRCSTATUS
+ CRC status
+ 0x400
+ read-only
+
+
+ CRCSTATUS
+ CRC status of packet received
+ 0
+ 0
+
+
+ CRCError
+ Packet received with CRC error
+ 0
+
+
+ CRCOk
+ Packet received with CRC ok
+ 1
+
+
+
+
+
+
+ RXMATCH
+ Received address
+ 0x408
+ read-only
+
+
+ RXMATCH
+ Received address
+ 0
+ 2
+
+
+
+
+ RXCRC
+ CRC field of previously received packet
+ 0x40C
+ read-only
+
+
+ RXCRC
+ CRC field of previously received packet
+ 0
+ 23
+
+
+
+
+ DAI
+ Device address match index
+ 0x410
+ read-only
+
+
+ DAI
+ Device address match index
+ 0
+ 2
+
+
+
+
+ PDUSTAT
+ Payload status
+ 0x414
+ read-only
+
+
+ PDUSTAT
+ Status on payload length vs. PCNF1.MAXLEN
+ 0
+ 0
+
+
+ LessThan
+ Payload less than PCNF1.MAXLEN
+ 0
+
+
+ GreaterThan
+ Payload greater than PCNF1.MAXLEN
+ 1
+
+
+
+
+
+
+ PACKETPTR
+ Packet pointer
+ 0x504
+ read-write
+ 0x00000000
+
+
+ PACKETPTR
+ Packet pointer
+ 0
+ 31
+
+
+
+
+ FREQUENCY
+ Frequency
+ 0x508
+ read-write
+ 0x00000002
+
+
+ FREQUENCY
+ Radio channel frequency
+ 0
+ 6
+
+
+ MAP
+ Channel map selection.
+ 8
+ 8
+
+
+ Default
+ Channel map between 2400 MHZ .. 2500 MHz
+ 0
+
+
+ Low
+ Channel map between 2360 MHZ .. 2460 MHz
+ 1
+
+
+
+
+
+
+ TXPOWER
+ Output power
+ 0x50C
+ read-write
+
+
+ TXPOWER
+ RADIO output power
+ 0
+ 7
+
+
+ Pos4dBm
+ +4 dBm
+ 0x4
+
+
+ Pos3dBm
+ +3 dBm
+ 0x3
+
+
+ 0dBm
+ 0 dBm
+ 0x0
+
+
+ Neg4dBm
+ -4 dBm
+ 0xFC
+
+
+ Neg8dBm
+ -8 dBm
+ 0xF8
+
+
+ Neg12dBm
+ -12 dBm
+ 0xF4
+
+
+ Neg16dBm
+ -16 dBm
+ 0xF0
+
+
+ Neg20dBm
+ -20 dBm
+ 0xEC
+
+
+ Neg30dBm
+ Deprecated enumerator - -40 dBm
+ 0xE2
+
+
+ Neg40dBm
+ -40 dBm
+ 0xD8
+
+
+
+
+
+
+ MODE
+ Data rate and modulation
+ 0x510
+ read-write
+
+
+ MODE
+ Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation.
+ 0
+ 3
+
+
+ Nrf_1Mbit
+ 1 Mbps Nordic proprietary radio mode
+ 0
+
+
+ Nrf_2Mbit
+ 2 Mbps Nordic proprietary radio mode
+ 1
+
+
+ Ble_1Mbit
+ 1 Mbps BLE
+ 3
+
+
+ Ble_2Mbit
+ 2 Mbps BLE
+ 4
+
+
+
+
+
+
+ PCNF0
+ Packet configuration register 0
+ 0x514
+ read-write
+
+
+ LFLEN
+ Length on air of LENGTH field in number of bits.
+ 0
+ 3
+
+
+ S0LEN
+ Length on air of S0 field in number of bytes.
+ 8
+ 8
+
+
+ S1LEN
+ Length on air of S1 field in number of bits.
+ 16
+ 19
+
+
+ S1INCL
+ Include or exclude S1 field in RAM
+ 20
+ 20
+
+
+ Automatic
+ Include S1 field in RAM only if S1LEN > 0
+ 0
+
+
+ Include
+ Always include S1 field in RAM independent of S1LEN
+ 1
+
+
+
+
+ PLEN
+ Length of preamble on air. Decision point: TASKS_START task
+ 24
+ 25
+
+
+ 8bit
+ 8-bit preamble
+ 0
+
+
+ 16bit
+ 16-bit preamble
+ 1
+
+
+
+
+ CRCINC
+ Indicates if LENGTH field contains CRC or not
+ 26
+ 26
+
+
+ Exclude
+ LENGTH does not contain CRC
+ 0
+
+
+ Include
+ LENGTH includes CRC
+ 1
+
+
+
+
+
+
+ PCNF1
+ Packet configuration register 1
+ 0x518
+ read-write
+
+
+ MAXLEN
+ Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
+ 0
+ 7
+
+
+ STATLEN
+ Static length in number of bytes
+ 8
+ 15
+
+
+ BALEN
+ Base address length in number of bytes
+ 16
+ 18
+
+
+ ENDIAN
+ On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields.
+ 24
+ 24
+
+
+ Little
+ Least significant bit on air first
+ 0
+
+
+ Big
+ Most significant bit on air first
+ 1
+
+
+
+
+ WHITEEN
+ Enable or disable packet whitening
+ 25
+ 25
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ BASE0
+ Base address 0
+ 0x51C
+ read-write
+
+
+ BASE0
+ Base address 0
+ 0
+ 31
+
+
+
+
+ BASE1
+ Base address 1
+ 0x520
+ read-write
+
+
+ BASE1
+ Base address 1
+ 0
+ 31
+
+
+
+
+ PREFIX0
+ Prefixes bytes for logical addresses 0-3
+ 0x524
+ read-write
+
+
+ AP0
+ Address prefix 0.
+ 0
+ 7
+
+
+ AP1
+ Address prefix 1.
+ 8
+ 15
+
+
+ AP2
+ Address prefix 2.
+ 16
+ 23
+
+
+ AP3
+ Address prefix 3.
+ 24
+ 31
+
+
+
+
+ PREFIX1
+ Prefixes bytes for logical addresses 4-7
+ 0x528
+ read-write
+
+
+ AP4
+ Address prefix 4.
+ 0
+ 7
+
+
+ AP5
+ Address prefix 5.
+ 8
+ 15
+
+
+ AP6
+ Address prefix 6.
+ 16
+ 23
+
+
+ AP7
+ Address prefix 7.
+ 24
+ 31
+
+
+
+
+ TXADDRESS
+ Transmit address select
+ 0x52C
+ read-write
+
+
+ TXADDRESS
+ Transmit address select
+ 0
+ 2
+
+
+
+
+ RXADDRESSES
+ Receive address select
+ 0x530
+ read-write
+
+
+ ADDR0
+ Enable or disable reception on logical address 0.
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR1
+ Enable or disable reception on logical address 1.
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR2
+ Enable or disable reception on logical address 2.
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR3
+ Enable or disable reception on logical address 3.
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR4
+ Enable or disable reception on logical address 4.
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR5
+ Enable or disable reception on logical address 5.
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR6
+ Enable or disable reception on logical address 6.
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR7
+ Enable or disable reception on logical address 7.
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ CRCCNF
+ CRC configuration
+ 0x534
+ read-write
+
+
+ LEN
+ CRC length in number of bytes.
+ 0
+ 1
+
+
+ Disabled
+ CRC length is zero and CRC calculation is disabled
+ 0
+
+
+ One
+ CRC length is one byte and CRC calculation is enabled
+ 1
+
+
+ Two
+ CRC length is two bytes and CRC calculation is enabled
+ 2
+
+
+ Three
+ CRC length is three bytes and CRC calculation is enabled
+ 3
+
+
+
+
+ SKIPADDR
+ Include or exclude packet address field out of CRC calculation.
+ 8
+ 9
+
+
+ Include
+ CRC calculation includes address field
+ 0
+
+
+ Skip
+ CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.
+ 1
+
+
+
+
+
+
+ CRCPOLY
+ CRC polynomial
+ 0x538
+ read-write
+ 0x00000000
+
+
+ CRCPOLY
+ CRC polynomial
+ 0
+ 23
+
+
+
+
+ CRCINIT
+ CRC initial value
+ 0x53C
+ read-write
+
+
+ CRCINIT
+ CRC initial value
+ 0
+ 23
+
+
+
+
+ TIFS
+ Interframe spacing in us
+ 0x544
+ read-write
+
+
+ TIFS
+ Interframe spacing in us
+ 0
+ 9
+
+
+
+
+ RSSISAMPLE
+ RSSI sample
+ 0x548
+ read-only
+
+
+ RSSISAMPLE
+ RSSI sample
+ 0
+ 6
+
+
+
+
+ STATE
+ Current radio state
+ 0x550
+ read-only
+
+
+ STATE
+ Current radio state
+ 0
+ 3
+
+
+ Disabled
+ RADIO is in the Disabled state
+ 0
+
+
+ RxRu
+ RADIO is in the RXRU state
+ 1
+
+
+ RxIdle
+ RADIO is in the RXIDLE state
+ 2
+
+
+ Rx
+ RADIO is in the RX state
+ 3
+
+
+ RxDisable
+ RADIO is in the RXDISABLED state
+ 4
+
+
+ TxRu
+ RADIO is in the TXRU state
+ 9
+
+
+ TxIdle
+ RADIO is in the TXIDLE state
+ 10
+
+
+ Tx
+ RADIO is in the TX state
+ 11
+
+
+ TxDisable
+ RADIO is in the TXDISABLED state
+ 12
+
+
+
+
+
+
+ DATAWHITEIV
+ Data whitening initial value
+ 0x554
+ read-write
+ 0x00000040
+
+
+ DATAWHITEIV
+ Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.
+ 0
+ 6
+
+
+
+
+ BCC
+ Bit counter compare
+ 0x560
+ read-write
+
+
+ BCC
+ Bit counter compare
+ 0
+ 31
+
+
+
+
+ 0x8
+ 0x4
+ DAB[%s]
+ Description collection: Device address base segment n
+ 0x600
+ read-write
+
+
+ DAB
+ Device address base segment n
+ 0
+ 31
+
+
+
+
+ 0x8
+ 0x4
+ DAP[%s]
+ Description collection: Device address prefix n
+ 0x620
+ read-write
+
+
+ DAP
+ Device address prefix n
+ 0
+ 15
+
+
+
+
+ DACNF
+ Device address match configuration
+ 0x640
+ read-write
+
+
+ ENA0
+ Enable or disable device address matching using device address 0
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA1
+ Enable or disable device address matching using device address 1
+ 1
+ 1
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA2
+ Enable or disable device address matching using device address 2
+ 2
+ 2
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA3
+ Enable or disable device address matching using device address 3
+ 3
+ 3
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA4
+ Enable or disable device address matching using device address 4
+ 4
+ 4
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA5
+ Enable or disable device address matching using device address 5
+ 5
+ 5
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA6
+ Enable or disable device address matching using device address 6
+ 6
+ 6
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA7
+ Enable or disable device address matching using device address 7
+ 7
+ 7
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ TXADD0
+ TxAdd for device address 0
+ 8
+ 8
+
+
+ TXADD1
+ TxAdd for device address 1
+ 9
+ 9
+
+
+ TXADD2
+ TxAdd for device address 2
+ 10
+ 10
+
+
+ TXADD3
+ TxAdd for device address 3
+ 11
+ 11
+
+
+ TXADD4
+ TxAdd for device address 4
+ 12
+ 12
+
+
+ TXADD5
+ TxAdd for device address 5
+ 13
+ 13
+
+
+ TXADD6
+ TxAdd for device address 6
+ 14
+ 14
+
+
+ TXADD7
+ TxAdd for device address 7
+ 15
+ 15
+
+
+
+
+ MODECNF0
+ Radio mode configuration register 0
+ 0x650
+ read-write
+ 0x00000200
+
+
+ RU
+ Radio ramp-up time
+ 0
+ 0
+
+
+ Default
+ Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51
+ 0
+
+
+ Fast
+ Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information
+ 1
+
+
+
+
+ DTX
+ Default TX value
+ 8
+ 9
+
+
+ B1
+ Transmit '1'
+ 0
+
+
+ B0
+ Transmit '0'
+ 1
+
+
+ Center
+ Transmit center frequency
+ 2
+
+
+
+
+
+
+ POWER
+ Peripheral power control
+ 0xFFC
+ read-write
+ 0x00000001
+
+
+ POWER
+ Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.
+ 0
+ 0
+
+
+ Disabled
+ Peripheral is powered off
+ 0
+
+
+ Enabled
+ Peripheral is powered on
+ 1
+
+
+
+
+
+
+
+
+ UART0
+ Universal Asynchronous Receiver/Transmitter
+ 0x40002000
+ UART
+
+ 0
+ 0x1000
+ registers
+
+
+ UARTE0_UART0
+ 2
+
+ UART
+ 0x20
+
+
+ TASKS_STARTRX
+ Start UART receiver
+ 0x000
+ write-only
+
+
+ TASKS_STARTRX
+ Start UART receiver
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOPRX
+ Stop UART receiver
+ 0x004
+ write-only
+
+
+ TASKS_STOPRX
+ Stop UART receiver
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTTX
+ Start UART transmitter
+ 0x008
+ write-only
+
+
+ TASKS_STARTTX
+ Start UART transmitter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOPTX
+ Stop UART transmitter
+ 0x00C
+ write-only
+
+
+ TASKS_STOPTX
+ Stop UART transmitter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SUSPEND
+ Suspend UART
+ 0x01C
+ write-only
+
+
+ TASKS_SUSPEND
+ Suspend UART
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_CTS
+ CTS is activated (set low). Clear To Send.
+ 0x100
+ read-write
+
+
+ EVENTS_CTS
+ CTS is activated (set low). Clear To Send.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_NCTS
+ CTS is deactivated (set high). Not Clear To Send.
+ 0x104
+ read-write
+
+
+ EVENTS_NCTS
+ CTS is deactivated (set high). Not Clear To Send.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXDRDY
+ Data received in RXD
+ 0x108
+ read-write
+
+
+ EVENTS_RXDRDY
+ Data received in RXD
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXDRDY
+ Data sent from TXD
+ 0x11C
+ read-write
+
+
+ EVENTS_TXDRDY
+ Data sent from TXD
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ Error detected
+ 0x124
+ read-write
+
+
+ EVENTS_ERROR
+ Error detected
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXTO
+ Receiver timeout
+ 0x144
+ read-write
+
+
+ EVENTS_RXTO
+ Receiver timeout
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ CTS_STARTRX
+ Shortcut between event CTS and task STARTRX
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ NCTS_STOPRX
+ Shortcut between event NCTS and task STOPRX
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ CTS
+ Write '1' to enable interrupt for event CTS
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ NCTS
+ Write '1' to enable interrupt for event NCTS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXDRDY
+ Write '1' to enable interrupt for event RXDRDY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXDRDY
+ Write '1' to enable interrupt for event TXDRDY
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXTO
+ Write '1' to enable interrupt for event RXTO
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ CTS
+ Write '1' to disable interrupt for event CTS
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ NCTS
+ Write '1' to disable interrupt for event NCTS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXDRDY
+ Write '1' to disable interrupt for event RXDRDY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXDRDY
+ Write '1' to disable interrupt for event TXDRDY
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXTO
+ Write '1' to disable interrupt for event RXTO
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSRC
+ Error source
+ 0x480
+ read-write
+ oneToClear
+
+
+ OVERRUN
+ Overrun error
+ 0
+ 0
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ PARITY
+ Parity error
+ 1
+ 1
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ FRAMING
+ Framing error occurred
+ 2
+ 2
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ BREAK
+ Break condition
+ 3
+ 3
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable UART
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable UART
+ 0
+ 3
+
+
+ Disabled
+ Disable UART
+ 0
+
+
+ Enabled
+ Enable UART
+ 4
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ UART_PSEL
+ read-write
+ 0x508
+
+ RTS
+ Pin select for RTS
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ TXD
+ Pin select for TXD
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ CTS
+ Pin select for CTS
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ RXD
+ Pin select for RXD
+ 0x00C
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ RXD
+ RXD register
+ 0x518
+ read-only
+ modifyExternal
+
+
+ RXD
+ RX data received in previous transfers, double buffered
+ 0
+ 7
+
+
+
+
+ TXD
+ TXD register
+ 0x51C
+ write-only
+
+
+ TXD
+ TX data to be transferred
+ 0
+ 7
+
+
+
+
+ BAUDRATE
+ Baud rate. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ BAUDRATE
+ Baud rate
+ 0
+ 31
+
+
+ Baud1200
+ 1200 baud (actual rate: 1205)
+ 0x0004F000
+
+
+ Baud2400
+ 2400 baud (actual rate: 2396)
+ 0x0009D000
+
+
+ Baud4800
+ 4800 baud (actual rate: 4808)
+ 0x0013B000
+
+
+ Baud9600
+ 9600 baud (actual rate: 9598)
+ 0x00275000
+
+
+ Baud14400
+ 14400 baud (actual rate: 14414)
+ 0x003B0000
+
+
+ Baud19200
+ 19200 baud (actual rate: 19208)
+ 0x004EA000
+
+
+ Baud28800
+ 28800 baud (actual rate: 28829)
+ 0x0075F000
+
+
+ Baud31250
+ 31250 baud
+ 0x00800000
+
+
+ Baud38400
+ 38400 baud (actual rate: 38462)
+ 0x009D5000
+
+
+ Baud56000
+ 56000 baud (actual rate: 55944)
+ 0x00E50000
+
+
+ Baud57600
+ 57600 baud (actual rate: 57762)
+ 0x00EBF000
+
+
+ Baud76800
+ 76800 baud (actual rate: 76923)
+ 0x013A9000
+
+
+ Baud115200
+ 115200 baud (actual rate: 115942)
+ 0x01D7E000
+
+
+ Baud230400
+ 230400 baud (actual rate: 231884)
+ 0x03AFB000
+
+
+ Baud250000
+ 250000 baud
+ 0x04000000
+
+
+ Baud460800
+ 460800 baud (actual rate: 470588)
+ 0x075F7000
+
+
+ Baud921600
+ 921600 baud (actual rate: 941176)
+ 0x0EBED000
+
+
+ Baud1M
+ 1Mega baud
+ 0x10000000
+
+
+
+
+
+
+ CONFIG
+ Configuration of parity and hardware flow control
+ 0x56C
+ read-write
+
+
+ HWFC
+ Hardware flow control
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ PARITY
+ Parity
+ 1
+ 3
+
+
+ Excluded
+ Exclude parity bit
+ 0x0
+
+
+ Included
+ Include parity bit
+ 0x7
+
+
+
+
+ STOP
+ Stop bits
+ 4
+ 4
+
+
+ One
+ One stop bit
+ 0
+
+
+ Two
+ Two stop bits
+ 1
+
+
+
+
+
+
+
+
+ UARTE0
+ UART with EasyDMA
+ 0x40002000
+ UART0
+ UARTE
+
+ 0
+ 0x1000
+ registers
+
+
+ UARTE0_UART0
+ 2
+
+ UARTE
+ 0x20
+
+
+ TASKS_STARTRX
+ Start UART receiver
+ 0x000
+ write-only
+
+
+ TASKS_STARTRX
+ Start UART receiver
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOPRX
+ Stop UART receiver
+ 0x004
+ write-only
+
+
+ TASKS_STOPRX
+ Stop UART receiver
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTTX
+ Start UART transmitter
+ 0x008
+ write-only
+
+
+ TASKS_STARTTX
+ Start UART transmitter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOPTX
+ Stop UART transmitter
+ 0x00C
+ write-only
+
+
+ TASKS_STOPTX
+ Stop UART transmitter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_FLUSHRX
+ Flush RX FIFO into RX buffer
+ 0x02C
+ write-only
+
+
+ TASKS_FLUSHRX
+ Flush RX FIFO into RX buffer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_CTS
+ CTS is activated (set low). Clear To Send.
+ 0x100
+ read-write
+
+
+ EVENTS_CTS
+ CTS is activated (set low). Clear To Send.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_NCTS
+ CTS is deactivated (set high). Not Clear To Send.
+ 0x104
+ read-write
+
+
+ EVENTS_NCTS
+ CTS is deactivated (set high). Not Clear To Send.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXDRDY
+ Data received in RXD (but potentially not yet transferred to Data RAM)
+ 0x108
+ read-write
+
+
+ EVENTS_RXDRDY
+ Data received in RXD (but potentially not yet transferred to Data RAM)
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDRX
+ Receive buffer is filled up
+ 0x110
+ read-write
+
+
+ EVENTS_ENDRX
+ Receive buffer is filled up
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXDRDY
+ Data sent from TXD
+ 0x11C
+ read-write
+
+
+ EVENTS_TXDRDY
+ Data sent from TXD
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDTX
+ Last TX byte transmitted
+ 0x120
+ read-write
+
+
+ EVENTS_ENDTX
+ Last TX byte transmitted
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ Error detected
+ 0x124
+ read-write
+
+
+ EVENTS_ERROR
+ Error detected
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXTO
+ Receiver timeout
+ 0x144
+ read-write
+
+
+ EVENTS_RXTO
+ Receiver timeout
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXSTARTED
+ UART receiver has started
+ 0x14C
+ read-write
+
+
+ EVENTS_RXSTARTED
+ UART receiver has started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXSTARTED
+ UART transmitter has started
+ 0x150
+ read-write
+
+
+ EVENTS_TXSTARTED
+ UART transmitter has started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXSTOPPED
+ Transmitter stopped
+ 0x158
+ read-write
+
+
+ EVENTS_TXSTOPPED
+ Transmitter stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ ENDRX_STARTRX
+ Shortcut between event ENDRX and task STARTRX
+ 5
+ 5
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ ENDRX_STOPRX
+ Shortcut between event ENDRX and task STOPRX
+ 6
+ 6
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ CTS
+ Enable or disable interrupt for event CTS
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ NCTS
+ Enable or disable interrupt for event NCTS
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXDRDY
+ Enable or disable interrupt for event RXDRDY
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDRX
+ Enable or disable interrupt for event ENDRX
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXDRDY
+ Enable or disable interrupt for event TXDRDY
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDTX
+ Enable or disable interrupt for event ENDTX
+ 8
+ 8
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Enable or disable interrupt for event ERROR
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXTO
+ Enable or disable interrupt for event RXTO
+ 17
+ 17
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Enable or disable interrupt for event RXSTARTED
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Enable or disable interrupt for event TXSTARTED
+ 20
+ 20
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXSTOPPED
+ Enable or disable interrupt for event TXSTOPPED
+ 22
+ 22
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ CTS
+ Write '1' to enable interrupt for event CTS
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ NCTS
+ Write '1' to enable interrupt for event NCTS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXDRDY
+ Write '1' to enable interrupt for event RXDRDY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to enable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXDRDY
+ Write '1' to enable interrupt for event TXDRDY
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDTX
+ Write '1' to enable interrupt for event ENDTX
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXTO
+ Write '1' to enable interrupt for event RXTO
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to enable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to enable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXSTOPPED
+ Write '1' to enable interrupt for event TXSTOPPED
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ CTS
+ Write '1' to disable interrupt for event CTS
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ NCTS
+ Write '1' to disable interrupt for event NCTS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXDRDY
+ Write '1' to disable interrupt for event RXDRDY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to disable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXDRDY
+ Write '1' to disable interrupt for event TXDRDY
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDTX
+ Write '1' to disable interrupt for event ENDTX
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXTO
+ Write '1' to disable interrupt for event RXTO
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to disable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to disable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXSTOPPED
+ Write '1' to disable interrupt for event TXSTOPPED
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSRC
+ Error source Note : this register is read / write one to clear.
+ 0x480
+ read-write
+ oneToClear
+
+
+ OVERRUN
+ Overrun error
+ 0
+ 0
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ PARITY
+ Parity error
+ 1
+ 1
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ FRAMING
+ Framing error occurred
+ 2
+ 2
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ BREAK
+ Break condition
+ 3
+ 3
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable UART
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable UARTE
+ 0
+ 3
+
+
+ Disabled
+ Disable UARTE
+ 0
+
+
+ Enabled
+ Enable UARTE
+ 8
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ UARTE_PSEL
+ read-write
+ 0x508
+
+ RTS
+ Pin select for RTS signal
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ TXD
+ Pin select for TXD signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ CTS
+ Pin select for CTS signal
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ RXD
+ Pin select for RXD signal
+ 0x00C
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ BAUDRATE
+ Baud rate. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ BAUDRATE
+ Baud rate
+ 0
+ 31
+
+
+ Baud1200
+ 1200 baud (actual rate: 1205)
+ 0x0004F000
+
+
+ Baud2400
+ 2400 baud (actual rate: 2396)
+ 0x0009D000
+
+
+ Baud4800
+ 4800 baud (actual rate: 4808)
+ 0x0013B000
+
+
+ Baud9600
+ 9600 baud (actual rate: 9598)
+ 0x00275000
+
+
+ Baud14400
+ 14400 baud (actual rate: 14401)
+ 0x003AF000
+
+
+ Baud19200
+ 19200 baud (actual rate: 19208)
+ 0x004EA000
+
+
+ Baud28800
+ 28800 baud (actual rate: 28777)
+ 0x0075C000
+
+
+ Baud31250
+ 31250 baud
+ 0x00800000
+
+
+ Baud38400
+ 38400 baud (actual rate: 38369)
+ 0x009D0000
+
+
+ Baud56000
+ 56000 baud (actual rate: 55944)
+ 0x00E50000
+
+
+ Baud57600
+ 57600 baud (actual rate: 57554)
+ 0x00EB0000
+
+
+ Baud76800
+ 76800 baud (actual rate: 76923)
+ 0x013A9000
+
+
+ Baud115200
+ 115200 baud (actual rate: 115108)
+ 0x01D60000
+
+
+ Baud230400
+ 230400 baud (actual rate: 231884)
+ 0x03B00000
+
+
+ Baud250000
+ 250000 baud
+ 0x04000000
+
+
+ Baud460800
+ 460800 baud (actual rate: 457143)
+ 0x07400000
+
+
+ Baud921600
+ 921600 baud (actual rate: 941176)
+ 0x0F000000
+
+
+ Baud1M
+ 1Mega baud
+ 0x10000000
+
+
+
+
+
+
+ RXD
+ RXD EasyDMA channel
+ UARTE_RXD
+ read-write
+ 0x534
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0
+ 9
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 9
+
+
+
+
+
+ TXD
+ TXD EasyDMA channel
+ UARTE_TXD
+ read-write
+ 0x544
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0
+ 9
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 9
+
+
+
+
+
+ CONFIG
+ Configuration of parity and hardware flow control
+ 0x56C
+ read-write
+
+
+ HWFC
+ Hardware flow control
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ PARITY
+ Parity
+ 1
+ 3
+
+
+ Excluded
+ Exclude parity bit
+ 0x0
+
+
+ Included
+ Include even parity bit
+ 0x7
+
+
+
+
+ STOP
+ Stop bits
+ 4
+ 4
+
+
+ One
+ One stop bit
+ 0
+
+
+ Two
+ Two stop bits
+ 1
+
+
+
+
+
+
+
+
+ TWI0
+ I2C compatible Two-Wire Interface
+ 0x40003000
+ TWI
+
+ 0
+ 0x1000
+ registers
+
+
+ TWIM0_TWIS0_TWI0
+ 3
+
+ TWI
+ 0x20
+
+
+ TASKS_STARTRX
+ Start TWI receive sequence
+ 0x000
+ write-only
+
+
+ TASKS_STARTRX
+ Start TWI receive sequence
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTTX
+ Start TWI transmit sequence
+ 0x008
+ write-only
+
+
+ TASKS_STARTTX
+ Start TWI transmit sequence
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop TWI transaction
+ 0x014
+ write-only
+
+
+ TASKS_STOP
+ Stop TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0x01C
+ write-only
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0x020
+ write-only
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0x104
+ read-write
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXDREADY
+ TWI RXD byte received
+ 0x108
+ read-write
+
+
+ EVENTS_RXDREADY
+ TWI RXD byte received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXDSENT
+ TWI TXD byte sent
+ 0x11C
+ read-write
+
+
+ EVENTS_TXDSENT
+ TWI TXD byte sent
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ TWI error
+ 0x124
+ read-write
+
+
+ EVENTS_ERROR
+ TWI error
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_BB
+ TWI byte boundary, generated before each byte that is sent or received
+ 0x138
+ read-write
+
+
+ EVENTS_BB
+ TWI byte boundary, generated before each byte that is sent or received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_SUSPENDED
+ TWI entered the suspended state
+ 0x148
+ read-write
+
+
+ EVENTS_SUSPENDED
+ TWI entered the suspended state
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ BB_SUSPEND
+ Shortcut between event BB and task SUSPEND
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ BB_STOP
+ Shortcut between event BB and task STOP
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXDREADY
+ Write '1' to enable interrupt for event RXDREADY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXDSENT
+ Write '1' to enable interrupt for event TXDSENT
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ BB
+ Write '1' to enable interrupt for event BB
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SUSPENDED
+ Write '1' to enable interrupt for event SUSPENDED
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXDREADY
+ Write '1' to disable interrupt for event RXDREADY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXDSENT
+ Write '1' to disable interrupt for event TXDSENT
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ BB
+ Write '1' to disable interrupt for event BB
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SUSPENDED
+ Write '1' to disable interrupt for event SUSPENDED
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSRC
+ Error source
+ 0x4C4
+ read-write
+ oneToClear
+
+
+ OVERRUN
+ Overrun error
+ 0
+ 0
+
+ read
+
+ NotPresent
+ Read: no overrun occured
+ 0
+
+
+ Present
+ Read: overrun occured
+ 1
+
+
+
+
+ ANACK
+ NACK received after sending the address (write '1' to clear)
+ 1
+ 1
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ DNACK
+ NACK received after sending a data byte (write '1' to clear)
+ 2
+ 2
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable TWI
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable TWI
+ 0
+ 3
+
+
+ Disabled
+ Disable TWI
+ 0
+
+
+ Enabled
+ Enable TWI
+ 5
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ TWI_PSEL
+ read-write
+ 0x508
+
+ SCL
+ Pin select for SCL
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ SDA
+ Pin select for SDA
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ RXD
+ RXD register
+ 0x518
+ read-only
+ modifyExternal
+
+
+ RXD
+ RXD register
+ 0
+ 7
+
+
+
+
+ TXD
+ TXD register
+ 0x51C
+ read-write
+
+
+ TXD
+ TXD register
+ 0
+ 7
+
+
+
+
+ FREQUENCY
+ TWI frequency. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ FREQUENCY
+ TWI master clock frequency
+ 0
+ 31
+
+
+ K100
+ 100 kbps
+ 0x01980000
+
+
+ K250
+ 250 kbps
+ 0x04000000
+
+
+ K400
+ 400 kbps (actual rate 410.256 kbps)
+ 0x06680000
+
+
+
+
+
+
+ ADDRESS
+ Address used in the TWI transfer
+ 0x588
+ read-write
+
+
+ ADDRESS
+ Address used in the TWI transfer
+ 0
+ 6
+
+
+
+
+
+
+ TWIM0
+ I2C compatible Two-Wire Master Interface with EasyDMA
+ 0x40003000
+ TWI0
+ TWIM
+
+ 0
+ 0x1000
+ registers
+
+
+ TWIM0_TWIS0_TWI0
+ 3
+
+ TWIM
+ 0x20
+
+
+ TASKS_STARTRX
+ Start TWI receive sequence
+ 0x000
+ write-only
+
+
+ TASKS_STARTRX
+ Start TWI receive sequence
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTTX
+ Start TWI transmit sequence
+ 0x008
+ write-only
+
+
+ TASKS_STARTTX
+ Start TWI transmit sequence
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop TWI transaction. Must be issued while the TWI master is not suspended.
+ 0x014
+ write-only
+
+
+ TASKS_STOP
+ Stop TWI transaction. Must be issued while the TWI master is not suspended.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0x01C
+ write-only
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0x020
+ write-only
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0x104
+ read-write
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ TWI error
+ 0x124
+ read-write
+
+
+ EVENTS_ERROR
+ TWI error
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_SUSPENDED
+ Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
+ 0x148
+ read-write
+
+
+ EVENTS_SUSPENDED
+ Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXSTARTED
+ Receive sequence started
+ 0x14C
+ read-write
+
+
+ EVENTS_RXSTARTED
+ Receive sequence started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXSTARTED
+ Transmit sequence started
+ 0x150
+ read-write
+
+
+ EVENTS_TXSTARTED
+ Transmit sequence started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_LASTRX
+ Byte boundary, starting to receive the last byte
+ 0x15C
+ read-write
+
+
+ EVENTS_LASTRX
+ Byte boundary, starting to receive the last byte
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_LASTTX
+ Byte boundary, starting to transmit the last byte
+ 0x160
+ read-write
+
+
+ EVENTS_LASTTX
+ Byte boundary, starting to transmit the last byte
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ LASTTX_STARTRX
+ Shortcut between event LASTTX and task STARTRX
+ 7
+ 7
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LASTTX_SUSPEND
+ Shortcut between event LASTTX and task SUSPEND
+ 8
+ 8
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LASTTX_STOP
+ Shortcut between event LASTTX and task STOP
+ 9
+ 9
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LASTRX_STARTTX
+ Shortcut between event LASTRX and task STARTTX
+ 10
+ 10
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LASTRX_SUSPEND
+ Shortcut between event LASTRX and task SUSPEND
+ 11
+ 11
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LASTRX_STOP
+ Shortcut between event LASTRX and task STOP
+ 12
+ 12
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ STOPPED
+ Enable or disable interrupt for event STOPPED
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Enable or disable interrupt for event ERROR
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ SUSPENDED
+ Enable or disable interrupt for event SUSPENDED
+ 18
+ 18
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Enable or disable interrupt for event RXSTARTED
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Enable or disable interrupt for event TXSTARTED
+ 20
+ 20
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ LASTRX
+ Enable or disable interrupt for event LASTRX
+ 23
+ 23
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ LASTTX
+ Enable or disable interrupt for event LASTTX
+ 24
+ 24
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SUSPENDED
+ Write '1' to enable interrupt for event SUSPENDED
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to enable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to enable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ LASTRX
+ Write '1' to enable interrupt for event LASTRX
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ LASTTX
+ Write '1' to enable interrupt for event LASTTX
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SUSPENDED
+ Write '1' to disable interrupt for event SUSPENDED
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to disable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to disable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ LASTRX
+ Write '1' to disable interrupt for event LASTRX
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ LASTTX
+ Write '1' to disable interrupt for event LASTTX
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSRC
+ Error source
+ 0x4C4
+ read-write
+ oneToClear
+
+
+ OVERRUN
+ Overrun error
+ 0
+ 0
+
+
+ NotReceived
+ Error did not occur
+ 0
+
+
+ Received
+ Error occurred
+ 1
+
+
+
+
+ ANACK
+ NACK received after sending the address (write '1' to clear)
+ 1
+ 1
+
+
+ NotReceived
+ Error did not occur
+ 0
+
+
+ Received
+ Error occurred
+ 1
+
+
+
+
+ DNACK
+ NACK received after sending a data byte (write '1' to clear)
+ 2
+ 2
+
+
+ NotReceived
+ Error did not occur
+ 0
+
+
+ Received
+ Error occurred
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable TWIM
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable TWIM
+ 0
+ 3
+
+
+ Disabled
+ Disable TWIM
+ 0
+
+
+ Enabled
+ Enable TWIM
+ 6
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ TWIM_PSEL
+ read-write
+ 0x508
+
+ SCL
+ Pin select for SCL signal
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ SDA
+ Pin select for SDA signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ FREQUENCY
+ TWI frequency. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ FREQUENCY
+ TWI master clock frequency
+ 0
+ 31
+
+
+ K100
+ 100 kbps
+ 0x01980000
+
+
+ K250
+ 250 kbps
+ 0x04000000
+
+
+ K400
+ 400 kbps
+ 0x06400000
+
+
+
+
+
+
+ RXD
+ RXD EasyDMA channel
+ TWIM_RXD
+ read-write
+ 0x534
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0
+ 13
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte.
+ 0
+ 13
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 2
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ TXD
+ TXD EasyDMA channel
+ TWIM_TXD
+ read-write
+ 0x544
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0
+ 13
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte.
+ 0
+ 13
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 2
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ ADDRESS
+ Address used in the TWI transfer
+ 0x588
+ read-write
+
+
+ ADDRESS
+ Address used in the TWI transfer
+ 0
+ 6
+
+
+
+
+
+
+ TWIS0
+ I2C compatible Two-Wire Slave Interface with EasyDMA
+ 0x40003000
+ TWI0
+ TWIS
+
+ 0
+ 0x1000
+ registers
+
+
+ TWIM0_TWIS0_TWI0
+ 3
+
+ TWIS
+ 0x20
+
+
+ TASKS_STOP
+ Stop TWI transaction
+ 0x014
+ write-only
+
+
+ TASKS_STOP
+ Stop TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0x01C
+ write-only
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0x020
+ write-only
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_PREPARERX
+ Prepare the TWI slave to respond to a write command
+ 0x030
+ write-only
+
+
+ TASKS_PREPARERX
+ Prepare the TWI slave to respond to a write command
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_PREPARETX
+ Prepare the TWI slave to respond to a read command
+ 0x034
+ write-only
+
+
+ TASKS_PREPARETX
+ Prepare the TWI slave to respond to a read command
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0x104
+ read-write
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ TWI error
+ 0x124
+ read-write
+
+
+ EVENTS_ERROR
+ TWI error
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXSTARTED
+ Receive sequence started
+ 0x14C
+ read-write
+
+
+ EVENTS_RXSTARTED
+ Receive sequence started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXSTARTED
+ Transmit sequence started
+ 0x150
+ read-write
+
+
+ EVENTS_TXSTARTED
+ Transmit sequence started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_WRITE
+ Write command received
+ 0x164
+ read-write
+
+
+ EVENTS_WRITE
+ Write command received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_READ
+ Read command received
+ 0x168
+ read-write
+
+
+ EVENTS_READ
+ Read command received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ WRITE_SUSPEND
+ Shortcut between event WRITE and task SUSPEND
+ 13
+ 13
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ READ_SUSPEND
+ Shortcut between event READ and task SUSPEND
+ 14
+ 14
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ STOPPED
+ Enable or disable interrupt for event STOPPED
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Enable or disable interrupt for event ERROR
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Enable or disable interrupt for event RXSTARTED
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Enable or disable interrupt for event TXSTARTED
+ 20
+ 20
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ WRITE
+ Enable or disable interrupt for event WRITE
+ 25
+ 25
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ READ
+ Enable or disable interrupt for event READ
+ 26
+ 26
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to enable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to enable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ WRITE
+ Write '1' to enable interrupt for event WRITE
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ READ
+ Write '1' to enable interrupt for event READ
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to disable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to disable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ WRITE
+ Write '1' to disable interrupt for event WRITE
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ READ
+ Write '1' to disable interrupt for event READ
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSRC
+ Error source
+ 0x4D0
+ read-write
+ oneToClear
+
+
+ OVERFLOW
+ RX buffer overflow detected, and prevented
+ 0
+ 0
+
+
+ NotDetected
+ Error did not occur
+ 0
+
+
+ Detected
+ Error occurred
+ 1
+
+
+
+
+ DNACK
+ NACK sent after receiving a data byte
+ 2
+ 2
+
+
+ NotReceived
+ Error did not occur
+ 0
+
+
+ Received
+ Error occurred
+ 1
+
+
+
+
+ OVERREAD
+ TX buffer over-read detected, and prevented
+ 3
+ 3
+
+
+ NotDetected
+ Error did not occur
+ 0
+
+
+ Detected
+ Error occurred
+ 1
+
+
+
+
+
+
+ MATCH
+ Status register indicating which address had a match
+ 0x4D4
+ read-only
+
+
+ MATCH
+ Which of the addresses in {ADDRESS} matched the incoming address
+ 0
+ 0
+
+
+
+
+ ENABLE
+ Enable TWIS
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable TWIS
+ 0
+ 3
+
+
+ Disabled
+ Disable TWIS
+ 0
+
+
+ Enabled
+ Enable TWIS
+ 9
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ TWIS_PSEL
+ read-write
+ 0x508
+
+ SCL
+ Pin select for SCL signal
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ SDA
+ Pin select for SDA signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ RXD
+ RXD EasyDMA channel
+ TWIS_RXD
+ read-write
+ 0x534
+
+ PTR
+ RXD Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ RXD Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in RXD buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in RXD buffer
+ 0
+ 13
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last RXD transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last RXD transaction
+ 0
+ 13
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ TXD
+ TXD EasyDMA channel
+ TWIS_TXD
+ read-write
+ 0x544
+
+ PTR
+ TXD Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ TXD Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in TXD buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in TXD buffer
+ 0
+ 13
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last TXD transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last TXD transaction
+ 0
+ 13
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ 0x2
+ 0x4
+ ADDRESS[%s]
+ Description collection: TWI slave address n
+ 0x588
+ read-write
+
+
+ ADDRESS
+ TWI slave address
+ 0
+ 6
+
+
+
+
+ CONFIG
+ Configuration register for the address match mechanism
+ 0x594
+ read-write
+ 0x00000001
+
+
+ ADDRESS0
+ Enable or disable address matching on ADDRESS[0]
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ADDRESS1
+ Enable or disable address matching on ADDRESS[1]
+ 1
+ 1
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+
+
+ ORC
+ Over-read character. Character sent out in case of an over-read of the transmit buffer.
+ 0x5C0
+ read-write
+
+
+ ORC
+ Over-read character. Character sent out in case of an over-read of the transmit buffer.
+ 0
+ 7
+
+
+
+
+
+
+ SPI0
+ Serial Peripheral Interface
+ 0x40004000
+ SPI
+
+ 0
+ 0x1000
+ registers
+
+
+ SPIM0_SPIS0_SPI0
+ 4
+
+ SPI
+ 0x20
+
+
+ EVENTS_READY
+ TXD byte sent and RXD byte received
+ 0x108
+ read-write
+
+
+ EVENTS_READY
+ TXD byte sent and RXD byte received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ READY
+ Write '1' to enable interrupt for event READY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ READY
+ Write '1' to disable interrupt for event READY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable SPI
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable SPI
+ 0
+ 3
+
+
+ Disabled
+ Disable SPI
+ 0
+
+
+ Enabled
+ Enable SPI
+ 1
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ SPI_PSEL
+ read-write
+ 0x508
+
+ SCK
+ Pin select for SCK
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MOSI
+ Pin select for MOSI signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MISO
+ Pin select for MISO signal
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ RXD
+ RXD register
+ 0x518
+ read-only
+ modifyExternal
+
+
+ RXD
+ RX data received. Double buffered
+ 0
+ 7
+
+
+
+
+ TXD
+ TXD register
+ 0x51C
+ read-write
+
+
+ TXD
+ TX data to send. Double buffered
+ 0
+ 7
+
+
+
+
+ FREQUENCY
+ SPI frequency. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ FREQUENCY
+ SPI master data rate
+ 0
+ 31
+
+
+ K125
+ 125 kbps
+ 0x02000000
+
+
+ K250
+ 250 kbps
+ 0x04000000
+
+
+ K500
+ 500 kbps
+ 0x08000000
+
+
+ M1
+ 1 Mbps
+ 0x10000000
+
+
+ M2
+ 2 Mbps
+ 0x20000000
+
+
+ M4
+ 4 Mbps
+ 0x40000000
+
+
+ M8
+ 8 Mbps
+ 0x80000000
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x554
+ read-write
+
+
+ ORDER
+ Bit order
+ 0
+ 0
+
+
+ MsbFirst
+ Most significant bit shifted out first
+ 0
+
+
+ LsbFirst
+ Least significant bit shifted out first
+ 1
+
+
+
+
+ CPHA
+ Serial clock (SCK) phase
+ 1
+ 1
+
+
+ Leading
+ Sample on leading edge of clock, shift serial data on trailing edge
+ 0
+
+
+ Trailing
+ Sample on trailing edge of clock, shift serial data on leading edge
+ 1
+
+
+
+
+ CPOL
+ Serial clock (SCK) polarity
+ 2
+ 2
+
+
+ ActiveHigh
+ Active high
+ 0
+
+
+ ActiveLow
+ Active low
+ 1
+
+
+
+
+
+
+
+
+ SPIM0
+ Serial Peripheral Interface Master with EasyDMA
+ 0x40004000
+ SPI0
+ SPIM
+
+ 0
+ 0x1000
+ registers
+
+
+ SPIM0_SPIS0_SPI0
+ 4
+
+ SPIM
+ 0x20
+
+
+ TASKS_START
+ Start SPI transaction
+ 0x010
+ write-only
+
+
+ TASKS_START
+ Start SPI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop SPI transaction
+ 0x014
+ write-only
+
+
+ TASKS_STOP
+ Stop SPI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SUSPEND
+ Suspend SPI transaction
+ 0x01C
+ write-only
+
+
+ TASKS_SUSPEND
+ Suspend SPI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RESUME
+ Resume SPI transaction
+ 0x020
+ write-only
+
+
+ TASKS_RESUME
+ Resume SPI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ SPI transaction has stopped
+ 0x104
+ read-write
+
+
+ EVENTS_STOPPED
+ SPI transaction has stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDRX
+ End of RXD buffer reached
+ 0x110
+ read-write
+
+
+ EVENTS_ENDRX
+ End of RXD buffer reached
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ End of RXD buffer and TXD buffer reached
+ 0x118
+ read-write
+
+
+ EVENTS_END
+ End of RXD buffer and TXD buffer reached
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDTX
+ End of TXD buffer reached
+ 0x120
+ read-write
+
+
+ EVENTS_ENDTX
+ End of TXD buffer reached
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_STARTED
+ Transaction started
+ 0x14C
+ read-write
+
+
+ EVENTS_STARTED
+ Transaction started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ END_START
+ Shortcut between event END and task START
+ 17
+ 17
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to enable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDTX
+ Write '1' to enable interrupt for event ENDTX
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ STARTED
+ Write '1' to enable interrupt for event STARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to disable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDTX
+ Write '1' to disable interrupt for event ENDTX
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ STARTED
+ Write '1' to disable interrupt for event STARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable SPIM
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable SPIM
+ 0
+ 3
+
+
+ Disabled
+ Disable SPIM
+ 0
+
+
+ Enabled
+ Enable SPIM
+ 7
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ SPIM_PSEL
+ read-write
+ 0x508
+
+ SCK
+ Pin select for SCK
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MOSI
+ Pin select for MOSI signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MISO
+ Pin select for MISO signal
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ FREQUENCY
+ SPI frequency. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ FREQUENCY
+ SPI master data rate
+ 0
+ 31
+
+
+ K125
+ 125 kbps
+ 0x02000000
+
+
+ K250
+ 250 kbps
+ 0x04000000
+
+
+ K500
+ 500 kbps
+ 0x08000000
+
+
+ M1
+ 1 Mbps
+ 0x10000000
+
+
+ M2
+ 2 Mbps
+ 0x20000000
+
+
+ M4
+ 4 Mbps
+ 0x40000000
+
+
+ M8
+ 8 Mbps
+ 0x80000000
+
+
+
+
+
+
+ RXD
+ RXD EasyDMA channel
+ SPIM_RXD
+ read-write
+ 0x534
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0
+ 13
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 13
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ TXD
+ TXD EasyDMA channel
+ SPIM_TXD
+ read-write
+ 0x544
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0
+ 13
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 13
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x554
+ read-write
+
+
+ ORDER
+ Bit order
+ 0
+ 0
+
+
+ MsbFirst
+ Most significant bit shifted out first
+ 0
+
+
+ LsbFirst
+ Least significant bit shifted out first
+ 1
+
+
+
+
+ CPHA
+ Serial clock (SCK) phase
+ 1
+ 1
+
+
+ Leading
+ Sample on leading edge of clock, shift serial data on trailing edge
+ 0
+
+
+ Trailing
+ Sample on trailing edge of clock, shift serial data on leading edge
+ 1
+
+
+
+
+ CPOL
+ Serial clock (SCK) polarity
+ 2
+ 2
+
+
+ ActiveHigh
+ Active high
+ 0
+
+
+ ActiveLow
+ Active low
+ 1
+
+
+
+
+
+
+ ORC
+ Over-read character. Character clocked out in case and over-read of the TXD buffer.
+ 0x5C0
+ read-write
+
+
+ ORC
+ Over-read character. Character clocked out in case and over-read of the TXD buffer.
+ 0
+ 7
+
+
+
+
+
+
+ SPIS0
+ SPI Slave
+ 0x40004000
+ SPI0
+ SPIS
+
+ 0
+ 0x1000
+ registers
+
+
+ SPIM0_SPIS0_SPI0
+ 4
+
+ SPIS
+ 0x20
+
+
+ TASKS_ACQUIRE
+ Acquire SPI semaphore
+ 0x024
+ write-only
+
+
+ TASKS_ACQUIRE
+ Acquire SPI semaphore
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RELEASE
+ Release SPI semaphore, enabling the SPI slave to acquire it
+ 0x028
+ write-only
+
+
+ TASKS_RELEASE
+ Release SPI semaphore, enabling the SPI slave to acquire it
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ Granted transaction completed
+ 0x104
+ read-write
+
+
+ EVENTS_END
+ Granted transaction completed
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDRX
+ End of RXD buffer reached
+ 0x110
+ read-write
+
+
+ EVENTS_ENDRX
+ End of RXD buffer reached
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ACQUIRED
+ Semaphore acquired
+ 0x128
+ read-write
+
+
+ EVENTS_ACQUIRED
+ Semaphore acquired
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ END_ACQUIRE
+ Shortcut between event END and task ACQUIRE
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to enable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ACQUIRED
+ Write '1' to enable interrupt for event ACQUIRED
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to disable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ACQUIRED
+ Write '1' to disable interrupt for event ACQUIRED
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ SEMSTAT
+ Semaphore status register
+ 0x400
+ read-only
+ 0x00000001
+
+
+ SEMSTAT
+ Semaphore status
+ 0
+ 1
+
+
+ Free
+ Semaphore is free
+ 0
+
+
+ CPU
+ Semaphore is assigned to CPU
+ 1
+
+
+ SPIS
+ Semaphore is assigned to SPI slave
+ 2
+
+
+ CPUPending
+ Semaphore is assigned to SPI but a handover to the CPU is pending
+ 3
+
+
+
+
+
+
+ STATUS
+ Status from last transaction
+ 0x440
+ read-write
+
+
+ OVERREAD
+ TX buffer over-read detected, and prevented
+ 0
+ 0
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+ write
+
+ Clear
+ Write: clear error on writing '1'
+ 1
+
+
+
+
+ OVERFLOW
+ RX buffer overflow detected, and prevented
+ 1
+ 1
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+ write
+
+ Clear
+ Write: clear error on writing '1'
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable SPI slave
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable SPI slave
+ 0
+ 3
+
+
+ Disabled
+ Disable SPI slave
+ 0
+
+
+ Enabled
+ Enable SPI slave
+ 2
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ SPIS_PSEL
+ read-write
+ 0x508
+
+ SCK
+ Pin select for SCK
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MISO
+ Pin select for MISO signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MOSI
+ Pin select for MOSI signal
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ CSN
+ Pin select for CSN signal
+ 0x00C
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ RXD
+ Unspecified
+ SPIS_RXD
+ read-write
+ 0x534
+
+ PTR
+ RXD data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ RXD data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0
+ 13
+
+
+
+
+ AMOUNT
+ Number of bytes received in last granted transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes received in the last granted transaction
+ 0
+ 13
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ TXD
+ Unspecified
+ SPIS_TXD
+ read-write
+ 0x544
+
+ PTR
+ TXD data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ TXD data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0
+ 13
+
+
+
+
+ AMOUNT
+ Number of bytes transmitted in last granted transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transmitted in last granted transaction
+ 0
+ 13
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x554
+ read-write
+
+
+ ORDER
+ Bit order
+ 0
+ 0
+
+
+ MsbFirst
+ Most significant bit shifted out first
+ 0
+
+
+ LsbFirst
+ Least significant bit shifted out first
+ 1
+
+
+
+
+ CPHA
+ Serial clock (SCK) phase
+ 1
+ 1
+
+
+ Leading
+ Sample on leading edge of clock, shift serial data on trailing edge
+ 0
+
+
+ Trailing
+ Sample on trailing edge of clock, shift serial data on leading edge
+ 1
+
+
+
+
+ CPOL
+ Serial clock (SCK) polarity
+ 2
+ 2
+
+
+ ActiveHigh
+ Active high
+ 0
+
+
+ ActiveLow
+ Active low
+ 1
+
+
+
+
+
+
+ DEF
+ Default character. Character clocked out in case of an ignored transaction.
+ 0x55C
+ read-write
+
+
+ DEF
+ Default character. Character clocked out in case of an ignored transaction.
+ 0
+ 7
+
+
+
+
+ ORC
+ Over-read character
+ 0x5C0
+ read-write
+
+
+ ORC
+ Over-read character. Character clocked out after an over-read of the transmit buffer.
+ 0
+ 7
+
+
+
+
+
+
+ GPIOTE
+ GPIO Tasks and Events
+ 0x40006000
+
+ 0
+ 0x1000
+ registers
+
+
+ GPIOTE
+ 6
+
+ GPIOTE
+ 0x20
+
+
+ 0x8
+ 0x4
+ TASKS_OUT[%s]
+ Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
+ 0x000
+ write-only
+
+
+ TASKS_OUT
+ Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ TASKS_SET[%s]
+ Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
+ 0x030
+ write-only
+
+
+ TASKS_SET
+ Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ TASKS_CLR[%s]
+ Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
+ 0x060
+ write-only
+
+
+ TASKS_CLR
+ Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ EVENTS_IN[%s]
+ Description collection: Event generated from pin specified in CONFIG[n].PSEL
+ 0x100
+ read-write
+
+
+ EVENTS_IN
+ Event generated from pin specified in CONFIG[n].PSEL
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_PORT
+ Event generated from multiple input GPIO pins with SENSE mechanism enabled
+ 0x17C
+ read-write
+
+
+ EVENTS_PORT
+ Event generated from multiple input GPIO pins with SENSE mechanism enabled
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ IN0
+ Write '1' to enable interrupt for event IN[0]
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN1
+ Write '1' to enable interrupt for event IN[1]
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN2
+ Write '1' to enable interrupt for event IN[2]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN3
+ Write '1' to enable interrupt for event IN[3]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN4
+ Write '1' to enable interrupt for event IN[4]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN5
+ Write '1' to enable interrupt for event IN[5]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN6
+ Write '1' to enable interrupt for event IN[6]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN7
+ Write '1' to enable interrupt for event IN[7]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PORT
+ Write '1' to enable interrupt for event PORT
+ 31
+ 31
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ IN0
+ Write '1' to disable interrupt for event IN[0]
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN1
+ Write '1' to disable interrupt for event IN[1]
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN2
+ Write '1' to disable interrupt for event IN[2]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN3
+ Write '1' to disable interrupt for event IN[3]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN4
+ Write '1' to disable interrupt for event IN[4]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN5
+ Write '1' to disable interrupt for event IN[5]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN6
+ Write '1' to disable interrupt for event IN[6]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN7
+ Write '1' to disable interrupt for event IN[7]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PORT
+ Write '1' to disable interrupt for event PORT
+ 31
+ 31
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ CONFIG[%s]
+ Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
+ 0x510
+ read-write
+
+
+ MODE
+ Mode
+ 0
+ 1
+
+
+ Disabled
+ Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.
+ 0
+
+
+ Event
+ Event mode
+ 1
+
+
+ Task
+ Task mode
+ 3
+
+
+
+
+ PSEL
+ GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event
+ 8
+ 12
+
+
+ POLARITY
+ When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
+ 16
+ 17
+
+
+ None
+ Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.
+ 0
+
+
+ LoToHi
+ Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.
+ 1
+
+
+ HiToLo
+ Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.
+ 2
+
+
+ Toggle
+ Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.
+ 3
+
+
+
+
+ OUTINIT
+ When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
+ 20
+ 20
+
+
+ Low
+ Task mode: Initial value of pin before task triggering is low
+ 0
+
+
+ High
+ Task mode: Initial value of pin before task triggering is high
+ 1
+
+
+
+
+
+
+
+
+ SAADC
+ Analog to Digital Converter
+ 0x40007000
+
+ 0
+ 0x1000
+ registers
+
+
+ SAADC
+ 7
+
+ SAADC
+ 0x20
+
+
+ TASKS_START
+ Start the ADC and prepare the result buffer in RAM
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start the ADC and prepare the result buffer in RAM
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SAMPLE
+ Take one ADC sample, if scan is enabled all channels are sampled
+ 0x004
+ write-only
+
+
+ TASKS_SAMPLE
+ Take one ADC sample, if scan is enabled all channels are sampled
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop the ADC and terminate any on-going conversion
+ 0x008
+ write-only
+
+
+ TASKS_STOP
+ Stop the ADC and terminate any on-going conversion
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CALIBRATEOFFSET
+ Starts offset auto-calibration
+ 0x00C
+ write-only
+
+
+ TASKS_CALIBRATEOFFSET
+ Starts offset auto-calibration
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STARTED
+ The ADC has started
+ 0x100
+ read-write
+
+
+ EVENTS_STARTED
+ The ADC has started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ The ADC has filled up the Result buffer
+ 0x104
+ read-write
+
+
+ EVENTS_END
+ The ADC has filled up the Result buffer
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DONE
+ A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.
+ 0x108
+ read-write
+
+
+ EVENTS_DONE
+ A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RESULTDONE
+ A result is ready to get transferred to RAM.
+ 0x10C
+ read-write
+
+
+ EVENTS_RESULTDONE
+ A result is ready to get transferred to RAM.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CALIBRATEDONE
+ Calibration is complete
+ 0x110
+ read-write
+
+
+ EVENTS_CALIBRATEDONE
+ Calibration is complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ The ADC has stopped
+ 0x114
+ read-write
+
+
+ EVENTS_STOPPED
+ The ADC has stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ 8
+ 0x008
+ EVENTS_CH[%s]
+ Peripheral events.
+ SAADC_EVENTS_CH
+ read-write
+ 0x118
+
+ LIMITH
+ Description cluster: Last results is equal or above CH[n].LIMIT.HIGH
+ 0x000
+ read-write
+
+
+ LIMITH
+ Last results is equal or above CH[n].LIMIT.HIGH
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ LIMITL
+ Description cluster: Last results is equal or below CH[n].LIMIT.LOW
+ 0x004
+ read-write
+
+
+ LIMITL
+ Last results is equal or below CH[n].LIMIT.LOW
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ STARTED
+ Enable or disable interrupt for event STARTED
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ END
+ Enable or disable interrupt for event END
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ DONE
+ Enable or disable interrupt for event DONE
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RESULTDONE
+ Enable or disable interrupt for event RESULTDONE
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CALIBRATEDONE
+ Enable or disable interrupt for event CALIBRATEDONE
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ STOPPED
+ Enable or disable interrupt for event STOPPED
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH0LIMITH
+ Enable or disable interrupt for event CH0LIMITH
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH0LIMITL
+ Enable or disable interrupt for event CH0LIMITL
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH1LIMITH
+ Enable or disable interrupt for event CH1LIMITH
+ 8
+ 8
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH1LIMITL
+ Enable or disable interrupt for event CH1LIMITL
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH2LIMITH
+ Enable or disable interrupt for event CH2LIMITH
+ 10
+ 10
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH2LIMITL
+ Enable or disable interrupt for event CH2LIMITL
+ 11
+ 11
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH3LIMITH
+ Enable or disable interrupt for event CH3LIMITH
+ 12
+ 12
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH3LIMITL
+ Enable or disable interrupt for event CH3LIMITL
+ 13
+ 13
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH4LIMITH
+ Enable or disable interrupt for event CH4LIMITH
+ 14
+ 14
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH4LIMITL
+ Enable or disable interrupt for event CH4LIMITL
+ 15
+ 15
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH5LIMITH
+ Enable or disable interrupt for event CH5LIMITH
+ 16
+ 16
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH5LIMITL
+ Enable or disable interrupt for event CH5LIMITL
+ 17
+ 17
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH6LIMITH
+ Enable or disable interrupt for event CH6LIMITH
+ 18
+ 18
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH6LIMITL
+ Enable or disable interrupt for event CH6LIMITL
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH7LIMITH
+ Enable or disable interrupt for event CH7LIMITH
+ 20
+ 20
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH7LIMITL
+ Enable or disable interrupt for event CH7LIMITL
+ 21
+ 21
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STARTED
+ Write '1' to enable interrupt for event STARTED
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DONE
+ Write '1' to enable interrupt for event DONE
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RESULTDONE
+ Write '1' to enable interrupt for event RESULTDONE
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CALIBRATEDONE
+ Write '1' to enable interrupt for event CALIBRATEDONE
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH0LIMITH
+ Write '1' to enable interrupt for event CH0LIMITH
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH0LIMITL
+ Write '1' to enable interrupt for event CH0LIMITL
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH1LIMITH
+ Write '1' to enable interrupt for event CH1LIMITH
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH1LIMITL
+ Write '1' to enable interrupt for event CH1LIMITL
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH2LIMITH
+ Write '1' to enable interrupt for event CH2LIMITH
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH2LIMITL
+ Write '1' to enable interrupt for event CH2LIMITL
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH3LIMITH
+ Write '1' to enable interrupt for event CH3LIMITH
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH3LIMITL
+ Write '1' to enable interrupt for event CH3LIMITL
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH4LIMITH
+ Write '1' to enable interrupt for event CH4LIMITH
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH4LIMITL
+ Write '1' to enable interrupt for event CH4LIMITL
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH5LIMITH
+ Write '1' to enable interrupt for event CH5LIMITH
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH5LIMITL
+ Write '1' to enable interrupt for event CH5LIMITL
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH6LIMITH
+ Write '1' to enable interrupt for event CH6LIMITH
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH6LIMITL
+ Write '1' to enable interrupt for event CH6LIMITL
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH7LIMITH
+ Write '1' to enable interrupt for event CH7LIMITH
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH7LIMITL
+ Write '1' to enable interrupt for event CH7LIMITL
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STARTED
+ Write '1' to disable interrupt for event STARTED
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DONE
+ Write '1' to disable interrupt for event DONE
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RESULTDONE
+ Write '1' to disable interrupt for event RESULTDONE
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CALIBRATEDONE
+ Write '1' to disable interrupt for event CALIBRATEDONE
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH0LIMITH
+ Write '1' to disable interrupt for event CH0LIMITH
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH0LIMITL
+ Write '1' to disable interrupt for event CH0LIMITL
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH1LIMITH
+ Write '1' to disable interrupt for event CH1LIMITH
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH1LIMITL
+ Write '1' to disable interrupt for event CH1LIMITL
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH2LIMITH
+ Write '1' to disable interrupt for event CH2LIMITH
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH2LIMITL
+ Write '1' to disable interrupt for event CH2LIMITL
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH3LIMITH
+ Write '1' to disable interrupt for event CH3LIMITH
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH3LIMITL
+ Write '1' to disable interrupt for event CH3LIMITL
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH4LIMITH
+ Write '1' to disable interrupt for event CH4LIMITH
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH4LIMITL
+ Write '1' to disable interrupt for event CH4LIMITL
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH5LIMITH
+ Write '1' to disable interrupt for event CH5LIMITH
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH5LIMITL
+ Write '1' to disable interrupt for event CH5LIMITL
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH6LIMITH
+ Write '1' to disable interrupt for event CH6LIMITH
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH6LIMITL
+ Write '1' to disable interrupt for event CH6LIMITL
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH7LIMITH
+ Write '1' to disable interrupt for event CH7LIMITH
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH7LIMITL
+ Write '1' to disable interrupt for event CH7LIMITL
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ STATUS
+ Status
+ 0x400
+ read-only
+
+
+ STATUS
+ Status
+ 0
+ 0
+
+
+ Ready
+ ADC is ready. No on-going conversion.
+ 0
+
+
+ Busy
+ ADC is busy. Conversion in progress.
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable or disable ADC
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable ADC
+ 0
+ 0
+
+
+ Disabled
+ Disable ADC
+ 0
+
+
+ Enabled
+ Enable ADC
+ 1
+
+
+
+
+
+
+ 8
+ 0x010
+ CH[%s]
+ Unspecified
+ SAADC_CH
+ read-write
+ 0x510
+
+ PSELP
+ Description cluster: Input positive pin selection for CH[n]
+ 0x000
+ read-write
+ 0x00000000
+
+
+ PSELP
+ Analog positive input channel
+ 0
+ 4
+
+
+ NC
+ Not connected
+ 0
+
+
+ AnalogInput0
+ AIN0
+ 1
+
+
+ AnalogInput1
+ AIN1
+ 2
+
+
+ AnalogInput2
+ AIN2
+ 3
+
+
+ AnalogInput3
+ AIN3
+ 4
+
+
+ AnalogInput4
+ AIN4
+ 5
+
+
+ AnalogInput5
+ AIN5
+ 6
+
+
+ AnalogInput6
+ AIN6
+ 7
+
+
+ AnalogInput7
+ AIN7
+ 8
+
+
+ VDD
+ VDD
+ 9
+
+
+
+
+
+
+ PSELN
+ Description cluster: Input negative pin selection for CH[n]
+ 0x004
+ read-write
+ 0x00000000
+
+
+ PSELN
+ Analog negative input, enables differential channel
+ 0
+ 4
+
+
+ NC
+ Not connected
+ 0
+
+
+ AnalogInput0
+ AIN0
+ 1
+
+
+ AnalogInput1
+ AIN1
+ 2
+
+
+ AnalogInput2
+ AIN2
+ 3
+
+
+ AnalogInput3
+ AIN3
+ 4
+
+
+ AnalogInput4
+ AIN4
+ 5
+
+
+ AnalogInput5
+ AIN5
+ 6
+
+
+ AnalogInput6
+ AIN6
+ 7
+
+
+ AnalogInput7
+ AIN7
+ 8
+
+
+ VDD
+ VDD
+ 9
+
+
+
+
+
+
+ CONFIG
+ Description cluster: Input configuration for CH[n]
+ 0x008
+ read-write
+ 0x00020000
+
+
+ RESP
+ Positive channel resistor control
+ 0
+ 1
+
+
+ Bypass
+ Bypass resistor ladder
+ 0
+
+
+ Pulldown
+ Pull-down to GND
+ 1
+
+
+ Pullup
+ Pull-up to VDD
+ 2
+
+
+ VDD1_2
+ Set input at VDD/2
+ 3
+
+
+
+
+ RESN
+ Negative channel resistor control
+ 4
+ 5
+
+
+ Bypass
+ Bypass resistor ladder
+ 0
+
+
+ Pulldown
+ Pull-down to GND
+ 1
+
+
+ Pullup
+ Pull-up to VDD
+ 2
+
+
+ VDD1_2
+ Set input at VDD/2
+ 3
+
+
+
+
+ GAIN
+ Gain control
+ 8
+ 10
+
+
+ Gain1_6
+ 1/6
+ 0
+
+
+ Gain1_5
+ 1/5
+ 1
+
+
+ Gain1_4
+ 1/4
+ 2
+
+
+ Gain1_3
+ 1/3
+ 3
+
+
+ Gain1_2
+ 1/2
+ 4
+
+
+ Gain1
+ 1
+ 5
+
+
+ Gain2
+ 2
+ 6
+
+
+ Gain4
+ 4
+ 7
+
+
+
+
+ REFSEL
+ Reference control
+ 12
+ 12
+
+
+ Internal
+ Internal reference (0.6 V)
+ 0
+
+
+ VDD1_4
+ VDD/4 as reference
+ 1
+
+
+
+
+ TACQ
+ Acquisition time, the time the ADC uses to sample the input voltage
+ 16
+ 18
+
+
+ 3us
+ 3 us
+ 0
+
+
+ 5us
+ 5 us
+ 1
+
+
+ 10us
+ 10 us
+ 2
+
+
+ 15us
+ 15 us
+ 3
+
+
+ 20us
+ 20 us
+ 4
+
+
+ 40us
+ 40 us
+ 5
+
+
+
+
+ MODE
+ Enable differential mode
+ 20
+ 20
+
+
+ SE
+ Single ended, PSELN will be ignored, negative input to ADC shorted to GND
+ 0
+
+
+ Diff
+ Differential
+ 1
+
+
+
+
+ BURST
+ Enable burst mode
+ 24
+ 24
+
+
+ Disabled
+ Burst mode is disabled (normal operation)
+ 0
+
+
+ Enabled
+ Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.
+ 1
+
+
+
+
+
+
+ LIMIT
+ Description cluster: High/low limits for event monitoring a channel
+ 0x00C
+ read-write
+ 0x7FFF8000
+
+
+ LOW
+ Low level limit
+ 0
+ 15
+
+
+ HIGH
+ High level limit
+ 16
+ 31
+
+
+
+
+
+ RESOLUTION
+ Resolution configuration
+ 0x5F0
+ read-write
+ 0x00000001
+
+
+ VAL
+ Set the resolution
+ 0
+ 2
+
+
+ 8bit
+ 8 bit
+ 0
+
+
+ 10bit
+ 10 bit
+ 1
+
+
+ 12bit
+ 12 bit
+ 2
+
+
+ 14bit
+ 14 bit
+ 3
+
+
+
+
+
+
+ OVERSAMPLE
+ Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
+ 0x5F4
+ read-write
+
+
+ OVERSAMPLE
+ Oversample control
+ 0
+ 3
+
+
+ Bypass
+ Bypass oversampling
+ 0
+
+
+ Over2x
+ Oversample 2x
+ 1
+
+
+ Over4x
+ Oversample 4x
+ 2
+
+
+ Over8x
+ Oversample 8x
+ 3
+
+
+ Over16x
+ Oversample 16x
+ 4
+
+
+ Over32x
+ Oversample 32x
+ 5
+
+
+ Over64x
+ Oversample 64x
+ 6
+
+
+ Over128x
+ Oversample 128x
+ 7
+
+
+ Over256x
+ Oversample 256x
+ 8
+
+
+
+
+
+
+ SAMPLERATE
+ Controls normal or continuous sample rate
+ 0x5F8
+ read-write
+
+
+ CC
+ Capture and compare value. Sample rate is 16 MHz/CC
+ 0
+ 10
+
+
+ MODE
+ Select mode for sample rate control
+ 12
+ 12
+
+
+ Task
+ Rate is controlled from SAMPLE task
+ 0
+
+
+ Timers
+ Rate is controlled from local timer (use CC to control the rate)
+ 1
+
+
+
+
+
+
+ RESULT
+ RESULT EasyDMA channel
+ SAADC_RESULT
+ read-write
+ 0x62C
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of buffer words to transfer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of buffer words to transfer
+ 0
+ 14
+
+
+
+
+ AMOUNT
+ Number of buffer words transferred since last START
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of buffer words transferred since last START. This register can be read after an END or STOPPED event.
+ 0
+ 14
+
+
+
+
+
+
+
+ TIMER0
+ Timer/Counter 0
+ 0x40008000
+ TIMER
+
+ 0
+ 0x1000
+ registers
+
+
+ TIMER0
+ 8
+
+ TIMER
+ 0x20
+
+
+ TASKS_START
+ Start Timer
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start Timer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop Timer
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stop Timer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_COUNT
+ Increment Timer (Counter mode only)
+ 0x008
+ write-only
+
+
+ TASKS_COUNT
+ Increment Timer (Counter mode only)
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CLEAR
+ Clear time
+ 0x00C
+ write-only
+
+
+ TASKS_CLEAR
+ Clear time
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SHUTDOWN
+ Deprecated register - Shut down timer
+ 0x010
+ write-only
+
+
+ TASKS_SHUTDOWN
+ Deprecated field - Shut down timer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x6
+ 0x4
+ TASKS_CAPTURE[%s]
+ Description collection: Capture Timer value to CC[n] register
+ 0x040
+ write-only
+
+
+ TASKS_CAPTURE
+ Capture Timer value to CC[n] register
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x6
+ 0x4
+ EVENTS_COMPARE[%s]
+ Description collection: Compare event on CC[n] match
+ 0x140
+ read-write
+
+
+ EVENTS_COMPARE
+ Compare event on CC[n] match
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ COMPARE0_CLEAR
+ Shortcut between event COMPARE[0] and task CLEAR
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE1_CLEAR
+ Shortcut between event COMPARE[1] and task CLEAR
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE2_CLEAR
+ Shortcut between event COMPARE[2] and task CLEAR
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE3_CLEAR
+ Shortcut between event COMPARE[3] and task CLEAR
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE4_CLEAR
+ Shortcut between event COMPARE[4] and task CLEAR
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE5_CLEAR
+ Shortcut between event COMPARE[5] and task CLEAR
+ 5
+ 5
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE0_STOP
+ Shortcut between event COMPARE[0] and task STOP
+ 8
+ 8
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE1_STOP
+ Shortcut between event COMPARE[1] and task STOP
+ 9
+ 9
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE2_STOP
+ Shortcut between event COMPARE[2] and task STOP
+ 10
+ 10
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE3_STOP
+ Shortcut between event COMPARE[3] and task STOP
+ 11
+ 11
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE4_STOP
+ Shortcut between event COMPARE[4] and task STOP
+ 12
+ 12
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE5_STOP
+ Shortcut between event COMPARE[5] and task STOP
+ 13
+ 13
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ COMPARE0
+ Write '1' to enable interrupt for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to enable interrupt for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to enable interrupt for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to enable interrupt for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE4
+ Write '1' to enable interrupt for event COMPARE[4]
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE5
+ Write '1' to enable interrupt for event COMPARE[5]
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ COMPARE0
+ Write '1' to disable interrupt for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to disable interrupt for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to disable interrupt for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to disable interrupt for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE4
+ Write '1' to disable interrupt for event COMPARE[4]
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE5
+ Write '1' to disable interrupt for event COMPARE[5]
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ MODE
+ Timer mode selection
+ 0x504
+ read-write
+
+
+ MODE
+ Timer mode
+ 0
+ 1
+
+
+ Timer
+ Select Timer mode
+ 0
+
+
+ Counter
+ Deprecated enumerator - Select Counter mode
+ 1
+
+
+ LowPowerCounter
+ Select Low Power Counter mode
+ 2
+
+
+
+
+
+
+ BITMODE
+ Configure the number of bits used by the TIMER
+ 0x508
+ read-write
+
+
+ BITMODE
+ Timer bit width
+ 0
+ 1
+
+
+ 16Bit
+ 16 bit timer bit width
+ 0
+
+
+ 08Bit
+ 8 bit timer bit width
+ 1
+
+
+ 24Bit
+ 24 bit timer bit width
+ 2
+
+
+ 32Bit
+ 32 bit timer bit width
+ 3
+
+
+
+
+
+
+ PRESCALER
+ Timer prescaler register
+ 0x510
+ read-write
+ 0x00000004
+
+
+ PRESCALER
+ Prescaler value
+ 0
+ 3
+
+
+
+
+ 0x6
+ 0x4
+ CC[%s]
+ Description collection: Capture/Compare register n
+ 0x540
+ read-write
+
+
+ CC
+ Capture/Compare value
+ 0
+ 31
+
+
+
+
+
+
+ TIMER1
+ Timer/Counter 1
+ 0x40009000
+
+ TIMER1
+ 9
+
+
+
+ TIMER2
+ Timer/Counter 2
+ 0x4000A000
+
+ TIMER2
+ 10
+
+
+
+ RTC0
+ Real time counter 0
+ 0x4000B000
+ RTC
+
+ 0
+ 0x1000
+ registers
+
+
+ RTC0
+ 11
+
+ RTC
+ 0x20
+
+
+ TASKS_START
+ Start RTC COUNTER
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start RTC COUNTER
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop RTC COUNTER
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stop RTC COUNTER
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CLEAR
+ Clear RTC COUNTER
+ 0x008
+ write-only
+
+
+ TASKS_CLEAR
+ Clear RTC COUNTER
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_TRIGOVRFLW
+ Set COUNTER to 0xFFFFF0
+ 0x00C
+ write-only
+
+
+ TASKS_TRIGOVRFLW
+ Set COUNTER to 0xFFFFF0
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_TICK
+ Event on COUNTER increment
+ 0x100
+ read-write
+
+
+ EVENTS_TICK
+ Event on COUNTER increment
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_OVRFLW
+ Event on COUNTER overflow
+ 0x104
+ read-write
+
+
+ EVENTS_OVRFLW
+ Event on COUNTER overflow
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ 0x4
+ 0x4
+ EVENTS_COMPARE[%s]
+ Description collection: Compare event on CC[n] match
+ 0x140
+ read-write
+
+
+ EVENTS_COMPARE
+ Compare event on CC[n] match
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ TICK
+ Write '1' to enable interrupt for event TICK
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ OVRFLW
+ Write '1' to enable interrupt for event OVRFLW
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE0
+ Write '1' to enable interrupt for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to enable interrupt for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to enable interrupt for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to enable interrupt for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ TICK
+ Write '1' to disable interrupt for event TICK
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ OVRFLW
+ Write '1' to disable interrupt for event OVRFLW
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE0
+ Write '1' to disable interrupt for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to disable interrupt for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to disable interrupt for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to disable interrupt for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ EVTEN
+ Enable or disable event routing
+ 0x340
+ read-write
+
+
+ TICK
+ Enable or disable event routing for event TICK
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+ OVRFLW
+ Enable or disable event routing for event OVRFLW
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+ COMPARE0
+ Enable or disable event routing for event COMPARE[0]
+ 16
+ 16
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+ COMPARE1
+ Enable or disable event routing for event COMPARE[1]
+ 17
+ 17
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+ COMPARE2
+ Enable or disable event routing for event COMPARE[2]
+ 18
+ 18
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+ COMPARE3
+ Enable or disable event routing for event COMPARE[3]
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+
+
+ EVTENSET
+ Enable event routing
+ 0x344
+ read-write
+
+
+ TICK
+ Write '1' to enable event routing for event TICK
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ OVRFLW
+ Write '1' to enable event routing for event OVRFLW
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE0
+ Write '1' to enable event routing for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to enable event routing for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to enable event routing for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to enable event routing for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ EVTENCLR
+ Disable event routing
+ 0x348
+ read-write
+
+
+ TICK
+ Write '1' to disable event routing for event TICK
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ OVRFLW
+ Write '1' to disable event routing for event OVRFLW
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE0
+ Write '1' to disable event routing for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to disable event routing for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to disable event routing for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to disable event routing for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ COUNTER
+ Current COUNTER value
+ 0x504
+ read-only
+
+
+ COUNTER
+ Counter value
+ 0
+ 23
+
+
+
+
+ PRESCALER
+ 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped
+ 0x508
+ read-write
+
+
+ PRESCALER
+ Prescaler value
+ 0
+ 11
+
+
+
+
+ 0x4
+ 0x4
+ CC[%s]
+ Description collection: Compare register n
+ 0x540
+ read-write
+
+
+ COMPARE
+ Compare value
+ 0
+ 23
+
+
+
+
+
+
+ TEMP
+ Temperature Sensor
+ 0x4000C000
+
+ 0
+ 0x1000
+ registers
+
+
+ TEMP
+ 12
+
+ TEMP
+ 0x20
+
+
+ TASKS_START
+ Start temperature measurement
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start temperature measurement
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop temperature measurement
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stop temperature measurement
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_DATARDY
+ Temperature measurement complete, data ready
+ 0x100
+ read-write
+
+
+ EVENTS_DATARDY
+ Temperature measurement complete, data ready
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ DATARDY
+ Write '1' to enable interrupt for event DATARDY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ DATARDY
+ Write '1' to disable interrupt for event DATARDY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ TEMP
+ Temperature in degC (0.25deg steps)
+ 0x508
+ read-only
+ int32_t
+
+
+ TEMP
+ Temperature in degC (0.25deg steps)
+ 0
+ 31
+
+
+
+
+ A0
+ Slope of 1st piece wise linear function
+ 0x520
+ read-write
+ 0x00000326
+
+
+ A0
+ Slope of 1st piece wise linear function
+ 0
+ 11
+
+
+
+
+ A1
+ Slope of 2nd piece wise linear function
+ 0x524
+ read-write
+ 0x00000348
+
+
+ A1
+ Slope of 2nd piece wise linear function
+ 0
+ 11
+
+
+
+
+ A2
+ Slope of 3rd piece wise linear function
+ 0x528
+ read-write
+ 0x000003AA
+
+
+ A2
+ Slope of 3rd piece wise linear function
+ 0
+ 11
+
+
+
+
+ A3
+ Slope of 4th piece wise linear function
+ 0x52C
+ read-write
+ 0x0000040E
+
+
+ A3
+ Slope of 4th piece wise linear function
+ 0
+ 11
+
+
+
+
+ A4
+ Slope of 5th piece wise linear function
+ 0x530
+ read-write
+ 0x000004BD
+
+
+ A4
+ Slope of 5th piece wise linear function
+ 0
+ 11
+
+
+
+
+ A5
+ Slope of 6th piece wise linear function
+ 0x534
+ read-write
+ 0x000005A3
+
+
+ A5
+ Slope of 6th piece wise linear function
+ 0
+ 11
+
+
+
+
+ B0
+ y-intercept of 1st piece wise linear function
+ 0x540
+ read-write
+ 0x00003FEF
+
+
+ B0
+ y-intercept of 1st piece wise linear function
+ 0
+ 13
+
+
+
+
+ B1
+ y-intercept of 2nd piece wise linear function
+ 0x544
+ read-write
+ 0x00003FBE
+
+
+ B1
+ y-intercept of 2nd piece wise linear function
+ 0
+ 13
+
+
+
+
+ B2
+ y-intercept of 3rd piece wise linear function
+ 0x548
+ read-write
+ 0x00003FBE
+
+
+ B2
+ y-intercept of 3rd piece wise linear function
+ 0
+ 13
+
+
+
+
+ B3
+ y-intercept of 4th piece wise linear function
+ 0x54C
+ read-write
+ 0x00000012
+
+
+ B3
+ y-intercept of 4th piece wise linear function
+ 0
+ 13
+
+
+
+
+ B4
+ y-intercept of 5th piece wise linear function
+ 0x550
+ read-write
+ 0x00000124
+
+
+ B4
+ y-intercept of 5th piece wise linear function
+ 0
+ 13
+
+
+
+
+ B5
+ y-intercept of 6th piece wise linear function
+ 0x554
+ read-write
+ 0x0000027C
+
+
+ B5
+ y-intercept of 6th piece wise linear function
+ 0
+ 13
+
+
+
+
+ T0
+ End point of 1st piece wise linear function
+ 0x560
+ read-write
+ 0x000000E2
+
+
+ T0
+ End point of 1st piece wise linear function
+ 0
+ 7
+
+
+
+
+ T1
+ End point of 2nd piece wise linear function
+ 0x564
+ read-write
+ 0x00000000
+
+
+ T1
+ End point of 2nd piece wise linear function
+ 0
+ 7
+
+
+
+
+ T2
+ End point of 3rd piece wise linear function
+ 0x568
+ read-write
+ 0x00000019
+
+
+ T2
+ End point of 3rd piece wise linear function
+ 0
+ 7
+
+
+
+
+ T3
+ End point of 4th piece wise linear function
+ 0x56C
+ read-write
+ 0x0000003C
+
+
+ T3
+ End point of 4th piece wise linear function
+ 0
+ 7
+
+
+
+
+ T4
+ End point of 5th piece wise linear function
+ 0x570
+ read-write
+ 0x00000050
+
+
+ T4
+ End point of 5th piece wise linear function
+ 0
+ 7
+
+
+
+
+
+
+ RNG
+ Random Number Generator
+ 0x4000D000
+
+ 0
+ 0x1000
+ registers
+
+
+ RNG
+ 13
+
+ RNG
+ 0x20
+
+
+ TASKS_START
+ Task starting the random number generator
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Task starting the random number generator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Task stopping the random number generator
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Task stopping the random number generator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_VALRDY
+ Event being generated for every new random number written to the VALUE register
+ 0x100
+ read-write
+
+
+ EVENTS_VALRDY
+ Event being generated for every new random number written to the VALUE register
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ VALRDY_STOP
+ Shortcut between event VALRDY and task STOP
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ VALRDY
+ Write '1' to enable interrupt for event VALRDY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ VALRDY
+ Write '1' to disable interrupt for event VALRDY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x504
+ read-write
+
+
+ DERCEN
+ Bias correction
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+
+
+ VALUE
+ Output random number
+ 0x508
+ read-only
+
+
+ VALUE
+ Generated random number
+ 0
+ 7
+
+
+
+
+
+
+ ECB
+ AES ECB Mode Encryption
+ 0x4000E000
+
+ 0
+ 0x1000
+ registers
+
+
+ ECB
+ 14
+
+ ECB
+ 0x20
+
+
+ TASKS_STARTECB
+ Start ECB block encrypt
+ 0x000
+ write-only
+
+
+ TASKS_STARTECB
+ Start ECB block encrypt
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOPECB
+ Abort a possible executing ECB operation
+ 0x004
+ write-only
+
+
+ TASKS_STOPECB
+ Abort a possible executing ECB operation
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_ENDECB
+ ECB block encrypt complete
+ 0x100
+ read-write
+
+
+ EVENTS_ENDECB
+ ECB block encrypt complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERRORECB
+ ECB block encrypt aborted because of a STOPECB task or due to an error
+ 0x104
+ read-write
+
+
+ EVENTS_ERRORECB
+ ECB block encrypt aborted because of a STOPECB task or due to an error
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ ENDECB
+ Write '1' to enable interrupt for event ENDECB
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERRORECB
+ Write '1' to enable interrupt for event ERRORECB
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ ENDECB
+ Write '1' to disable interrupt for event ENDECB
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERRORECB
+ Write '1' to disable interrupt for event ERRORECB
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ECBDATAPTR
+ ECB block encrypt memory pointers
+ 0x504
+ read-write
+
+
+ ECBDATAPTR
+ Pointer to the ECB data structure (see Table 1 ECB data structure overview)
+ 0
+ 31
+
+
+
+
+
+
+ AAR
+ Accelerated Address Resolver
+ 0x4000F000
+
+ 0
+ 0x1000
+ registers
+
+
+ CCM_AAR
+ 15
+
+ AAR
+ 0x20
+
+
+ TASKS_START
+ Start resolving addresses based on IRKs specified in the IRK data structure
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start resolving addresses based on IRKs specified in the IRK data structure
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop resolving addresses
+ 0x008
+ write-only
+
+
+ TASKS_STOP
+ Stop resolving addresses
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ Address resolution procedure complete
+ 0x100
+ read-write
+
+
+ EVENTS_END
+ Address resolution procedure complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RESOLVED
+ Address resolved
+ 0x104
+ read-write
+
+
+ EVENTS_RESOLVED
+ Address resolved
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_NOTRESOLVED
+ Address not resolved
+ 0x108
+ read-write
+
+
+ EVENTS_NOTRESOLVED
+ Address not resolved
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RESOLVED
+ Write '1' to enable interrupt for event RESOLVED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ NOTRESOLVED
+ Write '1' to enable interrupt for event NOTRESOLVED
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RESOLVED
+ Write '1' to disable interrupt for event RESOLVED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ NOTRESOLVED
+ Write '1' to disable interrupt for event NOTRESOLVED
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ STATUS
+ Resolution status
+ 0x400
+ read-only
+
+
+ STATUS
+ The IRK that was used last time an address was resolved
+ 0
+ 3
+
+
+
+
+ ENABLE
+ Enable AAR
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable AAR
+ 0
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 3
+
+
+
+
+
+
+ NIRK
+ Number of IRKs
+ 0x504
+ read-write
+ 0x00000001
+
+
+ NIRK
+ Number of Identity root keys available in the IRK data structure
+ 0
+ 4
+
+
+
+
+ IRKPTR
+ Pointer to IRK data structure
+ 0x508
+ read-write
+
+
+ IRKPTR
+ Pointer to the IRK data structure
+ 0
+ 31
+
+
+
+
+ ADDRPTR
+ Pointer to the resolvable address
+ 0x510
+ read-write
+
+
+ ADDRPTR
+ Pointer to the resolvable address (6-bytes)
+ 0
+ 31
+
+
+
+
+ SCRATCHPTR
+ Pointer to data area used for temporary storage
+ 0x514
+ read-write
+
+
+ SCRATCHPTR
+ Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved.
+ 0
+ 31
+
+
+
+
+
+
+ CCM
+ AES CCM Mode Encryption
+ 0x4000F000
+ AAR
+
+ 0
+ 0x1000
+ registers
+
+
+ CCM_AAR
+ 15
+
+ CCM
+ 0x20
+
+
+ TASKS_KSGEN
+ Start generation of key-stream. This operation will stop by itself when completed.
+ 0x000
+ write-only
+
+
+ TASKS_KSGEN
+ Start generation of key-stream. This operation will stop by itself when completed.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CRYPT
+ Start encryption/decryption. This operation will stop by itself when completed.
+ 0x004
+ write-only
+
+
+ TASKS_CRYPT
+ Start encryption/decryption. This operation will stop by itself when completed.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop encryption/decryption
+ 0x008
+ write-only
+
+
+ TASKS_STOP
+ Stop encryption/decryption
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RATEOVERRIDE
+ Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
+ 0x00C
+ write-only
+
+
+ TASKS_RATEOVERRIDE
+ Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_ENDKSGEN
+ Key-stream generation complete
+ 0x100
+ read-write
+
+
+ EVENTS_ENDKSGEN
+ Key-stream generation complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDCRYPT
+ Encrypt/decrypt complete
+ 0x104
+ read-write
+
+
+ EVENTS_ENDCRYPT
+ Encrypt/decrypt complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ Deprecated register - CCM error event
+ 0x108
+ read-write
+
+
+ EVENTS_ERROR
+ Deprecated field - CCM error event
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ ENDKSGEN_CRYPT
+ Shortcut between event ENDKSGEN and task CRYPT
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ ENDKSGEN
+ Write '1' to enable interrupt for event ENDKSGEN
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDCRYPT
+ Write '1' to enable interrupt for event ENDCRYPT
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Deprecated intsetfield - Write '1' to enable interrupt for event ERROR
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ ENDKSGEN
+ Write '1' to disable interrupt for event ENDKSGEN
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDCRYPT
+ Write '1' to disable interrupt for event ENDCRYPT
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Deprecated intclrfield - Write '1' to disable interrupt for event ERROR
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ MICSTATUS
+ MIC check result
+ 0x400
+ read-only
+
+
+ MICSTATUS
+ The result of the MIC check performed during the previous decryption operation
+ 0
+ 0
+
+
+ CheckFailed
+ MIC check failed
+ 0
+
+
+ CheckPassed
+ MIC check passed
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable CCM
+ 0
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 2
+
+
+
+
+
+
+ MODE
+ Operation mode
+ 0x504
+ read-write
+ 0x00000001
+
+
+ MODE
+ The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.
+ 0
+ 0
+
+
+ Encryption
+ AES CCM packet encryption mode
+ 0
+
+
+ Decryption
+ AES CCM packet decryption mode
+ 1
+
+
+
+
+ DATARATE
+ Radio data rate that the CCM shall run synchronous with
+ 16
+ 17
+
+
+ 1Mbit
+ 1 Mbps
+ 0
+
+
+ 2Mbit
+ 2 Mbps
+ 1
+
+
+ 125Kbps
+ 125 Kbps
+ 2
+
+
+ 500Kbps
+ 500 Kbps
+ 3
+
+
+
+
+ LENGTH
+ Packet length configuration
+ 24
+ 24
+
+
+ Default
+ Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated.
+ 0
+
+
+ Extended
+ Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated.
+ 1
+
+
+
+
+
+
+ CNFPTR
+ Pointer to data structure holding AES key and NONCE vector
+ 0x508
+ read-write
+
+
+ CNFPTR
+ Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)
+ 0
+ 31
+
+
+
+
+ INPTR
+ Input pointer
+ 0x50C
+ read-write
+
+
+ INPTR
+ Input pointer
+ 0
+ 31
+
+
+
+
+ OUTPTR
+ Output pointer
+ 0x510
+ read-write
+
+
+ OUTPTR
+ Output pointer
+ 0
+ 31
+
+
+
+
+ SCRATCHPTR
+ Pointer to data area used for temporary storage
+ 0x514
+ read-write
+
+
+ SCRATCHPTR
+ Pointer to a scratch data area used for temporary storage during key-stream generation,
+ MIC generation and encryption/decryption.
+ 0
+ 31
+
+
+
+
+ MAXPACKETSIZE
+ Length of key-stream generated when MODE.LENGTH = Extended.
+ 0x518
+ read-write
+ 0x000000FB
+
+
+ MAXPACKETSIZE
+ Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.
+ 0
+ 7
+
+
+
+
+ RATEOVERRIDE
+ Data rate override setting.
+ 0x51C
+ read-write
+ 0x00000000
+
+
+ RATEOVERRIDE
+ Data rate override setting.
+ 0
+ 1
+
+
+ 1Mbit
+ 1 Mbps
+ 0
+
+
+ 2Mbit
+ 2 Mbps
+ 1
+
+
+ 125Kbps
+ 125 Kbps
+ 2
+
+
+ 500Kbps
+ 500 Kbps
+ 3
+
+
+
+
+
+
+
+
+ WDT
+ Watchdog Timer
+ 0x40010000
+
+ 0
+ 0x1000
+ registers
+
+
+ WDT
+ 16
+
+ WDT
+ 0x20
+
+
+ TASKS_START
+ Start the watchdog
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start the watchdog
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_TIMEOUT
+ Watchdog timeout
+ 0x100
+ read-write
+
+
+ EVENTS_TIMEOUT
+ Watchdog timeout
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ TIMEOUT
+ Write '1' to enable interrupt for event TIMEOUT
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ TIMEOUT
+ Write '1' to disable interrupt for event TIMEOUT
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ RUNSTATUS
+ Run status
+ 0x400
+ read-only
+
+
+ RUNSTATUS
+ Indicates whether or not the watchdog is running
+ 0
+ 0
+
+
+ NotRunning
+ Watchdog not running
+ 0
+
+
+ Running
+ Watchdog is running
+ 1
+
+
+
+
+
+
+ REQSTATUS
+ Request status
+ 0x404
+ read-only
+ 0x00000001
+
+
+ RR0
+ Request status for RR[0] register
+ 0
+ 0
+
+
+ DisabledOrRequested
+ RR[0] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[0] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR1
+ Request status for RR[1] register
+ 1
+ 1
+
+
+ DisabledOrRequested
+ RR[1] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[1] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR2
+ Request status for RR[2] register
+ 2
+ 2
+
+
+ DisabledOrRequested
+ RR[2] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[2] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR3
+ Request status for RR[3] register
+ 3
+ 3
+
+
+ DisabledOrRequested
+ RR[3] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[3] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR4
+ Request status for RR[4] register
+ 4
+ 4
+
+
+ DisabledOrRequested
+ RR[4] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[4] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR5
+ Request status for RR[5] register
+ 5
+ 5
+
+
+ DisabledOrRequested
+ RR[5] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[5] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR6
+ Request status for RR[6] register
+ 6
+ 6
+
+
+ DisabledOrRequested
+ RR[6] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[6] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR7
+ Request status for RR[7] register
+ 7
+ 7
+
+
+ DisabledOrRequested
+ RR[7] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[7] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+
+
+ CRV
+ Counter reload value
+ 0x504
+ read-write
+ 0xFFFFFFFF
+
+
+ CRV
+ Counter reload value in number of cycles of the 32.768 kHz clock
+ 0
+ 31
+
+
+
+
+ RREN
+ Enable register for reload request registers
+ 0x508
+ read-write
+ 0x00000001
+
+
+ RR0
+ Enable or disable RR[0] register
+ 0
+ 0
+
+
+ Disabled
+ Disable RR[0] register
+ 0
+
+
+ Enabled
+ Enable RR[0] register
+ 1
+
+
+
+
+ RR1
+ Enable or disable RR[1] register
+ 1
+ 1
+
+
+ Disabled
+ Disable RR[1] register
+ 0
+
+
+ Enabled
+ Enable RR[1] register
+ 1
+
+
+
+
+ RR2
+ Enable or disable RR[2] register
+ 2
+ 2
+
+
+ Disabled
+ Disable RR[2] register
+ 0
+
+
+ Enabled
+ Enable RR[2] register
+ 1
+
+
+
+
+ RR3
+ Enable or disable RR[3] register
+ 3
+ 3
+
+
+ Disabled
+ Disable RR[3] register
+ 0
+
+
+ Enabled
+ Enable RR[3] register
+ 1
+
+
+
+
+ RR4
+ Enable or disable RR[4] register
+ 4
+ 4
+
+
+ Disabled
+ Disable RR[4] register
+ 0
+
+
+ Enabled
+ Enable RR[4] register
+ 1
+
+
+
+
+ RR5
+ Enable or disable RR[5] register
+ 5
+ 5
+
+
+ Disabled
+ Disable RR[5] register
+ 0
+
+
+ Enabled
+ Enable RR[5] register
+ 1
+
+
+
+
+ RR6
+ Enable or disable RR[6] register
+ 6
+ 6
+
+
+ Disabled
+ Disable RR[6] register
+ 0
+
+
+ Enabled
+ Enable RR[6] register
+ 1
+
+
+
+
+ RR7
+ Enable or disable RR[7] register
+ 7
+ 7
+
+
+ Disabled
+ Disable RR[7] register
+ 0
+
+
+ Enabled
+ Enable RR[7] register
+ 1
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x50C
+ read-write
+ 0x00000001
+
+
+ SLEEP
+ Configure the watchdog to either be paused, or kept running, while the CPU is sleeping
+ 0
+ 0
+
+
+ Pause
+ Pause watchdog while the CPU is sleeping
+ 0
+
+
+ Run
+ Keep the watchdog running while the CPU is sleeping
+ 1
+
+
+
+
+ HALT
+ Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger
+ 3
+ 3
+
+
+ Pause
+ Pause watchdog while the CPU is halted by the debugger
+ 0
+
+
+ Run
+ Keep the watchdog running while the CPU is halted by the debugger
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ RR[%s]
+ Description collection: Reload request n
+ 0x600
+ write-only
+
+
+ RR
+ Reload request register
+ 0
+ 31
+
+
+ Reload
+ Value to request a reload of the watchdog timer
+ 0x6E524635
+
+
+
+
+
+
+
+
+ RTC1
+ Real time counter 1
+ 0x40011000
+
+ RTC1
+ 17
+
+
+
+ EGU0
+ Event Generator Unit 0
+ 0x40014000
+ EGU
+
+ 0
+ 0x1000
+ registers
+
+
+ SWI0_EGU0
+ 20
+
+ EGU
+ 0x20
+
+
+ 0x10
+ 0x4
+ TASKS_TRIGGER[%s]
+ Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event
+ 0x000
+ write-only
+
+
+ TASKS_TRIGGER
+ Trigger n for triggering the corresponding TRIGGERED[n] event
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x10
+ 0x4
+ EVENTS_TRIGGERED[%s]
+ Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task
+ 0x100
+ read-write
+
+
+ EVENTS_TRIGGERED
+ Event number n generated by triggering the corresponding TRIGGER[n] task
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ TRIGGERED0
+ Enable or disable interrupt for event TRIGGERED[0]
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED1
+ Enable or disable interrupt for event TRIGGERED[1]
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED2
+ Enable or disable interrupt for event TRIGGERED[2]
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED3
+ Enable or disable interrupt for event TRIGGERED[3]
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED4
+ Enable or disable interrupt for event TRIGGERED[4]
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED5
+ Enable or disable interrupt for event TRIGGERED[5]
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED6
+ Enable or disable interrupt for event TRIGGERED[6]
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED7
+ Enable or disable interrupt for event TRIGGERED[7]
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED8
+ Enable or disable interrupt for event TRIGGERED[8]
+ 8
+ 8
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED9
+ Enable or disable interrupt for event TRIGGERED[9]
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED10
+ Enable or disable interrupt for event TRIGGERED[10]
+ 10
+ 10
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED11
+ Enable or disable interrupt for event TRIGGERED[11]
+ 11
+ 11
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED12
+ Enable or disable interrupt for event TRIGGERED[12]
+ 12
+ 12
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED13
+ Enable or disable interrupt for event TRIGGERED[13]
+ 13
+ 13
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED14
+ Enable or disable interrupt for event TRIGGERED[14]
+ 14
+ 14
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED15
+ Enable or disable interrupt for event TRIGGERED[15]
+ 15
+ 15
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ TRIGGERED0
+ Write '1' to enable interrupt for event TRIGGERED[0]
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED1
+ Write '1' to enable interrupt for event TRIGGERED[1]
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED2
+ Write '1' to enable interrupt for event TRIGGERED[2]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED3
+ Write '1' to enable interrupt for event TRIGGERED[3]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED4
+ Write '1' to enable interrupt for event TRIGGERED[4]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED5
+ Write '1' to enable interrupt for event TRIGGERED[5]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED6
+ Write '1' to enable interrupt for event TRIGGERED[6]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED7
+ Write '1' to enable interrupt for event TRIGGERED[7]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED8
+ Write '1' to enable interrupt for event TRIGGERED[8]
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED9
+ Write '1' to enable interrupt for event TRIGGERED[9]
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED10
+ Write '1' to enable interrupt for event TRIGGERED[10]
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED11
+ Write '1' to enable interrupt for event TRIGGERED[11]
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED12
+ Write '1' to enable interrupt for event TRIGGERED[12]
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED13
+ Write '1' to enable interrupt for event TRIGGERED[13]
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED14
+ Write '1' to enable interrupt for event TRIGGERED[14]
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED15
+ Write '1' to enable interrupt for event TRIGGERED[15]
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ TRIGGERED0
+ Write '1' to disable interrupt for event TRIGGERED[0]
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED1
+ Write '1' to disable interrupt for event TRIGGERED[1]
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED2
+ Write '1' to disable interrupt for event TRIGGERED[2]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED3
+ Write '1' to disable interrupt for event TRIGGERED[3]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED4
+ Write '1' to disable interrupt for event TRIGGERED[4]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED5
+ Write '1' to disable interrupt for event TRIGGERED[5]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED6
+ Write '1' to disable interrupt for event TRIGGERED[6]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED7
+ Write '1' to disable interrupt for event TRIGGERED[7]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED8
+ Write '1' to disable interrupt for event TRIGGERED[8]
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED9
+ Write '1' to disable interrupt for event TRIGGERED[9]
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED10
+ Write '1' to disable interrupt for event TRIGGERED[10]
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED11
+ Write '1' to disable interrupt for event TRIGGERED[11]
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED12
+ Write '1' to disable interrupt for event TRIGGERED[12]
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED13
+ Write '1' to disable interrupt for event TRIGGERED[13]
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED14
+ Write '1' to disable interrupt for event TRIGGERED[14]
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED15
+ Write '1' to disable interrupt for event TRIGGERED[15]
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+
+
+ SWI0
+ Software interrupt 0
+ 0x40014000
+ EGU0
+ SWI
+
+ 0
+ 0x1000
+ registers
+
+
+ SWI0_EGU0
+ 20
+
+ SWI
+ 0x20
+
+
+ UNUSED
+ Unused.
+ 0x000
+ 0x00000000
+ read-only
+
+
+
+
+ EGU1
+ Event Generator Unit 1
+ 0x40015000
+
+ SWI1_EGU1
+ 21
+
+
+
+ SWI1
+ Software interrupt 1
+ 0x40015000
+ EGU1
+
+ SWI1_EGU1
+ 21
+
+
+
+ SWI2
+ Software interrupt 2
+ 0x40016000
+
+ SWI2
+ 22
+
+
+
+ SWI3
+ Software interrupt 3
+ 0x40017000
+
+ SWI3
+ 23
+
+
+
+ SWI4
+ Software interrupt 4
+ 0x40018000
+
+ SWI4
+ 24
+
+
+
+ SWI5
+ Software interrupt 5
+ 0x40019000
+
+ SWI5
+ 25
+
+
+
+ NVMC
+ Non-volatile memory controller
+ 0x4001E000
+
+ 0
+ 0x1000
+ registers
+
+ NVMC
+ 0x20
+
+
+ READY
+ Ready flag
+ 0x400
+ read-only
+ 0x00000001
+
+
+ READY
+ NVMC is ready or busy
+ 0
+ 0
+
+
+ Busy
+ NVMC is busy (ongoing write or erase operation)
+ 0
+
+
+ Ready
+ NVMC is ready
+ 1
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x504
+ read-write
+
+
+ WEN
+ Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used.
+ 0
+ 1
+
+
+ Ren
+ Read only access
+ 0
+
+
+ Wen
+ Write enabled
+ 1
+
+
+ Een
+ Erase enabled
+ 2
+
+
+
+
+
+
+ ERASEPAGE
+ Register for erasing a page in code area
+ 0x508
+ read-write
+
+
+ ERASEPAGE
+ Register for starting erase of a page in code area.
+ 0
+ 31
+
+
+
+
+ ERASEPCR1
+ Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE.
+ 0x508
+ read-write
+ ERASEPAGE
+
+
+ ERASEPCR1
+ Register for erasing a page in code area. Equivalent to ERASEPAGE.
+ 0
+ 31
+
+
+
+
+ ERASEALL
+ Register for erasing all non-volatile user memory
+ 0x50C
+ read-write
+
+
+ ERASEALL
+ Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.
+ 0
+ 0
+
+
+ NoOperation
+ No operation
+ 0
+
+
+ Erase
+ Start erase of chip
+ 1
+
+
+
+
+
+
+ ERASEPCR0
+ Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE.
+ 0x510
+ read-write
+
+
+ ERASEPCR0
+ Register for starting erase of a page in code area. Equivalent to ERASEPAGE.
+ 0
+ 31
+
+
+
+
+ ERASEUICR
+ Register for erasing user information configuration registers
+ 0x514
+ read-write
+
+
+ ERASEUICR
+ Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.
+ 0
+ 0
+
+
+ NoOperation
+ No operation
+ 0
+
+
+ Erase
+ Start erase of UICR
+ 1
+
+
+
+
+
+
+ ERASEPAGEPARTIAL
+ Register for partial erase of a page in code area
+ 0x518
+ read-write
+
+
+ ERASEPAGEPARTIAL
+ Register for starting partial erase of a page in code area
+ 0
+ 31
+
+
+
+
+ ERASEPAGEPARTIALCFG
+ Register for partial erase configuration
+ 0x51C
+ read-write
+ 0x0000000A
+
+
+ DURATION
+ Duration of the partial erase in milliseconds
+ 0
+ 6
+
+
+
+
+
+
+ PPI
+ Programmable Peripheral Interconnect
+ 0x4001F000
+
+ 0
+ 0x1000
+ registers
+
+ PPI
+ 0x20
+
+
+ 6
+ 0x008
+ TASKS_CHG[%s]
+ Channel group tasks
+ PPI_TASKS_CHG
+ write-only
+ 0x000
+
+ EN
+ Description cluster: Enable channel group n
+ 0x000
+ write-only
+
+
+ EN
+ Enable channel group n
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ DIS
+ Description cluster: Disable channel group n
+ 0x004
+ write-only
+
+
+ DIS
+ Disable channel group n
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+
+ CHEN
+ Channel enable register
+ 0x500
+ read-write
+
+
+ CH0
+ Enable or disable channel 0
+ 0
+ 0
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH1
+ Enable or disable channel 1
+ 1
+ 1
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH2
+ Enable or disable channel 2
+ 2
+ 2
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH3
+ Enable or disable channel 3
+ 3
+ 3
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH4
+ Enable or disable channel 4
+ 4
+ 4
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH5
+ Enable or disable channel 5
+ 5
+ 5
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH6
+ Enable or disable channel 6
+ 6
+ 6
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH7
+ Enable or disable channel 7
+ 7
+ 7
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH8
+ Enable or disable channel 8
+ 8
+ 8
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH9
+ Enable or disable channel 9
+ 9
+ 9
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH10
+ Enable or disable channel 10
+ 10
+ 10
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH11
+ Enable or disable channel 11
+ 11
+ 11
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH12
+ Enable or disable channel 12
+ 12
+ 12
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH13
+ Enable or disable channel 13
+ 13
+ 13
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH14
+ Enable or disable channel 14
+ 14
+ 14
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH15
+ Enable or disable channel 15
+ 15
+ 15
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH16
+ Enable or disable channel 16
+ 16
+ 16
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH17
+ Enable or disable channel 17
+ 17
+ 17
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH18
+ Enable or disable channel 18
+ 18
+ 18
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH19
+ Enable or disable channel 19
+ 19
+ 19
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH20
+ Enable or disable channel 20
+ 20
+ 20
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH21
+ Enable or disable channel 21
+ 21
+ 21
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH22
+ Enable or disable channel 22
+ 22
+ 22
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH23
+ Enable or disable channel 23
+ 23
+ 23
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH24
+ Enable or disable channel 24
+ 24
+ 24
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH25
+ Enable or disable channel 25
+ 25
+ 25
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH26
+ Enable or disable channel 26
+ 26
+ 26
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH27
+ Enable or disable channel 27
+ 27
+ 27
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH28
+ Enable or disable channel 28
+ 28
+ 28
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH29
+ Enable or disable channel 29
+ 29
+ 29
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH30
+ Enable or disable channel 30
+ 30
+ 30
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH31
+ Enable or disable channel 31
+ 31
+ 31
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+
+
+ CHENSET
+ Channel enable set register
+ 0x504
+ read-write
+ oneToSet
+
+
+ CH0
+ Channel 0 enable set register. Writing '0' has no effect
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH1
+ Channel 1 enable set register. Writing '0' has no effect
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH2
+ Channel 2 enable set register. Writing '0' has no effect
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH3
+ Channel 3 enable set register. Writing '0' has no effect
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH4
+ Channel 4 enable set register. Writing '0' has no effect
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH5
+ Channel 5 enable set register. Writing '0' has no effect
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH6
+ Channel 6 enable set register. Writing '0' has no effect
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH7
+ Channel 7 enable set register. Writing '0' has no effect
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH8
+ Channel 8 enable set register. Writing '0' has no effect
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH9
+ Channel 9 enable set register. Writing '0' has no effect
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH10
+ Channel 10 enable set register. Writing '0' has no effect
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH11
+ Channel 11 enable set register. Writing '0' has no effect
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH12
+ Channel 12 enable set register. Writing '0' has no effect
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH13
+ Channel 13 enable set register. Writing '0' has no effect
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH14
+ Channel 14 enable set register. Writing '0' has no effect
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH15
+ Channel 15 enable set register. Writing '0' has no effect
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH16
+ Channel 16 enable set register. Writing '0' has no effect
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH17
+ Channel 17 enable set register. Writing '0' has no effect
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH18
+ Channel 18 enable set register. Writing '0' has no effect
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH19
+ Channel 19 enable set register. Writing '0' has no effect
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH20
+ Channel 20 enable set register. Writing '0' has no effect
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH21
+ Channel 21 enable set register. Writing '0' has no effect
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH22
+ Channel 22 enable set register. Writing '0' has no effect
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH23
+ Channel 23 enable set register. Writing '0' has no effect
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH24
+ Channel 24 enable set register. Writing '0' has no effect
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH25
+ Channel 25 enable set register. Writing '0' has no effect
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH26
+ Channel 26 enable set register. Writing '0' has no effect
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH27
+ Channel 27 enable set register. Writing '0' has no effect
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH28
+ Channel 28 enable set register. Writing '0' has no effect
+ 28
+ 28
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH29
+ Channel 29 enable set register. Writing '0' has no effect
+ 29
+ 29
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH30
+ Channel 30 enable set register. Writing '0' has no effect
+ 30
+ 30
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH31
+ Channel 31 enable set register. Writing '0' has no effect
+ 31
+ 31
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+
+
+ CHENCLR
+ Channel enable clear register
+ 0x508
+ read-write
+ oneToClear
+
+
+ CH0
+ Channel 0 enable clear register. Writing '0' has no effect
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH1
+ Channel 1 enable clear register. Writing '0' has no effect
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH2
+ Channel 2 enable clear register. Writing '0' has no effect
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH3
+ Channel 3 enable clear register. Writing '0' has no effect
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH4
+ Channel 4 enable clear register. Writing '0' has no effect
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH5
+ Channel 5 enable clear register. Writing '0' has no effect
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH6
+ Channel 6 enable clear register. Writing '0' has no effect
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH7
+ Channel 7 enable clear register. Writing '0' has no effect
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH8
+ Channel 8 enable clear register. Writing '0' has no effect
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH9
+ Channel 9 enable clear register. Writing '0' has no effect
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH10
+ Channel 10 enable clear register. Writing '0' has no effect
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH11
+ Channel 11 enable clear register. Writing '0' has no effect
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH12
+ Channel 12 enable clear register. Writing '0' has no effect
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH13
+ Channel 13 enable clear register. Writing '0' has no effect
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH14
+ Channel 14 enable clear register. Writing '0' has no effect
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH15
+ Channel 15 enable clear register. Writing '0' has no effect
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH16
+ Channel 16 enable clear register. Writing '0' has no effect
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH17
+ Channel 17 enable clear register. Writing '0' has no effect
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH18
+ Channel 18 enable clear register. Writing '0' has no effect
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH19
+ Channel 19 enable clear register. Writing '0' has no effect
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH20
+ Channel 20 enable clear register. Writing '0' has no effect
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH21
+ Channel 21 enable clear register. Writing '0' has no effect
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH22
+ Channel 22 enable clear register. Writing '0' has no effect
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH23
+ Channel 23 enable clear register. Writing '0' has no effect
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH24
+ Channel 24 enable clear register. Writing '0' has no effect
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH25
+ Channel 25 enable clear register. Writing '0' has no effect
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH26
+ Channel 26 enable clear register. Writing '0' has no effect
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH27
+ Channel 27 enable clear register. Writing '0' has no effect
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH28
+ Channel 28 enable clear register. Writing '0' has no effect
+ 28
+ 28
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH29
+ Channel 29 enable clear register. Writing '0' has no effect
+ 29
+ 29
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH30
+ Channel 30 enable clear register. Writing '0' has no effect
+ 30
+ 30
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH31
+ Channel 31 enable clear register. Writing '0' has no effect
+ 31
+ 31
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+
+
+ 20
+ 0x008
+ CH[%s]
+ PPI Channel
+ PPI_CH
+ read-write
+ 0x510
+
+ EEP
+ Description cluster: Channel n event end-point
+ 0x000
+ read-write
+
+
+ EEP
+ Pointer to event register. Accepts only addresses to registers from the Event group.
+ 0
+ 31
+
+
+
+
+ TEP
+ Description cluster: Channel n task end-point
+ 0x004
+ read-write
+
+
+ TEP
+ Pointer to task register. Accepts only addresses to registers from the Task group.
+ 0
+ 31
+
+
+
+
+
+ 0x6
+ 0x4
+ CHG[%s]
+ Description collection: Channel group n
+ 0x800
+ read-write
+
+
+ CH0
+ Include or exclude channel 0
+ 0
+ 0
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH1
+ Include or exclude channel 1
+ 1
+ 1
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH2
+ Include or exclude channel 2
+ 2
+ 2
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH3
+ Include or exclude channel 3
+ 3
+ 3
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH4
+ Include or exclude channel 4
+ 4
+ 4
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH5
+ Include or exclude channel 5
+ 5
+ 5
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH6
+ Include or exclude channel 6
+ 6
+ 6
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH7
+ Include or exclude channel 7
+ 7
+ 7
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH8
+ Include or exclude channel 8
+ 8
+ 8
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH9
+ Include or exclude channel 9
+ 9
+ 9
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH10
+ Include or exclude channel 10
+ 10
+ 10
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH11
+ Include or exclude channel 11
+ 11
+ 11
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH12
+ Include or exclude channel 12
+ 12
+ 12
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH13
+ Include or exclude channel 13
+ 13
+ 13
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH14
+ Include or exclude channel 14
+ 14
+ 14
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH15
+ Include or exclude channel 15
+ 15
+ 15
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH16
+ Include or exclude channel 16
+ 16
+ 16
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH17
+ Include or exclude channel 17
+ 17
+ 17
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH18
+ Include or exclude channel 18
+ 18
+ 18
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH19
+ Include or exclude channel 19
+ 19
+ 19
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH20
+ Include or exclude channel 20
+ 20
+ 20
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH21
+ Include or exclude channel 21
+ 21
+ 21
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH22
+ Include or exclude channel 22
+ 22
+ 22
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH23
+ Include or exclude channel 23
+ 23
+ 23
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH24
+ Include or exclude channel 24
+ 24
+ 24
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH25
+ Include or exclude channel 25
+ 25
+ 25
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH26
+ Include or exclude channel 26
+ 26
+ 26
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH27
+ Include or exclude channel 27
+ 27
+ 27
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH28
+ Include or exclude channel 28
+ 28
+ 28
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH29
+ Include or exclude channel 29
+ 29
+ 29
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH30
+ Include or exclude channel 30
+ 30
+ 30
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH31
+ Include or exclude channel 31
+ 31
+ 31
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+
+
+ 32
+ 0x004
+ FORK[%s]
+ Fork
+ PPI_FORK
+ read-write
+ 0x910
+
+ TEP
+ Description cluster: Channel n task end-point
+ 0x000
+ read-write
+
+
+ TEP
+ Pointer to task register
+ 0
+ 31
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52805_bitfields.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52805_bitfields.h
new file mode 100644
index 000000000..8c7e0246b
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52805_bitfields.h
@@ -0,0 +1,10267 @@
+/*
+
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef __NRF52805_BITS_H
+#define __NRF52805_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver */
+
+/* Register: AAR_TASKS_START */
+/* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
+
+/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
+#define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: AAR_TASKS_STOP */
+/* Description: Stop resolving addresses */
+
+/* Bit 0 : Stop resolving addresses */
+#define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: AAR_EVENTS_END */
+/* Description: Address resolution procedure complete */
+
+/* Bit 0 : Address resolution procedure complete */
+#define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: AAR_EVENTS_RESOLVED */
+/* Description: Address resolved */
+
+/* Bit 0 : Address resolved */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
+
+/* Register: AAR_EVENTS_NOTRESOLVED */
+/* Description: Address not resolved */
+
+/* Bit 0 : Address not resolved */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
+
+/* Register: AAR_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event END */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: AAR_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event END */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status */
+
+/* Bits 3..0 : The IRK that was used last time an address was resolved */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR */
+
+/* Bits 1..0 : Enable or disable AAR */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
+
+/* Register: AAR_NIRK */
+/* Description: Number of IRKs */
+
+/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_IRKPTR */
+/* Description: Pointer to IRK data structure */
+
+/* Bits 31..0 : Pointer to the IRK data structure */
+#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
+#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
+
+/* Register: AAR_ADDRPTR */
+/* Description: Pointer to the resolvable address */
+
+/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
+#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
+#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
+
+/* Register: AAR_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+
+/* Peripheral: BPROT */
+/* Description: Block Protect */
+
+/* Register: BPROT_CONFIG0 */
+/* Description: Block protect configuration register 0 */
+
+/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
+#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
+#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
+#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
+#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
+#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
+#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
+#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
+#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
+#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
+#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
+#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
+#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
+#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
+#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
+#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
+#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
+#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
+#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
+#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
+#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
+#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
+#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
+#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
+#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
+#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
+#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
+#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
+#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
+#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
+#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
+#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
+#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
+#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
+#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
+#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
+#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
+#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
+#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
+#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
+#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
+#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
+#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
+#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
+#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
+#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
+#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
+#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
+#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
+#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
+#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
+#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
+#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
+#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
+#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
+#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
+#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
+#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
+#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
+#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
+#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
+#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
+#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
+#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
+#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enabled */
+
+/* Register: BPROT_CONFIG1 */
+/* Description: Block protect configuration register 1 */
+
+/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
+#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
+#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
+#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
+#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
+#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
+#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
+#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
+#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
+#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
+#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
+#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
+#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
+#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
+#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
+#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
+#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
+#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
+#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
+#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
+#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
+#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
+#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
+#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
+#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
+#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
+#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
+#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
+#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
+#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
+#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
+#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
+#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
+
+/* Register: BPROT_DISABLEINDEBUG */
+/* Description: Disable protection mechanism in debug mode */
+
+/* Bit 0 : Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enabled in debug */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disabled in debug */
+
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption */
+
+/* Register: CCM_TASKS_KSGEN */
+/* Description: Start generation of key-stream. This operation will stop by itself when completed. */
+
+/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */
+#define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
+#define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
+#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_TASKS_CRYPT */
+/* Description: Start encryption/decryption. This operation will stop by itself when completed. */
+
+/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
+#define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
+#define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
+#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_TASKS_STOP */
+/* Description: Stop encryption/decryption */
+
+/* Bit 0 : Stop encryption/decryption */
+#define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_TASKS_RATEOVERRIDE */
+/* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
+
+/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
+#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */
+#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */
+#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_EVENTS_ENDKSGEN */
+/* Description: Key-stream generation complete */
+
+/* Bit 0 : Key-stream generation complete */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
+
+/* Register: CCM_EVENTS_ENDCRYPT */
+/* Description: Encrypt/decrypt complete */
+
+/* Bit 0 : Encrypt/decrypt complete */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
+
+/* Register: CCM_EVENTS_ERROR */
+/* Description: Deprecated register - CCM error event */
+
+/* Bit 0 : Deprecated field - CCM error event */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: CCM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
+
+/* Register: CCM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
+
+/* Register: CCM_MICSTATUS */
+/* Description: MIC check result */
+
+/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
+
+/* Register: CCM_ENABLE */
+/* Description: Enable */
+
+/* Bits 1..0 : Enable or disable CCM */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode */
+
+/* Bit 24 : Packet length configuration */
+#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
+#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
+#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */
+#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */
+
+/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
+#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
+#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
+#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
+#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
+#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */
+#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */
+
+/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
+
+/* Register: CCM_CNFPTR */
+/* Description: Pointer to data structure holding AES key and NONCE vector */
+
+/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
+#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
+#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
+
+/* Register: CCM_INPTR */
+/* Description: Input pointer */
+
+/* Bits 31..0 : Input pointer */
+#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
+#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
+
+/* Register: CCM_OUTPTR */
+/* Description: Output pointer */
+
+/* Bits 31..0 : Output pointer */
+#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
+#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
+
+/* Register: CCM_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation,
+ MIC generation and encryption/decryption. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+/* Register: CCM_MAXPACKETSIZE */
+/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */
+
+/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */
+#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
+#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
+
+/* Register: CCM_RATEOVERRIDE */
+/* Description: Data rate override setting. */
+
+/* Bits 1..0 : Data rate override setting. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control */
+
+/* Register: CLOCK_TASKS_HFCLKSTART */
+/* Description: Start HFCLK crystal oscillator */
+
+/* Bit 0 : Start HFCLK crystal oscillator */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_HFCLKSTOP */
+/* Description: Stop HFCLK crystal oscillator */
+
+/* Bit 0 : Stop HFCLK crystal oscillator */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_LFCLKSTART */
+/* Description: Start LFCLK source */
+
+/* Bit 0 : Start LFCLK source */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_LFCLKSTOP */
+/* Description: Stop LFCLK source */
+
+/* Bit 0 : Stop LFCLK source */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_CAL */
+/* Description: Start calibration of LFRC oscillator */
+
+/* Bit 0 : Start calibration of LFRC oscillator */
+#define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
+#define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
+#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_CTSTART */
+/* Description: Start calibration timer */
+
+/* Bit 0 : Start calibration timer */
+#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */
+#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */
+#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_CTSTOP */
+/* Description: Stop calibration timer */
+
+/* Bit 0 : Stop calibration timer */
+#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */
+#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */
+#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_EVENTS_HFCLKSTARTED */
+/* Description: HFCLK oscillator started */
+
+/* Bit 0 : HFCLK oscillator started */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_LFCLKSTARTED */
+/* Description: LFCLK started */
+
+/* Bit 0 : LFCLK started */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_DONE */
+/* Description: Calibration of LFCLK RC oscillator complete event */
+
+/* Bit 0 : Calibration of LFCLK RC oscillator complete event */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_CTTO */
+/* Description: Calibration timer timeout */
+
+/* Bit 0 : Calibration timer timeout */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to enable interrupt for event CTTO */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event DONE */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to disable interrupt for event CTTO */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event DONE */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Status indicating that HFCLKSTART task has been triggered */
+
+/* Bit 0 : HFCLKSTART task triggered or not */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: HFCLK status */
+
+/* Bit 16 : HFCLK state */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
+
+/* Bit 0 : Source of HFCLK */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Status indicating that LFCLKSTART task has been triggered */
+
+/* Bit 0 : LFCLKSTART task triggered or not */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: LFCLK status */
+
+/* Bit 16 : LFCLK state */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
+
+/* Bits 1..0 : Source of LFCLK */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK */
+
+/* Bit 17 : Enable or disable external source for LFCLK */
+#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
+#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
+
+/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
+#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
+#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval */
+
+/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption */
+
+/* Register: ECB_TASKS_STARTECB */
+/* Description: Start ECB block encrypt */
+
+/* Bit 0 : Start ECB block encrypt */
+#define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
+#define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
+#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
+
+/* Register: ECB_TASKS_STOPECB */
+/* Description: Abort a possible executing ECB operation */
+
+/* Bit 0 : Abort a possible executing ECB operation */
+#define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
+#define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
+#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
+
+/* Register: ECB_EVENTS_ENDECB */
+/* Description: ECB block encrypt complete */
+
+/* Bit 0 : ECB block encrypt complete */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
+
+/* Register: ECB_EVENTS_ERRORECB */
+/* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
+
+/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
+
+/* Register: ECB_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event ENDECB */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
+
+/* Register: ECB_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event ENDECB */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
+
+/* Register: ECB_ECBDATAPTR */
+/* Description: ECB block encrypt memory pointers */
+
+/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
+
+
+/* Peripheral: EGU */
+/* Description: Event Generator Unit 0 */
+
+/* Register: EGU_TASKS_TRIGGER */
+/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
+
+/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
+
+/* Register: EGU_EVENTS_TRIGGERED */
+/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
+
+/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
+
+/* Register: EGU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
+#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
+#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
+#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
+#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
+#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
+#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
+#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
+#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
+#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
+#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
+#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
+#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
+#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
+#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
+#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
+#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
+
+/* Register: EGU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
+#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
+#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
+#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
+#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
+#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
+#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
+#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
+#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
+#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
+#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
+#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
+#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
+#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
+#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
+#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
+#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
+
+/* Register: EGU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
+#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
+#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
+#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
+#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
+#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
+#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
+#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
+#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
+#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
+#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
+#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
+#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
+#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
+#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
+#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
+#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
+
+
+/* Peripheral: FICR */
+/* Description: Factory information configuration registers */
+
+/* Register: FICR_CODEPAGESIZE */
+/* Description: Code memory page size */
+
+/* Bits 31..0 : Code memory page size */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
+
+/* Register: FICR_CODESIZE */
+/* Description: Code memory size */
+
+/* Bits 31..0 : Code memory size in number of pages */
+#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
+#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
+
+/* Register: FICR_DEVICEID */
+/* Description: Description collection: Device identifier */
+
+/* Bits 31..0 : 64 bit unique device identifier */
+#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
+#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
+
+/* Register: FICR_ER */
+/* Description: Description collection: Encryption root, word n */
+
+/* Bits 31..0 : Encryption root, word n */
+#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
+#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
+
+/* Register: FICR_IR */
+/* Description: Description collection: Identity root, word n */
+
+/* Bits 31..0 : Identity root, word n */
+#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
+#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type */
+
+/* Bit 0 : Device address type */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
+
+/* Register: FICR_DEVICEADDR */
+/* Description: Description collection: Device address n */
+
+/* Bits 31..0 : 48 bit device address */
+#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
+#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
+
+/* Register: FICR_INFO_PART */
+/* Description: Part code */
+
+/* Bits 31..0 : Part code */
+#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
+#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N52805 (0x52805UL) /*!< nRF52805 */
+#define FICR_INFO_PART_PART_N52810 (0x52810UL) /*!< nRF52810 */
+#define FICR_INFO_PART_PART_N52811 (0x52811UL) /*!< nRF52811 */
+#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
+#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_VARIANT */
+/* Description: Part variant, hardware version and production configuration */
+
+/* Bits 31..0 : Part variant, hardware version and production configuration, encoded as ASCII */
+#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */
+#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
+#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
+#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
+#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
+#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */
+#define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */
+#define FICR_INFO_VARIANT_VARIANT_AACB (0x41414342UL) /*!< AACB */
+#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_PACKAGE */
+/* Description: Package option */
+
+/* Bits 31..0 : Package option */
+#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_CA (0x2004UL) /*!< CAxx - WLCSP */
+#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_RAM */
+/* Description: RAM variant */
+
+/* Bits 31..0 : RAM variant */
+#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
+#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
+#define FICR_INFO_RAM_RAM_K24 (0x18UL) /*!< 24 kByte RAM */
+#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_FLASH */
+/* Description: Flash variant */
+
+/* Bits 31..0 : Flash variant */
+#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_K192 (0xC0UL) /*!< 192 kByte flash */
+#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_TEMP_A0 */
+/* Description: Slope definition A0 */
+
+/* Bits 11..0 : A (slope definition) register */
+#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A1 */
+/* Description: Slope definition A1 */
+
+/* Bits 11..0 : A (slope definition) register */
+#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A2 */
+/* Description: Slope definition A2 */
+
+/* Bits 11..0 : A (slope definition) register */
+#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A3 */
+/* Description: Slope definition A3 */
+
+/* Bits 11..0 : A (slope definition) register */
+#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A4 */
+/* Description: Slope definition A4 */
+
+/* Bits 11..0 : A (slope definition) register */
+#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A5 */
+/* Description: Slope definition A5 */
+
+/* Bits 11..0 : A (slope definition) register */
+#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_B0 */
+/* Description: Y-intercept B0 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B1 */
+/* Description: Y-intercept B1 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B2 */
+/* Description: Y-intercept B2 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B3 */
+/* Description: Y-intercept B3 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B4 */
+/* Description: Y-intercept B4 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B5 */
+/* Description: Y-intercept B5 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_T0 */
+/* Description: Segment end T0 */
+
+/* Bits 7..0 : T (segment end) register */
+#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T1 */
+/* Description: Segment end T1 */
+
+/* Bits 7..0 : T (segment end) register */
+#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T2 */
+/* Description: Segment end T2 */
+
+/* Bits 7..0 : T (segment end) register */
+#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T3 */
+/* Description: Segment end T3 */
+
+/* Bits 7..0 : T (segment end) register */
+#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T4 */
+/* Description: Segment end T4 */
+
+/* Bits 7..0 : T (segment end) register */
+#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO Tasks and Events */
+
+/* Register: GPIOTE_TASKS_OUT */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_TASKS_SET */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_TASKS_CLR */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_EVENTS_IN */
+/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
+
+/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
+
+/* Register: GPIOTE_EVENTS_PORT */
+/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
+
+/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 31 : Write '1' to enable interrupt for event PORT */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event IN[7] */
+#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event IN[6] */
+#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event IN[5] */
+#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event IN[4] */
+#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event IN[3] */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event IN[2] */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event IN[1] */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event IN[0] */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 31 : Write '1' to disable interrupt for event PORT */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event IN[7] */
+#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event IN[6] */
+#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event IN[5] */
+#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event IN[4] */
+#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event IN[3] */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event IN[2] */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event IN[1] */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event IN[0] */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
+
+/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
+
+/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
+
+/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
+#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
+#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
+
+
+/* Peripheral: NVMC */
+/* Description: Non-volatile memory controller */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag */
+
+/* Bit 0 : NVMC is ready or busy */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register */
+
+/* Bits 1..0 : Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
+#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
+#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
+
+/* Register: NVMC_ERASEPAGE */
+/* Description: Register for erasing a page in code area */
+
+/* Bits 31..0 : Register for starting erase of a page in code area. */
+#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
+#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
+
+/* Register: NVMC_ERASEPCR1 */
+/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory */
+
+/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start erase of chip */
+
+/* Register: NVMC_ERASEPCR0 */
+/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for erasing user information configuration registers */
+
+/* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
+
+/* Register: NVMC_ERASEPAGEPARTIAL */
+/* Description: Register for partial erase of a page in code area */
+
+/* Bits 31..0 : Register for starting partial erase of a page in code area */
+#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */
+#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */
+
+/* Register: NVMC_ERASEPAGEPARTIALCFG */
+/* Description: Register for partial erase configuration */
+
+/* Bits 6..0 : Duration of the partial erase in milliseconds */
+#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
+#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
+
+
+/* Peripheral: GPIO */
+/* Description: GPIO Port */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register */
+
+/* Bit 31 : Set as output pin 31 */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 30 : Set as output pin 30 */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 29 : Set as output pin 29 */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 28 : Set as output pin 28 */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 27 : Set as output pin 27 */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 26 : Set as output pin 26 */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 25 : Set as output pin 25 */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 24 : Set as output pin 24 */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 23 : Set as output pin 23 */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 22 : Set as output pin 22 */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 21 : Set as output pin 21 */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 20 : Set as output pin 20 */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 19 : Set as output pin 19 */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 18 : Set as output pin 18 */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 17 : Set as output pin 17 */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 16 : Set as output pin 16 */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 15 : Set as output pin 15 */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 14 : Set as output pin 14 */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 13 : Set as output pin 13 */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 12 : Set as output pin 12 */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 11 : Set as output pin 11 */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 10 : Set as output pin 10 */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 9 : Set as output pin 9 */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 8 : Set as output pin 8 */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 7 : Set as output pin 7 */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 6 : Set as output pin 6 */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 5 : Set as output pin 5 */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 4 : Set as output pin 4 */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 3 : Set as output pin 3 */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 2 : Set as output pin 2 */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 1 : Set as output pin 1 */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 0 : Set as output pin 0 */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register */
+
+/* Bit 31 : Set as input pin 31 */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 30 : Set as input pin 30 */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 29 : Set as input pin 29 */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 28 : Set as input pin 28 */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 27 : Set as input pin 27 */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 26 : Set as input pin 26 */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 25 : Set as input pin 25 */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 24 : Set as input pin 24 */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 23 : Set as input pin 23 */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 22 : Set as input pin 22 */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 21 : Set as input pin 21 */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 20 : Set as input pin 20 */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 19 : Set as input pin 19 */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 18 : Set as input pin 18 */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 17 : Set as input pin 17 */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 16 : Set as input pin 16 */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 15 : Set as input pin 15 */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 14 : Set as input pin 14 */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 13 : Set as input pin 13 */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 12 : Set as input pin 12 */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 11 : Set as input pin 11 */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 10 : Set as input pin 10 */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 9 : Set as input pin 9 */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 8 : Set as input pin 8 */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 7 : Set as input pin 7 */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 6 : Set as input pin 6 */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 5 : Set as input pin 5 */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 4 : Set as input pin 4 */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 3 : Set as input pin 3 */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 2 : Set as input pin 2 */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 1 : Set as input pin 1 */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 0 : Set as input pin 0 */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Register: GPIO_LATCH */
+/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
+
+/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
+
+/* Register: GPIO_DETECTMODE */
+/* Description: Select between default DETECT signal behaviour and LDETECT mode */
+
+/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
+#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
+#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Description collection: Configuration of GPIO pins */
+
+/* Bits 17..16 : Pin sensing mechanism */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
+#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
+#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
+
+/* Bits 10..8 : Drive configuration */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
+
+/* Bits 3..2 : Pull configuration */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
+#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
+#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
+
+/* Bit 1 : Connect or disconnect input buffer */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
+
+/* Bit 0 : Pin direction. Same physical register as DIR register */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
+
+
+/* Peripheral: POWER */
+/* Description: Power control */
+
+/* Register: POWER_TASKS_CONSTLAT */
+/* Description: Enable Constant Latency mode */
+
+/* Bit 0 : Enable Constant Latency mode */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: POWER_TASKS_LOWPWR */
+/* Description: Enable Low-power mode (variable latency) */
+
+/* Bit 0 : Enable Low-power mode (variable latency) */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: POWER_EVENTS_POFWARN */
+/* Description: Power failure warning */
+
+/* Bit 0 : Power failure warning */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_SLEEPENTER */
+/* Description: CPU entered WFI/WFE sleep */
+
+/* Bit 0 : CPU entered WFI/WFE sleep */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_SLEEPEXIT */
+/* Description: CPU exited WFI/WFE sleep */
+
+/* Bit 0 : CPU exited WFI/WFE sleep */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
+#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
+#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event POFWARN */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
+
+/* Register: POWER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
+#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
+#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event POFWARN */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason */
+
+/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
+
+/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
+
+/* Bit 3 : Reset from CPU lock-up detected */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
+
+/* Bit 2 : Reset from soft reset detected */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
+
+/* Bit 1 : Reset from watchdog detected */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
+
+/* Bit 0 : Reset from pin-reset detected */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System OFF register */
+
+/* Bit 0 : Enable System OFF mode */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
+
+/* Register: POWER_POFCON */
+/* Description: Power failure comparator configuration */
+
+/* Bits 4..1 : Power failure comparator threshold setting */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
+#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
+#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
+#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
+#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
+#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
+#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
+#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
+#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
+#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
+#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
+#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
+
+/* Bit 0 : Enable or disable power failure comparator */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_GPREGRET2 */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_DCDCEN */
+/* Description: DC/DC enable register */
+
+/* Bit 0 : Enable or disable DC/DC converter */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_RAM_POWER */
+/* Description: Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
+#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
+#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERSET */
+/* Description: Description cluster: RAMn power control set register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERCLR */
+/* Description: Description cluster: RAMn power control clear register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
+
+/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
+
+
+/* Peripheral: PPI */
+/* Description: Programmable Peripheral Interconnect */
+
+/* Register: PPI_TASKS_CHG_EN */
+/* Description: Description cluster: Enable channel group n */
+
+/* Bit 0 : Enable channel group n */
+#define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
+#define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
+#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PPI_TASKS_CHG_DIS */
+/* Description: Description cluster: Disable channel group n */
+
+/* Bit 0 : Disable channel group n */
+#define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
+#define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
+#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable register */
+
+/* Bit 31 : Enable or disable channel 31 */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 30 : Enable or disable channel 30 */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 29 : Enable or disable channel 29 */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 28 : Enable or disable channel 28 */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 27 : Enable or disable channel 27 */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 26 : Enable or disable channel 26 */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 25 : Enable or disable channel 25 */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 24 : Enable or disable channel 24 */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 23 : Enable or disable channel 23 */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 22 : Enable or disable channel 22 */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 21 : Enable or disable channel 21 */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 20 : Enable or disable channel 20 */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 19 : Enable or disable channel 19 */
+#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 18 : Enable or disable channel 18 */
+#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 17 : Enable or disable channel 17 */
+#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 16 : Enable or disable channel 16 */
+#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 15 : Enable or disable channel 15 */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 14 : Enable or disable channel 14 */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 13 : Enable or disable channel 13 */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 12 : Enable or disable channel 12 */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 11 : Enable or disable channel 11 */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 10 : Enable or disable channel 10 */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 9 : Enable or disable channel 9 */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 8 : Enable or disable channel 8 */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 7 : Enable or disable channel 7 */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 6 : Enable or disable channel 6 */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 5 : Enable or disable channel 5 */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 4 : Enable or disable channel 4 */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 3 : Enable or disable channel 3 */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 2 : Enable or disable channel 2 */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 1 : Enable or disable channel 1 */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 0 : Enable or disable channel 0 */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set register */
+
+/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear register */
+
+/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
+
+/* Register: PPI_CH_EEP */
+/* Description: Description cluster: Channel n event end-point */
+
+/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
+#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
+#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
+
+/* Register: PPI_CH_TEP */
+/* Description: Description cluster: Channel n task end-point */
+
+/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
+#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+/* Register: PPI_CHG */
+/* Description: Description collection: Channel group n */
+
+/* Bit 31 : Include or exclude channel 31 */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH31_Included (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude channel 30 */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH30_Included (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude channel 29 */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH29_Included (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude channel 28 */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH28_Included (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude channel 27 */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH27_Included (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude channel 26 */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH26_Included (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude channel 25 */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH25_Included (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude channel 24 */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH24_Included (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude channel 23 */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH23_Included (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude channel 22 */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH22_Included (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude channel 21 */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH21_Included (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude channel 20 */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH20_Included (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude channel 19 */
+#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH19_Included (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude channel 18 */
+#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH18_Included (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude channel 17 */
+#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH17_Included (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude channel 16 */
+#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH16_Included (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude channel 15 */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH15_Included (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude channel 14 */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH14_Included (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude channel 13 */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH13_Included (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude channel 12 */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH12_Included (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude channel 11 */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH11_Included (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude channel 10 */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH10_Included (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude channel 9 */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH9_Included (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude channel 8 */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH8_Included (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude channel 7 */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH7_Included (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude channel 6 */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH6_Included (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude channel 5 */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH5_Included (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude channel 4 */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH4_Included (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude channel 3 */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH3_Included (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude channel 2 */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH2_Included (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude channel 1 */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH1_Included (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude channel 0 */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH0_Included (1UL) /*!< Include */
+
+/* Register: PPI_FORK_TEP */
+/* Description: Description cluster: Channel n task end-point */
+
+/* Bits 31..0 : Pointer to task register */
+#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+
+/* Peripheral: RADIO */
+/* Description: 2.4 GHz radio */
+
+/* Register: RADIO_TASKS_TXEN */
+/* Description: Enable RADIO in TX mode */
+
+/* Bit 0 : Enable RADIO in TX mode */
+#define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
+#define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
+#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_RXEN */
+/* Description: Enable RADIO in RX mode */
+
+/* Bit 0 : Enable RADIO in RX mode */
+#define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
+#define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
+#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_START */
+/* Description: Start RADIO */
+
+/* Bit 0 : Start RADIO */
+#define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_STOP */
+/* Description: Stop RADIO */
+
+/* Bit 0 : Stop RADIO */
+#define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_DISABLE */
+/* Description: Disable RADIO */
+
+/* Bit 0 : Disable RADIO */
+#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
+#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
+#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_RSSISTART */
+/* Description: Start the RSSI and take one single sample of the receive signal strength */
+
+/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */
+#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
+#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
+#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_RSSISTOP */
+/* Description: Stop the RSSI measurement */
+
+/* Bit 0 : Stop the RSSI measurement */
+#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
+#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
+#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_BCSTART */
+/* Description: Start the bit counter */
+
+/* Bit 0 : Start the bit counter */
+#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
+#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
+#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_BCSTOP */
+/* Description: Stop the bit counter */
+
+/* Bit 0 : Stop the bit counter */
+#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
+#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
+#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_EVENTS_READY */
+/* Description: RADIO has ramped up and is ready to be started */
+
+/* Bit 0 : RADIO has ramped up and is ready to be started */
+#define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_ADDRESS */
+/* Description: Address sent or received */
+
+/* Bit 0 : Address sent or received */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_PAYLOAD */
+/* Description: Packet payload sent or received */
+
+/* Bit 0 : Packet payload sent or received */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_END */
+/* Description: Packet sent or received */
+
+/* Bit 0 : Packet sent or received */
+#define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_DISABLED */
+/* Description: RADIO has been disabled */
+
+/* Bit 0 : RADIO has been disabled */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_DEVMATCH */
+/* Description: A device address match occurred on the last received packet */
+
+/* Bit 0 : A device address match occurred on the last received packet */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_DEVMISS */
+/* Description: No device address match occurred on the last received packet */
+
+/* Bit 0 : No device address match occurred on the last received packet */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_RSSIEND */
+/* Description: Sampling of receive signal strength complete */
+
+/* Bit 0 : Sampling of receive signal strength complete */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_BCMATCH */
+/* Description: Bit counter reached bit count value */
+
+/* Bit 0 : Bit counter reached bit count value */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_CRCOK */
+/* Description: Packet received with CRC ok */
+
+/* Bit 0 : Packet received with CRC ok */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_CRCERROR */
+/* Description: Packet received with CRC error */
+
+/* Bit 0 : Packet received with CRC error */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_TXREADY */
+/* Description: RADIO has ramped up and is ready to be started TX path */
+
+/* Bit 0 : RADIO has ramped up and is ready to be started TX path */
+#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */
+#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */
+#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_RXREADY */
+/* Description: RADIO has ramped up and is ready to be started RX path */
+
+/* Bit 0 : RADIO has ramped up and is ready to be started RX path */
+#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */
+#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */
+#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_MHRMATCH */
+/* Description: MAC header match found */
+
+/* Bit 0 : MAC header match found */
+#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */
+#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */
+#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_PHYEND */
+/* Description: Generated when last bit is sent on air */
+
+/* Bit 0 : Generated when last bit is sent on air */
+#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */
+#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */
+#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 21 : Shortcut between event PHYEND and task START */
+#define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */
+#define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */
+#define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 20 : Shortcut between event PHYEND and task DISABLE */
+#define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */
+#define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */
+#define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 19 : Shortcut between event RXREADY and task START */
+#define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */
+#define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */
+#define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 18 : Shortcut between event TXREADY and task START */
+#define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */
+#define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */
+#define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between event END and task START */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event DISABLED and task RXEN */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event DISABLED and task TXEN */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event END and task DISABLE */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event READY and task START */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RADIO_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 27 : Write '1' to enable interrupt for event PHYEND */
+#define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
+#define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
+#define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */
+#define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
+#define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
+#define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 22 : Write '1' to enable interrupt for event RXREADY */
+#define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
+#define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
+#define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */
+
+/* Bit 21 : Write '1' to enable interrupt for event TXREADY */
+#define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
+#define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
+#define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
+#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to enable interrupt for event CRCOK */
+#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event DISABLED */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event END */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event READY */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 27 : Write '1' to disable interrupt for event PHYEND */
+#define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
+#define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
+#define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */
+#define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
+#define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
+#define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 22 : Write '1' to disable interrupt for event RXREADY */
+#define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
+#define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
+#define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 21 : Write '1' to disable interrupt for event TXREADY */
+#define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
+#define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
+#define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
+#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to disable interrupt for event CRCOK */
+#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event DISABLED */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event END */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event READY */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status */
+
+/* Bit 0 : CRC status of packet received */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address */
+
+/* Bits 2..0 : Received address */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: CRC field of previously received packet */
+
+/* Bits 23..0 : CRC field of previously received packet */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index */
+
+/* Bits 2..0 : Device address match index */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_PDUSTAT */
+/* Description: Payload status */
+
+/* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */
+#define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */
+#define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */
+#define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */
+#define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */
+
+/* Register: RADIO_PACKETPTR */
+/* Description: Packet pointer */
+
+/* Bits 31..0 : Packet pointer */
+#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
+#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency */
+
+/* Bit 8 : Channel map selection. */
+#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
+#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
+#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
+#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
+
+/* Bits 6..0 : Radio channel frequency */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power */
+
+/* Bits 7..0 : RADIO output power */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation */
+
+/* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */
+#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration register 0 */
+
+/* Bit 26 : Indicates if LENGTH field contains CRC or not */
+#define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */
+#define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */
+#define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */
+#define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */
+
+/* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */
+#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
+#define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
+#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
+#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
+
+/* Bit 20 : Include or exclude S1 field in RAM */
+#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */
+#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
+
+/* Bits 19..16 : Length on air of S1 field in number of bits. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length on air of S0 field in number of bytes. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length on air of LENGTH field in number of bits. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration register 1 */
+
+/* Bit 25 : Enable or disable packet whitening */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_BASE0 */
+/* Description: Base address 0 */
+
+/* Bits 31..0 : Base address 0 */
+#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
+#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
+
+/* Register: RADIO_BASE1 */
+/* Description: Base address 1 */
+
+/* Bits 31..0 : Base address 1 */
+#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
+#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0-3 */
+
+/* Bits 31..24 : Address prefix 3. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4-7 */
+
+/* Bits 31..24 : Address prefix 7. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select */
+
+/* Bits 2..0 : Transmit address select */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select */
+
+/* Bit 7 : Enable or disable reception on logical address 7. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable reception on logical address 6. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable reception on logical address 5. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable reception on logical address 4. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable reception on logical address 3. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable reception on logical address 2. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable reception on logical address 1. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable reception on logical address 0. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration */
+
+/* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
+
+/* Bits 1..0 : CRC length in number of bytes. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial */
+
+/* Bits 23..0 : CRC polynomial */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value */
+
+/* Bits 23..0 : CRC initial value */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TIFS */
+/* Description: Interframe spacing in us */
+
+/* Bits 9..0 : Interframe spacing in us */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample */
+
+/* Bits 6..0 : RSSI sample */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state */
+
+/* Bits 3..0 : Current radio state */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
+#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
+#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
+#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
+#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
+#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
+#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
+#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
+#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value */
+
+/* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_BCC */
+/* Description: Bit counter compare */
+
+/* Bits 31..0 : Bit counter compare */
+#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
+#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
+
+/* Register: RADIO_DAB */
+/* Description: Description collection: Device address base segment n */
+
+/* Bits 31..0 : Device address base segment n */
+#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
+#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
+
+/* Register: RADIO_DAP */
+/* Description: Description collection: Device address prefix n */
+
+/* Bits 15..0 : Device address prefix n */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration */
+
+/* Bit 15 : TxAdd for device address 7 */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6 */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5 */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4 */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3 */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2 */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1 */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0 */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7 */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
+
+/* Bit 6 : Enable or disable device address matching using device address 6 */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
+
+/* Bit 5 : Enable or disable device address matching using device address 5 */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
+
+/* Bit 4 : Enable or disable device address matching using device address 4 */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
+
+/* Bit 3 : Enable or disable device address matching using device address 3 */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
+
+/* Bit 2 : Enable or disable device address matching using device address 2 */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
+
+/* Bit 1 : Enable or disable device address matching using device address 1 */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable device address matching using device address 0 */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
+
+/* Register: RADIO_MODECNF0 */
+/* Description: Radio mode configuration register 0 */
+
+/* Bits 9..8 : Default TX value */
+#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
+#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
+#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
+#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
+#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
+
+/* Bit 0 : Radio ramp-up time */
+#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
+#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
+#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */
+#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control */
+
+/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator */
+
+/* Register: RNG_TASKS_START */
+/* Description: Task starting the random number generator */
+
+/* Bit 0 : Task starting the random number generator */
+#define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RNG_TASKS_STOP */
+/* Description: Task stopping the random number generator */
+
+/* Bit 0 : Task stopping the random number generator */
+#define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RNG_EVENTS_VALRDY */
+/* Description: Event being generated for every new random number written to the VALUE register */
+
+/* Bit 0 : Event being generated for every new random number written to the VALUE register */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 0 : Shortcut between event VALRDY and task STOP */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RNG_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to enable interrupt for event VALRDY */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
+
+/* Register: RNG_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to disable interrupt for event VALRDY */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 0 : Bias correction */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
+
+/* Register: RNG_VALUE */
+/* Description: Output random number */
+
+/* Bits 7..0 : Generated random number */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0 */
+
+/* Register: RTC_TASKS_START */
+/* Description: Start RTC COUNTER */
+
+/* Bit 0 : Start RTC COUNTER */
+#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_STOP */
+/* Description: Stop RTC COUNTER */
+
+/* Bit 0 : Stop RTC COUNTER */
+#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_CLEAR */
+/* Description: Clear RTC COUNTER */
+
+/* Bit 0 : Clear RTC COUNTER */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_TRIGOVRFLW */
+/* Description: Set COUNTER to 0xFFFFF0 */
+
+/* Bit 0 : Set COUNTER to 0xFFFFF0 */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_EVENTS_TICK */
+/* Description: Event on COUNTER increment */
+
+/* Bit 0 : Event on COUNTER increment */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
+#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_EVENTS_OVRFLW */
+/* Description: Event on COUNTER overflow */
+
+/* Bit 0 : Event on COUNTER overflow */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_EVENTS_COMPARE */
+/* Description: Description collection: Compare event on CC[n] match */
+
+/* Bit 0 : Compare event on CC[n] match */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event TICK */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event TICK */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_EVTEN */
+/* Description: Enable or disable event routing */
+
+/* Bit 19 : Enable or disable event routing for event COMPARE[3] */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */
+
+/* Bit 18 : Enable or disable event routing for event COMPARE[2] */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */
+
+/* Bit 17 : Enable or disable event routing for event COMPARE[1] */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */
+
+/* Bit 16 : Enable or disable event routing for event COMPARE[0] */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */
+
+/* Bit 1 : Enable or disable event routing for event OVRFLW */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */
+
+/* Bit 0 : Enable or disable event routing for event TICK */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable event routing */
+
+/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable event routing for event OVRFLW */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable event routing for event TICK */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable event routing */
+
+/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable event routing for event OVRFLW */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable event routing for event TICK */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value */
+
+/* Bits 23..0 : Counter value */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
+
+/* Bits 11..0 : Prescaler value */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Description collection: Compare register n */
+
+/* Bits 23..0 : Compare value */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+
+/* Peripheral: SAADC */
+/* Description: Analog to Digital Converter */
+
+/* Register: SAADC_TASKS_START */
+/* Description: Start the ADC and prepare the result buffer in RAM */
+
+/* Bit 0 : Start the ADC and prepare the result buffer in RAM */
+#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_SAMPLE */
+/* Description: Take one ADC sample, if scan is enabled all channels are sampled */
+
+/* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_STOP */
+/* Description: Stop the ADC and terminate any on-going conversion */
+
+/* Bit 0 : Stop the ADC and terminate any on-going conversion */
+#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_CALIBRATEOFFSET */
+/* Description: Starts offset auto-calibration */
+
+/* Bit 0 : Starts offset auto-calibration */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_EVENTS_STARTED */
+/* Description: The ADC has started */
+
+/* Bit 0 : The ADC has started */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_END */
+/* Description: The ADC has filled up the Result buffer */
+
+/* Bit 0 : The ADC has filled up the Result buffer */
+#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_DONE */
+/* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
+
+/* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_RESULTDONE */
+/* Description: A result is ready to get transferred to RAM. */
+
+/* Bit 0 : A result is ready to get transferred to RAM. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CALIBRATEDONE */
+/* Description: Calibration is complete */
+
+/* Bit 0 : Calibration is complete */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_STOPPED */
+/* Description: The ADC has stopped */
+
+/* Bit 0 : The ADC has stopped */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CH_LIMITH */
+/* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */
+
+/* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CH_LIMITL */
+/* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */
+
+/* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
+#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
+#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
+#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
+#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
+#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
+#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
+#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
+#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
+#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
+#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
+#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
+#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
+#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
+#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
+#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
+#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event STOPPED */
+#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
+#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event RESULTDONE */
+#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event DONE */
+#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event END */
+#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event STARTED */
+#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
+#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
+#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
+#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
+#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
+#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
+#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
+#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
+#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
+#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
+#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
+#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
+#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
+#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
+#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
+#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
+#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event STOPPED */
+#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
+#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
+#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event DONE */
+#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event END */
+#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event STARTED */
+#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
+#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
+#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
+#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
+#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
+#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
+#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
+#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
+#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
+#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
+#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
+#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
+#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
+#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
+#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
+#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
+#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event STOPPED */
+#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
+#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
+#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event DONE */
+#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event END */
+#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event STARTED */
+#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: SAADC_STATUS */
+/* Description: Status */
+
+/* Bit 0 : Status */
+#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
+#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
+
+/* Register: SAADC_ENABLE */
+/* Description: Enable or disable ADC */
+
+/* Bit 0 : Enable or disable ADC */
+#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
+#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
+
+/* Register: SAADC_CH_PSELP */
+/* Description: Description cluster: Input positive pin selection for CH[n] */
+
+/* Bits 4..0 : Analog positive input channel */
+#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
+
+/* Register: SAADC_CH_PSELN */
+/* Description: Description cluster: Input negative pin selection for CH[n] */
+
+/* Bits 4..0 : Analog negative input, enables differential channel */
+#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
+
+/* Register: SAADC_CH_CONFIG */
+/* Description: Description cluster: Input configuration for CH[n] */
+
+/* Bit 24 : Enable burst mode */
+#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
+#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
+
+/* Bit 20 : Enable differential mode */
+#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
+#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
+#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
+
+/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
+#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
+#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
+#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
+#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
+#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
+#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
+
+/* Bit 12 : Reference control */
+#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
+#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
+
+/* Bits 10..8 : Gain control */
+#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
+#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
+#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
+#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
+
+/* Bits 5..4 : Negative channel resistor control */
+#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Bits 1..0 : Positive channel resistor control */
+#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Register: SAADC_CH_LIMIT */
+/* Description: Description cluster: High/low limits for event monitoring a channel */
+
+/* Bits 31..16 : High level limit */
+#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
+#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
+
+/* Bits 15..0 : Low level limit */
+#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
+#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
+
+/* Register: SAADC_RESOLUTION */
+/* Description: Resolution configuration */
+
+/* Bits 2..0 : Set the resolution */
+#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
+#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
+#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
+#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
+#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
+#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
+
+/* Register: SAADC_OVERSAMPLE */
+/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
+
+/* Bits 3..0 : Oversample control */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
+
+/* Register: SAADC_SAMPLERATE */
+/* Description: Controls normal or continuous sample rate */
+
+/* Bit 12 : Select mode for sample rate control */
+#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
+#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
+
+/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
+#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
+#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
+
+/* Register: SAADC_RESULT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SAADC_RESULT_MAXCNT */
+/* Description: Maximum number of buffer words to transfer */
+
+/* Bits 14..0 : Maximum number of buffer words to transfer */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SAADC_RESULT_AMOUNT */
+/* Description: Number of buffer words transferred since last START */
+
+/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: SPI */
+/* Description: Serial Peripheral Interface */
+
+/* Register: SPI_EVENTS_READY */
+/* Description: TXD byte sent and RXD byte received */
+
+/* Bit 0 : TXD byte sent and RXD byte received */
+#define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: SPI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to enable interrupt for event READY */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: SPI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to disable interrupt for event READY */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI */
+
+/* Bits 3..0 : Enable or disable SPI */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
+#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
+
+/* Register: SPI_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received. Double buffered */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to send. Double buffered */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+
+/* Peripheral: SPIM */
+/* Description: Serial Peripheral Interface Master with EasyDMA */
+
+/* Register: SPIM_TASKS_START */
+/* Description: Start SPI transaction */
+
+/* Bit 0 : Start SPI transaction */
+#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_STOP */
+/* Description: Stop SPI transaction */
+
+/* Bit 0 : Stop SPI transaction */
+#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_SUSPEND */
+/* Description: Suspend SPI transaction */
+
+/* Bit 0 : Suspend SPI transaction */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_RESUME */
+/* Description: Resume SPI transaction */
+
+/* Bit 0 : Resume SPI transaction */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_EVENTS_STOPPED */
+/* Description: SPI transaction has stopped */
+
+/* Bit 0 : SPI transaction has stopped */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_ENDRX */
+/* Description: End of RXD buffer reached */
+
+/* Bit 0 : End of RXD buffer reached */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_END */
+/* Description: End of RXD buffer and TXD buffer reached */
+
+/* Bit 0 : End of RXD buffer and TXD buffer reached */
+#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_ENDTX */
+/* Description: End of TXD buffer reached */
+
+/* Bit 0 : End of TXD buffer reached */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_STARTED */
+/* Description: Transaction started */
+
+/* Bit 0 : Transaction started */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 17 : Shortcut between event END and task START */
+#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
+#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to enable interrupt for event STARTED */
+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event ENDTX */
+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event END */
+#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: SPIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to disable interrupt for event STARTED */
+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event ENDTX */
+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event END */
+#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: SPIM_ENABLE */
+/* Description: Enable SPIM */
+
+/* Bits 3..0 : Enable or disable SPIM */
+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
+#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
+
+/* Register: SPIM_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_FREQUENCY */
+/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 13..0 : Maximum number of bytes in receive buffer */
+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 13..0 : Number of bytes transferred in the last transaction */
+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 13..0 : Maximum number of bytes in transmit buffer */
+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 13..0 : Number of bytes transferred in the last transaction */
+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIM_ORC */
+/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
+
+/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI Slave */
+
+/* Register: SPIS_TASKS_ACQUIRE */
+/* Description: Acquire SPI semaphore */
+
+/* Bit 0 : Acquire SPI semaphore */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIS_TASKS_RELEASE */
+/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
+
+/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIS_EVENTS_END */
+/* Description: Granted transaction completed */
+
+/* Bit 0 : Granted transaction completed */
+#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_EVENTS_ENDRX */
+/* Description: End of RXD buffer reached */
+
+/* Bit 0 : End of RXD buffer reached */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_EVENTS_ACQUIRED */
+/* Description: Semaphore acquired */
+
+/* Bit 0 : Semaphore acquired */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 2 : Shortcut between event END and task ACQUIRE */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event END */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event END */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status register */
+
+/* Bits 1..0 : Semaphore status */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction */
+
+/* Bit 1 : RX buffer overflow detected, and prevented */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 0 : TX buffer over-read detected, and prevented */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPI slave */
+
+/* Bits 3..0 : Enable or disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
+
+/* Register: SPIS_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_CSN */
+/* Description: Pin select for CSN signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_RXD_PTR */
+/* Description: RXD data pointer */
+
+/* Bits 31..0 : RXD data pointer */
+#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 13..0 : Maximum number of bytes in receive buffer */
+#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_RXD_AMOUNT */
+/* Description: Number of bytes received in last granted transaction */
+
+/* Bits 13..0 : Number of bytes received in the last granted transaction */
+#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIS_TXD_PTR */
+/* Description: TXD data pointer */
+
+/* Bits 31..0 : TXD data pointer */
+#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 13..0 : Maximum number of bytes in transmit buffer */
+#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_TXD_AMOUNT */
+/* Description: Number of bytes transmitted in last granted transaction */
+
+/* Bits 13..0 : Number of bytes transmitted in last granted transaction */
+#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. Character clocked out in case of an ignored transaction. */
+
+/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character */
+
+/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor */
+
+/* Register: TEMP_TASKS_START */
+/* Description: Start temperature measurement */
+
+/* Bit 0 : Start temperature measurement */
+#define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TEMP_TASKS_STOP */
+/* Description: Stop temperature measurement */
+
+/* Bit 0 : Stop temperature measurement */
+#define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TEMP_EVENTS_DATARDY */
+/* Description: Temperature measurement complete, data ready */
+
+/* Bit 0 : Temperature measurement complete, data ready */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
+
+/* Register: TEMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to enable interrupt for event DATARDY */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to disable interrupt for event DATARDY */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
+
+/* Register: TEMP_TEMP */
+/* Description: Temperature in degC (0.25deg steps) */
+
+/* Bits 31..0 : Temperature in degC (0.25deg steps) */
+#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
+#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
+
+/* Register: TEMP_A0 */
+/* Description: Slope of 1st piece wise linear function */
+
+/* Bits 11..0 : Slope of 1st piece wise linear function */
+#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
+#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
+
+/* Register: TEMP_A1 */
+/* Description: Slope of 2nd piece wise linear function */
+
+/* Bits 11..0 : Slope of 2nd piece wise linear function */
+#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
+#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
+
+/* Register: TEMP_A2 */
+/* Description: Slope of 3rd piece wise linear function */
+
+/* Bits 11..0 : Slope of 3rd piece wise linear function */
+#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
+#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
+
+/* Register: TEMP_A3 */
+/* Description: Slope of 4th piece wise linear function */
+
+/* Bits 11..0 : Slope of 4th piece wise linear function */
+#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
+#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
+
+/* Register: TEMP_A4 */
+/* Description: Slope of 5th piece wise linear function */
+
+/* Bits 11..0 : Slope of 5th piece wise linear function */
+#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
+#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
+
+/* Register: TEMP_A5 */
+/* Description: Slope of 6th piece wise linear function */
+
+/* Bits 11..0 : Slope of 6th piece wise linear function */
+#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
+#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
+
+/* Register: TEMP_B0 */
+/* Description: y-intercept of 1st piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 1st piece wise linear function */
+#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
+#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
+
+/* Register: TEMP_B1 */
+/* Description: y-intercept of 2nd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 2nd piece wise linear function */
+#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
+#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
+
+/* Register: TEMP_B2 */
+/* Description: y-intercept of 3rd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 3rd piece wise linear function */
+#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
+#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
+
+/* Register: TEMP_B3 */
+/* Description: y-intercept of 4th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 4th piece wise linear function */
+#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
+#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
+
+/* Register: TEMP_B4 */
+/* Description: y-intercept of 5th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 5th piece wise linear function */
+#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
+#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
+
+/* Register: TEMP_B5 */
+/* Description: y-intercept of 6th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 6th piece wise linear function */
+#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
+#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
+
+/* Register: TEMP_T0 */
+/* Description: End point of 1st piece wise linear function */
+
+/* Bits 7..0 : End point of 1st piece wise linear function */
+#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
+#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
+
+/* Register: TEMP_T1 */
+/* Description: End point of 2nd piece wise linear function */
+
+/* Bits 7..0 : End point of 2nd piece wise linear function */
+#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
+#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
+
+/* Register: TEMP_T2 */
+/* Description: End point of 3rd piece wise linear function */
+
+/* Bits 7..0 : End point of 3rd piece wise linear function */
+#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
+#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
+
+/* Register: TEMP_T3 */
+/* Description: End point of 4th piece wise linear function */
+
+/* Bits 7..0 : End point of 4th piece wise linear function */
+#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
+#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
+
+/* Register: TEMP_T4 */
+/* Description: End point of 5th piece wise linear function */
+
+/* Bits 7..0 : End point of 5th piece wise linear function */
+#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
+#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer/Counter 0 */
+
+/* Register: TIMER_TASKS_START */
+/* Description: Start Timer */
+
+/* Bit 0 : Start Timer */
+#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_STOP */
+/* Description: Stop Timer */
+
+/* Bit 0 : Stop Timer */
+#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_COUNT */
+/* Description: Increment Timer (Counter mode only) */
+
+/* Bit 0 : Increment Timer (Counter mode only) */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_CLEAR */
+/* Description: Clear time */
+
+/* Bit 0 : Clear time */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_SHUTDOWN */
+/* Description: Deprecated register - Shut down timer */
+
+/* Bit 0 : Deprecated field - Shut down timer */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_CAPTURE */
+/* Description: Description collection: Capture Timer value to CC[n] register */
+
+/* Bit 0 : Capture Timer value to CC[n] register */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_EVENTS_COMPARE */
+/* Description: Description collection: Compare event on CC[n] match */
+
+/* Bit 0 : Compare event on CC[n] match */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
+#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
+#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TIMER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
+#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
+#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
+#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
+#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Register: TIMER_MODE */
+/* Description: Timer mode selection */
+
+/* Bits 1..0 : Timer mode */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
+#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
+
+/* Register: TIMER_BITMODE */
+/* Description: Configure the number of bits used by the TIMER */
+
+/* Bits 1..0 : Timer bit width */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
+
+/* Register: TIMER_PRESCALER */
+/* Description: Timer prescaler register */
+
+/* Bits 3..0 : Prescaler value */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_CC */
+/* Description: Description collection: Capture/Compare register n */
+
+/* Bits 31..0 : Capture/Compare value */
+#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
+#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
+
+
+/* Peripheral: TWI */
+/* Description: I2C compatible Two-Wire Interface */
+
+/* Register: TWI_TASKS_STARTRX */
+/* Description: Start TWI receive sequence */
+
+/* Bit 0 : Start TWI receive sequence */
+#define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_STARTTX */
+/* Description: Start TWI transmit sequence */
+
+/* Bit 0 : Start TWI transmit sequence */
+#define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_STOP */
+/* Description: Stop TWI transaction */
+
+/* Bit 0 : Stop TWI transaction */
+#define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_RXDREADY */
+/* Description: TWI RXD byte received */
+
+/* Bit 0 : TWI RXD byte received */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_TXDSENT */
+/* Description: TWI TXD byte sent */
+
+/* Bit 0 : TWI TXD byte sent */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_BB */
+/* Description: TWI byte boundary, generated before each byte that is sent or received */
+
+/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */
+#define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */
+#define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */
+#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_SUSPENDED */
+/* Description: TWI entered the suspended state */
+
+/* Bit 0 : TWI entered the suspended state */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 1 : Shortcut between event BB and task STOP */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event BB and task SUSPEND */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event BB */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event BB */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable TWI */
+
+/* Bits 3..0 : Enable or disable TWI */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
+#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
+
+/* Register: TWI_PSEL_SCL */
+/* Description: Pin select for SCL */
+
+/* Bit 31 : Connection */
+#define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWI_PSEL_SDA */
+/* Description: Pin select for SDA */
+
+/* Bit 31 : Connection */
+#define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RXD register */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TXD register */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIM */
+/* Description: I2C compatible Two-Wire Master Interface with EasyDMA */
+
+/* Register: TWIM_TASKS_STARTRX */
+/* Description: Start TWI receive sequence */
+
+/* Bit 0 : Start TWI receive sequence */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_STARTTX */
+/* Description: Start TWI transmit sequence */
+
+/* Bit 0 : Start TWI transmit sequence */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_STOP */
+/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
+
+/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_SUSPENDED */
+/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
+
+/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_RXSTARTED */
+/* Description: Receive sequence started */
+
+/* Bit 0 : Receive sequence started */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_TXSTARTED */
+/* Description: Transmit sequence started */
+
+/* Bit 0 : Transmit sequence started */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_LASTRX */
+/* Description: Byte boundary, starting to receive the last byte */
+
+/* Bit 0 : Byte boundary, starting to receive the last byte */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_LASTTX */
+/* Description: Byte boundary, starting to transmit the last byte */
+
+/* Bit 0 : Byte boundary, starting to transmit the last byte */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 12 : Shortcut between event LASTRX and task STOP */
+#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */
+#define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */
+#define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */
+#define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between event LASTRX and task STARTTX */
+#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between event LASTTX and task STOP */
+#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 7 : Shortcut between event LASTTX and task STARTRX */
+#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 24 : Enable or disable interrupt for event LASTTX */
+#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for event LASTRX */
+#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
+#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
+#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for event SUSPENDED */
+#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event ERROR */
+#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
+#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 24 : Write '1' to enable interrupt for event LASTTX */
+#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to enable interrupt for event LASTRX */
+#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
+#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
+#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
+#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 24 : Write '1' to disable interrupt for event LASTTX */
+#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to disable interrupt for event LASTRX */
+#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
+#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
+#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
+#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIM_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : Overrun error */
+#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
+
+/* Register: TWIM_ENABLE */
+/* Description: Enable TWIM */
+
+/* Bits 3..0 : Enable or disable TWIM */
+#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
+#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
+
+/* Register: TWIM_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_FREQUENCY */
+/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
+
+/* Register: TWIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 13..0 : Maximum number of bytes in receive buffer */
+#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 13..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 13..0 : Maximum number of bytes in transmit buffer */
+#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 13..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIS */
+/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA */
+
+/* Register: TWIS_TASKS_STOP */
+/* Description: Stop TWI transaction */
+
+/* Bit 0 : Stop TWI transaction */
+#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_PREPARERX */
+/* Description: Prepare the TWI slave to respond to a write command */
+
+/* Bit 0 : Prepare the TWI slave to respond to a write command */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_PREPARETX */
+/* Description: Prepare the TWI slave to respond to a read command */
+
+/* Bit 0 : Prepare the TWI slave to respond to a read command */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_RXSTARTED */
+/* Description: Receive sequence started */
+
+/* Bit 0 : Receive sequence started */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_TXSTARTED */
+/* Description: Transmit sequence started */
+
+/* Bit 0 : Transmit sequence started */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_WRITE */
+/* Description: Write command received */
+
+/* Bit 0 : Write command received */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_READ */
+/* Description: Read command received */
+
+/* Bit 0 : Read command received */
+#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
+#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
+#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 14 : Shortcut between event READ and task SUSPEND */
+#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between event WRITE and task SUSPEND */
+#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIS_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 26 : Enable or disable interrupt for event READ */
+#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for event WRITE */
+#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
+#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
+#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event ERROR */
+#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
+#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 26 : Write '1' to enable interrupt for event READ */
+#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to enable interrupt for event WRITE */
+#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
+#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
+#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 26 : Write '1' to disable interrupt for event READ */
+#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to disable interrupt for event WRITE */
+#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
+#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
+#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIS_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : TX buffer over-read detected, and prevented */
+#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
+
+/* Bit 2 : NACK sent after receiving a data byte */
+#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : RX buffer overflow detected, and prevented */
+#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
+
+/* Register: TWIS_MATCH */
+/* Description: Status register indicating which address had a match */
+
+/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
+#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
+#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
+
+/* Register: TWIS_ENABLE */
+/* Description: Enable TWIS */
+
+/* Bits 3..0 : Enable or disable TWIS */
+#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
+#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
+
+/* Register: TWIS_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_RXD_PTR */
+/* Description: RXD Data pointer */
+
+/* Bits 31..0 : RXD Data pointer */
+#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in RXD buffer */
+
+/* Bits 13..0 : Maximum number of bytes in RXD buffer */
+#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last RXD transaction */
+
+/* Bits 13..0 : Number of bytes transferred in the last RXD transaction */
+#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIS_TXD_PTR */
+/* Description: TXD Data pointer */
+
+/* Bits 31..0 : TXD Data pointer */
+#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in TXD buffer */
+
+/* Bits 13..0 : Maximum number of bytes in TXD buffer */
+#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last TXD transaction */
+
+/* Bits 13..0 : Number of bytes transferred in the last TXD transaction */
+#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIS_ADDRESS */
+/* Description: Description collection: TWI slave address n */
+
+/* Bits 6..0 : TWI slave address */
+#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWIS_CONFIG */
+/* Description: Configuration register for the address match mechanism */
+
+/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
+#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
+#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
+
+/* Register: TWIS_ORC */
+/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+
+/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter */
+
+/* Register: UART_TASKS_STARTRX */
+/* Description: Start UART receiver */
+
+/* Bit 0 : Start UART receiver */
+#define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_STOPRX */
+/* Description: Stop UART receiver */
+
+/* Bit 0 : Stop UART receiver */
+#define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
+#define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
+#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_STARTTX */
+/* Description: Start UART transmitter */
+
+/* Bit 0 : Start UART transmitter */
+#define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_STOPTX */
+/* Description: Stop UART transmitter */
+
+/* Bit 0 : Stop UART transmitter */
+#define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
+#define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
+#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_SUSPEND */
+/* Description: Suspend UART */
+
+/* Bit 0 : Suspend UART */
+#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_EVENTS_CTS */
+/* Description: CTS is activated (set low). Clear To Send. */
+
+/* Bit 0 : CTS is activated (set low). Clear To Send. */
+#define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
+#define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
+#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_NCTS */
+/* Description: CTS is deactivated (set high). Not Clear To Send. */
+
+/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_RXDRDY */
+/* Description: Data received in RXD */
+
+/* Bit 0 : Data received in RXD */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_TXDRDY */
+/* Description: Data sent from TXD */
+
+/* Bit 0 : Data sent from TXD */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_ERROR */
+/* Description: Error detected */
+
+/* Bit 0 : Error detected */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_RXTO */
+/* Description: Receiver timeout */
+
+/* Bit 0 : Receiver timeout */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 4 : Shortcut between event NCTS and task STOPRX */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event CTS and task STARTRX */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UART_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 17 : Write '1' to enable interrupt for event RXTO */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event NCTS */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event CTS */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UART_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 17 : Write '1' to disable interrupt for event RXTO */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event NCTS */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event CTS */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : Break condition */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UART */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
+#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
+
+/* Register: UART_PSEL_RTS */
+/* Description: Pin select for RTS */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_TXD */
+/* Description: Pin select for TXD */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_CTS */
+/* Description: Pin select for CTS */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_RXD */
+/* Description: Pin select for RXD */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received in previous transfers, double buffered */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to be transferred */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
+#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
+#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bit 4 : Stop bits */
+#define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
+#define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
+#define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */
+#define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
+
+/* Bits 3..1 : Parity */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UARTE */
+/* Description: UART with EasyDMA */
+
+/* Register: UARTE_TASKS_STARTRX */
+/* Description: Start UART receiver */
+
+/* Bit 0 : Start UART receiver */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STOPRX */
+/* Description: Stop UART receiver */
+
+/* Bit 0 : Stop UART receiver */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STARTTX */
+/* Description: Start UART transmitter */
+
+/* Bit 0 : Start UART transmitter */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STOPTX */
+/* Description: Stop UART transmitter */
+
+/* Bit 0 : Stop UART transmitter */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_FLUSHRX */
+/* Description: Flush RX FIFO into RX buffer */
+
+/* Bit 0 : Flush RX FIFO into RX buffer */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_EVENTS_CTS */
+/* Description: CTS is activated (set low). Clear To Send. */
+
+/* Bit 0 : CTS is activated (set low). Clear To Send. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_NCTS */
+/* Description: CTS is deactivated (set high). Not Clear To Send. */
+
+/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXDRDY */
+/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
+
+/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ENDRX */
+/* Description: Receive buffer is filled up */
+
+/* Bit 0 : Receive buffer is filled up */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXDRDY */
+/* Description: Data sent from TXD */
+
+/* Bit 0 : Data sent from TXD */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ENDTX */
+/* Description: Last TX byte transmitted */
+
+/* Bit 0 : Last TX byte transmitted */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ERROR */
+/* Description: Error detected */
+
+/* Bit 0 : Error detected */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXTO */
+/* Description: Receiver timeout */
+
+/* Bit 0 : Receiver timeout */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXSTARTED */
+/* Description: UART receiver has started */
+
+/* Bit 0 : UART receiver has started */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXSTARTED */
+/* Description: UART transmitter has started */
+
+/* Bit 0 : UART transmitter has started */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXSTOPPED */
+/* Description: Transmitter stopped */
+
+/* Bit 0 : Transmitter stopped */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 6 : Shortcut between event ENDRX and task STOPRX */
+#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between event ENDRX and task STARTRX */
+#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UARTE_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
+#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
+#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
+#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for event RXTO */
+#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event ERROR */
+#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for event ENDTX */
+#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event TXDRDY */
+#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event ENDRX */
+#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event RXDRDY */
+#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event NCTS */
+#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event CTS */
+#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
+#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
+#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
+#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event RXTO */
+#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event ENDTX */
+#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
+#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
+#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
+#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event NCTS */
+#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event CTS */
+#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
+#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
+#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
+#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event RXTO */
+#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event ENDTX */
+#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
+#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
+#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
+#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event NCTS */
+#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event CTS */
+#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UARTE_ERRORSRC */
+/* Description: Error source Note : this register is read / write one to clear. */
+
+/* Bit 3 : Break condition */
+#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UARTE_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UARTE */
+#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
+#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
+
+/* Register: UARTE_PSEL_RTS */
+/* Description: Pin select for RTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_TXD */
+/* Description: Pin select for TXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_CTS */
+/* Description: Pin select for CTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_RXD */
+/* Description: Pin select for RXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UARTE_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 9..0 : Maximum number of bytes in receive buffer */
+#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 9..0 : Maximum number of bytes in transmit buffer */
+#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bit 4 : Stop bits */
+#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
+#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
+#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
+#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
+
+/* Bits 3..1 : Parity */
+#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UICR */
+/* Description: User information configuration registers */
+
+/* Register: UICR_NRFFW */
+/* Description: Description collection: Reserved for Nordic firmware design */
+
+/* Bits 31..0 : Reserved for Nordic firmware design */
+#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
+#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
+
+/* Register: UICR_NRFHW */
+/* Description: Description collection: Reserved for Nordic hardware design */
+
+/* Bits 31..0 : Reserved for Nordic hardware design */
+#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
+#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
+
+/* Register: UICR_CUSTOMER */
+/* Description: Description collection: Reserved for customer */
+
+/* Bits 31..0 : Reserved for customer */
+#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
+#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
+
+/* Register: UICR_PSELRESET */
+/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */
+
+/* Bit 31 : Connection */
+#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
+#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : GPIO pin number onto which nRESET is exposed */
+#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UICR_APPROTECT */
+/* Description: Access port protection */
+
+/* Bits 7..0 : Enable or disable access port protection. */
+#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
+#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
+#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer */
+
+/* Register: WDT_TASKS_START */
+/* Description: Start the watchdog */
+
+/* Bit 0 : Start the watchdog */
+#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: WDT_EVENTS_TIMEOUT */
+/* Description: Watchdog timeout */
+
+/* Bit 0 : Watchdog timeout */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
+
+/* Register: WDT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
+
+/* Register: WDT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Run status */
+
+/* Bit 0 : Indicates whether or not the watchdog is running */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status */
+
+/* Bit 7 : Request status for RR[7] register */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
+
+/* Bit 6 : Request status for RR[6] register */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
+
+/* Bit 5 : Request status for RR[5] register */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
+
+/* Bit 4 : Request status for RR[4] register */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
+
+/* Bit 3 : Request status for RR[3] register */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
+
+/* Bit 2 : Request status for RR[2] register */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
+
+/* Bit 1 : Request status for RR[1] register */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
+
+/* Bit 0 : Request status for RR[0] register */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
+
+/* Register: WDT_CRV */
+/* Description: Counter reload value */
+
+/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
+#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
+#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
+
+/* Register: WDT_RREN */
+/* Description: Enable register for reload request registers */
+
+/* Bit 7 : Enable or disable RR[7] register */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
+
+/* Bit 6 : Enable or disable RR[6] register */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
+
+/* Bit 5 : Enable or disable RR[5] register */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
+
+/* Bit 4 : Enable or disable RR[4] register */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
+
+/* Bit 3 : Enable or disable RR[3] register */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
+
+/* Bit 2 : Enable or disable RR[2] register */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
+
+/* Bit 1 : Enable or disable RR[1] register */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
+
+/* Bit 0 : Enable or disable RR[0] register */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
+
+/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
+
+/* Register: WDT_RR */
+/* Description: Description collection: Reload request n */
+
+/* Bits 31..0 : Reload request register */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
+
+
+/*lint --flb "Leave library region" */
+#endif
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52805_peripherals.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52805_peripherals.h
new file mode 100644
index 000000000..5c5beec2b
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52805_peripherals.h
@@ -0,0 +1,209 @@
+/*
+
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _NRF52805_PERIPHERALS_H
+#define _NRF52805_PERIPHERALS_H
+
+
+/* Clock Peripheral */
+#define CLOCK_PRESENT
+#define CLOCK_COUNT 1
+
+/* Power Peripheral */
+#define POWER_PRESENT
+#define POWER_COUNT 1
+
+#define POWER_FEATURE_RAM_REGISTERS_PRESENT
+#define POWER_FEATURE_RAM_REGISTERS_COUNT 3
+
+/* Systick timer */
+#define SYSTICK_PRESENT
+#define SYSTICK_COUNT 1
+
+/* Software Interrupts */
+#define SWI_PRESENT
+#define SWI_COUNT 6
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 1
+
+#define P0_PIN_NUM 32
+
+/* MPU and BPROT */
+#define BPROT_PRESENT
+
+#define BPROT_REGIONS_SIZE 4096
+#define BPROT_REGIONS_NUM 48
+
+/* Radio */
+#define RADIO_PRESENT
+#define RADIO_COUNT 1
+
+#define RADIO_EASYDMA_MAXCNT_SIZE 8
+
+/* Accelerated Address Resolver */
+#define AAR_PRESENT
+#define AAR_COUNT 1
+
+#define AAR_MAX_IRK_NUM 16
+
+/* AES Electronic CodeBook mode encryption */
+#define ECB_PRESENT
+#define ECB_COUNT 1
+
+/* AES CCM mode encryption */
+#define CCM_PRESENT
+#define CCM_COUNT 1
+
+/* Peripheral to Peripheral Interconnect */
+#define PPI_PRESENT
+#define PPI_COUNT 1
+
+#define PPI_CH_NUM 10
+#define PPI_FIXED_CH_NUM 12
+#define PPI_GROUP_NUM 6
+#define PPI_FEATURE_FORKS_PRESENT
+
+/* Event Generator Unit */
+#define EGU_PRESENT
+#define EGU_COUNT 2
+
+#define EGU0_CH_NUM 16
+#define EGU1_CH_NUM 16
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 3
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 32
+#define TIMER2_MAX_SIZE 32
+
+#define TIMER0_CC_NUM 4
+#define TIMER1_CC_NUM 4
+#define TIMER2_CC_NUM 4
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 2
+
+#define RTC0_CC_NUM 3
+#define RTC1_CC_NUM 4
+
+/* RNG */
+#define RNG_PRESENT
+#define RNG_COUNT 1
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 1
+
+/* Temperature Sensor */
+#define TEMP_PRESENT
+#define TEMP_COUNT 1
+
+/* Serial Peripheral Interface Master */
+#define SPI_PRESENT
+#define SPI_COUNT 2
+
+/* Serial Peripheral Interface Master with DMA */
+#define SPIM_PRESENT
+#define SPIM_COUNT 2
+
+#define SPIM0_MAX_DATARATE 8
+#define SPIM1_MAX_DATARATE 8
+
+#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
+#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
+
+#define SPIM0_FEATURE_DCX_PRESENT 0
+#define SPIM1_FEATURE_DCX_PRESENT 0
+
+#define SPIM0_FEATURE_RXDELAY_PRESENT 0
+#define SPIM1_FEATURE_RXDELAY_PRESENT 0
+
+#define SPIM0_EASYDMA_MAXCNT_SIZE 14
+#define SPIM1_EASYDMA_MAXCNT_SIZE 14
+
+/* Serial Peripheral Interface Slave with DMA*/
+#define SPIS_PRESENT
+#define SPIS_COUNT 2
+
+#define SPIS0_EASYDMA_MAXCNT_SIZE 14
+#define SPIS1_EASYDMA_MAXCNT_SIZE 14
+
+/* Two Wire Interface Master */
+#define TWI_PRESENT
+#define TWI_COUNT 1
+
+/* Two Wire Interface Master with DMA */
+#define TWIM_PRESENT
+#define TWIM_COUNT 1
+
+#define TWIM0_EASYDMA_MAXCNT_SIZE 14
+
+/* Two Wire Interface Slave with DMA */
+#define TWIS_PRESENT
+#define TWIS_COUNT 1
+
+#define TWIS0_EASYDMA_MAXCNT_SIZE 14
+
+/* Universal Asynchronous Receiver-Transmitter */
+#define UART_PRESENT
+#define UART_COUNT 1
+
+/* Universal Asynchronous Receiver-Transmitter with DMA */
+#define UARTE_PRESENT
+#define UARTE_COUNT 1
+
+#define UARTE0_EASYDMA_MAXCNT_SIZE 14
+
+/* Successive Approximation Analog to Digital Converter */
+#define SAADC_PRESENT
+#define SAADC_COUNT 1
+
+#define SAADC_EASYDMA_MAXCNT_SIZE 15
+
+#define SAADC_CH_NUM 8
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 1
+
+#define GPIOTE_CH_NUM 8
+
+#define GPIOTE_FEATURE_SET_PRESENT
+#define GPIOTE_FEATURE_CLR_PRESENT
+
+
+#endif // _NRF52805_PERIPHERALS_H
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf51801_xxab.ld b/third_party/NordicSemiconductor/nrfx/mdk/nrf52805_xxaa.ld
similarity index 77%
rename from third_party/NordicSemiconductor/nrfx/mdk/nrf51801_xxab.ld
rename to third_party/NordicSemiconductor/nrfx/mdk/nrf52805_xxaa.ld
index 5406e5893..b8ef436ee 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf51801_xxab.ld
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52805_xxaa.ld
@@ -6,7 +6,7 @@ GROUP(-lgcc -lc -lnosys)
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x30000
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x6000
}
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52810.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52810.h
index 5f91e3bc7..289a23ccf 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52810.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52810.h
@@ -30,10 +30,10 @@
* @file nrf52810.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 17. January 2019
- * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39
+ * @date 23. August 2019
+ * @note Generated by SVDConv V3.3.25 on Friday, 23.08.2019 12:15:13
* from File 'nrf52810.svd',
- * last modified on Thursday, 17.01.2019 16:25:35
+ * last modified on Friday, 23.08.2019 10:15:08
*/
@@ -122,8 +122,8 @@ typedef enum {
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __FPU_PRESENT 0 /*!< FPU present or not */
+#define __MPU_PRESENT 1 /*!< MPU present */
+#define __FPU_PRESENT 0 /*!< FPU present */
/** @} */ /* End of group Configuration_of_CMSIS */
@@ -591,12 +591,13 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu
typedef struct { /*!< (@ 0x10001000) UICR Structure */
__IM uint32_t RESERVED[5];
- __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware
+ __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware
design */
+ __IM uint32_t RESERVED1[2];
__IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware
design */
__IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */
- __IM uint32_t RESERVED1[64];
+ __IM uint32_t RESERVED2[64];
__IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET
function (see POWER chapter for details) */
__IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */
@@ -677,8 +678,8 @@ typedef struct { /*!< (@ 0x40000000) CLOCK Struct
typedef struct { /*!< (@ 0x40000000) POWER Structure */
__IM uint32_t RESERVED[30];
- __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */
- __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */
+ __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */
+ __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */
__IM uint32_t RESERVED1[34];
__IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */
__IM uint32_t RESERVED2[2];
@@ -1979,7 +1980,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
-#elif (__ARMCC_VERSION >= 6010050)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52810.svd b/third_party/NordicSemiconductor/nrfx/mdk/nrf52810.svd
index ad9d03896..ef83b7eb3 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52810.svd
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52810.svd
@@ -219,6 +219,16 @@ POSSIBILITY OF SUCH DAMAGE.\n
nRF52810
0x52810
+
+ N52811
+ nRF52811
+ 0x52811
+
+
+ N52832
+ nRF52832
+ 0x52832
+
Unspecified
Unspecified
@@ -313,6 +323,11 @@ POSSIBILITY OF SUCH DAMAGE.\n
QCxx - 32-pin QFN
0x2003
+
+ CA
+ CAxx - WLCSP
+ 0x2004
+
Unspecified
Unspecified
@@ -654,7 +669,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
0x20
- 0xF
+ 0xD
0x4
NRFFW[%s]
Description collection: Reserved for Nordic firmware design
@@ -2467,13 +2482,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
TASKS_CONSTLAT
- Enable constant latency mode
+ Enable Constant Latency mode
0x078
write-only
TASKS_CONSTLAT
- Enable constant latency mode
+ Enable Constant Latency mode
0
0
@@ -2488,13 +2503,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
TASKS_LOWPWR
- Enable low power mode (variable latency)
+ Enable Low-power mode (variable latency)
0x07C
write-only
TASKS_LOWPWR
- Enable low power mode (variable latency)
+ Enable Low-power mode (variable latency)
0
0
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52810_bitfields.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52810_bitfields.h
index fcd2fc346..f47207e17 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52810_bitfields.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52810_bitfields.h
@@ -1707,6 +1707,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
#define FICR_INFO_PART_PART_N52810 (0x52810UL) /*!< nRF52810 */
+#define FICR_INFO_PART_PART_N52811 (0x52811UL) /*!< nRF52811 */
+#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_VARIANT */
@@ -1733,6 +1735,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
#define FICR_INFO_PACKAGE_PACKAGE_QC (0x2003UL) /*!< QCxx - 32-pin QFN */
+#define FICR_INFO_PACKAGE_PACKAGE_CA (0x2004UL) /*!< CAxx - WLCSP */
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_RAM */
@@ -4111,17 +4114,17 @@ POSSIBILITY OF SUCH DAMAGE.
/* Description: Power control */
/* Register: POWER_TASKS_CONSTLAT */
-/* Description: Enable constant latency mode */
+/* Description: Enable Constant Latency mode */
-/* Bit 0 : Enable constant latency mode */
+/* Bit 0 : Enable Constant Latency mode */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
/* Register: POWER_TASKS_LOWPWR */
-/* Description: Enable low power mode (variable latency) */
+/* Description: Enable Low-power mode (variable latency) */
-/* Bit 0 : Enable low power mode (variable latency) */
+/* Bit 0 : Enable Low-power mode (variable latency) */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52810_name_change.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52810_name_change.h
index 6f7f6360d..3cc56d3b9 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52810_name_change.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52810_name_change.h
@@ -52,4 +52,4 @@ POSSIBILITY OF SUCH DAMAGE.
/*lint --flb "Leave library region" */
-#endif /* NRF52810_NAME_CHANGE_H */
\ No newline at end of file
+#endif /* NRF52810_NAME_CHANGE_H */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52811.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52811.h
index 641c447d4..6df51f96a 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52811.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52811.h
@@ -30,10 +30,10 @@
* @file nrf52811.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 17. January 2019
- * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39
+ * @date 23. August 2019
+ * @note Generated by SVDConv V3.3.25 on Friday, 23.08.2019 12:15:13
* from File 'nrf52811.svd',
- * last modified on Thursday, 17.01.2019 16:25:35
+ * last modified on Friday, 23.08.2019 10:15:08
*/
@@ -122,8 +122,8 @@ typedef enum {
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __FPU_PRESENT 0 /*!< FPU present or not */
+#define __MPU_PRESENT 1 /*!< MPU present */
+#define __FPU_PRESENT 0 /*!< FPU present */
/** @} */ /* End of group Configuration_of_CMSIS */
@@ -230,6 +230,25 @@ typedef struct {
} POWER_RAM_Type; /*!< Size = 16 (0x10) */
+/**
+ * @brief RADIO_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin
+ n */
+} RADIO_PSEL_Type; /*!< Size = 32 (0x20) */
+
+
+/**
+ * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */
+} RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */
+
+
/**
* @brief UART_PSEL [PSEL] (Unspecified)
*/
@@ -591,12 +610,13 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu
typedef struct { /*!< (@ 0x10001000) UICR Structure */
__IM uint32_t RESERVED[5];
- __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware
+ __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware
design */
+ __IM uint32_t RESERVED1[2];
__IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware
design */
__IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */
- __IM uint32_t RESERVED1[64];
+ __IM uint32_t RESERVED2[64];
__IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET
function (see POWER chapter for details) */
__IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */
@@ -677,8 +697,8 @@ typedef struct { /*!< (@ 0x40000000) CLOCK Struct
typedef struct { /*!< (@ 0x40000000) POWER Structure */
__IM uint32_t RESERVED[30];
- __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */
- __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */
+ __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */
+ __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */
__IM uint32_t RESERVED1[34];
__IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */
__IM uint32_t RESERVED2[2];
@@ -779,7 +799,7 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct
__IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */
__IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new
ED sample is ready for readout from the
- RADIO.EDSAMPLE register. */
+ RADIO.EDSAMPLE register */
__IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */
__IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */
__IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */
@@ -792,10 +812,10 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct
RX path */
__IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */
__IM uint32_t RESERVED3[3];
- __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and
- Ieee802154_250Kbit modes when last bit is
- sent on air. */
- __IM uint32_t RESERVED4[36];
+ __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air */
+ __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving
+ CTEInfo byte) */
+ __IM uint32_t RESERVED4[35];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED5[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@@ -807,7 +827,11 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct
__IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */
__IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */
__IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */
- __IM uint32_t RESERVED8[59];
+ __IM uint32_t RESERVED8[13];
+ __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */
+ __IM uint32_t RESERVED9[2];
+ __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */
+ __IM uint32_t RESERVED10[42];
__IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */
__IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */
__IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */
@@ -823,15 +847,15 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct
__IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */
__IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */
__IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */
- __IM uint32_t RESERVED9;
+ __IM uint32_t RESERVED11;
__IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */
__IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */
- __IM uint32_t RESERVED10;
+ __IM uint32_t RESERVED12;
__IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */
__IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */
- __IM uint32_t RESERVED11[2];
+ __IM uint32_t RESERVED13[2];
__IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */
- __IM uint32_t RESERVED12[39];
+ __IM uint32_t RESERVED14[39];
__IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment
n */
__IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix
@@ -839,14 +863,26 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct
__IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */
__IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */
__IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */
- __IM uint32_t RESERVED13;
+ __IM uint32_t RESERVED15;
__IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */
- __IM uint32_t RESERVED14[3];
+ __IM uint32_t RESERVED16[3];
__IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */
__IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */
__IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */
__IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */
- __IM uint32_t RESERVED15[611];
+ __IM uint32_t RESERVED17[164];
+ __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure
+ (AOD) */
+ __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */
+ __IM uint32_t RESERVED18[2];
+ __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */
+ __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */
+ __IM uint32_t RESERVED19[4];
+ __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */
+ __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */
+ __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */
+ __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */
+ __IM uint32_t RESERVED20[424];
__IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */
} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */
@@ -2018,7 +2054,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
-#elif (__ARMCC_VERSION >= 6010050)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52811.svd b/third_party/NordicSemiconductor/nrfx/mdk/nrf52811.svd
index f9810a20a..2c0f03fd0 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52811.svd
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52811.svd
@@ -224,6 +224,11 @@ POSSIBILITY OF SUCH DAMAGE.\n
nRF52811
0x52811
+
+ N52832
+ nRF52832
+ 0x52832
+
Unspecified
Unspecified
@@ -318,6 +323,11 @@ POSSIBILITY OF SUCH DAMAGE.\n
QCxx - 32-pin QFN
0x2003
+
+ CA
+ CAxx - WLCSP
+ 0x2004
+
Unspecified
Unspecified
@@ -659,7 +669,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
0x20
- 0xF
+ 0xD
0x4
NRFFW[%s]
Description collection: Reserved for Nordic firmware design
@@ -2472,13 +2482,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
TASKS_CONSTLAT
- Enable constant latency mode
+ Enable Constant Latency mode
0x078
write-only
TASKS_CONSTLAT
- Enable constant latency mode
+ Enable Constant Latency mode
0
0
@@ -2493,13 +2503,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
TASKS_LOWPWR
- Enable low power mode (variable latency)
+ Enable Low-power mode (variable latency)
0x07C
write-only
TASKS_LOWPWR
- Enable low power mode (variable latency)
+ Enable Low-power mode (variable latency)
0
0
@@ -9880,13 +9890,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
EVENTS_EDEND
- Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.
+ Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register
0x13C
read-write
EVENTS_EDEND
- Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.
+ Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register
0
0
@@ -10114,13 +10124,39 @@ POSSIBILITY OF SUCH DAMAGE.\n
EVENTS_PHYEND
- Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air.
+ Generated when last bit is sent on air
0x16C
read-write
EVENTS_PHYEND
- Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air.
+ Generated when last bit is sent on air
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CTEPRESENT
+ CTE is present (early warning right after receiving CTEInfo byte)
+ 0x170
+ read-write
+
+
+ EVENTS_CTEPRESENT
+ CTE is present (early warning right after receiving CTEInfo byte)
0
0
@@ -11088,6 +11124,33 @@ POSSIBILITY OF SUCH DAMAGE.\n
+
+ CTEPRESENT
+ Write '1' to enable interrupt for event CTEPRESENT
+ 28
+ 28
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
@@ -11690,6 +11753,33 @@ POSSIBILITY OF SUCH DAMAGE.\n
+
+ CTEPRESENT
+ Write '1' to disable interrupt for event CTEPRESENT
+ 28
+ 28
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
@@ -11804,6 +11894,96 @@ POSSIBILITY OF SUCH DAMAGE.\n
+
+ CTESTATUS
+ CTEInfo parsed from received packet
+ 0x44C
+ read-only
+
+
+ CTETIME
+ CTETime parsed from packet
+ 0
+ 4
+
+
+ RFU
+ RFU parsed from packet
+ 5
+ 5
+
+
+ CTETYPE
+ CTEType parsed from packet
+ 6
+ 7
+
+
+
+
+ DFESTATUS
+ DFE status information
+ 0x458
+ read-only
+
+
+ SWITCHINGSTATE
+ Internal state of switching state machine
+ 0
+ 2
+
+
+ Idle
+ Switching state Idle
+ 0
+
+
+ Offset
+ Switching state Offset
+ 1
+
+
+ Guard
+ Switching state Guard
+ 2
+
+
+ Ref
+ Switching state Ref
+ 3
+
+
+ Switching
+ Switching state Switching
+ 4
+
+
+ Ending
+ Switching state Ending
+ 5
+
+
+
+
+ SAMPLINGSTATE
+ Internal state of sampling state machine
+ 4
+ 4
+
+
+ Idle
+ Sampling state Idle
+ 0
+
+
+ Sampling
+ Sampling state Sampling
+ 1
+
+
+
+
+
PACKETPTR
Packet pointer
@@ -11932,37 +12112,37 @@ POSSIBILITY OF SUCH DAMAGE.\n
Nrf_1Mbit
- 1 Mbit/s Nordic proprietary radio mode
+ 1 Mbps Nordic proprietary radio mode
0
Nrf_2Mbit
- 2 Mbit/s Nordic proprietary radio mode
+ 2 Mbps Nordic proprietary radio mode
1
Ble_1Mbit
- 1 Mbit/s BLE
+ 1 Mbps BLE
3
Ble_2Mbit
- 2 Mbit/s BLE
+ 2 Mbps BLE
4
Ble_LR125Kbit
- Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX
+ Long range 125 kbps TX, 125 kbps and 500 kbps RX
5
Ble_LR500Kbit
- Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX
+ Long range 500 kbps TX, 125 kbps and 500 kbps RX
6
Ieee802154_250Kbit
- IEEE 802.15.4-2006 250 kbit/s
+ IEEE 802.15.4-2006 250 kbps
15
@@ -12097,7 +12277,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
ENDIAN
- On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.
+ On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields.
24
24
@@ -12577,7 +12757,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
DATAWHITEIV
- Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.
+ Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.
0
6
@@ -13000,7 +13180,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
CCACORRTHRES
- CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode.
+ CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode.
16
23
@@ -13012,6 +13192,525 @@ POSSIBILITY OF SUCH DAMAGE.\n
+
+ DFEMODE
+ Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)
+ 0x900
+ read-write
+ 0x00000000
+
+
+ DFEOPMODE
+ Direction finding operation mode
+ 0
+ 1
+
+
+ Disabled
+ Direction finding mode disabled
+ 0
+
+
+ AoD
+ Direction finding mode set to AoD
+ 2
+
+
+ AoA
+ Direction finding mode set to AoA
+ 3
+
+
+
+
+
+
+ CTEINLINECONF
+ Configuration for CTE inline mode
+ 0x904
+ read-write
+ 0x00002800
+
+
+ CTEINLINECTRLEN
+ Enable parsing of CTEInfo from received packet in BLE modes
+ 0
+ 0
+
+
+ Enabled
+ Parsing of CTEInfo is enabled
+ 1
+
+
+ Disabled
+ Parsing of CTEInfo is disabled
+ 0
+
+
+
+
+ CTEINFOINS1
+ CTEInfo is S1 byte or not
+ 3
+ 3
+
+
+ InS1
+ CTEInfo is in S1 byte (data PDU)
+ 1
+
+
+ NotInS1
+ CTEInfo is NOT in S1 byte (advertising PDU)
+ 0
+
+
+
+
+ CTEERRORHANDLING
+ Sampling/switching if CRC is not OK
+ 4
+ 4
+
+
+ Yes
+ Sampling and antenna switching also when CRC is not OK
+ 1
+
+
+ No
+ No sampling and antenna switching when CRC is not OK
+ 0
+
+
+
+
+ CTETIMEVALIDRANGE
+ Max range of CTETime
+ 6
+ 7
+
+
+ 20
+ 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20
+ 0
+
+
+ 31
+ 31 in 8us unit
+ 1
+
+
+ 63
+ 63 in 8us unit
+ 2
+
+
+
+
+ CTEINLINERXMODE1US
+ Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set
+ 10
+ 12
+
+
+ 4us
+ 4us
+ 1
+
+
+ 2us
+ 2us
+ 2
+
+
+ 1us
+ 1us
+ 3
+
+
+ 500ns
+ 0.5us
+ 4
+
+
+ 250ns
+ 0.25us
+ 5
+
+
+ 125ns
+ 0.125us
+ 6
+
+
+
+
+ CTEINLINERXMODE2US
+ Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set
+ 13
+ 15
+
+
+ 4us
+ 4us
+ 1
+
+
+ 2us
+ 2us
+ 2
+
+
+ 1us
+ 1us
+ 3
+
+
+ 500ns
+ 0.5us
+ 4
+
+
+ 250ns
+ 0.25us
+ 5
+
+
+ 125ns
+ 0.125us
+ 6
+
+
+
+
+ S0CONF
+ S0 bit pattern to match
+ 16
+ 23
+
+
+ S0MASK
+ S0 bit mask to set which bit to match
+ 24
+ 31
+
+
+
+
+ DFECTRL1
+ Various configuration for Direction finding
+ 0x910
+ read-write
+ 0x00023282
+
+
+ NUMBEROF8US
+ Length of the AoA/AoD procedure in number of 8 us units
+ 0
+ 5
+
+
+ DFEINEXTENSION
+ Add CTE extension and do antenna switching/sampling in this extension
+ 7
+ 7
+
+
+ CRC
+ AoA/AoD procedure triggered at end of CRC
+ 1
+
+
+ Payload
+ Antenna switching/sampling is done in the packet payload
+ 0
+
+
+
+
+ TSWITCHSPACING
+ Interval between every time the antenna is changed in the SWITCHING state
+ 8
+ 10
+
+
+ 4us
+ 4us
+ 1
+
+
+ 2us
+ 2us
+ 2
+
+
+ 1us
+ 1us
+ 3
+
+
+
+
+ TSAMPLESPACINGREF
+ Interval between samples in the REFERENCE period
+ 12
+ 14
+
+
+ 4us
+ 4us
+ 1
+
+
+ 2us
+ 2us
+ 2
+
+
+ 1us
+ 1us
+ 3
+
+
+ 500ns
+ 0.5us
+ 4
+
+
+ 250ns
+ 0.25us
+ 5
+
+
+ 125ns
+ 0.125us
+ 6
+
+
+
+
+ SAMPLETYPE
+ Whether to sample I/Q or magnitude/phase
+ 15
+ 15
+
+
+ IQ
+ Complex samples in I and Q
+ 0
+
+
+ MagPhase
+ Complex samples as magnitude and phase
+ 1
+
+
+
+
+ TSAMPLESPACING
+ Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0
+ 16
+ 18
+
+
+ 4us
+ 4us
+ 1
+
+
+ 2us
+ 2us
+ 2
+
+
+ 1us
+ 1us
+ 3
+
+
+ 500ns
+ 0.5us
+ 4
+
+
+ 250ns
+ 0.25us
+ 5
+
+
+ 125ns
+ 0.125us
+ 6
+
+
+
+
+ AGCBACKOFFGAIN
+ Gain will be lowered by the specified number of gain steps at the start of CTE
+ 24
+ 27
+
+
+
+
+ DFECTRL2
+ Start offset for Direction finding
+ 0x914
+ read-write
+ 0x00000000
+
+
+ TSWITCHOFFSET
+ Signed value offset after the end of the CRC before starting switching in number of 16M cycles
+ 0
+ 12
+
+
+ TSAMPLEOFFSET
+ Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start
+ 16
+ 27
+
+
+
+
+ SWITCHPATTERN
+ GPIO patterns to be used for each antenna
+ 0x928
+ read-write
+ 0x00000000
+
+
+ SWITCHPATTERN
+ Fill array of GPIO patterns for antenna control
+ 0
+ 7
+
+
+
+
+ CLEARPATTERN
+ Clear the GPIO pattern array for antenna control
+ 0x92C
+ read-write
+
+
+ CLEARPATTERN
+ Clears GPIO pattern array for antenna control
+ 0
+ 0
+ oneToClear
+
+
+ Clear
+ Clear the GPIO pattern
+ 1
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ RADIO_PSEL
+ read-write
+ 0x930
+
+ 0x8
+ 0x4
+ DFEGPIO[%s]
+ Description collection: Pin select for DFE pin n
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ DFEPACKET
+ DFE packet EasyDMA channel
+ RADIO_DFEPACKET
+ read-write
+ 0x950
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+ 0x00000000
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of buffer words to transfer
+ 0x004
+ read-write
+ 0x00001000
+
+
+ MAXCNT
+ Maximum number of buffer words to transfer
+ 0
+ 12
+
+
+
+
+ AMOUNT
+ Number of samples transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of samples transferred in the last transaction
+ 0
+ 15
+
+
+
+
POWER
Peripheral power control
@@ -27996,7 +28695,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
SCRATCHPTR
- Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved.
+ Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved.
0
31
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52811_bitfields.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52811_bitfields.h
index 4d0e08388..1a35ffe43 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52811_bitfields.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52811_bitfields.h
@@ -169,7 +169,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: AAR_SCRATCHPTR */
/* Description: Pointer to data area used for temporary storage */
-/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */
#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
@@ -1708,6 +1708,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
#define FICR_INFO_PART_PART_N52810 (0x52810UL) /*!< nRF52810 */
#define FICR_INFO_PART_PART_N52811 (0x52811UL) /*!< nRF52811 */
+#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_VARIANT */
@@ -1734,6 +1735,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
#define FICR_INFO_PACKAGE_PACKAGE_QC (0x2003UL) /*!< QCxx - 32-pin QFN */
+#define FICR_INFO_PACKAGE_PACKAGE_CA (0x2004UL) /*!< CAxx - WLCSP */
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_RAM */
@@ -4112,17 +4114,17 @@ POSSIBILITY OF SUCH DAMAGE.
/* Description: Power control */
/* Register: POWER_TASKS_CONSTLAT */
-/* Description: Enable constant latency mode */
+/* Description: Enable Constant Latency mode */
-/* Bit 0 : Enable constant latency mode */
+/* Bit 0 : Enable Constant Latency mode */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
/* Register: POWER_TASKS_LOWPWR */
-/* Description: Enable low power mode (variable latency) */
+/* Description: Enable Low-power mode (variable latency) */
-/* Bit 0 : Enable low power mode (variable latency) */
+/* Bit 0 : Enable Low-power mode (variable latency) */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
@@ -6187,9 +6189,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */
/* Register: RADIO_EVENTS_EDEND */
-/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
+/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */
-/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
+/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */
#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */
#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */
#define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */
@@ -6268,14 +6270,23 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */
/* Register: RADIO_EVENTS_PHYEND */
-/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */
+/* Description: Generated when last bit is sent on air */
-/* Bit 0 : Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */
+/* Bit 0 : Generated when last bit is sent on air */
#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */
#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */
#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */
#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */
+/* Register: RADIO_EVENTS_CTEPRESENT */
+/* Description: CTE is present (early warning right after receiving CTEInfo byte) */
+
+/* Bit 0 : CTE is present (early warning right after receiving CTEInfo byte) */
+#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */
+#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask of EVENTS_CTEPRESENT field. */
+#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL) /*!< Event generated */
+
/* Register: RADIO_SHORTS */
/* Description: Shortcuts between local events and tasks */
@@ -6396,6 +6407,13 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RADIO_INTENSET */
/* Description: Enable interrupt */
+/* Bit 28 : Write '1' to enable interrupt for event CTEPRESENT */
+#define RADIO_INTENSET_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
+#define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
+#define RADIO_INTENSET_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CTEPRESENT_Set (1UL) /*!< Enable */
+
/* Bit 27 : Write '1' to enable interrupt for event PHYEND */
#define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
#define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
@@ -6553,6 +6571,13 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RADIO_INTENCLR */
/* Description: Disable interrupt */
+/* Bit 28 : Write '1' to disable interrupt for event CTEPRESENT */
+#define RADIO_INTENCLR_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
+#define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
+#define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CTEPRESENT_Clear (1UL) /*!< Disable */
+
/* Bit 27 : Write '1' to disable interrupt for event PHYEND */
#define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
#define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
@@ -6752,6 +6777,40 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */
#define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */
+/* Register: RADIO_CTESTATUS */
+/* Description: CTEInfo parsed from received packet */
+
+/* Bits 7..6 : CTEType parsed from packet */
+#define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */
+#define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */
+
+/* Bit 5 : RFU parsed from packet */
+#define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */
+#define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */
+
+/* Bits 4..0 : CTETime parsed from packet */
+#define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */
+#define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */
+
+/* Register: RADIO_DFESTATUS */
+/* Description: DFE status information */
+
+/* Bit 4 : Internal state of sampling state machine */
+#define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */
+#define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */
+#define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL) /*!< Sampling state Idle */
+#define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL) /*!< Sampling state Sampling */
+
+/* Bits 2..0 : Internal state of switching state machine */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE field. */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL) /*!< Switching state Idle */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL) /*!< Switching state Offset */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL) /*!< Switching state Guard */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL) /*!< Switching state Ref */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL) /*!< Switching state Switching */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL) /*!< Switching state Ending */
+
/* Register: RADIO_PACKETPTR */
/* Description: Packet pointer */
@@ -6795,13 +6854,13 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
-#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
-#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s BLE */
-#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s BLE */
-#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
-#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
-#define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */
+#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */
+#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbps TX, 125 kbps and 500 kbps RX */
+#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbps TX, 125 kbps and 500 kbps RX */
+#define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */
/* Register: RADIO_PCNF0 */
/* Description: Packet configuration register 0 */
@@ -6855,7 +6914,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
-/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
+/* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */
#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
@@ -7048,7 +7107,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RADIO_DATAWHITEIV */
/* Description: Data whitening initial value */
-/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
+/* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
@@ -7214,7 +7273,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */
#define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */
-/* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */
+/* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. */
#define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */
#define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */
@@ -7231,6 +7290,186 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */
#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
+/* Register: RADIO_DFEMODE */
+/* Description: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */
+
+/* Bits 1..0 : Direction finding operation mode */
+#define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */
+#define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */
+#define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL) /*!< Direction finding mode disabled */
+#define RADIO_DFEMODE_DFEOPMODE_AoD (2UL) /*!< Direction finding mode set to AoD */
+#define RADIO_DFEMODE_DFEOPMODE_AoA (3UL) /*!< Direction finding mode set to AoA */
+
+/* Register: RADIO_CTEINLINECONF */
+/* Description: Configuration for CTE inline mode */
+
+/* Bits 31..24 : S0 bit mask to set which bit to match */
+#define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */
+#define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */
+
+/* Bits 23..16 : S0 bit pattern to match */
+#define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */
+#define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */
+
+/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125us */
+
+/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125us */
+
+/* Bits 7..6 : Max range of CTETime */
+#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */
+#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */
+#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 */
+#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8us unit */
+#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8us unit */
+
+/* Bit 4 : Sampling/switching if CRC is not OK */
+#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */
+#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of CTEERRORHANDLING field. */
+#define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL) /*!< No sampling and antenna switching when CRC is not OK */
+#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL) /*!< Sampling and antenna switching also when CRC is not OK */
+
+/* Bit 3 : CTEInfo is S1 byte or not */
+#define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */
+#define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 field. */
+#define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */
+#define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL) /*!< CTEInfo is in S1 byte (data PDU) */
+
+/* Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */
+#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */
+#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of CTEINLINECTRLEN field. */
+#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL) /*!< Parsing of CTEInfo is disabled */
+#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL) /*!< Parsing of CTEInfo is enabled */
+
+/* Register: RADIO_DFECTRL1 */
+/* Description: Various configuration for Direction finding */
+
+/* Bits 27..24 : Gain will be lowered by the specified number of gain steps at the start of CTE */
+#define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */
+#define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */
+
+/* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */
+#define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */
+#define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */
+#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4us */
+#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2us */
+#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1us */
+#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5us */
+#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25us */
+#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125us */
+
+/* Bit 15 : Whether to sample I/Q or magnitude/phase */
+#define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */
+#define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */
+#define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL) /*!< Complex samples in I and Q */
+#define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL) /*!< Complex samples as magnitude and phase */
+
+/* Bits 14..12 : Interval between samples in the REFERENCE period */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4us */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2us */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1us */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5us */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25us */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125us */
+
+/* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */
+#define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */
+#define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */
+#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4us */
+#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2us */
+#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1us */
+
+/* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */
+#define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */
+#define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field. */
+#define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL) /*!< Antenna switching/sampling is done in the packet payload */
+#define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL) /*!< AoA/AoD procedure triggered at end of CRC */
+
+/* Bits 5..0 : Length of the AoA/AoD procedure in number of 8 us units */
+#define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */
+#define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */
+
+/* Register: RADIO_DFECTRL2 */
+/* Description: Start offset for Direction finding */
+
+/* Bits 27..16 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start */
+#define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */
+#define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */
+
+/* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */
+#define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */
+#define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */
+
+/* Register: RADIO_SWITCHPATTERN */
+/* Description: GPIO patterns to be used for each antenna */
+
+/* Bits 7..0 : Fill array of GPIO patterns for antenna control */
+#define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */
+#define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */
+
+/* Register: RADIO_CLEARPATTERN */
+/* Description: Clear the GPIO pattern array for antenna control */
+
+/* Bit 0 : Clears GPIO pattern array for antenna control */
+#define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */
+#define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN field. */
+#define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL) /*!< Clear the GPIO pattern */
+
+/* Register: RADIO_PSEL_DFEGPIO */
+/* Description: Description collection: Pin select for DFE pin n */
+
+/* Bit 31 : Connection */
+#define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL) /*!< Connect */
+#define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define RADIO_PSEL_DFEGPIO_PORT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: RADIO_DFEPACKET_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: RADIO_DFEPACKET_MAXCNT */
+/* Description: Maximum number of buffer words to transfer */
+
+/* Bits 12..0 : Maximum number of buffer words to transfer */
+#define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0x1FFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: RADIO_DFEPACKET_AMOUNT */
+/* Description: Number of samples transferred in the last transaction */
+
+/* Bits 15..0 : Number of samples transferred in the last transaction */
+#define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
/* Register: RADIO_POWER */
/* Description: Peripheral power control */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52832_xxaa.ld b/third_party/NordicSemiconductor/nrfx/mdk/nrf52832_xxaa.ld
new file mode 100644
index 000000000..ca2811692
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52832_xxaa.ld
@@ -0,0 +1,13 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
+}
+
+
+INCLUDE "nrf_common.ld"
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52833.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52833.h
new file mode 100644
index 000000000..d03eb9ecf
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52833.h
@@ -0,0 +1,2794 @@
+/*
+ * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @file nrf52833.h
+ * @brief CMSIS HeaderFile
+ * @version 1
+ * @date 23. August 2019
+ * @note Generated by SVDConv V3.3.25 on Friday, 23.08.2019 12:15:13
+ * from File 'nrf52833.svd',
+ * last modified on Friday, 23.08.2019 10:15:09
+ */
+
+
+
+/** @addtogroup Nordic Semiconductor
+ * @{
+ */
+
+
+/** @addtogroup nrf52833
+ * @{
+ */
+
+
+#ifndef NRF52833_H
+#define NRF52833_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+typedef enum {
+/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+/* ========================================== nrf52833 Specific Interrupt Numbers ========================================== */
+ POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
+ RADIO_IRQn = 1, /*!< 1 RADIO */
+ UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
+ NFCT_IRQn = 5, /*!< 5 NFCT */
+ GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
+ SAADC_IRQn = 7, /*!< 7 SAADC */
+ TIMER0_IRQn = 8, /*!< 8 TIMER0 */
+ TIMER1_IRQn = 9, /*!< 9 TIMER1 */
+ TIMER2_IRQn = 10, /*!< 10 TIMER2 */
+ RTC0_IRQn = 11, /*!< 11 RTC0 */
+ TEMP_IRQn = 12, /*!< 12 TEMP */
+ RNG_IRQn = 13, /*!< 13 RNG */
+ ECB_IRQn = 14, /*!< 14 ECB */
+ CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
+ WDT_IRQn = 16, /*!< 16 WDT */
+ RTC1_IRQn = 17, /*!< 17 RTC1 */
+ QDEC_IRQn = 18, /*!< 18 QDEC */
+ COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */
+ SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
+ SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
+ SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */
+ SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */
+ SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */
+ SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */
+ TIMER3_IRQn = 26, /*!< 26 TIMER3 */
+ TIMER4_IRQn = 27, /*!< 27 TIMER4 */
+ PWM0_IRQn = 28, /*!< 28 PWM0 */
+ PDM_IRQn = 29, /*!< 29 PDM */
+ MWU_IRQn = 32, /*!< 32 MWU */
+ PWM1_IRQn = 33, /*!< 33 PWM1 */
+ PWM2_IRQn = 34, /*!< 34 PWM2 */
+ SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */
+ RTC2_IRQn = 36, /*!< 36 RTC2 */
+ I2S_IRQn = 37, /*!< 37 I2S */
+ FPU_IRQn = 38, /*!< 38 FPU */
+ USBD_IRQn = 39, /*!< 39 USBD */
+ UARTE1_IRQn = 40, /*!< 40 UARTE1 */
+ PWM3_IRQn = 45, /*!< 45 PWM3 */
+ SPIM3_IRQn = 47 /*!< 47 SPIM3 */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
+#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __DSP_PRESENT 0 /*!< DSP present or not */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 1 /*!< MPU present */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
+#include "system_nrf52833.h" /*!< nrf52833 System */
+
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+#endif
+
+
+/* ======================================== Start of section using anonymous unions ======================================== */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+ #pragma clang diagnostic ignored "-Wnested-anon-types"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Cluster Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+
+/**
+ * @brief FICR_INFO [INFO] (Device info)
+ */
+typedef struct {
+ __IM uint32_t PART; /*!< (@ 0x00000000) Part code */
+ __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */
+ __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */
+ __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */
+ __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */
+} FICR_INFO_Type; /*!< Size = 20 (0x14) */
+
+
+/**
+ * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients)
+ */
+typedef struct {
+ __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */
+ __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */
+ __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */
+ __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */
+ __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */
+ __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */
+ __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */
+ __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */
+ __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */
+ __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */
+ __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */
+ __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */
+ __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */
+ __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */
+ __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */
+ __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */
+ __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */
+} FICR_TEMP_Type; /*!< Size = 68 (0x44) */
+
+
+/**
+ * @brief FICR_NFC [NFC] (Unspecified)
+ */
+typedef struct {
+ __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read
+ these values to populate NFCID1_3RD_LAST,
+ NFCID1_2ND_LAST, and NFCID1_LAST. */
+ __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read
+ these values to populate NFCID1_3RD_LAST,
+ NFCID1_2ND_LAST, and NFCID1_LAST. */
+ __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read
+ these values to populate NFCID1_3RD_LAST,
+ NFCID1_2ND_LAST, and NFCID1_LAST. */
+ __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read
+ these values to populate NFCID1_3RD_LAST,
+ NFCID1_2ND_LAST, and NFCID1_LAST. */
+} FICR_NFC_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief POWER_RAM [RAM] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */
+ __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */
+ __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear
+ register */
+ __IM uint32_t RESERVED;
+} POWER_RAM_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief RADIO_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin
+ n */
+} RADIO_PSEL_Type; /*!< Size = 32 (0x20) */
+
+
+/**
+ * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */
+} RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief UART_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */
+ __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */
+ __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */
+ __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */
+} UART_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief UARTE_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */
+ __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */
+ __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */
+ __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */
+} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief UARTE_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} UARTE_RXD_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief UARTE_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} UARTE_TXD_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief SPI_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */
+ __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */
+} SPI_PSEL_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief SPIM_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */
+ __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */
+ __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */
+} SPIM_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIM_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIM_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIM_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIM_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIM_IFTIMING [IFTIMING] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */
+ __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge
+ of SCK and minimum duration CSN must stay
+ high between transactions */
+} SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SPIS_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */
+ __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */
+} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIS_RXD [RXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIS_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIS_TXD [TXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIS_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWI_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */
+} TWI_PSEL_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief TWIM_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */
+} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief TWIM_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIM_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWIM_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIM_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWIS_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */
+} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief TWIS_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIS_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWIS_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIS_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */
+} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief NFCT_TXD [TXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */
+ __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */
+} NFCT_TXD_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief NFCT_RXD [RXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */
+} NFCT_RXD_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.)
+ */
+typedef struct {
+ __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or
+ above CH[n].LIMIT.HIGH */
+ __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or
+ below CH[n].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SAADC_CH [CH] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection
+ for CH[n] */
+ __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection
+ for CH[n] */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for
+ CH[n] */
+ __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event
+ monitoring of a channel */
+} SAADC_CH_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written
+ to output RAM buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM
+ buffer since the previous START task */
+} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief QDEC_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */
+ __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */
+ __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */
+} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief PWM_SEQ [SEQ] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM
+ of this sequence */
+ __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles)
+ in this sequence */
+ __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM
+ periods between samples loaded into compare
+ register */
+ __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */
+ __IM uint32_t RESERVED[4];
+} PWM_SEQ_Type; /*!< Size = 32 (0x20) */
+
+
+/**
+ * @brief PWM_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for
+ PWM channel n */
+} PWM_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief PDM_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */
+ __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */
+} PDM_PSEL_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief PDM_SAMPLE [SAMPLE] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with
+ EasyDMA */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA
+ mode */
+} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief ACL_ACL [ACL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Configure the word-aligned
+ start address of region n to protect */
+ __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect
+ counting from address ACL[n].ADDR. Write
+ '0' as no effect. */
+ __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region
+ n as defined by start address ACL[n].ADDR
+ and size ACL[n].SIZE */
+ __IM uint32_t RESERVED;
+} ACL_ACL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks)
+ */
+typedef struct {
+ __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */
+ __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */
+} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief PPI_CH [CH] (PPI Channel)
+ */
+typedef struct {
+ __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */
+ __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */
+} PPI_CH_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief PPI_FORK [FORK] (Fork)
+ */
+typedef struct {
+ __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */
+} PPI_FORK_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.)
+ */
+typedef struct {
+ __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n
+ detected */
+ __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n
+ detected */
+} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.)
+ */
+typedef struct {
+ __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral
+ region n detected */
+ __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral
+ region n detected */
+} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief MWU_PERREGION [PERREGION] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt
+ in region n, write access detected while
+ corresponding subregion was enabled for
+ watching */
+ __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt
+ in region n, read access detected while
+ corresponding subregion was enabled for
+ watching */
+} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief MWU_REGION [REGION] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region
+ n */
+ __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */
+ __IM uint32_t RESERVED[2];
+} MWU_REGION_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief MWU_PREGION [PREGION] (Unspecified)
+ */
+typedef struct {
+ __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */
+ __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */
+ __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */
+ __IM uint32_t RESERVED;
+} MWU_PREGION_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief I2S_CONFIG [CONFIG] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */
+ __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */
+ __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */
+ __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */
+ __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */
+ __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */
+ __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */
+ __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */
+ __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */
+ __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */
+} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */
+
+
+/**
+ * @brief I2S_RXD [RXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */
+} I2S_RXD_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief I2S_TXD [TXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */
+} I2S_TXD_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief I2S_RXTXD [RXTXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */
+} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief I2S_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */
+ __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */
+ __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */
+ __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */
+ __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */
+} I2S_PSEL_Type; /*!< Size = 20 (0x14) */
+
+
+/**
+ * @brief USBD_HALTED [HALTED] (Unspecified)
+ */
+typedef struct {
+ __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status.
+ Can be used as is as response to a GetStatus()
+ request to endpoint. */
+ __IM uint32_t RESERVED;
+ __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status.
+ Can be used as is as response to a GetStatus()
+ request to endpoint. */
+} USBD_HALTED_Type; /*!< Size = 68 (0x44) */
+
+
+/**
+ * @brief USBD_SIZE [SIZE] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received
+ last in the data stage of this OUT endpoint */
+ __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT
+ data endpoint */
+} USBD_SIZE_Type; /*!< Size = 36 (0x24) */
+
+
+/**
+ * @brief USBD_EPIN [EPIN] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes
+ to transfer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred
+ in the last transaction */
+ __IM uint32_t RESERVED[2];
+} USBD_EPIN_Type; /*!< Size = 20 (0x14) */
+
+
+/**
+ * @brief USBD_ISOIN [ISOIN] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} USBD_ISOIN_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief USBD_EPOUT [EPOUT] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes
+ to transfer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred
+ in the last transaction */
+ __IM uint32_t RESERVED[2];
+} USBD_EPOUT_Type; /*!< Size = 20 (0x14) */
+
+
+/**
+ * @brief USBD_ISOOUT [ISOOUT] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */
+
+
+/** @} */ /* End of group Device_Peripheral_clusters */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ FICR ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Factory information configuration registers (FICR)
+ */
+
+typedef struct { /*!< (@ 0x10000000) FICR Structure */
+ __IM uint32_t RESERVED[4];
+ __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */
+ __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */
+ __IM uint32_t RESERVED1[18];
+ __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */
+ __IM uint32_t RESERVED2[6];
+ __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word
+ n */
+ __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */
+ __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */
+ __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */
+ __IM uint32_t RESERVED3[21];
+ __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */
+ __IM uint32_t RESERVED4[143];
+ __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature
+ n */
+ __IM uint32_t RESERVED5[42];
+ __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization
+ coefficients */
+ __IM uint32_t RESERVED6[2];
+ __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */
+} NRF_FICR_Type; /*!< Size = 1120 (0x460) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UICR ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief User information configuration registers (UICR)
+ */
+
+typedef struct { /*!< (@ 0x10001000) UICR Structure */
+ __IM uint32_t RESERVED[5];
+ __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware
+ design */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware
+ design */
+ __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET
+ function (see POWER chapter for details) */
+ __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */
+ __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality:
+ NFC antenna or GPIO */
+ __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */
+ __IM uint32_t RESERVED3[60];
+ __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The
+ maximum output voltage from this stage is
+ given as VDDH - VREG0DROP. */
+} NRF_UICR_Type; /*!< Size = 776 (0x308) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CLOCK ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Clock control (CLOCK)
+ */
+
+typedef struct { /*!< (@ 0x40000000) CLOCK Structure */
+ __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */
+ __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */
+ __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */
+ __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */
+ __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */
+ __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */
+ __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */
+ __IM uint32_t RESERVED[57];
+ __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */
+ __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */
+ __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */
+ __IM uint32_t RESERVED2[5];
+ __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready
+ to process new tasks */
+ __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready
+ to process new tasks */
+ __IM uint32_t RESERVED3[117];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[63];
+ __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been
+ triggered */
+ __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */
+ __IM uint32_t RESERVED5;
+ __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been
+ triggered */
+ __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */
+ __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART
+ task was triggered */
+ __IM uint32_t RESERVED6[62];
+ __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */
+ __IM uint32_t RESERVED7[3];
+ __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering
+ the TASKS_HFCLKSTART task. */
+ __IOM uint32_t LFXODEBOUNCE; /*!< (@ 0x0000052C) LFXO debounce time. The LFXO is started by triggering
+ the TASKS_LFCLKSTART task when the LFCLKSRC
+ register is configured for Xtal. */
+ __IM uint32_t RESERVED8[2];
+ __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */
+ __IM uint32_t RESERVED9[8];
+ __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */
+} NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ POWER ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Power control (POWER)
+ */
+
+typedef struct { /*!< (@ 0x40000000) POWER Structure */
+ __IM uint32_t RESERVED[30];
+ __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */
+ __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */
+ __IM uint32_t RESERVED1[34];
+ __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */
+ __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */
+ __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */
+ __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */
+ __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */
+ __IM uint32_t RESERVED3[119];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[61];
+ __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */
+ __IM uint32_t RESERVED5[9];
+ __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */
+ __IM uint32_t RESERVED6[3];
+ __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */
+ __IM uint32_t RESERVED7[49];
+ __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */
+ __IM uint32_t RESERVED8[3];
+ __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */
+ __IM uint32_t RESERVED9[2];
+ __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */
+ __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */
+ __IM uint32_t RESERVED10[21];
+ __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */
+ __IM uint32_t RESERVED11[49];
+ __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */
+ __IM uint32_t RESERVED12[175];
+ __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */
+} NRF_POWER_Type; /*!< Size = 2448 (0x990) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ P0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIO Port 1 (P0)
+ */
+
+typedef struct { /*!< (@ 0x50000000) P0 Structure */
+ __IM uint32_t RESERVED[321];
+ __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */
+ __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */
+ __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */
+ __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */
+ __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */
+ __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */
+ __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */
+ __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that
+ have met the criteria set in the PIN_CNF[n].SENSE
+ registers */
+ __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour
+ and LDETECT mode */
+ __IM uint32_t RESERVED1[118];
+ __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO
+ pins */
+} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RADIO ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief 2.4 GHz radio (RADIO)
+ */
+
+typedef struct { /*!< (@ 0x40001000) RADIO Structure */
+ __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */
+ __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */
+ __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */
+ __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of
+ the receive signal strength */
+ __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */
+ __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */
+ __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */
+ __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE
+ 802.15.4 mode */
+ __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */
+ __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE
+ 802.15.4 mode */
+ __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */
+ __IM uint32_t RESERVED[51];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */
+ __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */
+ __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */
+ __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */
+ __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received
+ packet */
+ __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last
+ received packet */
+ __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */
+ __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */
+ __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */
+ __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new
+ ED sample is ready for readout from the
+ RADIO.EDSAMPLE register */
+ __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */
+ __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */
+ __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */
+ __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */
+ __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed
+ from Ble_LR125Kbit to Ble_LR500Kbit. */
+ __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started
+ TX path */
+ __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started
+ RX path */
+ __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air */
+ __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving
+ CTEInfo byte) */
+ __IM uint32_t RESERVED4[35];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED5[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED6[61];
+ __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */
+ __IM uint32_t RESERVED7;
+ __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */
+ __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */
+ __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */
+ __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */
+ __IM uint32_t RESERVED8[13];
+ __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */
+ __IM uint32_t RESERVED9[2];
+ __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */
+ __IM uint32_t RESERVED10[42];
+ __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */
+ __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */
+ __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */
+ __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */
+ __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */
+ __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */
+ __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */
+ __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */
+ __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */
+ __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */
+ __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */
+ __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */
+ __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */
+ __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */
+ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */
+ __IM uint32_t RESERVED12;
+ __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */
+ __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */
+ __IM uint32_t RESERVED13[2];
+ __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */
+ __IM uint32_t RESERVED14[39];
+ __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment
+ n */
+ __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix
+ n */
+ __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */
+ __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */
+ __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */
+ __IM uint32_t RESERVED16[3];
+ __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */
+ __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */
+ __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */
+ __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */
+ __IM uint32_t RESERVED17[164];
+ __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure
+ (AOD) */
+ __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */
+ __IM uint32_t RESERVED18[2];
+ __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */
+ __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */
+ __IM uint32_t RESERVED19[4];
+ __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */
+ __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */
+ __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */
+ __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */
+ __IM uint32_t RESERVED20[424];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */
+} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Universal Asynchronous Receiver/Transmitter (UART0)
+ */
+
+typedef struct { /*!< (@ 0x40002000) UART0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */
+ __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */
+ __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */
+ __IM uint32_t RESERVED[3];
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */
+ __IM uint32_t RESERVED1[56];
+ __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */
+ __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */
+ __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */
+ __IM uint32_t RESERVED2[4];
+ __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */
+ __IM uint32_t RESERVED5[46];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED6[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED7[93];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */
+ __IM uint32_t RESERVED8[31];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
+ __IM uint32_t RESERVED9;
+ __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
+ selected. */
+ __IM uint32_t RESERVED11[17];
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */
+} NRF_UART_Type; /*!< Size = 1392 (0x570) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UARTE0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART with EasyDMA 0 (UARTE0)
+ */
+
+typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */
+ __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */
+ __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */
+ __IM uint32_t RESERVED[7];
+ __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */
+ __IM uint32_t RESERVED1[52];
+ __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */
+ __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */
+ __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet
+ transferred to Data RAM) */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */
+ __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */
+ __IM uint32_t RESERVED7[41];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED8[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[93];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write
+ one to clear. */
+ __IM uint32_t RESERVED10[31];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
+ __IM uint32_t RESERVED11;
+ __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[3];
+ __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
+ selected. */
+ __IM uint32_t RESERVED13[3];
+ __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IM uint32_t RESERVED14;
+ __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED15[7];
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */
+} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Serial Peripheral Interface 0 (SPI0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) SPI0 Structure */
+ __IM uint32_t RESERVED[66];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */
+ __IM uint32_t RESERVED1[126];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */
+ __IM uint32_t RESERVED3;
+ __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED4;
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED6[11];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+} NRF_SPI_Type; /*!< Size = 1368 (0x558) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPIM0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */
+ __IM uint32_t RESERVED[4];
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */
+ __IM uint32_t RESERVED1;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */
+ __IM uint32_t RESERVED2[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */
+ __IM uint32_t RESERVED6[10];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */
+ __IM uint32_t RESERVED7[44];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED8[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[61];
+ __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields
+ in this register is set to STALL by hardware
+ whenever a stall occurres and can be cleared
+ (set to NOSTALL) by the CPU. */
+ __IM uint32_t RESERVED10[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */
+ __IM uint32_t RESERVED11;
+ __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[3];
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED13[3];
+ __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+ __IM uint32_t RESERVED14[2];
+ __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */
+ __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */
+ __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */
+ __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */
+ __IM uint32_t RESERVED15[19];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have
+ been transmitted in the case when RXD.MAXCNT
+ is greater than TXD.MAXCNT */
+} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPIS0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI Slave 0 (SPIS0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */
+ __IM uint32_t RESERVED[9];
+ __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */
+ __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave
+ to acquire it */
+ __IM uint32_t RESERVED1[54];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */
+ __IM uint32_t RESERVED3[5];
+ __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */
+ __IM uint32_t RESERVED4[53];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED5[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED6[61];
+ __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */
+ __IM uint32_t RESERVED7[15];
+ __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */
+ __IM uint32_t RESERVED8[47];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */
+ __IM uint32_t RESERVED9;
+ __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED10[7];
+ __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */
+ __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case
+ of an ignored transaction. */
+ __IM uint32_t RESERVED12[24];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */
+} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Interface 0 (TWI0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) TWI0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */
+ __IM uint32_t RESERVED2;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */
+ __IM uint32_t RESERVED4[4];
+ __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte
+ that is sent or received */
+ __IM uint32_t RESERVED7[3];
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */
+ __IM uint32_t RESERVED8[45];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED9[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED10[110];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */
+ __IM uint32_t RESERVED11[14];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */
+ __IM uint32_t RESERVED12;
+ __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED13[2];
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED15[24];
+ __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */
+} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWIM0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the
+ TWI master is not suspended. */
+ __IM uint32_t RESERVED2;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED5[8];
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND
+ task has been issued, TWI traffic is now
+ suspended. */
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */
+ __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last
+ byte */
+ __IM uint32_t RESERVED7[39];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED8[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[110];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */
+ __IM uint32_t RESERVED10[14];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */
+ __IM uint32_t RESERVED11;
+ __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[5];
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED13[3];
+ __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED14[13];
+ __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */
+} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWIS0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */
+ __IM uint32_t RESERVED[5];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */
+ __IM uint32_t RESERVED1;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED2[3];
+ __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */
+ __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */
+ __IM uint32_t RESERVED3[51];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED5[9];
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */
+ __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */
+ __IM uint32_t RESERVED7[37];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED8[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[113];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */
+ __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had
+ a match */
+ __IM uint32_t RESERVED10[10];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */
+ __IM uint32_t RESERVED11;
+ __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[9];
+ __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED13[13];
+ __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match
+ mechanism */
+ __IM uint32_t RESERVED15[10];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case
+ of an over-read of the transmit buffer. */
+} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ NFCT ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief NFC-A compatible radio (NFCT)
+ */
+
+typedef struct { /*!< (@ 0x40005000) NFCT Structure */
+ __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing
+ frames, change state to activated */
+ __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */
+ __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to
+ sense mode */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change
+ state to transmit */
+ __IM uint32_t RESERVED[3];
+ __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */
+ __IM uint32_t RESERVED1;
+ __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */
+ __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */
+ __IM uint32_t RESERVED2[53];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send
+ frames */
+ __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */
+ __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */
+ __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted
+ frame */
+ __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air
+ symbol of a frame */
+ __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received
+ frame */
+ __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity)
+ and transferred to RAM, and EasyDMA has
+ ended accessing the RX buffer */
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register
+ contains details on the source of the error. */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX
+ register contains details on the source
+ of the error. */
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN)
+ in Data RAM full. */
+ __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA
+ has ended accessing the TX buffer */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */
+ __IM uint32_t RESERVED5[3];
+ __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */
+ __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */
+ __IM uint32_t RESERVED6[43];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED7[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED8[62];
+ __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */
+ __IM uint32_t RESERVED9;
+ __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */
+ __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */
+ __IM uint32_t RESERVED10[3];
+ __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */
+ __IM uint32_t RESERVED11[6];
+ __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */
+ __IM uint32_t RESERVED12[49];
+ __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */
+ __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */
+ __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */
+ __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in
+ Data RAM */
+ __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD
+ data storage each */
+ __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */
+ __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t MODULATIONCTRL; /*!< (@ 0x0000052C) Enables the modulation output to a GPIO pin which
+ can be connected to a second external antenna. */
+ __IM uint32_t RESERVED14[2];
+ __IOM uint32_t MODULATIONPSEL; /*!< (@ 0x00000538) Pin select for Modulation control. */
+ __IM uint32_t RESERVED15[21];
+ __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */
+ __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */
+ __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */
+ __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function.
+ This setting must be done before the NFCT
+ peripheral is activated. */
+ __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */
+ __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */
+} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOTE ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIO Tasks and Events (GPIOTE)
+ */
+
+typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */
+ __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is configured in CONFIG[n].POLARITY. */
+ __IM uint32_t RESERVED[4];
+ __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is to set it high. */
+ __IM uint32_t RESERVED1[4];
+ __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is to set it low. */
+ __IM uint32_t RESERVED2[32];
+ __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from
+ pin specified in CONFIG[n].PSEL */
+ __IM uint32_t RESERVED3[23];
+ __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins
+ with SENSE mechanism enabled */
+ __IM uint32_t RESERVED4[97];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED5[129];
+ __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n],
+ SET[n] and CLR[n] tasks and IN[n] event */
+} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SAADC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC)
+ */
+
+typedef struct { /*!< (@ 0x40007000) SAADC Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer
+ in RAM */
+ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */
+ __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */
+ __IM uint32_t RESERVED[60];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */
+ __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending
+ on the configuration, multiple conversions
+ might be needed for a result to be transferred
+ to RAM. */
+ __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */
+ __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */
+ __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */
+ __IM uint32_t RESERVED1[106];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[61];
+ __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */
+ __IM uint32_t RESERVED4[3];
+ __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */
+ __IM uint32_t RESERVED5[24];
+ __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */
+ __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is
+ applied before averaging, thus for high
+ OVERSAMPLE a higher RESOLUTION should be
+ used. */
+ __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */
+ __IM uint32_t RESERVED6[12];
+ __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */
+} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Timer/Counter 0 (TIMER0)
+ */
+
+typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */
+ __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */
+ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */
+ __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */
+ __IM uint32_t RESERVED[11];
+ __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to
+ CC[n] register */
+ __IM uint32_t RESERVED1[58];
+ __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
+ match */
+ __IM uint32_t RESERVED2[42];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED3[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[126];
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */
+ __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */
+ __IM uint32_t RESERVED6[11];
+ __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register
+ n */
+} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RTC0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Real time counter 0 (RTC0)
+ */
+
+typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */
+ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */
+ __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */
+ __IM uint32_t RESERVED[60];
+ __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */
+ __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */
+ __IM uint32_t RESERVED1[14];
+ __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
+ match */
+ __IM uint32_t RESERVED2[109];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[13];
+ __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */
+ __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */
+ __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */
+ __IM uint32_t RESERVED4[110];
+ __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */
+ __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu
+ t be written when RTC is stopped */
+ __IM uint32_t RESERVED5[13];
+ __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */
+} NRF_RTC_Type; /*!< Size = 1360 (0x550) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TEMP ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Temperature Sensor (TEMP)
+ */
+
+typedef struct { /*!< (@ 0x4000C000) TEMP Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */
+ __IM uint32_t RESERVED1[128];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[127];
+ __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */
+ __IM uint32_t RESERVED3[5];
+ __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */
+ __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */
+ __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */
+ __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */
+ __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */
+ __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */
+ __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */
+ __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */
+ __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */
+ __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */
+ __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */
+ __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */
+ __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */
+ __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */
+ __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */
+} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RNG ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Random Number Generator (RNG)
+ */
+
+typedef struct { /*!< (@ 0x4000D000) RNG Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number
+ written to the VALUE register */
+ __IM uint32_t RESERVED1[63];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[126];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */
+ __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */
+} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ECB ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief AES ECB Mode Encryption (ECB)
+ */
+
+typedef struct { /*!< (@ 0x4000E000) ECB Structure */
+ __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */
+ __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */
+ __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB
+ task or due to an error */
+ __IM uint32_t RESERVED1[127];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[126];
+ __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */
+} NRF_ECB_Type; /*!< Size = 1288 (0x508) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ AAR ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Accelerated Address Resolver (AAR)
+ */
+
+typedef struct { /*!< (@ 0x4000F000) AAR Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified
+ in the IRK data structure */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */
+ __IM uint32_t RESERVED1[61];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */
+ __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */
+ __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */
+ __IM uint32_t RESERVED2[126];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */
+ __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */
+ __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */
+ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
+} NRF_AAR_Type; /*!< Size = 1304 (0x518) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CCM ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief AES CCM Mode Encryption (CCM)
+ */
+
+typedef struct { /*!< (@ 0x4000F000) CCM Structure */
+ __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation
+ will stop by itself when completed. */
+ __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will
+ stop by itself when completed. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */
+ __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with
+ the contents of the RATEOVERRIDE register
+ for any ongoing encryption/decryption */
+ __IM uint32_t RESERVED[60];
+ __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */
+ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */
+ __IM uint32_t RESERVED1[61];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */
+ __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and
+ NONCE vector */
+ __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */
+ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */
+ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
+ __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH
+ = Extended. */
+ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */
+} NRF_CCM_Type; /*!< Size = 1312 (0x520) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ WDT ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Watchdog Timer (WDT)
+ */
+
+typedef struct { /*!< (@ 0x40010000) WDT Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */
+ __IM uint32_t RESERVED[63];
+ __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */
+ __IM uint32_t RESERVED1[128];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[61];
+ __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */
+ __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */
+ __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */
+ __IM uint32_t RESERVED4[60];
+ __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */
+} NRF_WDT_Type; /*!< Size = 1568 (0x620) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ QDEC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Quadrature Decoder (QDEC)
+ */
+
+typedef struct { /*!< (@ 0x40012000) QDEC Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */
+ __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */
+ __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */
+ __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */
+ __IM uint32_t RESERVED[59];
+ __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value
+ written to the SAMPLE register */
+ __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */
+ __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */
+ __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */
+ __IM uint32_t RESERVED1[59];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */
+ __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */
+ __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */
+ __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */
+ __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY
+ and DBLRDY events can be generated */
+ __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */
+ __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the
+ READCLRACC or RDCLRACC task */
+ __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */
+ __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */
+ __IM uint32_t RESERVED4[5];
+ __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */
+ __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected
+ double transitions */
+ __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC
+ or RDCLRDBL task */
+} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ COMP ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Comparator (COMP)
+ */
+
+typedef struct { /*!< (@ 0x40013000) COMP Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */
+ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */
+ __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */
+ __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */
+ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */
+ __IM uint32_t RESERVED1[60];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED2[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */
+ __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */
+ __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */
+ __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */
+ __IM uint32_t RESERVED5[8];
+ __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */
+ __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */
+ __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */
+} NRF_COMP_Type; /*!< Size = 1340 (0x53c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ LPCOMP ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Low Power Comparator (LPCOMP)
+ */
+
+typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */
+ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */
+ __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */
+ __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */
+ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */
+ __IM uint32_t RESERVED1[60];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */
+ __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */
+ __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */
+ __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */
+ __IM uint32_t RESERVED5[4];
+ __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */
+ __IM uint32_t RESERVED6[5];
+ __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */
+} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ EGU0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Event Generator Unit 0 (EGU0)
+ */
+
+typedef struct { /*!< (@ 0x40014000) EGU0 Structure */
+ __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering
+ the corresponding TRIGGERED[n] event */
+ __IM uint32_t RESERVED[48];
+ __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated
+ by triggering the corresponding TRIGGER[n]
+ task */
+ __IM uint32_t RESERVED1[112];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+} NRF_EGU_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SWI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Software interrupt 0 (SWI0)
+ */
+
+typedef struct { /*!< (@ 0x40014000) SWI0 Structure */
+ __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */
+} NRF_SWI_Type; /*!< Size = 4 (0x4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PWM0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Pulse width modulation unit 0 (PWM0)
+ */
+
+typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at
+ the end of current PWM period, and stops
+ sequence playback */
+ __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value
+ on all enabled channels from sequence n,
+ and starts playing that sequence at the
+ rate defined in SEQ[n]REFRESH and/or DECODER.MODE.
+ Causes PWM generation to start if not running. */
+ __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on
+ all enabled channels if DECODER.MODE=NextStep.
+ Does not cause PWM generation to start if
+ not running. */
+ __IM uint32_t RESERVED1[60];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses
+ are no longer generated */
+ __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started
+ on sequence n */
+ __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every
+ sequence n, when last value from RAM has
+ been applied to wave counter */
+ __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */
+ __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount
+ of times defined in LOOP.CNT */
+ __IM uint32_t RESERVED2[56];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */
+ __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter
+ counts */
+ __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */
+ __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */
+ __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */
+ __IM uint32_t RESERVED5[2];
+ __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */
+ __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */
+} NRF_PWM_Type; /*!< Size = 1392 (0x570) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
+ */
+
+typedef struct { /*!< (@ 0x4001D000) PDM Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified
+ by SAMPLE.MAXCNT (or the last sample after
+ a STOP task has been received) to Data RAM */
+ __IM uint32_t RESERVED1[125];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */
+ __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */
+ __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones'
+ signals */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */
+ __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */
+ __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output
+ sample rate. Change PDMCLKCTRL accordingly. */
+ __IM uint32_t RESERVED4[7];
+ __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */
+ __IM uint32_t RESERVED5[6];
+ __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */
+} NRF_PDM_Type; /*!< Size = 1384 (0x568) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ACL ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Access control lists (ACL)
+ */
+
+typedef struct { /*!< (@ 0x4001E000) ACL Structure */
+ __IM uint32_t RESERVED[512];
+ __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */
+} NRF_ACL_Type; /*!< Size = 2176 (0x880) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ NVMC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Non Volatile Memory Controller (NVMC)
+ */
+
+typedef struct { /*!< (@ 0x4001E000) NVMC Structure */
+ __IM uint32_t RESERVED[256];
+ __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */
+ __IM uint32_t RESERVED1;
+ __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */
+ __IM uint32_t RESERVED2[62];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */
+
+ union {
+ __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */
+ __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a
+ page in code area, equivalent to ERASEPAGE */
+ };
+ __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */
+ __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a
+ page in code area, equivalent to ERASEPAGE */
+ __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration
+ registers */
+ __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code
+ area */
+ __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */
+ __IM uint32_t RESERVED3[8];
+ __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */
+ __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */
+} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PPI ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Programmable Peripheral Interconnect (PPI)
+ */
+
+typedef struct { /*!< (@ 0x4001F000) PPI Structure */
+ __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */
+ __IM uint32_t RESERVED[308];
+ __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */
+ __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */
+ __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */
+ __IM uint32_t RESERVED1;
+ __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */
+ __IM uint32_t RESERVED2[148];
+ __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */
+ __IM uint32_t RESERVED3[62];
+ __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */
+} NRF_PPI_Type; /*!< Size = 2448 (0x990) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ MWU ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Memory Watch Unit (MWU)
+ */
+
+typedef struct { /*!< (@ 0x40020000) MWU Structure */
+ __IM uint32_t RESERVED[64];
+ __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */
+ __IM uint32_t RESERVED1[16];
+ __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */
+ __IM uint32_t RESERVED2[100];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[5];
+ __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */
+ __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */
+ __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */
+ __IM uint32_t RESERVED4[53];
+ __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */
+ __IM uint32_t RESERVED5[64];
+ __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */
+ __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */
+ __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */
+ __IM uint32_t RESERVED6[57];
+ __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */
+ __IM uint32_t RESERVED7[32];
+ __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */
+} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2S ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Inter-IC Sound (I2S)
+ */
+
+typedef struct { /*!< (@ 0x40025000) I2S Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK
+ generator when this is enabled. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator.
+ Triggering this task will cause the STOPPED
+ event to be generated. */
+ __IM uint32_t RESERVED[63];
+ __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal
+ double-buffers. When the I2S module is started
+ and RX is enabled, this event will be generated
+ for every RXTXD.MAXCNT words that are received
+ on the SDIN pin. */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal
+ double-buffers. When the I2S module is started
+ and TX is enabled, this event will be generated
+ for every RXTXD.MAXCNT words that are sent
+ on the SDOUT pin. */
+ __IM uint32_t RESERVED2[122];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */
+ __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */
+ __IM uint32_t RESERVED4[3];
+ __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */
+ __IM uint32_t RESERVED5;
+ __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */
+ __IM uint32_t RESERVED6[3];
+ __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */
+ __IM uint32_t RESERVED7[3];
+ __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */
+} NRF_I2S_Type; /*!< Size = 1396 (0x574) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ FPU ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief FPU (FPU)
+ */
+
+typedef struct { /*!< (@ 0x40026000) FPU Structure */
+ __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */
+} NRF_FPU_Type; /*!< Size = 4 (0x4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ USBD ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Universal serial bus device (USBD)
+ */
+
+typedef struct { /*!< (@ 0x40027000) USBD Structure */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR
+ and EPIN[n].MAXCNT registers values, and
+ enables endpoint IN n to respond to traffic
+ from host */
+ __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers
+ values, and enables sending data on ISO
+ endpoint */
+ __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR
+ and EPOUT[n].MAXCNT registers values, and
+ enables endpoint n to respond to traffic
+ from host */
+ __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers
+ values, and enables receiving of data on
+ ISO endpoint */
+ __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */
+ __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */
+ __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint
+ 0 */
+ __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined
+ in the DPDMVALUE register */
+ __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state
+ (USB engine takes control) */
+ __IM uint32_t RESERVED1[40];
+ __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected
+ on USB lines */
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT,
+ or EPOUT[n].PTR and EPOUT[n].MAXCNT registers
+ have been captured on all endpoints reported
+ in the EPSTATUS register */
+ __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer
+ has been consumed. The buffer can be accessed
+ safely by software. */
+ __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place
+ on the control endpoint */
+ __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The
+ buffer can be accessed safely by software. */
+ __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer
+ has been consumed. The buffer can be accessed
+ safely by software. */
+ __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The
+ buffer can be accessed safely by software. */
+ __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition
+ has been detected on USB lines */
+ __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific
+ events has occurred. Check EVENTCAUSE register
+ to find the cause. */
+ __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged)
+ on the control endpoint */
+ __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint,
+ indicated by the EPDATASTATUS register */
+ __IM uint32_t RESERVED2[39];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[61];
+ __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */
+ __IM uint32_t RESERVED5[7];
+ __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA
+ registers have been captured */
+ __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an
+ acknowledged data transfer has occurred
+ (EPDATA event) */
+ __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */
+ __IM uint32_t RESERVED7[3];
+ __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */
+ __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */
+ __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */
+ __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */
+ __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */
+ __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */
+ __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */
+ __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */
+ __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */
+ __IM uint32_t RESERVED8[15];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */
+ __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */
+ __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by
+ the DPDMDRIVE task. The DPDMNODRIVE task
+ reverts the control of the lines to MAC
+ IP (no forcing). */
+ __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */
+ __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */
+ __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */
+ __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */
+ __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */
+ __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame
+ counter */
+ __IM uint32_t RESERVED9[2];
+ __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during
+ USB suspend */
+ __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint
+ to an IN token when no data is ready to
+ be sent */
+ __IM uint32_t RESERVED10[51];
+ __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */
+ __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */
+ __IM uint32_t RESERVED11[21];
+ __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */
+ __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */
+} NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+#define NRF_FICR_BASE 0x10000000UL
+#define NRF_UICR_BASE 0x10001000UL
+#define NRF_CLOCK_BASE 0x40000000UL
+#define NRF_POWER_BASE 0x40000000UL
+#define NRF_P0_BASE 0x50000000UL
+#define NRF_P1_BASE 0x50000300UL
+#define NRF_RADIO_BASE 0x40001000UL
+#define NRF_UART0_BASE 0x40002000UL
+#define NRF_UARTE0_BASE 0x40002000UL
+#define NRF_SPI0_BASE 0x40003000UL
+#define NRF_SPIM0_BASE 0x40003000UL
+#define NRF_SPIS0_BASE 0x40003000UL
+#define NRF_TWI0_BASE 0x40003000UL
+#define NRF_TWIM0_BASE 0x40003000UL
+#define NRF_TWIS0_BASE 0x40003000UL
+#define NRF_SPI1_BASE 0x40004000UL
+#define NRF_SPIM1_BASE 0x40004000UL
+#define NRF_SPIS1_BASE 0x40004000UL
+#define NRF_TWI1_BASE 0x40004000UL
+#define NRF_TWIM1_BASE 0x40004000UL
+#define NRF_TWIS1_BASE 0x40004000UL
+#define NRF_NFCT_BASE 0x40005000UL
+#define NRF_GPIOTE_BASE 0x40006000UL
+#define NRF_SAADC_BASE 0x40007000UL
+#define NRF_TIMER0_BASE 0x40008000UL
+#define NRF_TIMER1_BASE 0x40009000UL
+#define NRF_TIMER2_BASE 0x4000A000UL
+#define NRF_RTC0_BASE 0x4000B000UL
+#define NRF_TEMP_BASE 0x4000C000UL
+#define NRF_RNG_BASE 0x4000D000UL
+#define NRF_ECB_BASE 0x4000E000UL
+#define NRF_AAR_BASE 0x4000F000UL
+#define NRF_CCM_BASE 0x4000F000UL
+#define NRF_WDT_BASE 0x40010000UL
+#define NRF_RTC1_BASE 0x40011000UL
+#define NRF_QDEC_BASE 0x40012000UL
+#define NRF_COMP_BASE 0x40013000UL
+#define NRF_LPCOMP_BASE 0x40013000UL
+#define NRF_EGU0_BASE 0x40014000UL
+#define NRF_SWI0_BASE 0x40014000UL
+#define NRF_EGU1_BASE 0x40015000UL
+#define NRF_SWI1_BASE 0x40015000UL
+#define NRF_EGU2_BASE 0x40016000UL
+#define NRF_SWI2_BASE 0x40016000UL
+#define NRF_EGU3_BASE 0x40017000UL
+#define NRF_SWI3_BASE 0x40017000UL
+#define NRF_EGU4_BASE 0x40018000UL
+#define NRF_SWI4_BASE 0x40018000UL
+#define NRF_EGU5_BASE 0x40019000UL
+#define NRF_SWI5_BASE 0x40019000UL
+#define NRF_TIMER3_BASE 0x4001A000UL
+#define NRF_TIMER4_BASE 0x4001B000UL
+#define NRF_PWM0_BASE 0x4001C000UL
+#define NRF_PDM_BASE 0x4001D000UL
+#define NRF_ACL_BASE 0x4001E000UL
+#define NRF_NVMC_BASE 0x4001E000UL
+#define NRF_PPI_BASE 0x4001F000UL
+#define NRF_MWU_BASE 0x40020000UL
+#define NRF_PWM1_BASE 0x40021000UL
+#define NRF_PWM2_BASE 0x40022000UL
+#define NRF_SPI2_BASE 0x40023000UL
+#define NRF_SPIM2_BASE 0x40023000UL
+#define NRF_SPIS2_BASE 0x40023000UL
+#define NRF_RTC2_BASE 0x40024000UL
+#define NRF_I2S_BASE 0x40025000UL
+#define NRF_FPU_BASE 0x40026000UL
+#define NRF_USBD_BASE 0x40027000UL
+#define NRF_UARTE1_BASE 0x40028000UL
+#define NRF_PWM3_BASE 0x4002D000UL
+#define NRF_SPIM3_BASE 0x4002F000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE)
+#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE)
+#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE)
+#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE)
+#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE)
+#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE)
+#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE)
+#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE)
+#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE)
+#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE)
+#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE)
+#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE)
+#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE)
+#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE)
+#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE)
+#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE)
+#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE)
+#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE)
+#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE)
+#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE)
+#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE)
+#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE)
+#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE)
+#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE)
+#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE)
+#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE)
+#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE)
+#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE)
+#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE)
+#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE)
+#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE)
+#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE)
+#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE)
+#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE)
+#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE)
+#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE)
+#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE)
+#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE)
+#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE)
+#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE)
+#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE)
+#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE)
+#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE)
+#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE)
+#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE)
+#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE)
+#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE)
+#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE)
+#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE)
+#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE)
+#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE)
+#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE)
+#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE)
+#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE)
+#define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE)
+#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE)
+#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE)
+#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE)
+#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE)
+#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE)
+#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE)
+#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE)
+#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE)
+#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE)
+#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE)
+#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE)
+#define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE)
+#define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE)
+#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE)
+#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+
+/* ========================================= End of section using anonymous unions ========================================= */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF52833_H */
+
+
+/** @} */ /* End of group nrf52833 */
+
+/** @} */ /* End of group Nordic Semiconductor */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52833.svd b/third_party/NordicSemiconductor/nrfx/mdk/nrf52833.svd
new file mode 100644
index 000000000..5a081c92a
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52833.svd
@@ -0,0 +1,53945 @@
+
+
+
+ Nordic Semiconductor
+ Nordic
+ nrf52833
+ nrf52
+ 1
+ nRF52833 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller
+
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.\n
+\n
+Redistribution and use in source and binary forms, with or without\n
+modification, are permitted provided that the following conditions are met:\n
+\n
+1. Redistributions of source code must retain the above copyright notice, this\n
+ list of conditions and the following disclaimer.\n
+\n
+2. Redistributions in binary form must reproduce the above copyright\n
+ notice, this list of conditions and the following disclaimer in the\n
+ documentation and/or other materials provided with the distribution.\n
+\n
+3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
+ contributors may be used to endorse or promote products derived from this\n
+ software without specific prior written permission.\n
+\n
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
+POSSIBILITY OF SUCH DAMAGE.\n
+
+ 8
+ 32
+ 32
+ 0x00000000
+ 0xFFFFFFFF
+
+ CM4
+ r0p1
+ little
+ 1
+ 1
+ 3
+ 0
+
+ system_nrf52833
+ NRF_
+
+ 2048
+ 2048
+ 112
+
+
+
+ FICR
+ Factory information configuration registers
+ 0x10000000
+
+ 0
+ 0x1000
+ registers
+
+ FICR
+ 0x20
+
+
+ CODEPAGESIZE
+ Code memory page size
+ 0x010
+ read-only
+ 0xFFFFFFFF
+
+
+ CODEPAGESIZE
+ Code memory page size
+ 0
+ 31
+
+
+
+
+ CODESIZE
+ Code memory size
+ 0x014
+ read-only
+ 0xFFFFFFFF
+
+
+ CODESIZE
+ Code memory size in number of pages
+ 0
+ 31
+
+
+
+
+ 0x2
+ 0x4
+ DEVICEID[%s]
+ Description collection: Device identifier
+ 0x060
+ read-only
+ 0xFFFFFFFF
+
+
+ DEVICEID
+ 64 bit unique device identifier
+ 0
+ 31
+
+
+
+
+ 0x4
+ 0x4
+ ER[%s]
+ Description collection: Encryption root, word n
+ 0x080
+ read-only
+ 0xFFFFFFFF
+
+
+ ER
+ Encryption root, word n
+ 0
+ 31
+
+
+
+
+ 0x4
+ 0x4
+ IR[%s]
+ Description collection: Identity Root, word n
+ 0x090
+ read-only
+ 0xFFFFFFFF
+
+
+ IR
+ Identity Root, word n
+ 0
+ 31
+
+
+
+
+ DEVICEADDRTYPE
+ Device address type
+ 0x0A0
+ read-only
+ 0xFFFFFFFF
+
+
+ DEVICEADDRTYPE
+ Device address type
+ 0
+ 0
+
+
+ Public
+ Public address
+ 0
+
+
+ Random
+ Random address
+ 1
+
+
+
+
+
+
+ 0x2
+ 0x4
+ DEVICEADDR[%s]
+ Description collection: Device address n
+ 0x0A4
+ read-only
+ 0xFFFFFFFF
+
+
+ DEVICEADDR
+ 48 bit device address
+ 0
+ 31
+
+
+
+
+ INFO
+ Device info
+ FICR_INFO
+ read-only
+ 0x100
+
+ PART
+ Part code
+ 0x000
+ read-only
+ 0x00052833
+
+
+ PART
+ Part code
+ 0
+ 31
+
+
+ N52833
+ nRF52833
+ 0x52833
+
+
+ N52840
+ nRF52840
+ 0x52840
+
+
+ Unspecified
+ Unspecified
+ 0xFFFFFFFF
+
+
+
+
+
+
+ VARIANT
+ Build code (hardware version and production configuration)
+ 0x004
+ read-only
+ 0xFFFFFFFF
+
+
+ VARIANT
+ Build code (hardware version and production configuration). Encoded as ASCII.
+ 0
+ 31
+
+
+ AAAA
+ AAAA
+ 0x41414141
+
+
+ AAAB
+ AAAB
+ 0x41414142
+
+
+ Unspecified
+ Unspecified
+ 0xFFFFFFFF
+
+
+
+
+
+
+ PACKAGE
+ Package option
+ 0x008
+ read-only
+ 0xFFFFFFFF
+
+
+ PACKAGE
+ Package option
+ 0
+ 31
+
+
+ QD
+ QDxx - 40-pin QFN
+ 0x2007
+
+
+ QI
+ QIxx - 73-pin aQFN
+ 0x2004
+
+
+ CJ
+ CJxx - WLCSP
+ 0x2008
+
+
+ Unspecified
+ Unspecified
+ 0xFFFFFFFF
+
+
+
+
+
+
+ RAM
+ RAM variant
+ 0x00C
+ read-only
+ 0xFFFFFFFF
+
+
+ RAM
+ RAM variant
+ 0
+ 31
+
+
+ K16
+ 16 kByte RAM
+ 0x10
+
+
+ K32
+ 32 kByte RAM
+ 0x20
+
+
+ K64
+ 64 kByte RAM
+ 0x40
+
+
+ K128
+ 128 kByte RAM
+ 0x80
+
+
+ K256
+ 256 kByte RAM
+ 0x100
+
+
+ Unspecified
+ Unspecified
+ 0xFFFFFFFF
+
+
+
+
+
+
+ FLASH
+ Flash variant
+ 0x010
+ read-only
+ 0xFFFFFFFF
+
+
+ FLASH
+ Flash variant
+ 0
+ 31
+
+
+ K128
+ 128 kByte FLASH
+ 0x80
+
+
+ K256
+ 256 kByte FLASH
+ 0x100
+
+
+ K512
+ 512 kByte FLASH
+ 0x200
+
+
+ K1024
+ 1 MByte FLASH
+ 0x400
+
+
+ K2048
+ 2 MByte FLASH
+ 0x800
+
+
+ Unspecified
+ Unspecified
+ 0xFFFFFFFF
+
+
+
+
+
+
+
+ 0x3
+ 0x4
+ PRODTEST[%s]
+ Description collection: Production test signature n
+ 0x350
+ read-only
+ 0xFFFFFFFF
+
+
+ PRODTEST
+ Production test signature n
+ 0
+ 31
+
+
+ Done
+ Production tests done
+ 0xBB42319F
+
+
+ NotDone
+ Production tests not done
+ 0xFFFFFFFF
+
+
+
+
+
+
+ TEMP
+ Registers storing factory TEMP module linearization coefficients
+ FICR_TEMP
+ read-only
+ 0x404
+
+ A0
+ Slope definition A0
+ 0x000
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register.
+ 0
+ 11
+
+
+
+
+ A1
+ Slope definition A1
+ 0x004
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register.
+ 0
+ 11
+
+
+
+
+ A2
+ Slope definition A2
+ 0x008
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register.
+ 0
+ 11
+
+
+
+
+ A3
+ Slope definition A3
+ 0x00C
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register.
+ 0
+ 11
+
+
+
+
+ A4
+ Slope definition A4
+ 0x010
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register.
+ 0
+ 11
+
+
+
+
+ A5
+ Slope definition A5
+ 0x014
+ read-only
+ 0xFFFFFFFF
+
+
+ A
+ A (slope definition) register.
+ 0
+ 11
+
+
+
+
+ B0
+ Y-intercept B0
+ 0x018
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ B1
+ Y-intercept B1
+ 0x01C
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ B2
+ Y-intercept B2
+ 0x020
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ B3
+ Y-intercept B3
+ 0x024
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ B4
+ Y-intercept B4
+ 0x028
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ B5
+ Y-intercept B5
+ 0x02C
+ read-only
+ 0xFFFFFFFF
+
+
+ B
+ B (y-intercept)
+ 0
+ 13
+
+
+
+
+ T0
+ Segment end T0
+ 0x030
+ read-only
+ 0xFFFFFFFF
+
+
+ T
+ T (segment end) register
+ 0
+ 7
+
+
+
+
+ T1
+ Segment end T1
+ 0x034
+ read-only
+ 0xFFFFFFFF
+
+
+ T
+ T (segment end) register
+ 0
+ 7
+
+
+
+
+ T2
+ Segment end T2
+ 0x038
+ read-only
+ 0xFFFFFFFF
+
+
+ T
+ T (segment end) register
+ 0
+ 7
+
+
+
+
+ T3
+ Segment end T3
+ 0x03C
+ read-only
+ 0xFFFFFFFF
+
+
+ T
+ T (segment end) register
+ 0
+ 7
+
+
+
+
+ T4
+ Segment end T4
+ 0x040
+ read-only
+ 0xFFFFFFFF
+
+
+ T
+ T (segment end) register
+ 0
+ 7
+
+
+
+
+
+ NFC
+ Unspecified
+ FICR_NFC
+ read-write
+ 0x450
+
+ TAGHEADER0
+ Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST.
+ 0x000
+ read-only
+ 0xFFFFFF5F
+
+
+ MFGID
+ Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F
+ 0
+ 7
+
+
+ UD1
+ Unique identifier byte 1
+ 8
+ 15
+
+
+ UD2
+ Unique identifier byte 2
+ 16
+ 23
+
+
+ UD3
+ Unique identifier byte 3
+ 24
+ 31
+
+
+
+
+ TAGHEADER1
+ Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST.
+ 0x004
+ read-only
+ 0xFFFFFFFF
+
+
+ UD4
+ Unique identifier byte 4
+ 0
+ 7
+
+
+ UD5
+ Unique identifier byte 5
+ 8
+ 15
+
+
+ UD6
+ Unique identifier byte 6
+ 16
+ 23
+
+
+ UD7
+ Unique identifier byte 7
+ 24
+ 31
+
+
+
+
+ TAGHEADER2
+ Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST.
+ 0x008
+ read-only
+ 0xFFFFFFFF
+
+
+ UD8
+ Unique identifier byte 8
+ 0
+ 7
+
+
+ UD9
+ Unique identifier byte 9
+ 8
+ 15
+
+
+ UD10
+ Unique identifier byte 10
+ 16
+ 23
+
+
+ UD11
+ Unique identifier byte 11
+ 24
+ 31
+
+
+
+
+ TAGHEADER3
+ Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST.
+ 0x00C
+ read-only
+ 0xFFFFFFFF
+
+
+ UD12
+ Unique identifier byte 12
+ 0
+ 7
+
+
+ UD13
+ Unique identifier byte 13
+ 8
+ 15
+
+
+ UD14
+ Unique identifier byte 14
+ 16
+ 23
+
+
+ UD15
+ Unique identifier byte 15
+ 24
+ 31
+
+
+
+
+
+
+
+ UICR
+ User information configuration registers
+ 0x10001000
+
+ 0
+ 0x1000
+ registers
+
+ UICR
+ 0x20
+
+
+ 0xD
+ 0x4
+ NRFFW[%s]
+ Description collection: Reserved for Nordic firmware design
+ 0x014
+ read-write
+ 0xFFFFFFFF
+
+
+ NRFFW
+ Reserved for Nordic firmware design
+ 0
+ 31
+
+
+
+
+ 0xC
+ 0x4
+ NRFHW[%s]
+ Description collection: Reserved for Nordic hardware design
+ 0x050
+ read-write
+ 0xFFFFFFFF
+
+
+ NRFHW
+ Reserved for Nordic hardware design
+ 0
+ 31
+
+
+
+
+ 0x20
+ 0x4
+ CUSTOMER[%s]
+ Description collection: Reserved for customer
+ 0x080
+ read-write
+ 0xFFFFFFFF
+
+
+ CUSTOMER
+ Reserved for customer
+ 0
+ 31
+
+
+
+
+ 0x2
+ 0x4
+ PSELRESET[%s]
+ Description collection: Mapping of the nRESET function (see POWER chapter for details)
+ 0x200
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ GPIO pin number onto which nRESET is exposed
+ 0
+ 4
+
+
+ PORT
+ Port number onto which nRESET is exposed
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ APPROTECT
+ Access port protection
+ 0x208
+ read-write
+ 0xFFFFFFFF
+
+
+ PALL
+ Enable or disable access port protection.
+ 0
+ 7
+
+
+ Disabled
+ Disable
+ 0xFF
+
+
+ Enabled
+ Enable
+ 0x00
+
+
+
+
+
+
+ NFCPINS
+ Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
+ 0x20C
+ read-write
+ 0xFFFFFFFF
+
+
+ PROTECT
+ Setting of pins dedicated to NFC functionality
+ 0
+ 0
+
+
+ Disabled
+ Operation as GPIO pins. Same protection as normal GPIO pins
+ 0
+
+
+ NFC
+ Operation as NFC antenna pins. Configures the protection for NFC operation
+ 1
+
+
+
+
+
+
+ DEBUGCTRL
+ Processor debug control
+ 0x210
+ read-write
+ 0xFFFFFFFF
+
+
+ CPUNIDEN
+ Configure CPU non-intrusive debug features
+ 0
+ 7
+
+
+ Enabled
+ Enable CPU ITM and ETM functionality (default behavior)
+ 0xFF
+
+
+ Disabled
+ Disable CPU ITM and ETM functionality
+ 0x00
+
+
+
+
+ CPUFPBEN
+ Configure CPU flash patch and breakpoint (FPB) unit behavior
+ 8
+ 15
+
+
+ Enabled
+ Enable CPU FPB unit (default behavior)
+ 0xFF
+
+
+ Disabled
+ Disable CPU FPB unit. Writes into the FPB registers will be ignored.
+ 0x00
+
+
+
+
+
+
+ REGOUT0
+ Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP.
+ 0x304
+ read-write
+ 0xFFFFFFFF
+
+
+ VOUT
+ Output voltage from REG0 regulator stage.
+ 0
+ 2
+
+
+ 1V8
+ 1.8 V
+ 0
+
+
+ 2V1
+ 2.1 V
+ 1
+
+
+ 2V4
+ 2.4 V
+ 2
+
+
+ 2V7
+ 2.7 V
+ 3
+
+
+ 3V0
+ 3.0 V
+ 4
+
+
+ 3V3
+ 3.3 V
+ 5
+
+
+ DEFAULT
+ Default voltage: 1.8 V
+ 7
+
+
+
+
+
+
+
+
+ CLOCK
+ Clock control
+ 0x40000000
+
+ 0
+ 0x1000
+ registers
+
+
+ POWER_CLOCK
+ 0
+
+ CLOCK
+ 0x20
+
+
+ TASKS_HFCLKSTART
+ Start HFXO crystal oscillator
+ 0x000
+ write-only
+
+
+ TASKS_HFCLKSTART
+ Start HFXO crystal oscillator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_HFCLKSTOP
+ Stop HFXO crystal oscillator
+ 0x004
+ write-only
+
+
+ TASKS_HFCLKSTOP
+ Stop HFXO crystal oscillator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_LFCLKSTART
+ Start LFCLK
+ 0x008
+ write-only
+
+
+ TASKS_LFCLKSTART
+ Start LFCLK
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_LFCLKSTOP
+ Stop LFCLK
+ 0x00C
+ write-only
+
+
+ TASKS_LFCLKSTOP
+ Stop LFCLK
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CAL
+ Start calibration of LFRC
+ 0x010
+ write-only
+
+
+ TASKS_CAL
+ Start calibration of LFRC
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CTSTART
+ Start calibration timer
+ 0x014
+ write-only
+
+
+ TASKS_CTSTART
+ Start calibration timer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CTSTOP
+ Stop calibration timer
+ 0x018
+ write-only
+
+
+ TASKS_CTSTOP
+ Stop calibration timer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_HFCLKSTARTED
+ HFXO crystal oscillator started
+ 0x100
+ read-write
+
+
+ EVENTS_HFCLKSTARTED
+ HFXO crystal oscillator started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_LFCLKSTARTED
+ LFCLK started
+ 0x104
+ read-write
+
+
+ EVENTS_LFCLKSTARTED
+ LFCLK started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DONE
+ Calibration of LFRC completed
+ 0x10C
+ read-write
+
+
+ EVENTS_DONE
+ Calibration of LFRC completed
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CTTO
+ Calibration timer timeout
+ 0x110
+ read-write
+
+
+ EVENTS_CTTO
+ Calibration timer timeout
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CTSTARTED
+ Calibration timer has been started and is ready to process new tasks
+ 0x128
+ read-write
+
+
+ EVENTS_CTSTARTED
+ Calibration timer has been started and is ready to process new tasks
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CTSTOPPED
+ Calibration timer has been stopped and is ready to process new tasks
+ 0x12C
+ read-write
+
+
+ EVENTS_CTSTOPPED
+ Calibration timer has been stopped and is ready to process new tasks
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ HFCLKSTARTED
+ Write '1' to enable interrupt for event HFCLKSTARTED
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ LFCLKSTARTED
+ Write '1' to enable interrupt for event LFCLKSTARTED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DONE
+ Write '1' to enable interrupt for event DONE
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CTTO
+ Write '1' to enable interrupt for event CTTO
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CTSTARTED
+ Write '1' to enable interrupt for event CTSTARTED
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CTSTOPPED
+ Write '1' to enable interrupt for event CTSTOPPED
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ HFCLKSTARTED
+ Write '1' to disable interrupt for event HFCLKSTARTED
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ LFCLKSTARTED
+ Write '1' to disable interrupt for event LFCLKSTARTED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DONE
+ Write '1' to disable interrupt for event DONE
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CTTO
+ Write '1' to disable interrupt for event CTTO
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CTSTARTED
+ Write '1' to disable interrupt for event CTSTARTED
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CTSTOPPED
+ Write '1' to disable interrupt for event CTSTOPPED
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ HFCLKRUN
+ Status indicating that HFCLKSTART task has been triggered
+ 0x408
+ read-only
+
+
+ STATUS
+ HFCLKSTART task triggered or not
+ 0
+ 0
+
+
+ NotTriggered
+ Task not triggered
+ 0
+
+
+ Triggered
+ Task triggered
+ 1
+
+
+
+
+
+
+ HFCLKSTAT
+ HFCLK status
+ 0x40C
+ read-only
+
+
+ SRC
+ Source of HFCLK
+ 0
+ 0
+
+
+ RC
+ 64 MHz internal oscillator (HFINT)
+ 0
+
+
+ Xtal
+ 64 MHz crystal oscillator (HFXO)
+ 1
+
+
+
+
+ STATE
+ HFCLK state
+ 16
+ 16
+
+
+ NotRunning
+ HFCLK not running
+ 0
+
+
+ Running
+ HFCLK running
+ 1
+
+
+
+
+
+
+ LFCLKRUN
+ Status indicating that LFCLKSTART task has been triggered
+ 0x414
+ read-only
+
+
+ STATUS
+ LFCLKSTART task triggered or not
+ 0
+ 0
+
+
+ NotTriggered
+ Task not triggered
+ 0
+
+
+ Triggered
+ Task triggered
+ 1
+
+
+
+
+
+
+ LFCLKSTAT
+ LFCLK status
+ 0x418
+ read-only
+
+
+ SRC
+ Source of LFCLK
+ 0
+ 1
+
+
+ RC
+ 32.768 kHz RC oscillator (LFRC)
+ 0
+
+
+ Xtal
+ 32.768 kHz crystal oscillator (LFXO)
+ 1
+
+
+ Synth
+ 32.768 kHz synthesized from HFCLK (LFSYNT)
+ 2
+
+
+
+
+ STATE
+ LFCLK state
+ 16
+ 16
+
+
+ NotRunning
+ LFCLK not running
+ 0
+
+
+ Running
+ LFCLK running
+ 1
+
+
+
+
+
+
+ LFCLKSRCCOPY
+ Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
+ 0x41C
+ read-only
+
+
+ SRC
+ Clock source
+ 0
+ 1
+
+
+ RC
+ 32.768 kHz RC oscillator (LFRC)
+ 0
+
+
+ Xtal
+ 32.768 kHz crystal oscillator (LFXO)
+ 1
+
+
+ Synth
+ 32.768 kHz synthesized from HFCLK (LFSYNT)
+ 2
+
+
+
+
+
+
+ LFCLKSRC
+ Clock source for the LFCLK
+ 0x518
+ read-write
+
+
+ SRC
+ Clock source
+ 0
+ 1
+
+
+ RC
+ 32.768 kHz RC oscillator (LFRC)
+ 0
+
+
+ Xtal
+ 32.768 kHz crystal oscillator (LFXO)
+ 1
+
+
+ Synth
+ 32.768 kHz synthesized from HFCLK (LFSYNT)
+ 2
+
+
+
+
+ BYPASS
+ Enable or disable bypass of LFCLK crystal oscillator with external clock source
+ 16
+ 16
+
+
+ Disabled
+ Disable (use with Xtal or low-swing external source)
+ 0
+
+
+ Enabled
+ Enable (use with rail-to-rail external source)
+ 1
+
+
+
+
+ EXTERNAL
+ Enable or disable external source for LFCLK
+ 17
+ 17
+
+
+ Disabled
+ Disable external source (use with Xtal)
+ 0
+
+
+ Enabled
+ Enable use of external source instead of Xtal (SRC needs to be set to Xtal)
+ 1
+
+
+
+
+
+
+ HFXODEBOUNCE
+ HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task.
+ 0x528
+ read-write
+ 0x00000010
+
+
+ HFXODEBOUNCE
+ HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us.
+ 0
+ 7
+
+
+ Db256us
+ 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals.
+ 0x10
+
+
+ Db1024us
+ 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals.
+ 0x40
+
+
+
+
+
+
+ LFXODEBOUNCE
+ LFXO debounce time. The LFXO is started by triggering the TASKS_LFCLKSTART task when the LFCLKSRC register is configured for Xtal.
+ 0x52C
+ read-write
+ 0x00000000
+
+
+ LFXODEBOUNCE
+ LFXO debounce time.
+ 0
+ 0
+
+
+ Normal
+ 8192 32.768 kHz periods, or 0.25 s. Recommended for normal Operating Temperature conditions.
+ 0
+
+
+ Extended
+ 16384 32.768 kHz periods, or 0.5 s. Recommended for Extended Operating Temperature conditions.
+ 1
+
+
+
+
+
+
+ CTIV
+ Calibration timer interval
+ 0x538
+ read-write
+
+
+ CTIV
+ Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.
+ 0
+ 6
+
+
+
+
+ TRACECONFIG
+ Clocking options for the trace port debug interface
+ 0x55C
+ read-write
+ 0x00000000
+
+
+ TRACEPORTSPEED
+ Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two.
+ 0
+ 1
+
+
+ 32MHz
+ 32 MHz trace port clock (TRACECLK = 16 MHz)
+ 0
+
+
+ 16MHz
+ 16 MHz trace port clock (TRACECLK = 8 MHz)
+ 1
+
+
+ 8MHz
+ 8 MHz trace port clock (TRACECLK = 4 MHz)
+ 2
+
+
+ 4MHz
+ 4 MHz trace port clock (TRACECLK = 2 MHz)
+ 3
+
+
+
+
+ TRACEMUX
+ Pin multiplexing of trace signals. See pin assignment chapter for more details.
+ 16
+ 17
+
+
+ GPIO
+ No trace signals routed to pins. All pins can be used as regular GPIOs.
+ 0
+
+
+ Serial
+ SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs.
+ 1
+
+
+ Parallel
+ All trace signals (TRACECLK and TRACEDATA[n]) routed to pins.
+ 2
+
+
+
+
+
+
+
+
+ POWER
+ Power control
+ 0x40000000
+ CLOCK
+
+ 0
+ 0x1000
+ registers
+
+
+ POWER_CLOCK
+ 0
+
+ POWER
+ 0x20
+
+
+ TASKS_CONSTLAT
+ Enable Constant Latency mode
+ 0x78
+ write-only
+
+
+ TASKS_CONSTLAT
+ Enable Constant Latency mode
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_LOWPWR
+ Enable Low-power mode (variable latency)
+ 0x7C
+ write-only
+
+
+ TASKS_LOWPWR
+ Enable Low-power mode (variable latency)
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_POFWARN
+ Power failure warning
+ 0x108
+ read-write
+
+
+ EVENTS_POFWARN
+ Power failure warning
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_SLEEPENTER
+ CPU entered WFI/WFE sleep
+ 0x114
+ read-write
+
+
+ EVENTS_SLEEPENTER
+ CPU entered WFI/WFE sleep
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_SLEEPEXIT
+ CPU exited WFI/WFE sleep
+ 0x118
+ read-write
+
+
+ EVENTS_SLEEPEXIT
+ CPU exited WFI/WFE sleep
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_USBDETECTED
+ Voltage supply detected on VBUS
+ 0x11C
+ read-write
+
+
+ EVENTS_USBDETECTED
+ Voltage supply detected on VBUS
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_USBREMOVED
+ Voltage supply removed from VBUS
+ 0x120
+ read-write
+
+
+ EVENTS_USBREMOVED
+ Voltage supply removed from VBUS
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_USBPWRRDY
+ USB 3.3 V supply ready
+ 0x124
+ read-write
+
+
+ EVENTS_USBPWRRDY
+ USB 3.3 V supply ready
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ POFWARN
+ Write '1' to enable interrupt for event POFWARN
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SLEEPENTER
+ Write '1' to enable interrupt for event SLEEPENTER
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SLEEPEXIT
+ Write '1' to enable interrupt for event SLEEPEXIT
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ USBDETECTED
+ Write '1' to enable interrupt for event USBDETECTED
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ USBREMOVED
+ Write '1' to enable interrupt for event USBREMOVED
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ USBPWRRDY
+ Write '1' to enable interrupt for event USBPWRRDY
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ POFWARN
+ Write '1' to disable interrupt for event POFWARN
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SLEEPENTER
+ Write '1' to disable interrupt for event SLEEPENTER
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SLEEPEXIT
+ Write '1' to disable interrupt for event SLEEPEXIT
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ USBDETECTED
+ Write '1' to disable interrupt for event USBDETECTED
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ USBREMOVED
+ Write '1' to disable interrupt for event USBREMOVED
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ USBPWRRDY
+ Write '1' to disable interrupt for event USBPWRRDY
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ RESETREAS
+ Reset reason
+ 0x400
+ read-write
+
+
+ RESETPIN
+ Reset from pin-reset detected
+ 0
+ 0
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ DOG
+ Reset from watchdog detected
+ 1
+ 1
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ SREQ
+ Reset from soft reset detected
+ 2
+ 2
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ LOCKUP
+ Reset from CPU lock-up detected
+ 3
+ 3
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ OFF
+ Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO
+ 16
+ 16
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ LPCOMP
+ Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP
+ 17
+ 17
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ DIF
+ Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode
+ 18
+ 18
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ NFC
+ Reset due to wake up from System OFF mode by NFC field detect
+ 19
+ 19
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+ VBUS
+ Reset due to wake up from System OFF mode by VBUS rising into valid range
+ 20
+ 20
+
+
+ NotDetected
+ Not detected
+ 0
+
+
+ Detected
+ Detected
+ 1
+
+
+
+
+
+
+ RAMSTATUS
+ Deprecated register - RAM status register
+ 0x428
+ read-only
+ 0x00000000
+
+
+ RAMBLOCK0
+ RAM block 0 is on or off/powering up
+ 0
+ 0
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ RAMBLOCK1
+ RAM block 1 is on or off/powering up
+ 1
+ 1
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ RAMBLOCK2
+ RAM block 2 is on or off/powering up
+ 2
+ 2
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ RAMBLOCK3
+ RAM block 3 is on or off/powering up
+ 3
+ 3
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+
+
+ USBREGSTATUS
+ USB supply status
+ 0x438
+ read-only
+ 0x00000000
+
+
+ VBUSDETECT
+ VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information)
+ 0
+ 0
+
+
+ NoVbus
+ VBUS voltage below valid threshold
+ 0
+
+
+ VbusPresent
+ VBUS voltage above valid threshold
+ 1
+
+
+
+
+ OUTPUTRDY
+ USB supply output settling time elapsed
+ 1
+ 1
+
+
+ NotReady
+ USBREG output settling time not elapsed
+ 0
+
+
+ Ready
+ USBREG output settling time elapsed (same information as USBPWRRDY event)
+ 1
+
+
+
+
+
+
+ SYSTEMOFF
+ System OFF register
+ 0x500
+ write-only
+
+
+ SYSTEMOFF
+ Enable System OFF mode
+ 0
+ 0
+
+
+ Enter
+ Enable System OFF mode
+ 1
+
+
+
+
+
+
+ POFCON
+ Power-fail comparator configuration
+ 0x510
+ read-write
+
+
+ POF
+ Enable or disable power failure warning
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ THRESHOLD
+ Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages.
+ 1
+ 4
+
+
+ V17
+ Set threshold to 1.7 V
+ 4
+
+
+ V18
+ Set threshold to 1.8 V
+ 5
+
+
+ V19
+ Set threshold to 1.9 V
+ 6
+
+
+ V20
+ Set threshold to 2.0 V
+ 7
+
+
+ V21
+ Set threshold to 2.1 V
+ 8
+
+
+ V22
+ Set threshold to 2.2 V
+ 9
+
+
+ V23
+ Set threshold to 2.3 V
+ 10
+
+
+ V24
+ Set threshold to 2.4 V
+ 11
+
+
+ V25
+ Set threshold to 2.5 V
+ 12
+
+
+ V26
+ Set threshold to 2.6 V
+ 13
+
+
+ V27
+ Set threshold to 2.7 V
+ 14
+
+
+ V28
+ Set threshold to 2.8 V
+ 15
+
+
+
+
+ THRESHOLDVDDH
+ Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH).
+ 8
+ 11
+
+
+ V27
+ Set threshold to 2.7 V
+ 0
+
+
+ V28
+ Set threshold to 2.8 V
+ 1
+
+
+ V29
+ Set threshold to 2.9 V
+ 2
+
+
+ V30
+ Set threshold to 3.0 V
+ 3
+
+
+ V31
+ Set threshold to 3.1 V
+ 4
+
+
+ V32
+ Set threshold to 3.2 V
+ 5
+
+
+ V33
+ Set threshold to 3.3 V
+ 6
+
+
+ V34
+ Set threshold to 3.4 V
+ 7
+
+
+ V35
+ Set threshold to 3.5 V
+ 8
+
+
+ V36
+ Set threshold to 3.6 V
+ 9
+
+
+ V37
+ Set threshold to 3.7 V
+ 10
+
+
+ V38
+ Set threshold to 3.8 V
+ 11
+
+
+ V39
+ Set threshold to 3.9 V
+ 12
+
+
+ V40
+ Set threshold to 4.0 V
+ 13
+
+
+ V41
+ Set threshold to 4.1 V
+ 14
+
+
+ V42
+ Set threshold to 4.2 V
+ 15
+
+
+
+
+
+
+ GPREGRET
+ General purpose retention register
+ 0x51C
+ read-write
+
+
+ GPREGRET
+ General purpose retention register
+ 0
+ 7
+
+
+
+
+ GPREGRET2
+ General purpose retention register
+ 0x520
+ read-write
+
+
+ GPREGRET
+ General purpose retention register
+ 0
+ 7
+
+
+
+
+ DCDCEN
+ Enable DC/DC converter for REG1 stage
+ 0x578
+ read-write
+
+
+ DCDCEN
+ Enable DC/DC converter for REG1 stage.
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ MAINREGSTATUS
+ Main supply status
+ 0x640
+ read-only
+ 0x00000000
+
+
+ MAINREGSTATUS
+ Main supply status
+ 0
+ 0
+
+
+ Normal
+ Normal voltage mode. Voltage supplied on VDD.
+ 0
+
+
+ High
+ High voltage mode. Voltage supplied on VDDH.
+ 1
+
+
+
+
+
+
+ 9
+ 0x010
+ RAM[%s]
+ Unspecified
+ POWER_RAM
+ read-write
+ 0x900
+
+ POWER
+ Description cluster: RAMn power control register
+ 0x000
+ read-write
+ 0x0000FFFF
+
+
+ S0POWER
+ Keep RAM section S0 on or off in System ON mode.
+ 0
+ 0
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S1POWER
+ Keep RAM section S1 on or off in System ON mode.
+ 1
+ 1
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S2POWER
+ Keep RAM section S2 on or off in System ON mode.
+ 2
+ 2
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S3POWER
+ Keep RAM section S3 on or off in System ON mode.
+ 3
+ 3
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S4POWER
+ Keep RAM section S4 on or off in System ON mode.
+ 4
+ 4
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S5POWER
+ Keep RAM section S5 on or off in System ON mode.
+ 5
+ 5
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S6POWER
+ Keep RAM section S6 on or off in System ON mode.
+ 6
+ 6
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S7POWER
+ Keep RAM section S7 on or off in System ON mode.
+ 7
+ 7
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S8POWER
+ Keep RAM section S8 on or off in System ON mode.
+ 8
+ 8
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S9POWER
+ Keep RAM section S9 on or off in System ON mode.
+ 9
+ 9
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S10POWER
+ Keep RAM section S10 on or off in System ON mode.
+ 10
+ 10
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S11POWER
+ Keep RAM section S11 on or off in System ON mode.
+ 11
+ 11
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S12POWER
+ Keep RAM section S12 on or off in System ON mode.
+ 12
+ 12
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S13POWER
+ Keep RAM section S13 on or off in System ON mode.
+ 13
+ 13
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S14POWER
+ Keep RAM section S14 on or off in System ON mode.
+ 14
+ 14
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S15POWER
+ Keep RAM section S15 on or off in System ON mode.
+ 15
+ 15
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S0RETENTION
+ Keep retention on RAM section S0 when RAM section is off
+ 16
+ 16
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S1RETENTION
+ Keep retention on RAM section S1 when RAM section is off
+ 17
+ 17
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S2RETENTION
+ Keep retention on RAM section S2 when RAM section is off
+ 18
+ 18
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S3RETENTION
+ Keep retention on RAM section S3 when RAM section is off
+ 19
+ 19
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S4RETENTION
+ Keep retention on RAM section S4 when RAM section is off
+ 20
+ 20
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S5RETENTION
+ Keep retention on RAM section S5 when RAM section is off
+ 21
+ 21
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S6RETENTION
+ Keep retention on RAM section S6 when RAM section is off
+ 22
+ 22
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S7RETENTION
+ Keep retention on RAM section S7 when RAM section is off
+ 23
+ 23
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S8RETENTION
+ Keep retention on RAM section S8 when RAM section is off
+ 24
+ 24
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S9RETENTION
+ Keep retention on RAM section S9 when RAM section is off
+ 25
+ 25
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S10RETENTION
+ Keep retention on RAM section S10 when RAM section is off
+ 26
+ 26
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S11RETENTION
+ Keep retention on RAM section S11 when RAM section is off
+ 27
+ 27
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S12RETENTION
+ Keep retention on RAM section S12 when RAM section is off
+ 28
+ 28
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S13RETENTION
+ Keep retention on RAM section S13 when RAM section is off
+ 29
+ 29
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S14RETENTION
+ Keep retention on RAM section S14 when RAM section is off
+ 30
+ 30
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S15RETENTION
+ Keep retention on RAM section S15 when RAM section is off
+ 31
+ 31
+
+
+ Off
+ Off
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+
+
+ POWERSET
+ Description cluster: RAMn power control set register
+ 0x004
+ write-only
+ 0x0000FFFF
+
+
+ S0POWER
+ Keep RAM section S0 of RAMn on or off in System ON mode
+ 0
+ 0
+
+
+ On
+ On
+ 1
+
+
+
+
+ S1POWER
+ Keep RAM section S1 of RAMn on or off in System ON mode
+ 1
+ 1
+
+
+ On
+ On
+ 1
+
+
+
+
+ S2POWER
+ Keep RAM section S2 of RAMn on or off in System ON mode
+ 2
+ 2
+
+
+ On
+ On
+ 1
+
+
+
+
+ S3POWER
+ Keep RAM section S3 of RAMn on or off in System ON mode
+ 3
+ 3
+
+
+ On
+ On
+ 1
+
+
+
+
+ S4POWER
+ Keep RAM section S4 of RAMn on or off in System ON mode
+ 4
+ 4
+
+
+ On
+ On
+ 1
+
+
+
+
+ S5POWER
+ Keep RAM section S5 of RAMn on or off in System ON mode
+ 5
+ 5
+
+
+ On
+ On
+ 1
+
+
+
+
+ S6POWER
+ Keep RAM section S6 of RAMn on or off in System ON mode
+ 6
+ 6
+
+
+ On
+ On
+ 1
+
+
+
+
+ S7POWER
+ Keep RAM section S7 of RAMn on or off in System ON mode
+ 7
+ 7
+
+
+ On
+ On
+ 1
+
+
+
+
+ S8POWER
+ Keep RAM section S8 of RAMn on or off in System ON mode
+ 8
+ 8
+
+
+ On
+ On
+ 1
+
+
+
+
+ S9POWER
+ Keep RAM section S9 of RAMn on or off in System ON mode
+ 9
+ 9
+
+
+ On
+ On
+ 1
+
+
+
+
+ S10POWER
+ Keep RAM section S10 of RAMn on or off in System ON mode
+ 10
+ 10
+
+
+ On
+ On
+ 1
+
+
+
+
+ S11POWER
+ Keep RAM section S11 of RAMn on or off in System ON mode
+ 11
+ 11
+
+
+ On
+ On
+ 1
+
+
+
+
+ S12POWER
+ Keep RAM section S12 of RAMn on or off in System ON mode
+ 12
+ 12
+
+
+ On
+ On
+ 1
+
+
+
+
+ S13POWER
+ Keep RAM section S13 of RAMn on or off in System ON mode
+ 13
+ 13
+
+
+ On
+ On
+ 1
+
+
+
+
+ S14POWER
+ Keep RAM section S14 of RAMn on or off in System ON mode
+ 14
+ 14
+
+
+ On
+ On
+ 1
+
+
+
+
+ S15POWER
+ Keep RAM section S15 of RAMn on or off in System ON mode
+ 15
+ 15
+
+
+ On
+ On
+ 1
+
+
+
+
+ S0RETENTION
+ Keep retention on RAM section S0 when RAM section is switched off
+ 16
+ 16
+
+
+ On
+ On
+ 1
+
+
+
+
+ S1RETENTION
+ Keep retention on RAM section S1 when RAM section is switched off
+ 17
+ 17
+
+
+ On
+ On
+ 1
+
+
+
+
+ S2RETENTION
+ Keep retention on RAM section S2 when RAM section is switched off
+ 18
+ 18
+
+
+ On
+ On
+ 1
+
+
+
+
+ S3RETENTION
+ Keep retention on RAM section S3 when RAM section is switched off
+ 19
+ 19
+
+
+ On
+ On
+ 1
+
+
+
+
+ S4RETENTION
+ Keep retention on RAM section S4 when RAM section is switched off
+ 20
+ 20
+
+
+ On
+ On
+ 1
+
+
+
+
+ S5RETENTION
+ Keep retention on RAM section S5 when RAM section is switched off
+ 21
+ 21
+
+
+ On
+ On
+ 1
+
+
+
+
+ S6RETENTION
+ Keep retention on RAM section S6 when RAM section is switched off
+ 22
+ 22
+
+
+ On
+ On
+ 1
+
+
+
+
+ S7RETENTION
+ Keep retention on RAM section S7 when RAM section is switched off
+ 23
+ 23
+
+
+ On
+ On
+ 1
+
+
+
+
+ S8RETENTION
+ Keep retention on RAM section S8 when RAM section is switched off
+ 24
+ 24
+
+
+ On
+ On
+ 1
+
+
+
+
+ S9RETENTION
+ Keep retention on RAM section S9 when RAM section is switched off
+ 25
+ 25
+
+
+ On
+ On
+ 1
+
+
+
+
+ S10RETENTION
+ Keep retention on RAM section S10 when RAM section is switched off
+ 26
+ 26
+
+
+ On
+ On
+ 1
+
+
+
+
+ S11RETENTION
+ Keep retention on RAM section S11 when RAM section is switched off
+ 27
+ 27
+
+
+ On
+ On
+ 1
+
+
+
+
+ S12RETENTION
+ Keep retention on RAM section S12 when RAM section is switched off
+ 28
+ 28
+
+
+ On
+ On
+ 1
+
+
+
+
+ S13RETENTION
+ Keep retention on RAM section S13 when RAM section is switched off
+ 29
+ 29
+
+
+ On
+ On
+ 1
+
+
+
+
+ S14RETENTION
+ Keep retention on RAM section S14 when RAM section is switched off
+ 30
+ 30
+
+
+ On
+ On
+ 1
+
+
+
+
+ S15RETENTION
+ Keep retention on RAM section S15 when RAM section is switched off
+ 31
+ 31
+
+
+ On
+ On
+ 1
+
+
+
+
+
+
+ POWERCLR
+ Description cluster: RAMn power control clear register
+ 0x008
+ write-only
+ 0x0000FFFF
+
+
+ S0POWER
+ Keep RAM section S0 of RAMn on or off in System ON mode
+ 0
+ 0
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S1POWER
+ Keep RAM section S1 of RAMn on or off in System ON mode
+ 1
+ 1
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S2POWER
+ Keep RAM section S2 of RAMn on or off in System ON mode
+ 2
+ 2
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S3POWER
+ Keep RAM section S3 of RAMn on or off in System ON mode
+ 3
+ 3
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S4POWER
+ Keep RAM section S4 of RAMn on or off in System ON mode
+ 4
+ 4
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S5POWER
+ Keep RAM section S5 of RAMn on or off in System ON mode
+ 5
+ 5
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S6POWER
+ Keep RAM section S6 of RAMn on or off in System ON mode
+ 6
+ 6
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S7POWER
+ Keep RAM section S7 of RAMn on or off in System ON mode
+ 7
+ 7
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S8POWER
+ Keep RAM section S8 of RAMn on or off in System ON mode
+ 8
+ 8
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S9POWER
+ Keep RAM section S9 of RAMn on or off in System ON mode
+ 9
+ 9
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S10POWER
+ Keep RAM section S10 of RAMn on or off in System ON mode
+ 10
+ 10
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S11POWER
+ Keep RAM section S11 of RAMn on or off in System ON mode
+ 11
+ 11
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S12POWER
+ Keep RAM section S12 of RAMn on or off in System ON mode
+ 12
+ 12
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S13POWER
+ Keep RAM section S13 of RAMn on or off in System ON mode
+ 13
+ 13
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S14POWER
+ Keep RAM section S14 of RAMn on or off in System ON mode
+ 14
+ 14
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S15POWER
+ Keep RAM section S15 of RAMn on or off in System ON mode
+ 15
+ 15
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S0RETENTION
+ Keep retention on RAM section S0 when RAM section is switched off
+ 16
+ 16
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S1RETENTION
+ Keep retention on RAM section S1 when RAM section is switched off
+ 17
+ 17
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S2RETENTION
+ Keep retention on RAM section S2 when RAM section is switched off
+ 18
+ 18
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S3RETENTION
+ Keep retention on RAM section S3 when RAM section is switched off
+ 19
+ 19
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S4RETENTION
+ Keep retention on RAM section S4 when RAM section is switched off
+ 20
+ 20
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S5RETENTION
+ Keep retention on RAM section S5 when RAM section is switched off
+ 21
+ 21
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S6RETENTION
+ Keep retention on RAM section S6 when RAM section is switched off
+ 22
+ 22
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S7RETENTION
+ Keep retention on RAM section S7 when RAM section is switched off
+ 23
+ 23
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S8RETENTION
+ Keep retention on RAM section S8 when RAM section is switched off
+ 24
+ 24
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S9RETENTION
+ Keep retention on RAM section S9 when RAM section is switched off
+ 25
+ 25
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S10RETENTION
+ Keep retention on RAM section S10 when RAM section is switched off
+ 26
+ 26
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S11RETENTION
+ Keep retention on RAM section S11 when RAM section is switched off
+ 27
+ 27
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S12RETENTION
+ Keep retention on RAM section S12 when RAM section is switched off
+ 28
+ 28
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S13RETENTION
+ Keep retention on RAM section S13 when RAM section is switched off
+ 29
+ 29
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S14RETENTION
+ Keep retention on RAM section S14 when RAM section is switched off
+ 30
+ 30
+
+
+ Off
+ Off
+ 1
+
+
+
+
+ S15RETENTION
+ Keep retention on RAM section S15 when RAM section is switched off
+ 31
+ 31
+
+
+ Off
+ Off
+ 1
+
+
+
+
+
+
+
+
+
+ P0
+ GPIO Port 1
+ 0x50000000
+ GPIO
+
+ 0
+ 0x1000
+ registers
+
+ GPIO
+ 0x20
+
+
+ OUT
+ Write GPIO port
+ 0x504
+ read-write
+
+
+ PIN0
+ Pin 0
+ 0
+ 0
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN1
+ Pin 1
+ 1
+ 1
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN2
+ Pin 2
+ 2
+ 2
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN3
+ Pin 3
+ 3
+ 3
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN4
+ Pin 4
+ 4
+ 4
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN5
+ Pin 5
+ 5
+ 5
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN6
+ Pin 6
+ 6
+ 6
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN7
+ Pin 7
+ 7
+ 7
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN8
+ Pin 8
+ 8
+ 8
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN9
+ Pin 9
+ 9
+ 9
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN10
+ Pin 10
+ 10
+ 10
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN11
+ Pin 11
+ 11
+ 11
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN12
+ Pin 12
+ 12
+ 12
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN13
+ Pin 13
+ 13
+ 13
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN14
+ Pin 14
+ 14
+ 14
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN15
+ Pin 15
+ 15
+ 15
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN16
+ Pin 16
+ 16
+ 16
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN17
+ Pin 17
+ 17
+ 17
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN18
+ Pin 18
+ 18
+ 18
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN19
+ Pin 19
+ 19
+ 19
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN20
+ Pin 20
+ 20
+ 20
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN21
+ Pin 21
+ 21
+ 21
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN22
+ Pin 22
+ 22
+ 22
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN23
+ Pin 23
+ 23
+ 23
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN24
+ Pin 24
+ 24
+ 24
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN25
+ Pin 25
+ 25
+ 25
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN26
+ Pin 26
+ 26
+ 26
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN27
+ Pin 27
+ 27
+ 27
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN28
+ Pin 28
+ 28
+ 28
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN29
+ Pin 29
+ 29
+ 29
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN30
+ Pin 30
+ 30
+ 30
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+ PIN31
+ Pin 31
+ 31
+ 31
+
+
+ Low
+ Pin driver is low
+ 0
+
+
+ High
+ Pin driver is high
+ 1
+
+
+
+
+
+
+ OUTSET
+ Set individual bits in GPIO port
+ 0x508
+ read-write
+ oneToSet
+
+
+ PIN0
+ Pin 0
+ 0
+ 0
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN1
+ Pin 1
+ 1
+ 1
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN2
+ Pin 2
+ 2
+ 2
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN3
+ Pin 3
+ 3
+ 3
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN4
+ Pin 4
+ 4
+ 4
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN5
+ Pin 5
+ 5
+ 5
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN6
+ Pin 6
+ 6
+ 6
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN7
+ Pin 7
+ 7
+ 7
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN8
+ Pin 8
+ 8
+ 8
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN9
+ Pin 9
+ 9
+ 9
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN10
+ Pin 10
+ 10
+ 10
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN11
+ Pin 11
+ 11
+ 11
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN12
+ Pin 12
+ 12
+ 12
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN13
+ Pin 13
+ 13
+ 13
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN14
+ Pin 14
+ 14
+ 14
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN15
+ Pin 15
+ 15
+ 15
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN16
+ Pin 16
+ 16
+ 16
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN17
+ Pin 17
+ 17
+ 17
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN18
+ Pin 18
+ 18
+ 18
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN19
+ Pin 19
+ 19
+ 19
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN20
+ Pin 20
+ 20
+ 20
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN21
+ Pin 21
+ 21
+ 21
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN22
+ Pin 22
+ 22
+ 22
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN23
+ Pin 23
+ 23
+ 23
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN24
+ Pin 24
+ 24
+ 24
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN25
+ Pin 25
+ 25
+ 25
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN26
+ Pin 26
+ 26
+ 26
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN27
+ Pin 27
+ 27
+ 27
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN28
+ Pin 28
+ 28
+ 28
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN29
+ Pin 29
+ 29
+ 29
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN30
+ Pin 30
+ 30
+ 30
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN31
+ Pin 31
+ 31
+ 31
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets the pin high; writing a '0' has no effect
+ 1
+
+
+
+
+
+
+ OUTCLR
+ Clear individual bits in GPIO port
+ 0x50C
+ read-write
+ oneToClear
+
+
+ PIN0
+ Pin 0
+ 0
+ 0
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN1
+ Pin 1
+ 1
+ 1
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN2
+ Pin 2
+ 2
+ 2
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN3
+ Pin 3
+ 3
+ 3
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN4
+ Pin 4
+ 4
+ 4
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN5
+ Pin 5
+ 5
+ 5
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN6
+ Pin 6
+ 6
+ 6
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN7
+ Pin 7
+ 7
+ 7
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN8
+ Pin 8
+ 8
+ 8
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN9
+ Pin 9
+ 9
+ 9
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN10
+ Pin 10
+ 10
+ 10
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN11
+ Pin 11
+ 11
+ 11
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN12
+ Pin 12
+ 12
+ 12
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN13
+ Pin 13
+ 13
+ 13
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN14
+ Pin 14
+ 14
+ 14
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN15
+ Pin 15
+ 15
+ 15
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN16
+ Pin 16
+ 16
+ 16
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN17
+ Pin 17
+ 17
+ 17
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN18
+ Pin 18
+ 18
+ 18
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN19
+ Pin 19
+ 19
+ 19
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN20
+ Pin 20
+ 20
+ 20
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN21
+ Pin 21
+ 21
+ 21
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN22
+ Pin 22
+ 22
+ 22
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN23
+ Pin 23
+ 23
+ 23
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN24
+ Pin 24
+ 24
+ 24
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN25
+ Pin 25
+ 25
+ 25
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN26
+ Pin 26
+ 26
+ 26
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN27
+ Pin 27
+ 27
+ 27
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN28
+ Pin 28
+ 28
+ 28
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN29
+ Pin 29
+ 29
+ 29
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN30
+ Pin 30
+ 30
+ 30
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN31
+ Pin 31
+ 31
+ 31
+
+ read
+
+ Low
+ Read: pin driver is low
+ 0
+
+
+ High
+ Read: pin driver is high
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets the pin low; writing a '0' has no effect
+ 1
+
+
+
+
+
+
+ IN
+ Read GPIO port
+ 0x510
+ read-only
+
+
+ PIN0
+ Pin 0
+ 0
+ 0
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN1
+ Pin 1
+ 1
+ 1
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN2
+ Pin 2
+ 2
+ 2
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN3
+ Pin 3
+ 3
+ 3
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN4
+ Pin 4
+ 4
+ 4
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN5
+ Pin 5
+ 5
+ 5
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN6
+ Pin 6
+ 6
+ 6
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN7
+ Pin 7
+ 7
+ 7
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN8
+ Pin 8
+ 8
+ 8
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN9
+ Pin 9
+ 9
+ 9
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN10
+ Pin 10
+ 10
+ 10
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN11
+ Pin 11
+ 11
+ 11
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN12
+ Pin 12
+ 12
+ 12
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN13
+ Pin 13
+ 13
+ 13
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN14
+ Pin 14
+ 14
+ 14
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN15
+ Pin 15
+ 15
+ 15
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN16
+ Pin 16
+ 16
+ 16
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN17
+ Pin 17
+ 17
+ 17
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN18
+ Pin 18
+ 18
+ 18
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN19
+ Pin 19
+ 19
+ 19
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN20
+ Pin 20
+ 20
+ 20
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN21
+ Pin 21
+ 21
+ 21
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN22
+ Pin 22
+ 22
+ 22
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN23
+ Pin 23
+ 23
+ 23
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN24
+ Pin 24
+ 24
+ 24
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN25
+ Pin 25
+ 25
+ 25
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN26
+ Pin 26
+ 26
+ 26
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN27
+ Pin 27
+ 27
+ 27
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN28
+ Pin 28
+ 28
+ 28
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN29
+ Pin 29
+ 29
+ 29
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN30
+ Pin 30
+ 30
+ 30
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+ PIN31
+ Pin 31
+ 31
+ 31
+
+
+ Low
+ Pin input is low
+ 0
+
+
+ High
+ Pin input is high
+ 1
+
+
+
+
+
+
+ DIR
+ Direction of GPIO pins
+ 0x514
+ read-write
+
+
+ PIN0
+ Pin 0
+ 0
+ 0
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN1
+ Pin 1
+ 1
+ 1
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN2
+ Pin 2
+ 2
+ 2
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN3
+ Pin 3
+ 3
+ 3
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN4
+ Pin 4
+ 4
+ 4
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN5
+ Pin 5
+ 5
+ 5
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN6
+ Pin 6
+ 6
+ 6
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN7
+ Pin 7
+ 7
+ 7
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN8
+ Pin 8
+ 8
+ 8
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN9
+ Pin 9
+ 9
+ 9
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN10
+ Pin 10
+ 10
+ 10
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN11
+ Pin 11
+ 11
+ 11
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN12
+ Pin 12
+ 12
+ 12
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN13
+ Pin 13
+ 13
+ 13
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN14
+ Pin 14
+ 14
+ 14
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN15
+ Pin 15
+ 15
+ 15
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN16
+ Pin 16
+ 16
+ 16
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN17
+ Pin 17
+ 17
+ 17
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN18
+ Pin 18
+ 18
+ 18
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN19
+ Pin 19
+ 19
+ 19
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN20
+ Pin 20
+ 20
+ 20
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN21
+ Pin 21
+ 21
+ 21
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN22
+ Pin 22
+ 22
+ 22
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN23
+ Pin 23
+ 23
+ 23
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN24
+ Pin 24
+ 24
+ 24
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN25
+ Pin 25
+ 25
+ 25
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN26
+ Pin 26
+ 26
+ 26
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN27
+ Pin 27
+ 27
+ 27
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN28
+ Pin 28
+ 28
+ 28
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN29
+ Pin 29
+ 29
+ 29
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN30
+ Pin 30
+ 30
+ 30
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+ PIN31
+ Pin 31
+ 31
+ 31
+
+
+ Input
+ Pin set as input
+ 0
+
+
+ Output
+ Pin set as output
+ 1
+
+
+
+
+
+
+ DIRSET
+ DIR set register
+ 0x518
+ read-write
+ oneToSet
+
+
+ PIN0
+ Set as output pin 0
+ 0
+ 0
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN1
+ Set as output pin 1
+ 1
+ 1
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN2
+ Set as output pin 2
+ 2
+ 2
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN3
+ Set as output pin 3
+ 3
+ 3
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN4
+ Set as output pin 4
+ 4
+ 4
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN5
+ Set as output pin 5
+ 5
+ 5
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN6
+ Set as output pin 6
+ 6
+ 6
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN7
+ Set as output pin 7
+ 7
+ 7
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN8
+ Set as output pin 8
+ 8
+ 8
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN9
+ Set as output pin 9
+ 9
+ 9
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN10
+ Set as output pin 10
+ 10
+ 10
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN11
+ Set as output pin 11
+ 11
+ 11
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN12
+ Set as output pin 12
+ 12
+ 12
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN13
+ Set as output pin 13
+ 13
+ 13
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN14
+ Set as output pin 14
+ 14
+ 14
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN15
+ Set as output pin 15
+ 15
+ 15
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN16
+ Set as output pin 16
+ 16
+ 16
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN17
+ Set as output pin 17
+ 17
+ 17
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN18
+ Set as output pin 18
+ 18
+ 18
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN19
+ Set as output pin 19
+ 19
+ 19
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN20
+ Set as output pin 20
+ 20
+ 20
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN21
+ Set as output pin 21
+ 21
+ 21
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN22
+ Set as output pin 22
+ 22
+ 22
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN23
+ Set as output pin 23
+ 23
+ 23
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN24
+ Set as output pin 24
+ 24
+ 24
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN25
+ Set as output pin 25
+ 25
+ 25
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN26
+ Set as output pin 26
+ 26
+ 26
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN27
+ Set as output pin 27
+ 27
+ 27
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN28
+ Set as output pin 28
+ 28
+ 28
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN29
+ Set as output pin 29
+ 29
+ 29
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN30
+ Set as output pin 30
+ 30
+ 30
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN31
+ Set as output pin 31
+ 31
+ 31
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Set
+ Write: writing a '1' sets pin to output; writing a '0' has no effect
+ 1
+
+
+
+
+
+
+ DIRCLR
+ DIR clear register
+ 0x51C
+ read-write
+ oneToClear
+
+
+ PIN0
+ Set as input pin 0
+ 0
+ 0
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN1
+ Set as input pin 1
+ 1
+ 1
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN2
+ Set as input pin 2
+ 2
+ 2
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN3
+ Set as input pin 3
+ 3
+ 3
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN4
+ Set as input pin 4
+ 4
+ 4
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN5
+ Set as input pin 5
+ 5
+ 5
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN6
+ Set as input pin 6
+ 6
+ 6
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN7
+ Set as input pin 7
+ 7
+ 7
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN8
+ Set as input pin 8
+ 8
+ 8
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN9
+ Set as input pin 9
+ 9
+ 9
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN10
+ Set as input pin 10
+ 10
+ 10
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN11
+ Set as input pin 11
+ 11
+ 11
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN12
+ Set as input pin 12
+ 12
+ 12
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN13
+ Set as input pin 13
+ 13
+ 13
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN14
+ Set as input pin 14
+ 14
+ 14
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN15
+ Set as input pin 15
+ 15
+ 15
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN16
+ Set as input pin 16
+ 16
+ 16
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN17
+ Set as input pin 17
+ 17
+ 17
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN18
+ Set as input pin 18
+ 18
+ 18
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN19
+ Set as input pin 19
+ 19
+ 19
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN20
+ Set as input pin 20
+ 20
+ 20
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN21
+ Set as input pin 21
+ 21
+ 21
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN22
+ Set as input pin 22
+ 22
+ 22
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN23
+ Set as input pin 23
+ 23
+ 23
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN24
+ Set as input pin 24
+ 24
+ 24
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN25
+ Set as input pin 25
+ 25
+ 25
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN26
+ Set as input pin 26
+ 26
+ 26
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN27
+ Set as input pin 27
+ 27
+ 27
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN28
+ Set as input pin 28
+ 28
+ 28
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN29
+ Set as input pin 29
+ 29
+ 29
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN30
+ Set as input pin 30
+ 30
+ 30
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+ PIN31
+ Set as input pin 31
+ 31
+ 31
+
+ read
+
+ Input
+ Read: pin set as input
+ 0
+
+
+ Output
+ Read: pin set as output
+ 1
+
+
+
+ write
+
+ Clear
+ Write: writing a '1' sets pin to input; writing a '0' has no effect
+ 1
+
+
+
+
+
+
+ LATCH
+ Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers
+ 0x520
+ read-write
+
+
+ PIN0
+ Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.
+ 0
+ 0
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN1
+ Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.
+ 1
+ 1
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN2
+ Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.
+ 2
+ 2
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN3
+ Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.
+ 3
+ 3
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN4
+ Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.
+ 4
+ 4
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN5
+ Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.
+ 5
+ 5
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN6
+ Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.
+ 6
+ 6
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN7
+ Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.
+ 7
+ 7
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN8
+ Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.
+ 8
+ 8
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN9
+ Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.
+ 9
+ 9
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN10
+ Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.
+ 10
+ 10
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN11
+ Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.
+ 11
+ 11
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN12
+ Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.
+ 12
+ 12
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN13
+ Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.
+ 13
+ 13
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN14
+ Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.
+ 14
+ 14
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN15
+ Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.
+ 15
+ 15
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN16
+ Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.
+ 16
+ 16
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN17
+ Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.
+ 17
+ 17
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN18
+ Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.
+ 18
+ 18
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN19
+ Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.
+ 19
+ 19
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN20
+ Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.
+ 20
+ 20
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN21
+ Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.
+ 21
+ 21
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN22
+ Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.
+ 22
+ 22
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN23
+ Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.
+ 23
+ 23
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN24
+ Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.
+ 24
+ 24
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN25
+ Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.
+ 25
+ 25
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN26
+ Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.
+ 26
+ 26
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN27
+ Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.
+ 27
+ 27
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN28
+ Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.
+ 28
+ 28
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN29
+ Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.
+ 29
+ 29
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN30
+ Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.
+ 30
+ 30
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+ PIN31
+ Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.
+ 31
+ 31
+
+
+ NotLatched
+ Criteria has not been met
+ 0
+
+
+ Latched
+ Criteria has been met
+ 1
+
+
+
+
+
+
+ DETECTMODE
+ Select between default DETECT signal behaviour and LDETECT mode
+ 0x524
+ read-write
+
+
+ DETECTMODE
+ Select between default DETECT signal behaviour and LDETECT mode
+ 0
+ 0
+
+
+ Default
+ DETECT directly connected to PIN DETECT signals
+ 0
+
+
+ LDETECT
+ Use the latched LDETECT behaviour
+ 1
+
+
+
+
+
+
+ 0x20
+ 0x4
+ PIN_CNF[%s]
+ Description collection: Configuration of GPIO pins
+ 0x700
+ read-write
+ 0x00000002
+
+
+ DIR
+ Pin direction. Same physical register as DIR register
+ 0
+ 0
+
+
+ Input
+ Configure pin as an input pin
+ 0
+
+
+ Output
+ Configure pin as an output pin
+ 1
+
+
+
+
+ INPUT
+ Connect or disconnect input buffer
+ 1
+ 1
+
+
+ Connect
+ Connect input buffer
+ 0
+
+
+ Disconnect
+ Disconnect input buffer
+ 1
+
+
+
+
+ PULL
+ Pull configuration
+ 2
+ 3
+
+
+ Disabled
+ No pull
+ 0
+
+
+ Pulldown
+ Pull down on pin
+ 1
+
+
+ Pullup
+ Pull up on pin
+ 3
+
+
+
+
+ DRIVE
+ Drive configuration
+ 8
+ 10
+
+
+ S0S1
+ Standard '0', standard '1'
+ 0
+
+
+ H0S1
+ High drive '0', standard '1'
+ 1
+
+
+ S0H1
+ Standard '0', high drive '1'
+ 2
+
+
+ H0H1
+ High drive '0', high 'drive '1''
+ 3
+
+
+ D0S1
+ Disconnect '0' standard '1' (normally used for wired-or connections)
+ 4
+
+
+ D0H1
+ Disconnect '0', high drive '1' (normally used for wired-or connections)
+ 5
+
+
+ S0D1
+ Standard '0'. disconnect '1' (normally used for wired-and connections)
+ 6
+
+
+ H0D1
+ High drive '0', disconnect '1' (normally used for wired-and connections)
+ 7
+
+
+
+
+ SENSE
+ Pin sensing mechanism
+ 16
+ 17
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ High
+ Sense for high level
+ 2
+
+
+ Low
+ Sense for low level
+ 3
+
+
+
+
+
+
+
+
+ P1
+ GPIO Port 2
+ 0x50000300
+ P0
+
+
+ RADIO
+ 2.4 GHz radio
+ 0x40001000
+
+ 0
+ 0x1000
+ registers
+
+
+ RADIO
+ 1
+
+ RADIO
+ 0x20
+
+
+ TASKS_TXEN
+ Enable RADIO in TX mode
+ 0x000
+ write-only
+
+
+ TASKS_TXEN
+ Enable RADIO in TX mode
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RXEN
+ Enable RADIO in RX mode
+ 0x004
+ write-only
+
+
+ TASKS_RXEN
+ Enable RADIO in RX mode
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_START
+ Start RADIO
+ 0x008
+ write-only
+
+
+ TASKS_START
+ Start RADIO
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop RADIO
+ 0x00C
+ write-only
+
+
+ TASKS_STOP
+ Stop RADIO
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_DISABLE
+ Disable RADIO
+ 0x010
+ write-only
+
+
+ TASKS_DISABLE
+ Disable RADIO
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RSSISTART
+ Start the RSSI and take one single sample of the receive signal strength
+ 0x014
+ write-only
+
+
+ TASKS_RSSISTART
+ Start the RSSI and take one single sample of the receive signal strength
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RSSISTOP
+ Stop the RSSI measurement
+ 0x018
+ write-only
+
+
+ TASKS_RSSISTOP
+ Stop the RSSI measurement
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_BCSTART
+ Start the bit counter
+ 0x01C
+ write-only
+
+
+ TASKS_BCSTART
+ Start the bit counter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_BCSTOP
+ Stop the bit counter
+ 0x020
+ write-only
+
+
+ TASKS_BCSTOP
+ Stop the bit counter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_EDSTART
+ Start the energy detect measurement used in IEEE 802.15.4 mode
+ 0x024
+ write-only
+
+
+ TASKS_EDSTART
+ Start the energy detect measurement used in IEEE 802.15.4 mode
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_EDSTOP
+ Stop the energy detect measurement
+ 0x028
+ write-only
+
+
+ TASKS_EDSTOP
+ Stop the energy detect measurement
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CCASTART
+ Start the clear channel assessment used in IEEE 802.15.4 mode
+ 0x02C
+ write-only
+
+
+ TASKS_CCASTART
+ Start the clear channel assessment used in IEEE 802.15.4 mode
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CCASTOP
+ Stop the clear channel assessment
+ 0x030
+ write-only
+
+
+ TASKS_CCASTOP
+ Stop the clear channel assessment
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_READY
+ RADIO has ramped up and is ready to be started
+ 0x100
+ read-write
+
+
+ EVENTS_READY
+ RADIO has ramped up and is ready to be started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ADDRESS
+ Address sent or received
+ 0x104
+ read-write
+
+
+ EVENTS_ADDRESS
+ Address sent or received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_PAYLOAD
+ Packet payload sent or received
+ 0x108
+ read-write
+
+
+ EVENTS_PAYLOAD
+ Packet payload sent or received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ Packet sent or received
+ 0x10C
+ read-write
+
+
+ EVENTS_END
+ Packet sent or received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DISABLED
+ RADIO has been disabled
+ 0x110
+ read-write
+
+
+ EVENTS_DISABLED
+ RADIO has been disabled
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DEVMATCH
+ A device address match occurred on the last received packet
+ 0x114
+ read-write
+
+
+ EVENTS_DEVMATCH
+ A device address match occurred on the last received packet
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DEVMISS
+ No device address match occurred on the last received packet
+ 0x118
+ read-write
+
+
+ EVENTS_DEVMISS
+ No device address match occurred on the last received packet
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RSSIEND
+ Sampling of receive signal strength complete
+ 0x11C
+ read-write
+
+
+ EVENTS_RSSIEND
+ Sampling of receive signal strength complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_BCMATCH
+ Bit counter reached bit count value
+ 0x128
+ read-write
+
+
+ EVENTS_BCMATCH
+ Bit counter reached bit count value
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CRCOK
+ Packet received with CRC ok
+ 0x130
+ read-write
+
+
+ EVENTS_CRCOK
+ Packet received with CRC ok
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CRCERROR
+ Packet received with CRC error
+ 0x134
+ read-write
+
+
+ EVENTS_CRCERROR
+ Packet received with CRC error
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_FRAMESTART
+ IEEE 802.15.4 length field received
+ 0x138
+ read-write
+
+
+ EVENTS_FRAMESTART
+ IEEE 802.15.4 length field received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_EDEND
+ Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register
+ 0x13C
+ read-write
+
+
+ EVENTS_EDEND
+ Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_EDSTOPPED
+ The sampling of energy detection has stopped
+ 0x140
+ read-write
+
+
+ EVENTS_EDSTOPPED
+ The sampling of energy detection has stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CCAIDLE
+ Wireless medium in idle - clear to send
+ 0x144
+ read-write
+
+
+ EVENTS_CCAIDLE
+ Wireless medium in idle - clear to send
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CCABUSY
+ Wireless medium busy - do not send
+ 0x148
+ read-write
+
+
+ EVENTS_CCABUSY
+ Wireless medium busy - do not send
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CCASTOPPED
+ The CCA has stopped
+ 0x14C
+ read-write
+
+
+ EVENTS_CCASTOPPED
+ The CCA has stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RATEBOOST
+ Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
+ 0x150
+ read-write
+
+
+ EVENTS_RATEBOOST
+ Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXREADY
+ RADIO has ramped up and is ready to be started TX path
+ 0x154
+ read-write
+
+
+ EVENTS_TXREADY
+ RADIO has ramped up and is ready to be started TX path
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXREADY
+ RADIO has ramped up and is ready to be started RX path
+ 0x158
+ read-write
+
+
+ EVENTS_RXREADY
+ RADIO has ramped up and is ready to be started RX path
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_MHRMATCH
+ MAC header match found
+ 0x15C
+ read-write
+
+
+ EVENTS_MHRMATCH
+ MAC header match found
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_PHYEND
+ Generated when last bit is sent on air
+ 0x16C
+ read-write
+
+
+ EVENTS_PHYEND
+ Generated when last bit is sent on air
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CTEPRESENT
+ CTE is present (early warning right after receiving CTEInfo byte)
+ 0x170
+ read-write
+
+
+ EVENTS_CTEPRESENT
+ CTE is present (early warning right after receiving CTEInfo byte)
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ READY_START
+ Shortcut between event READY and task START
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ END_DISABLE
+ Shortcut between event END and task DISABLE
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ DISABLED_TXEN
+ Shortcut between event DISABLED and task TXEN
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ DISABLED_RXEN
+ Shortcut between event DISABLED and task RXEN
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ ADDRESS_RSSISTART
+ Shortcut between event ADDRESS and task RSSISTART
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ END_START
+ Shortcut between event END and task START
+ 5
+ 5
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ ADDRESS_BCSTART
+ Shortcut between event ADDRESS and task BCSTART
+ 6
+ 6
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ DISABLED_RSSISTOP
+ Shortcut between event DISABLED and task RSSISTOP
+ 8
+ 8
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ RXREADY_CCASTART
+ Shortcut between event RXREADY and task CCASTART
+ 11
+ 11
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ CCAIDLE_TXEN
+ Shortcut between event CCAIDLE and task TXEN
+ 12
+ 12
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ CCABUSY_DISABLE
+ Shortcut between event CCABUSY and task DISABLE
+ 13
+ 13
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ FRAMESTART_BCSTART
+ Shortcut between event FRAMESTART and task BCSTART
+ 14
+ 14
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ READY_EDSTART
+ Shortcut between event READY and task EDSTART
+ 15
+ 15
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ EDEND_DISABLE
+ Shortcut between event EDEND and task DISABLE
+ 16
+ 16
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ CCAIDLE_STOP
+ Shortcut between event CCAIDLE and task STOP
+ 17
+ 17
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ TXREADY_START
+ Shortcut between event TXREADY and task START
+ 18
+ 18
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ RXREADY_START
+ Shortcut between event RXREADY and task START
+ 19
+ 19
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ PHYEND_DISABLE
+ Shortcut between event PHYEND and task DISABLE
+ 20
+ 20
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ PHYEND_START
+ Shortcut between event PHYEND and task START
+ 21
+ 21
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ READY
+ Write '1' to enable interrupt for event READY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ADDRESS
+ Write '1' to enable interrupt for event ADDRESS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PAYLOAD
+ Write '1' to enable interrupt for event PAYLOAD
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DISABLED
+ Write '1' to enable interrupt for event DISABLED
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DEVMATCH
+ Write '1' to enable interrupt for event DEVMATCH
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DEVMISS
+ Write '1' to enable interrupt for event DEVMISS
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RSSIEND
+ Write '1' to enable interrupt for event RSSIEND
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ BCMATCH
+ Write '1' to enable interrupt for event BCMATCH
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CRCOK
+ Write '1' to enable interrupt for event CRCOK
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CRCERROR
+ Write '1' to enable interrupt for event CRCERROR
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ FRAMESTART
+ Write '1' to enable interrupt for event FRAMESTART
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ EDEND
+ Write '1' to enable interrupt for event EDEND
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ EDSTOPPED
+ Write '1' to enable interrupt for event EDSTOPPED
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CCAIDLE
+ Write '1' to enable interrupt for event CCAIDLE
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CCABUSY
+ Write '1' to enable interrupt for event CCABUSY
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CCASTOPPED
+ Write '1' to enable interrupt for event CCASTOPPED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RATEBOOST
+ Write '1' to enable interrupt for event RATEBOOST
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXREADY
+ Write '1' to enable interrupt for event TXREADY
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXREADY
+ Write '1' to enable interrupt for event RXREADY
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ MHRMATCH
+ Write '1' to enable interrupt for event MHRMATCH
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PHYEND
+ Write '1' to enable interrupt for event PHYEND
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CTEPRESENT
+ Write '1' to enable interrupt for event CTEPRESENT
+ 28
+ 28
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ READY
+ Write '1' to disable interrupt for event READY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ADDRESS
+ Write '1' to disable interrupt for event ADDRESS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PAYLOAD
+ Write '1' to disable interrupt for event PAYLOAD
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DISABLED
+ Write '1' to disable interrupt for event DISABLED
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DEVMATCH
+ Write '1' to disable interrupt for event DEVMATCH
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DEVMISS
+ Write '1' to disable interrupt for event DEVMISS
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RSSIEND
+ Write '1' to disable interrupt for event RSSIEND
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ BCMATCH
+ Write '1' to disable interrupt for event BCMATCH
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CRCOK
+ Write '1' to disable interrupt for event CRCOK
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CRCERROR
+ Write '1' to disable interrupt for event CRCERROR
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ FRAMESTART
+ Write '1' to disable interrupt for event FRAMESTART
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ EDEND
+ Write '1' to disable interrupt for event EDEND
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ EDSTOPPED
+ Write '1' to disable interrupt for event EDSTOPPED
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CCAIDLE
+ Write '1' to disable interrupt for event CCAIDLE
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CCABUSY
+ Write '1' to disable interrupt for event CCABUSY
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CCASTOPPED
+ Write '1' to disable interrupt for event CCASTOPPED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RATEBOOST
+ Write '1' to disable interrupt for event RATEBOOST
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXREADY
+ Write '1' to disable interrupt for event TXREADY
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXREADY
+ Write '1' to disable interrupt for event RXREADY
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ MHRMATCH
+ Write '1' to disable interrupt for event MHRMATCH
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PHYEND
+ Write '1' to disable interrupt for event PHYEND
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CTEPRESENT
+ Write '1' to disable interrupt for event CTEPRESENT
+ 28
+ 28
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ CRCSTATUS
+ CRC status
+ 0x400
+ read-only
+
+
+ CRCSTATUS
+ CRC status of packet received
+ 0
+ 0
+
+
+ CRCError
+ Packet received with CRC error
+ 0
+
+
+ CRCOk
+ Packet received with CRC ok
+ 1
+
+
+
+
+
+
+ RXMATCH
+ Received address
+ 0x408
+ read-only
+
+
+ RXMATCH
+ Received address
+ 0
+ 2
+
+
+
+
+ RXCRC
+ CRC field of previously received packet
+ 0x40C
+ read-only
+
+
+ RXCRC
+ CRC field of previously received packet
+ 0
+ 23
+
+
+
+
+ DAI
+ Device address match index
+ 0x410
+ read-only
+
+
+ DAI
+ Device address match index
+ 0
+ 2
+
+
+
+
+ PDUSTAT
+ Payload status
+ 0x414
+ read-only
+
+
+ PDUSTAT
+ Status on payload length vs. PCNF1.MAXLEN
+ 0
+ 0
+
+
+ LessThan
+ Payload less than PCNF1.MAXLEN
+ 0
+
+
+ GreaterThan
+ Payload greater than PCNF1.MAXLEN
+ 1
+
+
+
+
+ CISTAT
+ Status on what rate packet is received with in Long Range
+ 1
+ 2
+
+
+ LR125kbit
+ Frame is received at 125 kbps
+ 0
+
+
+ LR500kbit
+ Frame is received at 500 kbps
+ 1
+
+
+
+
+
+
+ CTESTATUS
+ CTEInfo parsed from received packet
+ 0x44C
+ read-only
+
+
+ CTETIME
+ CTETime parsed from packet
+ 0
+ 4
+
+
+ RFU
+ RFU parsed from packet
+ 5
+ 5
+
+
+ CTETYPE
+ CTEType parsed from packet
+ 6
+ 7
+
+
+
+
+ DFESTATUS
+ DFE status information
+ 0x458
+ read-only
+
+
+ SWITCHINGSTATE
+ Internal state of switching state machine
+ 0
+ 2
+
+
+ Idle
+ Switching state Idle
+ 0
+
+
+ Offset
+ Switching state Offset
+ 1
+
+
+ Guard
+ Switching state Guard
+ 2
+
+
+ Ref
+ Switching state Ref
+ 3
+
+
+ Switching
+ Switching state Switching
+ 4
+
+
+ Ending
+ Switching state Ending
+ 5
+
+
+
+
+ SAMPLINGSTATE
+ Internal state of sampling state machine
+ 4
+ 4
+
+
+ Idle
+ Sampling state Idle
+ 0
+
+
+ Sampling
+ Sampling state Sampling
+ 1
+
+
+
+
+
+
+ PACKETPTR
+ Packet pointer
+ 0x504
+ read-write
+ 0x00000000
+
+
+ PACKETPTR
+ Packet pointer
+ 0
+ 31
+
+
+
+
+ FREQUENCY
+ Frequency
+ 0x508
+ read-write
+ 0x00000002
+
+
+ FREQUENCY
+ Radio channel frequency
+ 0
+ 6
+
+
+ MAP
+ Channel map selection.
+ 8
+ 8
+
+
+ Default
+ Channel map between 2400 MHZ .. 2500 MHz
+ 0
+
+
+ Low
+ Channel map between 2360 MHZ .. 2460 MHz
+ 1
+
+
+
+
+
+
+ TXPOWER
+ Output power
+ 0x50C
+ read-write
+
+
+ TXPOWER
+ RADIO output power
+ 0
+ 7
+
+
+ Pos8dBm
+ +8 dBm
+ 0x8
+
+
+ Pos7dBm
+ +7 dBm
+ 0x7
+
+
+ Pos6dBm
+ +6 dBm
+ 0x6
+
+
+ Pos5dBm
+ +5 dBm
+ 0x5
+
+
+ Pos4dBm
+ +4 dBm
+ 0x4
+
+
+ Pos3dBm
+ +3 dBm
+ 0x3
+
+
+ Pos2dBm
+ +2 dBm
+ 0x2
+
+
+ 0dBm
+ 0 dBm
+ 0x0
+
+
+ Neg4dBm
+ -4 dBm
+ 0xFC
+
+
+ Neg8dBm
+ -8 dBm
+ 0xF8
+
+
+ Neg12dBm
+ -12 dBm
+ 0xF4
+
+
+ Neg16dBm
+ -16 dBm
+ 0xF0
+
+
+ Neg20dBm
+ -20 dBm
+ 0xEC
+
+
+ Neg30dBm
+ Deprecated enumerator - -40 dBm
+ 0xE2
+
+
+ Neg40dBm
+ -40 dBm
+ 0xD8
+
+
+
+
+
+
+ MODE
+ Data rate and modulation
+ 0x510
+ read-write
+
+
+ MODE
+ Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation.
+ 0
+ 3
+
+
+ Nrf_1Mbit
+ 1 Mbps Nordic proprietary radio mode
+ 0
+
+
+ Nrf_2Mbit
+ 2 Mbps Nordic proprietary radio mode
+ 1
+
+
+ Ble_1Mbit
+ 1 Mbps BLE
+ 3
+
+
+ Ble_2Mbit
+ 2 Mbps BLE
+ 4
+
+
+ Ble_LR125Kbit
+ Long range 125 kbps TX, 125 kbps and 500 kbps RX
+ 5
+
+
+ Ble_LR500Kbit
+ Long range 500 kbps TX, 125 kbps and 500 kbps RX
+ 6
+
+
+ Ieee802154_250Kbit
+ IEEE 802.15.4-2006 250 kbps
+ 15
+
+
+
+
+
+
+ PCNF0
+ Packet configuration register 0
+ 0x514
+ read-write
+
+
+ LFLEN
+ Length on air of LENGTH field in number of bits.
+ 0
+ 3
+
+
+ S0LEN
+ Length on air of S0 field in number of bytes.
+ 8
+ 8
+
+
+ S1LEN
+ Length on air of S1 field in number of bits.
+ 16
+ 19
+
+
+ S1INCL
+ Include or exclude S1 field in RAM
+ 20
+ 20
+
+
+ Automatic
+ Include S1 field in RAM only if S1LEN > 0
+ 0
+
+
+ Include
+ Always include S1 field in RAM independent of S1LEN
+ 1
+
+
+
+
+ CILEN
+ Length of code indicator - long range
+ 22
+ 23
+
+
+ PLEN
+ Length of preamble on air. Decision point: TASKS_START task
+ 24
+ 25
+
+
+ 8bit
+ 8-bit preamble
+ 0
+
+
+ 16bit
+ 16-bit preamble
+ 1
+
+
+ 32bitZero
+ 32-bit zero preamble - used for IEEE 802.15.4
+ 2
+
+
+ LongRange
+ Preamble - used for BLE long range
+ 3
+
+
+
+
+ CRCINC
+ Indicates if LENGTH field contains CRC or not
+ 26
+ 26
+
+
+ Exclude
+ LENGTH does not contain CRC
+ 0
+
+
+ Include
+ LENGTH includes CRC
+ 1
+
+
+
+
+ TERMLEN
+ Length of TERM field in Long Range operation
+ 29
+ 30
+
+
+
+
+ PCNF1
+ Packet configuration register 1
+ 0x518
+ read-write
+
+
+ MAXLEN
+ Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
+ 0
+ 7
+
+
+ STATLEN
+ Static length in number of bytes
+ 8
+ 15
+
+
+ BALEN
+ Base address length in number of bytes
+ 16
+ 18
+
+
+ ENDIAN
+ On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields.
+ 24
+ 24
+
+
+ Little
+ Least significant bit on air first
+ 0
+
+
+ Big
+ Most significant bit on air first
+ 1
+
+
+
+
+ WHITEEN
+ Enable or disable packet whitening
+ 25
+ 25
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ BASE0
+ Base address 0
+ 0x51C
+ read-write
+
+
+ BASE0
+ Base address 0
+ 0
+ 31
+
+
+
+
+ BASE1
+ Base address 1
+ 0x520
+ read-write
+
+
+ BASE1
+ Base address 1
+ 0
+ 31
+
+
+
+
+ PREFIX0
+ Prefixes bytes for logical addresses 0-3
+ 0x524
+ read-write
+
+
+ AP0
+ Address prefix 0.
+ 0
+ 7
+
+
+ AP1
+ Address prefix 1.
+ 8
+ 15
+
+
+ AP2
+ Address prefix 2.
+ 16
+ 23
+
+
+ AP3
+ Address prefix 3.
+ 24
+ 31
+
+
+
+
+ PREFIX1
+ Prefixes bytes for logical addresses 4-7
+ 0x528
+ read-write
+
+
+ AP4
+ Address prefix 4.
+ 0
+ 7
+
+
+ AP5
+ Address prefix 5.
+ 8
+ 15
+
+
+ AP6
+ Address prefix 6.
+ 16
+ 23
+
+
+ AP7
+ Address prefix 7.
+ 24
+ 31
+
+
+
+
+ TXADDRESS
+ Transmit address select
+ 0x52C
+ read-write
+
+
+ TXADDRESS
+ Transmit address select
+ 0
+ 2
+
+
+
+
+ RXADDRESSES
+ Receive address select
+ 0x530
+ read-write
+
+
+ ADDR0
+ Enable or disable reception on logical address 0.
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR1
+ Enable or disable reception on logical address 1.
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR2
+ Enable or disable reception on logical address 2.
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR3
+ Enable or disable reception on logical address 3.
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR4
+ Enable or disable reception on logical address 4.
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR5
+ Enable or disable reception on logical address 5.
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR6
+ Enable or disable reception on logical address 6.
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ADDR7
+ Enable or disable reception on logical address 7.
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ CRCCNF
+ CRC configuration
+ 0x534
+ read-write
+
+
+ LEN
+ CRC length in number of bytes.
+ 0
+ 1
+
+
+ Disabled
+ CRC length is zero and CRC calculation is disabled
+ 0
+
+
+ One
+ CRC length is one byte and CRC calculation is enabled
+ 1
+
+
+ Two
+ CRC length is two bytes and CRC calculation is enabled
+ 2
+
+
+ Three
+ CRC length is three bytes and CRC calculation is enabled
+ 3
+
+
+
+
+ SKIPADDR
+ Include or exclude packet address field out of CRC calculation.
+ 8
+ 9
+
+
+ Include
+ CRC calculation includes address field
+ 0
+
+
+ Skip
+ CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.
+ 1
+
+
+ Ieee802154
+ CRC calculation as per 802.15.4 standard. Starting at first byte after length field.
+ 2
+
+
+
+
+
+
+ CRCPOLY
+ CRC polynomial
+ 0x538
+ read-write
+ 0x00000000
+
+
+ CRCPOLY
+ CRC polynomial
+ 0
+ 23
+
+
+
+
+ CRCINIT
+ CRC initial value
+ 0x53C
+ read-write
+
+
+ CRCINIT
+ CRC initial value
+ 0
+ 23
+
+
+
+
+ TIFS
+ Interframe spacing in us
+ 0x544
+ read-write
+
+
+ TIFS
+ Interframe spacing in us
+ 0
+ 9
+
+
+
+
+ RSSISAMPLE
+ RSSI sample
+ 0x548
+ read-only
+
+
+ RSSISAMPLE
+ RSSI sample
+ 0
+ 6
+
+
+
+
+ STATE
+ Current radio state
+ 0x550
+ read-only
+
+
+ STATE
+ Current radio state
+ 0
+ 3
+
+
+ Disabled
+ RADIO is in the Disabled state
+ 0
+
+
+ RxRu
+ RADIO is in the RXRU state
+ 1
+
+
+ RxIdle
+ RADIO is in the RXIDLE state
+ 2
+
+
+ Rx
+ RADIO is in the RX state
+ 3
+
+
+ RxDisable
+ RADIO is in the RXDISABLED state
+ 4
+
+
+ TxRu
+ RADIO is in the TXRU state
+ 9
+
+
+ TxIdle
+ RADIO is in the TXIDLE state
+ 10
+
+
+ Tx
+ RADIO is in the TX state
+ 11
+
+
+ TxDisable
+ RADIO is in the TXDISABLED state
+ 12
+
+
+
+
+
+
+ DATAWHITEIV
+ Data whitening initial value
+ 0x554
+ read-write
+ 0x00000040
+
+
+ DATAWHITEIV
+ Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.
+ 0
+ 6
+
+
+
+
+ BCC
+ Bit counter compare
+ 0x560
+ read-write
+
+
+ BCC
+ Bit counter compare
+ 0
+ 31
+
+
+
+
+ 0x8
+ 0x4
+ DAB[%s]
+ Description collection: Device address base segment n
+ 0x600
+ read-write
+
+
+ DAB
+ Device address base segment n
+ 0
+ 31
+
+
+
+
+ 0x8
+ 0x4
+ DAP[%s]
+ Description collection: Device address prefix n
+ 0x620
+ read-write
+
+
+ DAP
+ Device address prefix n
+ 0
+ 15
+
+
+
+
+ DACNF
+ Device address match configuration
+ 0x640
+ read-write
+
+
+ ENA0
+ Enable or disable device address matching using device address 0
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA1
+ Enable or disable device address matching using device address 1
+ 1
+ 1
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA2
+ Enable or disable device address matching using device address 2
+ 2
+ 2
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA3
+ Enable or disable device address matching using device address 3
+ 3
+ 3
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA4
+ Enable or disable device address matching using device address 4
+ 4
+ 4
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA5
+ Enable or disable device address matching using device address 5
+ 5
+ 5
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA6
+ Enable or disable device address matching using device address 6
+ 6
+ 6
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ENA7
+ Enable or disable device address matching using device address 7
+ 7
+ 7
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ TXADD0
+ TxAdd for device address 0
+ 8
+ 8
+
+
+ TXADD1
+ TxAdd for device address 1
+ 9
+ 9
+
+
+ TXADD2
+ TxAdd for device address 2
+ 10
+ 10
+
+
+ TXADD3
+ TxAdd for device address 3
+ 11
+ 11
+
+
+ TXADD4
+ TxAdd for device address 4
+ 12
+ 12
+
+
+ TXADD5
+ TxAdd for device address 5
+ 13
+ 13
+
+
+ TXADD6
+ TxAdd for device address 6
+ 14
+ 14
+
+
+ TXADD7
+ TxAdd for device address 7
+ 15
+ 15
+
+
+
+
+ MHRMATCHCONF
+ Search pattern configuration
+ 0x644
+ read-write
+
+
+ MHRMATCHCONF
+ Search pattern configuration
+ 0
+ 31
+
+
+
+
+ MHRMATCHMAS
+ Pattern mask
+ 0x648
+ read-write
+
+
+ MHRMATCHMAS
+ Pattern mask
+ 0
+ 31
+
+
+
+
+ MODECNF0
+ Radio mode configuration register 0
+ 0x650
+ read-write
+ 0x00000200
+
+
+ RU
+ Radio ramp-up time
+ 0
+ 0
+
+
+ Default
+ Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51
+ 0
+
+
+ Fast
+ Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information
+ 1
+
+
+
+
+ DTX
+ Default TX value
+ 8
+ 9
+
+
+ B1
+ Transmit '1'
+ 0
+
+
+ B0
+ Transmit '0'
+ 1
+
+
+ Center
+ Transmit center frequency
+ 2
+
+
+
+
+
+
+ SFD
+ IEEE 802.15.4 start of frame delimiter
+ 0x660
+ read-write
+ 0x000000A7
+
+
+ SFD
+ IEEE 802.15.4 start of frame delimiter
+ 0
+ 7
+
+
+
+
+ EDCNT
+ IEEE 802.15.4 energy detect loop count
+ 0x664
+ read-write
+ 0x00000000
+
+
+ EDCNT
+ IEEE 802.15.4 energy detect loop count
+ 0
+ 20
+
+
+
+
+ EDSAMPLE
+ IEEE 802.15.4 energy detect level
+ 0x668
+ read-write
+ 0x00000000
+
+
+ EDLVL
+ IEEE 802.15.4 energy detect level
+ 0
+ 7
+
+
+
+
+ CCACTRL
+ IEEE 802.15.4 clear channel assessment control
+ 0x66C
+ read-write
+ 0x052D0000
+
+
+ CCAMODE
+ CCA mode of operation
+ 0
+ 2
+
+
+ EdMode
+ Energy above threshold
+ 0
+
+
+ CarrierMode
+ Carrier seen
+ 1
+
+
+ CarrierAndEdMode
+ Energy above threshold AND carrier seen
+ 2
+
+
+ CarrierOrEdMode
+ Energy above threshold OR carrier seen
+ 3
+
+
+ EdModeTest1
+ Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging.
+ 4
+
+
+
+
+ CCAEDTHRES
+ CCA energy busy threshold. Used in all the CCA modes except CarrierMode.
+ 8
+ 15
+
+
+ CCACORRTHRES
+ CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode.
+ 16
+ 23
+
+
+ CCACORRCNT
+ Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled.
+ 24
+ 31
+
+
+
+
+ DFEMODE
+ Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)
+ 0x900
+ read-write
+ 0x00000000
+
+
+ DFEOPMODE
+ Direction finding operation mode
+ 0
+ 1
+
+
+ Disabled
+ Direction finding mode disabled
+ 0
+
+
+ AoD
+ Direction finding mode set to AoD
+ 2
+
+
+ AoA
+ Direction finding mode set to AoA
+ 3
+
+
+
+
+
+
+ CTEINLINECONF
+ Configuration for CTE inline mode
+ 0x904
+ read-write
+ 0x00002800
+
+
+ CTEINLINECTRLEN
+ Enable parsing of CTEInfo from received packet in BLE modes
+ 0
+ 0
+
+
+ Enabled
+ Parsing of CTEInfo is enabled
+ 1
+
+
+ Disabled
+ Parsing of CTEInfo is disabled
+ 0
+
+
+
+
+ CTEINFOINS1
+ CTEInfo is S1 byte or not
+ 3
+ 3
+
+
+ InS1
+ CTEInfo is in S1 byte (data PDU)
+ 1
+
+
+ NotInS1
+ CTEInfo is NOT in S1 byte (advertising PDU)
+ 0
+
+
+
+
+ CTEERRORHANDLING
+ Sampling/switching if CRC is not OK
+ 4
+ 4
+
+
+ Yes
+ Sampling and antenna switching also when CRC is not OK
+ 1
+
+
+ No
+ No sampling and antenna switching when CRC is not OK
+ 0
+
+
+
+
+ CTETIMEVALIDRANGE
+ Max range of CTETime
+ 6
+ 7
+
+
+ 20
+ 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20
+ 0
+
+
+ 31
+ 31 in 8us unit
+ 1
+
+
+ 63
+ 63 in 8us unit
+ 2
+
+
+
+
+ CTEINLINERXMODE1US
+ Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set
+ 10
+ 12
+
+
+ 4us
+ 4us
+ 1
+
+
+ 2us
+ 2us
+ 2
+
+
+ 1us
+ 1us
+ 3
+
+
+ 500ns
+ 0.5us
+ 4
+
+
+ 250ns
+ 0.25us
+ 5
+
+
+ 125ns
+ 0.125us
+ 6
+
+
+
+
+ CTEINLINERXMODE2US
+ Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set
+ 13
+ 15
+
+
+ 4us
+ 4us
+ 1
+
+
+ 2us
+ 2us
+ 2
+
+
+ 1us
+ 1us
+ 3
+
+
+ 500ns
+ 0.5us
+ 4
+
+
+ 250ns
+ 0.25us
+ 5
+
+
+ 125ns
+ 0.125us
+ 6
+
+
+
+
+ S0CONF
+ S0 bit pattern to match
+ 16
+ 23
+
+
+ S0MASK
+ S0 bit mask to set which bit to match
+ 24
+ 31
+
+
+
+
+ DFECTRL1
+ Various configuration for Direction finding
+ 0x910
+ read-write
+ 0x00023282
+
+
+ NUMBEROF8US
+ Length of the AoA/AoD procedure in number of 8 us units
+ 0
+ 5
+
+
+ DFEINEXTENSION
+ Add CTE extension and do antenna switching/sampling in this extension
+ 7
+ 7
+
+
+ CRC
+ AoA/AoD procedure triggered at end of CRC
+ 1
+
+
+ Payload
+ Antenna switching/sampling is done in the packet payload
+ 0
+
+
+
+
+ TSWITCHSPACING
+ Interval between every time the antenna is changed in the SWITCHING state
+ 8
+ 10
+
+
+ 4us
+ 4us
+ 1
+
+
+ 2us
+ 2us
+ 2
+
+
+ 1us
+ 1us
+ 3
+
+
+
+
+ TSAMPLESPACINGREF
+ Interval between samples in the REFERENCE period
+ 12
+ 14
+
+
+ 4us
+ 4us
+ 1
+
+
+ 2us
+ 2us
+ 2
+
+
+ 1us
+ 1us
+ 3
+
+
+ 500ns
+ 0.5us
+ 4
+
+
+ 250ns
+ 0.25us
+ 5
+
+
+ 125ns
+ 0.125us
+ 6
+
+
+
+
+ SAMPLETYPE
+ Whether to sample I/Q or magnitude/phase
+ 15
+ 15
+
+
+ IQ
+ Complex samples in I and Q
+ 0
+
+
+ MagPhase
+ Complex samples as magnitude and phase
+ 1
+
+
+
+
+ TSAMPLESPACING
+ Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0
+ 16
+ 18
+
+
+ 4us
+ 4us
+ 1
+
+
+ 2us
+ 2us
+ 2
+
+
+ 1us
+ 1us
+ 3
+
+
+ 500ns
+ 0.5us
+ 4
+
+
+ 250ns
+ 0.25us
+ 5
+
+
+ 125ns
+ 0.125us
+ 6
+
+
+
+
+ REPEATPATTERN
+ Repeat every antenna pattern N times.
+ 20
+ 23
+
+
+ NoRepeat
+ Do not repeat (1 time in total)
+ 0
+
+
+
+
+ AGCBACKOFFGAIN
+ Gain will be lowered by the specified number of gain steps at the start of CTE
+ 24
+ 27
+
+
+
+
+ DFECTRL2
+ Start offset for Direction finding
+ 0x914
+ read-write
+ 0x00000000
+
+
+ TSWITCHOFFSET
+ Signed value offset after the end of the CRC before starting switching in number of 16M cycles
+ 0
+ 12
+
+
+ TSAMPLEOFFSET
+ Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start
+ 16
+ 27
+
+
+
+
+ SWITCHPATTERN
+ GPIO patterns to be used for each antenna
+ 0x928
+ read-write
+ 0x00000000
+
+
+ SWITCHPATTERN
+ Fill array of GPIO patterns for antenna control
+ 0
+ 7
+
+
+
+
+ CLEARPATTERN
+ Clear the GPIO pattern array for antenna control
+ 0x92C
+ read-write
+
+
+ CLEARPATTERN
+ Clears GPIO pattern array for antenna control
+ 0
+ 0
+ oneToClear
+
+
+ Clear
+ Clear the GPIO pattern
+ 1
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ RADIO_PSEL
+ read-write
+ 0x930
+
+ 0x8
+ 0x4
+ DFEGPIO[%s]
+ Description collection: Pin select for DFE pin n
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ DFEPACKET
+ DFE packet EasyDMA channel
+ RADIO_DFEPACKET
+ read-write
+ 0x950
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+ 0x00000000
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of buffer words to transfer
+ 0x004
+ read-write
+ 0x00001000
+
+
+ MAXCNT
+ Maximum number of buffer words to transfer
+ 0
+ 13
+
+
+
+
+ AMOUNT
+ Number of samples transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of samples transferred in the last transaction
+ 0
+ 15
+
+
+
+
+
+ POWER
+ Peripheral power control
+ 0xFFC
+ read-write
+ 0x00000001
+
+
+ POWER
+ Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.
+ 0
+ 0
+
+
+ Disabled
+ Peripheral is powered off
+ 0
+
+
+ Enabled
+ Peripheral is powered on
+ 1
+
+
+
+
+
+
+
+
+ UART0
+ Universal Asynchronous Receiver/Transmitter
+ 0x40002000
+ UART
+
+ 0
+ 0x1000
+ registers
+
+
+ UARTE0_UART0
+ 2
+
+ UART
+ 0x20
+
+
+ TASKS_STARTRX
+ Start UART receiver
+ 0x000
+ write-only
+
+
+ TASKS_STARTRX
+ Start UART receiver
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOPRX
+ Stop UART receiver
+ 0x004
+ write-only
+
+
+ TASKS_STOPRX
+ Stop UART receiver
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTTX
+ Start UART transmitter
+ 0x008
+ write-only
+
+
+ TASKS_STARTTX
+ Start UART transmitter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOPTX
+ Stop UART transmitter
+ 0x00C
+ write-only
+
+
+ TASKS_STOPTX
+ Stop UART transmitter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SUSPEND
+ Suspend UART
+ 0x01C
+ write-only
+
+
+ TASKS_SUSPEND
+ Suspend UART
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_CTS
+ CTS is activated (set low). Clear To Send.
+ 0x100
+ read-write
+
+
+ EVENTS_CTS
+ CTS is activated (set low). Clear To Send.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_NCTS
+ CTS is deactivated (set high). Not Clear To Send.
+ 0x104
+ read-write
+
+
+ EVENTS_NCTS
+ CTS is deactivated (set high). Not Clear To Send.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXDRDY
+ Data received in RXD
+ 0x108
+ read-write
+
+
+ EVENTS_RXDRDY
+ Data received in RXD
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXDRDY
+ Data sent from TXD
+ 0x11C
+ read-write
+
+
+ EVENTS_TXDRDY
+ Data sent from TXD
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ Error detected
+ 0x124
+ read-write
+
+
+ EVENTS_ERROR
+ Error detected
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXTO
+ Receiver timeout
+ 0x144
+ read-write
+
+
+ EVENTS_RXTO
+ Receiver timeout
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ CTS_STARTRX
+ Shortcut between event CTS and task STARTRX
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ NCTS_STOPRX
+ Shortcut between event NCTS and task STOPRX
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ CTS
+ Write '1' to enable interrupt for event CTS
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ NCTS
+ Write '1' to enable interrupt for event NCTS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXDRDY
+ Write '1' to enable interrupt for event RXDRDY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXDRDY
+ Write '1' to enable interrupt for event TXDRDY
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXTO
+ Write '1' to enable interrupt for event RXTO
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ CTS
+ Write '1' to disable interrupt for event CTS
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ NCTS
+ Write '1' to disable interrupt for event NCTS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXDRDY
+ Write '1' to disable interrupt for event RXDRDY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXDRDY
+ Write '1' to disable interrupt for event TXDRDY
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXTO
+ Write '1' to disable interrupt for event RXTO
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSRC
+ Error source
+ 0x480
+ read-write
+ oneToClear
+
+
+ OVERRUN
+ Overrun error
+ 0
+ 0
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ PARITY
+ Parity error
+ 1
+ 1
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ FRAMING
+ Framing error occurred
+ 2
+ 2
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ BREAK
+ Break condition
+ 3
+ 3
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable UART
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable UART
+ 0
+ 3
+
+
+ Disabled
+ Disable UART
+ 0
+
+
+ Enabled
+ Enable UART
+ 4
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ UART_PSEL
+ read-write
+ 0x508
+
+ RTS
+ Pin select for RTS
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ TXD
+ Pin select for TXD
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ CTS
+ Pin select for CTS
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ RXD
+ Pin select for RXD
+ 0x00C
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ RXD
+ RXD register
+ 0x518
+ read-only
+ modifyExternal
+
+
+ RXD
+ RX data received in previous transfers, double buffered
+ 0
+ 7
+
+
+
+
+ TXD
+ TXD register
+ 0x51C
+ write-only
+
+
+ TXD
+ TX data to be transferred
+ 0
+ 7
+
+
+
+
+ BAUDRATE
+ Baud rate. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ BAUDRATE
+ Baud rate
+ 0
+ 31
+
+
+ Baud1200
+ 1200 baud (actual rate: 1205)
+ 0x0004F000
+
+
+ Baud2400
+ 2400 baud (actual rate: 2396)
+ 0x0009D000
+
+
+ Baud4800
+ 4800 baud (actual rate: 4808)
+ 0x0013B000
+
+
+ Baud9600
+ 9600 baud (actual rate: 9598)
+ 0x00275000
+
+
+ Baud14400
+ 14400 baud (actual rate: 14414)
+ 0x003B0000
+
+
+ Baud19200
+ 19200 baud (actual rate: 19208)
+ 0x004EA000
+
+
+ Baud28800
+ 28800 baud (actual rate: 28829)
+ 0x0075F000
+
+
+ Baud31250
+ 31250 baud
+ 0x00800000
+
+
+ Baud38400
+ 38400 baud (actual rate: 38462)
+ 0x009D5000
+
+
+ Baud56000
+ 56000 baud (actual rate: 55944)
+ 0x00E50000
+
+
+ Baud57600
+ 57600 baud (actual rate: 57762)
+ 0x00EBF000
+
+
+ Baud76800
+ 76800 baud (actual rate: 76923)
+ 0x013A9000
+
+
+ Baud115200
+ 115200 baud (actual rate: 115942)
+ 0x01D7E000
+
+
+ Baud230400
+ 230400 baud (actual rate: 231884)
+ 0x03AFB000
+
+
+ Baud250000
+ 250000 baud
+ 0x04000000
+
+
+ Baud460800
+ 460800 baud (actual rate: 470588)
+ 0x075F7000
+
+
+ Baud921600
+ 921600 baud (actual rate: 941176)
+ 0x0EBED000
+
+
+ Baud1M
+ 1Mega baud
+ 0x10000000
+
+
+
+
+
+
+ CONFIG
+ Configuration of parity and hardware flow control
+ 0x56C
+ read-write
+
+
+ HWFC
+ Hardware flow control
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ PARITY
+ Parity
+ 1
+ 3
+
+
+ Excluded
+ Exclude parity bit
+ 0x0
+
+
+ Included
+ Include parity bit
+ 0x7
+
+
+
+
+ STOP
+ Stop bits
+ 4
+ 4
+
+
+ One
+ One stop bit
+ 0
+
+
+ Two
+ Two stop bits
+ 1
+
+
+
+
+ PARITYTYPE
+ Even or odd parity type
+ 8
+ 8
+
+
+ Even
+ Even parity
+ 0
+
+
+ Odd
+ Odd parity
+ 1
+
+
+
+
+
+
+
+
+ UARTE0
+ UART with EasyDMA 0
+ 0x40002000
+ UART0
+ UARTE
+
+ 0
+ 0x1000
+ registers
+
+
+ UARTE0_UART0
+ 2
+
+ UARTE
+ 0x20
+
+
+ TASKS_STARTRX
+ Start UART receiver
+ 0x000
+ write-only
+
+
+ TASKS_STARTRX
+ Start UART receiver
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOPRX
+ Stop UART receiver
+ 0x004
+ write-only
+
+
+ TASKS_STOPRX
+ Stop UART receiver
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTTX
+ Start UART transmitter
+ 0x008
+ write-only
+
+
+ TASKS_STARTTX
+ Start UART transmitter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOPTX
+ Stop UART transmitter
+ 0x00C
+ write-only
+
+
+ TASKS_STOPTX
+ Stop UART transmitter
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_FLUSHRX
+ Flush RX FIFO into RX buffer
+ 0x02C
+ write-only
+
+
+ TASKS_FLUSHRX
+ Flush RX FIFO into RX buffer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_CTS
+ CTS is activated (set low). Clear To Send.
+ 0x100
+ read-write
+
+
+ EVENTS_CTS
+ CTS is activated (set low). Clear To Send.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_NCTS
+ CTS is deactivated (set high). Not Clear To Send.
+ 0x104
+ read-write
+
+
+ EVENTS_NCTS
+ CTS is deactivated (set high). Not Clear To Send.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXDRDY
+ Data received in RXD (but potentially not yet transferred to Data RAM)
+ 0x108
+ read-write
+
+
+ EVENTS_RXDRDY
+ Data received in RXD (but potentially not yet transferred to Data RAM)
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDRX
+ Receive buffer is filled up
+ 0x110
+ read-write
+
+
+ EVENTS_ENDRX
+ Receive buffer is filled up
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXDRDY
+ Data sent from TXD
+ 0x11C
+ read-write
+
+
+ EVENTS_TXDRDY
+ Data sent from TXD
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDTX
+ Last TX byte transmitted
+ 0x120
+ read-write
+
+
+ EVENTS_ENDTX
+ Last TX byte transmitted
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ Error detected
+ 0x124
+ read-write
+
+
+ EVENTS_ERROR
+ Error detected
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXTO
+ Receiver timeout
+ 0x144
+ read-write
+
+
+ EVENTS_RXTO
+ Receiver timeout
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXSTARTED
+ UART receiver has started
+ 0x14C
+ read-write
+
+
+ EVENTS_RXSTARTED
+ UART receiver has started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXSTARTED
+ UART transmitter has started
+ 0x150
+ read-write
+
+
+ EVENTS_TXSTARTED
+ UART transmitter has started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXSTOPPED
+ Transmitter stopped
+ 0x158
+ read-write
+
+
+ EVENTS_TXSTOPPED
+ Transmitter stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ ENDRX_STARTRX
+ Shortcut between event ENDRX and task STARTRX
+ 5
+ 5
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ ENDRX_STOPRX
+ Shortcut between event ENDRX and task STOPRX
+ 6
+ 6
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ CTS
+ Enable or disable interrupt for event CTS
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ NCTS
+ Enable or disable interrupt for event NCTS
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXDRDY
+ Enable or disable interrupt for event RXDRDY
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDRX
+ Enable or disable interrupt for event ENDRX
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXDRDY
+ Enable or disable interrupt for event TXDRDY
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDTX
+ Enable or disable interrupt for event ENDTX
+ 8
+ 8
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Enable or disable interrupt for event ERROR
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXTO
+ Enable or disable interrupt for event RXTO
+ 17
+ 17
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Enable or disable interrupt for event RXSTARTED
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Enable or disable interrupt for event TXSTARTED
+ 20
+ 20
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXSTOPPED
+ Enable or disable interrupt for event TXSTOPPED
+ 22
+ 22
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ CTS
+ Write '1' to enable interrupt for event CTS
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ NCTS
+ Write '1' to enable interrupt for event NCTS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXDRDY
+ Write '1' to enable interrupt for event RXDRDY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to enable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXDRDY
+ Write '1' to enable interrupt for event TXDRDY
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDTX
+ Write '1' to enable interrupt for event ENDTX
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXTO
+ Write '1' to enable interrupt for event RXTO
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to enable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to enable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXSTOPPED
+ Write '1' to enable interrupt for event TXSTOPPED
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ CTS
+ Write '1' to disable interrupt for event CTS
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ NCTS
+ Write '1' to disable interrupt for event NCTS
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXDRDY
+ Write '1' to disable interrupt for event RXDRDY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to disable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXDRDY
+ Write '1' to disable interrupt for event TXDRDY
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDTX
+ Write '1' to disable interrupt for event ENDTX
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXTO
+ Write '1' to disable interrupt for event RXTO
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to disable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to disable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXSTOPPED
+ Write '1' to disable interrupt for event TXSTOPPED
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSRC
+ Error source Note : this register is read / write one to clear.
+ 0x480
+ read-write
+ oneToClear
+
+
+ OVERRUN
+ Overrun error
+ 0
+ 0
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ PARITY
+ Parity error
+ 1
+ 1
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ FRAMING
+ Framing error occurred
+ 2
+ 2
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ BREAK
+ Break condition
+ 3
+ 3
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable UART
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable UARTE
+ 0
+ 3
+
+
+ Disabled
+ Disable UARTE
+ 0
+
+
+ Enabled
+ Enable UARTE
+ 8
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ UARTE_PSEL
+ read-write
+ 0x508
+
+ RTS
+ Pin select for RTS signal
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ TXD
+ Pin select for TXD signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ CTS
+ Pin select for CTS signal
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ RXD
+ Pin select for RXD signal
+ 0x00C
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ BAUDRATE
+ Baud rate. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ BAUDRATE
+ Baud rate
+ 0
+ 31
+
+
+ Baud1200
+ 1200 baud (actual rate: 1205)
+ 0x0004F000
+
+
+ Baud2400
+ 2400 baud (actual rate: 2396)
+ 0x0009D000
+
+
+ Baud4800
+ 4800 baud (actual rate: 4808)
+ 0x0013B000
+
+
+ Baud9600
+ 9600 baud (actual rate: 9598)
+ 0x00275000
+
+
+ Baud14400
+ 14400 baud (actual rate: 14401)
+ 0x003AF000
+
+
+ Baud19200
+ 19200 baud (actual rate: 19208)
+ 0x004EA000
+
+
+ Baud28800
+ 28800 baud (actual rate: 28777)
+ 0x0075C000
+
+
+ Baud31250
+ 31250 baud
+ 0x00800000
+
+
+ Baud38400
+ 38400 baud (actual rate: 38369)
+ 0x009D0000
+
+
+ Baud56000
+ 56000 baud (actual rate: 55944)
+ 0x00E50000
+
+
+ Baud57600
+ 57600 baud (actual rate: 57554)
+ 0x00EB0000
+
+
+ Baud76800
+ 76800 baud (actual rate: 76923)
+ 0x013A9000
+
+
+ Baud115200
+ 115200 baud (actual rate: 115108)
+ 0x01D60000
+
+
+ Baud230400
+ 230400 baud (actual rate: 231884)
+ 0x03B00000
+
+
+ Baud250000
+ 250000 baud
+ 0x04000000
+
+
+ Baud460800
+ 460800 baud (actual rate: 457143)
+ 0x07400000
+
+
+ Baud921600
+ 921600 baud (actual rate: 941176)
+ 0x0F000000
+
+
+ Baud1M
+ 1Mega baud
+ 0x10000000
+
+
+
+
+
+
+ RXD
+ RXD EasyDMA channel
+ UARTE_RXD
+ read-write
+ 0x534
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0
+ 15
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 15
+
+
+
+
+
+ TXD
+ TXD EasyDMA channel
+ UARTE_TXD
+ read-write
+ 0x544
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0
+ 15
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 15
+
+
+
+
+
+ CONFIG
+ Configuration of parity and hardware flow control
+ 0x56C
+ read-write
+
+
+ HWFC
+ Hardware flow control
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ PARITY
+ Parity
+ 1
+ 3
+
+
+ Excluded
+ Exclude parity bit
+ 0x0
+
+
+ Included
+ Include even parity bit
+ 0x7
+
+
+
+
+ STOP
+ Stop bits
+ 4
+ 4
+
+
+ One
+ One stop bit
+ 0
+
+
+ Two
+ Two stop bits
+ 1
+
+
+
+
+ PARITYTYPE
+ Even or odd parity type
+ 8
+ 8
+
+
+ Even
+ Even parity
+ 0
+
+
+ Odd
+ Odd parity
+ 1
+
+
+
+
+
+
+
+
+ SPI0
+ Serial Peripheral Interface 0
+ 0x40003000
+ SPI
+
+ 0
+ 0x1000
+ registers
+
+
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0
+ 3
+
+ SPI
+ 0x20
+
+
+ EVENTS_READY
+ TXD byte sent and RXD byte received
+ 0x108
+ read-write
+
+
+ EVENTS_READY
+ TXD byte sent and RXD byte received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ READY
+ Write '1' to enable interrupt for event READY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ READY
+ Write '1' to disable interrupt for event READY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable SPI
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable SPI
+ 0
+ 3
+
+
+ Disabled
+ Disable SPI
+ 0
+
+
+ Enabled
+ Enable SPI
+ 1
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ SPI_PSEL
+ read-write
+ 0x508
+
+ SCK
+ Pin select for SCK
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MOSI
+ Pin select for MOSI signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MISO
+ Pin select for MISO signal
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ RXD
+ RXD register
+ 0x518
+ read-only
+ modifyExternal
+
+
+ RXD
+ RX data received. Double buffered
+ 0
+ 7
+
+
+
+
+ TXD
+ TXD register
+ 0x51C
+ read-write
+
+
+ TXD
+ TX data to send. Double buffered
+ 0
+ 7
+
+
+
+
+ FREQUENCY
+ SPI frequency. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ FREQUENCY
+ SPI master data rate
+ 0
+ 31
+
+
+ K125
+ 125 kbps
+ 0x02000000
+
+
+ K250
+ 250 kbps
+ 0x04000000
+
+
+ K500
+ 500 kbps
+ 0x08000000
+
+
+ M1
+ 1 Mbps
+ 0x10000000
+
+
+ M2
+ 2 Mbps
+ 0x20000000
+
+
+ M4
+ 4 Mbps
+ 0x40000000
+
+
+ M8
+ 8 Mbps
+ 0x80000000
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x554
+ read-write
+
+
+ ORDER
+ Bit order
+ 0
+ 0
+
+
+ MsbFirst
+ Most significant bit shifted out first
+ 0
+
+
+ LsbFirst
+ Least significant bit shifted out first
+ 1
+
+
+
+
+ CPHA
+ Serial clock (SCK) phase
+ 1
+ 1
+
+
+ Leading
+ Sample on leading edge of clock, shift serial data on trailing edge
+ 0
+
+
+ Trailing
+ Sample on trailing edge of clock, shift serial data on leading edge
+ 1
+
+
+
+
+ CPOL
+ Serial clock (SCK) polarity
+ 2
+ 2
+
+
+ ActiveHigh
+ Active high
+ 0
+
+
+ ActiveLow
+ Active low
+ 1
+
+
+
+
+
+
+
+
+ SPIM0
+ Serial Peripheral Interface Master with EasyDMA 0
+ 0x40003000
+ SPI0
+ SPIM
+
+ 0
+ 0x1000
+ registers
+
+
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0
+ 3
+
+ SPIM
+ 0x20
+
+
+ TASKS_START
+ Start SPI transaction
+ 0x010
+ write-only
+
+
+ TASKS_START
+ Start SPI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop SPI transaction
+ 0x014
+ write-only
+
+
+ TASKS_STOP
+ Stop SPI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SUSPEND
+ Suspend SPI transaction
+ 0x01C
+ write-only
+
+
+ TASKS_SUSPEND
+ Suspend SPI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RESUME
+ Resume SPI transaction
+ 0x020
+ write-only
+
+
+ TASKS_RESUME
+ Resume SPI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ SPI transaction has stopped
+ 0x104
+ read-write
+
+
+ EVENTS_STOPPED
+ SPI transaction has stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDRX
+ End of RXD buffer reached
+ 0x110
+ read-write
+
+
+ EVENTS_ENDRX
+ End of RXD buffer reached
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ End of RXD buffer and TXD buffer reached
+ 0x118
+ read-write
+
+
+ EVENTS_END
+ End of RXD buffer and TXD buffer reached
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDTX
+ End of TXD buffer reached
+ 0x120
+ read-write
+
+
+ EVENTS_ENDTX
+ End of TXD buffer reached
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_STARTED
+ Transaction started
+ 0x14C
+ read-write
+
+
+ EVENTS_STARTED
+ Transaction started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ END_START
+ Shortcut between event END and task START
+ 17
+ 17
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to enable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDTX
+ Write '1' to enable interrupt for event ENDTX
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ STARTED
+ Write '1' to enable interrupt for event STARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to disable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDTX
+ Write '1' to disable interrupt for event ENDTX
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ STARTED
+ Write '1' to disable interrupt for event STARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ STALLSTAT
+ Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.
+ 0x400
+ read-write
+ 0x00000000
+
+
+ TX
+ Stall status for EasyDMA RAM reads
+ 0
+ 0
+
+
+ NOSTALL
+ No stall
+ 0
+
+
+ STALL
+ A stall has occurred
+ 1
+
+
+
+
+ RX
+ Stall status for EasyDMA RAM writes
+ 1
+ 1
+
+
+ NOSTALL
+ No stall
+ 0
+
+
+ STALL
+ A stall has occurred
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable SPIM
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable SPIM
+ 0
+ 3
+
+
+ Disabled
+ Disable SPIM
+ 0
+
+
+ Enabled
+ Enable SPIM
+ 7
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ SPIM_PSEL
+ read-write
+ 0x508
+
+ SCK
+ Pin select for SCK
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MOSI
+ Pin select for MOSI signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MISO
+ Pin select for MISO signal
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ CSN
+ Pin select for CSN
+ 0x00C
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ FREQUENCY
+ SPI frequency. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ FREQUENCY
+ SPI master data rate
+ 0
+ 31
+
+
+ K125
+ 125 kbps
+ 0x02000000
+
+
+ K250
+ 250 kbps
+ 0x04000000
+
+
+ K500
+ 500 kbps
+ 0x08000000
+
+
+ M1
+ 1 Mbps
+ 0x10000000
+
+
+ M2
+ 2 Mbps
+ 0x20000000
+
+
+ M4
+ 4 Mbps
+ 0x40000000
+
+
+ M8
+ 8 Mbps
+ 0x80000000
+
+
+ M16
+ 16 Mbps
+ 0x0A000000
+
+
+ M32
+ 32 Mbps
+ 0x14000000
+
+
+
+
+
+
+ RXD
+ RXD EasyDMA channel
+ SPIM_RXD
+ read-write
+ 0x534
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0
+ 15
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 15
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ TXD
+ TXD EasyDMA channel
+ SPIM_TXD
+ read-write
+ 0x544
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Number of bytes in transmit buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0
+ 15
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 15
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x554
+ read-write
+
+
+ ORDER
+ Bit order
+ 0
+ 0
+
+
+ MsbFirst
+ Most significant bit shifted out first
+ 0
+
+
+ LsbFirst
+ Least significant bit shifted out first
+ 1
+
+
+
+
+ CPHA
+ Serial clock (SCK) phase
+ 1
+ 1
+
+
+ Leading
+ Sample on leading edge of clock, shift serial data on trailing edge
+ 0
+
+
+ Trailing
+ Sample on trailing edge of clock, shift serial data on leading edge
+ 1
+
+
+
+
+ CPOL
+ Serial clock (SCK) polarity
+ 2
+ 2
+
+
+ ActiveHigh
+ Active high
+ 0
+
+
+ ActiveLow
+ Active low
+ 1
+
+
+
+
+
+
+ IFTIMING
+ Unspecified
+ SPIM_IFTIMING
+ read-write
+ 0x560
+
+ RXDELAY
+ Sample delay for input serial data on MISO
+ 0x000
+ read-write
+ 0x00000002
+
+
+ RXDELAY
+ Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK.
+ 0
+ 2
+
+
+
+
+ CSNDUR
+ Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions
+ 0x004
+ read-write
+ 0x00000002
+
+
+ CSNDUR
+ Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns).
+ 0
+ 7
+
+
+
+
+
+ CSNPOL
+ Polarity of CSN output
+ 0x568
+ read-write
+ 0x00000000
+
+
+ CSNPOL
+ Polarity of CSN output
+ 0
+ 0
+
+
+ LOW
+ Active low (idle state high)
+ 0
+
+
+ HIGH
+ Active high (idle state low)
+ 1
+
+
+
+
+
+
+ PSELDCX
+ Pin select for DCX signal
+ 0x56C
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ DCXCNT
+ DCX configuration
+ 0x570
+ read-write
+
+
+ DCXCNT
+ This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes.
+ 0
+ 3
+
+
+
+
+ ORC
+ Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT
+ 0x5C0
+ read-write
+
+
+ ORC
+ Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT.
+ 0
+ 7
+
+
+
+
+
+
+ SPIS0
+ SPI Slave 0
+ 0x40003000
+ SPI0
+ SPIS
+
+ 0
+ 0x1000
+ registers
+
+
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0
+ 3
+
+ SPIS
+ 0x20
+
+
+ TASKS_ACQUIRE
+ Acquire SPI semaphore
+ 0x024
+ write-only
+
+
+ TASKS_ACQUIRE
+ Acquire SPI semaphore
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RELEASE
+ Release SPI semaphore, enabling the SPI slave to acquire it
+ 0x028
+ write-only
+
+
+ TASKS_RELEASE
+ Release SPI semaphore, enabling the SPI slave to acquire it
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ Granted transaction completed
+ 0x104
+ read-write
+
+
+ EVENTS_END
+ Granted transaction completed
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDRX
+ End of RXD buffer reached
+ 0x110
+ read-write
+
+
+ EVENTS_ENDRX
+ End of RXD buffer reached
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ACQUIRED
+ Semaphore acquired
+ 0x128
+ read-write
+
+
+ EVENTS_ACQUIRED
+ Semaphore acquired
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ END_ACQUIRE
+ Shortcut between event END and task ACQUIRE
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to enable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ACQUIRED
+ Write '1' to enable interrupt for event ACQUIRED
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to disable interrupt for event ENDRX
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ACQUIRED
+ Write '1' to disable interrupt for event ACQUIRED
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ SEMSTAT
+ Semaphore status register
+ 0x400
+ read-only
+ 0x00000001
+
+
+ SEMSTAT
+ Semaphore status
+ 0
+ 1
+
+
+ Free
+ Semaphore is free
+ 0
+
+
+ CPU
+ Semaphore is assigned to CPU
+ 1
+
+
+ SPIS
+ Semaphore is assigned to SPI slave
+ 2
+
+
+ CPUPending
+ Semaphore is assigned to SPI but a handover to the CPU is pending
+ 3
+
+
+
+
+
+
+ STATUS
+ Status from last transaction
+ 0x440
+ read-write
+
+
+ OVERREAD
+ TX buffer over-read detected, and prevented
+ 0
+ 0
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+ write
+
+ Clear
+ Write: clear error on writing '1'
+ 1
+
+
+
+
+ OVERFLOW
+ RX buffer overflow detected, and prevented
+ 1
+ 1
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+ write
+
+ Clear
+ Write: clear error on writing '1'
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable SPI slave
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable SPI slave
+ 0
+ 3
+
+
+ Disabled
+ Disable SPI slave
+ 0
+
+
+ Enabled
+ Enable SPI slave
+ 2
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ SPIS_PSEL
+ read-write
+ 0x508
+
+ SCK
+ Pin select for SCK
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MISO
+ Pin select for MISO signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ MOSI
+ Pin select for MOSI signal
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ CSN
+ Pin select for CSN signal
+ 0x00C
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ RXD
+ Unspecified
+ SPIS_RXD
+ read-write
+ 0x534
+
+ PTR
+ RXD data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ RXD data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0
+ 15
+
+
+
+
+ AMOUNT
+ Number of bytes received in last granted transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes received in the last granted transaction
+ 0
+ 15
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ TXD
+ Unspecified
+ SPIS_TXD
+ read-write
+ 0x544
+
+ PTR
+ TXD data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ TXD data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0
+ 15
+
+
+
+
+ AMOUNT
+ Number of bytes transmitted in last granted transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transmitted in last granted transaction
+ 0
+ 15
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x554
+ read-write
+
+
+ ORDER
+ Bit order
+ 0
+ 0
+
+
+ MsbFirst
+ Most significant bit shifted out first
+ 0
+
+
+ LsbFirst
+ Least significant bit shifted out first
+ 1
+
+
+
+
+ CPHA
+ Serial clock (SCK) phase
+ 1
+ 1
+
+
+ Leading
+ Sample on leading edge of clock, shift serial data on trailing edge
+ 0
+
+
+ Trailing
+ Sample on trailing edge of clock, shift serial data on leading edge
+ 1
+
+
+
+
+ CPOL
+ Serial clock (SCK) polarity
+ 2
+ 2
+
+
+ ActiveHigh
+ Active high
+ 0
+
+
+ ActiveLow
+ Active low
+ 1
+
+
+
+
+
+
+ DEF
+ Default character. Character clocked out in case of an ignored transaction.
+ 0x55C
+ read-write
+
+
+ DEF
+ Default character. Character clocked out in case of an ignored transaction.
+ 0
+ 7
+
+
+
+
+ ORC
+ Over-read character
+ 0x5C0
+ read-write
+
+
+ ORC
+ Over-read character. Character clocked out after an over-read of the transmit buffer.
+ 0
+ 7
+
+
+
+
+
+
+ TWI0
+ I2C compatible Two-Wire Interface 0
+ 0x40003000
+ SPI0
+ TWI
+
+ 0
+ 0x1000
+ registers
+
+
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0
+ 3
+
+ TWI
+ 0x20
+
+
+ TASKS_STARTRX
+ Start TWI receive sequence
+ 0x000
+ write-only
+
+
+ TASKS_STARTRX
+ Start TWI receive sequence
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTTX
+ Start TWI transmit sequence
+ 0x008
+ write-only
+
+
+ TASKS_STARTTX
+ Start TWI transmit sequence
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop TWI transaction
+ 0x014
+ write-only
+
+
+ TASKS_STOP
+ Stop TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0x01C
+ write-only
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0x020
+ write-only
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0x104
+ read-write
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXDREADY
+ TWI RXD byte received
+ 0x108
+ read-write
+
+
+ EVENTS_RXDREADY
+ TWI RXD byte received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXDSENT
+ TWI TXD byte sent
+ 0x11C
+ read-write
+
+
+ EVENTS_TXDSENT
+ TWI TXD byte sent
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ TWI error
+ 0x124
+ read-write
+
+
+ EVENTS_ERROR
+ TWI error
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_BB
+ TWI byte boundary, generated before each byte that is sent or received
+ 0x138
+ read-write
+
+
+ EVENTS_BB
+ TWI byte boundary, generated before each byte that is sent or received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_SUSPENDED
+ TWI entered the suspended state
+ 0x148
+ read-write
+
+
+ EVENTS_SUSPENDED
+ TWI entered the suspended state
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ BB_SUSPEND
+ Shortcut between event BB and task SUSPEND
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ BB_STOP
+ Shortcut between event BB and task STOP
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXDREADY
+ Write '1' to enable interrupt for event RXDREADY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXDSENT
+ Write '1' to enable interrupt for event TXDSENT
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ BB
+ Write '1' to enable interrupt for event BB
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SUSPENDED
+ Write '1' to enable interrupt for event SUSPENDED
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXDREADY
+ Write '1' to disable interrupt for event RXDREADY
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXDSENT
+ Write '1' to disable interrupt for event TXDSENT
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ BB
+ Write '1' to disable interrupt for event BB
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SUSPENDED
+ Write '1' to disable interrupt for event SUSPENDED
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSRC
+ Error source
+ 0x4C4
+ read-write
+ oneToClear
+
+
+ OVERRUN
+ Overrun error
+ 0
+ 0
+
+ read
+
+ NotPresent
+ Read: no overrun occured
+ 0
+
+
+ Present
+ Read: overrun occured
+ 1
+
+
+
+
+ ANACK
+ NACK received after sending the address (write '1' to clear)
+ 1
+ 1
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+ DNACK
+ NACK received after sending a data byte (write '1' to clear)
+ 2
+ 2
+
+ read
+
+ NotPresent
+ Read: error not present
+ 0
+
+
+ Present
+ Read: error present
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable TWI
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable TWI
+ 0
+ 3
+
+
+ Disabled
+ Disable TWI
+ 0
+
+
+ Enabled
+ Enable TWI
+ 5
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ TWI_PSEL
+ read-write
+ 0x508
+
+ SCL
+ Pin select for SCL
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ SDA
+ Pin select for SDA
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ RXD
+ RXD register
+ 0x518
+ read-only
+ modifyExternal
+
+
+ RXD
+ RXD register
+ 0
+ 7
+
+
+
+
+ TXD
+ TXD register
+ 0x51C
+ read-write
+
+
+ TXD
+ TXD register
+ 0
+ 7
+
+
+
+
+ FREQUENCY
+ TWI frequency. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ FREQUENCY
+ TWI master clock frequency
+ 0
+ 31
+
+
+ K100
+ 100 kbps
+ 0x01980000
+
+
+ K250
+ 250 kbps
+ 0x04000000
+
+
+ K400
+ 400 kbps (actual rate 410.256 kbps)
+ 0x06680000
+
+
+
+
+
+
+ ADDRESS
+ Address used in the TWI transfer
+ 0x588
+ read-write
+
+
+ ADDRESS
+ Address used in the TWI transfer
+ 0
+ 6
+
+
+
+
+
+
+ TWIM0
+ I2C compatible Two-Wire Master Interface with EasyDMA 0
+ 0x40003000
+ SPI0
+ TWIM
+
+ 0
+ 0x1000
+ registers
+
+
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0
+ 3
+
+ TWIM
+ 0x20
+
+
+ TASKS_STARTRX
+ Start TWI receive sequence
+ 0x000
+ write-only
+
+
+ TASKS_STARTRX
+ Start TWI receive sequence
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTTX
+ Start TWI transmit sequence
+ 0x008
+ write-only
+
+
+ TASKS_STARTTX
+ Start TWI transmit sequence
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop TWI transaction. Must be issued while the TWI master is not suspended.
+ 0x014
+ write-only
+
+
+ TASKS_STOP
+ Stop TWI transaction. Must be issued while the TWI master is not suspended.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0x01C
+ write-only
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0x020
+ write-only
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0x104
+ read-write
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ TWI error
+ 0x124
+ read-write
+
+
+ EVENTS_ERROR
+ TWI error
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_SUSPENDED
+ Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
+ 0x148
+ read-write
+
+
+ EVENTS_SUSPENDED
+ Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXSTARTED
+ Receive sequence started
+ 0x14C
+ read-write
+
+
+ EVENTS_RXSTARTED
+ Receive sequence started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXSTARTED
+ Transmit sequence started
+ 0x150
+ read-write
+
+
+ EVENTS_TXSTARTED
+ Transmit sequence started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_LASTRX
+ Byte boundary, starting to receive the last byte
+ 0x15C
+ read-write
+
+
+ EVENTS_LASTRX
+ Byte boundary, starting to receive the last byte
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_LASTTX
+ Byte boundary, starting to transmit the last byte
+ 0x160
+ read-write
+
+
+ EVENTS_LASTTX
+ Byte boundary, starting to transmit the last byte
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ LASTTX_STARTRX
+ Shortcut between event LASTTX and task STARTRX
+ 7
+ 7
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LASTTX_SUSPEND
+ Shortcut between event LASTTX and task SUSPEND
+ 8
+ 8
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LASTTX_STOP
+ Shortcut between event LASTTX and task STOP
+ 9
+ 9
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LASTRX_STARTTX
+ Shortcut between event LASTRX and task STARTTX
+ 10
+ 10
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LASTRX_SUSPEND
+ Shortcut between event LASTRX and task SUSPEND
+ 11
+ 11
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LASTRX_STOP
+ Shortcut between event LASTRX and task STOP
+ 12
+ 12
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ STOPPED
+ Enable or disable interrupt for event STOPPED
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Enable or disable interrupt for event ERROR
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ SUSPENDED
+ Enable or disable interrupt for event SUSPENDED
+ 18
+ 18
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Enable or disable interrupt for event RXSTARTED
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Enable or disable interrupt for event TXSTARTED
+ 20
+ 20
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ LASTRX
+ Enable or disable interrupt for event LASTRX
+ 23
+ 23
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ LASTTX
+ Enable or disable interrupt for event LASTTX
+ 24
+ 24
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SUSPENDED
+ Write '1' to enable interrupt for event SUSPENDED
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to enable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to enable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ LASTRX
+ Write '1' to enable interrupt for event LASTRX
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ LASTTX
+ Write '1' to enable interrupt for event LASTTX
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SUSPENDED
+ Write '1' to disable interrupt for event SUSPENDED
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to disable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to disable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ LASTRX
+ Write '1' to disable interrupt for event LASTRX
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ LASTTX
+ Write '1' to disable interrupt for event LASTTX
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSRC
+ Error source
+ 0x4C4
+ read-write
+ oneToClear
+
+
+ OVERRUN
+ Overrun error
+ 0
+ 0
+
+
+ NotReceived
+ Error did not occur
+ 0
+
+
+ Received
+ Error occurred
+ 1
+
+
+
+
+ ANACK
+ NACK received after sending the address (write '1' to clear)
+ 1
+ 1
+
+
+ NotReceived
+ Error did not occur
+ 0
+
+
+ Received
+ Error occurred
+ 1
+
+
+
+
+ DNACK
+ NACK received after sending a data byte (write '1' to clear)
+ 2
+ 2
+
+
+ NotReceived
+ Error did not occur
+ 0
+
+
+ Received
+ Error occurred
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable TWIM
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable TWIM
+ 0
+ 3
+
+
+ Disabled
+ Disable TWIM
+ 0
+
+
+ Enabled
+ Enable TWIM
+ 6
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ TWIM_PSEL
+ read-write
+ 0x508
+
+ SCL
+ Pin select for SCL signal
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ SDA
+ Pin select for SDA signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ FREQUENCY
+ TWI frequency. Accuracy depends on the HFCLK source selected.
+ 0x524
+ read-write
+ 0x04000000
+
+
+ FREQUENCY
+ TWI master clock frequency
+ 0
+ 31
+
+
+ K100
+ 100 kbps
+ 0x01980000
+
+
+ K250
+ 250 kbps
+ 0x04000000
+
+
+ K400
+ 400 kbps
+ 0x06400000
+
+
+
+
+
+
+ RXD
+ RXD EasyDMA channel
+ TWIM_RXD
+ read-write
+ 0x534
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in receive buffer
+ 0
+ 15
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte.
+ 0
+ 15
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 2
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ TXD
+ TXD EasyDMA channel
+ TWIM_TXD
+ read-write
+ 0x544
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in transmit buffer
+ 0
+ 15
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte.
+ 0
+ 15
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 2
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ ADDRESS
+ Address used in the TWI transfer
+ 0x588
+ read-write
+
+
+ ADDRESS
+ Address used in the TWI transfer
+ 0
+ 6
+
+
+
+
+
+
+ TWIS0
+ I2C compatible Two-Wire Slave Interface with EasyDMA 0
+ 0x40003000
+ SPI0
+ TWIS
+
+ 0
+ 0x1000
+ registers
+
+
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0
+ 3
+
+ TWIS
+ 0x20
+
+
+ TASKS_STOP
+ Stop TWI transaction
+ 0x014
+ write-only
+
+
+ TASKS_STOP
+ Stop TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0x01C
+ write-only
+
+
+ TASKS_SUSPEND
+ Suspend TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0x020
+ write-only
+
+
+ TASKS_RESUME
+ Resume TWI transaction
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_PREPARERX
+ Prepare the TWI slave to respond to a write command
+ 0x030
+ write-only
+
+
+ TASKS_PREPARERX
+ Prepare the TWI slave to respond to a write command
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_PREPARETX
+ Prepare the TWI slave to respond to a read command
+ 0x034
+ write-only
+
+
+ TASKS_PREPARETX
+ Prepare the TWI slave to respond to a read command
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0x104
+ read-write
+
+
+ EVENTS_STOPPED
+ TWI stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ TWI error
+ 0x124
+ read-write
+
+
+ EVENTS_ERROR
+ TWI error
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXSTARTED
+ Receive sequence started
+ 0x14C
+ read-write
+
+
+ EVENTS_RXSTARTED
+ Receive sequence started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXSTARTED
+ Transmit sequence started
+ 0x150
+ read-write
+
+
+ EVENTS_TXSTARTED
+ Transmit sequence started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_WRITE
+ Write command received
+ 0x164
+ read-write
+
+
+ EVENTS_WRITE
+ Write command received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_READ
+ Read command received
+ 0x168
+ read-write
+
+
+ EVENTS_READ
+ Read command received
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ WRITE_SUSPEND
+ Shortcut between event WRITE and task SUSPEND
+ 13
+ 13
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ READ_SUSPEND
+ Shortcut between event READ and task SUSPEND
+ 14
+ 14
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ STOPPED
+ Enable or disable interrupt for event STOPPED
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Enable or disable interrupt for event ERROR
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Enable or disable interrupt for event RXSTARTED
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Enable or disable interrupt for event TXSTARTED
+ 20
+ 20
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ WRITE
+ Enable or disable interrupt for event WRITE
+ 25
+ 25
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ READ
+ Enable or disable interrupt for event READ
+ 26
+ 26
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to enable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to enable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ WRITE
+ Write '1' to enable interrupt for event WRITE
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ READ
+ Write '1' to enable interrupt for event READ
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXSTARTED
+ Write '1' to disable interrupt for event RXSTARTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXSTARTED
+ Write '1' to disable interrupt for event TXSTARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ WRITE
+ Write '1' to disable interrupt for event WRITE
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ READ
+ Write '1' to disable interrupt for event READ
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSRC
+ Error source
+ 0x4D0
+ read-write
+ oneToClear
+
+
+ OVERFLOW
+ RX buffer overflow detected, and prevented
+ 0
+ 0
+
+
+ NotDetected
+ Error did not occur
+ 0
+
+
+ Detected
+ Error occurred
+ 1
+
+
+
+
+ DNACK
+ NACK sent after receiving a data byte
+ 2
+ 2
+
+
+ NotReceived
+ Error did not occur
+ 0
+
+
+ Received
+ Error occurred
+ 1
+
+
+
+
+ OVERREAD
+ TX buffer over-read detected, and prevented
+ 3
+ 3
+
+
+ NotDetected
+ Error did not occur
+ 0
+
+
+ Detected
+ Error occurred
+ 1
+
+
+
+
+
+
+ MATCH
+ Status register indicating which address had a match
+ 0x4D4
+ read-only
+
+
+ MATCH
+ Which of the addresses in {ADDRESS} matched the incoming address
+ 0
+ 0
+
+
+
+
+ ENABLE
+ Enable TWIS
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable TWIS
+ 0
+ 3
+
+
+ Disabled
+ Disable TWIS
+ 0
+
+
+ Enabled
+ Enable TWIS
+ 9
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ TWIS_PSEL
+ read-write
+ 0x508
+
+ SCL
+ Pin select for SCL signal
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ SDA
+ Pin select for SDA signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ RXD
+ RXD EasyDMA channel
+ TWIS_RXD
+ read-write
+ 0x534
+
+ PTR
+ RXD Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ RXD Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in RXD buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in RXD buffer
+ 0
+ 15
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last RXD transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last RXD transaction
+ 0
+ 15
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ TXD
+ TXD EasyDMA channel
+ TWIS_TXD
+ read-write
+ 0x544
+
+ PTR
+ TXD Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ TXD Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes in TXD buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes in TXD buffer
+ 0
+ 15
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last TXD transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last TXD transaction
+ 0
+ 15
+
+
+
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
+
+
+ 0x2
+ 0x4
+ ADDRESS[%s]
+ Description collection: TWI slave address n
+ 0x588
+ read-write
+
+
+ ADDRESS
+ TWI slave address
+ 0
+ 6
+
+
+
+
+ CONFIG
+ Configuration register for the address match mechanism
+ 0x594
+ read-write
+ 0x00000001
+
+
+ ADDRESS0
+ Enable or disable address matching on ADDRESS[0]
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+ ADDRESS1
+ Enable or disable address matching on ADDRESS[1]
+ 1
+ 1
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+
+
+ ORC
+ Over-read character. Character sent out in case of an over-read of the transmit buffer.
+ 0x5C0
+ read-write
+
+
+ ORC
+ Over-read character. Character sent out in case of an over-read of the transmit buffer.
+ 0
+ 7
+
+
+
+
+
+
+ SPI1
+ Serial Peripheral Interface 1
+ 0x40004000
+
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1
+ 4
+
+
+
+ SPIM1
+ Serial Peripheral Interface Master with EasyDMA 1
+ 0x40004000
+ SPI1
+
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1
+ 4
+
+
+
+ SPIS1
+ SPI Slave 1
+ 0x40004000
+ SPI1
+
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1
+ 4
+
+
+
+ TWI1
+ I2C compatible Two-Wire Interface 1
+ 0x40004000
+ SPI1
+
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1
+ 4
+
+
+
+ TWIM1
+ I2C compatible Two-Wire Master Interface with EasyDMA 1
+ 0x40004000
+ SPI1
+
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1
+ 4
+
+
+
+ TWIS1
+ I2C compatible Two-Wire Slave Interface with EasyDMA 1
+ 0x40004000
+ SPI1
+
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1
+ 4
+
+
+
+ NFCT
+ NFC-A compatible radio
+ 0x40005000
+
+ 0
+ 0x1000
+ registers
+
+
+ NFCT
+ 5
+
+ NFCT
+ 0x20
+
+
+ TASKS_ACTIVATE
+ Activate NFCT peripheral for incoming and outgoing frames, change state to activated
+ 0x000
+ write-only
+
+
+ TASKS_ACTIVATE
+ Activate NFCT peripheral for incoming and outgoing frames, change state to activated
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_DISABLE
+ Disable NFCT peripheral
+ 0x004
+ write-only
+
+
+ TASKS_DISABLE
+ Disable NFCT peripheral
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SENSE
+ Enable NFC sense field mode, change state to sense mode
+ 0x008
+ write-only
+
+
+ TASKS_SENSE
+ Enable NFC sense field mode, change state to sense mode
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTTX
+ Start transmission of an outgoing frame, change state to transmit
+ 0x00C
+ write-only
+
+
+ TASKS_STARTTX
+ Start transmission of an outgoing frame, change state to transmit
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_ENABLERXDATA
+ Initializes the EasyDMA for receive.
+ 0x01C
+ write-only
+
+
+ TASKS_ENABLERXDATA
+ Initializes the EasyDMA for receive.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_GOIDLE
+ Force state machine to IDLE state
+ 0x024
+ write-only
+
+
+ TASKS_GOIDLE
+ Force state machine to IDLE state
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_GOSLEEP
+ Force state machine to SLEEP_A state
+ 0x028
+ write-only
+
+
+ TASKS_GOSLEEP
+ Force state machine to SLEEP_A state
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_READY
+ The NFCT peripheral is ready to receive and send frames
+ 0x100
+ read-write
+
+
+ EVENTS_READY
+ The NFCT peripheral is ready to receive and send frames
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_FIELDDETECTED
+ Remote NFC field detected
+ 0x104
+ read-write
+
+
+ EVENTS_FIELDDETECTED
+ Remote NFC field detected
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_FIELDLOST
+ Remote NFC field lost
+ 0x108
+ read-write
+
+
+ EVENTS_FIELDLOST
+ Remote NFC field lost
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXFRAMESTART
+ Marks the start of the first symbol of a transmitted frame
+ 0x10C
+ read-write
+
+
+ EVENTS_TXFRAMESTART
+ Marks the start of the first symbol of a transmitted frame
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXFRAMEEND
+ Marks the end of the last transmitted on-air symbol of a frame
+ 0x110
+ read-write
+
+
+ EVENTS_TXFRAMEEND
+ Marks the end of the last transmitted on-air symbol of a frame
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXFRAMESTART
+ Marks the end of the first symbol of a received frame
+ 0x114
+ read-write
+
+
+ EVENTS_RXFRAMESTART
+ Marks the end of the first symbol of a received frame
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXFRAMEEND
+ Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer
+ 0x118
+ read-write
+
+
+ EVENTS_RXFRAMEEND
+ Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ NFC error reported. The ERRORSTATUS register contains details on the source of the error.
+ 0x11C
+ read-write
+
+
+ EVENTS_ERROR
+ NFC error reported. The ERRORSTATUS register contains details on the source of the error.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RXERROR
+ NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
+ 0x128
+ read-write
+
+
+ EVENTS_RXERROR
+ NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDRX
+ RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
+ 0x12C
+ read-write
+
+
+ EVENTS_ENDRX
+ RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDTX
+ Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
+ 0x130
+ read-write
+
+
+ EVENTS_ENDTX
+ Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_AUTOCOLRESSTARTED
+ Auto collision resolution process has started
+ 0x138
+ read-write
+
+
+ EVENTS_AUTOCOLRESSTARTED
+ Auto collision resolution process has started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_COLLISION
+ NFC auto collision resolution error reported.
+ 0x148
+ read-write
+
+
+ EVENTS_COLLISION
+ NFC auto collision resolution error reported.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_SELECTED
+ NFC auto collision resolution successfully completed
+ 0x14C
+ read-write
+
+
+ EVENTS_SELECTED
+ NFC auto collision resolution successfully completed
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_STARTED
+ EasyDMA is ready to receive or send frames.
+ 0x150
+ read-write
+
+
+ EVENTS_STARTED
+ EasyDMA is ready to receive or send frames.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ FIELDDETECTED_ACTIVATE
+ Shortcut between event FIELDDETECTED and task ACTIVATE
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ FIELDLOST_SENSE
+ Shortcut between event FIELDLOST and task SENSE
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ TXFRAMEEND_ENABLERXDATA
+ Shortcut between event TXFRAMEEND and task ENABLERXDATA
+ 5
+ 5
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ READY
+ Enable or disable interrupt for event READY
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ FIELDDETECTED
+ Enable or disable interrupt for event FIELDDETECTED
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ FIELDLOST
+ Enable or disable interrupt for event FIELDLOST
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXFRAMESTART
+ Enable or disable interrupt for event TXFRAMESTART
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXFRAMEEND
+ Enable or disable interrupt for event TXFRAMEEND
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXFRAMESTART
+ Enable or disable interrupt for event RXFRAMESTART
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXFRAMEEND
+ Enable or disable interrupt for event RXFRAMEEND
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Enable or disable interrupt for event ERROR
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RXERROR
+ Enable or disable interrupt for event RXERROR
+ 10
+ 10
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDRX
+ Enable or disable interrupt for event ENDRX
+ 11
+ 11
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDTX
+ Enable or disable interrupt for event ENDTX
+ 12
+ 12
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ AUTOCOLRESSTARTED
+ Enable or disable interrupt for event AUTOCOLRESSTARTED
+ 14
+ 14
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ COLLISION
+ Enable or disable interrupt for event COLLISION
+ 18
+ 18
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ SELECTED
+ Enable or disable interrupt for event SELECTED
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ STARTED
+ Enable or disable interrupt for event STARTED
+ 20
+ 20
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ READY
+ Write '1' to enable interrupt for event READY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ FIELDDETECTED
+ Write '1' to enable interrupt for event FIELDDETECTED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ FIELDLOST
+ Write '1' to enable interrupt for event FIELDLOST
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXFRAMESTART
+ Write '1' to enable interrupt for event TXFRAMESTART
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXFRAMEEND
+ Write '1' to enable interrupt for event TXFRAMEEND
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXFRAMESTART
+ Write '1' to enable interrupt for event RXFRAMESTART
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXFRAMEEND
+ Write '1' to enable interrupt for event RXFRAMEEND
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to enable interrupt for event ERROR
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RXERROR
+ Write '1' to enable interrupt for event RXERROR
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to enable interrupt for event ENDRX
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDTX
+ Write '1' to enable interrupt for event ENDTX
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ AUTOCOLRESSTARTED
+ Write '1' to enable interrupt for event AUTOCOLRESSTARTED
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COLLISION
+ Write '1' to enable interrupt for event COLLISION
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SELECTED
+ Write '1' to enable interrupt for event SELECTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ STARTED
+ Write '1' to enable interrupt for event STARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ READY
+ Write '1' to disable interrupt for event READY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ FIELDDETECTED
+ Write '1' to disable interrupt for event FIELDDETECTED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ FIELDLOST
+ Write '1' to disable interrupt for event FIELDLOST
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXFRAMESTART
+ Write '1' to disable interrupt for event TXFRAMESTART
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXFRAMEEND
+ Write '1' to disable interrupt for event TXFRAMEEND
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXFRAMESTART
+ Write '1' to disable interrupt for event RXFRAMESTART
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXFRAMEEND
+ Write '1' to disable interrupt for event RXFRAMEEND
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Write '1' to disable interrupt for event ERROR
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RXERROR
+ Write '1' to disable interrupt for event RXERROR
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDRX
+ Write '1' to disable interrupt for event ENDRX
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDTX
+ Write '1' to disable interrupt for event ENDTX
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ AUTOCOLRESSTARTED
+ Write '1' to disable interrupt for event AUTOCOLRESSTARTED
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COLLISION
+ Write '1' to disable interrupt for event COLLISION
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SELECTED
+ Write '1' to disable interrupt for event SELECTED
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ STARTED
+ Write '1' to disable interrupt for event STARTED
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ERRORSTATUS
+ NFC Error Status register
+ 0x404
+ read-write
+ oneToClear
+
+
+ FRAMEDELAYTIMEOUT
+ No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX
+ 0
+ 0
+
+
+
+
+ FRAMESTATUS
+ Unspecified
+ NFCT_FRAMESTATUS
+ read-write
+ 0x40C
+
+ RX
+ Result of last incoming frame
+ 0x000
+ read-write
+ oneToClear
+
+
+ CRCERROR
+ No valid end of frame (EoF) detected
+ 0
+ 0
+
+
+ CRCCorrect
+ Valid CRC detected
+ 0
+
+
+ CRCError
+ CRC received does not match local check
+ 1
+
+
+
+
+ PARITYSTATUS
+ Parity status of received frame
+ 2
+ 2
+
+
+ ParityOK
+ Frame received with parity OK
+ 0
+
+
+ ParityError
+ Frame received with parity error
+ 1
+
+
+
+
+ OVERRUN
+ Overrun detected
+ 3
+ 3
+
+
+ NoOverrun
+ No overrun detected
+ 0
+
+
+ Overrun
+ Overrun error
+ 1
+
+
+
+
+
+
+
+ NFCTAGSTATE
+ NfcTag state register
+ 0x410
+ read-only
+
+
+ NFCTAGSTATE
+ NfcTag state
+ 0
+ 2
+
+
+ Disabled
+ Disabled or sense
+ 0
+
+
+ RampUp
+ RampUp
+ 2
+
+
+ Idle
+ Idle
+ 3
+
+
+ Receive
+ Receive
+ 4
+
+
+ FrameDelay
+ FrameDelay
+ 5
+
+
+ Transmit
+ Transmit
+ 6
+
+
+
+
+
+
+ SLEEPSTATE
+ Sleep state during automatic collision resolution
+ 0x420
+ read-only
+ 0x00000000
+
+
+ SLEEPSTATE
+ Reflects the sleep state during automatic collision resolution. Set to IDLE
+ by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a
+ GOSLEEP task.
+ 0
+ 0
+
+
+ Idle
+ State is IDLE.
+ 0
+
+
+ SleepA
+ State is SLEEP_A.
+ 1
+
+
+
+
+
+
+ FIELDPRESENT
+ Indicates the presence or not of a valid field
+ 0x43C
+ read-only
+
+
+ FIELDPRESENT
+ Indicates if a valid field is present. Available only in the activated state.
+ 0
+ 0
+
+
+ NoField
+ No valid field detected
+ 0
+
+
+ FieldPresent
+ Valid field detected
+ 1
+
+
+
+
+ LOCKDETECT
+ Indicates if the low level has locked to the field
+ 1
+ 1
+
+
+ NotLocked
+ Not locked to field
+ 0
+
+
+ Locked
+ Locked to field
+ 1
+
+
+
+
+
+
+ FRAMEDELAYMIN
+ Minimum frame delay
+ 0x504
+ read-write
+ 0x00000480
+
+
+ FRAMEDELAYMIN
+ Minimum frame delay in number of 13.56 MHz clocks
+ 0
+ 15
+
+
+
+
+ FRAMEDELAYMAX
+ Maximum frame delay
+ 0x508
+ read-write
+ 0x00001000
+
+
+ FRAMEDELAYMAX
+ Maximum frame delay in number of 13.56 MHz clocks
+ 0
+ 19
+
+
+
+
+ FRAMEDELAYMODE
+ Configuration register for the Frame Delay Timer
+ 0x50C
+ read-write
+ 0x00000001
+
+
+ FRAMEDELAYMODE
+ Configuration register for the Frame Delay Timer
+ 0
+ 1
+
+
+ FreeRun
+ Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.
+ 0
+
+
+ Window
+ Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX
+ 1
+
+
+ ExactVal
+ Frame is transmitted exactly at FRAMEDELAYMAX
+ 2
+
+
+ WindowGrid
+ Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX
+ 3
+
+
+
+
+
+
+ PACKETPTR
+ Packet pointer for TXD and RXD data storage in Data RAM
+ 0x510
+ read-write
+ 0x00000000
+
+
+ PTR
+ Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address.
+ 0
+ 31
+
+
+
+
+ MAXLEN
+ Size of the RAM buffer allocated to TXD and RXD data storage each
+ 0x514
+ read-write
+
+
+ MAXLEN
+ Size of the RAM buffer allocated to TXD and RXD data storage each
+ 0
+ 8
+
+
+
+
+ TXD
+ Unspecified
+ NFCT_TXD
+ read-write
+ 0x518
+
+ FRAMECONFIG
+ Configuration of outgoing frames
+ 0x000
+ read-write
+ 0x00000017
+
+
+ PARITY
+ Indicates if parity is added to the frame
+ 0
+ 0
+
+
+ NoParity
+ Parity is not added to TX frames
+ 0
+
+
+ Parity
+ Parity is added to TX frames
+ 1
+
+
+
+
+ DISCARDMODE
+ Discarding unused bits at start or end of a frame
+ 1
+ 1
+
+
+ DiscardEnd
+ Unused bits are discarded at end of frame (EoF)
+ 0
+
+
+ DiscardStart
+ Unused bits are discarded at start of frame (SoF)
+ 1
+
+
+
+
+ SOF
+ Adding SoF or not in TX frames
+ 2
+ 2
+
+
+ NoSoF
+ SoF symbol not added
+ 0
+
+
+ SoF
+ SoF symbol added
+ 1
+
+
+
+
+ CRCMODETX
+ CRC mode for outgoing frames
+ 4
+ 4
+
+
+ NoCRCTX
+ CRC is not added to the frame
+ 0
+
+
+ CRC16TX
+ 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame
+ 1
+
+
+
+
+
+
+ AMOUNT
+ Size of outgoing frame
+ 0x004
+ read-write
+
+
+ TXDATABITS
+ Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit).
+ 0
+ 2
+
+
+ TXDATABYTES
+ Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing
+ 3
+ 11
+
+
+
+
+
+ RXD
+ Unspecified
+ NFCT_RXD
+ read-write
+ 0x520
+
+ FRAMECONFIG
+ Configuration of incoming frames
+ 0x000
+ read-write
+ 0x00000015
+
+
+ PARITY
+ Indicates if parity expected in RX frame
+ 0
+ 0
+
+
+ NoParity
+ Parity is not expected in RX frames
+ 0
+
+
+ Parity
+ Parity is expected in RX frames
+ 1
+
+
+
+
+ SOF
+ SoF expected or not in RX frames
+ 2
+ 2
+
+
+ NoSoF
+ SoF symbol is not expected in RX frames
+ 0
+
+
+ SoF
+ SoF symbol is expected in RX frames
+ 1
+
+
+
+
+ CRCMODERX
+ CRC mode for incoming frames
+ 4
+ 4
+
+
+ NoCRCRX
+ CRC is not expected in RX frames
+ 0
+
+
+ CRC16RX
+ Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated
+ 1
+
+
+
+
+
+
+ AMOUNT
+ Size of last incoming frame
+ 0x004
+ read-only
+
+
+ RXDATABITS
+ Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing).
+ 0
+ 2
+
+
+ RXDATABYTES
+ Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing)
+ 3
+ 11
+
+
+
+
+
+ MODULATIONCTRL
+ Enables the modulation output to a GPIO pin which can be connected to a second external antenna.
+ 0x52C
+ read-write
+ 0x00000001
+
+
+ MODULATIONCTRL
+ Configuration of modulation control.
+ 0
+ 1
+
+
+ Invalid
+ Invalid, defaults to same behaviour as for Internal
+ 0x0
+
+
+ Internal
+ Use internal modulator only
+ 0x1
+
+
+ ModToGpio
+ Output digital modulation signal to a GPIO pin.
+ 0x2
+
+
+ InternalAndModToGpio
+ Use internal modulator and output digital modulation signal to a GPIO pin.
+ 0x3
+
+
+
+
+
+
+ MODULATIONPSEL
+ Pin select for Modulation control.
+ 0x538
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ NFCID1_LAST
+ Last NFCID1 part (4, 7 or 10 bytes ID)
+ 0x590
+ read-write
+ 0x00006363
+
+
+ NFCID1_Z
+ NFCID1 byte Z (very last byte sent)
+ 0
+ 7
+
+
+ NFCID1_Y
+ NFCID1 byte Y
+ 8
+ 15
+
+
+ NFCID1_X
+ NFCID1 byte X
+ 16
+ 23
+
+
+ NFCID1_W
+ NFCID1 byte W
+ 24
+ 31
+
+
+
+
+ NFCID1_2ND_LAST
+ Second last NFCID1 part (7 or 10 bytes ID)
+ 0x594
+ read-write
+
+
+ NFCID1_V
+ NFCID1 byte V
+ 0
+ 7
+
+
+ NFCID1_U
+ NFCID1 byte U
+ 8
+ 15
+
+
+ NFCID1_T
+ NFCID1 byte T
+ 16
+ 23
+
+
+
+
+ NFCID1_3RD_LAST
+ Third last NFCID1 part (10 bytes ID)
+ 0x598
+ read-write
+
+
+ NFCID1_S
+ NFCID1 byte S
+ 0
+ 7
+
+
+ NFCID1_R
+ NFCID1 byte R
+ 8
+ 15
+
+
+ NFCID1_Q
+ NFCID1 byte Q
+ 16
+ 23
+
+
+
+
+ AUTOCOLRESCONFIG
+ Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated.
+ 0x59C
+ read-write
+ 0x00000002
+
+
+ MODE
+ Enables/disables auto collision resolution
+ 0
+ 0
+
+
+ Enabled
+ Auto collision resolution enabled
+ 0
+
+
+ Disabled
+ Auto collision resolution disabled
+ 1
+
+
+
+
+
+
+ SENSRES
+ NFC-A SENS_RES auto-response settings
+ 0x5A0
+ read-write
+ 0x00000001
+
+
+ BITFRAMESDD
+ Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
+ 0
+ 4
+
+
+ SDD00000
+ SDD pattern 00000
+ 0
+
+
+ SDD00001
+ SDD pattern 00001
+ 1
+
+
+ SDD00010
+ SDD pattern 00010
+ 2
+
+
+ SDD00100
+ SDD pattern 00100
+ 4
+
+
+ SDD01000
+ SDD pattern 01000
+ 8
+
+
+ SDD10000
+ SDD pattern 10000
+ 16
+
+
+
+
+ RFU5
+ Reserved for future use. Shall be 0.
+ 5
+ 5
+
+
+ NFCIDSIZE
+ NFCID1 size. This value is used by the auto collision resolution engine.
+ 6
+ 7
+
+
+ NFCID1Single
+ NFCID1 size: single (4 bytes)
+ 0
+
+
+ NFCID1Double
+ NFCID1 size: double (7 bytes)
+ 1
+
+
+ NFCID1Triple
+ NFCID1 size: triple (10 bytes)
+ 2
+
+
+
+
+ PLATFCONFIG
+ Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
+ 8
+ 11
+
+
+ RFU74
+ Reserved for future use. Shall be 0.
+ 12
+ 15
+
+
+
+
+ SELRES
+ NFC-A SEL_RES auto-response settings
+ 0x5A4
+ read-write
+
+
+ RFU10
+ Reserved for future use. Shall be 0.
+ 0
+ 1
+
+
+ CASCADE
+ Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0)
+ 2
+ 2
+
+
+ RFU43
+ Reserved for future use. Shall be 0.
+ 3
+ 4
+
+
+ PROTOCOL
+ Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
+ 5
+ 6
+
+
+ RFU7
+ Reserved for future use. Shall be 0.
+ 7
+ 7
+
+
+
+
+
+
+ GPIOTE
+ GPIO Tasks and Events
+ 0x40006000
+
+ 0
+ 0x1000
+ registers
+
+
+ GPIOTE
+ 6
+
+ GPIOTE
+ 0x20
+
+
+ 0x8
+ 0x4
+ TASKS_OUT[%s]
+ Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
+ 0x000
+ write-only
+
+
+ TASKS_OUT
+ Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ TASKS_SET[%s]
+ Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
+ 0x030
+ write-only
+
+
+ TASKS_SET
+ Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ TASKS_CLR[%s]
+ Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
+ 0x060
+ write-only
+
+
+ TASKS_CLR
+ Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ EVENTS_IN[%s]
+ Description collection: Event generated from pin specified in CONFIG[n].PSEL
+ 0x100
+ read-write
+
+
+ EVENTS_IN
+ Event generated from pin specified in CONFIG[n].PSEL
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_PORT
+ Event generated from multiple input GPIO pins with SENSE mechanism enabled
+ 0x17C
+ read-write
+
+
+ EVENTS_PORT
+ Event generated from multiple input GPIO pins with SENSE mechanism enabled
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ IN0
+ Write '1' to enable interrupt for event IN[0]
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN1
+ Write '1' to enable interrupt for event IN[1]
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN2
+ Write '1' to enable interrupt for event IN[2]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN3
+ Write '1' to enable interrupt for event IN[3]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN4
+ Write '1' to enable interrupt for event IN[4]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN5
+ Write '1' to enable interrupt for event IN[5]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN6
+ Write '1' to enable interrupt for event IN[6]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ IN7
+ Write '1' to enable interrupt for event IN[7]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PORT
+ Write '1' to enable interrupt for event PORT
+ 31
+ 31
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ IN0
+ Write '1' to disable interrupt for event IN[0]
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN1
+ Write '1' to disable interrupt for event IN[1]
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN2
+ Write '1' to disable interrupt for event IN[2]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN3
+ Write '1' to disable interrupt for event IN[3]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN4
+ Write '1' to disable interrupt for event IN[4]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN5
+ Write '1' to disable interrupt for event IN[5]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN6
+ Write '1' to disable interrupt for event IN[6]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ IN7
+ Write '1' to disable interrupt for event IN[7]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PORT
+ Write '1' to disable interrupt for event PORT
+ 31
+ 31
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ CONFIG[%s]
+ Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
+ 0x510
+ read-write
+
+
+ MODE
+ Mode
+ 0
+ 1
+
+
+ Disabled
+ Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.
+ 0
+
+
+ Event
+ Event mode
+ 1
+
+
+ Task
+ Task mode
+ 3
+
+
+
+
+ PSEL
+ GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event
+ 8
+ 12
+
+
+ PORT
+ Port number
+ 13
+ 13
+
+
+ POLARITY
+ When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
+ 16
+ 17
+
+
+ None
+ Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.
+ 0
+
+
+ LoToHi
+ Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.
+ 1
+
+
+ HiToLo
+ Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.
+ 2
+
+
+ Toggle
+ Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.
+ 3
+
+
+
+
+ OUTINIT
+ When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
+ 20
+ 20
+
+
+ Low
+ Task mode: Initial value of pin before task triggering is low
+ 0
+
+
+ High
+ Task mode: Initial value of pin before task triggering is high
+ 1
+
+
+
+
+
+
+
+
+ SAADC
+ Successive approximation register (SAR) analog-to-digital converter
+ 0x40007000
+
+ 0
+ 0x1000
+ registers
+
+
+ SAADC
+ 7
+
+ SAADC
+ 0x20
+
+
+ TASKS_START
+ Starts the SAADC and prepares the result buffer in RAM
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Starts the SAADC and prepares the result buffer in RAM
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SAMPLE
+ Takes one SAADC sample
+ 0x004
+ write-only
+
+
+ TASKS_SAMPLE
+ Takes one SAADC sample
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stops the SAADC and terminates all on-going conversions
+ 0x008
+ write-only
+
+
+ TASKS_STOP
+ Stops the SAADC and terminates all on-going conversions
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CALIBRATEOFFSET
+ Starts offset auto-calibration
+ 0x00C
+ write-only
+
+
+ TASKS_CALIBRATEOFFSET
+ Starts offset auto-calibration
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STARTED
+ The SAADC has started
+ 0x100
+ read-write
+
+
+ EVENTS_STARTED
+ The SAADC has started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ The SAADC has filled up the result buffer
+ 0x104
+ read-write
+
+
+ EVENTS_END
+ The SAADC has filled up the result buffer
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DONE
+ A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.
+ 0x108
+ read-write
+
+
+ EVENTS_DONE
+ A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RESULTDONE
+ Result ready for transfer to RAM
+ 0x10C
+ read-write
+
+
+ EVENTS_RESULTDONE
+ Result ready for transfer to RAM
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CALIBRATEDONE
+ Calibration is complete
+ 0x110
+ read-write
+
+
+ EVENTS_CALIBRATEDONE
+ Calibration is complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ The SAADC has stopped
+ 0x114
+ read-write
+
+
+ EVENTS_STOPPED
+ The SAADC has stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ 8
+ 0x008
+ EVENTS_CH[%s]
+ Peripheral events.
+ SAADC_EVENTS_CH
+ read-write
+ 0x118
+
+ LIMITH
+ Description cluster: Last result is equal or above CH[n].LIMIT.HIGH
+ 0x000
+ read-write
+
+
+ LIMITH
+ Last result is equal or above CH[n].LIMIT.HIGH
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ LIMITL
+ Description cluster: Last result is equal or below CH[n].LIMIT.LOW
+ 0x004
+ read-write
+
+
+ LIMITL
+ Last result is equal or below CH[n].LIMIT.LOW
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ STARTED
+ Enable or disable interrupt for event STARTED
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ END
+ Enable or disable interrupt for event END
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ DONE
+ Enable or disable interrupt for event DONE
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ RESULTDONE
+ Enable or disable interrupt for event RESULTDONE
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CALIBRATEDONE
+ Enable or disable interrupt for event CALIBRATEDONE
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ STOPPED
+ Enable or disable interrupt for event STOPPED
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH0LIMITH
+ Enable or disable interrupt for event CH0LIMITH
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH0LIMITL
+ Enable or disable interrupt for event CH0LIMITL
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH1LIMITH
+ Enable or disable interrupt for event CH1LIMITH
+ 8
+ 8
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH1LIMITL
+ Enable or disable interrupt for event CH1LIMITL
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH2LIMITH
+ Enable or disable interrupt for event CH2LIMITH
+ 10
+ 10
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH2LIMITL
+ Enable or disable interrupt for event CH2LIMITL
+ 11
+ 11
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH3LIMITH
+ Enable or disable interrupt for event CH3LIMITH
+ 12
+ 12
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH3LIMITL
+ Enable or disable interrupt for event CH3LIMITL
+ 13
+ 13
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH4LIMITH
+ Enable or disable interrupt for event CH4LIMITH
+ 14
+ 14
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH4LIMITL
+ Enable or disable interrupt for event CH4LIMITL
+ 15
+ 15
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH5LIMITH
+ Enable or disable interrupt for event CH5LIMITH
+ 16
+ 16
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH5LIMITL
+ Enable or disable interrupt for event CH5LIMITL
+ 17
+ 17
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH6LIMITH
+ Enable or disable interrupt for event CH6LIMITH
+ 18
+ 18
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH6LIMITL
+ Enable or disable interrupt for event CH6LIMITL
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH7LIMITH
+ Enable or disable interrupt for event CH7LIMITH
+ 20
+ 20
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CH7LIMITL
+ Enable or disable interrupt for event CH7LIMITL
+ 21
+ 21
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STARTED
+ Write '1' to enable interrupt for event STARTED
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DONE
+ Write '1' to enable interrupt for event DONE
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RESULTDONE
+ Write '1' to enable interrupt for event RESULTDONE
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CALIBRATEDONE
+ Write '1' to enable interrupt for event CALIBRATEDONE
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH0LIMITH
+ Write '1' to enable interrupt for event CH0LIMITH
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH0LIMITL
+ Write '1' to enable interrupt for event CH0LIMITL
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH1LIMITH
+ Write '1' to enable interrupt for event CH1LIMITH
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH1LIMITL
+ Write '1' to enable interrupt for event CH1LIMITL
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH2LIMITH
+ Write '1' to enable interrupt for event CH2LIMITH
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH2LIMITL
+ Write '1' to enable interrupt for event CH2LIMITL
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH3LIMITH
+ Write '1' to enable interrupt for event CH3LIMITH
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH3LIMITL
+ Write '1' to enable interrupt for event CH3LIMITL
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH4LIMITH
+ Write '1' to enable interrupt for event CH4LIMITH
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH4LIMITL
+ Write '1' to enable interrupt for event CH4LIMITL
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH5LIMITH
+ Write '1' to enable interrupt for event CH5LIMITH
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH5LIMITL
+ Write '1' to enable interrupt for event CH5LIMITL
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH6LIMITH
+ Write '1' to enable interrupt for event CH6LIMITH
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH6LIMITL
+ Write '1' to enable interrupt for event CH6LIMITL
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH7LIMITH
+ Write '1' to enable interrupt for event CH7LIMITH
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CH7LIMITL
+ Write '1' to enable interrupt for event CH7LIMITL
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STARTED
+ Write '1' to disable interrupt for event STARTED
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DONE
+ Write '1' to disable interrupt for event DONE
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RESULTDONE
+ Write '1' to disable interrupt for event RESULTDONE
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CALIBRATEDONE
+ Write '1' to disable interrupt for event CALIBRATEDONE
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH0LIMITH
+ Write '1' to disable interrupt for event CH0LIMITH
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH0LIMITL
+ Write '1' to disable interrupt for event CH0LIMITL
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH1LIMITH
+ Write '1' to disable interrupt for event CH1LIMITH
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH1LIMITL
+ Write '1' to disable interrupt for event CH1LIMITL
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH2LIMITH
+ Write '1' to disable interrupt for event CH2LIMITH
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH2LIMITL
+ Write '1' to disable interrupt for event CH2LIMITL
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH3LIMITH
+ Write '1' to disable interrupt for event CH3LIMITH
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH3LIMITL
+ Write '1' to disable interrupt for event CH3LIMITL
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH4LIMITH
+ Write '1' to disable interrupt for event CH4LIMITH
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH4LIMITL
+ Write '1' to disable interrupt for event CH4LIMITL
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH5LIMITH
+ Write '1' to disable interrupt for event CH5LIMITH
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH5LIMITL
+ Write '1' to disable interrupt for event CH5LIMITL
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH6LIMITH
+ Write '1' to disable interrupt for event CH6LIMITH
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH6LIMITL
+ Write '1' to disable interrupt for event CH6LIMITL
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH7LIMITH
+ Write '1' to disable interrupt for event CH7LIMITH
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CH7LIMITL
+ Write '1' to disable interrupt for event CH7LIMITL
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ STATUS
+ Status
+ 0x400
+ read-only
+
+
+ STATUS
+ Status
+ 0
+ 0
+
+
+ Ready
+ SAADC is ready. No on-going conversions.
+ 0
+
+
+ Busy
+ SAADC is busy. Conversion in progress.
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable or disable SAADC
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable SAADC
+ 0
+ 0
+
+
+ Disabled
+ Disable SAADC
+ 0
+
+
+ Enabled
+ Enable SAADC
+ 1
+
+
+
+
+
+
+ 8
+ 0x010
+ CH[%s]
+ Unspecified
+ SAADC_CH
+ read-write
+ 0x510
+
+ PSELP
+ Description cluster: Input positive pin selection for CH[n]
+ 0x000
+ read-write
+ 0x00000000
+
+
+ PSELP
+ Analog positive input channel
+ 0
+ 4
+
+
+ NC
+ Not connected
+ 0
+
+
+ AnalogInput0
+ AIN0
+ 1
+
+
+ AnalogInput1
+ AIN1
+ 2
+
+
+ AnalogInput2
+ AIN2
+ 3
+
+
+ AnalogInput3
+ AIN3
+ 4
+
+
+ AnalogInput4
+ AIN4
+ 5
+
+
+ AnalogInput5
+ AIN5
+ 6
+
+
+ AnalogInput6
+ AIN6
+ 7
+
+
+ AnalogInput7
+ AIN7
+ 8
+
+
+ VDD
+ VDD
+ 9
+
+
+ VDDHDIV5
+ VDDH/5
+ 0x0D
+
+
+
+
+
+
+ PSELN
+ Description cluster: Input negative pin selection for CH[n]
+ 0x004
+ read-write
+ 0x00000000
+
+
+ PSELN
+ Analog negative input, enables differential channel
+ 0
+ 4
+
+
+ NC
+ Not connected
+ 0
+
+
+ AnalogInput0
+ AIN0
+ 1
+
+
+ AnalogInput1
+ AIN1
+ 2
+
+
+ AnalogInput2
+ AIN2
+ 3
+
+
+ AnalogInput3
+ AIN3
+ 4
+
+
+ AnalogInput4
+ AIN4
+ 5
+
+
+ AnalogInput5
+ AIN5
+ 6
+
+
+ AnalogInput6
+ AIN6
+ 7
+
+
+ AnalogInput7
+ AIN7
+ 8
+
+
+ VDD
+ VDD
+ 9
+
+
+ VDDHDIV5
+ VDDH/5
+ 0x0D
+
+
+
+
+
+
+ CONFIG
+ Description cluster: Input configuration for CH[n]
+ 0x008
+ read-write
+ 0x00020000
+
+
+ RESP
+ Positive channel resistor control
+ 0
+ 1
+
+
+ Bypass
+ Bypass resistor ladder
+ 0
+
+
+ Pulldown
+ Pull-down to GND
+ 1
+
+
+ Pullup
+ Pull-up to VDD
+ 2
+
+
+ VDD1_2
+ Set input at VDD/2
+ 3
+
+
+
+
+ RESN
+ Negative channel resistor control
+ 4
+ 5
+
+
+ Bypass
+ Bypass resistor ladder
+ 0
+
+
+ Pulldown
+ Pull-down to GND
+ 1
+
+
+ Pullup
+ Pull-up to VDD
+ 2
+
+
+ VDD1_2
+ Set input at VDD/2
+ 3
+
+
+
+
+ GAIN
+ Gain control
+ 8
+ 10
+
+
+ Gain1_6
+ 1/6
+ 0
+
+
+ Gain1_5
+ 1/5
+ 1
+
+
+ Gain1_4
+ 1/4
+ 2
+
+
+ Gain1_3
+ 1/3
+ 3
+
+
+ Gain1_2
+ 1/2
+ 4
+
+
+ Gain1
+ 1
+ 5
+
+
+ Gain2
+ 2
+ 6
+
+
+ Gain4
+ 4
+ 7
+
+
+
+
+ REFSEL
+ Reference control
+ 12
+ 12
+
+
+ Internal
+ Internal reference (0.6 V)
+ 0
+
+
+ VDD1_4
+ VDD/4 as reference
+ 1
+
+
+
+
+ TACQ
+ Acquisition time, the time the SAADC uses to sample the input voltage
+ 16
+ 18
+
+
+ 3us
+ 3 us
+ 0
+
+
+ 5us
+ 5 us
+ 1
+
+
+ 10us
+ 10 us
+ 2
+
+
+ 15us
+ 15 us
+ 3
+
+
+ 20us
+ 20 us
+ 4
+
+
+ 40us
+ 40 us
+ 5
+
+
+
+
+ MODE
+ Enable differential mode
+ 20
+ 20
+
+
+ SE
+ Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND
+ 0
+
+
+ Diff
+ Differential
+ 1
+
+
+
+
+ BURST
+ Enable burst mode
+ 24
+ 24
+
+
+ Disabled
+ Burst mode is disabled (normal operation)
+ 0
+
+
+ Enabled
+ Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.
+ 1
+
+
+
+
+
+
+ LIMIT
+ Description cluster: High/low limits for event monitoring of a channel
+ 0x00C
+ read-write
+ 0x7FFF8000
+
+
+ LOW
+ Low level limit
+ 0
+ 15
+
+
+ HIGH
+ High level limit
+ 16
+ 31
+
+
+
+
+
+ RESOLUTION
+ Resolution configuration
+ 0x5F0
+ read-write
+ 0x00000001
+
+
+ VAL
+ Set the resolution
+ 0
+ 2
+
+
+ 8bit
+ 8 bits
+ 0
+
+
+ 10bit
+ 10 bits
+ 1
+
+
+ 12bit
+ 12 bits
+ 2
+
+
+ 14bit
+ 14 bits
+ 3
+
+
+
+
+
+
+ OVERSAMPLE
+ Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
+ 0x5F4
+ read-write
+
+
+ OVERSAMPLE
+ Oversample control
+ 0
+ 3
+
+
+ Bypass
+ Bypass oversampling
+ 0
+
+
+ Over2x
+ Oversample 2x
+ 1
+
+
+ Over4x
+ Oversample 4x
+ 2
+
+
+ Over8x
+ Oversample 8x
+ 3
+
+
+ Over16x
+ Oversample 16x
+ 4
+
+
+ Over32x
+ Oversample 32x
+ 5
+
+
+ Over64x
+ Oversample 64x
+ 6
+
+
+ Over128x
+ Oversample 128x
+ 7
+
+
+ Over256x
+ Oversample 256x
+ 8
+
+
+
+
+
+
+ SAMPLERATE
+ Controls normal or continuous sample rate
+ 0x5F8
+ read-write
+
+
+ CC
+ Capture and compare value. Sample rate is 16 MHz/CC
+ 0
+ 10
+
+
+ MODE
+ Select mode for sample rate control
+ 12
+ 12
+
+
+ Task
+ Rate is controlled from SAMPLE task
+ 0
+
+
+ Timers
+ Rate is controlled from local timer (use CC to control the rate)
+ 1
+
+
+
+
+
+
+ RESULT
+ RESULT EasyDMA channel
+ SAADC_RESULT
+ read-write
+ 0x62C
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of 16-bit samples to be written to output RAM buffer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of 16-bit samples to be written to output RAM buffer
+ 0
+ 14
+
+
+
+
+ AMOUNT
+ Number of 16-bit samples written to output RAM buffer since the previous START task
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event.
+ 0
+ 14
+
+
+
+
+
+
+
+ TIMER0
+ Timer/Counter 0
+ 0x40008000
+ TIMER
+
+ 0
+ 0x1000
+ registers
+
+
+ TIMER0
+ 8
+
+ TIMER
+ 0x20
+
+
+ TASKS_START
+ Start Timer
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start Timer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop Timer
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stop Timer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_COUNT
+ Increment Timer (Counter mode only)
+ 0x008
+ write-only
+
+
+ TASKS_COUNT
+ Increment Timer (Counter mode only)
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CLEAR
+ Clear time
+ 0x00C
+ write-only
+
+
+ TASKS_CLEAR
+ Clear time
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SHUTDOWN
+ Deprecated register - Shut down timer
+ 0x010
+ write-only
+
+
+ TASKS_SHUTDOWN
+ Deprecated field - Shut down timer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x6
+ 0x4
+ TASKS_CAPTURE[%s]
+ Description collection: Capture Timer value to CC[n] register
+ 0x040
+ write-only
+
+
+ TASKS_CAPTURE
+ Capture Timer value to CC[n] register
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x6
+ 0x4
+ EVENTS_COMPARE[%s]
+ Description collection: Compare event on CC[n] match
+ 0x140
+ read-write
+
+
+ EVENTS_COMPARE
+ Compare event on CC[n] match
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ COMPARE0_CLEAR
+ Shortcut between event COMPARE[0] and task CLEAR
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE1_CLEAR
+ Shortcut between event COMPARE[1] and task CLEAR
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE2_CLEAR
+ Shortcut between event COMPARE[2] and task CLEAR
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE3_CLEAR
+ Shortcut between event COMPARE[3] and task CLEAR
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE4_CLEAR
+ Shortcut between event COMPARE[4] and task CLEAR
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE5_CLEAR
+ Shortcut between event COMPARE[5] and task CLEAR
+ 5
+ 5
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE0_STOP
+ Shortcut between event COMPARE[0] and task STOP
+ 8
+ 8
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE1_STOP
+ Shortcut between event COMPARE[1] and task STOP
+ 9
+ 9
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE2_STOP
+ Shortcut between event COMPARE[2] and task STOP
+ 10
+ 10
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE3_STOP
+ Shortcut between event COMPARE[3] and task STOP
+ 11
+ 11
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE4_STOP
+ Shortcut between event COMPARE[4] and task STOP
+ 12
+ 12
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ COMPARE5_STOP
+ Shortcut between event COMPARE[5] and task STOP
+ 13
+ 13
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ COMPARE0
+ Write '1' to enable interrupt for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to enable interrupt for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to enable interrupt for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to enable interrupt for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE4
+ Write '1' to enable interrupt for event COMPARE[4]
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE5
+ Write '1' to enable interrupt for event COMPARE[5]
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ COMPARE0
+ Write '1' to disable interrupt for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to disable interrupt for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to disable interrupt for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to disable interrupt for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE4
+ Write '1' to disable interrupt for event COMPARE[4]
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE5
+ Write '1' to disable interrupt for event COMPARE[5]
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ MODE
+ Timer mode selection
+ 0x504
+ read-write
+
+
+ MODE
+ Timer mode
+ 0
+ 1
+
+
+ Timer
+ Select Timer mode
+ 0
+
+
+ Counter
+ Deprecated enumerator - Select Counter mode
+ 1
+
+
+ LowPowerCounter
+ Select Low Power Counter mode
+ 2
+
+
+
+
+
+
+ BITMODE
+ Configure the number of bits used by the TIMER
+ 0x508
+ read-write
+
+
+ BITMODE
+ Timer bit width
+ 0
+ 1
+
+
+ 16Bit
+ 16 bit timer bit width
+ 0
+
+
+ 08Bit
+ 8 bit timer bit width
+ 1
+
+
+ 24Bit
+ 24 bit timer bit width
+ 2
+
+
+ 32Bit
+ 32 bit timer bit width
+ 3
+
+
+
+
+
+
+ PRESCALER
+ Timer prescaler register
+ 0x510
+ read-write
+ 0x00000004
+
+
+ PRESCALER
+ Prescaler value
+ 0
+ 3
+
+
+
+
+ 0x6
+ 0x4
+ CC[%s]
+ Description collection: Capture/Compare register n
+ 0x540
+ read-write
+
+
+ CC
+ Capture/Compare value
+ 0
+ 31
+
+
+
+
+
+
+ TIMER1
+ Timer/Counter 1
+ 0x40009000
+
+ TIMER1
+ 9
+
+
+
+ TIMER2
+ Timer/Counter 2
+ 0x4000A000
+
+ TIMER2
+ 10
+
+
+
+ RTC0
+ Real time counter 0
+ 0x4000B000
+ RTC
+
+ 0
+ 0x1000
+ registers
+
+
+ RTC0
+ 11
+
+ RTC
+ 0x20
+
+
+ TASKS_START
+ Start RTC COUNTER
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start RTC COUNTER
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop RTC COUNTER
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stop RTC COUNTER
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CLEAR
+ Clear RTC COUNTER
+ 0x008
+ write-only
+
+
+ TASKS_CLEAR
+ Clear RTC COUNTER
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_TRIGOVRFLW
+ Set COUNTER to 0xFFFFF0
+ 0x00C
+ write-only
+
+
+ TASKS_TRIGOVRFLW
+ Set COUNTER to 0xFFFFF0
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_TICK
+ Event on COUNTER increment
+ 0x100
+ read-write
+
+
+ EVENTS_TICK
+ Event on COUNTER increment
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_OVRFLW
+ Event on COUNTER overflow
+ 0x104
+ read-write
+
+
+ EVENTS_OVRFLW
+ Event on COUNTER overflow
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ 0x4
+ 0x4
+ EVENTS_COMPARE[%s]
+ Description collection: Compare event on CC[n] match
+ 0x140
+ read-write
+
+
+ EVENTS_COMPARE
+ Compare event on CC[n] match
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ TICK
+ Write '1' to enable interrupt for event TICK
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ OVRFLW
+ Write '1' to enable interrupt for event OVRFLW
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE0
+ Write '1' to enable interrupt for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to enable interrupt for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to enable interrupt for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to enable interrupt for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ TICK
+ Write '1' to disable interrupt for event TICK
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ OVRFLW
+ Write '1' to disable interrupt for event OVRFLW
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE0
+ Write '1' to disable interrupt for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to disable interrupt for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to disable interrupt for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to disable interrupt for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ EVTEN
+ Enable or disable event routing
+ 0x340
+ read-write
+
+
+ TICK
+ Enable or disable event routing for event TICK
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+ OVRFLW
+ Enable or disable event routing for event OVRFLW
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+ COMPARE0
+ Enable or disable event routing for event COMPARE[0]
+ 16
+ 16
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+ COMPARE1
+ Enable or disable event routing for event COMPARE[1]
+ 17
+ 17
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+ COMPARE2
+ Enable or disable event routing for event COMPARE[2]
+ 18
+ 18
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+ COMPARE3
+ Enable or disable event routing for event COMPARE[3]
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Disable
+ 1
+
+
+
+
+
+
+ EVTENSET
+ Enable event routing
+ 0x344
+ read-write
+
+
+ TICK
+ Write '1' to enable event routing for event TICK
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ OVRFLW
+ Write '1' to enable event routing for event OVRFLW
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE0
+ Write '1' to enable event routing for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to enable event routing for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to enable event routing for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to enable event routing for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ EVTENCLR
+ Disable event routing
+ 0x348
+ read-write
+
+
+ TICK
+ Write '1' to disable event routing for event TICK
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ OVRFLW
+ Write '1' to disable event routing for event OVRFLW
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE0
+ Write '1' to disable event routing for event COMPARE[0]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE1
+ Write '1' to disable event routing for event COMPARE[1]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE2
+ Write '1' to disable event routing for event COMPARE[2]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ COMPARE3
+ Write '1' to disable event routing for event COMPARE[3]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ COUNTER
+ Current COUNTER value
+ 0x504
+ read-only
+
+
+ COUNTER
+ Counter value
+ 0
+ 23
+
+
+
+
+ PRESCALER
+ 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped
+ 0x508
+ read-write
+
+
+ PRESCALER
+ Prescaler value
+ 0
+ 11
+
+
+
+
+ 0x4
+ 0x4
+ CC[%s]
+ Description collection: Compare register n
+ 0x540
+ read-write
+
+
+ COMPARE
+ Compare value
+ 0
+ 23
+
+
+
+
+
+
+ TEMP
+ Temperature Sensor
+ 0x4000C000
+
+ 0
+ 0x1000
+ registers
+
+
+ TEMP
+ 12
+
+ TEMP
+ 0x20
+
+
+ TASKS_START
+ Start temperature measurement
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start temperature measurement
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop temperature measurement
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stop temperature measurement
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_DATARDY
+ Temperature measurement complete, data ready
+ 0x100
+ read-write
+
+
+ EVENTS_DATARDY
+ Temperature measurement complete, data ready
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ DATARDY
+ Write '1' to enable interrupt for event DATARDY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ DATARDY
+ Write '1' to disable interrupt for event DATARDY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ TEMP
+ Temperature in degC (0.25deg steps)
+ 0x508
+ read-only
+ int32_t
+
+
+ TEMP
+ Temperature in degC (0.25deg steps)
+ 0
+ 31
+
+
+
+
+ A0
+ Slope of 1st piece wise linear function
+ 0x520
+ read-write
+ 0x00000326
+
+
+ A0
+ Slope of 1st piece wise linear function
+ 0
+ 11
+
+
+
+
+ A1
+ Slope of 2nd piece wise linear function
+ 0x524
+ read-write
+ 0x00000348
+
+
+ A1
+ Slope of 2nd piece wise linear function
+ 0
+ 11
+
+
+
+
+ A2
+ Slope of 3rd piece wise linear function
+ 0x528
+ read-write
+ 0x000003AA
+
+
+ A2
+ Slope of 3rd piece wise linear function
+ 0
+ 11
+
+
+
+
+ A3
+ Slope of 4th piece wise linear function
+ 0x52C
+ read-write
+ 0x0000040E
+
+
+ A3
+ Slope of 4th piece wise linear function
+ 0
+ 11
+
+
+
+
+ A4
+ Slope of 5th piece wise linear function
+ 0x530
+ read-write
+ 0x000004BD
+
+
+ A4
+ Slope of 5th piece wise linear function
+ 0
+ 11
+
+
+
+
+ A5
+ Slope of 6th piece wise linear function
+ 0x534
+ read-write
+ 0x000005A3
+
+
+ A5
+ Slope of 6th piece wise linear function
+ 0
+ 11
+
+
+
+
+ B0
+ y-intercept of 1st piece wise linear function
+ 0x540
+ read-write
+ 0x00003FEF
+
+
+ B0
+ y-intercept of 1st piece wise linear function
+ 0
+ 13
+
+
+
+
+ B1
+ y-intercept of 2nd piece wise linear function
+ 0x544
+ read-write
+ 0x00003FBE
+
+
+ B1
+ y-intercept of 2nd piece wise linear function
+ 0
+ 13
+
+
+
+
+ B2
+ y-intercept of 3rd piece wise linear function
+ 0x548
+ read-write
+ 0x00003FBE
+
+
+ B2
+ y-intercept of 3rd piece wise linear function
+ 0
+ 13
+
+
+
+
+ B3
+ y-intercept of 4th piece wise linear function
+ 0x54C
+ read-write
+ 0x00000012
+
+
+ B3
+ y-intercept of 4th piece wise linear function
+ 0
+ 13
+
+
+
+
+ B4
+ y-intercept of 5th piece wise linear function
+ 0x550
+ read-write
+ 0x00000124
+
+
+ B4
+ y-intercept of 5th piece wise linear function
+ 0
+ 13
+
+
+
+
+ B5
+ y-intercept of 6th piece wise linear function
+ 0x554
+ read-write
+ 0x0000027C
+
+
+ B5
+ y-intercept of 6th piece wise linear function
+ 0
+ 13
+
+
+
+
+ T0
+ End point of 1st piece wise linear function
+ 0x560
+ read-write
+ 0x000000E2
+
+
+ T0
+ End point of 1st piece wise linear function
+ 0
+ 7
+
+
+
+
+ T1
+ End point of 2nd piece wise linear function
+ 0x564
+ read-write
+ 0x00000000
+
+
+ T1
+ End point of 2nd piece wise linear function
+ 0
+ 7
+
+
+
+
+ T2
+ End point of 3rd piece wise linear function
+ 0x568
+ read-write
+ 0x00000019
+
+
+ T2
+ End point of 3rd piece wise linear function
+ 0
+ 7
+
+
+
+
+ T3
+ End point of 4th piece wise linear function
+ 0x56C
+ read-write
+ 0x0000003C
+
+
+ T3
+ End point of 4th piece wise linear function
+ 0
+ 7
+
+
+
+
+ T4
+ End point of 5th piece wise linear function
+ 0x570
+ read-write
+ 0x00000050
+
+
+ T4
+ End point of 5th piece wise linear function
+ 0
+ 7
+
+
+
+
+
+
+ RNG
+ Random Number Generator
+ 0x4000D000
+
+ 0
+ 0x1000
+ registers
+
+
+ RNG
+ 13
+
+ RNG
+ 0x20
+
+
+ TASKS_START
+ Task starting the random number generator
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Task starting the random number generator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Task stopping the random number generator
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Task stopping the random number generator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_VALRDY
+ Event being generated for every new random number written to the VALUE register
+ 0x100
+ read-write
+
+
+ EVENTS_VALRDY
+ Event being generated for every new random number written to the VALUE register
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ VALRDY_STOP
+ Shortcut between event VALRDY and task STOP
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ VALRDY
+ Write '1' to enable interrupt for event VALRDY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ VALRDY
+ Write '1' to disable interrupt for event VALRDY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x504
+ read-write
+
+
+ DERCEN
+ Bias correction
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enabled
+ 1
+
+
+
+
+
+
+ VALUE
+ Output random number
+ 0x508
+ read-only
+
+
+ VALUE
+ Generated random number
+ 0
+ 7
+
+
+
+
+
+
+ ECB
+ AES ECB Mode Encryption
+ 0x4000E000
+
+ 0
+ 0x1000
+ registers
+
+
+ ECB
+ 14
+
+ ECB
+ 0x20
+
+
+ TASKS_STARTECB
+ Start ECB block encrypt
+ 0x000
+ write-only
+
+
+ TASKS_STARTECB
+ Start ECB block encrypt
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOPECB
+ Abort a possible executing ECB operation
+ 0x004
+ write-only
+
+
+ TASKS_STOPECB
+ Abort a possible executing ECB operation
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_ENDECB
+ ECB block encrypt complete
+ 0x100
+ read-write
+
+
+ EVENTS_ENDECB
+ ECB block encrypt complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERRORECB
+ ECB block encrypt aborted because of a STOPECB task or due to an error
+ 0x104
+ read-write
+
+
+ EVENTS_ERRORECB
+ ECB block encrypt aborted because of a STOPECB task or due to an error
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ ENDECB
+ Write '1' to enable interrupt for event ENDECB
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERRORECB
+ Write '1' to enable interrupt for event ERRORECB
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ ENDECB
+ Write '1' to disable interrupt for event ENDECB
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERRORECB
+ Write '1' to disable interrupt for event ERRORECB
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ECBDATAPTR
+ ECB block encrypt memory pointers
+ 0x504
+ read-write
+
+
+ ECBDATAPTR
+ Pointer to the ECB data structure (see Table 1 ECB data structure overview)
+ 0
+ 31
+
+
+
+
+
+
+ AAR
+ Accelerated Address Resolver
+ 0x4000F000
+
+ 0
+ 0x1000
+ registers
+
+
+ CCM_AAR
+ 15
+
+ AAR
+ 0x20
+
+
+ TASKS_START
+ Start resolving addresses based on IRKs specified in the IRK data structure
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start resolving addresses based on IRKs specified in the IRK data structure
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop resolving addresses
+ 0x008
+ write-only
+
+
+ TASKS_STOP
+ Stop resolving addresses
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ Address resolution procedure complete
+ 0x100
+ read-write
+
+
+ EVENTS_END
+ Address resolution procedure complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_RESOLVED
+ Address resolved
+ 0x104
+ read-write
+
+
+ EVENTS_RESOLVED
+ Address resolved
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_NOTRESOLVED
+ Address not resolved
+ 0x108
+ read-write
+
+
+ EVENTS_NOTRESOLVED
+ Address not resolved
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ RESOLVED
+ Write '1' to enable interrupt for event RESOLVED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ NOTRESOLVED
+ Write '1' to enable interrupt for event NOTRESOLVED
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ RESOLVED
+ Write '1' to disable interrupt for event RESOLVED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ NOTRESOLVED
+ Write '1' to disable interrupt for event NOTRESOLVED
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ STATUS
+ Resolution status
+ 0x400
+ read-only
+
+
+ STATUS
+ The IRK that was used last time an address was resolved
+ 0
+ 3
+
+
+
+
+ ENABLE
+ Enable AAR
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable AAR
+ 0
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 3
+
+
+
+
+
+
+ NIRK
+ Number of IRKs
+ 0x504
+ read-write
+ 0x00000001
+
+
+ NIRK
+ Number of Identity root keys available in the IRK data structure
+ 0
+ 4
+
+
+
+
+ IRKPTR
+ Pointer to IRK data structure
+ 0x508
+ read-write
+
+
+ IRKPTR
+ Pointer to the IRK data structure
+ 0
+ 31
+
+
+
+
+ ADDRPTR
+ Pointer to the resolvable address
+ 0x510
+ read-write
+
+
+ ADDRPTR
+ Pointer to the resolvable address (6-bytes)
+ 0
+ 31
+
+
+
+
+ SCRATCHPTR
+ Pointer to data area used for temporary storage
+ 0x514
+ read-write
+
+
+ SCRATCHPTR
+ Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved.
+ 0
+ 31
+
+
+
+
+
+
+ CCM
+ AES CCM Mode Encryption
+ 0x4000F000
+ AAR
+
+ 0
+ 0x1000
+ registers
+
+
+ CCM_AAR
+ 15
+
+ CCM
+ 0x20
+
+
+ TASKS_KSGEN
+ Start generation of key-stream. This operation will stop by itself when completed.
+ 0x000
+ write-only
+
+
+ TASKS_KSGEN
+ Start generation of key-stream. This operation will stop by itself when completed.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_CRYPT
+ Start encryption/decryption. This operation will stop by itself when completed.
+ 0x004
+ write-only
+
+
+ TASKS_CRYPT
+ Start encryption/decryption. This operation will stop by itself when completed.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop encryption/decryption
+ 0x008
+ write-only
+
+
+ TASKS_STOP
+ Stop encryption/decryption
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RATEOVERRIDE
+ Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
+ 0x00C
+ write-only
+
+
+ TASKS_RATEOVERRIDE
+ Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_ENDKSGEN
+ Key-stream generation complete
+ 0x100
+ read-write
+
+
+ EVENTS_ENDKSGEN
+ Key-stream generation complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDCRYPT
+ Encrypt/decrypt complete
+ 0x104
+ read-write
+
+
+ EVENTS_ENDCRYPT
+ Encrypt/decrypt complete
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ERROR
+ Deprecated register - CCM error event
+ 0x108
+ read-write
+
+
+ EVENTS_ERROR
+ Deprecated field - CCM error event
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ ENDKSGEN_CRYPT
+ Shortcut between event ENDKSGEN and task CRYPT
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ ENDKSGEN
+ Write '1' to enable interrupt for event ENDKSGEN
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDCRYPT
+ Write '1' to enable interrupt for event ENDCRYPT
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ERROR
+ Deprecated intsetfield - Write '1' to enable interrupt for event ERROR
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ ENDKSGEN
+ Write '1' to disable interrupt for event ENDKSGEN
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDCRYPT
+ Write '1' to disable interrupt for event ENDCRYPT
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ERROR
+ Deprecated intclrfield - Write '1' to disable interrupt for event ERROR
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ MICSTATUS
+ MIC check result
+ 0x400
+ read-only
+
+
+ MICSTATUS
+ The result of the MIC check performed during the previous decryption operation
+ 0
+ 0
+
+
+ CheckFailed
+ MIC check failed
+ 0
+
+
+ CheckPassed
+ MIC check passed
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable CCM
+ 0
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 2
+
+
+
+
+
+
+ MODE
+ Operation mode
+ 0x504
+ read-write
+ 0x00000001
+
+
+ MODE
+ The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.
+ 0
+ 0
+
+
+ Encryption
+ AES CCM packet encryption mode
+ 0
+
+
+ Decryption
+ AES CCM packet decryption mode
+ 1
+
+
+
+
+ DATARATE
+ Radio data rate that the CCM shall run synchronous with
+ 16
+ 17
+
+
+ 1Mbit
+ 1 Mbps
+ 0
+
+
+ 2Mbit
+ 2 Mbps
+ 1
+
+
+ 125Kbps
+ 125 Kbps
+ 2
+
+
+ 500Kbps
+ 500 Kbps
+ 3
+
+
+
+
+ LENGTH
+ Packet length configuration
+ 24
+ 24
+
+
+ Default
+ Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated.
+ 0
+
+
+ Extended
+ Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated.
+ 1
+
+
+
+
+
+
+ CNFPTR
+ Pointer to data structure holding AES key and NONCE vector
+ 0x508
+ read-write
+
+
+ CNFPTR
+ Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)
+ 0
+ 31
+
+
+
+
+ INPTR
+ Input pointer
+ 0x50C
+ read-write
+
+
+ INPTR
+ Input pointer
+ 0
+ 31
+
+
+
+
+ OUTPTR
+ Output pointer
+ 0x510
+ read-write
+
+
+ OUTPTR
+ Output pointer
+ 0
+ 31
+
+
+
+
+ SCRATCHPTR
+ Pointer to data area used for temporary storage
+ 0x514
+ read-write
+
+
+ SCRATCHPTR
+ Pointer to a scratch data area used for temporary storage during key-stream generation,
+ MIC generation and encryption/decryption.
+ 0
+ 31
+
+
+
+
+ MAXPACKETSIZE
+ Length of key-stream generated when MODE.LENGTH = Extended.
+ 0x518
+ read-write
+ 0x000000FB
+
+
+ MAXPACKETSIZE
+ Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.
+ 0
+ 7
+
+
+
+
+ RATEOVERRIDE
+ Data rate override setting.
+ 0x51C
+ read-write
+ 0x00000000
+
+
+ RATEOVERRIDE
+ Data rate override setting.
+ 0
+ 1
+
+
+ 1Mbit
+ 1 Mbps
+ 0
+
+
+ 2Mbit
+ 2 Mbps
+ 1
+
+
+ 125Kbps
+ 125 Kbps
+ 2
+
+
+ 500Kbps
+ 500 Kbps
+ 3
+
+
+
+
+
+
+
+
+ WDT
+ Watchdog Timer
+ 0x40010000
+
+ 0
+ 0x1000
+ registers
+
+
+ WDT
+ 16
+
+ WDT
+ 0x20
+
+
+ TASKS_START
+ Start the watchdog
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start the watchdog
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_TIMEOUT
+ Watchdog timeout
+ 0x100
+ read-write
+
+
+ EVENTS_TIMEOUT
+ Watchdog timeout
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ TIMEOUT
+ Write '1' to enable interrupt for event TIMEOUT
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ TIMEOUT
+ Write '1' to disable interrupt for event TIMEOUT
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ RUNSTATUS
+ Run status
+ 0x400
+ read-only
+
+
+ RUNSTATUS
+ Indicates whether or not the watchdog is running
+ 0
+ 0
+
+
+ NotRunning
+ Watchdog not running
+ 0
+
+
+ Running
+ Watchdog is running
+ 1
+
+
+
+
+
+
+ REQSTATUS
+ Request status
+ 0x404
+ read-only
+ 0x00000001
+
+
+ RR0
+ Request status for RR[0] register
+ 0
+ 0
+
+
+ DisabledOrRequested
+ RR[0] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[0] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR1
+ Request status for RR[1] register
+ 1
+ 1
+
+
+ DisabledOrRequested
+ RR[1] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[1] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR2
+ Request status for RR[2] register
+ 2
+ 2
+
+
+ DisabledOrRequested
+ RR[2] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[2] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR3
+ Request status for RR[3] register
+ 3
+ 3
+
+
+ DisabledOrRequested
+ RR[3] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[3] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR4
+ Request status for RR[4] register
+ 4
+ 4
+
+
+ DisabledOrRequested
+ RR[4] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[4] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR5
+ Request status for RR[5] register
+ 5
+ 5
+
+
+ DisabledOrRequested
+ RR[5] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[5] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR6
+ Request status for RR[6] register
+ 6
+ 6
+
+
+ DisabledOrRequested
+ RR[6] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[6] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+ RR7
+ Request status for RR[7] register
+ 7
+ 7
+
+
+ DisabledOrRequested
+ RR[7] register is not enabled, or are already requesting reload
+ 0
+
+
+ EnabledAndUnrequested
+ RR[7] register is enabled, and are not yet requesting reload
+ 1
+
+
+
+
+
+
+ CRV
+ Counter reload value
+ 0x504
+ read-write
+ 0xFFFFFFFF
+
+
+ CRV
+ Counter reload value in number of cycles of the 32.768 kHz clock
+ 0
+ 31
+
+
+
+
+ RREN
+ Enable register for reload request registers
+ 0x508
+ read-write
+ 0x00000001
+
+
+ RR0
+ Enable or disable RR[0] register
+ 0
+ 0
+
+
+ Disabled
+ Disable RR[0] register
+ 0
+
+
+ Enabled
+ Enable RR[0] register
+ 1
+
+
+
+
+ RR1
+ Enable or disable RR[1] register
+ 1
+ 1
+
+
+ Disabled
+ Disable RR[1] register
+ 0
+
+
+ Enabled
+ Enable RR[1] register
+ 1
+
+
+
+
+ RR2
+ Enable or disable RR[2] register
+ 2
+ 2
+
+
+ Disabled
+ Disable RR[2] register
+ 0
+
+
+ Enabled
+ Enable RR[2] register
+ 1
+
+
+
+
+ RR3
+ Enable or disable RR[3] register
+ 3
+ 3
+
+
+ Disabled
+ Disable RR[3] register
+ 0
+
+
+ Enabled
+ Enable RR[3] register
+ 1
+
+
+
+
+ RR4
+ Enable or disable RR[4] register
+ 4
+ 4
+
+
+ Disabled
+ Disable RR[4] register
+ 0
+
+
+ Enabled
+ Enable RR[4] register
+ 1
+
+
+
+
+ RR5
+ Enable or disable RR[5] register
+ 5
+ 5
+
+
+ Disabled
+ Disable RR[5] register
+ 0
+
+
+ Enabled
+ Enable RR[5] register
+ 1
+
+
+
+
+ RR6
+ Enable or disable RR[6] register
+ 6
+ 6
+
+
+ Disabled
+ Disable RR[6] register
+ 0
+
+
+ Enabled
+ Enable RR[6] register
+ 1
+
+
+
+
+ RR7
+ Enable or disable RR[7] register
+ 7
+ 7
+
+
+ Disabled
+ Disable RR[7] register
+ 0
+
+
+ Enabled
+ Enable RR[7] register
+ 1
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x50C
+ read-write
+ 0x00000001
+
+
+ SLEEP
+ Configure the watchdog to either be paused, or kept running, while the CPU is sleeping
+ 0
+ 0
+
+
+ Pause
+ Pause watchdog while the CPU is sleeping
+ 0
+
+
+ Run
+ Keep the watchdog running while the CPU is sleeping
+ 1
+
+
+
+
+ HALT
+ Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger
+ 3
+ 3
+
+
+ Pause
+ Pause watchdog while the CPU is halted by the debugger
+ 0
+
+
+ Run
+ Keep the watchdog running while the CPU is halted by the debugger
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ RR[%s]
+ Description collection: Reload request n
+ 0x600
+ write-only
+
+
+ RR
+ Reload request register
+ 0
+ 31
+
+
+ Reload
+ Value to request a reload of the watchdog timer
+ 0x6E524635
+
+
+
+
+
+
+
+
+ RTC1
+ Real time counter 1
+ 0x40011000
+
+ RTC1
+ 17
+
+
+
+ QDEC
+ Quadrature Decoder
+ 0x40012000
+
+ 0
+ 0x1000
+ registers
+
+
+ QDEC
+ 18
+
+ QDEC
+ 0x20
+
+
+ TASKS_START
+ Task starting the quadrature decoder
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Task starting the quadrature decoder
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Task stopping the quadrature decoder
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Task stopping the quadrature decoder
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_READCLRACC
+ Read and clear ACC and ACCDBL
+ 0x008
+ write-only
+
+
+ TASKS_READCLRACC
+ Read and clear ACC and ACCDBL
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RDCLRACC
+ Read and clear ACC
+ 0x00C
+ write-only
+
+
+ TASKS_RDCLRACC
+ Read and clear ACC
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_RDCLRDBL
+ Read and clear ACCDBL
+ 0x010
+ write-only
+
+
+ TASKS_RDCLRDBL
+ Read and clear ACCDBL
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_SAMPLERDY
+ Event being generated for every new sample value written to the SAMPLE register
+ 0x100
+ read-write
+
+
+ EVENTS_SAMPLERDY
+ Event being generated for every new sample value written to the SAMPLE register
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_REPORTRDY
+ Non-null report ready
+ 0x104
+ read-write
+
+
+ EVENTS_REPORTRDY
+ Non-null report ready
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ACCOF
+ ACC or ACCDBL register overflow
+ 0x108
+ read-write
+
+
+ EVENTS_ACCOF
+ ACC or ACCDBL register overflow
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DBLRDY
+ Double displacement(s) detected
+ 0x10C
+ read-write
+
+
+ EVENTS_DBLRDY
+ Double displacement(s) detected
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ QDEC has been stopped
+ 0x110
+ read-write
+
+
+ EVENTS_STOPPED
+ QDEC has been stopped
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ REPORTRDY_READCLRACC
+ Shortcut between event REPORTRDY and task READCLRACC
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ SAMPLERDY_STOP
+ Shortcut between event SAMPLERDY and task STOP
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ REPORTRDY_RDCLRACC
+ Shortcut between event REPORTRDY and task RDCLRACC
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ REPORTRDY_STOP
+ Shortcut between event REPORTRDY and task STOP
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ DBLRDY_RDCLRDBL
+ Shortcut between event DBLRDY and task RDCLRDBL
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ DBLRDY_STOP
+ Shortcut between event DBLRDY and task STOP
+ 5
+ 5
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ SAMPLERDY_READCLRACC
+ Shortcut between event SAMPLERDY and task READCLRACC
+ 6
+ 6
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ SAMPLERDY
+ Write '1' to enable interrupt for event SAMPLERDY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REPORTRDY
+ Write '1' to enable interrupt for event REPORTRDY
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ACCOF
+ Write '1' to enable interrupt for event ACCOF
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DBLRDY
+ Write '1' to enable interrupt for event DBLRDY
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ SAMPLERDY
+ Write '1' to disable interrupt for event SAMPLERDY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REPORTRDY
+ Write '1' to disable interrupt for event REPORTRDY
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ACCOF
+ Write '1' to disable interrupt for event ACCOF
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DBLRDY
+ Write '1' to disable interrupt for event DBLRDY
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable the quadrature decoder
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable the quadrature decoder
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ LEDPOL
+ LED output pin polarity
+ 0x504
+ read-write
+
+
+ LEDPOL
+ LED output pin polarity
+ 0
+ 0
+
+
+ ActiveLow
+ Led active on output pin low
+ 0
+
+
+ ActiveHigh
+ Led active on output pin high
+ 1
+
+
+
+
+
+
+ SAMPLEPER
+ Sample period
+ 0x508
+ read-write
+
+
+ SAMPLEPER
+ Sample period. The SAMPLE register will be updated for every new sample
+ 0
+ 3
+
+
+ 128us
+ 128 us
+ 0
+
+
+ 256us
+ 256 us
+ 1
+
+
+ 512us
+ 512 us
+ 2
+
+
+ 1024us
+ 1024 us
+ 3
+
+
+ 2048us
+ 2048 us
+ 4
+
+
+ 4096us
+ 4096 us
+ 5
+
+
+ 8192us
+ 8192 us
+ 6
+
+
+ 16384us
+ 16384 us
+ 7
+
+
+ 32ms
+ 32768 us
+ 8
+
+
+ 65ms
+ 65536 us
+ 9
+
+
+ 131ms
+ 131072 us
+ 10
+
+
+
+
+
+
+ SAMPLE
+ Motion sample value
+ 0x50C
+ read-only
+ int32_t
+
+
+ SAMPLE
+ Last motion sample
+ 0
+ 31
+
+
+
+
+ REPORTPER
+ Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
+ 0x510
+ read-write
+
+
+ REPORTPER
+ Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated
+ 0
+ 3
+
+
+ 10Smpl
+ 10 samples / report
+ 0
+
+
+ 40Smpl
+ 40 samples / report
+ 1
+
+
+ 80Smpl
+ 80 samples / report
+ 2
+
+
+ 120Smpl
+ 120 samples / report
+ 3
+
+
+ 160Smpl
+ 160 samples / report
+ 4
+
+
+ 200Smpl
+ 200 samples / report
+ 5
+
+
+ 240Smpl
+ 240 samples / report
+ 6
+
+
+ 280Smpl
+ 280 samples / report
+ 7
+
+
+ 1Smpl
+ 1 sample / report
+ 8
+
+
+
+
+
+
+ ACC
+ Register accumulating the valid transitions
+ 0x514
+ read-only
+ int32_t
+
+
+ ACC
+ Register accumulating all valid samples (not double transition) read from the SAMPLE register
+ 0
+ 31
+
+
+
+
+ ACCREAD
+ Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
+ 0x518
+ read-only
+ int32_t
+
+
+ ACCREAD
+ Snapshot of the ACC register.
+ 0
+ 31
+
+
+
+
+ PSEL
+ Unspecified
+ QDEC_PSEL
+ read-write
+ 0x51C
+
+ LED
+ Pin select for LED signal
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ A
+ Pin select for A signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ B
+ Pin select for B signal
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ DBFEN
+ Enable input debounce filters
+ 0x528
+ read-write
+
+
+ DBFEN
+ Enable input debounce filters
+ 0
+ 0
+
+
+ Disabled
+ Debounce input filters disabled
+ 0
+
+
+ Enabled
+ Debounce input filters enabled
+ 1
+
+
+
+
+
+
+ LEDPRE
+ Time period the LED is switched ON prior to sampling
+ 0x540
+ read-write
+ 0x00000010
+
+
+ LEDPRE
+ Period in us the LED is switched on prior to sampling
+ 0
+ 8
+
+
+
+
+ ACCDBL
+ Register accumulating the number of detected double transitions
+ 0x544
+ read-only
+
+
+ ACCDBL
+ Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).
+ 0
+ 3
+
+
+
+
+ ACCDBLREAD
+ Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
+ 0x548
+ read-only
+
+
+ ACCDBLREAD
+ Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered.
+ 0
+ 3
+
+
+
+
+
+
+ COMP
+ Comparator
+ 0x40013000
+
+ 0
+ 0x1000
+ registers
+
+
+ COMP_LPCOMP
+ 19
+
+ COMP
+ 0x20
+
+
+ TASKS_START
+ Start comparator
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start comparator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop comparator
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stop comparator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SAMPLE
+ Sample comparator value
+ 0x008
+ write-only
+
+
+ TASKS_SAMPLE
+ Sample comparator value
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_READY
+ COMP is ready and output is valid
+ 0x100
+ read-write
+
+
+ EVENTS_READY
+ COMP is ready and output is valid
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DOWN
+ Downward crossing
+ 0x104
+ read-write
+
+
+ EVENTS_DOWN
+ Downward crossing
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_UP
+ Upward crossing
+ 0x108
+ read-write
+
+
+ EVENTS_UP
+ Upward crossing
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CROSS
+ Downward or upward crossing
+ 0x10C
+ read-write
+
+
+ EVENTS_CROSS
+ Downward or upward crossing
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ READY_SAMPLE
+ Shortcut between event READY and task SAMPLE
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ READY_STOP
+ Shortcut between event READY and task STOP
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ DOWN_STOP
+ Shortcut between event DOWN and task STOP
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ UP_STOP
+ Shortcut between event UP and task STOP
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ CROSS_STOP
+ Shortcut between event CROSS and task STOP
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ READY
+ Enable or disable interrupt for event READY
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ DOWN
+ Enable or disable interrupt for event DOWN
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ UP
+ Enable or disable interrupt for event UP
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ CROSS
+ Enable or disable interrupt for event CROSS
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ READY
+ Write '1' to enable interrupt for event READY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DOWN
+ Write '1' to enable interrupt for event DOWN
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ UP
+ Write '1' to enable interrupt for event UP
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CROSS
+ Write '1' to enable interrupt for event CROSS
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ READY
+ Write '1' to disable interrupt for event READY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DOWN
+ Write '1' to disable interrupt for event DOWN
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ UP
+ Write '1' to disable interrupt for event UP
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CROSS
+ Write '1' to disable interrupt for event CROSS
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ RESULT
+ Compare result
+ 0x400
+ read-only
+
+
+ RESULT
+ Result of last compare. Decision point SAMPLE task.
+ 0
+ 0
+
+
+ Below
+ Input voltage is below the threshold (VIN+ < VIN-)
+ 0
+
+
+ Above
+ Input voltage is above the threshold (VIN+ > VIN-)
+ 1
+
+
+
+
+
+
+ ENABLE
+ COMP enable
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable COMP
+ 0
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 2
+
+
+
+
+
+
+ PSEL
+ Pin select
+ 0x504
+ read-write
+
+
+ PSEL
+ Analog pin select
+ 0
+ 2
+
+
+ AnalogInput0
+ AIN0 selected as analog input
+ 0
+
+
+ AnalogInput1
+ AIN1 selected as analog input
+ 1
+
+
+ AnalogInput2
+ AIN2 selected as analog input
+ 2
+
+
+ AnalogInput3
+ AIN3 selected as analog input
+ 3
+
+
+ AnalogInput4
+ AIN4 selected as analog input
+ 4
+
+
+ AnalogInput5
+ AIN5 selected as analog input
+ 5
+
+
+ AnalogInput6
+ AIN6 selected as analog input
+ 6
+
+
+ AnalogInput7
+ AIN7 selected as analog input
+ 7
+
+
+
+
+
+
+ REFSEL
+ Reference source select for single-ended mode
+ 0x508
+ read-write
+ 0x00000004
+
+
+ REFSEL
+ Reference select
+ 0
+ 2
+
+
+ Int1V2
+ VREF = internal 1.2 V reference (VDD >= 1.7 V)
+ 0
+
+
+ Int1V8
+ VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)
+ 1
+
+
+ Int2V4
+ VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)
+ 2
+
+
+ VDD
+ VREF = VDD
+ 4
+
+
+ ARef
+ VREF = AREF (VDD >= VREF >= AREFMIN)
+ 5
+
+
+
+
+
+
+ EXTREFSEL
+ External reference select
+ 0x50C
+ read-write
+
+
+ EXTREFSEL
+ External analog reference select
+ 0
+ 2
+
+
+ AnalogReference0
+ Use AIN0 as external analog reference
+ 0
+
+
+ AnalogReference1
+ Use AIN1 as external analog reference
+ 1
+
+
+ AnalogReference2
+ Use AIN2 as external analog reference
+ 2
+
+
+ AnalogReference3
+ Use AIN3 as external analog reference
+ 3
+
+
+ AnalogReference4
+ Use AIN4 as external analog reference
+ 4
+
+
+ AnalogReference5
+ Use AIN5 as external analog reference
+ 5
+
+
+ AnalogReference6
+ Use AIN6 as external analog reference
+ 6
+
+
+ AnalogReference7
+ Use AIN7 as external analog reference
+ 7
+
+
+
+
+
+
+ TH
+ Threshold configuration for hysteresis unit
+ 0x530
+ read-write
+ 0x00000000
+
+
+ THDOWN
+ VDOWN = (THDOWN+1)/64*VREF
+ 0
+ 5
+
+
+ THUP
+ VUP = (THUP+1)/64*VREF
+ 8
+ 13
+
+
+
+
+ MODE
+ Mode configuration
+ 0x534
+ read-write
+
+
+ SP
+ Speed and power modes
+ 0
+ 1
+
+
+ Low
+ Low-power mode
+ 0
+
+
+ Normal
+ Normal mode
+ 1
+
+
+ High
+ High-speed mode
+ 2
+
+
+
+
+ MAIN
+ Main operation modes
+ 8
+ 8
+
+
+ SE
+ Single-ended mode
+ 0
+
+
+ Diff
+ Differential mode
+ 1
+
+
+
+
+
+
+ HYST
+ Comparator hysteresis enable
+ 0x538
+ read-write
+
+
+ HYST
+ Comparator hysteresis
+ 0
+ 0
+
+
+ NoHyst
+ Comparator hysteresis disabled
+ 0
+
+
+ Hyst50mV
+ Comparator hysteresis enabled
+ 1
+
+
+
+
+
+
+
+
+ LPCOMP
+ Low Power Comparator
+ 0x40013000
+ COMP
+
+ 0
+ 0x1000
+ registers
+
+
+ COMP_LPCOMP
+ 19
+
+ LPCOMP
+ 0x20
+
+
+ TASKS_START
+ Start comparator
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Start comparator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stop comparator
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stop comparator
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_SAMPLE
+ Sample comparator value
+ 0x008
+ write-only
+
+
+ TASKS_SAMPLE
+ Sample comparator value
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_READY
+ LPCOMP is ready and output is valid
+ 0x100
+ read-write
+
+
+ EVENTS_READY
+ LPCOMP is ready and output is valid
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_DOWN
+ Downward crossing
+ 0x104
+ read-write
+
+
+ EVENTS_DOWN
+ Downward crossing
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_UP
+ Upward crossing
+ 0x108
+ read-write
+
+
+ EVENTS_UP
+ Upward crossing
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_CROSS
+ Downward or upward crossing
+ 0x10C
+ read-write
+
+
+ EVENTS_CROSS
+ Downward or upward crossing
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ READY_SAMPLE
+ Shortcut between event READY and task SAMPLE
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ READY_STOP
+ Shortcut between event READY and task STOP
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ DOWN_STOP
+ Shortcut between event DOWN and task STOP
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ UP_STOP
+ Shortcut between event UP and task STOP
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ CROSS_STOP
+ Shortcut between event CROSS and task STOP
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ READY
+ Write '1' to enable interrupt for event READY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ DOWN
+ Write '1' to enable interrupt for event DOWN
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ UP
+ Write '1' to enable interrupt for event UP
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ CROSS
+ Write '1' to enable interrupt for event CROSS
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ READY
+ Write '1' to disable interrupt for event READY
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ DOWN
+ Write '1' to disable interrupt for event DOWN
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ UP
+ Write '1' to disable interrupt for event UP
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ CROSS
+ Write '1' to disable interrupt for event CROSS
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ RESULT
+ Compare result
+ 0x400
+ read-only
+
+
+ RESULT
+ Result of last compare. Decision point SAMPLE task.
+ 0
+ 0
+
+
+ Below
+ Input voltage is below the reference threshold (VIN+ < VIN-).
+ 0
+
+
+ Above
+ Input voltage is above the reference threshold (VIN+ > VIN-).
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable LPCOMP
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable or disable LPCOMP
+ 0
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ PSEL
+ Input pin select
+ 0x504
+ read-write
+
+
+ PSEL
+ Analog pin select
+ 0
+ 2
+
+
+ AnalogInput0
+ AIN0 selected as analog input
+ 0
+
+
+ AnalogInput1
+ AIN1 selected as analog input
+ 1
+
+
+ AnalogInput2
+ AIN2 selected as analog input
+ 2
+
+
+ AnalogInput3
+ AIN3 selected as analog input
+ 3
+
+
+ AnalogInput4
+ AIN4 selected as analog input
+ 4
+
+
+ AnalogInput5
+ AIN5 selected as analog input
+ 5
+
+
+ AnalogInput6
+ AIN6 selected as analog input
+ 6
+
+
+ AnalogInput7
+ AIN7 selected as analog input
+ 7
+
+
+
+
+
+
+ REFSEL
+ Reference select
+ 0x508
+ read-write
+ 0x00000004
+
+
+ REFSEL
+ Reference select
+ 0
+ 3
+
+
+ Ref1_8Vdd
+ VDD * 1/8 selected as reference
+ 0
+
+
+ Ref2_8Vdd
+ VDD * 2/8 selected as reference
+ 1
+
+
+ Ref3_8Vdd
+ VDD * 3/8 selected as reference
+ 2
+
+
+ Ref4_8Vdd
+ VDD * 4/8 selected as reference
+ 3
+
+
+ Ref5_8Vdd
+ VDD * 5/8 selected as reference
+ 4
+
+
+ Ref6_8Vdd
+ VDD * 6/8 selected as reference
+ 5
+
+
+ Ref7_8Vdd
+ VDD * 7/8 selected as reference
+ 6
+
+
+ ARef
+ External analog reference selected
+ 7
+
+
+ Ref1_16Vdd
+ VDD * 1/16 selected as reference
+ 8
+
+
+ Ref3_16Vdd
+ VDD * 3/16 selected as reference
+ 9
+
+
+ Ref5_16Vdd
+ VDD * 5/16 selected as reference
+ 10
+
+
+ Ref7_16Vdd
+ VDD * 7/16 selected as reference
+ 11
+
+
+ Ref9_16Vdd
+ VDD * 9/16 selected as reference
+ 12
+
+
+ Ref11_16Vdd
+ VDD * 11/16 selected as reference
+ 13
+
+
+ Ref13_16Vdd
+ VDD * 13/16 selected as reference
+ 14
+
+
+ Ref15_16Vdd
+ VDD * 15/16 selected as reference
+ 15
+
+
+
+
+
+
+ EXTREFSEL
+ External reference select
+ 0x50C
+ read-write
+
+
+ EXTREFSEL
+ External analog reference select
+ 0
+ 0
+
+
+ AnalogReference0
+ Use AIN0 as external analog reference
+ 0
+
+
+ AnalogReference1
+ Use AIN1 as external analog reference
+ 1
+
+
+
+
+
+
+ ANADETECT
+ Analog detect configuration
+ 0x520
+ read-write
+
+
+ ANADETECT
+ Analog detect configuration
+ 0
+ 1
+
+
+ Cross
+ Generate ANADETECT on crossing, both upward crossing and downward crossing
+ 0
+
+
+ Up
+ Generate ANADETECT on upward crossing only
+ 1
+
+
+ Down
+ Generate ANADETECT on downward crossing only
+ 2
+
+
+
+
+
+
+ HYST
+ Comparator hysteresis enable
+ 0x538
+ read-write
+
+
+ HYST
+ Comparator hysteresis enable
+ 0
+ 0
+
+
+ Disabled
+ Comparator hysteresis disabled
+ 0
+
+
+ Enabled
+ Comparator hysteresis enabled
+ 1
+
+
+
+
+
+
+
+
+ EGU0
+ Event Generator Unit 0
+ 0x40014000
+ EGU
+
+ 0
+ 0x1000
+ registers
+
+
+ SWI0_EGU0
+ 20
+
+ EGU
+ 0x20
+
+
+ 0x10
+ 0x4
+ TASKS_TRIGGER[%s]
+ Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event
+ 0x000
+ write-only
+
+
+ TASKS_TRIGGER
+ Trigger n for triggering the corresponding TRIGGERED[n] event
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x10
+ 0x4
+ EVENTS_TRIGGERED[%s]
+ Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task
+ 0x100
+ read-write
+
+
+ EVENTS_TRIGGERED
+ Event number n generated by triggering the corresponding TRIGGER[n] task
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ TRIGGERED0
+ Enable or disable interrupt for event TRIGGERED[0]
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED1
+ Enable or disable interrupt for event TRIGGERED[1]
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED2
+ Enable or disable interrupt for event TRIGGERED[2]
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED3
+ Enable or disable interrupt for event TRIGGERED[3]
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED4
+ Enable or disable interrupt for event TRIGGERED[4]
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED5
+ Enable or disable interrupt for event TRIGGERED[5]
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED6
+ Enable or disable interrupt for event TRIGGERED[6]
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED7
+ Enable or disable interrupt for event TRIGGERED[7]
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED8
+ Enable or disable interrupt for event TRIGGERED[8]
+ 8
+ 8
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED9
+ Enable or disable interrupt for event TRIGGERED[9]
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED10
+ Enable or disable interrupt for event TRIGGERED[10]
+ 10
+ 10
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED11
+ Enable or disable interrupt for event TRIGGERED[11]
+ 11
+ 11
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED12
+ Enable or disable interrupt for event TRIGGERED[12]
+ 12
+ 12
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED13
+ Enable or disable interrupt for event TRIGGERED[13]
+ 13
+ 13
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED14
+ Enable or disable interrupt for event TRIGGERED[14]
+ 14
+ 14
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TRIGGERED15
+ Enable or disable interrupt for event TRIGGERED[15]
+ 15
+ 15
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ TRIGGERED0
+ Write '1' to enable interrupt for event TRIGGERED[0]
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED1
+ Write '1' to enable interrupt for event TRIGGERED[1]
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED2
+ Write '1' to enable interrupt for event TRIGGERED[2]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED3
+ Write '1' to enable interrupt for event TRIGGERED[3]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED4
+ Write '1' to enable interrupt for event TRIGGERED[4]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED5
+ Write '1' to enable interrupt for event TRIGGERED[5]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED6
+ Write '1' to enable interrupt for event TRIGGERED[6]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED7
+ Write '1' to enable interrupt for event TRIGGERED[7]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED8
+ Write '1' to enable interrupt for event TRIGGERED[8]
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED9
+ Write '1' to enable interrupt for event TRIGGERED[9]
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED10
+ Write '1' to enable interrupt for event TRIGGERED[10]
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED11
+ Write '1' to enable interrupt for event TRIGGERED[11]
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED12
+ Write '1' to enable interrupt for event TRIGGERED[12]
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED13
+ Write '1' to enable interrupt for event TRIGGERED[13]
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED14
+ Write '1' to enable interrupt for event TRIGGERED[14]
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TRIGGERED15
+ Write '1' to enable interrupt for event TRIGGERED[15]
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ TRIGGERED0
+ Write '1' to disable interrupt for event TRIGGERED[0]
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED1
+ Write '1' to disable interrupt for event TRIGGERED[1]
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED2
+ Write '1' to disable interrupt for event TRIGGERED[2]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED3
+ Write '1' to disable interrupt for event TRIGGERED[3]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED4
+ Write '1' to disable interrupt for event TRIGGERED[4]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED5
+ Write '1' to disable interrupt for event TRIGGERED[5]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED6
+ Write '1' to disable interrupt for event TRIGGERED[6]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED7
+ Write '1' to disable interrupt for event TRIGGERED[7]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED8
+ Write '1' to disable interrupt for event TRIGGERED[8]
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED9
+ Write '1' to disable interrupt for event TRIGGERED[9]
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED10
+ Write '1' to disable interrupt for event TRIGGERED[10]
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED11
+ Write '1' to disable interrupt for event TRIGGERED[11]
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED12
+ Write '1' to disable interrupt for event TRIGGERED[12]
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED13
+ Write '1' to disable interrupt for event TRIGGERED[13]
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED14
+ Write '1' to disable interrupt for event TRIGGERED[14]
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TRIGGERED15
+ Write '1' to disable interrupt for event TRIGGERED[15]
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+
+
+ SWI0
+ Software interrupt 0
+ 0x40014000
+ EGU0
+ SWI
+
+ 0
+ 0x1000
+ registers
+
+
+ SWI0_EGU0
+ 20
+
+ SWI
+ 0x20
+
+
+ UNUSED
+ Unused.
+ 0x000
+ 0x00000000
+ read-only
+
+
+
+
+ EGU1
+ Event Generator Unit 1
+ 0x40015000
+
+ SWI1_EGU1
+ 21
+
+
+
+ SWI1
+ Software interrupt 1
+ 0x40015000
+ EGU1
+
+ SWI1_EGU1
+ 21
+
+
+
+ EGU2
+ Event Generator Unit 2
+ 0x40016000
+
+ SWI2_EGU2
+ 22
+
+
+
+ SWI2
+ Software interrupt 2
+ 0x40016000
+ EGU2
+
+ SWI2_EGU2
+ 22
+
+
+
+ EGU3
+ Event Generator Unit 3
+ 0x40017000
+
+ SWI3_EGU3
+ 23
+
+
+
+ SWI3
+ Software interrupt 3
+ 0x40017000
+ EGU3
+
+ SWI3_EGU3
+ 23
+
+
+
+ EGU4
+ Event Generator Unit 4
+ 0x40018000
+
+ SWI4_EGU4
+ 24
+
+
+
+ SWI4
+ Software interrupt 4
+ 0x40018000
+ EGU4
+
+ SWI4_EGU4
+ 24
+
+
+
+ EGU5
+ Event Generator Unit 5
+ 0x40019000
+
+ SWI5_EGU5
+ 25
+
+
+
+ SWI5
+ Software interrupt 5
+ 0x40019000
+ EGU5
+
+ SWI5_EGU5
+ 25
+
+
+
+ TIMER3
+ Timer/Counter 3
+ 0x4001A000
+
+ TIMER3
+ 26
+
+
+
+ TIMER4
+ Timer/Counter 4
+ 0x4001B000
+
+ TIMER4
+ 27
+
+
+
+ PWM0
+ Pulse width modulation unit 0
+ 0x4001C000
+ PWM
+
+ 0
+ 0x1000
+ registers
+
+
+ PWM0
+ 28
+
+ PWM
+ 0x20
+
+
+ TASKS_STOP
+ Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x2
+ 0x4
+ TASKS_SEQSTART[%s]
+ Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.
+ 0x008
+ write-only
+
+
+ TASKS_SEQSTART
+ Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_NEXTSTEP
+ Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.
+ 0x010
+ write-only
+
+
+ TASKS_NEXTSTEP
+ Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ Response to STOP task, emitted when PWM pulses are no longer generated
+ 0x104
+ read-write
+
+
+ EVENTS_STOPPED
+ Response to STOP task, emitted when PWM pulses are no longer generated
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ 0x2
+ 0x4
+ EVENTS_SEQSTARTED[%s]
+ Description collection: First PWM period started on sequence n
+ 0x108
+ read-write
+
+
+ EVENTS_SEQSTARTED
+ First PWM period started on sequence n
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ 0x2
+ 0x4
+ EVENTS_SEQEND[%s]
+ Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter
+ 0x110
+ read-write
+
+
+ EVENTS_SEQEND
+ Emitted at end of every sequence n, when last value from RAM has been applied to wave counter
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_PWMPERIODEND
+ Emitted at the end of each PWM period
+ 0x118
+ read-write
+
+
+ EVENTS_PWMPERIODEND
+ Emitted at the end of each PWM period
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_LOOPSDONE
+ Concatenated sequences have been played the amount of times defined in LOOP.CNT
+ 0x11C
+ read-write
+
+
+ EVENTS_LOOPSDONE
+ Concatenated sequences have been played the amount of times defined in LOOP.CNT
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ SEQEND0_STOP
+ Shortcut between event SEQEND[0] and task STOP
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ SEQEND1_STOP
+ Shortcut between event SEQEND[1] and task STOP
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LOOPSDONE_SEQSTART0
+ Shortcut between event LOOPSDONE and task SEQSTART[0]
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LOOPSDONE_SEQSTART1
+ Shortcut between event LOOPSDONE and task SEQSTART[1]
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ LOOPSDONE_STOP
+ Shortcut between event LOOPSDONE and task STOP
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ STOPPED
+ Enable or disable interrupt for event STOPPED
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ SEQSTARTED0
+ Enable or disable interrupt for event SEQSTARTED[0]
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ SEQSTARTED1
+ Enable or disable interrupt for event SEQSTARTED[1]
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ SEQEND0
+ Enable or disable interrupt for event SEQEND[0]
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ SEQEND1
+ Enable or disable interrupt for event SEQEND[1]
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ PWMPERIODEND
+ Enable or disable interrupt for event PWMPERIODEND
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ LOOPSDONE
+ Enable or disable interrupt for event LOOPSDONE
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SEQSTARTED0
+ Write '1' to enable interrupt for event SEQSTARTED[0]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SEQSTARTED1
+ Write '1' to enable interrupt for event SEQSTARTED[1]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SEQEND0
+ Write '1' to enable interrupt for event SEQEND[0]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SEQEND1
+ Write '1' to enable interrupt for event SEQEND[1]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PWMPERIODEND
+ Write '1' to enable interrupt for event PWMPERIODEND
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ LOOPSDONE
+ Write '1' to enable interrupt for event LOOPSDONE
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SEQSTARTED0
+ Write '1' to disable interrupt for event SEQSTARTED[0]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SEQSTARTED1
+ Write '1' to disable interrupt for event SEQSTARTED[1]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SEQEND0
+ Write '1' to disable interrupt for event SEQEND[0]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SEQEND1
+ Write '1' to disable interrupt for event SEQEND[1]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PWMPERIODEND
+ Write '1' to disable interrupt for event PWMPERIODEND
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ LOOPSDONE
+ Write '1' to disable interrupt for event LOOPSDONE
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ENABLE
+ PWM module enable register
+ 0x500
+ read-write
+ 0x00000000
+
+
+ ENABLE
+ Enable or disable PWM module
+ 0
+ 0
+
+
+ Disabled
+ Disabled
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ MODE
+ Selects operating mode of the wave counter
+ 0x504
+ read-write
+ 0x00000000
+
+
+ UPDOWN
+ Selects up mode or up-and-down mode for the counter
+ 0
+ 0
+
+
+ Up
+ Up counter, edge-aligned PWM duty cycle
+ 0
+
+
+ UpAndDown
+ Up and down counter, center-aligned PWM duty cycle
+ 1
+
+
+
+
+
+
+ COUNTERTOP
+ Value up to which the pulse generator counter counts
+ 0x508
+ read-write
+ 0x000003FF
+
+
+ COUNTERTOP
+ Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used.
+ 0
+ 14
+
+
+
+
+ PRESCALER
+ Configuration for PWM_CLK
+ 0x50C
+ read-write
+ 0x00000000
+
+
+ PRESCALER
+ Prescaler of PWM_CLK
+ 0
+ 2
+
+
+ DIV_1
+ Divide by 1 (16 MHz)
+ 0
+
+
+ DIV_2
+ Divide by 2 (8 MHz)
+ 1
+
+
+ DIV_4
+ Divide by 4 (4 MHz)
+ 2
+
+
+ DIV_8
+ Divide by 8 (2 MHz)
+ 3
+
+
+ DIV_16
+ Divide by 16 (1 MHz)
+ 4
+
+
+ DIV_32
+ Divide by 32 (500 kHz)
+ 5
+
+
+ DIV_64
+ Divide by 64 (250 kHz)
+ 6
+
+
+ DIV_128
+ Divide by 128 (125 kHz)
+ 7
+
+
+
+
+
+
+ DECODER
+ Configuration of the decoder
+ 0x510
+ read-write
+ 0x00000000
+
+
+ LOAD
+ How a sequence is read from RAM and spread to the compare register
+ 0
+ 1
+
+
+ Common
+ 1st half word (16-bit) used in all PWM channels 0..3
+ 0
+
+
+ Grouped
+ 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3
+ 1
+
+
+ Individual
+ 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3
+ 2
+
+
+ WaveForm
+ 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP
+ 3
+
+
+
+
+ MODE
+ Selects source for advancing the active sequence
+ 8
+ 8
+
+
+ RefreshCount
+ SEQ[n].REFRESH is used to determine loading internal compare registers
+ 0
+
+
+ NextStep
+ NEXTSTEP task causes a new value to be loaded to internal compare registers
+ 1
+
+
+
+
+
+
+ LOOP
+ Number of playbacks of a loop
+ 0x514
+ read-write
+ 0x00000000
+
+
+ CNT
+ Number of playbacks of pattern cycles
+ 0
+ 15
+
+
+ Disabled
+ Looping disabled (stop at the end of the sequence)
+ 0
+
+
+
+
+
+
+ 2
+ 0x020
+ SEQ[%s]
+ Unspecified
+ PWM_SEQ
+ read-write
+ 0x520
+
+ PTR
+ Description cluster: Beginning address in RAM of this sequence
+ 0x000
+ read-write
+ 0x00000000
+
+
+ PTR
+ Beginning address in RAM of this sequence
+ 0
+ 31
+
+
+
+
+ CNT
+ Description cluster: Number of values (duty cycles) in this sequence
+ 0x004
+ read-write
+ 0x00000000
+
+
+ CNT
+ Number of values (duty cycles) in this sequence
+ 0
+ 14
+
+
+ Disabled
+ Sequence is disabled, and shall not be started as it is empty
+ 0
+
+
+
+
+
+
+ REFRESH
+ Description cluster: Number of additional PWM periods between samples loaded into compare register
+ 0x008
+ read-write
+ 0x00000001
+
+
+ CNT
+ Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)
+ 0
+ 23
+
+
+ Continuous
+ Update every PWM period
+ 0
+
+
+
+
+
+
+ ENDDELAY
+ Description cluster: Time added after the sequence
+ 0x00C
+ read-write
+ 0x00000000
+
+
+ CNT
+ Time added after the sequence in PWM periods
+ 0
+ 23
+
+
+
+
+
+ PSEL
+ Unspecified
+ PWM_PSEL
+ read-write
+ 0x560
+
+ 0x4
+ 0x4
+ OUT[%s]
+ Description collection: Output pin select for PWM channel n
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+
+
+ PDM
+ Pulse Density Modulation (Digital Microphone) Interface
+ 0x4001D000
+
+ 0
+ 0x1000
+ registers
+
+
+ PDM
+ 29
+
+ PDM
+ 0x20
+
+
+ TASKS_START
+ Starts continuous PDM transfer
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Starts continuous PDM transfer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stops PDM transfer
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stops PDM transfer
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_STARTED
+ PDM transfer has started
+ 0x100
+ read-write
+
+
+ EVENTS_STARTED
+ PDM transfer has started
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ PDM transfer has finished
+ 0x104
+ read-write
+
+
+ EVENTS_STOPPED
+ PDM transfer has finished
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_END
+ The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM
+ 0x108
+ read-write
+
+
+ EVENTS_END
+ The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ STARTED
+ Enable or disable interrupt for event STARTED
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ STOPPED
+ Enable or disable interrupt for event STOPPED
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ END
+ Enable or disable interrupt for event END
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ STARTED
+ Write '1' to enable interrupt for event STARTED
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ END
+ Write '1' to enable interrupt for event END
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ STARTED
+ Write '1' to disable interrupt for event STARTED
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ END
+ Write '1' to disable interrupt for event END
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ENABLE
+ PDM module enable register
+ 0x500
+ read-write
+ 0x00000000
+
+
+ ENABLE
+ Enable or disable PDM module
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ PDMCLKCTRL
+ PDM clock generator control
+ 0x504
+ read-write
+ 0x08400000
+
+
+ FREQ
+ PDM_CLK frequency
+ 0
+ 31
+
+
+ 1000K
+ PDM_CLK = 32 MHz / 32 = 1.000 MHz
+ 0x08000000
+
+
+ Default
+ PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64.
+ 0x08400000
+
+
+ 1067K
+ PDM_CLK = 32 MHz / 30 = 1.067 MHz
+ 0x08800000
+
+
+ 1231K
+ PDM_CLK = 32 MHz / 26 = 1.231 MHz
+ 0x09800000
+
+
+ 1280K
+ PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80.
+ 0x0A000000
+
+
+ 1333K
+ PDM_CLK = 32 MHz / 24 = 1.333 MHz
+ 0x0A800000
+
+
+
+
+
+
+ MODE
+ Defines the routing of the connected PDM microphones' signals
+ 0x508
+ read-write
+ 0x00000000
+
+
+ OPERATION
+ Mono or stereo operation
+ 0
+ 0
+
+
+ Stereo
+ Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]
+ 0
+
+
+ Mono
+ Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]
+ 1
+
+
+
+
+ EDGE
+ Defines on which PDM_CLK edge Left (or mono) is sampled
+ 1
+ 1
+
+
+ LeftFalling
+ Left (or mono) is sampled on falling edge of PDM_CLK
+ 0
+
+
+ LeftRising
+ Left (or mono) is sampled on rising edge of PDM_CLK
+ 1
+
+
+
+
+
+
+ GAINL
+ Left output gain adjustment
+ 0x518
+ read-write
+ 0x00000028
+
+
+ GAINL
+ Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust
+ 0
+ 6
+
+
+ MinGain
+ -20dB gain adjustment (minimum)
+ 0x00
+
+
+ DefaultGain
+ 0dB gain adjustment
+ 0x28
+
+
+ MaxGain
+ +20dB gain adjustment (maximum)
+ 0x50
+
+
+
+
+
+
+ GAINR
+ Right output gain adjustment
+ 0x51C
+ read-write
+ 0x00000028
+
+
+ GAINR
+ Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
+ 0
+ 6
+
+
+ MinGain
+ -20dB gain adjustment (minimum)
+ 0x00
+
+
+ DefaultGain
+ 0dB gain adjustment
+ 0x28
+
+
+ MaxGain
+ +20dB gain adjustment (maximum)
+ 0x50
+
+
+
+
+
+
+ RATIO
+ Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly.
+ 0x520
+ read-write
+ 0x00000000
+
+
+ RATIO
+ Selects the ratio between PDM_CLK and output sample rate
+ 0
+ 0
+
+
+ Ratio64
+ Ratio of 64
+ 0
+
+
+ Ratio80
+ Ratio of 80
+ 1
+
+
+
+
+
+
+ PSEL
+ Unspecified
+ PDM_PSEL
+ read-write
+ 0x540
+
+ CLK
+ Pin number configuration for PDM CLK signal
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ DIN
+ Pin number configuration for PDM DIN signal
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+ SAMPLE
+ Unspecified
+ PDM_SAMPLE
+ read-write
+ 0x560
+
+ PTR
+ RAM address pointer to write samples to with EasyDMA
+ 0x000
+ read-write
+
+
+ SAMPLEPTR
+ Address to write PDM samples to over DMA
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Number of samples to allocate memory for in EasyDMA mode
+ 0x004
+ read-write
+
+
+ BUFFSIZE
+ Length of DMA RAM allocation in number of samples
+ 0
+ 14
+
+
+
+
+
+
+
+ ACL
+ Access control lists
+ 0x4001E000
+
+ 0
+ 0x1000
+ registers
+
+ ACL
+ 0x20
+
+
+ 8
+ 0x010
+ ACL[%s]
+ Unspecified
+ ACL_ACL
+ read-write
+ 0x800
+
+ ADDR
+ Description cluster: Configure the word-aligned start address of region n to protect
+ 0x000
+ read-writeonce
+ 0x00000000
+
+
+ ADDR
+ Valid word-aligned start address of region n to protect. Address must point to a flash page boundary.
+ 0
+ 31
+
+
+
+
+ SIZE
+ Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect.
+ 0x004
+ read-writeonce
+ 0x00000000
+
+
+ SIZE
+ Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512 kB.
+ 0
+ 31
+
+
+
+
+ PERM
+ Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE
+ 0x008
+ read-writeonce
+ 0x00000000
+
+
+ WRITE
+ Configure write and erase permissions for region n. Write '0' has no effect.
+ 1
+ 1
+
+
+ Enable
+ Allow write and erase instructions to region n
+ 0
+
+
+ Disable
+ Block write and erase instructions to region n
+ 1
+
+
+
+
+ READ
+ Configure read permissions for region n. Write '0' has no effect.
+ 2
+ 2
+
+
+ Enable
+ Allow read instructions to region n
+ 0
+
+
+ Disable
+ Block read instructions to region n
+ 1
+
+
+
+
+
+
+
+
+
+ NVMC
+ Non Volatile Memory Controller
+ 0x4001E000
+ ACL
+
+ 0
+ 0x1000
+ registers
+
+ NVMC
+ 0x20
+
+
+ READY
+ Ready flag
+ 0x400
+ read-only
+ 0x00000001
+
+
+ READY
+ NVMC is ready or busy
+ 0
+ 0
+
+
+ Busy
+ NVMC is busy (on-going write or erase operation)
+ 0
+
+
+ Ready
+ NVMC is ready
+ 1
+
+
+
+
+
+
+ READYNEXT
+ Ready flag
+ 0x408
+ read-only
+ 0x00000001
+
+
+ READYNEXT
+ NVMC can accept a new write operation
+ 0
+ 0
+
+
+ Busy
+ NVMC cannot accept any write operation
+ 0
+
+
+ Ready
+ NVMC is ready
+ 1
+
+
+
+
+
+
+ CONFIG
+ Configuration register
+ 0x504
+ read-write
+
+
+ WEN
+ Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.
+ 0
+ 1
+
+
+ Ren
+ Read only access
+ 0
+
+
+ Wen
+ Write enabled
+ 1
+
+
+ Een
+ Erase enabled
+ 2
+
+
+
+
+
+
+ ERASEPAGE
+ Register for erasing a page in code area
+ 0x508
+ write-only
+
+
+ ERASEPAGE
+ Register for starting erase of a page in code area
+ 0
+ 31
+
+
+
+
+ ERASEPCR1
+ Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE
+ 0x508
+ write-only
+ ERASEPAGE
+
+
+ ERASEPCR1
+ Register for erasing a page in code area, equivalent to ERASEPAGE
+ 0
+ 31
+
+
+
+
+ ERASEALL
+ Register for erasing all non-volatile user memory
+ 0x50C
+ write-only
+
+
+ ERASEALL
+ Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.
+ 0
+ 0
+
+
+ NoOperation
+ No operation
+ 0
+
+
+ Erase
+ Start chip erase
+ 1
+
+
+
+
+
+
+ ERASEPCR0
+ Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE
+ 0x510
+ write-only
+
+
+ ERASEPCR0
+ Register for starting erase of a page in code area, equivalent to ERASEPAGE
+ 0
+ 31
+
+
+
+
+ ERASEUICR
+ Register for erasing user information configuration registers
+ 0x514
+ write-only
+
+
+ ERASEUICR
+ Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.
+ 0
+ 0
+
+
+ NoOperation
+ No operation
+ 0
+
+
+ Erase
+ Start erase of UICR
+ 1
+
+
+
+
+
+
+ ERASEPAGEPARTIAL
+ Register for partial erase of a page in code area
+ 0x518
+ write-only
+
+
+ ERASEPAGEPARTIAL
+ Register for starting partial erase of a page in code area
+ 0
+ 31
+
+
+
+
+ ERASEPAGEPARTIALCFG
+ Register for partial erase configuration
+ 0x51C
+ read-write
+ 0x0000000A
+
+
+ DURATION
+ Duration of the partial erase in milliseconds
+ 0
+ 6
+
+
+
+
+ ICACHECNF
+ I-code cache configuration register
+ 0x540
+ read-write
+ 0x00000000
+
+
+ CACHEEN
+ Cache enable
+ 0
+ 0
+
+
+ Disabled
+ Disable cache. Invalidates all cache entries.
+ 0
+
+
+ Enabled
+ Enable cache
+ 1
+
+
+
+
+ CACHEPROFEN
+ Cache profiling enable
+ 8
+ 8
+
+
+ Disabled
+ Disable cache profiling
+ 0
+
+
+ Enabled
+ Enable cache profiling
+ 1
+
+
+
+
+
+
+ IHIT
+ I-code cache hit counter
+ 0x548
+ read-write
+
+
+ HITS
+ Number of cache hits
+ 0
+ 31
+
+
+
+
+ IMISS
+ I-code cache miss counter
+ 0x54C
+ read-write
+
+
+ MISSES
+ Number of cache misses
+ 0
+ 31
+
+
+
+
+
+
+ PPI
+ Programmable Peripheral Interconnect
+ 0x4001F000
+
+ 0
+ 0x1000
+ registers
+
+ PPI
+ 0x20
+
+
+ 6
+ 0x008
+ TASKS_CHG[%s]
+ Channel group tasks
+ PPI_TASKS_CHG
+ write-only
+ 0x000
+
+ EN
+ Description cluster: Enable channel group n
+ 0x000
+ write-only
+
+
+ EN
+ Enable channel group n
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ DIS
+ Description cluster: Disable channel group n
+ 0x004
+ write-only
+
+
+ DIS
+ Disable channel group n
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+
+ CHEN
+ Channel enable register
+ 0x500
+ read-write
+
+
+ CH0
+ Enable or disable channel 0
+ 0
+ 0
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH1
+ Enable or disable channel 1
+ 1
+ 1
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH2
+ Enable or disable channel 2
+ 2
+ 2
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH3
+ Enable or disable channel 3
+ 3
+ 3
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH4
+ Enable or disable channel 4
+ 4
+ 4
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH5
+ Enable or disable channel 5
+ 5
+ 5
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH6
+ Enable or disable channel 6
+ 6
+ 6
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH7
+ Enable or disable channel 7
+ 7
+ 7
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH8
+ Enable or disable channel 8
+ 8
+ 8
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH9
+ Enable or disable channel 9
+ 9
+ 9
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH10
+ Enable or disable channel 10
+ 10
+ 10
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH11
+ Enable or disable channel 11
+ 11
+ 11
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH12
+ Enable or disable channel 12
+ 12
+ 12
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH13
+ Enable or disable channel 13
+ 13
+ 13
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH14
+ Enable or disable channel 14
+ 14
+ 14
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH15
+ Enable or disable channel 15
+ 15
+ 15
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH16
+ Enable or disable channel 16
+ 16
+ 16
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH17
+ Enable or disable channel 17
+ 17
+ 17
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH18
+ Enable or disable channel 18
+ 18
+ 18
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH19
+ Enable or disable channel 19
+ 19
+ 19
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH20
+ Enable or disable channel 20
+ 20
+ 20
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH21
+ Enable or disable channel 21
+ 21
+ 21
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH22
+ Enable or disable channel 22
+ 22
+ 22
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH23
+ Enable or disable channel 23
+ 23
+ 23
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH24
+ Enable or disable channel 24
+ 24
+ 24
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH25
+ Enable or disable channel 25
+ 25
+ 25
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH26
+ Enable or disable channel 26
+ 26
+ 26
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH27
+ Enable or disable channel 27
+ 27
+ 27
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH28
+ Enable or disable channel 28
+ 28
+ 28
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH29
+ Enable or disable channel 29
+ 29
+ 29
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH30
+ Enable or disable channel 30
+ 30
+ 30
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+ CH31
+ Enable or disable channel 31
+ 31
+ 31
+
+
+ Disabled
+ Disable channel
+ 0
+
+
+ Enabled
+ Enable channel
+ 1
+
+
+
+
+
+
+ CHENSET
+ Channel enable set register
+ 0x504
+ read-write
+ oneToSet
+
+
+ CH0
+ Channel 0 enable set register. Writing '0' has no effect
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH1
+ Channel 1 enable set register. Writing '0' has no effect
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH2
+ Channel 2 enable set register. Writing '0' has no effect
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH3
+ Channel 3 enable set register. Writing '0' has no effect
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH4
+ Channel 4 enable set register. Writing '0' has no effect
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH5
+ Channel 5 enable set register. Writing '0' has no effect
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH6
+ Channel 6 enable set register. Writing '0' has no effect
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH7
+ Channel 7 enable set register. Writing '0' has no effect
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH8
+ Channel 8 enable set register. Writing '0' has no effect
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH9
+ Channel 9 enable set register. Writing '0' has no effect
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH10
+ Channel 10 enable set register. Writing '0' has no effect
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH11
+ Channel 11 enable set register. Writing '0' has no effect
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH12
+ Channel 12 enable set register. Writing '0' has no effect
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH13
+ Channel 13 enable set register. Writing '0' has no effect
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH14
+ Channel 14 enable set register. Writing '0' has no effect
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH15
+ Channel 15 enable set register. Writing '0' has no effect
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH16
+ Channel 16 enable set register. Writing '0' has no effect
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH17
+ Channel 17 enable set register. Writing '0' has no effect
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH18
+ Channel 18 enable set register. Writing '0' has no effect
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH19
+ Channel 19 enable set register. Writing '0' has no effect
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH20
+ Channel 20 enable set register. Writing '0' has no effect
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH21
+ Channel 21 enable set register. Writing '0' has no effect
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH22
+ Channel 22 enable set register. Writing '0' has no effect
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH23
+ Channel 23 enable set register. Writing '0' has no effect
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH24
+ Channel 24 enable set register. Writing '0' has no effect
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH25
+ Channel 25 enable set register. Writing '0' has no effect
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH26
+ Channel 26 enable set register. Writing '0' has no effect
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH27
+ Channel 27 enable set register. Writing '0' has no effect
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH28
+ Channel 28 enable set register. Writing '0' has no effect
+ 28
+ 28
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH29
+ Channel 29 enable set register. Writing '0' has no effect
+ 29
+ 29
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH30
+ Channel 30 enable set register. Writing '0' has no effect
+ 30
+ 30
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+ CH31
+ Channel 31 enable set register. Writing '0' has no effect
+ 31
+ 31
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Set
+ Write: Enable channel
+ 1
+
+
+
+
+
+
+ CHENCLR
+ Channel enable clear register
+ 0x508
+ read-write
+ oneToClear
+
+
+ CH0
+ Channel 0 enable clear register. Writing '0' has no effect
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH1
+ Channel 1 enable clear register. Writing '0' has no effect
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH2
+ Channel 2 enable clear register. Writing '0' has no effect
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH3
+ Channel 3 enable clear register. Writing '0' has no effect
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH4
+ Channel 4 enable clear register. Writing '0' has no effect
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH5
+ Channel 5 enable clear register. Writing '0' has no effect
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH6
+ Channel 6 enable clear register. Writing '0' has no effect
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH7
+ Channel 7 enable clear register. Writing '0' has no effect
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH8
+ Channel 8 enable clear register. Writing '0' has no effect
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH9
+ Channel 9 enable clear register. Writing '0' has no effect
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH10
+ Channel 10 enable clear register. Writing '0' has no effect
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH11
+ Channel 11 enable clear register. Writing '0' has no effect
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH12
+ Channel 12 enable clear register. Writing '0' has no effect
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH13
+ Channel 13 enable clear register. Writing '0' has no effect
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH14
+ Channel 14 enable clear register. Writing '0' has no effect
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH15
+ Channel 15 enable clear register. Writing '0' has no effect
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH16
+ Channel 16 enable clear register. Writing '0' has no effect
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH17
+ Channel 17 enable clear register. Writing '0' has no effect
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH18
+ Channel 18 enable clear register. Writing '0' has no effect
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH19
+ Channel 19 enable clear register. Writing '0' has no effect
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH20
+ Channel 20 enable clear register. Writing '0' has no effect
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH21
+ Channel 21 enable clear register. Writing '0' has no effect
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH22
+ Channel 22 enable clear register. Writing '0' has no effect
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH23
+ Channel 23 enable clear register. Writing '0' has no effect
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH24
+ Channel 24 enable clear register. Writing '0' has no effect
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH25
+ Channel 25 enable clear register. Writing '0' has no effect
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH26
+ Channel 26 enable clear register. Writing '0' has no effect
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH27
+ Channel 27 enable clear register. Writing '0' has no effect
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH28
+ Channel 28 enable clear register. Writing '0' has no effect
+ 28
+ 28
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH29
+ Channel 29 enable clear register. Writing '0' has no effect
+ 29
+ 29
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH30
+ Channel 30 enable clear register. Writing '0' has no effect
+ 30
+ 30
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+ CH31
+ Channel 31 enable clear register. Writing '0' has no effect
+ 31
+ 31
+
+ read
+
+ Disabled
+ Read: channel disabled
+ 0
+
+
+ Enabled
+ Read: channel enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Write: disable channel
+ 1
+
+
+
+
+
+
+ 20
+ 0x008
+ CH[%s]
+ PPI Channel
+ PPI_CH
+ read-write
+ 0x510
+
+ EEP
+ Description cluster: Channel n event end-point
+ 0x000
+ read-write
+
+
+ EEP
+ Pointer to event register. Accepts only addresses to registers from the Event group.
+ 0
+ 31
+
+
+
+
+ TEP
+ Description cluster: Channel n task end-point
+ 0x004
+ read-write
+
+
+ TEP
+ Pointer to task register. Accepts only addresses to registers from the Task group.
+ 0
+ 31
+
+
+
+
+
+ 0x6
+ 0x4
+ CHG[%s]
+ Description collection: Channel group n
+ 0x800
+ read-write
+
+
+ CH0
+ Include or exclude channel 0
+ 0
+ 0
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH1
+ Include or exclude channel 1
+ 1
+ 1
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH2
+ Include or exclude channel 2
+ 2
+ 2
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH3
+ Include or exclude channel 3
+ 3
+ 3
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH4
+ Include or exclude channel 4
+ 4
+ 4
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH5
+ Include or exclude channel 5
+ 5
+ 5
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH6
+ Include or exclude channel 6
+ 6
+ 6
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH7
+ Include or exclude channel 7
+ 7
+ 7
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH8
+ Include or exclude channel 8
+ 8
+ 8
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH9
+ Include or exclude channel 9
+ 9
+ 9
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH10
+ Include or exclude channel 10
+ 10
+ 10
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH11
+ Include or exclude channel 11
+ 11
+ 11
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH12
+ Include or exclude channel 12
+ 12
+ 12
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH13
+ Include or exclude channel 13
+ 13
+ 13
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH14
+ Include or exclude channel 14
+ 14
+ 14
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH15
+ Include or exclude channel 15
+ 15
+ 15
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH16
+ Include or exclude channel 16
+ 16
+ 16
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH17
+ Include or exclude channel 17
+ 17
+ 17
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH18
+ Include or exclude channel 18
+ 18
+ 18
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH19
+ Include or exclude channel 19
+ 19
+ 19
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH20
+ Include or exclude channel 20
+ 20
+ 20
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH21
+ Include or exclude channel 21
+ 21
+ 21
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH22
+ Include or exclude channel 22
+ 22
+ 22
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH23
+ Include or exclude channel 23
+ 23
+ 23
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH24
+ Include or exclude channel 24
+ 24
+ 24
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH25
+ Include or exclude channel 25
+ 25
+ 25
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH26
+ Include or exclude channel 26
+ 26
+ 26
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH27
+ Include or exclude channel 27
+ 27
+ 27
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH28
+ Include or exclude channel 28
+ 28
+ 28
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH29
+ Include or exclude channel 29
+ 29
+ 29
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH30
+ Include or exclude channel 30
+ 30
+ 30
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+ CH31
+ Include or exclude channel 31
+ 31
+ 31
+
+
+ Excluded
+ Exclude
+ 0
+
+
+ Included
+ Include
+ 1
+
+
+
+
+
+
+ 32
+ 0x004
+ FORK[%s]
+ Fork
+ PPI_FORK
+ read-write
+ 0x910
+
+ TEP
+ Description cluster: Channel n task end-point
+ 0x000
+ read-write
+
+
+ TEP
+ Pointer to task register
+ 0
+ 31
+
+
+
+
+
+
+
+ MWU
+ Memory Watch Unit
+ 0x40020000
+
+ 0
+ 0x1000
+ registers
+
+
+ MWU
+ 32
+
+ MWU
+ 0x20
+
+
+ 4
+ 0x008
+ EVENTS_REGION[%s]
+ Peripheral events.
+ MWU_EVENTS_REGION
+ read-write
+ 0x100
+
+ WA
+ Description cluster: Write access to region n detected
+ 0x000
+ read-write
+
+
+ WA
+ Write access to region n detected
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ RA
+ Description cluster: Read access to region n detected
+ 0x004
+ read-write
+
+
+ RA
+ Read access to region n detected
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+
+ 2
+ 0x008
+ EVENTS_PREGION[%s]
+ Peripheral events.
+ MWU_EVENTS_PREGION
+ read-write
+ 0x160
+
+ WA
+ Description cluster: Write access to peripheral region n detected
+ 0x000
+ read-write
+
+
+ WA
+ Write access to peripheral region n detected
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ RA
+ Description cluster: Read access to peripheral region n detected
+ 0x004
+ read-write
+
+
+ RA
+ Read access to peripheral region n detected
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ REGION0WA
+ Enable or disable interrupt for event REGION0WA
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION0RA
+ Enable or disable interrupt for event REGION0RA
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION1WA
+ Enable or disable interrupt for event REGION1WA
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION1RA
+ Enable or disable interrupt for event REGION1RA
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION2WA
+ Enable or disable interrupt for event REGION2WA
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION2RA
+ Enable or disable interrupt for event REGION2RA
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION3WA
+ Enable or disable interrupt for event REGION3WA
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION3RA
+ Enable or disable interrupt for event REGION3RA
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ PREGION0WA
+ Enable or disable interrupt for event PREGION0WA
+ 24
+ 24
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ PREGION0RA
+ Enable or disable interrupt for event PREGION0RA
+ 25
+ 25
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ PREGION1WA
+ Enable or disable interrupt for event PREGION1WA
+ 26
+ 26
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ PREGION1RA
+ Enable or disable interrupt for event PREGION1RA
+ 27
+ 27
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ REGION0WA
+ Write '1' to enable interrupt for event REGION0WA
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION0RA
+ Write '1' to enable interrupt for event REGION0RA
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION1WA
+ Write '1' to enable interrupt for event REGION1WA
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION1RA
+ Write '1' to enable interrupt for event REGION1RA
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION2WA
+ Write '1' to enable interrupt for event REGION2WA
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION2RA
+ Write '1' to enable interrupt for event REGION2RA
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION3WA
+ Write '1' to enable interrupt for event REGION3WA
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION3RA
+ Write '1' to enable interrupt for event REGION3RA
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PREGION0WA
+ Write '1' to enable interrupt for event PREGION0WA
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PREGION0RA
+ Write '1' to enable interrupt for event PREGION0RA
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PREGION1WA
+ Write '1' to enable interrupt for event PREGION1WA
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PREGION1RA
+ Write '1' to enable interrupt for event PREGION1RA
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ REGION0WA
+ Write '1' to disable interrupt for event REGION0WA
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION0RA
+ Write '1' to disable interrupt for event REGION0RA
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION1WA
+ Write '1' to disable interrupt for event REGION1WA
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION1RA
+ Write '1' to disable interrupt for event REGION1RA
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION2WA
+ Write '1' to disable interrupt for event REGION2WA
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION2RA
+ Write '1' to disable interrupt for event REGION2RA
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION3WA
+ Write '1' to disable interrupt for event REGION3WA
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION3RA
+ Write '1' to disable interrupt for event REGION3RA
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PREGION0WA
+ Write '1' to disable interrupt for event PREGION0WA
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PREGION0RA
+ Write '1' to disable interrupt for event PREGION0RA
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PREGION1WA
+ Write '1' to disable interrupt for event PREGION1WA
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PREGION1RA
+ Write '1' to disable interrupt for event PREGION1RA
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ NMIEN
+ Enable or disable interrupt
+ 0x320
+ read-write
+
+
+ REGION0WA
+ Enable or disable interrupt for event REGION0WA
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION0RA
+ Enable or disable interrupt for event REGION0RA
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION1WA
+ Enable or disable interrupt for event REGION1WA
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION1RA
+ Enable or disable interrupt for event REGION1RA
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION2WA
+ Enable or disable interrupt for event REGION2WA
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION2RA
+ Enable or disable interrupt for event REGION2RA
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION3WA
+ Enable or disable interrupt for event REGION3WA
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ REGION3RA
+ Enable or disable interrupt for event REGION3RA
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ PREGION0WA
+ Enable or disable interrupt for event PREGION0WA
+ 24
+ 24
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ PREGION0RA
+ Enable or disable interrupt for event PREGION0RA
+ 25
+ 25
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ PREGION1WA
+ Enable or disable interrupt for event PREGION1WA
+ 26
+ 26
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ PREGION1RA
+ Enable or disable interrupt for event PREGION1RA
+ 27
+ 27
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ NMIENSET
+ Enable interrupt
+ 0x324
+ read-write
+
+
+ REGION0WA
+ Write '1' to enable interrupt for event REGION0WA
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION0RA
+ Write '1' to enable interrupt for event REGION0RA
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION1WA
+ Write '1' to enable interrupt for event REGION1WA
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION1RA
+ Write '1' to enable interrupt for event REGION1RA
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION2WA
+ Write '1' to enable interrupt for event REGION2WA
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION2RA
+ Write '1' to enable interrupt for event REGION2RA
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION3WA
+ Write '1' to enable interrupt for event REGION3WA
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ REGION3RA
+ Write '1' to enable interrupt for event REGION3RA
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PREGION0WA
+ Write '1' to enable interrupt for event PREGION0WA
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PREGION0RA
+ Write '1' to enable interrupt for event PREGION0RA
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PREGION1WA
+ Write '1' to enable interrupt for event PREGION1WA
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ PREGION1RA
+ Write '1' to enable interrupt for event PREGION1RA
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ NMIENCLR
+ Disable interrupt
+ 0x328
+ read-write
+
+
+ REGION0WA
+ Write '1' to disable interrupt for event REGION0WA
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION0RA
+ Write '1' to disable interrupt for event REGION0RA
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION1WA
+ Write '1' to disable interrupt for event REGION1WA
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION1RA
+ Write '1' to disable interrupt for event REGION1RA
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION2WA
+ Write '1' to disable interrupt for event REGION2WA
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION2RA
+ Write '1' to disable interrupt for event REGION2RA
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION3WA
+ Write '1' to disable interrupt for event REGION3WA
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ REGION3RA
+ Write '1' to disable interrupt for event REGION3RA
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PREGION0WA
+ Write '1' to disable interrupt for event PREGION0WA
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PREGION0RA
+ Write '1' to disable interrupt for event PREGION0RA
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PREGION1WA
+ Write '1' to disable interrupt for event PREGION1WA
+ 26
+ 26
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ PREGION1RA
+ Write '1' to disable interrupt for event PREGION1RA
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ 2
+ 0x008
+ PERREGION[%s]
+ Unspecified
+ MWU_PERREGION
+ read-write
+ 0x400
+
+ SUBSTATWA
+ Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching
+ 0x000
+ read-write
+ oneToClear
+
+
+ SR0
+ Subregion 0 in region n (write '1' to clear)
+ 0
+ 0
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR1
+ Subregion 1 in region n (write '1' to clear)
+ 1
+ 1
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR2
+ Subregion 2 in region n (write '1' to clear)
+ 2
+ 2
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR3
+ Subregion 3 in region n (write '1' to clear)
+ 3
+ 3
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR4
+ Subregion 4 in region n (write '1' to clear)
+ 4
+ 4
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR5
+ Subregion 5 in region n (write '1' to clear)
+ 5
+ 5
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR6
+ Subregion 6 in region n (write '1' to clear)
+ 6
+ 6
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR7
+ Subregion 7 in region n (write '1' to clear)
+ 7
+ 7
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR8
+ Subregion 8 in region n (write '1' to clear)
+ 8
+ 8
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR9
+ Subregion 9 in region n (write '1' to clear)
+ 9
+ 9
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR10
+ Subregion 10 in region n (write '1' to clear)
+ 10
+ 10
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR11
+ Subregion 11 in region n (write '1' to clear)
+ 11
+ 11
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR12
+ Subregion 12 in region n (write '1' to clear)
+ 12
+ 12
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR13
+ Subregion 13 in region n (write '1' to clear)
+ 13
+ 13
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR14
+ Subregion 14 in region n (write '1' to clear)
+ 14
+ 14
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR15
+ Subregion 15 in region n (write '1' to clear)
+ 15
+ 15
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR16
+ Subregion 16 in region n (write '1' to clear)
+ 16
+ 16
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR17
+ Subregion 17 in region n (write '1' to clear)
+ 17
+ 17
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR18
+ Subregion 18 in region n (write '1' to clear)
+ 18
+ 18
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR19
+ Subregion 19 in region n (write '1' to clear)
+ 19
+ 19
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR20
+ Subregion 20 in region n (write '1' to clear)
+ 20
+ 20
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR21
+ Subregion 21 in region n (write '1' to clear)
+ 21
+ 21
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR22
+ Subregion 22 in region n (write '1' to clear)
+ 22
+ 22
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR23
+ Subregion 23 in region n (write '1' to clear)
+ 23
+ 23
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR24
+ Subregion 24 in region n (write '1' to clear)
+ 24
+ 24
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR25
+ Subregion 25 in region n (write '1' to clear)
+ 25
+ 25
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR26
+ Subregion 26 in region n (write '1' to clear)
+ 26
+ 26
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR27
+ Subregion 27 in region n (write '1' to clear)
+ 27
+ 27
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR28
+ Subregion 28 in region n (write '1' to clear)
+ 28
+ 28
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR29
+ Subregion 29 in region n (write '1' to clear)
+ 29
+ 29
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR30
+ Subregion 30 in region n (write '1' to clear)
+ 30
+ 30
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR31
+ Subregion 31 in region n (write '1' to clear)
+ 31
+ 31
+
+
+ NoAccess
+ No write access occurred in this subregion
+ 0
+
+
+ Access
+ Write access(es) occurred in this subregion
+ 1
+
+
+
+
+
+
+ SUBSTATRA
+ Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching
+ 0x004
+ read-write
+ oneToClear
+
+
+ SR0
+ Subregion 0 in region n (write '1' to clear)
+ 0
+ 0
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR1
+ Subregion 1 in region n (write '1' to clear)
+ 1
+ 1
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR2
+ Subregion 2 in region n (write '1' to clear)
+ 2
+ 2
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR3
+ Subregion 3 in region n (write '1' to clear)
+ 3
+ 3
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR4
+ Subregion 4 in region n (write '1' to clear)
+ 4
+ 4
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR5
+ Subregion 5 in region n (write '1' to clear)
+ 5
+ 5
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR6
+ Subregion 6 in region n (write '1' to clear)
+ 6
+ 6
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR7
+ Subregion 7 in region n (write '1' to clear)
+ 7
+ 7
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR8
+ Subregion 8 in region n (write '1' to clear)
+ 8
+ 8
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR9
+ Subregion 9 in region n (write '1' to clear)
+ 9
+ 9
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR10
+ Subregion 10 in region n (write '1' to clear)
+ 10
+ 10
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR11
+ Subregion 11 in region n (write '1' to clear)
+ 11
+ 11
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR12
+ Subregion 12 in region n (write '1' to clear)
+ 12
+ 12
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR13
+ Subregion 13 in region n (write '1' to clear)
+ 13
+ 13
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR14
+ Subregion 14 in region n (write '1' to clear)
+ 14
+ 14
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR15
+ Subregion 15 in region n (write '1' to clear)
+ 15
+ 15
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR16
+ Subregion 16 in region n (write '1' to clear)
+ 16
+ 16
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR17
+ Subregion 17 in region n (write '1' to clear)
+ 17
+ 17
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR18
+ Subregion 18 in region n (write '1' to clear)
+ 18
+ 18
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR19
+ Subregion 19 in region n (write '1' to clear)
+ 19
+ 19
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR20
+ Subregion 20 in region n (write '1' to clear)
+ 20
+ 20
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR21
+ Subregion 21 in region n (write '1' to clear)
+ 21
+ 21
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR22
+ Subregion 22 in region n (write '1' to clear)
+ 22
+ 22
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR23
+ Subregion 23 in region n (write '1' to clear)
+ 23
+ 23
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR24
+ Subregion 24 in region n (write '1' to clear)
+ 24
+ 24
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR25
+ Subregion 25 in region n (write '1' to clear)
+ 25
+ 25
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR26
+ Subregion 26 in region n (write '1' to clear)
+ 26
+ 26
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR27
+ Subregion 27 in region n (write '1' to clear)
+ 27
+ 27
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR28
+ Subregion 28 in region n (write '1' to clear)
+ 28
+ 28
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR29
+ Subregion 29 in region n (write '1' to clear)
+ 29
+ 29
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR30
+ Subregion 30 in region n (write '1' to clear)
+ 30
+ 30
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+ SR31
+ Subregion 31 in region n (write '1' to clear)
+ 31
+ 31
+
+
+ NoAccess
+ No read access occurred in this subregion
+ 0
+
+
+ Access
+ Read access(es) occurred in this subregion
+ 1
+
+
+
+
+
+
+
+ REGIONEN
+ Enable/disable regions watch
+ 0x510
+ read-write
+
+
+ RGN0WA
+ Enable/disable write access watch in region[0]
+ 0
+ 0
+
+
+ Disable
+ Disable write access watch in this region
+ 0
+
+
+ Enable
+ Enable write access watch in this region
+ 1
+
+
+
+
+ RGN0RA
+ Enable/disable read access watch in region[0]
+ 1
+ 1
+
+
+ Disable
+ Disable read access watch in this region
+ 0
+
+
+ Enable
+ Enable read access watch in this region
+ 1
+
+
+
+
+ RGN1WA
+ Enable/disable write access watch in region[1]
+ 2
+ 2
+
+
+ Disable
+ Disable write access watch in this region
+ 0
+
+
+ Enable
+ Enable write access watch in this region
+ 1
+
+
+
+
+ RGN1RA
+ Enable/disable read access watch in region[1]
+ 3
+ 3
+
+
+ Disable
+ Disable read access watch in this region
+ 0
+
+
+ Enable
+ Enable read access watch in this region
+ 1
+
+
+
+
+ RGN2WA
+ Enable/disable write access watch in region[2]
+ 4
+ 4
+
+
+ Disable
+ Disable write access watch in this region
+ 0
+
+
+ Enable
+ Enable write access watch in this region
+ 1
+
+
+
+
+ RGN2RA
+ Enable/disable read access watch in region[2]
+ 5
+ 5
+
+
+ Disable
+ Disable read access watch in this region
+ 0
+
+
+ Enable
+ Enable read access watch in this region
+ 1
+
+
+
+
+ RGN3WA
+ Enable/disable write access watch in region[3]
+ 6
+ 6
+
+
+ Disable
+ Disable write access watch in this region
+ 0
+
+
+ Enable
+ Enable write access watch in this region
+ 1
+
+
+
+
+ RGN3RA
+ Enable/disable read access watch in region[3]
+ 7
+ 7
+
+
+ Disable
+ Disable read access watch in this region
+ 0
+
+
+ Enable
+ Enable read access watch in this region
+ 1
+
+
+
+
+ PRGN0WA
+ Enable/disable write access watch in PREGION[0]
+ 24
+ 24
+
+
+ Disable
+ Disable write access watch in this PREGION
+ 0
+
+
+ Enable
+ Enable write access watch in this PREGION
+ 1
+
+
+
+
+ PRGN0RA
+ Enable/disable read access watch in PREGION[0]
+ 25
+ 25
+
+
+ Disable
+ Disable read access watch in this PREGION
+ 0
+
+
+ Enable
+ Enable read access watch in this PREGION
+ 1
+
+
+
+
+ PRGN1WA
+ Enable/disable write access watch in PREGION[1]
+ 26
+ 26
+
+
+ Disable
+ Disable write access watch in this PREGION
+ 0
+
+
+ Enable
+ Enable write access watch in this PREGION
+ 1
+
+
+
+
+ PRGN1RA
+ Enable/disable read access watch in PREGION[1]
+ 27
+ 27
+
+
+ Disable
+ Disable read access watch in this PREGION
+ 0
+
+
+ Enable
+ Enable read access watch in this PREGION
+ 1
+
+
+
+
+
+
+ REGIONENSET
+ Enable regions watch
+ 0x514
+ read-write
+
+
+ RGN0WA
+ Enable write access watch in region[0]
+ 0
+ 0
+
+ read
+
+ Disabled
+ Write access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable write access watch in this region
+ 1
+
+
+
+
+ RGN0RA
+ Enable read access watch in region[0]
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable read access watch in this region
+ 1
+
+
+
+
+ RGN1WA
+ Enable write access watch in region[1]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Write access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable write access watch in this region
+ 1
+
+
+
+
+ RGN1RA
+ Enable read access watch in region[1]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable read access watch in this region
+ 1
+
+
+
+
+ RGN2WA
+ Enable write access watch in region[2]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Write access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable write access watch in this region
+ 1
+
+
+
+
+ RGN2RA
+ Enable read access watch in region[2]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable read access watch in this region
+ 1
+
+
+
+
+ RGN3WA
+ Enable write access watch in region[3]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Write access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable write access watch in this region
+ 1
+
+
+
+
+ RGN3RA
+ Enable read access watch in region[3]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable read access watch in this region
+ 1
+
+
+
+
+ PRGN0WA
+ Enable write access watch in PREGION[0]
+ 24
+ 24
+
+ read
+
+ Disabled
+ Write access watch in this PREGION is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this PREGION is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable write access watch in this PREGION
+ 1
+
+
+
+
+ PRGN0RA
+ Enable read access watch in PREGION[0]
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read access watch in this PREGION is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this PREGION is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable read access watch in this PREGION
+ 1
+
+
+
+
+ PRGN1WA
+ Enable write access watch in PREGION[1]
+ 26
+ 26
+
+ read
+
+ Disabled
+ Write access watch in this PREGION is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this PREGION is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable write access watch in this PREGION
+ 1
+
+
+
+
+ PRGN1RA
+ Enable read access watch in PREGION[1]
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read access watch in this PREGION is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this PREGION is enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable read access watch in this PREGION
+ 1
+
+
+
+
+
+
+ REGIONENCLR
+ Disable regions watch
+ 0x518
+ read-write
+
+
+ RGN0WA
+ Disable write access watch in region[0]
+ 0
+ 0
+
+ read
+
+ Disabled
+ Write access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable write access watch in this region
+ 1
+
+
+
+
+ RGN0RA
+ Disable read access watch in region[0]
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable read access watch in this region
+ 1
+
+
+
+
+ RGN1WA
+ Disable write access watch in region[1]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Write access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable write access watch in this region
+ 1
+
+
+
+
+ RGN1RA
+ Disable read access watch in region[1]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable read access watch in this region
+ 1
+
+
+
+
+ RGN2WA
+ Disable write access watch in region[2]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Write access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable write access watch in this region
+ 1
+
+
+
+
+ RGN2RA
+ Disable read access watch in region[2]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable read access watch in this region
+ 1
+
+
+
+
+ RGN3WA
+ Disable write access watch in region[3]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Write access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable write access watch in this region
+ 1
+
+
+
+
+ RGN3RA
+ Disable read access watch in region[3]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read access watch in this region is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this region is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable read access watch in this region
+ 1
+
+
+
+
+ PRGN0WA
+ Disable write access watch in PREGION[0]
+ 24
+ 24
+
+ read
+
+ Disabled
+ Write access watch in this PREGION is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this PREGION is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable write access watch in this PREGION
+ 1
+
+
+
+
+ PRGN0RA
+ Disable read access watch in PREGION[0]
+ 25
+ 25
+
+ read
+
+ Disabled
+ Read access watch in this PREGION is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this PREGION is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable read access watch in this PREGION
+ 1
+
+
+
+
+ PRGN1WA
+ Disable write access watch in PREGION[1]
+ 26
+ 26
+
+ read
+
+ Disabled
+ Write access watch in this PREGION is disabled
+ 0
+
+
+ Enabled
+ Write access watch in this PREGION is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable write access watch in this PREGION
+ 1
+
+
+
+
+ PRGN1RA
+ Disable read access watch in PREGION[1]
+ 27
+ 27
+
+ read
+
+ Disabled
+ Read access watch in this PREGION is disabled
+ 0
+
+
+ Enabled
+ Read access watch in this PREGION is enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable read access watch in this PREGION
+ 1
+
+
+
+
+
+
+ 4
+ 0x010
+ REGION[%s]
+ Unspecified
+ MWU_REGION
+ read-write
+ 0x600
+
+ START
+ Description cluster: Start address for region n
+ 0x000
+ read-write
+ 0x00000000
+
+
+ START
+ Start address for region
+ 0
+ 31
+
+
+
+
+ END
+ Description cluster: End address of region n
+ 0x004
+ read-write
+
+
+ END
+ End address of region.
+ 0
+ 31
+
+
+
+
+
+ 2
+ 0x010
+ PREGION[%s]
+ Unspecified
+ MWU_PREGION
+ read-write
+ 0x6C0
+
+ START
+ Description cluster: Reserved for future use
+ 0x000
+ read-only
+
+
+ START
+ Reserved for future use
+ 0
+ 31
+
+
+
+
+ END
+ Description cluster: Reserved for future use
+ 0x004
+ read-only
+
+
+ END
+ Reserved for future use
+ 0
+ 31
+
+
+
+
+ SUBS
+ Description cluster: Subregions of region n
+ 0x008
+ read-write
+ 0x00000000
+
+
+ SR0
+ Include or exclude subregion 0 in region
+ 0
+ 0
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR1
+ Include or exclude subregion 1 in region
+ 1
+ 1
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR2
+ Include or exclude subregion 2 in region
+ 2
+ 2
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR3
+ Include or exclude subregion 3 in region
+ 3
+ 3
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR4
+ Include or exclude subregion 4 in region
+ 4
+ 4
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR5
+ Include or exclude subregion 5 in region
+ 5
+ 5
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR6
+ Include or exclude subregion 6 in region
+ 6
+ 6
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR7
+ Include or exclude subregion 7 in region
+ 7
+ 7
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR8
+ Include or exclude subregion 8 in region
+ 8
+ 8
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR9
+ Include or exclude subregion 9 in region
+ 9
+ 9
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR10
+ Include or exclude subregion 10 in region
+ 10
+ 10
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR11
+ Include or exclude subregion 11 in region
+ 11
+ 11
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR12
+ Include or exclude subregion 12 in region
+ 12
+ 12
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR13
+ Include or exclude subregion 13 in region
+ 13
+ 13
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR14
+ Include or exclude subregion 14 in region
+ 14
+ 14
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR15
+ Include or exclude subregion 15 in region
+ 15
+ 15
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR16
+ Include or exclude subregion 16 in region
+ 16
+ 16
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR17
+ Include or exclude subregion 17 in region
+ 17
+ 17
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR18
+ Include or exclude subregion 18 in region
+ 18
+ 18
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR19
+ Include or exclude subregion 19 in region
+ 19
+ 19
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR20
+ Include or exclude subregion 20 in region
+ 20
+ 20
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR21
+ Include or exclude subregion 21 in region
+ 21
+ 21
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR22
+ Include or exclude subregion 22 in region
+ 22
+ 22
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR23
+ Include or exclude subregion 23 in region
+ 23
+ 23
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR24
+ Include or exclude subregion 24 in region
+ 24
+ 24
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR25
+ Include or exclude subregion 25 in region
+ 25
+ 25
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR26
+ Include or exclude subregion 26 in region
+ 26
+ 26
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR27
+ Include or exclude subregion 27 in region
+ 27
+ 27
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR28
+ Include or exclude subregion 28 in region
+ 28
+ 28
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR29
+ Include or exclude subregion 29 in region
+ 29
+ 29
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR30
+ Include or exclude subregion 30 in region
+ 30
+ 30
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+ SR31
+ Include or exclude subregion 31 in region
+ 31
+ 31
+
+
+ Exclude
+ Exclude
+ 0
+
+
+ Include
+ Include
+ 1
+
+
+
+
+
+
+
+
+
+ PWM1
+ Pulse width modulation unit 1
+ 0x40021000
+
+ PWM1
+ 33
+
+
+
+ PWM2
+ Pulse width modulation unit 2
+ 0x40022000
+
+ PWM2
+ 34
+
+
+
+ SPI2
+ Serial Peripheral Interface 2
+ 0x40023000
+
+ SPIM2_SPIS2_SPI2
+ 35
+
+
+
+ SPIM2
+ Serial Peripheral Interface Master with EasyDMA 2
+ 0x40023000
+ SPI2
+
+ SPIM2_SPIS2_SPI2
+ 35
+
+
+
+ SPIS2
+ SPI Slave 2
+ 0x40023000
+ SPI2
+
+ SPIM2_SPIS2_SPI2
+ 35
+
+
+
+ RTC2
+ Real time counter 2
+ 0x40024000
+
+ RTC2
+ 36
+
+
+
+ I2S
+ Inter-IC Sound
+ 0x40025000
+
+ 0
+ 0x1000
+ registers
+
+
+ I2S
+ 37
+
+ I2S
+ 0x20
+
+
+ TASKS_START
+ Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
+ 0x000
+ write-only
+
+
+ TASKS_START
+ Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STOP
+ Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.
+ 0x004
+ write-only
+
+
+ TASKS_STOP
+ Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_RXPTRUPD
+ The RXD.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.
+ 0x104
+ read-write
+
+
+ EVENTS_RXPTRUPD
+ The RXD.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_STOPPED
+ I2S transfer stopped.
+ 0x108
+ read-write
+
+
+ EVENTS_STOPPED
+ I2S transfer stopped.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_TXPTRUPD
+ The TDX.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
+ 0x114
+ read-write
+
+
+ EVENTS_TXPTRUPD
+ The TDX.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ RXPTRUPD
+ Enable or disable interrupt for event RXPTRUPD
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ STOPPED
+ Enable or disable interrupt for event STOPPED
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ TXPTRUPD
+ Enable or disable interrupt for event TXPTRUPD
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ RXPTRUPD
+ Write '1' to enable interrupt for event RXPTRUPD
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ STOPPED
+ Write '1' to enable interrupt for event STOPPED
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ TXPTRUPD
+ Write '1' to enable interrupt for event TXPTRUPD
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ RXPTRUPD
+ Write '1' to disable interrupt for event RXPTRUPD
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ STOPPED
+ Write '1' to disable interrupt for event STOPPED
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ TXPTRUPD
+ Write '1' to disable interrupt for event TXPTRUPD
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ ENABLE
+ Enable I2S module.
+ 0x500
+ read-write
+ 0x00000000
+
+
+ ENABLE
+ Enable I2S module.
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ CONFIG
+ Unspecified
+ I2S_CONFIG
+ read-write
+ 0x504
+
+ MODE
+ I2S mode.
+ 0x000
+ read-write
+ 0x00000000
+
+
+ MODE
+ I2S mode.
+ 0
+ 0
+
+
+ Master
+ Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx.
+ 0
+
+
+ Slave
+ Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx
+ 1
+
+
+
+
+
+
+ RXEN
+ Reception (RX) enable.
+ 0x004
+ read-write
+ 0x00000000
+
+
+ RXEN
+ Reception (RX) enable.
+ 0
+ 0
+
+
+ Disabled
+ Reception disabled and now data will be written to the RXD.PTR address.
+ 0
+
+
+ Enabled
+ Reception enabled.
+ 1
+
+
+
+
+
+
+ TXEN
+ Transmission (TX) enable.
+ 0x008
+ read-write
+ 0x00000001
+
+
+ TXEN
+ Transmission (TX) enable.
+ 0
+ 0
+
+
+ Disabled
+ Transmission disabled and now data will be read from the RXD.TXD address.
+ 0
+
+
+ Enabled
+ Transmission enabled.
+ 1
+
+
+
+
+
+
+ MCKEN
+ Master clock generator enable.
+ 0x00C
+ read-write
+ 0x00000001
+
+
+ MCKEN
+ Master clock generator enable.
+ 0
+ 0
+
+
+ Disabled
+ Master clock generator disabled and PSEL.MCK not connected(available as GPIO).
+ 0
+
+
+ Enabled
+ Master clock generator running and MCK output on PSEL.MCK.
+ 1
+
+
+
+
+
+
+ MCKFREQ
+ Master clock generator frequency.
+ 0x010
+ read-write
+ 0x20000000
+
+
+ MCKFREQ
+ Master clock generator frequency.
+ 0
+ 31
+
+
+ 32MDIV8
+ 32 MHz / 8 = 4.0 MHz
+ 0x20000000
+
+
+ 32MDIV10
+ 32 MHz / 10 = 3.2 MHz
+ 0x18000000
+
+
+ 32MDIV11
+ 32 MHz / 11 = 2.9090909 MHz
+ 0x16000000
+
+
+ 32MDIV15
+ 32 MHz / 15 = 2.1333333 MHz
+ 0x11000000
+
+
+ 32MDIV16
+ 32 MHz / 16 = 2.0 MHz
+ 0x10000000
+
+
+ 32MDIV21
+ 32 MHz / 21 = 1.5238095
+ 0x0C000000
+
+
+ 32MDIV23
+ 32 MHz / 23 = 1.3913043 MHz
+ 0x0B000000
+
+
+ 32MDIV30
+ 32 MHz / 30 = 1.0666667 MHz
+ 0x08800000
+
+
+ 32MDIV31
+ 32 MHz / 31 = 1.0322581 MHz
+ 0x08400000
+
+
+ 32MDIV32
+ 32 MHz / 32 = 1.0 MHz
+ 0x08000000
+
+
+ 32MDIV42
+ 32 MHz / 42 = 0.7619048 MHz
+ 0x06000000
+
+
+ 32MDIV63
+ 32 MHz / 63 = 0.5079365 MHz
+ 0x04100000
+
+
+ 32MDIV125
+ 32 MHz / 125 = 0.256 MHz
+ 0x020C0000
+
+
+
+
+
+
+ RATIO
+ MCK / LRCK ratio.
+ 0x014
+ read-write
+ 0x00000006
+
+
+ RATIO
+ MCK / LRCK ratio.
+ 0
+ 3
+
+
+ 32X
+ LRCK = MCK / 32
+ 0
+
+
+ 48X
+ LRCK = MCK / 48
+ 1
+
+
+ 64X
+ LRCK = MCK / 64
+ 2
+
+
+ 96X
+ LRCK = MCK / 96
+ 3
+
+
+ 128X
+ LRCK = MCK / 128
+ 4
+
+
+ 192X
+ LRCK = MCK / 192
+ 5
+
+
+ 256X
+ LRCK = MCK / 256
+ 6
+
+
+ 384X
+ LRCK = MCK / 384
+ 7
+
+
+ 512X
+ LRCK = MCK / 512
+ 8
+
+
+
+
+
+
+ SWIDTH
+ Sample width.
+ 0x018
+ read-write
+ 0x00000001
+
+
+ SWIDTH
+ Sample width.
+ 0
+ 1
+
+
+ 8Bit
+ 8 bit.
+ 0
+
+
+ 16Bit
+ 16 bit.
+ 1
+
+
+ 24Bit
+ 24 bit.
+ 2
+
+
+
+
+
+
+ ALIGN
+ Alignment of sample within a frame.
+ 0x01C
+ read-write
+ 0x00000000
+
+
+ ALIGN
+ Alignment of sample within a frame.
+ 0
+ 0
+
+
+ Left
+ Left-aligned.
+ 0
+
+
+ Right
+ Right-aligned.
+ 1
+
+
+
+
+
+
+ FORMAT
+ Frame format.
+ 0x020
+ read-write
+ 0x00000000
+
+
+ FORMAT
+ Frame format.
+ 0
+ 0
+
+
+ I2S
+ Original I2S format.
+ 0
+
+
+ Aligned
+ Alternate (left- or right-aligned) format.
+ 1
+
+
+
+
+
+
+ CHANNELS
+ Enable channels.
+ 0x024
+ read-write
+ 0x00000000
+
+
+ CHANNELS
+ Enable channels.
+ 0
+ 1
+
+
+ Stereo
+ Stereo.
+ 0
+
+
+ Left
+ Left only.
+ 1
+
+
+ Right
+ Right only.
+ 2
+
+
+
+
+
+
+
+ RXD
+ Unspecified
+ I2S_RXD
+ read-write
+ 0x538
+
+ PTR
+ Receive buffer RAM start address.
+ 0x000
+ read-write
+ 0x00000000
+
+
+ PTR
+ Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address.
+ 0
+ 31
+
+
+
+
+
+ TXD
+ Unspecified
+ I2S_TXD
+ read-write
+ 0x540
+
+ PTR
+ Transmit buffer RAM start address.
+ 0x000
+ read-write
+ 0x00000000
+
+
+ PTR
+ Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address.
+ 0
+ 31
+
+
+
+
+
+ RXTXD
+ Unspecified
+ I2S_RXTXD
+ read-write
+ 0x550
+
+ MAXCNT
+ Size of RXD and TXD buffers.
+ 0x000
+ read-write
+ 0x00000000
+
+
+ MAXCNT
+ Size of RXD and TXD buffers in number of 32 bit words.
+ 0
+ 13
+
+
+
+
+
+ PSEL
+ Unspecified
+ I2S_PSEL
+ read-write
+ 0x560
+
+ MCK
+ Pin select for MCK signal.
+ 0x000
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ SCK
+ Pin select for SCK signal.
+ 0x004
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ LRCK
+ Pin select for LRCK signal.
+ 0x008
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ SDIN
+ Pin select for SDIN signal.
+ 0x00C
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+ SDOUT
+ Pin select for SDOUT signal.
+ 0x010
+ read-write
+ 0xFFFFFFFF
+
+
+ PIN
+ Pin number
+ 0
+ 4
+
+
+ PORT
+ Port number
+ 5
+ 5
+
+
+ CONNECT
+ Connection
+ 31
+ 31
+
+
+ Disconnected
+ Disconnect
+ 1
+
+
+ Connected
+ Connect
+ 0
+
+
+
+
+
+
+
+
+
+ FPU
+ FPU
+ 0x40026000
+
+ 0
+ 0x1000
+ registers
+
+
+ FPU
+ 38
+
+ FPU
+ 0x20
+
+
+ UNUSED
+ Unused.
+ 0x000
+ 0x00000000
+ read-only
+
+
+
+
+ USBD
+ Universal serial bus device
+ 0x40027000
+
+ 0
+ 0x1000
+ registers
+
+
+ USBD
+ 39
+
+ USBD
+ 0x20
+
+
+ 0x8
+ 0x4
+ TASKS_STARTEPIN[%s]
+ Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host
+ 0x004
+ write-only
+
+
+ TASKS_STARTEPIN
+ Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTISOIN
+ Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint
+ 0x024
+ write-only
+
+
+ TASKS_STARTISOIN
+ Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ TASKS_STARTEPOUT[%s]
+ Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host
+ 0x028
+ write-only
+
+
+ TASKS_STARTEPOUT
+ Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_STARTISOOUT
+ Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint
+ 0x048
+ write-only
+
+
+ TASKS_STARTISOOUT
+ Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_EP0RCVOUT
+ Allows OUT data stage on control endpoint 0
+ 0x04C
+ write-only
+
+
+ TASKS_EP0RCVOUT
+ Allows OUT data stage on control endpoint 0
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_EP0STATUS
+ Allows status stage on control endpoint 0
+ 0x050
+ write-only
+
+
+ TASKS_EP0STATUS
+ Allows status stage on control endpoint 0
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_EP0STALL
+ Stalls data and status stage on control endpoint 0
+ 0x054
+ write-only
+
+
+ TASKS_EP0STALL
+ Stalls data and status stage on control endpoint 0
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_DPDMDRIVE
+ Forces D+ and D- lines into the state defined in the DPDMVALUE register
+ 0x058
+ write-only
+
+
+ TASKS_DPDMDRIVE
+ Forces D+ and D- lines into the state defined in the DPDMVALUE register
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ TASKS_DPDMNODRIVE
+ Stops forcing D+ and D- lines into any state (USB engine takes control)
+ 0x05C
+ write-only
+
+
+ TASKS_DPDMNODRIVE
+ Stops forcing D+ and D- lines into any state (USB engine takes control)
+ 0
+ 0
+
+
+ Trigger
+ Trigger task
+ 1
+
+
+
+
+
+
+ EVENTS_USBRESET
+ Signals that a USB reset condition has been detected on USB lines
+ 0x100
+ read-write
+
+
+ EVENTS_USBRESET
+ Signals that a USB reset condition has been detected on USB lines
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_STARTED
+ Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register
+ 0x104
+ read-write
+
+
+ EVENTS_STARTED
+ Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ EVENTS_ENDEPIN[%s]
+ Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software.
+ 0x108
+ read-write
+
+
+ EVENTS_ENDEPIN
+ The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_EP0DATADONE
+ An acknowledged data transfer has taken place on the control endpoint
+ 0x128
+ read-write
+
+
+ EVENTS_EP0DATADONE
+ An acknowledged data transfer has taken place on the control endpoint
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDISOIN
+ The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software.
+ 0x12C
+ read-write
+
+
+ EVENTS_ENDISOIN
+ The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ EVENTS_ENDEPOUT[%s]
+ Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software.
+ 0x130
+ read-write
+
+
+ EVENTS_ENDEPOUT
+ The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_ENDISOOUT
+ The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software.
+ 0x150
+ read-write
+
+
+ EVENTS_ENDISOOUT
+ The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_SOF
+ Signals that a SOF (start of frame) condition has been detected on USB lines
+ 0x154
+ read-write
+
+
+ EVENTS_SOF
+ Signals that a SOF (start of frame) condition has been detected on USB lines
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_USBEVENT
+ An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.
+ 0x158
+ read-write
+
+
+ EVENTS_USBEVENT
+ An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_EP0SETUP
+ A valid SETUP token has been received (and acknowledged) on the control endpoint
+ 0x15C
+ read-write
+
+
+ EVENTS_EP0SETUP
+ A valid SETUP token has been received (and acknowledged) on the control endpoint
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ EVENTS_EPDATA
+ A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register
+ 0x160
+ read-write
+
+
+ EVENTS_EPDATA
+ A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register
+ 0
+ 0
+
+
+ NotGenerated
+ Event not generated
+ 0
+
+
+ Generated
+ Event generated
+ 1
+
+
+
+
+
+
+ SHORTS
+ Shortcuts between local events and tasks
+ 0x200
+ read-write
+
+
+ EP0DATADONE_STARTEPIN0
+ Shortcut between event EP0DATADONE and task STARTEPIN[0]
+ 0
+ 0
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ EP0DATADONE_STARTEPOUT0
+ Shortcut between event EP0DATADONE and task STARTEPOUT[0]
+ 1
+ 1
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ EP0DATADONE_EP0STATUS
+ Shortcut between event EP0DATADONE and task EP0STATUS
+ 2
+ 2
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ ENDEPOUT0_EP0STATUS
+ Shortcut between event ENDEPOUT[0] and task EP0STATUS
+ 3
+ 3
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+ ENDEPOUT0_EP0RCVOUT
+ Shortcut between event ENDEPOUT[0] and task EP0RCVOUT
+ 4
+ 4
+
+
+ Disabled
+ Disable shortcut
+ 0
+
+
+ Enabled
+ Enable shortcut
+ 1
+
+
+
+
+
+
+ INTEN
+ Enable or disable interrupt
+ 0x300
+ read-write
+
+
+ USBRESET
+ Enable or disable interrupt for event USBRESET
+ 0
+ 0
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ STARTED
+ Enable or disable interrupt for event STARTED
+ 1
+ 1
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPIN0
+ Enable or disable interrupt for event ENDEPIN[0]
+ 2
+ 2
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPIN1
+ Enable or disable interrupt for event ENDEPIN[1]
+ 3
+ 3
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPIN2
+ Enable or disable interrupt for event ENDEPIN[2]
+ 4
+ 4
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPIN3
+ Enable or disable interrupt for event ENDEPIN[3]
+ 5
+ 5
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPIN4
+ Enable or disable interrupt for event ENDEPIN[4]
+ 6
+ 6
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPIN5
+ Enable or disable interrupt for event ENDEPIN[5]
+ 7
+ 7
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPIN6
+ Enable or disable interrupt for event ENDEPIN[6]
+ 8
+ 8
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPIN7
+ Enable or disable interrupt for event ENDEPIN[7]
+ 9
+ 9
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ EP0DATADONE
+ Enable or disable interrupt for event EP0DATADONE
+ 10
+ 10
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDISOIN
+ Enable or disable interrupt for event ENDISOIN
+ 11
+ 11
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT0
+ Enable or disable interrupt for event ENDEPOUT[0]
+ 12
+ 12
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT1
+ Enable or disable interrupt for event ENDEPOUT[1]
+ 13
+ 13
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT2
+ Enable or disable interrupt for event ENDEPOUT[2]
+ 14
+ 14
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT3
+ Enable or disable interrupt for event ENDEPOUT[3]
+ 15
+ 15
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT4
+ Enable or disable interrupt for event ENDEPOUT[4]
+ 16
+ 16
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT5
+ Enable or disable interrupt for event ENDEPOUT[5]
+ 17
+ 17
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT6
+ Enable or disable interrupt for event ENDEPOUT[6]
+ 18
+ 18
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT7
+ Enable or disable interrupt for event ENDEPOUT[7]
+ 19
+ 19
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ ENDISOOUT
+ Enable or disable interrupt for event ENDISOOUT
+ 20
+ 20
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ SOF
+ Enable or disable interrupt for event SOF
+ 21
+ 21
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ USBEVENT
+ Enable or disable interrupt for event USBEVENT
+ 22
+ 22
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ EP0SETUP
+ Enable or disable interrupt for event EP0SETUP
+ 23
+ 23
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+ EPDATA
+ Enable or disable interrupt for event EPDATA
+ 24
+ 24
+
+
+ Disabled
+ Disable
+ 0
+
+
+ Enabled
+ Enable
+ 1
+
+
+
+
+
+
+ INTENSET
+ Enable interrupt
+ 0x304
+ read-write
+
+
+ USBRESET
+ Write '1' to enable interrupt for event USBRESET
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ STARTED
+ Write '1' to enable interrupt for event STARTED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPIN0
+ Write '1' to enable interrupt for event ENDEPIN[0]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPIN1
+ Write '1' to enable interrupt for event ENDEPIN[1]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPIN2
+ Write '1' to enable interrupt for event ENDEPIN[2]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPIN3
+ Write '1' to enable interrupt for event ENDEPIN[3]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPIN4
+ Write '1' to enable interrupt for event ENDEPIN[4]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPIN5
+ Write '1' to enable interrupt for event ENDEPIN[5]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPIN6
+ Write '1' to enable interrupt for event ENDEPIN[6]
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPIN7
+ Write '1' to enable interrupt for event ENDEPIN[7]
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ EP0DATADONE
+ Write '1' to enable interrupt for event EP0DATADONE
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDISOIN
+ Write '1' to enable interrupt for event ENDISOIN
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT0
+ Write '1' to enable interrupt for event ENDEPOUT[0]
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT1
+ Write '1' to enable interrupt for event ENDEPOUT[1]
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT2
+ Write '1' to enable interrupt for event ENDEPOUT[2]
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT3
+ Write '1' to enable interrupt for event ENDEPOUT[3]
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT4
+ Write '1' to enable interrupt for event ENDEPOUT[4]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT5
+ Write '1' to enable interrupt for event ENDEPOUT[5]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT6
+ Write '1' to enable interrupt for event ENDEPOUT[6]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDEPOUT7
+ Write '1' to enable interrupt for event ENDEPOUT[7]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ ENDISOOUT
+ Write '1' to enable interrupt for event ENDISOOUT
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ SOF
+ Write '1' to enable interrupt for event SOF
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ USBEVENT
+ Write '1' to enable interrupt for event USBEVENT
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ EP0SETUP
+ Write '1' to enable interrupt for event EP0SETUP
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+ EPDATA
+ Write '1' to enable interrupt for event EPDATA
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Set
+ Enable
+ 1
+
+
+
+
+
+
+ INTENCLR
+ Disable interrupt
+ 0x308
+ read-write
+
+
+ USBRESET
+ Write '1' to disable interrupt for event USBRESET
+ 0
+ 0
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ STARTED
+ Write '1' to disable interrupt for event STARTED
+ 1
+ 1
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPIN0
+ Write '1' to disable interrupt for event ENDEPIN[0]
+ 2
+ 2
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPIN1
+ Write '1' to disable interrupt for event ENDEPIN[1]
+ 3
+ 3
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPIN2
+ Write '1' to disable interrupt for event ENDEPIN[2]
+ 4
+ 4
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPIN3
+ Write '1' to disable interrupt for event ENDEPIN[3]
+ 5
+ 5
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPIN4
+ Write '1' to disable interrupt for event ENDEPIN[4]
+ 6
+ 6
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPIN5
+ Write '1' to disable interrupt for event ENDEPIN[5]
+ 7
+ 7
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPIN6
+ Write '1' to disable interrupt for event ENDEPIN[6]
+ 8
+ 8
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPIN7
+ Write '1' to disable interrupt for event ENDEPIN[7]
+ 9
+ 9
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ EP0DATADONE
+ Write '1' to disable interrupt for event EP0DATADONE
+ 10
+ 10
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDISOIN
+ Write '1' to disable interrupt for event ENDISOIN
+ 11
+ 11
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPOUT0
+ Write '1' to disable interrupt for event ENDEPOUT[0]
+ 12
+ 12
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPOUT1
+ Write '1' to disable interrupt for event ENDEPOUT[1]
+ 13
+ 13
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPOUT2
+ Write '1' to disable interrupt for event ENDEPOUT[2]
+ 14
+ 14
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPOUT3
+ Write '1' to disable interrupt for event ENDEPOUT[3]
+ 15
+ 15
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPOUT4
+ Write '1' to disable interrupt for event ENDEPOUT[4]
+ 16
+ 16
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPOUT5
+ Write '1' to disable interrupt for event ENDEPOUT[5]
+ 17
+ 17
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPOUT6
+ Write '1' to disable interrupt for event ENDEPOUT[6]
+ 18
+ 18
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDEPOUT7
+ Write '1' to disable interrupt for event ENDEPOUT[7]
+ 19
+ 19
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ ENDISOOUT
+ Write '1' to disable interrupt for event ENDISOOUT
+ 20
+ 20
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ SOF
+ Write '1' to disable interrupt for event SOF
+ 21
+ 21
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ USBEVENT
+ Write '1' to disable interrupt for event USBEVENT
+ 22
+ 22
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ EP0SETUP
+ Write '1' to disable interrupt for event EP0SETUP
+ 23
+ 23
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+ EPDATA
+ Write '1' to disable interrupt for event EPDATA
+ 24
+ 24
+
+ read
+
+ Disabled
+ Read: Disabled
+ 0
+
+
+ Enabled
+ Read: Enabled
+ 1
+
+
+
+ write
+
+ Clear
+ Disable
+ 1
+
+
+
+
+
+
+ EVENTCAUSE
+ Details on what caused the USBEVENT event
+ 0x400
+ read-write
+ oneToClear
+
+
+ ISOOUTCRC
+ CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear.
+ 0
+ 0
+
+
+ NotDetected
+ No error detected
+ 0
+
+
+ Detected
+ Error detected
+ 1
+
+
+
+
+ SUSPEND
+ Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear.
+ 8
+ 8
+
+
+ NotDetected
+ Suspend not detected
+ 0
+
+
+ Detected
+ Suspend detected
+ 1
+
+
+
+
+ RESUME
+ Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear.
+ 9
+ 9
+
+
+ NotDetected
+ Resume not detected
+ 0
+
+
+ Detected
+ Resume detected
+ 1
+
+
+
+
+ USBWUALLOWED
+ USB MAC has been woken up and operational. Write '1' to clear.
+ 10
+ 10
+
+
+ NotAllowed
+ Wake up not allowed
+ 0
+
+
+ Allowed
+ Wake up allowed
+ 1
+
+
+
+
+ READY
+ USB device is ready for normal operation. Write '1' to clear.
+ 11
+ 11
+
+
+ NotDetected
+ USBEVENT was not issued due to USBD peripheral ready
+ 0
+
+
+ Ready
+ USBD peripheral is ready
+ 1
+
+
+
+
+
+
+ HALTED
+ Unspecified
+ USBD_HALTED
+ read-write
+ 0x420
+
+ 0x8
+ 0x4
+ EPIN[%s]
+ Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.
+ 0x000
+ read-only
+
+
+ GETSTATUS
+ IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.
+ 0
+ 15
+
+
+ NotHalted
+ Endpoint is not halted
+ 0
+
+
+ Halted
+ Endpoint is halted
+ 1
+
+
+
+
+
+
+ 0x8
+ 0x4
+ EPOUT[%s]
+ Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.
+ 0x024
+ read-only
+
+
+ GETSTATUS
+ OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.
+ 0
+ 15
+
+
+ NotHalted
+ Endpoint is not halted
+ 0
+
+
+ Halted
+ Endpoint is halted
+ 1
+
+
+
+
+
+
+
+ EPSTATUS
+ Provides information on which endpoint's EasyDMA registers have been captured
+ 0x468
+ read-write
+ oneToClear
+
+
+ EPIN0
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 0
+ 0
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPIN1
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 1
+ 1
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPIN2
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 2
+ 2
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPIN3
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 3
+ 3
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPIN4
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 4
+ 4
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPIN5
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 5
+ 5
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPIN6
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 6
+ 6
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPIN7
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 7
+ 7
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPIN8
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 8
+ 8
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPOUT0
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 16
+ 16
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPOUT1
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 17
+ 17
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPOUT2
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 18
+ 18
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPOUT3
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 19
+ 19
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPOUT4
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 20
+ 20
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPOUT5
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 21
+ 21
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPOUT6
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 22
+ 22
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPOUT7
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 23
+ 23
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+ EPOUT8
+ Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+ 24
+ 24
+
+
+ NoData
+ EasyDMA registers have not been captured for this endpoint
+ 0
+
+
+ DataDone
+ EasyDMA registers have been captured for this endpoint
+ 1
+
+
+
+
+
+
+ EPDATASTATUS
+ Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event)
+ 0x46C
+ read-write
+ oneToClear
+
+
+ EPIN1
+ Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+ 1
+ 1
+
+
+ NotDone
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ DataDone
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPIN2
+ Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+ 2
+ 2
+
+
+ NotDone
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ DataDone
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPIN3
+ Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+ 3
+ 3
+
+
+ NotDone
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ DataDone
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPIN4
+ Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+ 4
+ 4
+
+
+ NotDone
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ DataDone
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPIN5
+ Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+ 5
+ 5
+
+
+ NotDone
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ DataDone
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPIN6
+ Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+ 6
+ 6
+
+
+ NotDone
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ DataDone
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPIN7
+ Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+ 7
+ 7
+
+
+ NotDone
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ DataDone
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPOUT1
+ Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+ 17
+ 17
+
+
+ NotStarted
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ Started
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPOUT2
+ Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+ 18
+ 18
+
+
+ NotStarted
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ Started
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPOUT3
+ Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+ 19
+ 19
+
+
+ NotStarted
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ Started
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPOUT4
+ Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+ 20
+ 20
+
+
+ NotStarted
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ Started
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPOUT5
+ Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+ 21
+ 21
+
+
+ NotStarted
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ Started
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPOUT6
+ Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+ 22
+ 22
+
+
+ NotStarted
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ Started
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+ EPOUT7
+ Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+ 23
+ 23
+
+
+ NotStarted
+ No acknowledged data transfer on this endpoint
+ 0
+
+
+ Started
+ Acknowledged data transfer on this endpoint has occurred
+ 1
+
+
+
+
+
+
+ USBADDR
+ Device USB address
+ 0x470
+ read-only
+
+
+ ADDR
+ Device USB address
+ 0
+ 6
+
+
+
+
+ BMREQUESTTYPE
+ SETUP data, byte 0, bmRequestType
+ 0x480
+ read-only
+ 0x00000000
+
+
+ RECIPIENT
+ Data transfer type
+ 0
+ 4
+
+
+ Device
+ Device
+ 0
+
+
+ Interface
+ Interface
+ 1
+
+
+ Endpoint
+ Endpoint
+ 2
+
+
+ Other
+ Other
+ 3
+
+
+
+
+ TYPE
+ Data transfer type
+ 5
+ 6
+
+
+ Standard
+ Standard
+ 0
+
+
+ Class
+ Class
+ 1
+
+
+ Vendor
+ Vendor
+ 2
+
+
+
+
+ DIRECTION
+ Data transfer direction
+ 7
+ 7
+
+
+ HostToDevice
+ Host-to-device
+ 0
+
+
+ DeviceToHost
+ Device-to-host
+ 1
+
+
+
+
+
+
+ BREQUEST
+ SETUP data, byte 1, bRequest
+ 0x484
+ read-only
+ 0x00000000
+
+
+ BREQUEST
+ SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values.
+ 0
+ 7
+
+
+ STD_GET_STATUS
+ Standard request GET_STATUS
+ 0
+
+
+ STD_CLEAR_FEATURE
+ Standard request CLEAR_FEATURE
+ 1
+
+
+ STD_SET_FEATURE
+ Standard request SET_FEATURE
+ 3
+
+
+ STD_SET_ADDRESS
+ Standard request SET_ADDRESS
+ 5
+
+
+ STD_GET_DESCRIPTOR
+ Standard request GET_DESCRIPTOR
+ 6
+
+
+ STD_SET_DESCRIPTOR
+ Standard request SET_DESCRIPTOR
+ 7
+
+
+ STD_GET_CONFIGURATION
+ Standard request GET_CONFIGURATION
+ 8
+
+
+ STD_SET_CONFIGURATION
+ Standard request SET_CONFIGURATION
+ 9
+
+
+ STD_GET_INTERFACE
+ Standard request GET_INTERFACE
+ 10
+
+
+ STD_SET_INTERFACE
+ Standard request SET_INTERFACE
+ 11
+
+
+ STD_SYNCH_FRAME
+ Standard request SYNCH_FRAME
+ 12
+
+
+
+
+
+
+ WVALUEL
+ SETUP data, byte 2, LSB of wValue
+ 0x488
+ read-only
+ 0x00000000
+
+
+ WVALUEL
+ SETUP data, byte 2, LSB of wValue
+ 0
+ 7
+
+
+
+
+ WVALUEH
+ SETUP data, byte 3, MSB of wValue
+ 0x48C
+ read-only
+ 0x00000000
+
+
+ WVALUEH
+ SETUP data, byte 3, MSB of wValue
+ 0
+ 7
+
+
+
+
+ WINDEXL
+ SETUP data, byte 4, LSB of wIndex
+ 0x490
+ read-only
+ 0x00000000
+
+
+ WINDEXL
+ SETUP data, byte 4, LSB of wIndex
+ 0
+ 7
+
+
+
+
+ WINDEXH
+ SETUP data, byte 5, MSB of wIndex
+ 0x494
+ read-only
+ 0x00000000
+
+
+ WINDEXH
+ SETUP data, byte 5, MSB of wIndex
+ 0
+ 7
+
+
+
+
+ WLENGTHL
+ SETUP data, byte 6, LSB of wLength
+ 0x498
+ read-only
+ 0x00000000
+
+
+ WLENGTHL
+ SETUP data, byte 6, LSB of wLength
+ 0
+ 7
+
+
+
+
+ WLENGTHH
+ SETUP data, byte 7, MSB of wLength
+ 0x49C
+ read-only
+ 0x00000000
+
+
+ WLENGTHH
+ SETUP data, byte 7, MSB of wLength
+ 0
+ 7
+
+
+
+
+ SIZE
+ Unspecified
+ USBD_SIZE
+ read-write
+ 0x4A0
+
+ 0x8
+ 0x4
+ EPOUT[%s]
+ Description collection: Number of bytes received last in the data stage of this OUT endpoint
+ 0x000
+ read-write
+
+
+ SIZE
+ Number of bytes received last in the data stage of this OUT endpoint
+ 0
+ 6
+
+
+
+
+ ISOOUT
+ Number of bytes received last on this ISO OUT data endpoint
+ 0x020
+ read-only
+ 0x00010000
+
+
+ SIZE
+ Number of bytes received last on this ISO OUT data endpoint
+ 0
+ 9
+
+
+ ZERO
+ Zero-length data packet received
+ 16
+ 16
+
+
+ Normal
+ No zero-length data received, use value in SIZE
+ 0
+
+
+ ZeroData
+ Zero-length data received, ignore value in SIZE
+ 1
+
+
+
+
+
+
+
+ ENABLE
+ Enable USB
+ 0x500
+ read-write
+
+
+ ENABLE
+ Enable USB
+ 0
+ 0
+
+
+ Disabled
+ USB peripheral is disabled
+ 0
+
+
+ Enabled
+ USB peripheral is enabled
+ 1
+
+
+
+
+
+
+ USBPULLUP
+ Control of the USB pull-up
+ 0x504
+ read-write
+
+
+ CONNECT
+ Control of the USB pull-up on the D+ line
+ 0
+ 0
+
+
+ Disabled
+ Pull-up is disconnected
+ 0
+
+
+ Enabled
+ Pull-up is connected to D+
+ 1
+
+
+
+
+
+
+ DPDMVALUE
+ State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing).
+ 0x508
+ read-write
+
+
+ STATE
+ State D+ and D- lines will be forced into by the DPDMDRIVE task
+ 0
+ 4
+
+
+ Resume
+ D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state)
+ 1
+
+
+ J
+ D+ forced high, D- forced low (J state)
+ 2
+
+
+ K
+ D+ forced low, D- forced high (K state)
+ 4
+
+
+
+
+
+
+ DTOGGLE
+ Data toggle control and status
+ 0x50C
+ read-write
+ 0x00000100
+
+
+ EP
+ Select bulk endpoint number
+ 0
+ 2
+
+
+ IO
+ Selects IN or OUT endpoint
+ 7
+ 7
+
+
+ Out
+ Selects OUT endpoint
+ 0
+
+
+ In
+ Selects IN endpoint
+ 1
+
+
+
+
+ VALUE
+ Data toggle value
+ 8
+ 9
+
+
+ Nop
+ No action on data toggle when writing the register with this value
+ 0
+
+
+ Data0
+ Data toggle is DATA0 on endpoint set by EP and IO
+ 1
+
+
+ Data1
+ Data toggle is DATA1 on endpoint set by EP and IO
+ 2
+
+
+
+
+
+
+ EPINEN
+ Endpoint IN enable
+ 0x510
+ read-write
+ 0x00000001
+
+
+ IN0
+ Enable IN endpoint 0
+ 0
+ 0
+
+
+ Disable
+ Disable endpoint IN 0 (no response to IN tokens)
+ 0
+
+
+ Enable
+ Enable endpoint IN 0 (response to IN tokens)
+ 1
+
+
+
+
+ IN1
+ Enable IN endpoint 1
+ 1
+ 1
+
+
+ Disable
+ Disable endpoint IN 1 (no response to IN tokens)
+ 0
+
+
+ Enable
+ Enable endpoint IN 1 (response to IN tokens)
+ 1
+
+
+
+
+ IN2
+ Enable IN endpoint 2
+ 2
+ 2
+
+
+ Disable
+ Disable endpoint IN 2 (no response to IN tokens)
+ 0
+
+
+ Enable
+ Enable endpoint IN 2 (response to IN tokens)
+ 1
+
+
+
+
+ IN3
+ Enable IN endpoint 3
+ 3
+ 3
+
+
+ Disable
+ Disable endpoint IN 3 (no response to IN tokens)
+ 0
+
+
+ Enable
+ Enable endpoint IN 3 (response to IN tokens)
+ 1
+
+
+
+
+ IN4
+ Enable IN endpoint 4
+ 4
+ 4
+
+
+ Disable
+ Disable endpoint IN 4 (no response to IN tokens)
+ 0
+
+
+ Enable
+ Enable endpoint IN 4 (response to IN tokens)
+ 1
+
+
+
+
+ IN5
+ Enable IN endpoint 5
+ 5
+ 5
+
+
+ Disable
+ Disable endpoint IN 5 (no response to IN tokens)
+ 0
+
+
+ Enable
+ Enable endpoint IN 5 (response to IN tokens)
+ 1
+
+
+
+
+ IN6
+ Enable IN endpoint 6
+ 6
+ 6
+
+
+ Disable
+ Disable endpoint IN 6 (no response to IN tokens)
+ 0
+
+
+ Enable
+ Enable endpoint IN 6 (response to IN tokens)
+ 1
+
+
+
+
+ IN7
+ Enable IN endpoint 7
+ 7
+ 7
+
+
+ Disable
+ Disable endpoint IN 7 (no response to IN tokens)
+ 0
+
+
+ Enable
+ Enable endpoint IN 7 (response to IN tokens)
+ 1
+
+
+
+
+ ISOIN
+ Enable ISO IN endpoint
+ 8
+ 8
+
+
+ Disable
+ Disable ISO IN endpoint 8
+ 0
+
+
+ Enable
+ Enable ISO IN endpoint 8
+ 1
+
+
+
+
+
+
+ EPOUTEN
+ Endpoint OUT enable
+ 0x514
+ read-write
+ 0x00000001
+
+
+ OUT0
+ Enable OUT endpoint 0
+ 0
+ 0
+
+
+ Disable
+ Disable endpoint OUT 0 (no response to OUT tokens)
+ 0
+
+
+ Enable
+ Enable endpoint OUT 0 (response to OUT tokens)
+ 1
+
+
+
+
+ OUT1
+ Enable OUT endpoint 1
+ 1
+ 1
+
+
+ Disable
+ Disable endpoint OUT 1 (no response to OUT tokens)
+ 0
+
+
+ Enable
+ Enable endpoint OUT 1 (response to OUT tokens)
+ 1
+
+
+
+
+ OUT2
+ Enable OUT endpoint 2
+ 2
+ 2
+
+
+ Disable
+ Disable endpoint OUT 2 (no response to OUT tokens)
+ 0
+
+
+ Enable
+ Enable endpoint OUT 2 (response to OUT tokens)
+ 1
+
+
+
+
+ OUT3
+ Enable OUT endpoint 3
+ 3
+ 3
+
+
+ Disable
+ Disable endpoint OUT 3 (no response to OUT tokens)
+ 0
+
+
+ Enable
+ Enable endpoint OUT 3 (response to OUT tokens)
+ 1
+
+
+
+
+ OUT4
+ Enable OUT endpoint 4
+ 4
+ 4
+
+
+ Disable
+ Disable endpoint OUT 4 (no response to OUT tokens)
+ 0
+
+
+ Enable
+ Enable endpoint OUT 4 (response to OUT tokens)
+ 1
+
+
+
+
+ OUT5
+ Enable OUT endpoint 5
+ 5
+ 5
+
+
+ Disable
+ Disable endpoint OUT 5 (no response to OUT tokens)
+ 0
+
+
+ Enable
+ Enable endpoint OUT 5 (response to OUT tokens)
+ 1
+
+
+
+
+ OUT6
+ Enable OUT endpoint 6
+ 6
+ 6
+
+
+ Disable
+ Disable endpoint OUT 6 (no response to OUT tokens)
+ 0
+
+
+ Enable
+ Enable endpoint OUT 6 (response to OUT tokens)
+ 1
+
+
+
+
+ OUT7
+ Enable OUT endpoint 7
+ 7
+ 7
+
+
+ Disable
+ Disable endpoint OUT 7 (no response to OUT tokens)
+ 0
+
+
+ Enable
+ Enable endpoint OUT 7 (response to OUT tokens)
+ 1
+
+
+
+
+ ISOOUT
+ Enable ISO OUT endpoint 8
+ 8
+ 8
+
+
+ Disable
+ Disable ISO OUT endpoint 8
+ 0
+
+
+ Enable
+ Enable ISO OUT endpoint 8
+ 1
+
+
+
+
+
+
+ EPSTALL
+ STALL endpoints
+ 0x518
+ write-only
+ 0x00000000
+ modifyExternal
+
+
+ EP
+ Select endpoint number
+ 0
+ 2
+
+
+ IO
+ Selects IN or OUT endpoint
+ 7
+ 7
+
+
+ Out
+ Selects OUT endpoint
+ 0
+
+
+ In
+ Selects IN endpoint
+ 1
+
+
+
+
+ STALL
+ Stall selected endpoint
+ 8
+ 8
+
+
+ UnStall
+ Don't stall selected endpoint
+ 0
+
+
+ Stall
+ Stall selected endpoint
+ 1
+
+
+
+
+
+
+ ISOSPLIT
+ Controls the split of ISO buffers
+ 0x51C
+ read-write
+
+
+ SPLIT
+ Controls the split of ISO buffers
+ 0
+ 15
+
+
+ OneDir
+ Full buffer dedicated to either iso IN or OUT
+ 0x0000
+
+
+ HalfIN
+ Lower half for IN, upper half for OUT
+ 0x0080
+
+
+
+
+
+
+ FRAMECNTR
+ Returns the current value of the start of frame counter
+ 0x520
+ read-only
+
+
+ FRAMECNTR
+ Returns the current value of the start of frame counter
+ 0
+ 10
+
+
+
+
+ LOWPOWER
+ Controls USBD peripheral low power mode during USB suspend
+ 0x52C
+ read-write
+ 0x00000000
+
+
+ LOWPOWER
+ Controls USBD peripheral low-power mode during USB suspend
+ 0
+ 0
+
+
+ ForceNormal
+ Software must write this value to exit low power mode and before performing a remote wake-up
+ 0
+
+
+ LowPower
+ Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral
+ 1
+
+
+
+
+
+
+ ISOINCONFIG
+ Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent
+ 0x530
+ read-write
+
+
+ RESPONSE
+ Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent
+ 0
+ 0
+
+
+ NoResp
+ Endpoint does not respond in that case
+ 0
+
+
+ ZeroData
+ Endpoint responds with a zero-length data packet in that case
+ 1
+
+
+
+
+
+
+ 8
+ 0x014
+ EPIN[%s]
+ Unspecified
+ USBD_EPIN
+ read-write
+ 0x600
+
+ PTR
+ Description cluster: Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Description cluster: Maximum number of bytes to transfer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes to transfer
+ 0
+ 6
+
+
+
+
+ AMOUNT
+ Description cluster: Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 6
+
+
+
+
+
+ ISOIN
+ Unspecified
+ USBD_ISOIN
+ read-write
+ 0x6A0
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes to transfer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes to transfer
+ 0
+ 9
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 9
+
+
+
+
+
+ 8
+ 0x014
+ EPOUT[%s]
+ Unspecified
+ USBD_EPOUT
+ read-write
+ 0x700
+
+ PTR
+ Description cluster: Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Description cluster: Maximum number of bytes to transfer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes to transfer
+ 0
+ 6
+
+
+
+
+ AMOUNT
+ Description cluster: Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 6
+
+
+
+
+
+ ISOOUT
+ Unspecified
+ USBD_ISOOUT
+ read-write
+ 0x7A0
+
+ PTR
+ Data pointer
+ 0x000
+ read-write
+
+
+ PTR
+ Data pointer
+ 0
+ 31
+
+
+
+
+ MAXCNT
+ Maximum number of bytes to transfer
+ 0x004
+ read-write
+
+
+ MAXCNT
+ Maximum number of bytes to transfer
+ 0
+ 9
+
+
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0x008
+ read-only
+
+
+ AMOUNT
+ Number of bytes transferred in the last transaction
+ 0
+ 9
+
+
+
+
+
+
+
+ UARTE1
+ UART with EasyDMA 1
+ 0x40028000
+
+ UARTE1
+ 40
+
+
+
+ PWM3
+ Pulse width modulation unit 3
+ 0x4002D000
+
+ PWM3
+ 45
+
+
+
+ SPIM3
+ Serial Peripheral Interface Master with EasyDMA 3
+ 0x4002F000
+
+ SPIM3
+ 47
+
+
+
+
\ No newline at end of file
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52833_bitfields.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52833_bitfields.h
new file mode 100644
index 000000000..cefc6be77
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52833_bitfields.h
@@ -0,0 +1,17053 @@
+/*
+
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef __NRF52833_BITS_H
+#define __NRF52833_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver */
+
+/* Register: AAR_TASKS_START */
+/* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
+
+/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
+#define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: AAR_TASKS_STOP */
+/* Description: Stop resolving addresses */
+
+/* Bit 0 : Stop resolving addresses */
+#define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: AAR_EVENTS_END */
+/* Description: Address resolution procedure complete */
+
+/* Bit 0 : Address resolution procedure complete */
+#define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: AAR_EVENTS_RESOLVED */
+/* Description: Address resolved */
+
+/* Bit 0 : Address resolved */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
+
+/* Register: AAR_EVENTS_NOTRESOLVED */
+/* Description: Address not resolved */
+
+/* Bit 0 : Address not resolved */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
+
+/* Register: AAR_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event END */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: AAR_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event END */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status */
+
+/* Bits 3..0 : The IRK that was used last time an address was resolved */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR */
+
+/* Bits 1..0 : Enable or disable AAR */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
+
+/* Register: AAR_NIRK */
+/* Description: Number of IRKs */
+
+/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_IRKPTR */
+/* Description: Pointer to IRK data structure */
+
+/* Bits 31..0 : Pointer to the IRK data structure */
+#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
+#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
+
+/* Register: AAR_ADDRPTR */
+/* Description: Pointer to the resolvable address */
+
+/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
+#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
+#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
+
+/* Register: AAR_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+
+/* Peripheral: ACL */
+/* Description: Access control lists */
+
+/* Register: ACL_ACL_ADDR */
+/* Description: Description cluster: Configure the word-aligned start address of region n to protect */
+
+/* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */
+#define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
+#define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
+
+/* Register: ACL_ACL_SIZE */
+/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */
+
+/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512 kB. */
+#define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
+
+/* Register: ACL_ACL_PERM */
+/* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */
+
+/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */
+#define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
+#define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
+#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */
+#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */
+
+/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */
+#define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
+#define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */
+#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */
+
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption */
+
+/* Register: CCM_TASKS_KSGEN */
+/* Description: Start generation of key-stream. This operation will stop by itself when completed. */
+
+/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */
+#define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
+#define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
+#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_TASKS_CRYPT */
+/* Description: Start encryption/decryption. This operation will stop by itself when completed. */
+
+/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
+#define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
+#define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
+#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_TASKS_STOP */
+/* Description: Stop encryption/decryption */
+
+/* Bit 0 : Stop encryption/decryption */
+#define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_TASKS_RATEOVERRIDE */
+/* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
+
+/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
+#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */
+#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */
+#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_EVENTS_ENDKSGEN */
+/* Description: Key-stream generation complete */
+
+/* Bit 0 : Key-stream generation complete */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
+
+/* Register: CCM_EVENTS_ENDCRYPT */
+/* Description: Encrypt/decrypt complete */
+
+/* Bit 0 : Encrypt/decrypt complete */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
+
+/* Register: CCM_EVENTS_ERROR */
+/* Description: Deprecated register - CCM error event */
+
+/* Bit 0 : Deprecated field - CCM error event */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: CCM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
+
+/* Register: CCM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
+
+/* Register: CCM_MICSTATUS */
+/* Description: MIC check result */
+
+/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
+
+/* Register: CCM_ENABLE */
+/* Description: Enable */
+
+/* Bits 1..0 : Enable or disable CCM */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode */
+
+/* Bit 24 : Packet length configuration */
+#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
+#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
+#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */
+#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */
+
+/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
+#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
+#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
+#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
+#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
+#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */
+#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */
+
+/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
+
+/* Register: CCM_CNFPTR */
+/* Description: Pointer to data structure holding AES key and NONCE vector */
+
+/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
+#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
+#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
+
+/* Register: CCM_INPTR */
+/* Description: Input pointer */
+
+/* Bits 31..0 : Input pointer */
+#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
+#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
+
+/* Register: CCM_OUTPTR */
+/* Description: Output pointer */
+
+/* Bits 31..0 : Output pointer */
+#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
+#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
+
+/* Register: CCM_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation,
+ MIC generation and encryption/decryption. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+/* Register: CCM_MAXPACKETSIZE */
+/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */
+
+/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */
+#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
+#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
+
+/* Register: CCM_RATEOVERRIDE */
+/* Description: Data rate override setting. */
+
+/* Bits 1..0 : Data rate override setting. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control */
+
+/* Register: CLOCK_TASKS_HFCLKSTART */
+/* Description: Start HFXO crystal oscillator */
+
+/* Bit 0 : Start HFXO crystal oscillator */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_HFCLKSTOP */
+/* Description: Stop HFXO crystal oscillator */
+
+/* Bit 0 : Stop HFXO crystal oscillator */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_LFCLKSTART */
+/* Description: Start LFCLK */
+
+/* Bit 0 : Start LFCLK */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_LFCLKSTOP */
+/* Description: Stop LFCLK */
+
+/* Bit 0 : Stop LFCLK */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_CAL */
+/* Description: Start calibration of LFRC */
+
+/* Bit 0 : Start calibration of LFRC */
+#define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
+#define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
+#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_CTSTART */
+/* Description: Start calibration timer */
+
+/* Bit 0 : Start calibration timer */
+#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */
+#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */
+#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_CTSTOP */
+/* Description: Stop calibration timer */
+
+/* Bit 0 : Stop calibration timer */
+#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */
+#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */
+#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_EVENTS_HFCLKSTARTED */
+/* Description: HFXO crystal oscillator started */
+
+/* Bit 0 : HFXO crystal oscillator started */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_LFCLKSTARTED */
+/* Description: LFCLK started */
+
+/* Bit 0 : LFCLK started */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_DONE */
+/* Description: Calibration of LFRC completed */
+
+/* Bit 0 : Calibration of LFRC completed */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_CTTO */
+/* Description: Calibration timer timeout */
+
+/* Bit 0 : Calibration timer timeout */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_CTSTARTED */
+/* Description: Calibration timer has been started and is ready to process new tasks */
+
+/* Bit 0 : Calibration timer has been started and is ready to process new tasks */
+#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */
+#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */
+#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_CTSTOPPED */
+/* Description: Calibration timer has been stopped and is ready to process new tasks */
+
+/* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */
+#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */
+#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */
+#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */
+#define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
+#define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
+#define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */
+#define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
+#define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
+#define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event CTTO */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event DONE */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */
+#define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
+#define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
+#define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */
+#define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
+#define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
+#define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event CTTO */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event DONE */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Status indicating that HFCLKSTART task has been triggered */
+
+/* Bit 0 : HFCLKSTART task triggered or not */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: HFCLK status */
+
+/* Bit 16 : HFCLK state */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
+
+/* Bit 0 : Source of HFCLK */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Status indicating that LFCLKSTART task has been triggered */
+
+/* Bit 0 : LFCLKSTART task triggered or not */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: LFCLK status */
+
+/* Bit 16 : LFCLK state */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
+
+/* Bits 1..0 : Source of LFCLK */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK */
+
+/* Bit 17 : Enable or disable external source for LFCLK */
+#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
+#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
+
+/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
+#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
+#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
+
+/* Register: CLOCK_HFXODEBOUNCE */
+/* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */
+
+/* Bits 7..0 : HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. */
+#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos (0UL) /*!< Position of HFXODEBOUNCE field. */
+#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Msk (0xFFUL << CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos) /*!< Bit mask of HFXODEBOUNCE field. */
+#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. */
+#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db1024us (0x40UL) /*!< 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. */
+
+/* Register: CLOCK_LFXODEBOUNCE */
+/* Description: LFXO debounce time. The LFXO is started by triggering the TASKS_LFCLKSTART task when the LFCLKSRC register is configured for Xtal. */
+
+/* Bit 0 : LFXO debounce time. */
+#define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Pos (0UL) /*!< Position of LFXODEBOUNCE field. */
+#define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Msk (0x1UL << CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Pos) /*!< Bit mask of LFXODEBOUNCE field. */
+#define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Normal (0UL) /*!< 8192 32.768 kHz periods, or 0.25 s. Recommended for normal Operating Temperature conditions. */
+#define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Extended (1UL) /*!< 16384 32.768 kHz periods, or 0.5 s. Recommended for Extended Operating Temperature conditions. */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval */
+
+/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+/* Register: CLOCK_TRACECONFIG */
+/* Description: Clocking options for the trace port debug interface */
+
+/* Bits 17..16 : Pin multiplexing of trace signals. See pin assignment chapter for more details. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< No trace signals routed to pins. All pins can be used as regular GPIOs. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. */
+
+/* Bits 1..0 : Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz trace port clock (TRACECLK = 16 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz trace port clock (TRACECLK = 8 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz trace port clock (TRACECLK = 4 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz trace port clock (TRACECLK = 2 MHz) */
+
+
+/* Peripheral: COMP */
+/* Description: Comparator */
+
+/* Register: COMP_TASKS_START */
+/* Description: Start comparator */
+
+/* Bit 0 : Start comparator */
+#define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: COMP_TASKS_STOP */
+/* Description: Stop comparator */
+
+/* Bit 0 : Stop comparator */
+#define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: COMP_TASKS_SAMPLE */
+/* Description: Sample comparator value */
+
+/* Bit 0 : Sample comparator value */
+#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
+#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
+#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: COMP_EVENTS_READY */
+/* Description: COMP is ready and output is valid */
+
+/* Bit 0 : COMP is ready and output is valid */
+#define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: COMP_EVENTS_DOWN */
+/* Description: Downward crossing */
+
+/* Bit 0 : Downward crossing */
+#define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
+#define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
+#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
+#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
+
+/* Register: COMP_EVENTS_UP */
+/* Description: Upward crossing */
+
+/* Bit 0 : Upward crossing */
+#define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
+#define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
+#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
+#define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
+
+/* Register: COMP_EVENTS_CROSS */
+/* Description: Downward or upward crossing */
+
+/* Bit 0 : Downward or upward crossing */
+#define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
+#define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
+#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
+#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
+
+/* Register: COMP_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 4 : Shortcut between event CROSS and task STOP */
+#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event UP and task STOP */
+#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event DOWN and task STOP */
+#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event READY and task STOP */
+#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event READY and task SAMPLE */
+#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: COMP_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 3 : Enable or disable interrupt for event CROSS */
+#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event UP */
+#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event DOWN */
+#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event READY */
+#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: COMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to enable interrupt for event CROSS */
+#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event UP */
+#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event DOWN */
+#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event READY */
+#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: COMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to disable interrupt for event CROSS */
+#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event UP */
+#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event DOWN */
+#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event READY */
+#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: COMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */
+#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */
+
+/* Register: COMP_ENABLE */
+/* Description: COMP enable */
+
+/* Bits 1..0 : Enable or disable COMP */
+#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: COMP_PSEL */
+/* Description: Pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: COMP_REFSEL */
+/* Description: Reference source select for single-ended mode */
+
+/* Bits 2..0 : Reference select */
+#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */
+#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
+#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */
+
+/* Register: COMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bits 2..0 : External analog reference select */
+#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */
+
+/* Register: COMP_TH */
+/* Description: Threshold configuration for hysteresis unit */
+
+/* Bits 13..8 : VUP = (THUP+1)/64*VREF */
+#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
+#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
+
+/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
+#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
+#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
+
+/* Register: COMP_MODE */
+/* Description: Mode configuration */
+
+/* Bit 8 : Main operation modes */
+#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
+#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
+#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
+#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
+
+/* Bits 1..0 : Speed and power modes */
+#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
+#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
+#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
+#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
+#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
+
+/* Register: COMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis */
+#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption */
+
+/* Register: ECB_TASKS_STARTECB */
+/* Description: Start ECB block encrypt */
+
+/* Bit 0 : Start ECB block encrypt */
+#define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
+#define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
+#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
+
+/* Register: ECB_TASKS_STOPECB */
+/* Description: Abort a possible executing ECB operation */
+
+/* Bit 0 : Abort a possible executing ECB operation */
+#define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
+#define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
+#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
+
+/* Register: ECB_EVENTS_ENDECB */
+/* Description: ECB block encrypt complete */
+
+/* Bit 0 : ECB block encrypt complete */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
+
+/* Register: ECB_EVENTS_ERRORECB */
+/* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
+
+/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
+
+/* Register: ECB_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event ENDECB */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
+
+/* Register: ECB_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event ENDECB */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
+
+/* Register: ECB_ECBDATAPTR */
+/* Description: ECB block encrypt memory pointers */
+
+/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
+
+
+/* Peripheral: EGU */
+/* Description: Event Generator Unit 0 */
+
+/* Register: EGU_TASKS_TRIGGER */
+/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
+
+/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
+
+/* Register: EGU_EVENTS_TRIGGERED */
+/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
+
+/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
+
+/* Register: EGU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
+#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
+#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
+#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
+#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
+#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
+#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
+#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
+#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
+#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
+#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
+#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
+#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
+#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
+#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
+#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
+#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
+
+/* Register: EGU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
+#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
+#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
+#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
+#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
+#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
+#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
+#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
+#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
+#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
+#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
+#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
+#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
+#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
+#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
+#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
+#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
+
+/* Register: EGU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
+#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
+#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
+#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
+#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
+#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
+#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
+#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
+#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
+#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
+#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
+#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
+#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
+#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
+#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
+#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
+#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
+
+
+/* Peripheral: FICR */
+/* Description: Factory information configuration registers */
+
+/* Register: FICR_CODEPAGESIZE */
+/* Description: Code memory page size */
+
+/* Bits 31..0 : Code memory page size */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
+
+/* Register: FICR_CODESIZE */
+/* Description: Code memory size */
+
+/* Bits 31..0 : Code memory size in number of pages */
+#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
+#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
+
+/* Register: FICR_DEVICEID */
+/* Description: Description collection: Device identifier */
+
+/* Bits 31..0 : 64 bit unique device identifier */
+#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
+#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
+
+/* Register: FICR_ER */
+/* Description: Description collection: Encryption root, word n */
+
+/* Bits 31..0 : Encryption root, word n */
+#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
+#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
+
+/* Register: FICR_IR */
+/* Description: Description collection: Identity Root, word n */
+
+/* Bits 31..0 : Identity Root, word n */
+#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
+#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type */
+
+/* Bit 0 : Device address type */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
+
+/* Register: FICR_DEVICEADDR */
+/* Description: Description collection: Device address n */
+
+/* Bits 31..0 : 48 bit device address */
+#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
+#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
+
+/* Register: FICR_INFO_PART */
+/* Description: Part code */
+
+/* Bits 31..0 : Part code */
+#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
+#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */
+#define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */
+#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_VARIANT */
+/* Description: Build code (hardware version and production configuration) */
+
+/* Bits 31..0 : Build code (hardware version and production configuration). Encoded as ASCII. */
+#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
+#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
+#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_PACKAGE */
+/* Description: Package option */
+
+/* Bits 31..0 : Package option */
+#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */
+#define FICR_INFO_PACKAGE_PACKAGE_QD (0x2007UL) /*!< QDxx - 40-pin QFN */
+#define FICR_INFO_PACKAGE_PACKAGE_CJ (0x2008UL) /*!< CJxx - WLCSP */
+#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_RAM */
+/* Description: RAM variant */
+
+/* Bits 31..0 : RAM variant */
+#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
+#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
+#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
+#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
+#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
+#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */
+#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */
+#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_FLASH */
+/* Description: Flash variant */
+
+/* Bits 31..0 : Flash variant */
+#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */
+#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_PRODTEST */
+/* Description: Description collection: Production test signature n */
+
+/* Bits 31..0 : Production test signature n */
+#define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */
+#define FICR_PRODTEST_PRODTEST_Msk (0xFFFFFFFFUL << FICR_PRODTEST_PRODTEST_Pos) /*!< Bit mask of PRODTEST field. */
+#define FICR_PRODTEST_PRODTEST_Done (0xBB42319FUL) /*!< Production tests done */
+#define FICR_PRODTEST_PRODTEST_NotDone (0xFFFFFFFFUL) /*!< Production tests not done */
+
+/* Register: FICR_TEMP_A0 */
+/* Description: Slope definition A0 */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A1 */
+/* Description: Slope definition A1 */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A2 */
+/* Description: Slope definition A2 */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A3 */
+/* Description: Slope definition A3 */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A4 */
+/* Description: Slope definition A4 */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A5 */
+/* Description: Slope definition A5 */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_B0 */
+/* Description: Y-intercept B0 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B1 */
+/* Description: Y-intercept B1 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B2 */
+/* Description: Y-intercept B2 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B3 */
+/* Description: Y-intercept B3 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B4 */
+/* Description: Y-intercept B4 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B5 */
+/* Description: Y-intercept B5 */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_T0 */
+/* Description: Segment end T0 */
+
+/* Bits 7..0 : T (segment end) register */
+#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T1 */
+/* Description: Segment end T1 */
+
+/* Bits 7..0 : T (segment end) register */
+#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T2 */
+/* Description: Segment end T2 */
+
+/* Bits 7..0 : T (segment end) register */
+#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T3 */
+/* Description: Segment end T3 */
+
+/* Bits 7..0 : T (segment end) register */
+#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T4 */
+/* Description: Segment end T4 */
+
+/* Bits 7..0 : T (segment end) register */
+#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_NFC_TAGHEADER0 */
+/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 3 */
+#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
+#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
+
+/* Bits 23..16 : Unique identifier byte 2 */
+#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
+#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
+
+/* Bits 15..8 : Unique identifier byte 1 */
+#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
+#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
+
+/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
+#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
+#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
+
+/* Register: FICR_NFC_TAGHEADER1 */
+/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 7 */
+#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
+#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
+
+/* Bits 23..16 : Unique identifier byte 6 */
+#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
+#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
+
+/* Bits 15..8 : Unique identifier byte 5 */
+#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
+#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
+
+/* Bits 7..0 : Unique identifier byte 4 */
+#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
+#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
+
+/* Register: FICR_NFC_TAGHEADER2 */
+/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 11 */
+#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
+#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
+
+/* Bits 23..16 : Unique identifier byte 10 */
+#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
+#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
+
+/* Bits 15..8 : Unique identifier byte 9 */
+#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
+#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
+
+/* Bits 7..0 : Unique identifier byte 8 */
+#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
+#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
+
+/* Register: FICR_NFC_TAGHEADER3 */
+/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 15 */
+#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
+#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
+
+/* Bits 23..16 : Unique identifier byte 14 */
+#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
+#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
+
+/* Bits 15..8 : Unique identifier byte 13 */
+#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
+#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
+
+/* Bits 7..0 : Unique identifier byte 12 */
+#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
+#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO Tasks and Events */
+
+/* Register: GPIOTE_TASKS_OUT */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_TASKS_SET */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_TASKS_CLR */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_EVENTS_IN */
+/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
+
+/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
+
+/* Register: GPIOTE_EVENTS_PORT */
+/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
+
+/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 31 : Write '1' to enable interrupt for event PORT */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event IN[7] */
+#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event IN[6] */
+#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event IN[5] */
+#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event IN[4] */
+#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event IN[3] */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event IN[2] */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event IN[1] */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event IN[0] */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 31 : Write '1' to disable interrupt for event PORT */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event IN[7] */
+#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event IN[6] */
+#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event IN[5] */
+#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event IN[4] */
+#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event IN[3] */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event IN[2] */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event IN[1] */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event IN[0] */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
+
+/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
+
+/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
+
+/* Bit 13 : Port number */
+#define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */
+#define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
+#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
+#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
+
+
+/* Peripheral: I2S */
+/* Description: Inter-IC Sound */
+
+/* Register: I2S_TASKS_START */
+/* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
+
+/* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
+#define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: I2S_TASKS_STOP */
+/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
+
+/* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
+#define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: I2S_EVENTS_RXPTRUPD */
+/* Description: The RXD.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
+
+/* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */
+
+/* Register: I2S_EVENTS_STOPPED */
+/* Description: I2S transfer stopped. */
+
+/* Bit 0 : I2S transfer stopped. */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: I2S_EVENTS_TXPTRUPD */
+/* Description: The TDX.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
+
+/* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */
+
+/* Register: I2S_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
+#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event STOPPED */
+#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
+#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
+#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event STOPPED */
+#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
+#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Register: I2S_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
+#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event STOPPED */
+#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
+#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Register: I2S_ENABLE */
+/* Description: Enable I2S module. */
+
+/* Bit 0 : Enable I2S module. */
+#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_CONFIG_MODE */
+/* Description: I2S mode. */
+
+/* Bit 0 : I2S mode. */
+#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
+#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
+
+/* Register: I2S_CONFIG_RXEN */
+/* Description: Reception (RX) enable. */
+
+/* Bit 0 : Reception (RX) enable. */
+#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
+#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: I2S_CONFIG_TXEN */
+/* Description: Transmission (TX) enable. */
+
+/* Bit 0 : Transmission (TX) enable. */
+#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
+#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
+
+/* Register: I2S_CONFIG_MCKEN */
+/* Description: Master clock generator enable. */
+
+/* Bit 0 : Master clock generator enable. */
+#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
+#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
+
+/* Register: I2S_CONFIG_MCKFREQ */
+/* Description: Master clock generator frequency. */
+
+/* Bits 31..0 : Master clock generator frequency. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
+
+/* Register: I2S_CONFIG_RATIO */
+/* Description: MCK / LRCK ratio. */
+
+/* Bits 3..0 : MCK / LRCK ratio. */
+#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
+#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
+#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
+#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
+#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
+#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
+#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
+#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
+#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
+
+/* Register: I2S_CONFIG_SWIDTH */
+/* Description: Sample width. */
+
+/* Bits 1..0 : Sample width. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
+
+/* Register: I2S_CONFIG_ALIGN */
+/* Description: Alignment of sample within a frame. */
+
+/* Bit 0 : Alignment of sample within a frame. */
+#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
+#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
+
+/* Register: I2S_CONFIG_FORMAT */
+/* Description: Frame format. */
+
+/* Bit 0 : Frame format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
+
+/* Register: I2S_CONFIG_CHANNELS */
+/* Description: Enable channels. */
+
+/* Bits 1..0 : Enable channels. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
+
+/* Register: I2S_RXD_PTR */
+/* Description: Receive buffer RAM start address. */
+
+/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
+#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_TXD_PTR */
+/* Description: Transmit buffer RAM start address. */
+
+/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
+#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_RXTXD_MAXCNT */
+/* Description: Size of RXD and TXD buffers. */
+
+/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: I2S_PSEL_MCK */
+/* Description: Pin select for MCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define I2S_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define I2S_PSEL_MCK_PORT_Msk (0x1UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SCK */
+/* Description: Pin select for SCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define I2S_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define I2S_PSEL_SCK_PORT_Msk (0x1UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_LRCK */
+/* Description: Pin select for LRCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define I2S_PSEL_LRCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define I2S_PSEL_LRCK_PORT_Msk (0x1UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDIN */
+/* Description: Pin select for SDIN signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define I2S_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define I2S_PSEL_SDIN_PORT_Msk (0x1UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDOUT */
+/* Description: Pin select for SDOUT signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define I2S_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define I2S_PSEL_SDOUT_PORT_Msk (0x1UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: LPCOMP */
+/* Description: Low Power Comparator */
+
+/* Register: LPCOMP_TASKS_START */
+/* Description: Start comparator */
+
+/* Bit 0 : Start comparator */
+#define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: LPCOMP_TASKS_STOP */
+/* Description: Stop comparator */
+
+/* Bit 0 : Stop comparator */
+#define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: LPCOMP_TASKS_SAMPLE */
+/* Description: Sample comparator value */
+
+/* Bit 0 : Sample comparator value */
+#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
+#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
+#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: LPCOMP_EVENTS_READY */
+/* Description: LPCOMP is ready and output is valid */
+
+/* Bit 0 : LPCOMP is ready and output is valid */
+#define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: LPCOMP_EVENTS_DOWN */
+/* Description: Downward crossing */
+
+/* Bit 0 : Downward crossing */
+#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
+#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
+#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
+#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
+
+/* Register: LPCOMP_EVENTS_UP */
+/* Description: Upward crossing */
+
+/* Bit 0 : Upward crossing */
+#define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
+#define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
+#define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
+#define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
+
+/* Register: LPCOMP_EVENTS_CROSS */
+/* Description: Downward or upward crossing */
+
+/* Bit 0 : Downward or upward crossing */
+#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
+#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
+#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
+#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
+
+/* Register: LPCOMP_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 4 : Shortcut between event CROSS and task STOP */
+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event UP and task STOP */
+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event DOWN and task STOP */
+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event READY and task STOP */
+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event READY and task SAMPLE */
+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: LPCOMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to enable interrupt for event CROSS */
+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event UP */
+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event DOWN */
+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event READY */
+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: LPCOMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to disable interrupt for event CROSS */
+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event UP */
+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event DOWN */
+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event READY */
+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: LPCOMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */
+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */
+
+/* Register: LPCOMP_ENABLE */
+/* Description: Enable LPCOMP */
+
+/* Bits 1..0 : Enable or disable LPCOMP */
+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: LPCOMP_PSEL */
+/* Description: Input pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: LPCOMP_REFSEL */
+/* Description: Reference select */
+
+/* Bits 3..0 : Reference select */
+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
+#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
+
+/* Register: LPCOMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: LPCOMP_ANADETECT */
+/* Description: Analog detect configuration */
+
+/* Bits 1..0 : Analog detect configuration */
+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
+
+/* Register: LPCOMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis enable */
+#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define LPCOMP_HYST_HYST_Disabled (0UL) /*!< Comparator hysteresis disabled */
+#define LPCOMP_HYST_HYST_Enabled (1UL) /*!< Comparator hysteresis enabled */
+
+
+/* Peripheral: MWU */
+/* Description: Memory Watch Unit */
+
+/* Register: MWU_EVENTS_REGION_WA */
+/* Description: Description cluster: Write access to region n detected */
+
+/* Bit 0 : Write access to region n detected */
+#define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
+#define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */
+#define MWU_EVENTS_REGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */
+#define MWU_EVENTS_REGION_WA_WA_Generated (1UL) /*!< Event generated */
+
+/* Register: MWU_EVENTS_REGION_RA */
+/* Description: Description cluster: Read access to region n detected */
+
+/* Bit 0 : Read access to region n detected */
+#define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
+#define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */
+#define MWU_EVENTS_REGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */
+#define MWU_EVENTS_REGION_RA_RA_Generated (1UL) /*!< Event generated */
+
+/* Register: MWU_EVENTS_PREGION_WA */
+/* Description: Description cluster: Write access to peripheral region n detected */
+
+/* Bit 0 : Write access to peripheral region n detected */
+#define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
+#define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */
+#define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */
+#define MWU_EVENTS_PREGION_WA_WA_Generated (1UL) /*!< Event generated */
+
+/* Register: MWU_EVENTS_PREGION_RA */
+/* Description: Description cluster: Read access to peripheral region n detected */
+
+/* Bit 0 : Read access to peripheral region n detected */
+#define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
+#define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */
+#define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */
+#define MWU_EVENTS_PREGION_RA_RA_Generated (1UL) /*!< Event generated */
+
+/* Register: MWU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 27 : Enable or disable interrupt for event PREGION1RA */
+#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable interrupt for event PREGION1WA */
+#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for event PREGION0RA */
+#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable interrupt for event PREGION0WA */
+#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event REGION3RA */
+#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event REGION3WA */
+#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event REGION2RA */
+#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event REGION2WA */
+#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event REGION1RA */
+#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event REGION1WA */
+#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event REGION0RA */
+#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event REGION0WA */
+#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
+#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
+#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
+#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
+#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
+#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
+#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
+#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
+#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
+#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
+#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
+#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
+#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
+#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
+#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
+#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
+#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
+#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
+#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
+#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
+#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
+#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
+#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
+#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
+#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_NMIEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 27 : Enable or disable interrupt for event PREGION1RA */
+#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable interrupt for event PREGION1WA */
+#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for event PREGION0RA */
+#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable interrupt for event PREGION0WA */
+#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event REGION3RA */
+#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event REGION3WA */
+#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event REGION2RA */
+#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event REGION2WA */
+#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event REGION1RA */
+#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event REGION1WA */
+#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event REGION0RA */
+#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event REGION0WA */
+#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENSET */
+/* Description: Enable interrupt */
+
+/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
+#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
+#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
+#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
+#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
+#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
+#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
+#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
+#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
+#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
+#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
+#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
+#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
+#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
+#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
+#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
+#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
+#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
+#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
+#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
+#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
+#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
+#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
+#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
+#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_PERREGION_SUBSTATWA */
+/* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Register: MWU_PERREGION_SUBSTATRA */
+/* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region n (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Register: MWU_REGIONEN */
+/* Description: Enable/disable regions watch */
+
+/* Bit 27 : Enable/disable read access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable/disable write access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable/disable read access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable/disable write access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable/disable read access watch in region[3] */
+#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable/disable write access watch in region[3] */
+#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable/disable read access watch in region[2] */
+#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable/disable write access watch in region[2] */
+#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable/disable read access watch in region[1] */
+#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable/disable write access watch in region[1] */
+#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable/disable read access watch in region[0] */
+#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable/disable write access watch in region[0] */
+#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENSET */
+/* Description: Enable regions watch */
+
+/* Bit 27 : Enable read access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable write access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable read access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable write access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable read access watch in region[3] */
+#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable write access watch in region[3] */
+#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable read access watch in region[2] */
+#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable write access watch in region[2] */
+#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable read access watch in region[1] */
+#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable write access watch in region[1] */
+#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable read access watch in region[0] */
+#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable write access watch in region[0] */
+#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENCLR */
+/* Description: Disable regions watch */
+
+/* Bit 27 : Disable read access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 26 : Disable write access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 25 : Disable read access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 24 : Disable write access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 7 : Disable read access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 6 : Disable write access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 5 : Disable read access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 4 : Disable write access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 3 : Disable read access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 2 : Disable write access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 1 : Disable read access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 0 : Disable write access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Register: MWU_REGION_START */
+/* Description: Description cluster: Start address for region n */
+
+/* Bits 31..0 : Start address for region */
+#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_REGION_END */
+/* Description: Description cluster: End address of region n */
+
+/* Bits 31..0 : End address of region. */
+#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_START */
+/* Description: Description cluster: Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_PREGION_END */
+/* Description: Description cluster: Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_SUBS */
+/* Description: Description cluster: Subregions of region n */
+
+/* Bit 31 : Include or exclude subregion 31 in region */
+#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude subregion 30 in region */
+#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude subregion 29 in region */
+#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude subregion 28 in region */
+#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude subregion 27 in region */
+#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude subregion 26 in region */
+#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude subregion 25 in region */
+#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude subregion 24 in region */
+#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude subregion 23 in region */
+#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude subregion 22 in region */
+#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude subregion 21 in region */
+#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude subregion 20 in region */
+#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude subregion 19 in region */
+#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude subregion 18 in region */
+#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude subregion 17 in region */
+#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude subregion 16 in region */
+#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude subregion 15 in region */
+#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude subregion 14 in region */
+#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude subregion 13 in region */
+#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude subregion 12 in region */
+#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude subregion 11 in region */
+#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude subregion 10 in region */
+#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude subregion 9 in region */
+#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude subregion 8 in region */
+#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude subregion 7 in region */
+#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude subregion 6 in region */
+#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude subregion 5 in region */
+#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude subregion 4 in region */
+#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude subregion 3 in region */
+#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude subregion 2 in region */
+#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude subregion 1 in region */
+#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude subregion 0 in region */
+#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
+
+
+/* Peripheral: NFCT */
+/* Description: NFC-A compatible radio */
+
+/* Register: NFCT_TASKS_ACTIVATE */
+/* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
+
+/* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
+#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
+#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
+#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_DISABLE */
+/* Description: Disable NFCT peripheral */
+
+/* Bit 0 : Disable NFCT peripheral */
+#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
+#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
+#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_SENSE */
+/* Description: Enable NFC sense field mode, change state to sense mode */
+
+/* Bit 0 : Enable NFC sense field mode, change state to sense mode */
+#define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */
+#define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */
+#define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_STARTTX */
+/* Description: Start transmission of an outgoing frame, change state to transmit */
+
+/* Bit 0 : Start transmission of an outgoing frame, change state to transmit */
+#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_ENABLERXDATA */
+/* Description: Initializes the EasyDMA for receive. */
+
+/* Bit 0 : Initializes the EasyDMA for receive. */
+#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */
+#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */
+#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_GOIDLE */
+/* Description: Force state machine to IDLE state */
+
+/* Bit 0 : Force state machine to IDLE state */
+#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */
+#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */
+#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_GOSLEEP */
+/* Description: Force state machine to SLEEP_A state */
+
+/* Bit 0 : Force state machine to SLEEP_A state */
+#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */
+#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */
+#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_EVENTS_READY */
+/* Description: The NFCT peripheral is ready to receive and send frames */
+
+/* Bit 0 : The NFCT peripheral is ready to receive and send frames */
+#define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_FIELDDETECTED */
+/* Description: Remote NFC field detected */
+
+/* Bit 0 : Remote NFC field detected */
+#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */
+#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */
+#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_FIELDLOST */
+/* Description: Remote NFC field lost */
+
+/* Bit 0 : Remote NFC field lost */
+#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */
+#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */
+#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_TXFRAMESTART */
+/* Description: Marks the start of the first symbol of a transmitted frame */
+
+/* Bit 0 : Marks the start of the first symbol of a transmitted frame */
+#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */
+#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */
+#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_TXFRAMEEND */
+/* Description: Marks the end of the last transmitted on-air symbol of a frame */
+
+/* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */
+#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */
+#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */
+#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_RXFRAMESTART */
+/* Description: Marks the end of the first symbol of a received frame */
+
+/* Bit 0 : Marks the end of the first symbol of a received frame */
+#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */
+#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */
+#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_RXFRAMEEND */
+/* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
+
+/* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
+#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */
+#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */
+#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_ERROR */
+/* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
+
+/* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
+#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_RXERROR */
+/* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
+
+/* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
+#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */
+#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */
+#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_ENDRX */
+/* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
+
+/* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
+#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_ENDTX */
+/* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
+
+/* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
+#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
+#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
+#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */
+/* Description: Auto collision resolution process has started */
+
+/* Bit 0 : Auto collision resolution process has started */
+#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */
+#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */
+#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_COLLISION */
+/* Description: NFC auto collision resolution error reported. */
+
+/* Bit 0 : NFC auto collision resolution error reported. */
+#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */
+#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */
+#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_SELECTED */
+/* Description: NFC auto collision resolution successfully completed */
+
+/* Bit 0 : NFC auto collision resolution successfully completed */
+#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */
+#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */
+#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_STARTED */
+/* Description: EasyDMA is ready to receive or send frames. */
+
+/* Bit 0 : EasyDMA is ready to receive or send frames. */
+#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event FIELDLOST and task SENSE */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: NFCT_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 20 : Enable or disable interrupt for event STARTED */
+#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event SELECTED */
+#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for event COLLISION */
+#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for event ENDTX */
+#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for event ENDRX */
+#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for event RXERROR */
+#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event ERROR */
+#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */
+#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */
+#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */
+#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */
+#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event FIELDLOST */
+#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */
+#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event READY */
+#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 20 : Write '1' to enable interrupt for event STARTED */
+#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event SELECTED */
+#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event COLLISION */
+#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to enable interrupt for event ENDTX */
+#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to enable interrupt for event ENDRX */
+#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event RXERROR */
+#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event ERROR */
+#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */
+#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */
+#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */
+#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */
+#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */
+#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */
+#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event READY */
+#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 20 : Write '1' to disable interrupt for event STARTED */
+#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event SELECTED */
+#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event COLLISION */
+#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to disable interrupt for event ENDTX */
+#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to disable interrupt for event ENDRX */
+#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event RXERROR */
+#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event ERROR */
+#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */
+#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */
+#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */
+#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */
+#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */
+#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */
+#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event READY */
+#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: NFCT_ERRORSTATUS */
+/* Description: NFC Error Status register */
+
+/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
+
+/* Register: NFCT_FRAMESTATUS_RX */
+/* Description: Result of last incoming frame */
+
+/* Bit 3 : Overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
+
+/* Bit 2 : Parity status of received frame */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
+
+/* Bit 0 : No valid end of frame (EoF) detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
+
+/* Register: NFCT_NFCTAGSTATE */
+/* Description: NfcTag state register */
+
+/* Bits 2..0 : NfcTag state */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL) /*!< Disabled or sense */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL) /*!< RampUp */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (3UL) /*!< Idle */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (4UL) /*!< Receive */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL) /*!< FrameDelay */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL) /*!< Transmit */
+
+/* Register: NFCT_SLEEPSTATE */
+/* Description: Sleep state during automatic collision resolution */
+
+/* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE
+ by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a
+ GOSLEEP task. */
+#define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */
+#define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */
+#define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0UL) /*!< State is IDLE. */
+#define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (1UL) /*!< State is SLEEP_A. */
+
+/* Register: NFCT_FIELDPRESENT */
+/* Description: Indicates the presence or not of a valid field */
+
+/* Bit 1 : Indicates if the low level has locked to the field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
+
+/* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
+
+/* Register: NFCT_FRAMEDELAYMIN */
+/* Description: Minimum frame delay */
+
+/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
+
+/* Register: NFCT_FRAMEDELAYMAX */
+/* Description: Maximum frame delay */
+
+/* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
+
+/* Register: NFCT_FRAMEDELAYMODE */
+/* Description: Configuration register for the Frame Delay Timer */
+
+/* Bits 1..0 : Configuration register for the Frame Delay Timer */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
+
+/* Register: NFCT_PACKETPTR */
+/* Description: Packet pointer for TXD and RXD data storage in Data RAM */
+
+/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */
+#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: NFCT_MAXLEN */
+/* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */
+
+/* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */
+#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: NFCT_TXD_FRAMECONFIG */
+/* Description: Configuration of outgoing frames */
+
+/* Bit 4 : CRC mode for outgoing frames */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
+
+/* Bit 2 : Adding SoF or not in TX frames */
+#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol not added */
+#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol added */
+
+/* Bit 1 : Discarding unused bits at start or end of a frame */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits are discarded at end of frame (EoF) */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits are discarded at start of frame (SoF) */
+
+/* Bit 0 : Indicates if parity is added to the frame */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added to TX frames */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added to TX frames */
+
+/* Register: NFCT_TXD_AMOUNT */
+/* Description: Size of outgoing frame */
+
+/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
+
+/* Register: NFCT_RXD_FRAMECONFIG */
+/* Description: Configuration of incoming frames */
+
+/* Bit 4 : CRC mode for incoming frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
+
+/* Bit 2 : SoF expected or not in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol is expected in RX frames */
+
+/* Bit 0 : Indicates if parity expected in RX frame */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
+
+/* Register: NFCT_RXD_AMOUNT */
+/* Description: Size of last incoming frame */
+
+/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
+
+/* Register: NFCT_MODULATIONCTRL */
+/* Description: Enables the modulation output to a GPIO pin which can be connected to a second external antenna. */
+
+/* Bits 1..0 : Configuration of modulation control. */
+#define NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos (0UL) /*!< Position of MODULATIONCTRL field. */
+#define NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk (0x3UL << NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos) /*!< Bit mask of MODULATIONCTRL field. */
+#define NFCT_MODULATIONCTRL_MODULATIONCTRL_Invalid (0x0UL) /*!< Invalid, defaults to same behaviour as for Internal */
+#define NFCT_MODULATIONCTRL_MODULATIONCTRL_Internal (0x1UL) /*!< Use internal modulator only */
+#define NFCT_MODULATIONCTRL_MODULATIONCTRL_ModToGpio (0x2UL) /*!< Output digital modulation signal to a GPIO pin. */
+#define NFCT_MODULATIONCTRL_MODULATIONCTRL_InternalAndModToGpio (0x3UL) /*!< Use internal modulator and output digital modulation signal to a GPIO pin. */
+
+/* Register: NFCT_MODULATIONPSEL */
+/* Description: Pin select for Modulation control. */
+
+/* Bit 31 : Connection */
+#define NFCT_MODULATIONPSEL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define NFCT_MODULATIONPSEL_CONNECT_Msk (0x1UL << NFCT_MODULATIONPSEL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define NFCT_MODULATIONPSEL_CONNECT_Connected (0UL) /*!< Connect */
+#define NFCT_MODULATIONPSEL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define NFCT_MODULATIONPSEL_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define NFCT_MODULATIONPSEL_PORT_Msk (0x1UL << NFCT_MODULATIONPSEL_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define NFCT_MODULATIONPSEL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define NFCT_MODULATIONPSEL_PIN_Msk (0x1FUL << NFCT_MODULATIONPSEL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: NFCT_NFCID1_LAST */
+/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
+
+/* Bits 31..24 : NFCID1 byte W */
+#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
+#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
+
+/* Bits 23..16 : NFCID1 byte X */
+#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
+#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
+
+/* Bits 15..8 : NFCID1 byte Y */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
+
+/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
+
+/* Register: NFCT_NFCID1_2ND_LAST */
+/* Description: Second last NFCID1 part (7 or 10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte T */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
+
+/* Bits 15..8 : NFCID1 byte U */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
+
+/* Bits 7..0 : NFCID1 byte V */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
+
+/* Register: NFCT_NFCID1_3RD_LAST */
+/* Description: Third last NFCID1 part (10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte Q */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
+
+/* Bits 15..8 : NFCID1 byte R */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
+
+/* Bits 7..0 : NFCID1 byte S */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
+
+/* Register: NFCT_AUTOCOLRESCONFIG */
+/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. */
+
+/* Bit 0 : Enables/disables auto collision resolution */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */
+
+/* Register: NFCT_SENSRES */
+/* Description: NFC-A SENS_RES auto-response settings */
+
+/* Bits 15..12 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
+#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
+
+/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
+#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
+
+/* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */
+#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
+
+/* Bit 5 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
+#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
+
+/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
+
+/* Register: NFCT_SELRES */
+/* Description: NFC-A SEL_RES auto-response settings */
+
+/* Bit 7 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
+#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
+
+/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
+#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
+
+/* Bits 4..3 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
+#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
+
+/* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */
+#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
+#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
+
+/* Bits 1..0 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
+#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non Volatile Memory Controller */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag */
+
+/* Bit 0 : NVMC is ready or busy */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
+
+/* Register: NVMC_READYNEXT */
+/* Description: Ready flag */
+
+/* Bit 0 : NVMC can accept a new write operation */
+#define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
+#define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
+#define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
+#define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register */
+
+/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
+#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
+#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
+
+/* Register: NVMC_ERASEPAGE */
+/* Description: Register for erasing a page in code area */
+
+/* Bits 31..0 : Register for starting erase of a page in code area */
+#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
+#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
+
+/* Register: NVMC_ERASEPCR1 */
+/* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */
+
+/* Bits 31..0 : Register for erasing a page in code area, equivalent to ERASEPAGE */
+#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory */
+
+/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
+
+/* Register: NVMC_ERASEPCR0 */
+/* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */
+
+/* Bits 31..0 : Register for starting erase of a page in code area, equivalent to ERASEPAGE */
+#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for erasing user information configuration registers */
+
+/* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
+
+/* Register: NVMC_ERASEPAGEPARTIAL */
+/* Description: Register for partial erase of a page in code area */
+
+/* Bits 31..0 : Register for starting partial erase of a page in code area */
+#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */
+#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */
+
+/* Register: NVMC_ERASEPAGEPARTIALCFG */
+/* Description: Register for partial erase configuration */
+
+/* Bits 6..0 : Duration of the partial erase in milliseconds */
+#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
+#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
+
+/* Register: NVMC_ICACHECNF */
+/* Description: I-code cache configuration register */
+
+/* Bit 8 : Cache profiling enable */
+#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
+#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
+
+/* Bit 0 : Cache enable */
+#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
+#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
+
+/* Register: NVMC_IHIT */
+/* Description: I-code cache hit counter */
+
+/* Bits 31..0 : Number of cache hits */
+#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
+#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
+
+/* Register: NVMC_IMISS */
+/* Description: I-code cache miss counter */
+
+/* Bits 31..0 : Number of cache misses */
+#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
+#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
+
+
+/* Peripheral: GPIO */
+/* Description: GPIO Port 1 */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register */
+
+/* Bit 31 : Set as output pin 31 */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 30 : Set as output pin 30 */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 29 : Set as output pin 29 */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 28 : Set as output pin 28 */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 27 : Set as output pin 27 */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 26 : Set as output pin 26 */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 25 : Set as output pin 25 */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 24 : Set as output pin 24 */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 23 : Set as output pin 23 */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 22 : Set as output pin 22 */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 21 : Set as output pin 21 */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 20 : Set as output pin 20 */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 19 : Set as output pin 19 */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 18 : Set as output pin 18 */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 17 : Set as output pin 17 */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 16 : Set as output pin 16 */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 15 : Set as output pin 15 */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 14 : Set as output pin 14 */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 13 : Set as output pin 13 */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 12 : Set as output pin 12 */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 11 : Set as output pin 11 */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 10 : Set as output pin 10 */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 9 : Set as output pin 9 */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 8 : Set as output pin 8 */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 7 : Set as output pin 7 */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 6 : Set as output pin 6 */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 5 : Set as output pin 5 */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 4 : Set as output pin 4 */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 3 : Set as output pin 3 */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 2 : Set as output pin 2 */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 1 : Set as output pin 1 */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 0 : Set as output pin 0 */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register */
+
+/* Bit 31 : Set as input pin 31 */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 30 : Set as input pin 30 */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 29 : Set as input pin 29 */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 28 : Set as input pin 28 */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 27 : Set as input pin 27 */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 26 : Set as input pin 26 */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 25 : Set as input pin 25 */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 24 : Set as input pin 24 */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 23 : Set as input pin 23 */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 22 : Set as input pin 22 */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 21 : Set as input pin 21 */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 20 : Set as input pin 20 */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 19 : Set as input pin 19 */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 18 : Set as input pin 18 */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 17 : Set as input pin 17 */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 16 : Set as input pin 16 */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 15 : Set as input pin 15 */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 14 : Set as input pin 14 */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 13 : Set as input pin 13 */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 12 : Set as input pin 12 */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 11 : Set as input pin 11 */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 10 : Set as input pin 10 */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 9 : Set as input pin 9 */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 8 : Set as input pin 8 */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 7 : Set as input pin 7 */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 6 : Set as input pin 6 */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 5 : Set as input pin 5 */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 4 : Set as input pin 4 */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 3 : Set as input pin 3 */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 2 : Set as input pin 2 */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 1 : Set as input pin 1 */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 0 : Set as input pin 0 */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Register: GPIO_LATCH */
+/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
+
+/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
+
+/* Register: GPIO_DETECTMODE */
+/* Description: Select between default DETECT signal behaviour and LDETECT mode */
+
+/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
+#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
+#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Description collection: Configuration of GPIO pins */
+
+/* Bits 17..16 : Pin sensing mechanism */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
+#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
+#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
+
+/* Bits 10..8 : Drive configuration */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
+
+/* Bits 3..2 : Pull configuration */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
+#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
+#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
+
+/* Bit 1 : Connect or disconnect input buffer */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
+
+/* Bit 0 : Pin direction. Same physical register as DIR register */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
+
+
+/* Peripheral: PDM */
+/* Description: Pulse Density Modulation (Digital Microphone) Interface */
+
+/* Register: PDM_TASKS_START */
+/* Description: Starts continuous PDM transfer */
+
+/* Bit 0 : Starts continuous PDM transfer */
+#define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PDM_TASKS_STOP */
+/* Description: Stops PDM transfer */
+
+/* Bit 0 : Stops PDM transfer */
+#define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PDM_EVENTS_STARTED */
+/* Description: PDM transfer has started */
+
+/* Bit 0 : PDM transfer has started */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: PDM_EVENTS_STOPPED */
+/* Description: PDM transfer has finished */
+
+/* Bit 0 : PDM transfer has finished */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: PDM_EVENTS_END */
+/* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
+
+/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
+#define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: PDM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 2 : Enable or disable interrupt for event END */
+#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
+#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event STARTED */
+#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to enable interrupt for event END */
+#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event STARTED */
+#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: PDM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to disable interrupt for event END */
+#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event STARTED */
+#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: PDM_ENABLE */
+/* Description: PDM module enable register */
+
+/* Bit 0 : Enable or disable PDM module */
+#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_PDMCLKCTRL */
+/* Description: PDM clock generator control */
+
+/* Bits 31..0 : PDM_CLK frequency */
+#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
+#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
+#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
+#define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
+
+/* Register: PDM_MODE */
+/* Description: Defines the routing of the connected PDM microphones' signals */
+
+/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
+#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
+#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
+#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
+#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
+
+/* Bit 0 : Mono or stereo operation */
+#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
+#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
+#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
+#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
+
+/* Register: PDM_GAINL */
+/* Description: Left output gain adjustment */
+
+/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */
+#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
+#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
+#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment */
+#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_GAINR */
+/* Description: Right output gain adjustment */
+
+/* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
+#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
+#define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
+#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment */
+#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_RATIO */
+/* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
+
+/* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
+#define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */
+#define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */
+
+/* Register: PDM_PSEL_CLK */
+/* Description: Pin number configuration for PDM CLK signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define PDM_PSEL_CLK_PORT_Msk (0x1UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_PSEL_DIN */
+/* Description: Pin number configuration for PDM DIN signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define PDM_PSEL_DIN_PORT_Msk (0x1UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_SAMPLE_PTR */
+/* Description: RAM address pointer to write samples to with EasyDMA */
+
+/* Bits 31..0 : Address to write PDM samples to over DMA */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
+
+/* Register: PDM_SAMPLE_MAXCNT */
+/* Description: Number of samples to allocate memory for in EasyDMA mode */
+
+/* Bits 14..0 : Length of DMA RAM allocation in number of samples */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
+
+
+/* Peripheral: POWER */
+/* Description: Power control */
+
+/* Register: POWER_TASKS_CONSTLAT */
+/* Description: Enable Constant Latency mode */
+
+/* Bit 0 : Enable Constant Latency mode */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: POWER_TASKS_LOWPWR */
+/* Description: Enable Low-power mode (variable latency) */
+
+/* Bit 0 : Enable Low-power mode (variable latency) */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: POWER_EVENTS_POFWARN */
+/* Description: Power failure warning */
+
+/* Bit 0 : Power failure warning */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_SLEEPENTER */
+/* Description: CPU entered WFI/WFE sleep */
+
+/* Bit 0 : CPU entered WFI/WFE sleep */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_SLEEPEXIT */
+/* Description: CPU exited WFI/WFE sleep */
+
+/* Bit 0 : CPU exited WFI/WFE sleep */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_USBDETECTED */
+/* Description: Voltage supply detected on VBUS */
+
+/* Bit 0 : Voltage supply detected on VBUS */
+#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */
+#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */
+#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_USBREMOVED */
+/* Description: Voltage supply removed from VBUS */
+
+/* Bit 0 : Voltage supply removed from VBUS */
+#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */
+#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */
+#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_USBPWRRDY */
+/* Description: USB 3.3 V supply ready */
+
+/* Bit 0 : USB 3.3 V supply ready */
+#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */
+#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */
+#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */
+#define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
+#define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
+#define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */
+#define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
+#define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
+#define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */
+#define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
+#define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
+#define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
+#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
+#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event POFWARN */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
+
+/* Register: POWER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */
+#define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
+#define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
+#define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */
+#define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
+#define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
+#define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */
+#define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
+#define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
+#define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
+#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
+#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event POFWARN */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason */
+
+/* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */
+#define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */
+#define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */
+#define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_VBUS_Detected (1UL) /*!< Detected */
+
+/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
+#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
+#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
+#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
+
+/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
+
+/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
+
+/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
+
+/* Bit 3 : Reset from CPU lock-up detected */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
+
+/* Bit 2 : Reset from soft reset detected */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
+
+/* Bit 1 : Reset from watchdog detected */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
+
+/* Bit 0 : Reset from pin-reset detected */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
+
+/* Register: POWER_RAMSTATUS */
+/* Description: Deprecated register - RAM status register */
+
+/* Bit 3 : RAM block 3 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
+
+/* Bit 2 : RAM block 2 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
+
+/* Bit 1 : RAM block 1 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
+
+/* Bit 0 : RAM block 0 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
+
+/* Register: POWER_USBREGSTATUS */
+/* Description: USB supply status */
+
+/* Bit 1 : USB supply output settling time elapsed */
+#define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */
+#define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */
+#define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */
+#define POWER_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */
+
+/* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */
+#define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */
+#define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */
+#define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */
+#define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System OFF register */
+
+/* Bit 0 : Enable System OFF mode */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
+
+/* Register: POWER_POFCON */
+/* Description: Power-fail comparator configuration */
+
+/* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */
+#define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */
+#define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */
+#define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */
+#define POWER_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */
+#define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */
+#define POWER_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */
+#define POWER_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */
+#define POWER_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */
+#define POWER_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */
+#define POWER_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */
+#define POWER_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */
+#define POWER_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */
+#define POWER_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */
+#define POWER_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */
+#define POWER_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */
+#define POWER_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */
+#define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */
+#define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */
+
+/* Bits 4..1 : Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
+#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
+#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
+#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
+#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
+#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
+#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
+#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
+#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
+#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
+#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
+#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
+
+/* Bit 0 : Enable or disable power failure warning */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_GPREGRET2 */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_DCDCEN */
+/* Description: Enable DC/DC converter for REG1 stage */
+
+/* Bit 0 : Enable DC/DC converter for REG1 stage. */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_MAINREGSTATUS */
+/* Description: Main supply status */
+
+/* Bit 0 : Main supply status */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */
+
+/* Register: POWER_RAM_POWER */
+/* Description: Description cluster: RAMn power control register */
+
+/* Bit 31 : Keep retention on RAM section S15 when RAM section is off */
+#define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
+#define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
+#define POWER_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S15RETENTION_On (1UL) /*!< On */
+
+/* Bit 30 : Keep retention on RAM section S14 when RAM section is off */
+#define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
+#define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
+#define POWER_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S14RETENTION_On (1UL) /*!< On */
+
+/* Bit 29 : Keep retention on RAM section S13 when RAM section is off */
+#define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
+#define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
+#define POWER_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S13RETENTION_On (1UL) /*!< On */
+
+/* Bit 28 : Keep retention on RAM section S12 when RAM section is off */
+#define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
+#define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
+#define POWER_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S12RETENTION_On (1UL) /*!< On */
+
+/* Bit 27 : Keep retention on RAM section S11 when RAM section is off */
+#define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
+#define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
+#define POWER_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S11RETENTION_On (1UL) /*!< On */
+
+/* Bit 26 : Keep retention on RAM section S10 when RAM section is off */
+#define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
+#define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
+#define POWER_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S10RETENTION_On (1UL) /*!< On */
+
+/* Bit 25 : Keep retention on RAM section S9 when RAM section is off */
+#define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
+#define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
+#define POWER_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S9RETENTION_On (1UL) /*!< On */
+
+/* Bit 24 : Keep retention on RAM section S8 when RAM section is off */
+#define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
+#define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
+#define POWER_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S8RETENTION_On (1UL) /*!< On */
+
+/* Bit 23 : Keep retention on RAM section S7 when RAM section is off */
+#define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
+#define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
+#define POWER_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S7RETENTION_On (1UL) /*!< On */
+
+/* Bit 22 : Keep retention on RAM section S6 when RAM section is off */
+#define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
+#define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
+#define POWER_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S6RETENTION_On (1UL) /*!< On */
+
+/* Bit 21 : Keep retention on RAM section S5 when RAM section is off */
+#define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
+#define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
+#define POWER_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S5RETENTION_On (1UL) /*!< On */
+
+/* Bit 20 : Keep retention on RAM section S4 when RAM section is off */
+#define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
+#define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
+#define POWER_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S4RETENTION_On (1UL) /*!< On */
+
+/* Bit 19 : Keep retention on RAM section S3 when RAM section is off */
+#define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define POWER_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
+
+/* Bit 18 : Keep retention on RAM section S2 when RAM section is off */
+#define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define POWER_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is off */
+#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is off */
+#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 15 : Keep RAM section S15 on or off in System ON mode. */
+#define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
+#define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
+#define POWER_RAM_POWER_S15POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S15POWER_On (1UL) /*!< On */
+
+/* Bit 14 : Keep RAM section S14 on or off in System ON mode. */
+#define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
+#define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
+#define POWER_RAM_POWER_S14POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S14POWER_On (1UL) /*!< On */
+
+/* Bit 13 : Keep RAM section S13 on or off in System ON mode. */
+#define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
+#define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
+#define POWER_RAM_POWER_S13POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S13POWER_On (1UL) /*!< On */
+
+/* Bit 12 : Keep RAM section S12 on or off in System ON mode. */
+#define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
+#define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
+#define POWER_RAM_POWER_S12POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S12POWER_On (1UL) /*!< On */
+
+/* Bit 11 : Keep RAM section S11 on or off in System ON mode. */
+#define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
+#define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
+#define POWER_RAM_POWER_S11POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S11POWER_On (1UL) /*!< On */
+
+/* Bit 10 : Keep RAM section S10 on or off in System ON mode. */
+#define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
+#define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
+#define POWER_RAM_POWER_S10POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S10POWER_On (1UL) /*!< On */
+
+/* Bit 9 : Keep RAM section S9 on or off in System ON mode. */
+#define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
+#define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
+#define POWER_RAM_POWER_S9POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S9POWER_On (1UL) /*!< On */
+
+/* Bit 8 : Keep RAM section S8 on or off in System ON mode. */
+#define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
+#define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
+#define POWER_RAM_POWER_S8POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S8POWER_On (1UL) /*!< On */
+
+/* Bit 7 : Keep RAM section S7 on or off in System ON mode. */
+#define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
+#define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
+#define POWER_RAM_POWER_S7POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S7POWER_On (1UL) /*!< On */
+
+/* Bit 6 : Keep RAM section S6 on or off in System ON mode. */
+#define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
+#define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
+#define POWER_RAM_POWER_S6POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S6POWER_On (1UL) /*!< On */
+
+/* Bit 5 : Keep RAM section S5 on or off in System ON mode. */
+#define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
+#define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
+#define POWER_RAM_POWER_S5POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S5POWER_On (1UL) /*!< On */
+
+/* Bit 4 : Keep RAM section S4 on or off in System ON mode. */
+#define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
+#define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
+#define POWER_RAM_POWER_S4POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S4POWER_On (1UL) /*!< On */
+
+/* Bit 3 : Keep RAM section S3 on or off in System ON mode. */
+#define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define POWER_RAM_POWER_S3POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S3POWER_On (1UL) /*!< On */
+
+/* Bit 2 : Keep RAM section S2 on or off in System ON mode. */
+#define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define POWER_RAM_POWER_S2POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S2POWER_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 on or off in System ON mode. */
+#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 on or off in System ON mode. */
+#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERSET */
+/* Description: Description cluster: RAMn power control set register */
+
+/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
+#define POWER_RAM_POWERSET_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
+#define POWER_RAM_POWERSET_S15RETENTION_On (1UL) /*!< On */
+
+/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
+#define POWER_RAM_POWERSET_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
+#define POWER_RAM_POWERSET_S14RETENTION_On (1UL) /*!< On */
+
+/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
+#define POWER_RAM_POWERSET_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
+#define POWER_RAM_POWERSET_S13RETENTION_On (1UL) /*!< On */
+
+/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
+#define POWER_RAM_POWERSET_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
+#define POWER_RAM_POWERSET_S12RETENTION_On (1UL) /*!< On */
+
+/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
+#define POWER_RAM_POWERSET_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
+#define POWER_RAM_POWERSET_S11RETENTION_On (1UL) /*!< On */
+
+/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
+#define POWER_RAM_POWERSET_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
+#define POWER_RAM_POWERSET_S10RETENTION_On (1UL) /*!< On */
+
+/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
+#define POWER_RAM_POWERSET_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
+#define POWER_RAM_POWERSET_S9RETENTION_On (1UL) /*!< On */
+
+/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
+#define POWER_RAM_POWERSET_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
+#define POWER_RAM_POWERSET_S8RETENTION_On (1UL) /*!< On */
+
+/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
+#define POWER_RAM_POWERSET_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
+#define POWER_RAM_POWERSET_S7RETENTION_On (1UL) /*!< On */
+
+/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
+#define POWER_RAM_POWERSET_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
+#define POWER_RAM_POWERSET_S6RETENTION_On (1UL) /*!< On */
+
+/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
+#define POWER_RAM_POWERSET_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
+#define POWER_RAM_POWERSET_S5RETENTION_On (1UL) /*!< On */
+
+/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
+#define POWER_RAM_POWERSET_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
+#define POWER_RAM_POWERSET_S4RETENTION_On (1UL) /*!< On */
+
+/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define POWER_RAM_POWERSET_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define POWER_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
+
+/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define POWER_RAM_POWERSET_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define POWER_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
+#define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
+#define POWER_RAM_POWERSET_S15POWER_On (1UL) /*!< On */
+
+/* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
+#define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
+#define POWER_RAM_POWERSET_S14POWER_On (1UL) /*!< On */
+
+/* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
+#define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
+#define POWER_RAM_POWERSET_S13POWER_On (1UL) /*!< On */
+
+/* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
+#define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
+#define POWER_RAM_POWERSET_S12POWER_On (1UL) /*!< On */
+
+/* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
+#define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
+#define POWER_RAM_POWERSET_S11POWER_On (1UL) /*!< On */
+
+/* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
+#define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
+#define POWER_RAM_POWERSET_S10POWER_On (1UL) /*!< On */
+
+/* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
+#define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
+#define POWER_RAM_POWERSET_S9POWER_On (1UL) /*!< On */
+
+/* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
+#define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
+#define POWER_RAM_POWERSET_S8POWER_On (1UL) /*!< On */
+
+/* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
+#define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
+#define POWER_RAM_POWERSET_S7POWER_On (1UL) /*!< On */
+
+/* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
+#define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
+#define POWER_RAM_POWERSET_S6POWER_On (1UL) /*!< On */
+
+/* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
+#define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
+#define POWER_RAM_POWERSET_S5POWER_On (1UL) /*!< On */
+
+/* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
+#define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
+#define POWER_RAM_POWERSET_S4POWER_On (1UL) /*!< On */
+
+/* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define POWER_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
+
+/* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define POWER_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERCLR */
+/* Description: Description cluster: RAMn power control clear register */
+
+/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
+#define POWER_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
+#define POWER_RAM_POWERCLR_S15RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
+#define POWER_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
+#define POWER_RAM_POWERCLR_S14RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
+#define POWER_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
+#define POWER_RAM_POWERCLR_S13RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
+#define POWER_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
+#define POWER_RAM_POWERCLR_S12RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
+#define POWER_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
+#define POWER_RAM_POWERCLR_S11RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
+#define POWER_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
+#define POWER_RAM_POWERCLR_S10RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
+#define POWER_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
+#define POWER_RAM_POWERCLR_S9RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
+#define POWER_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
+#define POWER_RAM_POWERCLR_S8RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
+#define POWER_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
+#define POWER_RAM_POWERCLR_S7RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
+#define POWER_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
+#define POWER_RAM_POWERCLR_S6RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
+#define POWER_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
+#define POWER_RAM_POWERCLR_S5RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
+#define POWER_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
+#define POWER_RAM_POWERCLR_S4RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define POWER_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define POWER_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define POWER_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define POWER_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
+#define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
+#define POWER_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */
+
+/* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
+#define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
+#define POWER_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */
+
+/* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
+#define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
+#define POWER_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */
+
+/* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
+#define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
+#define POWER_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */
+
+/* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
+#define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
+#define POWER_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */
+
+/* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
+#define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
+#define POWER_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */
+
+/* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
+#define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
+#define POWER_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */
+
+/* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
+#define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
+#define POWER_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */
+
+/* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
+#define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
+#define POWER_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */
+
+/* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
+#define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
+#define POWER_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */
+
+/* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
+#define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
+#define POWER_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */
+
+/* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
+#define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
+#define POWER_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */
+
+/* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define POWER_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
+
+/* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define POWER_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
+
+/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
+
+/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
+
+
+/* Peripheral: PPI */
+/* Description: Programmable Peripheral Interconnect */
+
+/* Register: PPI_TASKS_CHG_EN */
+/* Description: Description cluster: Enable channel group n */
+
+/* Bit 0 : Enable channel group n */
+#define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
+#define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
+#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PPI_TASKS_CHG_DIS */
+/* Description: Description cluster: Disable channel group n */
+
+/* Bit 0 : Disable channel group n */
+#define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
+#define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
+#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable register */
+
+/* Bit 31 : Enable or disable channel 31 */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 30 : Enable or disable channel 30 */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 29 : Enable or disable channel 29 */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 28 : Enable or disable channel 28 */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 27 : Enable or disable channel 27 */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 26 : Enable or disable channel 26 */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 25 : Enable or disable channel 25 */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 24 : Enable or disable channel 24 */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 23 : Enable or disable channel 23 */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 22 : Enable or disable channel 22 */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 21 : Enable or disable channel 21 */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 20 : Enable or disable channel 20 */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 19 : Enable or disable channel 19 */
+#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 18 : Enable or disable channel 18 */
+#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 17 : Enable or disable channel 17 */
+#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 16 : Enable or disable channel 16 */
+#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 15 : Enable or disable channel 15 */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 14 : Enable or disable channel 14 */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 13 : Enable or disable channel 13 */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 12 : Enable or disable channel 12 */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 11 : Enable or disable channel 11 */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 10 : Enable or disable channel 10 */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 9 : Enable or disable channel 9 */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 8 : Enable or disable channel 8 */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 7 : Enable or disable channel 7 */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 6 : Enable or disable channel 6 */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 5 : Enable or disable channel 5 */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 4 : Enable or disable channel 4 */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 3 : Enable or disable channel 3 */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 2 : Enable or disable channel 2 */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 1 : Enable or disable channel 1 */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 0 : Enable or disable channel 0 */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set register */
+
+/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear register */
+
+/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
+
+/* Register: PPI_CH_EEP */
+/* Description: Description cluster: Channel n event end-point */
+
+/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
+#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
+#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
+
+/* Register: PPI_CH_TEP */
+/* Description: Description cluster: Channel n task end-point */
+
+/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
+#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+/* Register: PPI_CHG */
+/* Description: Description collection: Channel group n */
+
+/* Bit 31 : Include or exclude channel 31 */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH31_Included (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude channel 30 */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH30_Included (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude channel 29 */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH29_Included (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude channel 28 */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH28_Included (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude channel 27 */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH27_Included (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude channel 26 */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH26_Included (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude channel 25 */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH25_Included (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude channel 24 */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH24_Included (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude channel 23 */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH23_Included (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude channel 22 */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH22_Included (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude channel 21 */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH21_Included (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude channel 20 */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH20_Included (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude channel 19 */
+#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH19_Included (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude channel 18 */
+#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH18_Included (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude channel 17 */
+#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH17_Included (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude channel 16 */
+#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH16_Included (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude channel 15 */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH15_Included (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude channel 14 */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH14_Included (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude channel 13 */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH13_Included (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude channel 12 */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH12_Included (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude channel 11 */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH11_Included (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude channel 10 */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH10_Included (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude channel 9 */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH9_Included (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude channel 8 */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH8_Included (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude channel 7 */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH7_Included (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude channel 6 */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH6_Included (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude channel 5 */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH5_Included (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude channel 4 */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH4_Included (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude channel 3 */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH3_Included (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude channel 2 */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH2_Included (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude channel 1 */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH1_Included (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude channel 0 */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH0_Included (1UL) /*!< Include */
+
+/* Register: PPI_FORK_TEP */
+/* Description: Description cluster: Channel n task end-point */
+
+/* Bits 31..0 : Pointer to task register */
+#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+
+/* Peripheral: PWM */
+/* Description: Pulse width modulation unit 0 */
+
+/* Register: PWM_TASKS_STOP */
+/* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
+
+/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
+#define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PWM_TASKS_SEQSTART */
+/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
+
+/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
+#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
+#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
+#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PWM_TASKS_NEXTSTEP */
+/* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
+
+/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
+#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
+#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
+#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PWM_EVENTS_STOPPED */
+/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
+
+/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_SEQSTARTED */
+/* Description: Description collection: First PWM period started on sequence n */
+
+/* Bit 0 : First PWM period started on sequence n */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_SEQEND */
+/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
+
+/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_PWMPERIODEND */
+/* Description: Emitted at the end of each PWM period */
+
+/* Bit 0 : Emitted at the end of each PWM period */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_LOOPSDONE */
+/* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
+
+/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
+#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
+#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
+#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: PWM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
+#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
+#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
+#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
+#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
+#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
+#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
+#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
+#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
+#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
+#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
+#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
+#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
+#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: PWM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
+#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
+#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
+#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
+#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
+#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
+#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: PWM_ENABLE */
+/* Description: PWM module enable register */
+
+/* Bit 0 : Enable or disable PWM module */
+#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
+#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_MODE */
+/* Description: Selects operating mode of the wave counter */
+
+/* Bit 0 : Selects up mode or up-and-down mode for the counter */
+#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
+#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
+
+/* Register: PWM_COUNTERTOP */
+/* Description: Value up to which the pulse generator counter counts */
+
+/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
+#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
+#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
+
+/* Register: PWM_PRESCALER */
+/* Description: Configuration for PWM_CLK */
+
+/* Bits 2..0 : Prescaler of PWM_CLK */
+#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */
+
+/* Register: PWM_DECODER */
+/* Description: Configuration of the decoder */
+
+/* Bit 8 : Selects source for advancing the active sequence */
+#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
+#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
+#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
+#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
+
+/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
+#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
+#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
+#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
+#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
+#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
+#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
+
+/* Register: PWM_LOOP */
+/* Description: Number of playbacks of a loop */
+
+/* Bits 15..0 : Number of playbacks of pattern cycles */
+#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
+
+/* Register: PWM_SEQ_PTR */
+/* Description: Description cluster: Beginning address in RAM of this sequence */
+
+/* Bits 31..0 : Beginning address in RAM of this sequence */
+#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: PWM_SEQ_CNT */
+/* Description: Description cluster: Number of values (duty cycles) in this sequence */
+
+/* Bits 14..0 : Number of values (duty cycles) in this sequence */
+#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
+
+/* Register: PWM_SEQ_REFRESH */
+/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */
+
+/* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
+#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
+
+/* Register: PWM_SEQ_ENDDELAY */
+/* Description: Description cluster: Time added after the sequence */
+
+/* Bits 23..0 : Time added after the sequence in PWM periods */
+#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: PWM_PSEL_OUT */
+/* Description: Description collection: Output pin select for PWM channel n */
+
+/* Bit 31 : Connection */
+#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
+#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define PWM_PSEL_OUT_PORT_Msk (0x1UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: QDEC */
+/* Description: Quadrature Decoder */
+
+/* Register: QDEC_TASKS_START */
+/* Description: Task starting the quadrature decoder */
+
+/* Bit 0 : Task starting the quadrature decoder */
+#define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: QDEC_TASKS_STOP */
+/* Description: Task stopping the quadrature decoder */
+
+/* Bit 0 : Task stopping the quadrature decoder */
+#define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: QDEC_TASKS_READCLRACC */
+/* Description: Read and clear ACC and ACCDBL */
+
+/* Bit 0 : Read and clear ACC and ACCDBL */
+#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */
+#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */
+#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */
+
+/* Register: QDEC_TASKS_RDCLRACC */
+/* Description: Read and clear ACC */
+
+/* Bit 0 : Read and clear ACC */
+#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */
+#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */
+#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */
+
+/* Register: QDEC_TASKS_RDCLRDBL */
+/* Description: Read and clear ACCDBL */
+
+/* Bit 0 : Read and clear ACCDBL */
+#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */
+#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */
+#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */
+
+/* Register: QDEC_EVENTS_SAMPLERDY */
+/* Description: Event being generated for every new sample value written to the SAMPLE register */
+
+/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
+#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */
+#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */
+#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */
+#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */
+
+/* Register: QDEC_EVENTS_REPORTRDY */
+/* Description: Non-null report ready */
+
+/* Bit 0 : Non-null report ready */
+#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */
+#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */
+#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */
+#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: QDEC_EVENTS_ACCOF */
+/* Description: ACC or ACCDBL register overflow */
+
+/* Bit 0 : ACC or ACCDBL register overflow */
+#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */
+#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */
+#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */
+#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */
+
+/* Register: QDEC_EVENTS_DBLRDY */
+/* Description: Double displacement(s) detected */
+
+/* Bit 0 : Double displacement(s) detected */
+#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */
+#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */
+#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */
+#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: QDEC_EVENTS_STOPPED */
+/* Description: QDEC has been stopped */
+
+/* Bit 0 : QDEC has been stopped */
+#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: QDEC_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between event DBLRDY and task STOP */
+#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event REPORTRDY and task STOP */
+#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: QDEC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to enable interrupt for event STOPPED */
+#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */
+#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event ACCOF */
+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
+
+/* Register: QDEC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to disable interrupt for event STOPPED */
+#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */
+#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event ACCOF */
+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
+
+/* Register: QDEC_ENABLE */
+/* Description: Enable the quadrature decoder */
+
+/* Bit 0 : Enable or disable the quadrature decoder */
+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: QDEC_LEDPOL */
+/* Description: LED output pin polarity */
+
+/* Bit 0 : LED output pin polarity */
+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
+
+/* Register: QDEC_SAMPLEPER */
+/* Description: Sample period */
+
+/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
+
+/* Register: QDEC_SAMPLE */
+/* Description: Motion sample value */
+
+/* Bits 31..0 : Last motion sample */
+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
+
+/* Register: QDEC_REPORTPER */
+/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
+
+/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
+#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
+#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
+#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
+#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
+#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
+#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
+#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
+#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
+
+/* Register: QDEC_ACC */
+/* Description: Register accumulating the valid transitions */
+
+/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
+#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
+#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
+
+/* Register: QDEC_ACCREAD */
+/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
+
+/* Bits 31..0 : Snapshot of the ACC register. */
+#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
+#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
+
+/* Register: QDEC_PSEL_LED */
+/* Description: Pin select for LED signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QDEC_PSEL_LED_PORT_Msk (0x1UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_A */
+/* Description: Pin select for A signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QDEC_PSEL_A_PORT_Msk (0x1UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_B */
+/* Description: Pin select for B signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QDEC_PSEL_B_PORT_Msk (0x1UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_DBFEN */
+/* Description: Enable input debounce filters */
+
+/* Bit 0 : Enable input debounce filters */
+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
+
+/* Register: QDEC_LEDPRE */
+/* Description: Time period the LED is switched ON prior to sampling */
+
+/* Bits 8..0 : Period in us the LED is switched on prior to sampling */
+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
+
+/* Register: QDEC_ACCDBL */
+/* Description: Register accumulating the number of detected double transitions */
+
+/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
+
+/* Register: QDEC_ACCDBLREAD */
+/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
+
+/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
+
+
+/* Peripheral: RADIO */
+/* Description: 2.4 GHz radio */
+
+/* Register: RADIO_TASKS_TXEN */
+/* Description: Enable RADIO in TX mode */
+
+/* Bit 0 : Enable RADIO in TX mode */
+#define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
+#define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
+#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_RXEN */
+/* Description: Enable RADIO in RX mode */
+
+/* Bit 0 : Enable RADIO in RX mode */
+#define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
+#define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
+#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_START */
+/* Description: Start RADIO */
+
+/* Bit 0 : Start RADIO */
+#define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_STOP */
+/* Description: Stop RADIO */
+
+/* Bit 0 : Stop RADIO */
+#define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_DISABLE */
+/* Description: Disable RADIO */
+
+/* Bit 0 : Disable RADIO */
+#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
+#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
+#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_RSSISTART */
+/* Description: Start the RSSI and take one single sample of the receive signal strength */
+
+/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */
+#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
+#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
+#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_RSSISTOP */
+/* Description: Stop the RSSI measurement */
+
+/* Bit 0 : Stop the RSSI measurement */
+#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
+#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
+#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_BCSTART */
+/* Description: Start the bit counter */
+
+/* Bit 0 : Start the bit counter */
+#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
+#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
+#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_BCSTOP */
+/* Description: Stop the bit counter */
+
+/* Bit 0 : Stop the bit counter */
+#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
+#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
+#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_EDSTART */
+/* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */
+
+/* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */
+#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */
+#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */
+#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_EDSTOP */
+/* Description: Stop the energy detect measurement */
+
+/* Bit 0 : Stop the energy detect measurement */
+#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */
+#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */
+#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_CCASTART */
+/* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */
+
+/* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */
+#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */
+#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */
+#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_CCASTOP */
+/* Description: Stop the clear channel assessment */
+
+/* Bit 0 : Stop the clear channel assessment */
+#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */
+#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */
+#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_EVENTS_READY */
+/* Description: RADIO has ramped up and is ready to be started */
+
+/* Bit 0 : RADIO has ramped up and is ready to be started */
+#define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_ADDRESS */
+/* Description: Address sent or received */
+
+/* Bit 0 : Address sent or received */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_PAYLOAD */
+/* Description: Packet payload sent or received */
+
+/* Bit 0 : Packet payload sent or received */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_END */
+/* Description: Packet sent or received */
+
+/* Bit 0 : Packet sent or received */
+#define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_DISABLED */
+/* Description: RADIO has been disabled */
+
+/* Bit 0 : RADIO has been disabled */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_DEVMATCH */
+/* Description: A device address match occurred on the last received packet */
+
+/* Bit 0 : A device address match occurred on the last received packet */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_DEVMISS */
+/* Description: No device address match occurred on the last received packet */
+
+/* Bit 0 : No device address match occurred on the last received packet */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_RSSIEND */
+/* Description: Sampling of receive signal strength complete */
+
+/* Bit 0 : Sampling of receive signal strength complete */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_BCMATCH */
+/* Description: Bit counter reached bit count value */
+
+/* Bit 0 : Bit counter reached bit count value */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_CRCOK */
+/* Description: Packet received with CRC ok */
+
+/* Bit 0 : Packet received with CRC ok */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_CRCERROR */
+/* Description: Packet received with CRC error */
+
+/* Bit 0 : Packet received with CRC error */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_FRAMESTART */
+/* Description: IEEE 802.15.4 length field received */
+
+/* Bit 0 : IEEE 802.15.4 length field received */
+#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */
+#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */
+#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_EDEND */
+/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */
+
+/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */
+#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */
+#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */
+#define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_EDSTOPPED */
+/* Description: The sampling of energy detection has stopped */
+
+/* Bit 0 : The sampling of energy detection has stopped */
+#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */
+#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */
+#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_CCAIDLE */
+/* Description: Wireless medium in idle - clear to send */
+
+/* Bit 0 : Wireless medium in idle - clear to send */
+#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */
+#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */
+#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_CCABUSY */
+/* Description: Wireless medium busy - do not send */
+
+/* Bit 0 : Wireless medium busy - do not send */
+#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */
+#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */
+#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_CCASTOPPED */
+/* Description: The CCA has stopped */
+
+/* Bit 0 : The CCA has stopped */
+#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */
+#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */
+#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_RATEBOOST */
+/* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
+
+/* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
+#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */
+#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */
+#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_TXREADY */
+/* Description: RADIO has ramped up and is ready to be started TX path */
+
+/* Bit 0 : RADIO has ramped up and is ready to be started TX path */
+#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */
+#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */
+#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_RXREADY */
+/* Description: RADIO has ramped up and is ready to be started RX path */
+
+/* Bit 0 : RADIO has ramped up and is ready to be started RX path */
+#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */
+#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */
+#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_MHRMATCH */
+/* Description: MAC header match found */
+
+/* Bit 0 : MAC header match found */
+#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */
+#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */
+#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_PHYEND */
+/* Description: Generated when last bit is sent on air */
+
+/* Bit 0 : Generated when last bit is sent on air */
+#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */
+#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */
+#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_CTEPRESENT */
+/* Description: CTE is present (early warning right after receiving CTEInfo byte) */
+
+/* Bit 0 : CTE is present (early warning right after receiving CTEInfo byte) */
+#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */
+#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask of EVENTS_CTEPRESENT field. */
+#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 21 : Shortcut between event PHYEND and task START */
+#define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */
+#define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */
+#define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 20 : Shortcut between event PHYEND and task DISABLE */
+#define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */
+#define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */
+#define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 19 : Shortcut between event RXREADY and task START */
+#define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */
+#define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */
+#define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 18 : Shortcut between event TXREADY and task START */
+#define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */
+#define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */
+#define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 17 : Shortcut between event CCAIDLE and task STOP */
+#define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */
+#define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */
+#define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 16 : Shortcut between event EDEND and task DISABLE */
+#define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */
+#define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */
+#define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 15 : Shortcut between event READY and task EDSTART */
+#define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */
+#define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */
+#define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between event CCABUSY and task DISABLE */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between event CCAIDLE and task TXEN */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between event RXREADY and task CCASTART */
+#define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */
+#define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */
+#define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between event END and task START */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event DISABLED and task RXEN */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event DISABLED and task TXEN */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event END and task DISABLE */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event READY and task START */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RADIO_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 28 : Write '1' to enable interrupt for event CTEPRESENT */
+#define RADIO_INTENSET_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
+#define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
+#define RADIO_INTENSET_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CTEPRESENT_Set (1UL) /*!< Enable */
+
+/* Bit 27 : Write '1' to enable interrupt for event PHYEND */
+#define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
+#define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
+#define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */
+#define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
+#define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
+#define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 22 : Write '1' to enable interrupt for event RXREADY */
+#define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
+#define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
+#define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */
+
+/* Bit 21 : Write '1' to enable interrupt for event TXREADY */
+#define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
+#define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
+#define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
+#define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
+#define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
+#define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
+#define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
+#define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
+#define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event CCABUSY */
+#define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
+#define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
+#define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
+#define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
+#define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
+#define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
+#define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
+#define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
+#define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to enable interrupt for event EDEND */
+#define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */
+#define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */
+#define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */
+#define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
+#define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
+#define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
+#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to enable interrupt for event CRCOK */
+#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event DISABLED */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event END */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event READY */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 28 : Write '1' to disable interrupt for event CTEPRESENT */
+#define RADIO_INTENCLR_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
+#define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
+#define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CTEPRESENT_Clear (1UL) /*!< Disable */
+
+/* Bit 27 : Write '1' to disable interrupt for event PHYEND */
+#define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
+#define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
+#define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */
+#define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
+#define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
+#define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 22 : Write '1' to disable interrupt for event RXREADY */
+#define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
+#define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
+#define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 21 : Write '1' to disable interrupt for event TXREADY */
+#define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
+#define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
+#define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
+#define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
+#define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
+#define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
+#define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
+#define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
+#define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event CCABUSY */
+#define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
+#define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
+#define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
+#define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
+#define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
+#define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
+#define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
+#define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
+#define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to disable interrupt for event EDEND */
+#define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */
+#define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */
+#define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */
+#define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
+#define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
+#define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
+#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to disable interrupt for event CRCOK */
+#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event DISABLED */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event END */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event READY */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status */
+
+/* Bit 0 : CRC status of packet received */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address */
+
+/* Bits 2..0 : Received address */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: CRC field of previously received packet */
+
+/* Bits 23..0 : CRC field of previously received packet */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index */
+
+/* Bits 2..0 : Device address match index */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_PDUSTAT */
+/* Description: Payload status */
+
+/* Bits 2..1 : Status on what rate packet is received with in Long Range */
+#define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */
+#define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */
+#define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125 kbps */
+#define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500 kbps */
+
+/* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */
+#define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */
+#define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */
+#define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */
+#define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */
+
+/* Register: RADIO_CTESTATUS */
+/* Description: CTEInfo parsed from received packet */
+
+/* Bits 7..6 : CTEType parsed from packet */
+#define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */
+#define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */
+
+/* Bit 5 : RFU parsed from packet */
+#define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */
+#define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */
+
+/* Bits 4..0 : CTETime parsed from packet */
+#define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */
+#define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */
+
+/* Register: RADIO_DFESTATUS */
+/* Description: DFE status information */
+
+/* Bit 4 : Internal state of sampling state machine */
+#define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */
+#define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */
+#define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL) /*!< Sampling state Idle */
+#define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL) /*!< Sampling state Sampling */
+
+/* Bits 2..0 : Internal state of switching state machine */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE field. */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL) /*!< Switching state Idle */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL) /*!< Switching state Offset */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL) /*!< Switching state Guard */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL) /*!< Switching state Ref */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL) /*!< Switching state Switching */
+#define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL) /*!< Switching state Ending */
+
+/* Register: RADIO_PACKETPTR */
+/* Description: Packet pointer */
+
+/* Bits 31..0 : Packet pointer */
+#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
+#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency */
+
+/* Bit 8 : Channel map selection. */
+#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
+#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
+#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
+#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
+
+/* Bits 6..0 : Radio channel frequency */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power */
+
+/* Bits 7..0 : RADIO output power */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x5UL) /*!< +5 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation */
+
+/* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */
+#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */
+#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbps TX, 125 kbps and 500 kbps RX */
+#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbps TX, 125 kbps and 500 kbps RX */
+#define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration register 0 */
+
+/* Bits 30..29 : Length of TERM field in Long Range operation */
+#define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */
+#define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */
+
+/* Bit 26 : Indicates if LENGTH field contains CRC or not */
+#define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */
+#define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */
+#define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */
+#define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */
+
+/* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */
+#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
+#define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
+#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
+#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
+#define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
+#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */
+
+/* Bits 23..22 : Length of code indicator - long range */
+#define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */
+#define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */
+
+/* Bit 20 : Include or exclude S1 field in RAM */
+#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */
+#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
+
+/* Bits 19..16 : Length on air of S1 field in number of bits. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length on air of S0 field in number of bytes. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length on air of LENGTH field in number of bits. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration register 1 */
+
+/* Bit 25 : Enable or disable packet whitening */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_BASE0 */
+/* Description: Base address 0 */
+
+/* Bits 31..0 : Base address 0 */
+#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
+#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
+
+/* Register: RADIO_BASE1 */
+/* Description: Base address 1 */
+
+/* Bits 31..0 : Base address 1 */
+#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
+#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0-3 */
+
+/* Bits 31..24 : Address prefix 3. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4-7 */
+
+/* Bits 31..24 : Address prefix 7. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select */
+
+/* Bits 2..0 : Transmit address select */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select */
+
+/* Bit 7 : Enable or disable reception on logical address 7. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable reception on logical address 6. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable reception on logical address 5. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable reception on logical address 4. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable reception on logical address 3. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable reception on logical address 2. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable reception on logical address 1. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable reception on logical address 0. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration */
+
+/* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
+#define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */
+
+/* Bits 1..0 : CRC length in number of bytes. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial */
+
+/* Bits 23..0 : CRC polynomial */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value */
+
+/* Bits 23..0 : CRC initial value */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TIFS */
+/* Description: Interframe spacing in us */
+
+/* Bits 9..0 : Interframe spacing in us */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample */
+
+/* Bits 6..0 : RSSI sample */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state */
+
+/* Bits 3..0 : Current radio state */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
+#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
+#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
+#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
+#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
+#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
+#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
+#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
+#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value */
+
+/* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_BCC */
+/* Description: Bit counter compare */
+
+/* Bits 31..0 : Bit counter compare */
+#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
+#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
+
+/* Register: RADIO_DAB */
+/* Description: Description collection: Device address base segment n */
+
+/* Bits 31..0 : Device address base segment n */
+#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
+#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
+
+/* Register: RADIO_DAP */
+/* Description: Description collection: Device address prefix n */
+
+/* Bits 15..0 : Device address prefix n */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration */
+
+/* Bit 15 : TxAdd for device address 7 */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6 */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5 */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4 */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3 */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2 */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1 */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0 */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7 */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
+
+/* Bit 6 : Enable or disable device address matching using device address 6 */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
+
+/* Bit 5 : Enable or disable device address matching using device address 5 */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
+
+/* Bit 4 : Enable or disable device address matching using device address 4 */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
+
+/* Bit 3 : Enable or disable device address matching using device address 3 */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
+
+/* Bit 2 : Enable or disable device address matching using device address 2 */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
+
+/* Bit 1 : Enable or disable device address matching using device address 1 */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable device address matching using device address 0 */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
+
+/* Register: RADIO_MHRMATCHCONF */
+/* Description: Search pattern configuration */
+
+/* Bits 31..0 : Search pattern configuration */
+#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */
+#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */
+
+/* Register: RADIO_MHRMATCHMAS */
+/* Description: Pattern mask */
+
+/* Bits 31..0 : Pattern mask */
+#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */
+#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */
+
+/* Register: RADIO_MODECNF0 */
+/* Description: Radio mode configuration register 0 */
+
+/* Bits 9..8 : Default TX value */
+#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
+#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
+#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
+#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
+#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
+
+/* Bit 0 : Radio ramp-up time */
+#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
+#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
+#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */
+#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */
+
+/* Register: RADIO_SFD */
+/* Description: IEEE 802.15.4 start of frame delimiter */
+
+/* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */
+#define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */
+#define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */
+
+/* Register: RADIO_EDCNT */
+/* Description: IEEE 802.15.4 energy detect loop count */
+
+/* Bits 20..0 : IEEE 802.15.4 energy detect loop count */
+#define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */
+#define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */
+
+/* Register: RADIO_EDSAMPLE */
+/* Description: IEEE 802.15.4 energy detect level */
+
+/* Bits 7..0 : IEEE 802.15.4 energy detect level */
+#define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */
+#define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */
+
+/* Register: RADIO_CCACTRL */
+/* Description: IEEE 802.15.4 clear channel assessment control */
+
+/* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */
+#define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */
+#define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */
+
+/* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. */
+#define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */
+#define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */
+
+/* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */
+#define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */
+#define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */
+
+/* Bits 2..0 : CCA mode of operation */
+#define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */
+#define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */
+#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */
+#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */
+#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */
+#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */
+#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
+
+/* Register: RADIO_DFEMODE */
+/* Description: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */
+
+/* Bits 1..0 : Direction finding operation mode */
+#define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */
+#define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */
+#define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL) /*!< Direction finding mode disabled */
+#define RADIO_DFEMODE_DFEOPMODE_AoD (2UL) /*!< Direction finding mode set to AoD */
+#define RADIO_DFEMODE_DFEOPMODE_AoA (3UL) /*!< Direction finding mode set to AoA */
+
+/* Register: RADIO_CTEINLINECONF */
+/* Description: Configuration for CTE inline mode */
+
+/* Bits 31..24 : S0 bit mask to set which bit to match */
+#define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */
+#define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */
+
+/* Bits 23..16 : S0 bit pattern to match */
+#define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */
+#define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */
+
+/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125us */
+
+/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25us */
+#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125us */
+
+/* Bits 7..6 : Max range of CTETime */
+#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */
+#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */
+#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 */
+#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8us unit */
+#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8us unit */
+
+/* Bit 4 : Sampling/switching if CRC is not OK */
+#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */
+#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of CTEERRORHANDLING field. */
+#define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL) /*!< No sampling and antenna switching when CRC is not OK */
+#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL) /*!< Sampling and antenna switching also when CRC is not OK */
+
+/* Bit 3 : CTEInfo is S1 byte or not */
+#define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */
+#define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 field. */
+#define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */
+#define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL) /*!< CTEInfo is in S1 byte (data PDU) */
+
+/* Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */
+#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */
+#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of CTEINLINECTRLEN field. */
+#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL) /*!< Parsing of CTEInfo is disabled */
+#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL) /*!< Parsing of CTEInfo is enabled */
+
+/* Register: RADIO_DFECTRL1 */
+/* Description: Various configuration for Direction finding */
+
+/* Bits 27..24 : Gain will be lowered by the specified number of gain steps at the start of CTE */
+#define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */
+#define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */
+
+/* Bits 23..20 : Repeat every antenna pattern N times. */
+#define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */
+#define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */
+#define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0UL) /*!< Do not repeat (1 time in total) */
+
+/* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */
+#define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */
+#define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */
+#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4us */
+#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2us */
+#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1us */
+#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5us */
+#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25us */
+#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125us */
+
+/* Bit 15 : Whether to sample I/Q or magnitude/phase */
+#define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */
+#define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */
+#define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL) /*!< Complex samples in I and Q */
+#define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL) /*!< Complex samples as magnitude and phase */
+
+/* Bits 14..12 : Interval between samples in the REFERENCE period */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4us */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2us */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1us */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5us */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25us */
+#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125us */
+
+/* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */
+#define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */
+#define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */
+#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4us */
+#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2us */
+#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1us */
+
+/* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */
+#define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */
+#define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field. */
+#define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL) /*!< Antenna switching/sampling is done in the packet payload */
+#define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL) /*!< AoA/AoD procedure triggered at end of CRC */
+
+/* Bits 5..0 : Length of the AoA/AoD procedure in number of 8 us units */
+#define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */
+#define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */
+
+/* Register: RADIO_DFECTRL2 */
+/* Description: Start offset for Direction finding */
+
+/* Bits 27..16 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start */
+#define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */
+#define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */
+
+/* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */
+#define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */
+#define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */
+
+/* Register: RADIO_SWITCHPATTERN */
+/* Description: GPIO patterns to be used for each antenna */
+
+/* Bits 7..0 : Fill array of GPIO patterns for antenna control */
+#define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */
+#define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */
+
+/* Register: RADIO_CLEARPATTERN */
+/* Description: Clear the GPIO pattern array for antenna control */
+
+/* Bit 0 : Clears GPIO pattern array for antenna control */
+#define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */
+#define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN field. */
+#define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL) /*!< Clear the GPIO pattern */
+
+/* Register: RADIO_PSEL_DFEGPIO */
+/* Description: Description collection: Pin select for DFE pin n */
+
+/* Bit 31 : Connection */
+#define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL) /*!< Connect */
+#define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define RADIO_PSEL_DFEGPIO_PORT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: RADIO_DFEPACKET_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: RADIO_DFEPACKET_MAXCNT */
+/* Description: Maximum number of buffer words to transfer */
+
+/* Bits 13..0 : Maximum number of buffer words to transfer */
+#define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: RADIO_DFEPACKET_AMOUNT */
+/* Description: Number of samples transferred in the last transaction */
+
+/* Bits 15..0 : Number of samples transferred in the last transaction */
+#define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control */
+
+/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator */
+
+/* Register: RNG_TASKS_START */
+/* Description: Task starting the random number generator */
+
+/* Bit 0 : Task starting the random number generator */
+#define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RNG_TASKS_STOP */
+/* Description: Task stopping the random number generator */
+
+/* Bit 0 : Task stopping the random number generator */
+#define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RNG_EVENTS_VALRDY */
+/* Description: Event being generated for every new random number written to the VALUE register */
+
+/* Bit 0 : Event being generated for every new random number written to the VALUE register */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 0 : Shortcut between event VALRDY and task STOP */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RNG_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to enable interrupt for event VALRDY */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
+
+/* Register: RNG_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to disable interrupt for event VALRDY */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 0 : Bias correction */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
+
+/* Register: RNG_VALUE */
+/* Description: Output random number */
+
+/* Bits 7..0 : Generated random number */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0 */
+
+/* Register: RTC_TASKS_START */
+/* Description: Start RTC COUNTER */
+
+/* Bit 0 : Start RTC COUNTER */
+#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_STOP */
+/* Description: Stop RTC COUNTER */
+
+/* Bit 0 : Stop RTC COUNTER */
+#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_CLEAR */
+/* Description: Clear RTC COUNTER */
+
+/* Bit 0 : Clear RTC COUNTER */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_TRIGOVRFLW */
+/* Description: Set COUNTER to 0xFFFFF0 */
+
+/* Bit 0 : Set COUNTER to 0xFFFFF0 */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_EVENTS_TICK */
+/* Description: Event on COUNTER increment */
+
+/* Bit 0 : Event on COUNTER increment */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
+#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_EVENTS_OVRFLW */
+/* Description: Event on COUNTER overflow */
+
+/* Bit 0 : Event on COUNTER overflow */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_EVENTS_COMPARE */
+/* Description: Description collection: Compare event on CC[n] match */
+
+/* Bit 0 : Compare event on CC[n] match */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event TICK */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event TICK */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_EVTEN */
+/* Description: Enable or disable event routing */
+
+/* Bit 19 : Enable or disable event routing for event COMPARE[3] */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */
+
+/* Bit 18 : Enable or disable event routing for event COMPARE[2] */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */
+
+/* Bit 17 : Enable or disable event routing for event COMPARE[1] */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */
+
+/* Bit 16 : Enable or disable event routing for event COMPARE[0] */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */
+
+/* Bit 1 : Enable or disable event routing for event OVRFLW */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */
+
+/* Bit 0 : Enable or disable event routing for event TICK */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable event routing */
+
+/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable event routing for event OVRFLW */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable event routing for event TICK */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable event routing */
+
+/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable event routing for event OVRFLW */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable event routing for event TICK */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value */
+
+/* Bits 23..0 : Counter value */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
+
+/* Bits 11..0 : Prescaler value */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Description collection: Compare register n */
+
+/* Bits 23..0 : Compare value */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+
+/* Peripheral: SAADC */
+/* Description: Successive approximation register (SAR) analog-to-digital converter */
+
+/* Register: SAADC_TASKS_START */
+/* Description: Starts the SAADC and prepares the result buffer in RAM */
+
+/* Bit 0 : Starts the SAADC and prepares the result buffer in RAM */
+#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_SAMPLE */
+/* Description: Takes one SAADC sample */
+
+/* Bit 0 : Takes one SAADC sample */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_STOP */
+/* Description: Stops the SAADC and terminates all on-going conversions */
+
+/* Bit 0 : Stops the SAADC and terminates all on-going conversions */
+#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_CALIBRATEOFFSET */
+/* Description: Starts offset auto-calibration */
+
+/* Bit 0 : Starts offset auto-calibration */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_EVENTS_STARTED */
+/* Description: The SAADC has started */
+
+/* Bit 0 : The SAADC has started */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_END */
+/* Description: The SAADC has filled up the result buffer */
+
+/* Bit 0 : The SAADC has filled up the result buffer */
+#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_DONE */
+/* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */
+
+/* Bit 0 : A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_RESULTDONE */
+/* Description: Result ready for transfer to RAM */
+
+/* Bit 0 : Result ready for transfer to RAM */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CALIBRATEDONE */
+/* Description: Calibration is complete */
+
+/* Bit 0 : Calibration is complete */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_STOPPED */
+/* Description: The SAADC has stopped */
+
+/* Bit 0 : The SAADC has stopped */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CH_LIMITH */
+/* Description: Description cluster: Last result is equal or above CH[n].LIMIT.HIGH */
+
+/* Bit 0 : Last result is equal or above CH[n].LIMIT.HIGH */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CH_LIMITL */
+/* Description: Description cluster: Last result is equal or below CH[n].LIMIT.LOW */
+
+/* Bit 0 : Last result is equal or below CH[n].LIMIT.LOW */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
+#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
+#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
+#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
+#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
+#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
+#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
+#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
+#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
+#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
+#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
+#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
+#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
+#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
+#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
+#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
+#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event STOPPED */
+#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
+#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event RESULTDONE */
+#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event DONE */
+#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event END */
+#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event STARTED */
+#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
+#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
+#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
+#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
+#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
+#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
+#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
+#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
+#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
+#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
+#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
+#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
+#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
+#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
+#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
+#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
+#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event STOPPED */
+#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
+#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
+#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event DONE */
+#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event END */
+#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event STARTED */
+#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
+#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
+#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
+#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
+#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
+#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
+#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
+#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
+#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
+#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
+#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
+#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
+#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
+#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
+#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
+#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
+#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event STOPPED */
+#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
+#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
+#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event DONE */
+#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event END */
+#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event STARTED */
+#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: SAADC_STATUS */
+/* Description: Status */
+
+/* Bit 0 : Status */
+#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define SAADC_STATUS_STATUS_Ready (0UL) /*!< SAADC is ready. No on-going conversions. */
+#define SAADC_STATUS_STATUS_Busy (1UL) /*!< SAADC is busy. Conversion in progress. */
+
+/* Register: SAADC_ENABLE */
+/* Description: Enable or disable SAADC */
+
+/* Bit 0 : Enable or disable SAADC */
+#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SAADC */
+#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */
+
+/* Register: SAADC_CH_PSELP */
+/* Description: Description cluster: Input positive pin selection for CH[n] */
+
+/* Bits 4..0 : Analog positive input channel */
+#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
+#define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */
+
+/* Register: SAADC_CH_PSELN */
+/* Description: Description cluster: Input negative pin selection for CH[n] */
+
+/* Bits 4..0 : Analog negative input, enables differential channel */
+#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
+#define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */
+
+/* Register: SAADC_CH_CONFIG */
+/* Description: Description cluster: Input configuration for CH[n] */
+
+/* Bit 24 : Enable burst mode */
+#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
+#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
+
+/* Bit 20 : Enable differential mode */
+#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
+#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND */
+#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
+
+/* Bits 18..16 : Acquisition time, the time the SAADC uses to sample the input voltage */
+#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
+#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
+#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
+#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
+#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
+#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
+
+/* Bit 12 : Reference control */
+#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
+#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
+
+/* Bits 10..8 : Gain control */
+#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
+#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
+#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
+#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
+
+/* Bits 5..4 : Negative channel resistor control */
+#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Bits 1..0 : Positive channel resistor control */
+#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Register: SAADC_CH_LIMIT */
+/* Description: Description cluster: High/low limits for event monitoring of a channel */
+
+/* Bits 31..16 : High level limit */
+#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
+#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
+
+/* Bits 15..0 : Low level limit */
+#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
+#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
+
+/* Register: SAADC_RESOLUTION */
+/* Description: Resolution configuration */
+
+/* Bits 2..0 : Set the resolution */
+#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
+#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
+#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bits */
+#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bits */
+#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bits */
+#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bits */
+
+/* Register: SAADC_OVERSAMPLE */
+/* Description: Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
+
+/* Bits 3..0 : Oversample control */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
+
+/* Register: SAADC_SAMPLERATE */
+/* Description: Controls normal or continuous sample rate */
+
+/* Bit 12 : Select mode for sample rate control */
+#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
+#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
+
+/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
+#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
+#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
+
+/* Register: SAADC_RESULT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SAADC_RESULT_MAXCNT */
+/* Description: Maximum number of 16-bit samples to be written to output RAM buffer */
+
+/* Bits 14..0 : Maximum number of 16-bit samples to be written to output RAM buffer */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SAADC_RESULT_AMOUNT */
+/* Description: Number of 16-bit samples written to output RAM buffer since the previous START task */
+
+/* Bits 14..0 : Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: SPI */
+/* Description: Serial Peripheral Interface 0 */
+
+/* Register: SPI_EVENTS_READY */
+/* Description: TXD byte sent and RXD byte received */
+
+/* Bit 0 : TXD byte sent and RXD byte received */
+#define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: SPI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to enable interrupt for event READY */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: SPI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to disable interrupt for event READY */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI */
+
+/* Bits 3..0 : Enable or disable SPI */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
+#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
+
+/* Register: SPI_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPI_PSEL_SCK_PORT_Msk (0x1UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPI_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPI_PSEL_MOSI_PORT_Msk (0x1UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPI_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPI_PSEL_MISO_PORT_Msk (0x1UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received. Double buffered */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to send. Double buffered */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+
+/* Peripheral: SPIM */
+/* Description: Serial Peripheral Interface Master with EasyDMA 0 */
+
+/* Register: SPIM_TASKS_START */
+/* Description: Start SPI transaction */
+
+/* Bit 0 : Start SPI transaction */
+#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_STOP */
+/* Description: Stop SPI transaction */
+
+/* Bit 0 : Stop SPI transaction */
+#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_SUSPEND */
+/* Description: Suspend SPI transaction */
+
+/* Bit 0 : Suspend SPI transaction */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_RESUME */
+/* Description: Resume SPI transaction */
+
+/* Bit 0 : Resume SPI transaction */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_EVENTS_STOPPED */
+/* Description: SPI transaction has stopped */
+
+/* Bit 0 : SPI transaction has stopped */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_ENDRX */
+/* Description: End of RXD buffer reached */
+
+/* Bit 0 : End of RXD buffer reached */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_END */
+/* Description: End of RXD buffer and TXD buffer reached */
+
+/* Bit 0 : End of RXD buffer and TXD buffer reached */
+#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_ENDTX */
+/* Description: End of TXD buffer reached */
+
+/* Bit 0 : End of TXD buffer reached */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_STARTED */
+/* Description: Transaction started */
+
+/* Bit 0 : Transaction started */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 17 : Shortcut between event END and task START */
+#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
+#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to enable interrupt for event STARTED */
+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event ENDTX */
+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event END */
+#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: SPIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to disable interrupt for event STARTED */
+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event ENDTX */
+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event END */
+#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: SPIM_STALLSTAT */
+/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */
+
+/* Bit 1 : Stall status for EasyDMA RAM writes */
+#define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */
+#define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */
+#define SPIM_STALLSTAT_RX_NOSTALL (0UL) /*!< No stall */
+#define SPIM_STALLSTAT_RX_STALL (1UL) /*!< A stall has occurred */
+
+/* Bit 0 : Stall status for EasyDMA RAM reads */
+#define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */
+#define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */
+#define SPIM_STALLSTAT_TX_NOSTALL (0UL) /*!< No stall */
+#define SPIM_STALLSTAT_TX_STALL (1UL) /*!< A stall has occurred */
+
+/* Register: SPIM_ENABLE */
+/* Description: Enable SPIM */
+
+/* Bits 3..0 : Enable or disable SPIM */
+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
+#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
+
+/* Register: SPIM_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_CSN */
+/* Description: Pin select for CSN */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_FREQUENCY */
+/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 15..0 : Maximum number of bytes in receive buffer */
+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last transaction */
+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_TXD_MAXCNT */
+/* Description: Number of bytes in transmit buffer */
+
+/* Bits 15..0 : Maximum number of bytes in transmit buffer */
+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last transaction */
+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIM_IFTIMING_RXDELAY */
+/* Description: Sample delay for input serial data on MISO */
+
+/* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */
+#define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */
+#define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
+
+/* Register: SPIM_IFTIMING_CSNDUR */
+/* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions */
+
+/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */
+#define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */
+#define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */
+
+/* Register: SPIM_CSNPOL */
+/* Description: Polarity of CSN output */
+
+/* Bit 0 : Polarity of CSN output */
+#define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */
+#define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */
+#define SPIM_CSNPOL_CSNPOL_LOW (0UL) /*!< Active low (idle state high) */
+#define SPIM_CSNPOL_CSNPOL_HIGH (1UL) /*!< Active high (idle state low) */
+
+/* Register: SPIM_PSELDCX */
+/* Description: Pin select for DCX signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSELDCX_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSELDCX_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_DCXCNT */
+/* Description: DCX configuration */
+
+/* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */
+#define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */
+#define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */
+
+/* Register: SPIM_ORC */
+/* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
+
+/* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */
+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI Slave 0 */
+
+/* Register: SPIS_TASKS_ACQUIRE */
+/* Description: Acquire SPI semaphore */
+
+/* Bit 0 : Acquire SPI semaphore */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIS_TASKS_RELEASE */
+/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
+
+/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIS_EVENTS_END */
+/* Description: Granted transaction completed */
+
+/* Bit 0 : Granted transaction completed */
+#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_EVENTS_ENDRX */
+/* Description: End of RXD buffer reached */
+
+/* Bit 0 : End of RXD buffer reached */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_EVENTS_ACQUIRED */
+/* Description: Semaphore acquired */
+
+/* Bit 0 : Semaphore acquired */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 2 : Shortcut between event END and task ACQUIRE */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event END */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event END */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status register */
+
+/* Bits 1..0 : Semaphore status */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction */
+
+/* Bit 1 : RX buffer overflow detected, and prevented */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 0 : TX buffer over-read detected, and prevented */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPI slave */
+
+/* Bits 3..0 : Enable or disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
+
+/* Register: SPIS_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_CSN */
+/* Description: Pin select for CSN signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_RXD_PTR */
+/* Description: RXD data pointer */
+
+/* Bits 31..0 : RXD data pointer */
+#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 15..0 : Maximum number of bytes in receive buffer */
+#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_RXD_AMOUNT */
+/* Description: Number of bytes received in last granted transaction */
+
+/* Bits 15..0 : Number of bytes received in the last granted transaction */
+#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIS_TXD_PTR */
+/* Description: TXD data pointer */
+
+/* Bits 31..0 : TXD data pointer */
+#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 15..0 : Maximum number of bytes in transmit buffer */
+#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_TXD_AMOUNT */
+/* Description: Number of bytes transmitted in last granted transaction */
+
+/* Bits 15..0 : Number of bytes transmitted in last granted transaction */
+#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. Character clocked out in case of an ignored transaction. */
+
+/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character */
+
+/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor */
+
+/* Register: TEMP_TASKS_START */
+/* Description: Start temperature measurement */
+
+/* Bit 0 : Start temperature measurement */
+#define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TEMP_TASKS_STOP */
+/* Description: Stop temperature measurement */
+
+/* Bit 0 : Stop temperature measurement */
+#define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TEMP_EVENTS_DATARDY */
+/* Description: Temperature measurement complete, data ready */
+
+/* Bit 0 : Temperature measurement complete, data ready */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
+
+/* Register: TEMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to enable interrupt for event DATARDY */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to disable interrupt for event DATARDY */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
+
+/* Register: TEMP_TEMP */
+/* Description: Temperature in degC (0.25deg steps) */
+
+/* Bits 31..0 : Temperature in degC (0.25deg steps) */
+#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
+#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
+
+/* Register: TEMP_A0 */
+/* Description: Slope of 1st piece wise linear function */
+
+/* Bits 11..0 : Slope of 1st piece wise linear function */
+#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
+#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
+
+/* Register: TEMP_A1 */
+/* Description: Slope of 2nd piece wise linear function */
+
+/* Bits 11..0 : Slope of 2nd piece wise linear function */
+#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
+#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
+
+/* Register: TEMP_A2 */
+/* Description: Slope of 3rd piece wise linear function */
+
+/* Bits 11..0 : Slope of 3rd piece wise linear function */
+#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
+#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
+
+/* Register: TEMP_A3 */
+/* Description: Slope of 4th piece wise linear function */
+
+/* Bits 11..0 : Slope of 4th piece wise linear function */
+#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
+#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
+
+/* Register: TEMP_A4 */
+/* Description: Slope of 5th piece wise linear function */
+
+/* Bits 11..0 : Slope of 5th piece wise linear function */
+#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
+#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
+
+/* Register: TEMP_A5 */
+/* Description: Slope of 6th piece wise linear function */
+
+/* Bits 11..0 : Slope of 6th piece wise linear function */
+#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
+#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
+
+/* Register: TEMP_B0 */
+/* Description: y-intercept of 1st piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 1st piece wise linear function */
+#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
+#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
+
+/* Register: TEMP_B1 */
+/* Description: y-intercept of 2nd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 2nd piece wise linear function */
+#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
+#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
+
+/* Register: TEMP_B2 */
+/* Description: y-intercept of 3rd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 3rd piece wise linear function */
+#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
+#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
+
+/* Register: TEMP_B3 */
+/* Description: y-intercept of 4th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 4th piece wise linear function */
+#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
+#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
+
+/* Register: TEMP_B4 */
+/* Description: y-intercept of 5th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 5th piece wise linear function */
+#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
+#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
+
+/* Register: TEMP_B5 */
+/* Description: y-intercept of 6th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 6th piece wise linear function */
+#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
+#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
+
+/* Register: TEMP_T0 */
+/* Description: End point of 1st piece wise linear function */
+
+/* Bits 7..0 : End point of 1st piece wise linear function */
+#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
+#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
+
+/* Register: TEMP_T1 */
+/* Description: End point of 2nd piece wise linear function */
+
+/* Bits 7..0 : End point of 2nd piece wise linear function */
+#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
+#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
+
+/* Register: TEMP_T2 */
+/* Description: End point of 3rd piece wise linear function */
+
+/* Bits 7..0 : End point of 3rd piece wise linear function */
+#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
+#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
+
+/* Register: TEMP_T3 */
+/* Description: End point of 4th piece wise linear function */
+
+/* Bits 7..0 : End point of 4th piece wise linear function */
+#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
+#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
+
+/* Register: TEMP_T4 */
+/* Description: End point of 5th piece wise linear function */
+
+/* Bits 7..0 : End point of 5th piece wise linear function */
+#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
+#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer/Counter 0 */
+
+/* Register: TIMER_TASKS_START */
+/* Description: Start Timer */
+
+/* Bit 0 : Start Timer */
+#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_STOP */
+/* Description: Stop Timer */
+
+/* Bit 0 : Stop Timer */
+#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_COUNT */
+/* Description: Increment Timer (Counter mode only) */
+
+/* Bit 0 : Increment Timer (Counter mode only) */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_CLEAR */
+/* Description: Clear time */
+
+/* Bit 0 : Clear time */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_SHUTDOWN */
+/* Description: Deprecated register - Shut down timer */
+
+/* Bit 0 : Deprecated field - Shut down timer */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_CAPTURE */
+/* Description: Description collection: Capture Timer value to CC[n] register */
+
+/* Bit 0 : Capture Timer value to CC[n] register */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_EVENTS_COMPARE */
+/* Description: Description collection: Compare event on CC[n] match */
+
+/* Bit 0 : Compare event on CC[n] match */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
+#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
+#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TIMER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
+#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
+#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
+#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
+#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Register: TIMER_MODE */
+/* Description: Timer mode selection */
+
+/* Bits 1..0 : Timer mode */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
+#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
+
+/* Register: TIMER_BITMODE */
+/* Description: Configure the number of bits used by the TIMER */
+
+/* Bits 1..0 : Timer bit width */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
+
+/* Register: TIMER_PRESCALER */
+/* Description: Timer prescaler register */
+
+/* Bits 3..0 : Prescaler value */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_CC */
+/* Description: Description collection: Capture/Compare register n */
+
+/* Bits 31..0 : Capture/Compare value */
+#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
+#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
+
+
+/* Peripheral: TWI */
+/* Description: I2C compatible Two-Wire Interface 0 */
+
+/* Register: TWI_TASKS_STARTRX */
+/* Description: Start TWI receive sequence */
+
+/* Bit 0 : Start TWI receive sequence */
+#define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_STARTTX */
+/* Description: Start TWI transmit sequence */
+
+/* Bit 0 : Start TWI transmit sequence */
+#define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_STOP */
+/* Description: Stop TWI transaction */
+
+/* Bit 0 : Stop TWI transaction */
+#define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_RXDREADY */
+/* Description: TWI RXD byte received */
+
+/* Bit 0 : TWI RXD byte received */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_TXDSENT */
+/* Description: TWI TXD byte sent */
+
+/* Bit 0 : TWI TXD byte sent */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_BB */
+/* Description: TWI byte boundary, generated before each byte that is sent or received */
+
+/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */
+#define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */
+#define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */
+#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_SUSPENDED */
+/* Description: TWI entered the suspended state */
+
+/* Bit 0 : TWI entered the suspended state */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 1 : Shortcut between event BB and task STOP */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event BB and task SUSPEND */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event BB */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event BB */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable TWI */
+
+/* Bits 3..0 : Enable or disable TWI */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
+#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
+
+/* Register: TWI_PSEL_SCL */
+/* Description: Pin select for SCL */
+
+/* Bit 31 : Connection */
+#define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define TWI_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWI_PSEL_SCL_PORT_Msk (0x1UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWI_PSEL_SDA */
+/* Description: Pin select for SDA */
+
+/* Bit 31 : Connection */
+#define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define TWI_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWI_PSEL_SDA_PORT_Msk (0x1UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RXD register */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TXD register */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIM */
+/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
+
+/* Register: TWIM_TASKS_STARTRX */
+/* Description: Start TWI receive sequence */
+
+/* Bit 0 : Start TWI receive sequence */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_STARTTX */
+/* Description: Start TWI transmit sequence */
+
+/* Bit 0 : Start TWI transmit sequence */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_STOP */
+/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
+
+/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_SUSPENDED */
+/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
+
+/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_RXSTARTED */
+/* Description: Receive sequence started */
+
+/* Bit 0 : Receive sequence started */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_TXSTARTED */
+/* Description: Transmit sequence started */
+
+/* Bit 0 : Transmit sequence started */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_LASTRX */
+/* Description: Byte boundary, starting to receive the last byte */
+
+/* Bit 0 : Byte boundary, starting to receive the last byte */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_LASTTX */
+/* Description: Byte boundary, starting to transmit the last byte */
+
+/* Bit 0 : Byte boundary, starting to transmit the last byte */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 12 : Shortcut between event LASTRX and task STOP */
+#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */
+#define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */
+#define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */
+#define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between event LASTRX and task STARTTX */
+#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between event LASTTX and task STOP */
+#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 7 : Shortcut between event LASTTX and task STARTRX */
+#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 24 : Enable or disable interrupt for event LASTTX */
+#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for event LASTRX */
+#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
+#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
+#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for event SUSPENDED */
+#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event ERROR */
+#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
+#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 24 : Write '1' to enable interrupt for event LASTTX */
+#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to enable interrupt for event LASTRX */
+#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
+#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
+#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
+#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 24 : Write '1' to disable interrupt for event LASTTX */
+#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to disable interrupt for event LASTRX */
+#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
+#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
+#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
+#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIM_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : Overrun error */
+#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
+
+/* Register: TWIM_ENABLE */
+/* Description: Enable TWIM */
+
+/* Bits 3..0 : Enable or disable TWIM */
+#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
+#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
+
+/* Register: TWIM_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_FREQUENCY */
+/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
+
+/* Register: TWIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 15..0 : Maximum number of bytes in receive buffer */
+#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 15..0 : Maximum number of bytes in transmit buffer */
+#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIS */
+/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
+
+/* Register: TWIS_TASKS_STOP */
+/* Description: Stop TWI transaction */
+
+/* Bit 0 : Stop TWI transaction */
+#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_PREPARERX */
+/* Description: Prepare the TWI slave to respond to a write command */
+
+/* Bit 0 : Prepare the TWI slave to respond to a write command */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_PREPARETX */
+/* Description: Prepare the TWI slave to respond to a read command */
+
+/* Bit 0 : Prepare the TWI slave to respond to a read command */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_RXSTARTED */
+/* Description: Receive sequence started */
+
+/* Bit 0 : Receive sequence started */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_TXSTARTED */
+/* Description: Transmit sequence started */
+
+/* Bit 0 : Transmit sequence started */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_WRITE */
+/* Description: Write command received */
+
+/* Bit 0 : Write command received */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_READ */
+/* Description: Read command received */
+
+/* Bit 0 : Read command received */
+#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
+#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
+#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 14 : Shortcut between event READ and task SUSPEND */
+#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between event WRITE and task SUSPEND */
+#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIS_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 26 : Enable or disable interrupt for event READ */
+#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for event WRITE */
+#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
+#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
+#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event ERROR */
+#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
+#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 26 : Write '1' to enable interrupt for event READ */
+#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to enable interrupt for event WRITE */
+#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
+#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
+#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 26 : Write '1' to disable interrupt for event READ */
+#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to disable interrupt for event WRITE */
+#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
+#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
+#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIS_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : TX buffer over-read detected, and prevented */
+#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
+
+/* Bit 2 : NACK sent after receiving a data byte */
+#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : RX buffer overflow detected, and prevented */
+#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
+
+/* Register: TWIS_MATCH */
+/* Description: Status register indicating which address had a match */
+
+/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
+#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
+#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
+
+/* Register: TWIS_ENABLE */
+/* Description: Enable TWIS */
+
+/* Bits 3..0 : Enable or disable TWIS */
+#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
+#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
+
+/* Register: TWIS_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_RXD_PTR */
+/* Description: RXD Data pointer */
+
+/* Bits 31..0 : RXD Data pointer */
+#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in RXD buffer */
+
+/* Bits 15..0 : Maximum number of bytes in RXD buffer */
+#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last RXD transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last RXD transaction */
+#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIS_TXD_PTR */
+/* Description: TXD Data pointer */
+
+/* Bits 31..0 : TXD Data pointer */
+#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in TXD buffer */
+
+/* Bits 15..0 : Maximum number of bytes in TXD buffer */
+#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last TXD transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last TXD transaction */
+#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIS_ADDRESS */
+/* Description: Description collection: TWI slave address n */
+
+/* Bits 6..0 : TWI slave address */
+#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWIS_CONFIG */
+/* Description: Configuration register for the address match mechanism */
+
+/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
+#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
+#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
+
+/* Register: TWIS_ORC */
+/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+
+/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter */
+
+/* Register: UART_TASKS_STARTRX */
+/* Description: Start UART receiver */
+
+/* Bit 0 : Start UART receiver */
+#define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_STOPRX */
+/* Description: Stop UART receiver */
+
+/* Bit 0 : Stop UART receiver */
+#define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
+#define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
+#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_STARTTX */
+/* Description: Start UART transmitter */
+
+/* Bit 0 : Start UART transmitter */
+#define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_STOPTX */
+/* Description: Stop UART transmitter */
+
+/* Bit 0 : Stop UART transmitter */
+#define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
+#define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
+#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_SUSPEND */
+/* Description: Suspend UART */
+
+/* Bit 0 : Suspend UART */
+#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_EVENTS_CTS */
+/* Description: CTS is activated (set low). Clear To Send. */
+
+/* Bit 0 : CTS is activated (set low). Clear To Send. */
+#define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
+#define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
+#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_NCTS */
+/* Description: CTS is deactivated (set high). Not Clear To Send. */
+
+/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_RXDRDY */
+/* Description: Data received in RXD */
+
+/* Bit 0 : Data received in RXD */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_TXDRDY */
+/* Description: Data sent from TXD */
+
+/* Bit 0 : Data sent from TXD */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_ERROR */
+/* Description: Error detected */
+
+/* Bit 0 : Error detected */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_RXTO */
+/* Description: Receiver timeout */
+
+/* Bit 0 : Receiver timeout */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 4 : Shortcut between event NCTS and task STOPRX */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event CTS and task STARTRX */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UART_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 17 : Write '1' to enable interrupt for event RXTO */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event NCTS */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event CTS */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UART_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 17 : Write '1' to disable interrupt for event RXTO */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event NCTS */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event CTS */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : Break condition */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UART */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
+#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
+
+/* Register: UART_PSEL_RTS */
+/* Description: Pin select for RTS */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_RTS_PORT_Msk (0x1UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_TXD */
+/* Description: Pin select for TXD */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_TXD_PORT_Msk (0x1UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_CTS */
+/* Description: Pin select for CTS */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_CTS_PORT_Msk (0x1UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_RXD */
+/* Description: Pin select for RXD */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_RXD_PORT_Msk (0x1UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received in previous transfers, double buffered */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to be transferred */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
+#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
+#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bit 8 : Even or odd parity type */
+#define UART_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
+#define UART_CONFIG_PARITYTYPE_Msk (0x1UL << UART_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
+#define UART_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */
+#define UART_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */
+
+/* Bit 4 : Stop bits */
+#define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
+#define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
+#define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */
+#define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
+
+/* Bits 3..1 : Parity */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UARTE */
+/* Description: UART with EasyDMA 0 */
+
+/* Register: UARTE_TASKS_STARTRX */
+/* Description: Start UART receiver */
+
+/* Bit 0 : Start UART receiver */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STOPRX */
+/* Description: Stop UART receiver */
+
+/* Bit 0 : Stop UART receiver */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STARTTX */
+/* Description: Start UART transmitter */
+
+/* Bit 0 : Start UART transmitter */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STOPTX */
+/* Description: Stop UART transmitter */
+
+/* Bit 0 : Stop UART transmitter */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_FLUSHRX */
+/* Description: Flush RX FIFO into RX buffer */
+
+/* Bit 0 : Flush RX FIFO into RX buffer */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_EVENTS_CTS */
+/* Description: CTS is activated (set low). Clear To Send. */
+
+/* Bit 0 : CTS is activated (set low). Clear To Send. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_NCTS */
+/* Description: CTS is deactivated (set high). Not Clear To Send. */
+
+/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXDRDY */
+/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
+
+/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ENDRX */
+/* Description: Receive buffer is filled up */
+
+/* Bit 0 : Receive buffer is filled up */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXDRDY */
+/* Description: Data sent from TXD */
+
+/* Bit 0 : Data sent from TXD */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ENDTX */
+/* Description: Last TX byte transmitted */
+
+/* Bit 0 : Last TX byte transmitted */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ERROR */
+/* Description: Error detected */
+
+/* Bit 0 : Error detected */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXTO */
+/* Description: Receiver timeout */
+
+/* Bit 0 : Receiver timeout */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXSTARTED */
+/* Description: UART receiver has started */
+
+/* Bit 0 : UART receiver has started */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXSTARTED */
+/* Description: UART transmitter has started */
+
+/* Bit 0 : UART transmitter has started */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXSTOPPED */
+/* Description: Transmitter stopped */
+
+/* Bit 0 : Transmitter stopped */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 6 : Shortcut between event ENDRX and task STOPRX */
+#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between event ENDRX and task STARTRX */
+#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UARTE_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
+#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
+#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
+#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for event RXTO */
+#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event ERROR */
+#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for event ENDTX */
+#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event TXDRDY */
+#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event ENDRX */
+#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event RXDRDY */
+#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event NCTS */
+#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event CTS */
+#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
+#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
+#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
+#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event RXTO */
+#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event ENDTX */
+#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
+#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
+#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
+#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event NCTS */
+#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event CTS */
+#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
+#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
+#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
+#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event RXTO */
+#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event ENDTX */
+#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
+#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
+#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
+#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event NCTS */
+#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event CTS */
+#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UARTE_ERRORSRC */
+/* Description: Error source Note : this register is read / write one to clear. */
+
+/* Bit 3 : Break condition */
+#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UARTE_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UARTE */
+#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
+#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
+
+/* Register: UARTE_PSEL_RTS */
+/* Description: Pin select for RTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_TXD */
+/* Description: Pin select for TXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_CTS */
+/* Description: Pin select for CTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_RXD */
+/* Description: Pin select for RXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number */
+#define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UARTE_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 15..0 : Maximum number of bytes in receive buffer */
+#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last transaction */
+#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 15..0 : Maximum number of bytes in transmit buffer */
+#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last transaction */
+#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bit 8 : Even or odd parity type */
+#define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
+#define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
+#define UARTE_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */
+#define UARTE_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */
+
+/* Bit 4 : Stop bits */
+#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
+#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
+#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
+#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
+
+/* Bits 3..1 : Parity */
+#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UICR */
+/* Description: User information configuration registers */
+
+/* Register: UICR_NRFFW */
+/* Description: Description collection: Reserved for Nordic firmware design */
+
+/* Bits 31..0 : Reserved for Nordic firmware design */
+#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
+#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
+
+/* Register: UICR_NRFHW */
+/* Description: Description collection: Reserved for Nordic hardware design */
+
+/* Bits 31..0 : Reserved for Nordic hardware design */
+#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
+#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
+
+/* Register: UICR_CUSTOMER */
+/* Description: Description collection: Reserved for customer */
+
+/* Bits 31..0 : Reserved for customer */
+#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
+#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
+
+/* Register: UICR_PSELRESET */
+/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */
+
+/* Bit 31 : Connection */
+#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
+#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bit 5 : Port number onto which nRESET is exposed */
+#define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UICR_PSELRESET_PORT_Msk (0x1UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : GPIO pin number onto which nRESET is exposed */
+#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UICR_APPROTECT */
+/* Description: Access port protection */
+
+/* Bits 7..0 : Enable or disable access port protection. */
+#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
+#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
+#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
+
+/* Register: UICR_NFCPINS */
+/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
+
+/* Bit 0 : Setting of pins dedicated to NFC functionality */
+#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
+#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
+
+/* Register: UICR_DEBUGCTRL */
+/* Description: Processor debug control */
+
+/* Bits 15..8 : Configure CPU flash patch and breakpoint (FPB) unit behavior */
+#define UICR_DEBUGCTRL_CPUFPBEN_Pos (8UL) /*!< Position of CPUFPBEN field. */
+#define UICR_DEBUGCTRL_CPUFPBEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUFPBEN_Pos) /*!< Bit mask of CPUFPBEN field. */
+#define UICR_DEBUGCTRL_CPUFPBEN_Disabled (0x00UL) /*!< Disable CPU FPB unit. Writes into the FPB registers will be ignored. */
+#define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */
+
+/* Bits 7..0 : Configure CPU non-intrusive debug features */
+#define UICR_DEBUGCTRL_CPUNIDEN_Pos (0UL) /*!< Position of CPUNIDEN field. */
+#define UICR_DEBUGCTRL_CPUNIDEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUNIDEN_Pos) /*!< Bit mask of CPUNIDEN field. */
+#define UICR_DEBUGCTRL_CPUNIDEN_Disabled (0x00UL) /*!< Disable CPU ITM and ETM functionality */
+#define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */
+
+/* Register: UICR_REGOUT0 */
+/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. */
+
+/* Bits 2..0 : Output voltage from REG0 regulator stage. */
+#define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */
+#define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */
+#define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */
+#define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */
+#define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */
+#define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */
+#define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */
+#define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */
+#define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */
+
+
+/* Peripheral: USBD */
+/* Description: Universal serial bus device */
+
+/* Register: USBD_TASKS_STARTEPIN */
+/* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
+
+/* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
+#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */
+#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */
+#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: USBD_TASKS_STARTISOIN */
+/* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
+
+/* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
+#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */
+#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */
+#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: USBD_TASKS_STARTEPOUT */
+/* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
+
+/* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
+#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */
+#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */
+#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: USBD_TASKS_STARTISOOUT */
+/* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
+
+/* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
+#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */
+#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */
+#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: USBD_TASKS_EP0RCVOUT */
+/* Description: Allows OUT data stage on control endpoint 0 */
+
+/* Bit 0 : Allows OUT data stage on control endpoint 0 */
+#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */
+#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */
+#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: USBD_TASKS_EP0STATUS */
+/* Description: Allows status stage on control endpoint 0 */
+
+/* Bit 0 : Allows status stage on control endpoint 0 */
+#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */
+#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */
+#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */
+
+/* Register: USBD_TASKS_EP0STALL */
+/* Description: Stalls data and status stage on control endpoint 0 */
+
+/* Bit 0 : Stalls data and status stage on control endpoint 0 */
+#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */
+#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */
+#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */
+
+/* Register: USBD_TASKS_DPDMDRIVE */
+/* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */
+
+/* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */
+#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */
+#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */
+#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: USBD_TASKS_DPDMNODRIVE */
+/* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */
+
+/* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */
+#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */
+#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */
+#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: USBD_EVENTS_USBRESET */
+/* Description: Signals that a USB reset condition has been detected on USB lines */
+
+/* Bit 0 : Signals that a USB reset condition has been detected on USB lines */
+#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */
+#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */
+#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_EVENTS_STARTED */
+/* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
+
+/* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
+#define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_EVENTS_ENDEPIN */
+/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
+
+/* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
+#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */
+#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */
+#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_EVENTS_EP0DATADONE */
+/* Description: An acknowledged data transfer has taken place on the control endpoint */
+
+/* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */
+#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */
+#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */
+#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_EVENTS_ENDISOIN */
+/* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
+
+/* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
+#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */
+#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */
+#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_EVENTS_ENDEPOUT */
+/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
+
+/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
+#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */
+#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */
+#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_EVENTS_ENDISOOUT */
+/* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
+
+/* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
+#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */
+#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */
+#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_EVENTS_SOF */
+/* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */
+
+/* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */
+#define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */
+#define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */
+#define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_EVENTS_USBEVENT */
+/* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
+
+/* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
+#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */
+#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */
+#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_EVENTS_EP0SETUP */
+/* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */
+
+/* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */
+#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */
+#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */
+#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_EVENTS_EPDATA */
+/* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
+
+/* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
+#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */
+#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */
+#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */
+#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */
+
+/* Register: USBD_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: USBD_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 24 : Enable or disable interrupt for event EPDATA */
+#define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
+#define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
+#define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for event EP0SETUP */
+#define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
+#define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
+#define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */
+
+/* Bit 22 : Enable or disable interrupt for event USBEVENT */
+#define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
+#define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
+#define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */
+
+/* Bit 21 : Enable or disable interrupt for event SOF */
+#define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */
+#define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */
+#define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event ENDISOOUT */
+#define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
+#define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
+#define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */
+#define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
+#define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
+#define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */
+#define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
+#define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
+#define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */
+#define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
+#define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
+#define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */
+#define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
+#define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
+#define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */
+#define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
+#define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
+#define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */
+#define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
+#define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
+#define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */
+#define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
+#define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
+#define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */
+#define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
+#define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
+#define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for event ENDISOIN */
+#define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
+#define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
+#define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for event EP0DATADONE */
+#define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
+#define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
+#define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */
+#define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
+#define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
+#define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */
+#define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
+#define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
+#define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */
+#define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
+#define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
+#define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */
+#define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
+#define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
+#define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */
+#define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
+#define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
+#define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */
+#define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
+#define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
+#define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */
+#define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
+#define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
+#define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */
+#define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
+#define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
+#define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STARTED */
+#define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */
+#define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event USBRESET */
+#define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
+#define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
+#define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */
+
+/* Register: USBD_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 24 : Write '1' to enable interrupt for event EPDATA */
+#define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
+#define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
+#define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */
+#define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
+#define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
+#define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */
+
+/* Bit 22 : Write '1' to enable interrupt for event USBEVENT */
+#define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
+#define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
+#define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */
+
+/* Bit 21 : Write '1' to enable interrupt for event SOF */
+#define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */
+#define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */
+#define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */
+#define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
+#define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
+#define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */
+#define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
+#define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
+#define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */
+#define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
+#define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
+#define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */
+#define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
+#define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
+#define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */
+#define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
+#define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
+#define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */
+#define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
+#define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
+#define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */
+#define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
+#define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
+#define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */
+#define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
+#define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
+#define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */
+#define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
+#define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
+#define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */
+#define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
+#define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
+#define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */
+#define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
+#define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
+#define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */
+#define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
+#define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
+#define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */
+#define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
+#define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
+#define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */
+#define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
+#define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
+#define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */
+#define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
+#define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
+#define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */
+#define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
+#define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
+#define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */
+#define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
+#define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
+#define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */
+#define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
+#define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
+#define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */
+#define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
+#define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
+#define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STARTED */
+#define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */
+#define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event USBRESET */
+#define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
+#define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
+#define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */
+
+/* Register: USBD_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 24 : Write '1' to disable interrupt for event EPDATA */
+#define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
+#define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
+#define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */
+#define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
+#define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
+#define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */
+
+/* Bit 22 : Write '1' to disable interrupt for event USBEVENT */
+#define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
+#define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
+#define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */
+
+/* Bit 21 : Write '1' to disable interrupt for event SOF */
+#define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */
+#define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */
+#define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */
+#define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
+#define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
+#define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */
+#define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
+#define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
+#define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */
+#define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
+#define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
+#define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */
+#define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
+#define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
+#define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */
+#define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
+#define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
+#define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */
+#define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
+#define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
+#define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */
+#define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
+#define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
+#define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */
+#define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
+#define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
+#define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */
+#define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
+#define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
+#define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */
+#define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
+#define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
+#define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */
+#define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
+#define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
+#define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */
+#define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
+#define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
+#define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */
+#define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
+#define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
+#define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */
+#define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
+#define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
+#define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */
+#define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
+#define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
+#define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */
+#define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
+#define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
+#define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */
+#define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
+#define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
+#define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */
+#define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
+#define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
+#define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */
+#define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
+#define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
+#define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STARTED */
+#define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */
+#define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event USBRESET */
+#define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
+#define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
+#define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */
+
+/* Register: USBD_EVENTCAUSE */
+/* Description: Details on what caused the USBEVENT event */
+
+/* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */
+#define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */
+#define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */
+#define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */
+#define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */
+
+/* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */
+#define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */
+#define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */
+#define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */
+#define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */
+
+/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */
+#define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */
+#define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */
+#define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */
+#define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */
+
+/* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */
+#define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */
+#define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */
+#define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */
+#define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */
+
+/* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */
+#define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */
+#define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */
+#define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */
+#define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */
+
+/* Register: USBD_HALTED_EPIN */
+/* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+
+/* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+#define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
+#define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
+#define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
+#define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
+
+/* Register: USBD_HALTED_EPOUT */
+/* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+
+/* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+#define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
+#define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
+#define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
+#define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
+
+/* Register: USBD_EPSTATUS */
+/* Description: Provides information on which endpoint's EasyDMA registers have been captured */
+
+/* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */
+#define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */
+#define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
+#define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
+#define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
+#define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
+#define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
+#define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
+#define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
+#define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
+#define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
+#define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
+#define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
+#define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
+#define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
+#define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
+#define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */
+#define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */
+#define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */
+#define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */
+#define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
+#define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
+#define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
+#define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
+#define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
+#define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
+#define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
+#define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
+#define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
+#define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
+#define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
+#define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
+#define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
+#define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
+#define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */
+#define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */
+#define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Register: USBD_EPDATASTATUS */
+/* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */
+
+/* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
+#define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
+#define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
+#define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
+#define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
+#define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
+#define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
+#define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
+#define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
+#define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
+#define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
+#define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
+#define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
+#define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
+#define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
+#define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
+#define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
+#define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
+#define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
+#define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
+#define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
+#define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
+#define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
+#define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
+#define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
+#define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
+#define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
+#define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
+#define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Register: USBD_USBADDR */
+/* Description: Device USB address */
+
+/* Bits 6..0 : Device USB address */
+#define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
+#define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
+
+/* Register: USBD_BMREQUESTTYPE */
+/* Description: SETUP data, byte 0, bmRequestType */
+
+/* Bit 7 : Data transfer direction */
+#define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */
+#define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */
+#define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */
+#define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */
+
+/* Bits 6..5 : Data transfer type */
+#define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */
+#define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */
+#define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */
+#define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */
+#define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */
+
+/* Bits 4..0 : Data transfer type */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */
+
+/* Register: USBD_BREQUEST */
+/* Description: SETUP data, byte 1, bRequest */
+
+/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */
+#define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */
+#define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */
+#define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */
+#define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */
+#define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */
+#define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */
+#define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */
+#define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */
+#define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */
+#define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */
+#define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */
+#define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */
+#define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */
+
+/* Register: USBD_WVALUEL */
+/* Description: SETUP data, byte 2, LSB of wValue */
+
+/* Bits 7..0 : SETUP data, byte 2, LSB of wValue */
+#define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */
+#define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */
+
+/* Register: USBD_WVALUEH */
+/* Description: SETUP data, byte 3, MSB of wValue */
+
+/* Bits 7..0 : SETUP data, byte 3, MSB of wValue */
+#define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */
+#define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */
+
+/* Register: USBD_WINDEXL */
+/* Description: SETUP data, byte 4, LSB of wIndex */
+
+/* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */
+#define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */
+#define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */
+
+/* Register: USBD_WINDEXH */
+/* Description: SETUP data, byte 5, MSB of wIndex */
+
+/* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */
+#define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */
+#define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */
+
+/* Register: USBD_WLENGTHL */
+/* Description: SETUP data, byte 6, LSB of wLength */
+
+/* Bits 7..0 : SETUP data, byte 6, LSB of wLength */
+#define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */
+#define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */
+
+/* Register: USBD_WLENGTHH */
+/* Description: SETUP data, byte 7, MSB of wLength */
+
+/* Bits 7..0 : SETUP data, byte 7, MSB of wLength */
+#define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */
+#define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */
+
+/* Register: USBD_SIZE_EPOUT */
+/* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */
+
+/* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */
+#define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
+
+/* Register: USBD_SIZE_ISOOUT */
+/* Description: Number of bytes received last on this ISO OUT data endpoint */
+
+/* Bit 16 : Zero-length data packet received */
+#define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */
+#define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */
+#define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */
+#define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */
+
+/* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */
+#define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
+
+/* Register: USBD_ENABLE */
+/* Description: Enable USB */
+
+/* Bit 0 : Enable USB */
+#define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */
+#define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */
+
+/* Register: USBD_USBPULLUP */
+/* Description: Control of the USB pull-up */
+
+/* Bit 0 : Control of the USB pull-up on the D+ line */
+#define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */
+#define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */
+#define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */
+
+/* Register: USBD_DPDMVALUE */
+/* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */
+
+/* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */
+#define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */
+#define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
+#define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */
+
+/* Register: USBD_DTOGGLE */
+/* Description: Data toggle control and status */
+
+/* Bits 9..8 : Data toggle value */
+#define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */
+#define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+#define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */
+#define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */
+#define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */
+
+/* Bit 7 : Selects IN or OUT endpoint */
+#define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */
+#define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */
+#define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */
+#define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */
+
+/* Bits 2..0 : Select bulk endpoint number */
+#define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */
+#define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */
+
+/* Register: USBD_EPINEN */
+/* Description: Endpoint IN enable */
+
+/* Bit 8 : Enable ISO IN endpoint */
+#define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */
+#define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */
+#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */
+#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */
+
+/* Bit 7 : Enable IN endpoint 7 */
+#define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */
+#define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */
+
+/* Bit 6 : Enable IN endpoint 6 */
+#define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
+#define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */
+
+/* Bit 5 : Enable IN endpoint 5 */
+#define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
+#define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */
+
+/* Bit 4 : Enable IN endpoint 4 */
+#define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
+#define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */
+
+/* Bit 3 : Enable IN endpoint 3 */
+#define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
+#define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */
+
+/* Bit 2 : Enable IN endpoint 2 */
+#define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
+#define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
+
+/* Bit 1 : Enable IN endpoint 1 */
+#define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
+#define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */
+
+/* Bit 0 : Enable IN endpoint 0 */
+#define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
+#define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */
+
+/* Register: USBD_EPOUTEN */
+/* Description: Endpoint OUT enable */
+
+/* Bit 8 : Enable ISO OUT endpoint 8 */
+#define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */
+#define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */
+#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */
+#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */
+
+/* Bit 7 : Enable OUT endpoint 7 */
+#define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */
+#define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */
+#define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */
+
+/* Bit 6 : Enable OUT endpoint 6 */
+#define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */
+#define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */
+#define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */
+
+/* Bit 5 : Enable OUT endpoint 5 */
+#define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */
+#define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */
+#define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */
+
+/* Bit 4 : Enable OUT endpoint 4 */
+#define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */
+#define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */
+#define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */
+
+/* Bit 3 : Enable OUT endpoint 3 */
+#define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */
+#define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */
+#define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */
+
+/* Bit 2 : Enable OUT endpoint 2 */
+#define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
+#define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */
+#define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
+
+/* Bit 1 : Enable OUT endpoint 1 */
+#define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */
+#define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */
+#define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */
+
+/* Bit 0 : Enable OUT endpoint 0 */
+#define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */
+#define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */
+#define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */
+
+/* Register: USBD_EPSTALL */
+/* Description: STALL endpoints */
+
+/* Bit 8 : Stall selected endpoint */
+#define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */
+#define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */
+#define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */
+#define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */
+
+/* Bit 7 : Selects IN or OUT endpoint */
+#define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */
+#define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */
+#define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */
+#define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */
+
+/* Bits 2..0 : Select endpoint number */
+#define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */
+#define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */
+
+/* Register: USBD_ISOSPLIT */
+/* Description: Controls the split of ISO buffers */
+
+/* Bits 15..0 : Controls the split of ISO buffers */
+#define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */
+#define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */
+#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */
+#define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */
+
+/* Register: USBD_FRAMECNTR */
+/* Description: Returns the current value of the start of frame counter */
+
+/* Bits 10..0 : Returns the current value of the start of frame counter */
+#define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */
+#define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */
+
+/* Register: USBD_LOWPOWER */
+/* Description: Controls USBD peripheral low power mode during USB suspend */
+
+/* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */
+#define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */
+#define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */
+#define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL) /*!< Software must write this value to exit low power mode and before performing a remote wake-up */
+#define USBD_LOWPOWER_LOWPOWER_LowPower (1UL) /*!< Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral */
+
+/* Register: USBD_ISOINCONFIG */
+/* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
+
+/* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
+#define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */
+#define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */
+#define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */
+#define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */
+
+/* Register: USBD_EPIN_PTR */
+/* Description: Description cluster: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_EPIN_MAXCNT */
+/* Description: Description cluster: Maximum number of bytes to transfer */
+
+/* Bits 6..0 : Maximum number of bytes to transfer */
+#define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_EPIN_AMOUNT */
+/* Description: Description cluster: Number of bytes transferred in the last transaction */
+
+/* Bits 6..0 : Number of bytes transferred in the last transaction */
+#define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: USBD_ISOIN_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_ISOIN_MAXCNT */
+/* Description: Maximum number of bytes to transfer */
+
+/* Bits 9..0 : Maximum number of bytes to transfer */
+#define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_ISOIN_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: USBD_EPOUT_PTR */
+/* Description: Description cluster: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_EPOUT_MAXCNT */
+/* Description: Description cluster: Maximum number of bytes to transfer */
+
+/* Bits 6..0 : Maximum number of bytes to transfer */
+#define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_EPOUT_AMOUNT */
+/* Description: Description cluster: Number of bytes transferred in the last transaction */
+
+/* Bits 6..0 : Number of bytes transferred in the last transaction */
+#define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: USBD_ISOOUT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_ISOOUT_MAXCNT */
+/* Description: Maximum number of bytes to transfer */
+
+/* Bits 9..0 : Maximum number of bytes to transfer */
+#define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_ISOOUT_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer */
+
+/* Register: WDT_TASKS_START */
+/* Description: Start the watchdog */
+
+/* Bit 0 : Start the watchdog */
+#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: WDT_EVENTS_TIMEOUT */
+/* Description: Watchdog timeout */
+
+/* Bit 0 : Watchdog timeout */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
+
+/* Register: WDT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
+
+/* Register: WDT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Run status */
+
+/* Bit 0 : Indicates whether or not the watchdog is running */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status */
+
+/* Bit 7 : Request status for RR[7] register */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
+
+/* Bit 6 : Request status for RR[6] register */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
+
+/* Bit 5 : Request status for RR[5] register */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
+
+/* Bit 4 : Request status for RR[4] register */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
+
+/* Bit 3 : Request status for RR[3] register */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
+
+/* Bit 2 : Request status for RR[2] register */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
+
+/* Bit 1 : Request status for RR[1] register */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
+
+/* Bit 0 : Request status for RR[0] register */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
+
+/* Register: WDT_CRV */
+/* Description: Counter reload value */
+
+/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
+#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
+#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
+
+/* Register: WDT_RREN */
+/* Description: Enable register for reload request registers */
+
+/* Bit 7 : Enable or disable RR[7] register */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
+
+/* Bit 6 : Enable or disable RR[6] register */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
+
+/* Bit 5 : Enable or disable RR[5] register */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
+
+/* Bit 4 : Enable or disable RR[4] register */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
+
+/* Bit 3 : Enable or disable RR[3] register */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
+
+/* Bit 2 : Enable or disable RR[2] register */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
+
+/* Bit 1 : Enable or disable RR[1] register */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
+
+/* Bit 0 : Enable or disable RR[0] register */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
+
+/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
+
+/* Register: WDT_RR */
+/* Description: Description collection: Reload request n */
+
+/* Bits 31..0 : Reload request register */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
+
+
+/*lint --flb "Leave library region" */
+#endif
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52833_peripherals.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52833_peripherals.h
new file mode 100644
index 000000000..8b35b8129
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52833_peripherals.h
@@ -0,0 +1,301 @@
+/*
+
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _NRF52833_PERIPHERALS_H
+#define _NRF52833_PERIPHERALS_H
+
+/* Clock Peripheral */
+#define CLOCK_PRESENT
+#define CLOCK_COUNT 1
+
+#define CLOCK_FEATURE_LFXO_EXTENDED_DEBOUNCE_PRESENT
+
+/* Power Peripheral */
+#define POWER_PRESENT
+#define POWER_COUNT 1
+
+#define POWER_FEATURE_RAM_REGISTERS_PRESENT
+#define POWER_FEATURE_RAM_REGISTERS_COUNT 9
+
+#define POWER_FEATURE_VDDH_PRESENT
+
+/* Floating Point Unit */
+#define FPU_PRESENT
+#define FPU_COUNT 1
+
+/* Systick timer */
+#define SYSTICK_PRESENT
+#define SYSTICK_COUNT 1
+
+/* Software Interrupts */
+#define SWI_PRESENT
+#define SWI_COUNT 6
+
+/* Memory Watch Unit */
+#define MWU_PRESENT
+#define MWU_COUNT 1
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 2
+
+#define P0_PIN_NUM 32
+#define P1_PIN_NUM 10
+
+/* ACL */
+#define ACL_PRESENT
+
+#define ACL_REGIONS_COUNT 8
+
+/* Radio */
+#define RADIO_PRESENT
+#define RADIO_COUNT 1
+
+#define RADIO_EASYDMA_MAXCNT_SIZE 8
+
+/* Accelerated Address Resolver */
+#define AAR_PRESENT
+#define AAR_COUNT 1
+
+#define AAR_MAX_IRK_NUM 16
+
+/* AES Electronic CodeBook mode encryption */
+#define ECB_PRESENT
+#define ECB_COUNT 1
+
+/* AES CCM mode encryption */
+#define CCM_PRESENT
+#define CCM_COUNT 1
+
+/* NFC Tag */
+#define NFCT_PRESENT
+#define NFCT_COUNT 1
+
+#define NFCT_EASYDMA_MAXCNT_SIZE 9
+
+/* Peripheral to Peripheral Interconnect */
+#define PPI_PRESENT
+#define PPI_COUNT 1
+
+#define PPI_CH_NUM 20
+#define PPI_FIXED_CH_NUM 12
+#define PPI_GROUP_NUM 6
+#define PPI_FEATURE_FORKS_PRESENT
+
+/* Event Generator Unit */
+#define EGU_PRESENT
+#define EGU_COUNT 6
+
+#define EGU0_CH_NUM 16
+#define EGU1_CH_NUM 16
+#define EGU2_CH_NUM 16
+#define EGU3_CH_NUM 16
+#define EGU4_CH_NUM 16
+#define EGU5_CH_NUM 16
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 5
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 32
+#define TIMER2_MAX_SIZE 32
+#define TIMER3_MAX_SIZE 32
+#define TIMER4_MAX_SIZE 32
+
+#define TIMER0_CC_NUM 4
+#define TIMER1_CC_NUM 4
+#define TIMER2_CC_NUM 4
+#define TIMER3_CC_NUM 6
+#define TIMER4_CC_NUM 6
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 3
+
+#define RTC0_CC_NUM 3
+#define RTC1_CC_NUM 4
+#define RTC2_CC_NUM 4
+
+/* RNG */
+#define RNG_PRESENT
+#define RNG_COUNT 1
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 1
+
+/* Temperature Sensor */
+#define TEMP_PRESENT
+#define TEMP_COUNT 1
+
+/* Serial Peripheral Interface Master */
+#define SPI_PRESENT
+#define SPI_COUNT 3
+
+/* Serial Peripheral Interface Master with DMA */
+#define SPIM_PRESENT
+#define SPIM_COUNT 4
+
+#define SPIM0_MAX_DATARATE 8
+#define SPIM1_MAX_DATARATE 8
+#define SPIM2_MAX_DATARATE 8
+#define SPIM3_MAX_DATARATE 32
+
+#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
+#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
+#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
+#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1
+
+#define SPIM0_FEATURE_DCX_PRESENT 0
+#define SPIM1_FEATURE_DCX_PRESENT 0
+#define SPIM2_FEATURE_DCX_PRESENT 0
+#define SPIM3_FEATURE_DCX_PRESENT 1
+
+#define SPIM0_FEATURE_RXDELAY_PRESENT 0
+#define SPIM1_FEATURE_RXDELAY_PRESENT 0
+#define SPIM2_FEATURE_RXDELAY_PRESENT 0
+#define SPIM3_FEATURE_RXDELAY_PRESENT 1
+
+#define SPIM0_EASYDMA_MAXCNT_SIZE 16
+#define SPIM1_EASYDMA_MAXCNT_SIZE 16
+#define SPIM2_EASYDMA_MAXCNT_SIZE 16
+#define SPIM3_EASYDMA_MAXCNT_SIZE 16
+
+/* Serial Peripheral Interface Slave with DMA*/
+#define SPIS_PRESENT
+#define SPIS_COUNT 3
+
+#define SPIS0_EASYDMA_MAXCNT_SIZE 16
+#define SPIS1_EASYDMA_MAXCNT_SIZE 16
+#define SPIS2_EASYDMA_MAXCNT_SIZE 16
+
+/* Two Wire Interface Master */
+#define TWI_PRESENT
+#define TWI_COUNT 2
+
+/* Two Wire Interface Master with DMA */
+#define TWIM_PRESENT
+#define TWIM_COUNT 2
+
+#define TWIM0_EASYDMA_MAXCNT_SIZE 16
+#define TWIM1_EASYDMA_MAXCNT_SIZE 16
+
+/* Two Wire Interface Slave with DMA */
+#define TWIS_PRESENT
+#define TWIS_COUNT 2
+
+#define TWIS0_EASYDMA_MAXCNT_SIZE 16
+#define TWIS1_EASYDMA_MAXCNT_SIZE 16
+
+/* Universal Asynchronous Receiver-Transmitter */
+#define UART_PRESENT
+#define UART_COUNT 1
+
+#define UART0_FEATURE_ODD_PARITY_PRESENT
+
+/* Universal Asynchronous Receiver-Transmitter with DMA */
+#define UARTE_PRESENT
+#define UARTE_COUNT 2
+
+#define UARTE0_EASYDMA_MAXCNT_SIZE 16
+#define UARTE1_EASYDMA_MAXCNT_SIZE 16
+
+#define UARTE0_FEATURE_ODD_PARITY_PRESENT
+#define UARTE1_FEATURE_ODD_PARITY_PRESENT
+
+/* Quadrature Decoder */
+#define QDEC_PRESENT
+#define QDEC_COUNT 1
+
+/* Successive Approximation Analog to Digital Converter */
+#define SAADC_PRESENT
+#define SAADC_COUNT 1
+
+#define SAADC_EASYDMA_MAXCNT_SIZE 15
+
+#define SAADC_CH_NUM 8
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 1
+
+#define GPIOTE_CH_NUM 8
+
+#define GPIOTE_FEATURE_SET_PRESENT
+#define GPIOTE_FEATURE_CLR_PRESENT
+
+/* Low Power Comparator */
+#define LPCOMP_PRESENT
+#define LPCOMP_COUNT 1
+
+#define LPCOMP_REFSEL_RESOLUTION 16
+
+#define LPCOMP_FEATURE_HYST_PRESENT
+
+/* Comparator */
+#define COMP_PRESENT
+#define COMP_COUNT 1
+
+/* Pulse Width Modulator */
+#define PWM_PRESENT
+#define PWM_COUNT 4
+
+#define PWM0_CH_NUM 4
+#define PWM1_CH_NUM 4
+#define PWM2_CH_NUM 4
+#define PWM3_CH_NUM 4
+
+#define PWM0_EASYDMA_MAXCNT_SIZE 15
+#define PWM1_EASYDMA_MAXCNT_SIZE 15
+#define PWM2_EASYDMA_MAXCNT_SIZE 15
+#define PWM3_EASYDMA_MAXCNT_SIZE 15
+
+/* Pulse Density Modulator */
+#define PDM_PRESENT
+#define PDM_COUNT 1
+
+#define PDM_EASYDMA_MAXCNT_SIZE 15
+
+/* Inter-IC Sound Interface */
+#define I2S_PRESENT
+#define I2S_COUNT 1
+
+#define I2S_EASYDMA_MAXCNT_SIZE 14
+
+/* Universal Serial Bus Device */
+#define USBD_PRESENT
+#define USBD_COUNT 1
+
+#define USBD_EASYDMA_MAXCNT_SIZE 7
+
+#endif // _NRF52833_PERIPHERALS_H
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52833_xxaa.ld b/third_party/NordicSemiconductor/nrfx/mdk/nrf52833_xxaa.ld
new file mode 100644
index 000000000..2492b8132
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52833_xxaa.ld
@@ -0,0 +1,13 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000
+}
+
+
+INCLUDE "nrf_common.ld"
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.h
index 0fefdd405..2c0abbf02 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.h
@@ -30,10 +30,10 @@
* @file nrf52840.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 17. January 2019
- * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:40
+ * @date 23. August 2019
+ * @note Generated by SVDConv V3.3.25 on Friday, 23.08.2019 12:15:13
* from File 'nrf52840.svd',
- * last modified on Thursday, 17.01.2019 16:25:35
+ * last modified on Friday, 23.08.2019 10:15:09
*/
@@ -138,8 +138,8 @@ typedef enum {
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __MPU_PRESENT 1 /*!< MPU present */
+#define __FPU_PRESENT 1 /*!< FPU present */
/** @} */ /* End of group Configuration_of_CMSIS */
@@ -235,16 +235,16 @@ typedef struct {
typedef struct {
__IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read
these values to populate NFCID1_3RD_LAST,
- NFCID1_2ND_LAST and NFCID1_LAST. */
+ NFCID1_2ND_LAST, and NFCID1_LAST. */
__IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read
these values to populate NFCID1_3RD_LAST,
- NFCID1_2ND_LAST and NFCID1_LAST. */
+ NFCID1_2ND_LAST, and NFCID1_LAST. */
__IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read
these values to populate NFCID1_3RD_LAST,
- NFCID1_2ND_LAST and NFCID1_LAST. */
+ NFCID1_2ND_LAST, and NFCID1_LAST. */
__IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read
these values to populate NFCID1_3RD_LAST,
- NFCID1_2ND_LAST and NFCID1_LAST. */
+ NFCID1_2ND_LAST, and NFCID1_LAST. */
} FICR_NFC_Type; /*!< Size = 16 (0x10) */
@@ -924,21 +924,23 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu
typedef struct { /*!< (@ 0x10001000) UICR Structure */
__IM uint32_t RESERVED[5];
- __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware
+ __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware
design */
+ __IM uint32_t RESERVED1[2];
__IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware
design */
__IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */
- __IM uint32_t RESERVED1[64];
+ __IM uint32_t RESERVED2[64];
__IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET
function (see POWER chapter for details) */
__IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */
__IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality:
NFC antenna or GPIO */
__IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */
- __IM uint32_t RESERVED2[60];
- __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply
- voltage in high voltage mode */
+ __IM uint32_t RESERVED3[60];
+ __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The
+ maximum output voltage from this stage is
+ given as VDDH - VREG0DROP. */
} NRF_UICR_Type; /*!< Size = 776 (0x308) */
@@ -1010,8 +1012,8 @@ typedef struct { /*!< (@ 0x40000000) CLOCK Struct
typedef struct { /*!< (@ 0x40000000) POWER Structure */
__IM uint32_t RESERVED[30];
- __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */
- __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */
+ __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */
+ __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */
__IM uint32_t RESERVED1[34];
__IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */
__IM uint32_t RESERVED2[2];
@@ -1037,9 +1039,9 @@ typedef struct { /*!< (@ 0x40000000) POWER Struct
__IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */
__IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */
__IM uint32_t RESERVED10[21];
- __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage. */
+ __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */
__IM uint32_t RESERVED11;
- __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage. */
+ __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage */
__IM uint32_t RESERVED12[47];
__IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */
__IM uint32_t RESERVED13[175];
@@ -2540,17 +2542,17 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu
have been captured on all endpoints reported
in the EPSTATUS register */
__IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer
- has been consumed. The RAM buffer can be
- accessed safely by software. */
+ has been consumed. The buffer can be accessed
+ safely by software. */
__IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place
on the control endpoint */
__IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The
- RAM buffer can be accessed safely by software. */
+ buffer can be accessed safely by software. */
__IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer
- has been consumed. The RAM buffer can be
- accessed safely by software. */
+ has been consumed. The buffer can be accessed
+ safely by software. */
__IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The
- RAM buffer can be accessed safely by software. */
+ buffer can be accessed safely by software. */
__IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition
has been detected on USB lines */
__IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific
@@ -2901,7 +2903,7 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
-#elif (__ARMCC_VERSION >= 6010050)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.svd b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.svd
index 74bc36206..ccacbbc06 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.svd
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840.svd
@@ -214,6 +214,11 @@ POSSIBILITY OF SUCH DAMAGE.\n
0
31
+
+ N52833
+ nRF52833
+ 0x52833
+
N52840
nRF52840
@@ -303,6 +308,11 @@ POSSIBILITY OF SUCH DAMAGE.\n
QIxx - 73-pin aQFN
0x2004
+
+ CK
+ CKxx - WLCSP
+ 0x2005
+
Unspecified
Unspecified
@@ -706,7 +716,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
0x450
TAGHEADER0
- Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST.
0x000
read-only
0xFFFFFF5F
@@ -739,7 +749,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
TAGHEADER1
- Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST.
0x004
read-only
0xFFFFFFFF
@@ -772,7 +782,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
TAGHEADER2
- Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST.
0x008
read-only
0xFFFFFFFF
@@ -805,7 +815,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
TAGHEADER3
- Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST.
0x00C
read-only
0xFFFFFFFF
@@ -893,7 +903,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
Amount of bytes for the startup tests
0x00C
read-only
- 0x00000210
+ 0xFFFFFFFF
STARTUP
@@ -979,7 +989,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
0x20
- 0xF
+ 0xD
0x4
NRFFW[%s]
Description collection: Reserved for Nordic firmware design
@@ -1171,14 +1181,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
REGOUT0
- GPIO reference voltage / external output supply voltage in high voltage mode
+ Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP.
0x304
read-write
0xFFFFFFFF
VOUT
- Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF.
+ Output voltage from REG0 regulator stage.
0
2
@@ -2292,13 +2302,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
TASKS_CONSTLAT
- Enable constant latency mode
+ Enable Constant Latency mode
0x78
write-only
TASKS_CONSTLAT
- Enable constant latency mode
+ Enable Constant Latency mode
0
0
@@ -2313,13 +2323,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
TASKS_LOWPWR
- Enable low power mode (variable latency)
+ Enable Low-power mode (variable latency)
0x7C
write-only
TASKS_LOWPWR
- Enable low power mode (variable latency)
+ Enable Low-power mode (variable latency)
0
0
@@ -3357,7 +3367,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
DCDCEN
- Enable DC/DC converter for REG1 stage.
+ Enable DC/DC converter for REG1 stage
0x578
read-write
@@ -3383,7 +3393,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
DCDCEN0
- Enable DC/DC converter for REG0 stage.
+ Enable DC/DC converter for REG0 stage
0x580
read-write
@@ -49229,13 +49239,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
0x8
0x4
EVENTS_ENDEPIN[%s]
- Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
+ Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software.
0x108
read-write
EVENTS_ENDEPIN
- The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
+ The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software.
0
0
@@ -49281,13 +49291,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
EVENTS_ENDISOIN
- The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.
+ The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software.
0x12C
read-write
EVENTS_ENDISOIN
- The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.
+ The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software.
0
0
@@ -49309,13 +49319,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
0x8
0x4
EVENTS_ENDEPOUT[%s]
- Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
+ Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software.
0x130
read-write
EVENTS_ENDEPOUT
- The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
+ The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software.
0
0
@@ -49335,13 +49345,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
EVENTS_ENDISOOUT
- The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.
+ The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software.
0x150
read-write
EVENTS_ENDISOOUT
- The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.
+ The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software.
0
0
@@ -53093,7 +53103,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
PTR
- Data pointer. Accepts any address in Data RAM.
+ Data pointer
0
31
@@ -53142,7 +53152,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
PTR
- Data pointer. Accepts any address in Data RAM.
+ Data pointer
0
31
@@ -53193,7 +53203,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
PTR
- Data pointer. Accepts any address in Data RAM.
+ Data pointer
0
31
@@ -53242,7 +53252,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
PTR
- Data pointer. Accepts any address in Data RAM.
+ Data pointer
0
31
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_bitfields.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_bitfields.h
index 99cce73c2..5277c63ae 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_bitfields.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_bitfields.h
@@ -1599,6 +1599,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 31..0 : Part code */
#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */
#define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */
#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
@@ -1624,6 +1625,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */
+#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - WLCSP */
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_RAM */
@@ -1781,7 +1783,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
/* Register: FICR_NFC_TAGHEADER0 */
-/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 3 */
#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
@@ -1800,7 +1802,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
/* Register: FICR_NFC_TAGHEADER1 */
-/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 7 */
#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
@@ -1819,7 +1821,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
/* Register: FICR_NFC_TAGHEADER2 */
-/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 11 */
#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
@@ -1838,7 +1840,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
/* Register: FICR_NFC_TAGHEADER3 */
-/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
/* Bits 31..24 : Unique identifier byte 15 */
#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
@@ -7015,17 +7017,17 @@ POSSIBILITY OF SUCH DAMAGE.
/* Description: Power control */
/* Register: POWER_TASKS_CONSTLAT */
-/* Description: Enable constant latency mode */
+/* Description: Enable Constant Latency mode */
-/* Bit 0 : Enable constant latency mode */
+/* Bit 0 : Enable Constant Latency mode */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
/* Register: POWER_TASKS_LOWPWR */
-/* Description: Enable low power mode (variable latency) */
+/* Description: Enable Low-power mode (variable latency) */
-/* Bit 0 : Enable low power mode (variable latency) */
+/* Bit 0 : Enable Low-power mode (variable latency) */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
@@ -7341,7 +7343,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
/* Register: POWER_DCDCEN */
-/* Description: Enable DC/DC converter for REG1 stage. */
+/* Description: Enable DC/DC converter for REG1 stage */
/* Bit 0 : Enable DC/DC converter for REG1 stage. */
#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
@@ -7350,7 +7352,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
/* Register: POWER_DCDCEN0 */
-/* Description: Enable DC/DC converter for REG0 stage. */
+/* Description: Enable DC/DC converter for REG0 stage */
/* Bit 0 : Enable DC/DC converter for REG0 stage. */
#define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
@@ -15828,9 +15830,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */
/* Register: UICR_REGOUT0 */
-/* Description: GPIO reference voltage / external output supply voltage in high voltage mode */
+/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. */
-/* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */
+/* Bits 2..0 : Output voltage from REG0 regulator stage. */
#define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */
#define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */
#define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */
@@ -15936,9 +15938,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
/* Register: USBD_EVENTS_ENDEPIN */
-/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */
+/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
-/* Bit 0 : The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */
+/* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */
#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */
#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */
@@ -15954,27 +15956,27 @@ POSSIBILITY OF SUCH DAMAGE.
#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */
/* Register: USBD_EVENTS_ENDISOIN */
-/* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */
+/* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
-/* Bit 0 : The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */
+/* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */
#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */
#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */
#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */
/* Register: USBD_EVENTS_ENDEPOUT */
-/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */
+/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
-/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */
+/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */
#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */
#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */
#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */
/* Register: USBD_EVENTS_ENDISOOUT */
-/* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */
+/* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
-/* Bit 0 : The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */
+/* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */
#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */
#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */
@@ -17136,7 +17138,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: USBD_EPIN_PTR */
/* Description: Description cluster: Data pointer */
-/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+/* Bits 31..0 : Data pointer */
#define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
@@ -17157,7 +17159,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: USBD_ISOIN_PTR */
/* Description: Data pointer */
-/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+/* Bits 31..0 : Data pointer */
#define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
@@ -17178,7 +17180,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: USBD_EPOUT_PTR */
/* Description: Description cluster: Data pointer */
-/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+/* Bits 31..0 : Data pointer */
#define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
@@ -17199,7 +17201,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: USBD_ISOOUT_PTR */
/* Description: Data pointer */
-/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+/* Bits 31..0 : Data pointer */
#define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_peripherals.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_peripherals.h
index 415412fcc..731842baf 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_peripherals.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52840_peripherals.h
@@ -46,6 +46,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_FEATURE_RAM_REGISTERS_COUNT 9
#define POWER_FEATURE_VDDH_PRESENT
+#define POWER_FEATURE_VDDH_DCDC_PRESENT
/* Floating Point Unit */
#define FPU_PRESENT
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf52_to_nrf52833.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf52_to_nrf52833.h
new file mode 100644
index 000000000..8a541cc15
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf52_to_nrf52833.h
@@ -0,0 +1,150 @@
+/*
+
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef NRF52_TO_NRF52833_H
+#define NRF52_TO_NRF52833_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices.
+ * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the
+ * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
+ * from the nrf52_namechange.h file. */
+
+/* Differences between latest nRF52 headers and nRF52840 headers. */
+
+/* UART */
+/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
+#ifndef PSELRTS
+ #define PSELRTS PSEL.RTS
+#endif
+#ifndef PSELTXD
+ #define PSELTXD PSEL.TXD
+#endif
+#ifndef PSELCTS
+ #define PSELCTS PSEL.CTS
+#endif
+#ifndef PSELRXD
+ #define PSELRXD PSEL.RXD
+#endif
+
+/* TWI */
+/* The registers PSELSCL, PSELSDA were restructured into a struct. */
+#ifndef PSELSCL
+ #define PSELSCL PSEL.SCL
+#endif
+#ifndef PSELSDA
+ #define PSELSDA PSEL.SDA
+#endif
+
+/* LPCOMP */
+/* The hysteresis control enumerated values has changed name for nRF52833 devices. */
+#ifndef LPCOMP_HYST_HYST_NoHyst
+ #define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled
+#endif
+#ifndef LPCOMP_HYST_HYST_Hyst50mV
+ #define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled
+#endif
+
+
+/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
+
+/* I2S */
+/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
+#ifndef I2S_ENABLE_ENABLE_DISABLE
+ #define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
+#endif
+#ifndef I2S_ENABLE_ENABLE_ENABLE
+ #define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
+#endif
+#ifndef I2S_CONFIG_MODE_MODE_MASTER
+ #define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
+#endif
+#ifndef I2S_CONFIG_MODE_MODE_SLAVE
+ #define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
+#endif
+#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE
+ #define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
+#endif
+#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE
+ #define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
+#endif
+#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE
+ #define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
+#endif
+#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE
+ #define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
+#endif
+#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE
+ #define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
+#endif
+#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE
+ #define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
+#endif
+#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT
+ #define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
+#endif
+#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT
+ #define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
+#endif
+#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT
+ #define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
+#endif
+#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT
+ #define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
+#endif
+#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT
+ #define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
+#endif
+#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED
+ #define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
+#endif
+#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO
+ #define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
+#endif
+#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT
+ #define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
+#endif
+#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT
+ #define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
+#endif
+
+/* LPCOMP */
+/* Corrected typo in RESULT register. */
+#ifndef LPCOMP_RESULT_RESULT_Bellow
+ #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
+#endif
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF52_TO_NRF52833_H */
+
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf9160.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf9160.h
index c8d3eea1a..505034db8 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf9160.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf9160.h
@@ -30,10 +30,10 @@
* @file nrf9160.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 17. January 2019
- * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:40
+ * @date 23. August 2019
+ * @note Generated by SVDConv V3.3.25 on Friday, 23.08.2019 12:15:14
* from File 'nrf9160.svd',
- * last modified on Thursday, 17.01.2019 16:25:35
+ * last modified on Friday, 23.08.2019 10:15:09
*/
@@ -127,10 +127,10 @@ typedef enum {
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define __MPU_PRESENT 1 /*!< MPU present */
+#define __FPU_PRESENT 1 /*!< FPU present */
#define __FPU_DP 0 /*!< Double Precision FPU */
-#define __SAU_REGION_PRESENT 0 /*!< SAU present or not */
+#define __SAU_REGION_PRESENT 0 /*!< SAU present */
/** @} */ /* End of group Configuration_of_CMSIS */
@@ -214,8 +214,8 @@ typedef struct {
address range which the CPU can potentially
read! */
__IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the
- key slot with ID=n+1. Bits 0-15 and 16-31
- can only be written once. */
+ key slot. Bits 0-15 and 16-31 can only be
+ written when equal to 0xFFFF. */
} UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */
@@ -224,7 +224,7 @@ typedef struct {
*/
typedef struct {
__IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32]
- of value assigned to KMU key slot ID=n+1 */
+ of value assigned to KMU key slot. */
} UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */
@@ -343,7 +343,7 @@ typedef struct {
__IM uint32_t RESERVED[30];
__IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger */
__IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU
- to the debugger status has been read */
+ to the debugger has been read */
} CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */
@@ -351,8 +351,9 @@ typedef struct {
* @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified)
*/
typedef struct {
- __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock ERASEALL mechanism */
- __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Unlock ERASEPROTECT and perform ERASEALL */
+ __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register ERASEPROTECT.DISABLE from being
+ written until next reset */
+ __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable ERASEPROTECT and perform ERASEALL */
} CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */
@@ -406,7 +407,8 @@ typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */
__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
__IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */
-} SPIS_RXD_Type; /*!< Size = 12 (0xc) */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIS_RXD_Type; /*!< Size = 16 (0x10) */
/**
@@ -416,7 +418,8 @@ typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */
__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
__IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */
-} SPIS_TXD_Type; /*!< Size = 12 (0xc) */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIS_TXD_Type; /*!< Size = 16 (0x10) */
/**
@@ -466,7 +469,8 @@ typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */
__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */
__IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */
-} TWIS_RXD_Type; /*!< Size = 12 (0xc) */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIS_RXD_Type; /*!< Size = 16 (0x10) */
/**
@@ -476,7 +480,8 @@ typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */
__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */
__IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */
-} TWIS_TXD_Type; /*!< Size = 12 (0xc) */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIS_TXD_Type; /*!< Size = 16 (0x10) */
/**
@@ -742,7 +747,8 @@ typedef struct { /*!< (@ 0x00FF8000) UICR_S Struc
__IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */
__IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */
__IM uint32_t RESERVED3[53];
- __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: OTP bits [31+n*32:0+n*32]. */
+ __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: One time programmable
+ memory */
__IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */
} NRF_UICR_Type; /*!< Size = 4096 (0x1000) */
@@ -758,7 +764,9 @@ typedef struct { /*!< (@ 0x00FF8000) UICR_S Struc
*/
typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */
- __IM uint32_t RESERVED[320];
+ __OM uint32_t CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */
+ __OM uint32_t CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */
+ __IM uint32_t RESERVED[318];
__IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */
__IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */
__IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface */
@@ -825,10 +833,8 @@ typedef struct { /*!< (@ 0x50003000) SPU_S Struct
typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */
__IM uint32_t RESERVED[320];
__OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */
- __IM uint32_t RESERVED1[3];
- __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */
- __IM uint32_t RESERVED2[25];
- __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator */
+ __IM uint32_t RESERVED1[29];
+ __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator. */
} NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */
@@ -1005,7 +1011,7 @@ typedef struct { /*!< (@ 0x40008000) SPIM0_NS Str
__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
__IM uint32_t RESERVED20[26];
__IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in
- case and over-read of the TXD buffer. */
+ case an over-read of the TXD buffer. */
} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */
@@ -1054,14 +1060,12 @@ typedef struct { /*!< (@ 0x40008000) SPIS0_NS Str
__IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
__IM uint32_t RESERVED14[7];
__IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */
- __IM uint32_t RESERVED15;
__IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */
- __IM uint32_t RESERVED16;
__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
- __IM uint32_t RESERVED17;
+ __IM uint32_t RESERVED15;
__IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case
of an ignored transaction. */
- __IM uint32_t RESERVED18[24];
+ __IM uint32_t RESERVED16[24];
__IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */
} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */
@@ -1100,9 +1104,8 @@ typedef struct { /*!< (@ 0x40008000) TWIM0_NS Str
__IM uint32_t RESERVED8[7];
__IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
__IM uint32_t RESERVED9[8];
- __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND
- task has been issued, TWI traffic is now
- suspended. */
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is
+ now suspended. */
__IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
__IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
__IM uint32_t RESERVED10[2];
@@ -1206,14 +1209,13 @@ typedef struct { /*!< (@ 0x40008000) TWIS0_NS Str
__IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
__IM uint32_t RESERVED19[9];
__IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
- __IM uint32_t RESERVED20;
__IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
- __IM uint32_t RESERVED21[14];
+ __IM uint32_t RESERVED20[13];
__IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */
- __IM uint32_t RESERVED22;
+ __IM uint32_t RESERVED21;
__IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match
mechanism */
- __IM uint32_t RESERVED23[10];
+ __IM uint32_t RESERVED22[10];
__IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case
of an over-read of the transmit buffer. */
} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */
@@ -1460,7 +1462,9 @@ typedef struct { /*!< (@ 0x4000F000) TIMER0_NS St
__IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */
__IM uint32_t RESERVED8;
__IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */
- __IM uint32_t RESERVED9[11];
+ __IOM uint32_t ONESHOTEN[6]; /*!< (@ 0x00000514) Description collection: Enable one-shot operation
+ for Capture/Compare channel n */
+ __IM uint32_t RESERVED9[5];
__IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register
n */
} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */
@@ -1579,7 +1583,7 @@ typedef struct { /*!< (@ 0x40018000) WDT_NS Struc
/**
- * @brief Event Generator Unit 0 (EGU0_NS)
+ * @brief Event generator unit 0 (EGU0_NS)
*/
typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */
@@ -1838,9 +1842,9 @@ typedef struct { /*!< (@ 0x4002C000) FPU_NS Struc
typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */
__OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */
__IM uint32_t RESERVED[63];
- __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key successfully pushed over secure APB */
- __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key has been revoked and cannot be tasked for
- selection */
+ __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key slot successfully pushed over secure APB */
+ __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked
+ for selection */
__IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address
defined, or error during push operation */
__IM uint32_t RESERVED1[125];
@@ -1851,7 +1855,7 @@ typedef struct { /*!< (@ 0x40039000) KMU_NS Struc
__IM uint32_t RESERVED2[63];
__IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */
__IM uint32_t RESERVED3[60];
- __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot ID to be read over AHB or pushed
+ __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed
over secure APB when TASKS_PUSH_KEYSLOT
is started */
} NRF_KMU_Type; /*!< Size = 1284 (0x504) */
@@ -1875,7 +1879,7 @@ typedef struct { /*!< (@ 0x40039000) NVMC_NS Stru
__IM uint32_t RESERVED2[62];
__IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */
__IM uint32_t RESERVED3;
- __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */
+ __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */
__IM uint32_t RESERVED4[3];
__IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */
__IM uint32_t RESERVED5[8];
@@ -1886,13 +1890,7 @@ typedef struct { /*!< (@ 0x40039000) NVMC_NS Stru
__IM uint32_t RESERVED7[13];
__IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */
__OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */
- __IM uint32_t RESERVED8[93];
- __IOM uint32_t FORCEONNVM; /*!< (@ 0x00000700) Force on all NVM supplies. Also see the internal
- section in the NVMC chapter. */
- __IM uint32_t RESERVED9[9];
- __IOM uint32_t FORCEOFFNVM; /*!< (@ 0x00000728) Force off NVM supply. Also see the internal section
- in the NVMC chapter. */
-} NRF_NVMC_Type; /*!< Size = 1836 (0x72c) */
+} NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */
@@ -1912,6 +1910,44 @@ typedef struct { /*!< (@ 0x4003A000) VMC_NS Struc
+/* =========================================================================================================================== */
+/* ================ CC_HOST_RGF_S ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF_S)
+ */
+
+typedef struct { /*!< (@ 0x50840000) CC_HOST_RGF_S Structure */
+ __IM uint32_t RESERVED[1678];
+ __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */
+ __IM uint32_t RESERVED1[4];
+ __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register.
+ When this register is set, K_PRTL cannot
+ be used and a zeroed key will be used instead.
+ The value of this register is saved in the
+ CRYPTOCELL AO power domain. */
+ __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value
+ of this register is saved in the CRYPTOCELL
+ AO power domain. Reading from this address
+ returns the K_DR valid status indicating
+ if K_DR is successfully retained. */
+ __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value
+ of this register is saved in the CRYPTOCELL
+ AO power domain. */
+ __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value
+ of this register is saved in the CRYPTOCELL
+ AO power domain. */
+ __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The
+ value of this register is saved in the CRYPTOCELL
+ AO power domain. */
+ __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL
+ subsystem */
+} NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */
+
+
+
/* =========================================================================================================================== */
/* ================ CRYPTOCELL_S ================ */
/* =========================================================================================================================== */
@@ -1949,9 +1985,9 @@ typedef struct { /*!< (@ 0x40842500) P0_NS Struct
__IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that
have met the criteria set in the PIN_CNF[n].SENSE
registers */
- __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behaviour
+ __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior
and LDETECT mode (For non-secure pin only) */
- __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behaviour
+ __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior
and LDETECT mode (For secure pin only) */
__IM uint32_t RESERVED1[117];
__IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO
@@ -2074,6 +2110,7 @@ typedef struct { /*!< (@ 0x40842500) P0_NS Struct
#define NRF_NVMC_S_BASE 0x50039000UL
#define NRF_VMC_NS_BASE 0x4003A000UL
#define NRF_VMC_S_BASE 0x5003A000UL
+#define NRF_CC_HOST_RGF_S_BASE 0x50840000UL
#define NRF_CRYPTOCELL_S_BASE 0x50840000UL
#define NRF_P0_NS_BASE 0x40842500UL
#define NRF_P0_S_BASE 0x50842500UL
@@ -2193,6 +2230,7 @@ typedef struct { /*!< (@ 0x40842500) P0_NS Struct
#define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE)
#define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE)
#define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE)
+#define NRF_CC_HOST_RGF_S ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_S_BASE)
#define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE)
#define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE)
#define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE)
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf9160.svd b/third_party/NordicSemiconductor/nrfx/mdk/nrf9160.svd
index 22befbbc6..d34175309 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf9160.svd
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf9160.svd
@@ -613,16 +613,24 @@ POSSIBILITY OF SUCH DAMAGE.\n
0xBE
0x4
OTP[%s]
- Description collection: OTP bits [31+n*32:0+n*32].
+ Description collection: One time programmable memory
0x108
read-write
0xFFFFFFFF
- OTP
- Bits [31+n*32:0+n*32] of OTP region
+ LOWER
+ Lower half word
0
+ 15
+ read-writeonce
+
+
+ UPPER
+ Upper half word
+ 16
31
+ read-writeonce
@@ -660,7 +668,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
PERM
- Description cluster: Define permissions for the key slot with ID=n+1. Bits 0-15 and 16-31 can only be written once.
+ Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF.
0x004
read-write
0xFFFFFFFF
@@ -752,14 +760,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
0x4
0x4
VALUE[%s]
- Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot ID=n+1
+ Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot.
0x000
read-write
0xFFFFFFFF
VALUE
- Define bits [31+o*32:0+o*32] of value assigned to KMU key slot ID=n+1
+ Define bits [31+o*32:0+o*32] of value assigned to KMU key slot
0
31
@@ -784,6 +792,46 @@ POSSIBILITY OF SUCH DAMAGE.\n
TAD
0x20
+
+ CLOCKSTART
+ Start all trace and debug clocks.
+ 0x000
+ write-only
+
+
+ START
+ 0
+ 0
+
+
+ Start
+ Start all trace and debug clocks.
+ 1
+
+
+
+
+
+
+ CLOCKSTOP
+ Stop all trace and debug clocks.
+ 0x004
+ write-only
+
+
+ STOP
+ 0
+ 0
+
+
+ Stop
+ Stop all trace and debug clocks.
+ 1
+
+
+
+
+
ENABLE
Enable debug domain and aquire selected GPIOs
@@ -3140,94 +3188,9 @@ POSSIBILITY OF SUCH DAMAGE.\n
-
- POFCON
- Power-fail comparator configuration
- 0x510
- read-write
- 0x00000008
-
-
- POF
- Enable or disable power-fail comparator
- 0
- 0
-
-
- Disabled
- Disable
- 0
-
-
- Enabled
- Enable
- 1
-
-
-
-
- THRESHOLD
- Power-fail comparator threshold setting
- 1
- 4
-
-
- V19
- Set threshold to 1.9 V
- 6
-
-
- V20
- Set threshold to 2.0 V
- 7
-
-
- V21
- Set threshold to 2.1 V
- 8
-
-
- V22
- Set threshold to 2.2 V
- 9
-
-
- V23
- Set threshold to 2.3 V
- 10
-
-
- V24
- Set threshold to 2.4 V
- 11
-
-
- V25
- Set threshold to 2.5 V
- 12
-
-
- V26
- Set threshold to 2.6 V
- 13
-
-
- V27
- Set threshold to 2.7 V
- 14
-
-
- V28
- Set threshold to 2.8 V
- 15
-
-
-
-
-
DCDCEN
- Enable DC/DC mode of the main voltage regulator
+ Enable DC/DC mode of the main voltage regulator.
0x578
read-write
@@ -4837,7 +4800,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
TXSTATUS
- Status to indicate if data sent from the CPU to the debugger status has been read
+ Status to indicate if data sent from the CPU to the debugger has been read
0x84
read-only
0x00000000
@@ -4871,25 +4834,25 @@ POSSIBILITY OF SUCH DAMAGE.\n
0x500
LOCK
- Lock ERASEALL mechanism
+ Lock register ERASEPROTECT.DISABLE from being written until next reset
0x000
read-writeonce
0x00000000
- ERASEPROTECTLOCK
- Enable or disable the ERASEALL mechanism
+ LOCK
+ Lock register ERASEPROTECT.DISABLE from being written until next reset
0
0
Unlocked
- ERASEALL can be issued
+ Register ERASEPROTECT.DISABLE is writeable
0
Locked
- ERASEALL is locked
+ Register ERASEPROTECT.DISABLE is read-only
1
@@ -4898,14 +4861,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
DISABLE
- Unlock ERASEPROTECT and perform ERASEALL
+ Disable ERASEPROTECT and perform ERASEALL
0x004
read-write
0x00000000
KEY
- Initiate secure erase even though ERASEPROTECT is enabled if KEY fields match
+ The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side
0
31
@@ -6136,13 +6099,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
ORC
- Over-read character. Character clocked out in case and over-read of the TXD buffer.
+ Over-read character. Character clocked out in case an over-read of the TXD buffer.
0x5C0
read-write
ORC
- Over-read character. Character clocked out in case and over-read of the TXD buffer.
+ Over-read character. Character clocked out in case an over-read of the TXD buffer.
0
7
@@ -6961,6 +6924,32 @@ POSSIBILITY OF SUCH DAMAGE.\n
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
TXD
@@ -7010,6 +6999,32 @@ POSSIBILITY OF SUCH DAMAGE.\n
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
CONFIG
@@ -7437,13 +7452,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
EVENTS_SUSPENDED
- Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
+ SUSPEND task has been issued, TWI traffic is now suspended.
0x148
read-write
EVENTS_SUSPENDED
- Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
+ SUSPEND task has been issued, TWI traffic is now suspended.
0
0
@@ -10132,6 +10147,32 @@ POSSIBILITY OF SUCH DAMAGE.\n
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
TXD
@@ -10181,6 +10222,32 @@ POSSIBILITY OF SUCH DAMAGE.\n
+
+ LIST
+ EasyDMA list type
+ 0x00C
+ read-write
+
+
+ LIST
+ List type
+ 0
+ 1
+
+
+ Disabled
+ Disable EasyDMA list
+ 0
+
+
+ ArrayList
+ Use array list
+ 1
+
+
+
+
+
0x2
@@ -16180,7 +16247,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
Busy
- ADC is busy. Conversion in progress.
+ ADC is busy. Single conversion in progress.
1
@@ -16280,8 +16347,8 @@ POSSIBILITY OF SUCH DAMAGE.\n
8
- VDD
- VDD
+ VDDGPIO
+ VDD_GPIO
9
@@ -16347,8 +16414,8 @@ POSSIBILITY OF SUCH DAMAGE.\n
8
- VDD
- VDD
+ VDD_GPIO
+ VDD_GPIO
9
@@ -16380,12 +16447,12 @@ POSSIBILITY OF SUCH DAMAGE.\n
Pullup
- Pull-up to VDD
+ Pull-up to VDD_GPIO
2
VDD1_2
- Set input at VDD/2
+ Set input at VDD_GPIO/2
3
@@ -16408,12 +16475,12 @@ POSSIBILITY OF SUCH DAMAGE.\n
Pullup
- Pull-up to VDD
+ Pull-up to VDD_GPIO
2
VDD1_2
- Set input at VDD/2
+ Set input at VDD_GPIO/2
3
@@ -16479,7 +16546,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
VDD1_4
- VDD/4 as reference
+ VDD_GPIO/4 as reference
1
@@ -17816,6 +17883,34 @@ POSSIBILITY OF SUCH DAMAGE.\n
+
+ 0x6
+ 0x4
+ ONESHOTEN[%s]
+ Description collection: Enable one-shot operation for Capture/Compare channel n
+ 0x514
+ read-write
+
+
+ ONESHOTEN
+ Enable one-shot operation
+ 0
+ 0
+
+
+ Disable
+ Disable one-shot operation
+ 0
+
+
+ Enable
+ Enable one-shot operation
+ 1
+
+
+
+
+
0x6
0x4
@@ -21416,7 +21511,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU0_NS
- Event Generator Unit 0
+ Event generator unit 0
0x4001B000
EGU
@@ -22730,7 +22825,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU0_S
- Event Generator Unit 1
+ Event generator unit 1
0x5001B000
@@ -22741,7 +22836,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU1_NS
- Event Generator Unit 2
+ Event generator unit 2
0x4001C000
@@ -22752,7 +22847,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU1_S
- Event Generator Unit 3
+ Event generator unit 3
0x5001C000
@@ -22763,7 +22858,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU2_NS
- Event Generator Unit 4
+ Event generator unit 4
0x4001D000
@@ -22774,7 +22869,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU2_S
- Event Generator Unit 5
+ Event generator unit 5
0x5001D000
@@ -22785,7 +22880,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU3_NS
- Event Generator Unit 6
+ Event generator unit 6
0x4001E000
@@ -22796,7 +22891,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU3_S
- Event Generator Unit 7
+ Event generator unit 7
0x5001E000
@@ -22807,7 +22902,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU4_NS
- Event Generator Unit 8
+ Event generator unit 8
0x4001F000
@@ -22818,7 +22913,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU4_S
- Event Generator Unit 9
+ Event generator unit 9
0x5001F000
@@ -22829,7 +22924,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU5_NS
- Event Generator Unit 10
+ Event generator unit 10
0x40020000
@@ -22840,7 +22935,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
EGU5_S
- Event Generator Unit 11
+ Event generator unit 11
0x50020000
@@ -27740,13 +27835,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
EVENTS_KEYSLOT_PUSHED
- Key successfully pushed over secure APB
+ Key slot successfully pushed over secure APB
0x100
read-write
EVENTS_KEYSLOT_PUSHED
- Key successfully pushed over secure APB
+ Key slot successfully pushed over secure APB
0
0
@@ -27766,13 +27861,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
EVENTS_KEYSLOT_REVOKED
- Key has been revoked and cannot be tasked for selection
+ Key slot has been revoked and cannot be tasked for selection
0x104
read-write
EVENTS_KEYSLOT_REVOKED
- Key has been revoked and cannot be tasked for selection
+ Key slot has been revoked and cannot be tasked for selection
0
0
@@ -28168,14 +28263,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
SELECTKEYSLOT
- Select key slot ID to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started
+ Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started
0x500
read-write
0x00000000
ID
- Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Note that index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU keyslot ID=N+1
+ Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1
0
7
@@ -28296,7 +28391,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
ERASEALL
Register for erasing all non-volatile user memory
0x50C
- read-write
+ write-only
@@ -28390,7 +28485,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
HITS
- Number of cache hits
+ Number of cache hits Write zero to clear
0
31
@@ -28405,7 +28500,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
MISSES
- Number of cache misses
+ Number of cache misses Write zero to clear
0
31
@@ -28478,92 +28573,6 @@ POSSIBILITY OF SUCH DAMAGE.\n
-
- FORCEONNVM
- Force on all NVM supplies. Also see the internal section in the NVMC chapter.
- 0x700
- read-write
-
-
-
- FORCEONNVM
- Force on all NVM supplies. Also see the internal section in the NVMC chapter.
- 0
- 0
-
-
- DoNotForceOn
- Do not force on NVM supply
- 0
-
-
- ForceOn
- Force on NVM supply
- 1
-
-
-
-
-
-
- FORCEOFFNVM
- Force off NVM supply. Also see the internal section in the NVMC chapter.
- 0x728
- read-write
-
-
-
- FORCEOFFNVM0
- Force off NVM supply 0. Also see the internal section in the NVMC chapter.
- 0
- 0
-
-
- DoNotForceOff
- Do not force off supply
- 0
-
-
- ForceOff
- Force off supply
- 1
-
-
-
-
- FORCEOFFNVM1
- Force off NVM supply 1. Also see the internal section in the NVMC chapter.
- 1
- 1
-
-
- DoNotForceOff
- Do not force off supply
- 0
-
-
- ForceOff
- Force off supply
- 1
-
-
-
-
- KEY
- KEY
- 8
- 31
-
- write
-
- EnableWrite
- Must be written in order to write to bits 0-7. Any other value will ignore writes to this register. Read as zero.
- 0xACCE55
-
-
-
-
-
@@ -28997,10 +29006,192 @@ POSSIBILITY OF SUCH DAMAGE.\n
+
+ CC_HOST_RGF_S
+ CRYPTOCELL HOST_RGF interface
+ 0x50840000
+ CC_HOST_RGF
+
+
+
+ 0
+ 0x2000
+ registers
+
+ CC_HOST_RGF
+ 0x20
+
+
+ HOST_CRYPTOKEY_SEL
+ AES hardware key select
+ 0x1A38
+ read-write
+ 0x00000000
+
+
+ HOST_CRYPTOKEY_SEL
+ Select the source of the HW key that is used by the AES engine
+ 0
+ 1
+
+
+ K_DR
+ Use device root key K_DR from CRYPTOCELL AO power domain
+ 0
+
+
+ K_PRTL
+ Use hard-coded RTL key K_PRTL
+ 1
+
+
+ Session
+ Use provided session key
+ 2
+
+
+
+
+
+
+ HOST_IOT_KPRTL_LOCK
+ This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.
+ 0x1A4C
+ read-write
+ 0x00000000
+
+
+ HOST_IOT_KPRTL_LOCK
+ This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.
+ 0
+ 0
+
+
+ Disabled
+ K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL
+ 0
+
+
+ Enabled
+ K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead.
+ 1
+
+
+
+
+
+
+ HOST_IOT_KDR0
+ This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained.
+ 0x1A50
+ read-write
+ 0x00000000
+
+
+ HOST_IOT_KDR0
+ Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain.
+ 0
+ 31
+
+
+
+
+ HOST_IOT_KDR1
+ This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.
+ 0x1A54
+ write-only
+ 0x00000000
+
+
+ HOST_IOT_KDR1
+ K_DR bits 63:32
+ 0
+ 31
+
+
+
+
+ HOST_IOT_KDR2
+ This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.
+ 0x1A58
+ write-only
+ 0x00000000
+
+
+ HOST_IOT_KDR2
+ K_DR bits 95:64
+ 0
+ 31
+
+
+
+
+ HOST_IOT_KDR3
+ This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.
+ 0x1A5C
+ write-only
+ 0x00000000
+
+
+ HOST_IOT_KDR3
+ K_DR bits 127:96
+ 0
+ 31
+
+
+
+
+ HOST_IOT_LCS
+ Controls lifecycle state (LCS) for CRYPTOCELL subsystem
+ 0x1A60
+ read-write
+ 0x00000002
+
+
+ LCS
+ Lifecycle state value. This field is write-once per reset.
+ 0
+ 2
+
+
+ Debug
+ CC310 operates in debug mode
+ 0
+
+
+ Secure
+ CC310 operates in secure mode
+ 2
+
+
+
+
+ LCS_IS_VALID
+ Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset.
+ 8
+ 8
+
+
+ Invalid
+ Valid LCS not yet retained in the CRYPTOCELL AO power domain
+ 0
+
+
+ Valid
+ Valid LCS successfully retained in the CRYPTOCELL AO power domain
+ 1
+
+
+
+
+
+
+
CRYPTOCELL_S
ARM TrustZone CryptoCell register interface
0x50840000
+ CC_HOST_RGF_S
CRYPTOCELL
@@ -29036,7 +29227,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
Enabled
- CRYPTOCELL subsystem enabled
+ CRYPTOCELL subsystem enabled.
1
@@ -34890,13 +35081,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
DETECTMODE
- Select between default DETECT signal behaviour and LDETECT mode (For non-secure pin only)
+ Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only)
0x024
read-write
DETECTMODE
- Select between default DETECT signal behaviour and LDETECT mode
+ Select between default DETECT signal behavior and LDETECT mode
0
0
@@ -34907,7 +35098,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
LDETECT
- Use the latched LDETECT behaviour
+ Use the latched LDETECT behavior
1
@@ -34916,13 +35107,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
DETECTMODE_SEC
- Select between default DETECT signal behaviour and LDETECT mode (For secure pin only)
+ Select between default DETECT signal behavior and LDETECT mode (For secure pin only)
0x028
read-write
DETECTMODE
- Select between default DETECT signal behaviour and LDETECT mode
+ Select between default DETECT signal behavior and LDETECT mode
0
0
@@ -34933,7 +35124,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
LDETECT
- Use the latched LDETECT behaviour
+ Use the latched LDETECT behavior
1
@@ -35036,7 +35227,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
D0S1
- Disconnect '0' standard '1' (normally used for wired-or connections)
+ Disconnect '0', standard '1' (normally used for wired-or connections)
4
@@ -35046,7 +35237,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
S0D1
- Standard '0'. disconnect '1' (normally used for wired-and connections)
+ Standard '0', disconnect '1' (normally used for wired-and connections)
6
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_bitfields.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_bitfields.h
index a68ff80fc..f9e9e5747 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_bitfields.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_bitfields.h
@@ -35,6 +35,72 @@ POSSIBILITY OF SUCH DAMAGE.
/*lint ++flb "Enter library region" */
+/* Peripheral: CC_HOST_RGF */
+/* Description: CRYPTOCELL HOST_RGF interface */
+
+/* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */
+/* Description: AES hardware key select */
+
+/* Bits 1..0 : Select the source of the HW key that is used by the AES engine */
+#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */
+#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */
+#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */
+#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */
+#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */
+
+/* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */
+/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
+
+/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
+#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */
+#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */
+#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */
+#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */
+
+/* Register: CC_HOST_RGF_HOST_IOT_KDR0 */
+/* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */
+
+/* Bits 31..0 : Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */
+#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */
+#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */
+
+/* Register: CC_HOST_RGF_HOST_IOT_KDR1 */
+/* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
+
+/* Bits 31..0 : K_DR bits 63:32 */
+#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */
+#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */
+
+/* Register: CC_HOST_RGF_HOST_IOT_KDR2 */
+/* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
+
+/* Bits 31..0 : K_DR bits 95:64 */
+#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */
+#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */
+
+/* Register: CC_HOST_RGF_HOST_IOT_KDR3 */
+/* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
+
+/* Bits 31..0 : K_DR bits 127:96 */
+#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */
+#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */
+
+/* Register: CC_HOST_RGF_HOST_IOT_LCS */
+/* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */
+
+/* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */
+
+/* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */
+
+
/* Peripheral: CLOCK */
/* Description: Clock management 0 */
@@ -309,7 +375,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */
-#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */
+#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled. */
/* Peripheral: CTRLAPPERI */
@@ -339,7 +405,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */
/* Register: CTRLAPPERI_MAILBOX_TXSTATUS */
-/* Description: Status to indicate if data sent from the CPU to the debugger status has been read */
+/* Description: Status to indicate if data sent from the CPU to the debugger has been read */
/* Bit 0 : Status of data in register TXDATA */
#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */
@@ -348,18 +414,18 @@ POSSIBILITY OF SUCH DAMAGE.
#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */
/* Register: CTRLAPPERI_ERASEPROTECT_LOCK */
-/* Description: Lock ERASEALL mechanism */
+/* Description: Lock register ERASEPROTECT.DISABLE from being written until next reset */
-/* Bit 0 : Enable or disable the ERASEALL mechanism */
-#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos (0UL) /*!< Position of ERASEPROTECTLOCK field. */
-#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos) /*!< Bit mask of ERASEPROTECTLOCK field. */
-#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked (0UL) /*!< ERASEALL can be issued */
-#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked (1UL) /*!< ERASEALL is locked */
+/* Bit 0 : Lock register ERASEPROTECT.DISABLE from being written until next reset */
+#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
+#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */
+#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */
/* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */
-/* Description: Unlock ERASEPROTECT and perform ERASEALL */
+/* Description: Disable ERASEPROTECT and perform ERASEALL */
-/* Bits 31..0 : Initiate secure erase even though ERASEPROTECT is enabled if KEY fields match */
+/* Bits 31..0 : The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side */
#define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
#define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
@@ -839,7 +905,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: EGU */
-/* Description: Event Generator Unit 0 */
+/* Description: Event generator unit 0 */
/* Register: EGU_TASKS_TRIGGER */
/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
@@ -2409,18 +2475,18 @@ POSSIBILITY OF SUCH DAMAGE.
#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL) /*!< Trigger task */
/* Register: KMU_EVENTS_KEYSLOT_PUSHED */
-/* Description: Key successfully pushed over secure APB */
+/* Description: Key slot successfully pushed over secure APB */
-/* Bit 0 : Key successfully pushed over secure APB */
+/* Bit 0 : Key slot successfully pushed over secure APB */
#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */
#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */
#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0UL) /*!< Event not generated */
#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL) /*!< Event generated */
/* Register: KMU_EVENTS_KEYSLOT_REVOKED */
-/* Description: Key has been revoked and cannot be tasked for selection */
+/* Description: Key slot has been revoked and cannot be tasked for selection */
-/* Bit 0 : Key has been revoked and cannot be tasked for selection */
+/* Bit 0 : Key slot has been revoked and cannot be tasked for selection */
#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */
#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */
#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0UL) /*!< Event not generated */
@@ -2541,9 +2607,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define KMU_STATUS_SELECTED_Enabled (1UL) /*!< Key slot ID successfully selected by KMU */
/* Register: KMU_SELECTKEYSLOT */
-/* Description: Select key slot ID to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */
+/* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */
-/* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Note that index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU keyslot ID=N+1 */
+/* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1 */
#define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */
#define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */
@@ -2614,14 +2680,14 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: NVMC_IHIT */
/* Description: I-code cache hit counter */
-/* Bits 31..0 : Number of cache hits */
+/* Bits 31..0 : Number of cache hits Write zero to clear */
#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
/* Register: NVMC_IMISS */
/* Description: I-code cache miss counter */
-/* Bits 31..0 : Number of cache misses */
+/* Bits 31..0 : Number of cache misses Write zero to clear */
#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
@@ -2648,35 +2714,6 @@ POSSIBILITY OF SUCH DAMAGE.
#define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */
#define NVMC_WRITEUICRNS_SET_Set (1UL) /*!< Set value */
-/* Register: NVMC_FORCEONNVM */
-/* Description: Force on all NVM supplies. Also see the internal section in the NVMC chapter. */
-
-/* Bit 0 : Force on all NVM supplies. Also see the internal section in the NVMC chapter. */
-#define NVMC_FORCEONNVM_FORCEONNVM_Pos (0UL) /*!< Position of FORCEONNVM field. */
-#define NVMC_FORCEONNVM_FORCEONNVM_Msk (0x1UL << NVMC_FORCEONNVM_FORCEONNVM_Pos) /*!< Bit mask of FORCEONNVM field. */
-#define NVMC_FORCEONNVM_FORCEONNVM_DoNotForceOn (0UL) /*!< Do not force on NVM supply */
-#define NVMC_FORCEONNVM_FORCEONNVM_ForceOn (1UL) /*!< Force on NVM supply */
-
-/* Register: NVMC_FORCEOFFNVM */
-/* Description: Force off NVM supply. Also see the internal section in the NVMC chapter. */
-
-/* Bits 31..8 : KEY */
-#define NVMC_FORCEOFFNVM_KEY_Pos (8UL) /*!< Position of KEY field. */
-#define NVMC_FORCEOFFNVM_KEY_Msk (0xFFFFFFUL << NVMC_FORCEOFFNVM_KEY_Pos) /*!< Bit mask of KEY field. */
-#define NVMC_FORCEOFFNVM_KEY_EnableWrite (0xACCE55UL) /*!< Must be written in order to write to bits 0-7. Any other value will ignore writes to this register. Read as zero. */
-
-/* Bit 1 : Force off NVM supply 1. Also see the internal section in the NVMC chapter. */
-#define NVMC_FORCEOFFNVM_FORCEOFFNVM1_Pos (1UL) /*!< Position of FORCEOFFNVM1 field. */
-#define NVMC_FORCEOFFNVM_FORCEOFFNVM1_Msk (0x1UL << NVMC_FORCEOFFNVM_FORCEOFFNVM1_Pos) /*!< Bit mask of FORCEOFFNVM1 field. */
-#define NVMC_FORCEOFFNVM_FORCEOFFNVM1_DoNotForceOff (0UL) /*!< Do not force off supply */
-#define NVMC_FORCEOFFNVM_FORCEOFFNVM1_ForceOff (1UL) /*!< Force off supply */
-
-/* Bit 0 : Force off NVM supply 0. Also see the internal section in the NVMC chapter. */
-#define NVMC_FORCEOFFNVM_FORCEOFFNVM0_Pos (0UL) /*!< Position of FORCEOFFNVM0 field. */
-#define NVMC_FORCEOFFNVM_FORCEOFFNVM0_Msk (0x1UL << NVMC_FORCEOFFNVM_FORCEOFFNVM0_Pos) /*!< Bit mask of FORCEOFFNVM0 field. */
-#define NVMC_FORCEOFFNVM_FORCEOFFNVM0_DoNotForceOff (0UL) /*!< Do not force off supply */
-#define NVMC_FORCEOFFNVM_FORCEOFFNVM0_ForceOff (1UL) /*!< Force off supply */
-
/* Peripheral: GPIO */
/* Description: GPIO Port 0 */
@@ -4370,22 +4407,22 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
/* Register: GPIO_DETECTMODE */
-/* Description: Select between default DETECT signal behaviour and LDETECT mode (For non-secure pin only) */
+/* Description: Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) */
-/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
+/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
-#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
+#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
/* Register: GPIO_DETECTMODE_SEC */
-/* Description: Select between default DETECT signal behaviour and LDETECT mode (For secure pin only) */
+/* Description: Select between default DETECT signal behavior and LDETECT mode (For secure pin only) */
-/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
+/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
#define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
#define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
#define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
-#define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
+#define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
/* Register: GPIO_PIN_CNF */
/* Description: Description collection: Configuration of GPIO pins */
@@ -4404,9 +4441,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
-#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */
#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
-#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */
#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
/* Bits 3..2 : Pull configuration */
@@ -5436,31 +5473,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */
-/* Register: REGULATORS_POFCON */
-/* Description: Power-fail comparator configuration */
-
-/* Bits 4..1 : Power-fail comparator threshold setting */
-#define REGULATORS_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
-#define REGULATORS_POFCON_THRESHOLD_Msk (0xFUL << REGULATORS_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
-#define REGULATORS_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
-#define REGULATORS_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
-#define REGULATORS_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
-#define REGULATORS_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
-#define REGULATORS_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
-#define REGULATORS_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
-#define REGULATORS_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
-#define REGULATORS_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
-#define REGULATORS_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
-#define REGULATORS_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
-
-/* Bit 0 : Enable or disable power-fail comparator */
-#define REGULATORS_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
-#define REGULATORS_POFCON_POF_Msk (0x1UL << REGULATORS_POFCON_POF_Pos) /*!< Bit mask of POF field. */
-#define REGULATORS_POFCON_POF_Disabled (0UL) /*!< Disable */
-#define REGULATORS_POFCON_POF_Enabled (1UL) /*!< Enable */
-
/* Register: REGULATORS_DCDCEN */
-/* Description: Enable DC/DC mode of the main voltage regulator */
+/* Description: Enable DC/DC mode of the main voltage regulator. */
/* Bit 0 : Enable DC/DC converter */
#define REGULATORS_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
@@ -6582,7 +6596,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
-#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
+#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Single conversion in progress. */
/* Register: SAADC_ENABLE */
/* Description: Enable or disable ADC */
@@ -6608,7 +6622,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
-#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
+#define SAADC_CH_PSELP_PSELP_VDDGPIO (9UL) /*!< VDD_GPIO */
/* Register: SAADC_CH_PSELN */
/* Description: Description cluster: Input negative pin selection for CH[n] */
@@ -6625,7 +6639,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
-#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
+#define SAADC_CH_PSELN_PSELN_VDD_GPIO (9UL) /*!< VDD_GPIO */
/* Register: SAADC_CH_CONFIG */
/* Description: Description cluster: Input configuration for CH[n] */
@@ -6656,7 +6670,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
-#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
+#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD_GPIO/4 as reference */
/* Bits 10..8 : Gain control */
#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
@@ -6675,16 +6689,16 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
-#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
-#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD_GPIO */
+#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */
/* Bits 1..0 : Positive channel resistor control */
#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
-#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
-#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD_GPIO */
+#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */
/* Register: SAADC_CH_LIMIT */
/* Description: Description cluster: High/low limits for event monitoring a channel */
@@ -7185,9 +7199,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
/* Register: SPIM_ORC */
-/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
+/* Description: Over-read character. Character clocked out in case an over-read of the TXD buffer. */
-/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
+/* Bits 7..0 : Over-read character. Character clocked out in case an over-read of the TXD buffer. */
#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
@@ -7470,6 +7484,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+/* Register: SPIS_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
/* Register: SPIS_TXD_PTR */
/* Description: TXD data pointer */
@@ -7491,6 +7514,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+/* Register: SPIS_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
/* Register: SPIS_CONFIG */
/* Description: Configuration register */
@@ -8190,6 +8222,22 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: TAD */
/* Description: Trace and debug control */
+/* Register: TAD_CLOCKSTART */
+/* Description: Start all trace and debug clocks. */
+
+/* Bit 0 : */
+#define TAD_CLOCKSTART_START_Pos (0UL) /*!< Position of START field. */
+#define TAD_CLOCKSTART_START_Msk (0x1UL << TAD_CLOCKSTART_START_Pos) /*!< Bit mask of START field. */
+#define TAD_CLOCKSTART_START_Start (1UL) /*!< Start all trace and debug clocks. */
+
+/* Register: TAD_CLOCKSTOP */
+/* Description: Stop all trace and debug clocks. */
+
+/* Bit 0 : */
+#define TAD_CLOCKSTOP_STOP_Pos (0UL) /*!< Position of STOP field. */
+#define TAD_CLOCKSTOP_STOP_Msk (0x1UL << TAD_CLOCKSTOP_STOP_Pos) /*!< Bit mask of STOP field. */
+#define TAD_CLOCKSTOP_STOP_Stop (1UL) /*!< Stop all trace and debug clocks. */
+
/* Register: TAD_ENABLE */
/* Description: Enable debug domain and aquire selected GPIOs */
@@ -8620,6 +8668,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+/* Register: TIMER_ONESHOTEN */
+/* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */
+
+/* Bit 0 : Enable one-shot operation */
+#define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */
+#define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */
+#define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */
+#define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */
+
/* Register: TIMER_CC */
/* Description: Description collection: Capture/Compare register n */
@@ -8755,9 +8812,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
/* Register: TWIM_EVENTS_SUSPENDED */
-/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
+/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */
-/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
+/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
@@ -9680,6 +9737,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+/* Register: TWIS_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
/* Register: TWIS_TXD_PTR */
/* Description: TXD Data pointer */
@@ -9701,6 +9767,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+/* Register: TWIS_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
/* Register: TWIS_ADDRESS */
/* Description: Description collection: TWI slave address n */
@@ -10560,11 +10635,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
/* Register: UICR_OTP */
-/* Description: Description collection: OTP bits [31+n*32:0+n*32]. */
+/* Description: Description collection: One time programmable memory */
-/* Bits 31..0 : Bits [31+n*32:0+n*32] of OTP region */
-#define UICR_OTP_OTP_Pos (0UL) /*!< Position of OTP field. */
-#define UICR_OTP_OTP_Msk (0xFFFFFFFFUL << UICR_OTP_OTP_Pos) /*!< Bit mask of OTP field. */
+/* Bits 31..16 : Upper half word */
+#define UICR_OTP_UPPER_Pos (16UL) /*!< Position of UPPER field. */
+#define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos) /*!< Bit mask of UPPER field. */
+
+/* Bits 15..0 : Lower half word */
+#define UICR_OTP_LOWER_Pos (0UL) /*!< Position of LOWER field. */
+#define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos) /*!< Bit mask of LOWER field. */
/* Register: UICR_KEYSLOT_CONFIG_DEST */
/* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3])
@@ -10577,7 +10656,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos) /*!< Bit mask of DEST field. */
/* Register: UICR_KEYSLOT_CONFIG_PERM */
-/* Description: Description cluster: Define permissions for the key slot with ID=n+1. Bits 0-15 and 16-31 can only be written once. */
+/* Description: Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. */
/* Bit 16 : Revocation state for the key slot */
#define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */
@@ -10604,9 +10683,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL) /*!< Enable write to the key value registers */
/* Register: UICR_KEYSLOT_KEY_VALUE */
-/* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot ID=n+1 */
+/* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */
-/* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot ID=n+1 */
+/* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot */
#define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_name_change.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_name_change.h
new file mode 100644
index 000000000..9feeab57e
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_name_change.h
@@ -0,0 +1,56 @@
+/*
+
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef NRF9160_NAME_CHANGE_H
+#define NRF9160_NAME_CHANGE_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf9160.h and
+ * nrf9160_bitfields.h. The macros defined in this file were available previously. Do not use these
+ * macros on purpose. Use the ones defined in nrf9160.h and nrf9160_bitfields.h instead.
+ */
+
+ /* SAADC enums */
+ /* Changes to enum names in SAADC */
+ #define SAADC_CH_PSELP_PSELP_VDD SAADC_CH_PSELP_PSELP_VDDGPIO
+ #define SAADC_CH_PSELP_PSELN_VDD SAADC_CH_PSELP_PSELN_VDDGPIO
+
+ /* CTRLAP PERI Fields */
+ #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos
+ #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Msk CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk
+ #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked
+ #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked
+
+ /*lint --flb "Leave library region" */
+
+#endif /* NRF9160_NAME_CHANGE_H */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_xxaa.ld b/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_xxaa.ld
index 9353af4f6..113371037 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_xxaa.ld
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf9160_xxaa.ld
@@ -10,4 +10,4 @@ MEMORY
}
-INCLUDE "nrf_common.ld"
\ No newline at end of file
+INCLUDE "nrf_common.ld"
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf91_common.ld b/third_party/NordicSemiconductor/nrfx/mdk/nrf91_common.ld
deleted file mode 100644
index 0a2bf73c2..000000000
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf91_common.ld
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Linker script for Nordic Semiconductor nRF91 devices
- *
- * Version: Sourcery G++ 4.5-1
- * Support: https://support.codesourcery.com/GNUToolchain/
- *
- * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .text :
- {
- KEEP(*(.isr_vector))
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- *(.eh_frame*)
- . = ALIGN(4);
- } > FLASH
-
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- . = ALIGN(4);
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- . = ALIGN(4);
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- *(.jcr)
- . = ALIGN(4);
- /* All data end */
- __data_end__ = .;
-
- } > RAM
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start__ = .;
- *(.bss*)
- *(COMMON)
- . = ALIGN(4);
- __bss_end__ = .;
- } > RAM
-
- .heap (COPY):
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
\ No newline at end of file
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/nrf_peripherals.h b/third_party/NordicSemiconductor/nrfx/mdk/nrf_peripherals.h
index 14eb9b2fe..e3dd9ad6f 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/nrf_peripherals.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/nrf_peripherals.h
@@ -42,19 +42,23 @@ POSSIBILITY OF SUCH DAMAGE.
#elif defined(__APPLE__)
/* Do not include nrf specific files when building for PC host */
#else
-
+
#if defined(NRF51)
#include "nrf51_peripherals.h"
-
+
+ #elif defined (NRF52805_XXAA)
+ #include "nrf52805_peripherals.h"
#elif defined(NRF52810_XXAA)
#include "nrf52810_peripherals.h"
#elif defined(NRF52811_XXAA)
#include "nrf52811_peripherals.h"
#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
#include "nrf52832_peripherals.h"
+ #elif defined (NRF52833_XXAA)
+ #include "nrf52833_peripherals.h"
#elif defined(NRF52840_XXAA)
#include "nrf52840_peripherals.h"
-
+
#elif defined(NRF9160_XXAA)
#include "nrf9160_peripherals.h"
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf51.s b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf51.s
index 4c3d9a0c7..658156894 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf51.s
+++ b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf51.s
@@ -176,6 +176,7 @@ Dummy_Handler:
.extern Reset_Handler
.global nRFInitialize
+ .extern afterInitialize
.equ NRF_POWER_RAMON_ADDRESS, 0x40000524
.equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
.equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
@@ -193,7 +194,7 @@ nRFInitialize:
LDR R2, [R0]
ORRS R2, R1
STR R2, [R0]
- bx lr
+ b afterInitialize
/************************************************************************************
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52.s b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52.s
index ed8c5067e..4cdce20d6 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52.s
+++ b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52.s
@@ -232,10 +232,11 @@ Dummy_Handler:
.extern Reset_Handler
.global nRFInitialize
+ .extern afterInitialize
.thumb_func
nRFInitialize:
- bx lr
+ b afterInitialize
/************************************************************************************
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52805.s b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52805.s
new file mode 100644
index 000000000..0303941c0
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52805.s
@@ -0,0 +1,349 @@
+/***********************************************************************************
+ * SEGGER Microcontroller GmbH *
+ * The Embedded Experts *
+ ***********************************************************************************
+ * *
+ * (c) 2014 - 2018 SEGGER Microcontroller GmbH *
+ * *
+ * www.segger.com Support: support@segger.com *
+ * *
+ ***********************************************************************************
+ * *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or *
+ * without modification, are permitted provided that the following *
+ * conditions are met: *
+ * *
+ * - Redistributions of source code must retain the above copyright *
+ * notice, this list of conditions and the following disclaimer. *
+ * *
+ * - Neither the name of SEGGER Microcontroller GmbH *
+ * nor the names of its contributors may be used to endorse or *
+ * promote products derived from this software without specific *
+ * prior written permission. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
+ * DISCLAIMED. *
+ * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR *
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
+ * DAMAGE. *
+ * *
+ ***********************************************************************************/
+
+/************************************************************************************
+ * Preprocessor Definitions *
+ * ------------------------ *
+ * VECTORS_IN_RAM *
+ * *
+ * If defined, an area of RAM will large enough to store the vector table *
+ * will be reserved. *
+ * *
+ ************************************************************************************/
+
+ .syntax unified
+ .code 16
+
+ .section .init, "ax"
+ .align 0
+
+/************************************************************************************
+ * Default Exception Handlers *
+ ************************************************************************************/
+
+
+ .thumb_func
+ .weak NMI_Handler
+NMI_Handler:
+ b .
+
+ .thumb_func
+ .weak HardFault_Handler
+HardFault_Handler:
+ b .
+
+ .thumb_func
+ .weak MemoryManagement_Handler
+MemoryManagement_Handler:
+ b .
+
+ .thumb_func
+ .weak BusFault_Handler
+BusFault_Handler:
+ b .
+
+ .thumb_func
+ .weak UsageFault_Handler
+UsageFault_Handler:
+ b .
+
+ .thumb_func
+ .weak SVC_Handler
+SVC_Handler:
+ b .
+
+ .thumb_func
+ .weak DebugMon_Handler
+DebugMon_Handler:
+ b .
+
+ .thumb_func
+ .weak PendSV_Handler
+PendSV_Handler:
+ b .
+
+ .thumb_func
+ .weak SysTick_Handler
+SysTick_Handler:
+ b .
+
+ .thumb_func
+ .weak Dummy_Handler
+Dummy_Handler:
+ b .
+
+/************************************************************************************
+ * Default Interrupt Handlers *
+ ************************************************************************************/
+
+.weak POWER_CLOCK_IRQHandler
+.thumb_set POWER_CLOCK_IRQHandler, Dummy_Handler
+
+.weak RADIO_IRQHandler
+.thumb_set RADIO_IRQHandler, Dummy_Handler
+
+.weak UARTE0_UART0_IRQHandler
+.thumb_set UARTE0_UART0_IRQHandler, Dummy_Handler
+
+.weak TWIM0_TWIS0_TWI0_IRQHandler
+.thumb_set TWIM0_TWIS0_TWI0_IRQHandler, Dummy_Handler
+
+.weak SPIM0_SPIS0_SPI0_IRQHandler
+.thumb_set SPIM0_SPIS0_SPI0_IRQHandler, Dummy_Handler
+
+.weak GPIOTE_IRQHandler
+.thumb_set GPIOTE_IRQHandler, Dummy_Handler
+
+.weak SAADC_IRQHandler
+.thumb_set SAADC_IRQHandler, Dummy_Handler
+
+.weak TIMER0_IRQHandler
+.thumb_set TIMER0_IRQHandler, Dummy_Handler
+
+.weak TIMER1_IRQHandler
+.thumb_set TIMER1_IRQHandler, Dummy_Handler
+
+.weak TIMER2_IRQHandler
+.thumb_set TIMER2_IRQHandler, Dummy_Handler
+
+.weak RTC0_IRQHandler
+.thumb_set RTC0_IRQHandler, Dummy_Handler
+
+.weak TEMP_IRQHandler
+.thumb_set TEMP_IRQHandler, Dummy_Handler
+
+.weak RNG_IRQHandler
+.thumb_set RNG_IRQHandler, Dummy_Handler
+
+.weak ECB_IRQHandler
+.thumb_set ECB_IRQHandler, Dummy_Handler
+
+.weak CCM_AAR_IRQHandler
+.thumb_set CCM_AAR_IRQHandler, Dummy_Handler
+
+.weak WDT_IRQHandler
+.thumb_set WDT_IRQHandler, Dummy_Handler
+
+.weak RTC1_IRQHandler
+.thumb_set RTC1_IRQHandler, Dummy_Handler
+
+.weak SWI0_EGU0_IRQHandler
+.thumb_set SWI0_EGU0_IRQHandler, Dummy_Handler
+
+.weak SWI1_EGU1_IRQHandler
+.thumb_set SWI1_EGU1_IRQHandler, Dummy_Handler
+
+.weak SWI2_IRQHandler
+.thumb_set SWI2_IRQHandler, Dummy_Handler
+
+.weak SWI3_IRQHandler
+.thumb_set SWI3_IRQHandler, Dummy_Handler
+
+.weak SWI4_IRQHandler
+.thumb_set SWI4_IRQHandler, Dummy_Handler
+
+.weak SWI5_IRQHandler
+.thumb_set SWI5_IRQHandler, Dummy_Handler
+
+/************************************************************************************
+ * Reset Handler Extensions *
+ ************************************************************************************/
+
+ .extern Reset_Handler
+ .global nRFInitialize
+ .extern afterInitialize
+
+ .thumb_func
+nRFInitialize:
+ b afterInitialize
+
+
+/************************************************************************************
+ * Vector Table *
+ ************************************************************************************/
+
+ .section .vectors, "ax"
+ .align 0
+ .global _vectors
+ .extern __stack_end__
+
+_vectors:
+ .word __stack_end__
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemoryManagement_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0 /*Reserved */
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+/* External Interrupts */
+ .word POWER_CLOCK_IRQHandler
+ .word RADIO_IRQHandler
+ .word UARTE0_UART0_IRQHandler
+ .word TWIM0_TWIS0_TWI0_IRQHandler
+ .word SPIM0_SPIS0_SPI0_IRQHandler
+ .word 0 /*Reserved */
+ .word GPIOTE_IRQHandler
+ .word SAADC_IRQHandler
+ .word TIMER0_IRQHandler
+ .word TIMER1_IRQHandler
+ .word TIMER2_IRQHandler
+ .word RTC0_IRQHandler
+ .word TEMP_IRQHandler
+ .word RNG_IRQHandler
+ .word ECB_IRQHandler
+ .word CCM_AAR_IRQHandler
+ .word WDT_IRQHandler
+ .word RTC1_IRQHandler
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word SWI0_EGU0_IRQHandler
+ .word SWI1_EGU1_IRQHandler
+ .word SWI2_IRQHandler
+ .word SWI3_IRQHandler
+ .word SWI4_IRQHandler
+ .word SWI5_IRQHandler
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+_vectors_end:
+
+#ifdef VECTORS_IN_RAM
+ .section .vectors_ram, "ax"
+ .align 0
+ .global _vectors_ram
+
+_vectors_ram:
+ .space _vectors_end - _vectors, 0
+#endif
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52810.s b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52810.s
index 1cac950be..60831afd3 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52810.s
+++ b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52810.s
@@ -202,10 +202,34 @@ Dummy_Handler:
.extern Reset_Handler
.global nRFInitialize
+ .extern afterInitialize
.thumb_func
nRFInitialize:
- bx lr
+ /* Workaround for Errata 185 RAM: RAM corruption at extreme corners
+ * found at the Errata document for your device located
+ * at https://infocenter.nordicsemi.com/index.jsp */
+
+ LDR R0, =0x10000130
+ LDR R0, [R0]
+ LDR R1, =0x10000134
+ LDR R1, [R1]
+
+ CMP R0, #0xA
+ BNE skip
+ CMP R1, #0x0
+ BNE skip
+
+ LDR R0, =0x40000EE4
+ LDR R2, [R0]
+ LDR R3, =0xFFFFFF8F
+ ANDS R2, R2, R3
+ LDR R3, =0x00000040
+ ORRS R2, R2, R3
+ STR R2, [R0]
+
+skip:
+ b afterInitialize
/************************************************************************************
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52811.s b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52811.s
index 966e74cc4..e4f92e813 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52811.s
+++ b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52811.s
@@ -202,10 +202,11 @@ Dummy_Handler:
.extern Reset_Handler
.global nRFInitialize
+ .extern afterInitialize
.thumb_func
nRFInitialize:
- bx lr
+ b afterInitialize
/************************************************************************************
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52833.s b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52833.s
new file mode 100644
index 000000000..1c1377ed2
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52833.s
@@ -0,0 +1,403 @@
+/***********************************************************************************
+ * SEGGER Microcontroller GmbH *
+ * The Embedded Experts *
+ ***********************************************************************************
+ * *
+ * (c) 2014 - 2018 SEGGER Microcontroller GmbH *
+ * *
+ * www.segger.com Support: support@segger.com *
+ * *
+ ***********************************************************************************
+ * *
+ * All rights reserved. *
+ * *
+ * Redistribution and use in source and binary forms, with or *
+ * without modification, are permitted provided that the following *
+ * conditions are met: *
+ * *
+ * - Redistributions of source code must retain the above copyright *
+ * notice, this list of conditions and the following disclaimer. *
+ * *
+ * - Neither the name of SEGGER Microcontroller GmbH *
+ * nor the names of its contributors may be used to endorse or *
+ * promote products derived from this software without specific *
+ * prior written permission. *
+ * *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
+ * DISCLAIMED. *
+ * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR *
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
+ * DAMAGE. *
+ * *
+ ***********************************************************************************/
+
+/************************************************************************************
+ * Preprocessor Definitions *
+ * ------------------------ *
+ * VECTORS_IN_RAM *
+ * *
+ * If defined, an area of RAM will large enough to store the vector table *
+ * will be reserved. *
+ * *
+ ************************************************************************************/
+
+ .syntax unified
+ .code 16
+
+ .section .init, "ax"
+ .align 0
+
+/************************************************************************************
+ * Default Exception Handlers *
+ ************************************************************************************/
+
+
+ .thumb_func
+ .weak NMI_Handler
+NMI_Handler:
+ b .
+
+ .thumb_func
+ .weak HardFault_Handler
+HardFault_Handler:
+ b .
+
+ .thumb_func
+ .weak MemoryManagement_Handler
+MemoryManagement_Handler:
+ b .
+
+ .thumb_func
+ .weak BusFault_Handler
+BusFault_Handler:
+ b .
+
+ .thumb_func
+ .weak UsageFault_Handler
+UsageFault_Handler:
+ b .
+
+ .thumb_func
+ .weak SVC_Handler
+SVC_Handler:
+ b .
+
+ .thumb_func
+ .weak DebugMon_Handler
+DebugMon_Handler:
+ b .
+
+ .thumb_func
+ .weak PendSV_Handler
+PendSV_Handler:
+ b .
+
+ .thumb_func
+ .weak SysTick_Handler
+SysTick_Handler:
+ b .
+
+ .thumb_func
+ .weak Dummy_Handler
+Dummy_Handler:
+ b .
+
+/************************************************************************************
+ * Default Interrupt Handlers *
+ ************************************************************************************/
+
+.weak POWER_CLOCK_IRQHandler
+.thumb_set POWER_CLOCK_IRQHandler, Dummy_Handler
+
+.weak RADIO_IRQHandler
+.thumb_set RADIO_IRQHandler, Dummy_Handler
+
+.weak UARTE0_UART0_IRQHandler
+.thumb_set UARTE0_UART0_IRQHandler, Dummy_Handler
+
+.weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+.thumb_set SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, Dummy_Handler
+
+.weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+.thumb_set SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, Dummy_Handler
+
+.weak NFCT_IRQHandler
+.thumb_set NFCT_IRQHandler, Dummy_Handler
+
+.weak GPIOTE_IRQHandler
+.thumb_set GPIOTE_IRQHandler, Dummy_Handler
+
+.weak SAADC_IRQHandler
+.thumb_set SAADC_IRQHandler, Dummy_Handler
+
+.weak TIMER0_IRQHandler
+.thumb_set TIMER0_IRQHandler, Dummy_Handler
+
+.weak TIMER1_IRQHandler
+.thumb_set TIMER1_IRQHandler, Dummy_Handler
+
+.weak TIMER2_IRQHandler
+.thumb_set TIMER2_IRQHandler, Dummy_Handler
+
+.weak RTC0_IRQHandler
+.thumb_set RTC0_IRQHandler, Dummy_Handler
+
+.weak TEMP_IRQHandler
+.thumb_set TEMP_IRQHandler, Dummy_Handler
+
+.weak RNG_IRQHandler
+.thumb_set RNG_IRQHandler, Dummy_Handler
+
+.weak ECB_IRQHandler
+.thumb_set ECB_IRQHandler, Dummy_Handler
+
+.weak CCM_AAR_IRQHandler
+.thumb_set CCM_AAR_IRQHandler, Dummy_Handler
+
+.weak WDT_IRQHandler
+.thumb_set WDT_IRQHandler, Dummy_Handler
+
+.weak RTC1_IRQHandler
+.thumb_set RTC1_IRQHandler, Dummy_Handler
+
+.weak QDEC_IRQHandler
+.thumb_set QDEC_IRQHandler, Dummy_Handler
+
+.weak COMP_LPCOMP_IRQHandler
+.thumb_set COMP_LPCOMP_IRQHandler, Dummy_Handler
+
+.weak SWI0_EGU0_IRQHandler
+.thumb_set SWI0_EGU0_IRQHandler, Dummy_Handler
+
+.weak SWI1_EGU1_IRQHandler
+.thumb_set SWI1_EGU1_IRQHandler, Dummy_Handler
+
+.weak SWI2_EGU2_IRQHandler
+.thumb_set SWI2_EGU2_IRQHandler, Dummy_Handler
+
+.weak SWI3_EGU3_IRQHandler
+.thumb_set SWI3_EGU3_IRQHandler, Dummy_Handler
+
+.weak SWI4_EGU4_IRQHandler
+.thumb_set SWI4_EGU4_IRQHandler, Dummy_Handler
+
+.weak SWI5_EGU5_IRQHandler
+.thumb_set SWI5_EGU5_IRQHandler, Dummy_Handler
+
+.weak TIMER3_IRQHandler
+.thumb_set TIMER3_IRQHandler, Dummy_Handler
+
+.weak TIMER4_IRQHandler
+.thumb_set TIMER4_IRQHandler, Dummy_Handler
+
+.weak PWM0_IRQHandler
+.thumb_set PWM0_IRQHandler, Dummy_Handler
+
+.weak PDM_IRQHandler
+.thumb_set PDM_IRQHandler, Dummy_Handler
+
+.weak MWU_IRQHandler
+.thumb_set MWU_IRQHandler, Dummy_Handler
+
+.weak PWM1_IRQHandler
+.thumb_set PWM1_IRQHandler, Dummy_Handler
+
+.weak PWM2_IRQHandler
+.thumb_set PWM2_IRQHandler, Dummy_Handler
+
+.weak SPIM2_SPIS2_SPI2_IRQHandler
+.thumb_set SPIM2_SPIS2_SPI2_IRQHandler, Dummy_Handler
+
+.weak RTC2_IRQHandler
+.thumb_set RTC2_IRQHandler, Dummy_Handler
+
+.weak I2S_IRQHandler
+.thumb_set I2S_IRQHandler, Dummy_Handler
+
+.weak FPU_IRQHandler
+.thumb_set FPU_IRQHandler, Dummy_Handler
+
+.weak USBD_IRQHandler
+.thumb_set USBD_IRQHandler, Dummy_Handler
+
+.weak UARTE1_IRQHandler
+.thumb_set UARTE1_IRQHandler, Dummy_Handler
+
+.weak PWM3_IRQHandler
+.thumb_set PWM3_IRQHandler, Dummy_Handler
+
+.weak SPIM3_IRQHandler
+.thumb_set SPIM3_IRQHandler, Dummy_Handler
+
+/************************************************************************************
+ * Reset Handler Extensions *
+ ************************************************************************************/
+
+ .extern Reset_Handler
+ .global nRFInitialize
+ .extern afterInitialize
+
+ .thumb_func
+nRFInitialize:
+ b afterInitialize
+
+
+/************************************************************************************
+ * Vector Table *
+ ************************************************************************************/
+
+ .section .vectors, "ax"
+ .align 0
+ .global _vectors
+ .extern __stack_end__
+
+_vectors:
+ .word __stack_end__
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemoryManagement_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0 /*Reserved */
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+/* External Interrupts */
+ .word POWER_CLOCK_IRQHandler
+ .word RADIO_IRQHandler
+ .word UARTE0_UART0_IRQHandler
+ .word SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ .word SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ .word NFCT_IRQHandler
+ .word GPIOTE_IRQHandler
+ .word SAADC_IRQHandler
+ .word TIMER0_IRQHandler
+ .word TIMER1_IRQHandler
+ .word TIMER2_IRQHandler
+ .word RTC0_IRQHandler
+ .word TEMP_IRQHandler
+ .word RNG_IRQHandler
+ .word ECB_IRQHandler
+ .word CCM_AAR_IRQHandler
+ .word WDT_IRQHandler
+ .word RTC1_IRQHandler
+ .word QDEC_IRQHandler
+ .word COMP_LPCOMP_IRQHandler
+ .word SWI0_EGU0_IRQHandler
+ .word SWI1_EGU1_IRQHandler
+ .word SWI2_EGU2_IRQHandler
+ .word SWI3_EGU3_IRQHandler
+ .word SWI4_EGU4_IRQHandler
+ .word SWI5_EGU5_IRQHandler
+ .word TIMER3_IRQHandler
+ .word TIMER4_IRQHandler
+ .word PWM0_IRQHandler
+ .word PDM_IRQHandler
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word MWU_IRQHandler
+ .word PWM1_IRQHandler
+ .word PWM2_IRQHandler
+ .word SPIM2_SPIS2_SPI2_IRQHandler
+ .word RTC2_IRQHandler
+ .word I2S_IRQHandler
+ .word FPU_IRQHandler
+ .word USBD_IRQHandler
+ .word UARTE1_IRQHandler
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word PWM3_IRQHandler
+ .word 0 /*Reserved */
+ .word SPIM3_IRQHandler
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+ .word 0 /*Reserved */
+_vectors_end:
+
+#ifdef VECTORS_IN_RAM
+ .section .vectors_ram, "ax"
+ .align 0
+ .global _vectors_ram
+
+_vectors_ram:
+ .space _vectors_end - _vectors, 0
+#endif
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52840.s b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52840.s
index d2af2bb86..e895995ba 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52840.s
+++ b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf52840.s
@@ -250,10 +250,11 @@ Dummy_Handler:
.extern Reset_Handler
.global nRFInitialize
+ .extern afterInitialize
.thumb_func
nRFInitialize:
- bx lr
+ b afterInitialize
/************************************************************************************
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf9160.s b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf9160.s
index 49c5f0740..84162ad43 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf9160.s
+++ b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf9160.s
@@ -219,10 +219,11 @@ Dummy_Handler:
.extern Reset_Handler
.global nRFInitialize
+ .extern afterInitialize
.thumb_func
nRFInitialize:
- bx lr
+ b afterInitialize
/************************************************************************************
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf_common.s b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf_common.s
index ac5e9852b..4be4828f9 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf_common.s
+++ b/third_party/NordicSemiconductor/nrfx/mdk/ses_startup_nrf_common.s
@@ -87,6 +87,7 @@
#endif
.extern _vectors
.extern nRFInitialize
+ .global afterInitialize
.section .init, "ax"
.thumb_func
@@ -101,8 +102,8 @@
Reset_Handler:
/* Perform prestart tasks. */
- ldr r0, =nRFInitialize
- blx r0
+ b nRFInitialize
+afterInitialize:
#ifndef NO_STACK_INIT
/* Initialise main stack */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf.h b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf.h
new file mode 100644
index 000000000..2e45b2da9
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf.h
@@ -0,0 +1,61 @@
+/*
+
+Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: Apache-2.0
+
+Licensed under the Apache License, Version 2.0 (the License); you may
+not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an AS IS BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+*/
+
+#ifndef SYSTEM_NRF_H
+#define SYSTEM_NRF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_NRF_H */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf51.c b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf51.c
index e31f2fe0f..5d48081b5 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf51.c
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf51.c
@@ -58,7 +58,7 @@ void SystemInit(void)
/* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
to enable the use of peripherals" found at Product Anomaly document for your device found at
- https://www.nordicsemi.com/DocLib The side effect of executing these instructions in the devices
+ https://infocenter.nordicsemi.com/index.jsp The side effect of executing these instructions in the devices
that do not need it is that the new peripherals in the second generation devices (LPCOMP for
example) will not be available. */
if (is_manual_peripheral_setup_needed())
@@ -69,7 +69,7 @@ void SystemInit(void)
/* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
register is incorrect" found at Product Anomaly document for your device found at
- https://www.nordicsemi.com/DocLib There is no side effect of using these instruction if not needed. */
+ https://infocenter.nordicsemi.com/index.jsp There is no side effect of using these instruction if not needed. */
if (is_disabled_in_debug_needed())
{
NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
@@ -77,7 +77,7 @@ void SystemInit(void)
/* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices,
as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
- for your device found at https://www.nordicsemi.com/DocLib */
+ for your device found at https://infocenter.nordicsemi.com/index.jsp */
if (is_peripheral_domain_setup_needed()){
if (*(uint32_t volatile *)0x4006EC00 != 1){
*(uint32_t volatile *)0x4006EC00 = 0x9375;
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf51.h b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf51.h
index 3227cafc8..48bd31725 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf51.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf51.h
@@ -1,22 +1,32 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
- SPDX-License-Identifier: Apache-2.0
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
-Licensed under the Apache License, Version 2.0 (the License); you may
-not use this file except in compliance with the License.
-You may obtain a copy of the License at
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
- www.apache.org/licenses/LICENSE-2.0
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an AS IS BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
-NOTICE: This file has been modified by Nordic Semiconductor ASA.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
*/
@@ -27,32 +37,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
extern "C" {
#endif
-#include
-
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
+#include "system_nrf.h"
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52.c b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52.c
index be6abbf2d..06997da29 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52.c
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52.c
@@ -81,31 +81,31 @@ void SystemInit(void)
#endif
/* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_12()){
*(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
}
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_16()){
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
}
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_31()){
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
}
/* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_32()){
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
}
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
@@ -113,13 +113,13 @@ void SystemInit(void)
}
/* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_37()){
*(volatile uint32_t *)0x400005A0 = 0x3;
}
/* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_57()){
*(volatile uint32_t *)0x40005610 = 0x00000005;
*(volatile uint32_t *)0x40005688 = 0x00000001;
@@ -128,7 +128,7 @@ void SystemInit(void)
}
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_66()){
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
@@ -150,13 +150,13 @@ void SystemInit(void)
}
/* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_108()){
- *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F;
+ *(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
}
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_136()){
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
@@ -164,7 +164,7 @@ void SystemInit(void)
}
/* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_182()){
*(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
}
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52.h b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52.h
index d05316c1d..d35bd3c0c 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52.h
@@ -1,22 +1,32 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
- SPDX-License-Identifier: Apache-2.0
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
-Licensed under the Apache License, Version 2.0 (the License); you may
-not use this file except in compliance with the License.
-You may obtain a copy of the License at
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
- www.apache.org/licenses/LICENSE-2.0
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an AS IS BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
-NOTICE: This file has been modified by Nordic Semiconductor ASA.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
*/
@@ -27,32 +37,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
extern "C" {
#endif
-#include
-
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
+#include "system_nrf.h"
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52805.c b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52805.c
new file mode 100644
index 000000000..9a8751b65
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52805.c
@@ -0,0 +1,191 @@
+/*
+
+Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: Apache-2.0
+
+Licensed under the Apache License, Version 2.0 (the License); you may
+not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an AS IS BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+*/
+
+/* NOTE: Template files (including this one) are application specific and therefore expected to
+ be copied into the application project folder prior to its use! */
+
+#include
+#include
+#include "nrf.h"
+#include "system_nrf52805.h"
+
+/*lint ++flb "Enter library region" */
+
+#define __SYSTEM_CLOCK_64M (64000000UL)
+
+static bool errata_31(void);
+static bool errata_36(void);
+static bool errata_66(void);
+static bool errata_136(void);
+static bool errata_217(void);
+
+#if defined ( __CC_ARM )
+ uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#elif defined ( __ICCARM__ )
+ __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
+#elif defined ( __GNUC__ )
+ uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+ SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+void SystemInit(void)
+{
+ /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_31()){
+ *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
+ }
+
+ /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_36()){
+ NRF_CLOCK->EVENTS_DONE = 0;
+ NRF_CLOCK->EVENTS_CTTO = 0;
+ NRF_CLOCK->CTIV = 0;
+ }
+
+ /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_66()){
+ NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
+ NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
+ NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
+ NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
+ NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
+ NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
+ NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
+ NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
+ NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
+ NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
+ NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
+ NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
+ NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
+ NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
+ NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
+ NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
+ NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
+ }
+
+ /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_136()){
+ if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
+ NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
+ }
+ }
+
+ /* Workaround for Errata 217 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_217()){
+ *(volatile uint32_t *)0x40000EE4ul |= 0x0000000Ful;
+ }
+
+ /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+ defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+ reserved for PinReset and not available as normal GPIO. */
+ #if defined (CONFIG_GPIO_AS_PINRESET)
+
+ #define RESET_PIN 21
+
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[0] = RESET_PIN;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[1] = RESET_PIN;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NVIC_SystemReset();
+ }
+ #endif
+
+ SystemCoreClockUpdate();
+}
+
+static bool errata_31(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xFul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_36(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xFul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_66(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xFul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_136(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xFul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+static bool errata_217(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xFul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
+
+/*lint --flb "Leave library region" */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/startup_config.h b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52805.h
similarity index 55%
rename from third_party/NordicSemiconductor/nrfx/mdk/startup_config.h
rename to third_party/NordicSemiconductor/nrfx/mdk/system_nrf52805.h
index b9e9ae39c..e0c2977c9 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/startup_config.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52805.h
@@ -30,22 +30,17 @@ POSSIBILITY OF SUCH DAMAGE.
*/
-/* Configure stack size, stack alignement and heap size with a header file instead of project settings or modification of Nordic provided assembler files. Modify this file as needed. */
+#ifndef SYSTEM_NRF52805_H
+#define SYSTEM_NRF52805_H
-/* In order to make use this file,
- 1. For Keil uVision IDE, in the Options for Target -> Asm tab, define symbol __STARTUP_CONFIG and use the additional assembler option --cpreproc in Misc Control text box.
- 2. For GCC compiling, add extra assembly option -D__STARTUP_CONFIG.
- 3. For IAR Embedded Workbench define symbol __STARTUP_CONFIG in the Assembler options and define symbol __STARTUP_CONFIG=1 in the linker options.
-*/
+#ifdef __cplusplus
+extern "C" {
+#endif
-/* This file is a template and should be copied to the project directory. */
+#include "system_nrf.h"
-/* Define size of stack. Size must be multiple of 4. */
-#define __STARTUP_CONFIG_STACK_SIZE 0x1000
-
-/* Define alignement of stack. Alignment will be 2 to the power of __STARTUP_CONFIG_STACK_ALIGNEMENT. Since calling convention requires that the stack is aligned to 8-bytes when a function is called, the minimum __STARTUP_CONFIG_STACK_ALIGNEMENT is therefore 3. */
-#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
-
-/* Define size of heap. Size must be multiple of 4. */
-#define __STARTUP_CONFIG_HEAP_SIZE 0x1000
+#ifdef __cplusplus
+}
+#endif
+#endif /* SYSTEM_NRF52805_H */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52810.c b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52810.c
index 26ef79b7d..ac04dbe91 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52810.c
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52810.c
@@ -37,6 +37,7 @@ static bool errata_36(void);
static bool errata_66(void);
static bool errata_103(void);
static bool errata_136(void);
+static bool errata_217(void);
/* Helper functions for Errata workarounds in nRF52832 */
#if defined (DEVELOP_IN_NRF52832)
@@ -86,7 +87,7 @@ void SystemInit(void)
#if defined (DEVELOP_IN_NRF52832)
/* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
- for nRF52832 device located at https://www.nordicsemi.com/DocLib */
+ for nRF52832 device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_12()){
*(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
}
@@ -94,28 +95,28 @@ void SystemInit(void)
#if defined (DEVELOP_IN_NRF52832)
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
- for nRF52832 device located at https://www.nordicsemi.com/DocLib */
+ for nRF52832 device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_16()){
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
}
#endif
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_31()){
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
}
#if defined (DEVELOP_IN_NRF52832)
/* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
- for nRF52832 device located at https://www.nordicsemi.com/DocLib */
+ for nRF52832 device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_32()){
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
}
#endif
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
@@ -124,7 +125,7 @@ void SystemInit(void)
#if defined (DEVELOP_IN_NRF52832)
/* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_37()){
*(volatile uint32_t *)0x400005A0 = 0x3;
}
@@ -132,7 +133,7 @@ void SystemInit(void)
#if defined (DEVELOP_IN_NRF52832)
/* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_57()){
*(volatile uint32_t *)0x40005610 = 0x00000005;
*(volatile uint32_t *)0x40005688 = 0x00000001;
@@ -142,7 +143,7 @@ void SystemInit(void)
#endif
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_66()){
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
@@ -164,21 +165,21 @@ void SystemInit(void)
}
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_103()){
NRF_CCM->MAXPACKETSIZE = 0xFBul;
}
-
+
#if defined (DEVELOP_IN_NRF52832)
/* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_108()){
- *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F;
+ *(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
}
#endif
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_136()){
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
@@ -187,12 +188,18 @@ void SystemInit(void)
#if defined (DEVELOP_IN_NRF52832)
/* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_182()){
*(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
}
#endif
+ /* Workaround for Errata 217 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_217()){
+ *(volatile uint32_t *)0x40000EE4ul |= 0x0000000Ful;
+ }
+
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
@@ -248,10 +255,15 @@ static bool errata_16(void)
static bool errata_31(void)
{
- if ((*(uint32_t *)0x10000130ul == 0xAul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
- return true;
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
}
-
+
#if defined (DEVELOP_IN_NRF52832)
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
@@ -263,10 +275,11 @@ static bool errata_31(void)
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
+ return false;
}
#endif
- /* Fix should always apply. */
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
return true;
}
@@ -285,10 +298,15 @@ static bool errata_32(void)
static bool errata_36(void)
{
- if ((*(uint32_t *)0x10000130ul == 0xAul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
- return true;
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
}
-
+
#if defined (DEVELOP_IN_NRF52832)
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
@@ -300,10 +318,12 @@ static bool errata_36(void)
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
+ return false;
}
+
#endif
- /* Fix should always apply. */
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
return true;
}
@@ -335,30 +355,37 @@ static bool errata_57(void)
static bool errata_66(void)
{
- if ((*(uint32_t *)0x10000130ul == 0xAul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
- return true;
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
}
-
+
#if defined (DEVELOP_IN_NRF52832)
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
+ return false;
}
#endif
- /* Fix should always apply. */
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
return true;
}
static bool errata_103(void)
{
- if ((*(uint32_t *)0x10000130ul == 0xAul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
- return true;
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
}
- /* Fix should always apply. */
- return true;
+ return false;
}
#if defined (DEVELOP_IN_NRF52832)
@@ -382,10 +409,15 @@ static bool errata_108(void)
static bool errata_136(void)
{
- if ((*(uint32_t *)0x10000130ul == 0xAul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
- return true;
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
}
-
+
#if defined (DEVELOP_IN_NRF52832)
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){
@@ -397,10 +429,11 @@ static bool errata_136(void)
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){
return true;
}
+ return false;
}
#endif
- /* Fix should always apply. */
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
return true;
}
@@ -417,5 +450,20 @@ static bool errata_182(void)
}
#endif
+static bool errata_217(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xAul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return false;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
+
/*lint --flb "Leave library region" */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52810.h b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52810.h
index e395ee996..e2819fad2 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52810.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52810.h
@@ -1,22 +1,32 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
- SPDX-License-Identifier: Apache-2.0
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
-Licensed under the Apache License, Version 2.0 (the License); you may
-not use this file except in compliance with the License.
-You may obtain a copy of the License at
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
- www.apache.org/licenses/LICENSE-2.0
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an AS IS BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
-NOTICE: This file has been modified by Nordic Semiconductor ASA.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
*/
@@ -27,32 +37,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
extern "C" {
#endif
-#include
-
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
+#include "system_nrf.h"
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52811.c b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52811.c
index ddf76ed43..6fe44aa50 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52811.c
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52811.c
@@ -36,7 +36,13 @@ static bool errata_31(void);
static bool errata_36(void);
static bool errata_66(void);
static bool errata_136(void);
+static bool errata_217(void);
+/* nRF52840 erratas */
+#ifdef DEVELOP_IN_NRF52840
+ static bool errata_103(void);
+ static bool errata_115(void);
+#endif
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
@@ -54,13 +60,13 @@ void SystemCoreClockUpdate(void)
void SystemInit(void)
{
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_31()){
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
}
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
@@ -68,7 +74,7 @@ void SystemInit(void)
}
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_66()){
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
@@ -88,26 +94,54 @@ void SystemInit(void)
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
}
+
+ #ifdef DEVELOP_IN_NRF52840
+
+ /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_103()){
+ NRF_CCM->MAXPACKETSIZE = 0xFBul;
+ }
+
+ /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_115()){
+ *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
+ }
+ #endif
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_136()){
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
}
}
+
+ /* Workaround for Errata 217 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_217()){
+ *(volatile uint32_t *)0x40000EE4ul |= 0x0000000Ful;
+ }
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
+
+ #ifdef DEVELOP_IN_NRF52840
+ #define RESET_PIN 18
+ #else
+ #define RESET_PIN 21
+ #endif
+
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NRF_UICR->PSELRESET[0] = 21;
+ NRF_UICR->PSELRESET[0] = RESET_PIN;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
- NRF_UICR->PSELRESET[1] = 21;
+ NRF_UICR->PSELRESET[1] = RESET_PIN;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@@ -120,49 +154,140 @@ void SystemInit(void)
static bool errata_31(void)
{
- #if !defined (DISABLE_WORKAROUND_31)
- if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
- return true;
+ if (*(uint32_t *)0x10000130ul == 0xEul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
}
- #endif
-
- return false;
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
}
static bool errata_36(void)
{
- #if !defined (DISABLE_WORKAROUND_36)
- if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
- return true;
+ if (*(uint32_t *)0x10000130ul == 0xEul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
}
+
+ #ifdef DEVELOP_IN_NRF52840
+ if (*(uint32_t *)0x10000130ul == 0x8ul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x2ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x3ul){
+ return true;
+ }
+ }
#endif
-
- return false;
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
}
static bool errata_66(void)
{
- #if !defined (DISABLE_WORKAROUND_66)
- if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
- return true;
+ if (*(uint32_t *)0x10000130ul == 0xEul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
}
+
+ #ifdef DEVELOP_IN_NRF52840
+ if (*(uint32_t *)0x10000130ul == 0x8ul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x2ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x3ul){
+ return true;
+ }
+ }
#endif
-
- return false;
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
}
static bool errata_136(void)
{
- #if !defined (DISABLE_WORKAROUND_136)
- if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
- return true;
+ if (*(uint32_t *)0x10000130ul == 0xEul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
}
+
+ #ifdef DEVELOP_IN_NRF52840
+ if (*(uint32_t *)0x10000130ul == 0x8ul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x1ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x2ul){
+ return true;
+ }
+ if (*(uint32_t *)0x10000134ul == 0x3ul){
+ return true;
+ }
+ }
#endif
-
- return false;
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
}
+#ifdef DEVELOP_IN_NRF52840
+ static bool errata_103(void)
+ {
+ if (*(uint32_t *)0x10000130ul == 0x8ul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ return false;
+ }
+
+
+ static bool errata_115(void)
+ {
+ if (*(uint32_t *)0x10000130ul == 0x8ul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ return false;
+ }
+#endif
+
+static bool errata_217(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xEul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
+ return true;
+}
/*lint --flb "Leave library region" */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52811.h b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52811.h
index 20d87694b..ad8bb2f57 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52811.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52811.h
@@ -1,22 +1,32 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
- SPDX-License-Identifier: Apache-2.0
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
-Licensed under the Apache License, Version 2.0 (the License); you may
-not use this file except in compliance with the License.
-You may obtain a copy of the License at
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
- www.apache.org/licenses/LICENSE-2.0
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an AS IS BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
-NOTICE: This file has been modified by Nordic Semiconductor ASA.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
*/
@@ -27,32 +37,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
extern "C" {
#endif
-#include
-
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
+#include "system_nrf.h"
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52833.c b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52833.c
new file mode 100644
index 000000000..60a613327
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52833.c
@@ -0,0 +1,191 @@
+/*
+
+Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: Apache-2.0
+
+Licensed under the Apache License, Version 2.0 (the License); you may
+not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an AS IS BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+*/
+
+/* NOTE: Template files (including this one) are application specific and therefore expected to
+ be copied into the application project folder prior to its use! */
+
+#include
+#include
+#include "nrf.h"
+#include "system_nrf52833.h"
+
+/*lint ++flb "Enter library region" */
+
+#define __SYSTEM_CLOCK_64M (64000000UL)
+
+static bool errata_36(void);
+static bool errata_66(void);
+static bool errata_136(void);
+
+#if defined ( __CC_ARM )
+ uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#elif defined ( __ICCARM__ )
+ __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
+#elif defined ( __GNUC__ )
+ uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+ SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+void SystemInit(void)
+{
+ /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+ Specification to see which one). */
+ #if defined (ENABLE_SWO)
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+ NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ #endif
+
+ /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+ Specification to see which ones). */
+ #if defined (ENABLE_TRACE)
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+ NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ #endif
+
+ /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_36()){
+ NRF_CLOCK->EVENTS_DONE = 0;
+ NRF_CLOCK->EVENTS_CTTO = 0;
+ NRF_CLOCK->CTIV = 0;
+ }
+
+ /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_66()){
+ NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
+ NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
+ NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
+ NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
+ NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
+ NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
+ NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
+ NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
+ NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
+ NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
+ NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
+ NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
+ NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
+ NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
+ NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
+ NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
+ NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
+ }
+
+ /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_136()){
+ if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
+ NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
+ }
+ }
+
+ /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+ * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+ * operations are not used in your code. */
+ #if (__FPU_USED == 1)
+ SCB->CPACR |= (3UL << 20) | (3UL << 22);
+ __DSB();
+ __ISB();
+ #endif
+
+ /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+ two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+ normal GPIOs. */
+ #if defined (CONFIG_NFCT_PINS_AS_GPIOS)
+ if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NVIC_SystemReset();
+ }
+ #endif
+
+ /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+ defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+ reserved for PinReset and not available as normal GPIO. */
+ #if defined (CONFIG_GPIO_AS_PINRESET)
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[0] = 18;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[1] = 18;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NVIC_SystemReset();
+ }
+ #endif
+
+ SystemCoreClockUpdate();
+}
+
+static bool errata_36(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xDul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ return false;
+}
+
+
+static bool errata_66(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xDul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static bool errata_136(void)
+{
+ if (*(uint32_t *)0x10000130ul == 0xDul){
+ if (*(uint32_t *)0x10000134ul == 0x0ul){
+ return true;
+ }
+ }
+
+ return false;
+}
+
+/*lint --flb "Leave library region" */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52833.h b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52833.h
new file mode 100644
index 000000000..927a039f8
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52833.h
@@ -0,0 +1,46 @@
+/*
+
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef SYSTEM_NRF52833_H
+#define SYSTEM_NRF52833_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "system_nrf.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_NRF52833_H */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.c b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.c
index bd84aa20e..1d177d62f 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.c
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.c
@@ -77,7 +77,7 @@ void SystemInit(void)
#endif
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
@@ -85,7 +85,7 @@ void SystemInit(void)
}
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_66()){
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
@@ -107,31 +107,31 @@ void SystemInit(void)
}
/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_98()){
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
}
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_103()){
NRF_CCM->MAXPACKETSIZE = 0xFBul;
}
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_115()){
- *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
+ *(volatile uint32_t *)0x40000EE4ul = (*(volatile uint32_t *)0x40000EE4ul & 0xFFFFFFF0ul) | (*(uint32_t *)0x10000258ul & 0x0000000Ful);
}
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_120()){
*(volatile uint32_t *)0x40029640ul = 0x200ul;
}
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (errata_136()){
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
@@ -200,7 +200,8 @@ static bool errata_36(void)
return true;
}
}
-
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
return true;
}
@@ -221,7 +222,8 @@ static bool errata_66(void)
return true;
}
}
-
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
return true;
}
@@ -290,7 +292,8 @@ static bool errata_136(void)
return true;
}
}
-
+
+ /* Apply by default for unknown devices until errata is confirmed fixed. */
return true;
}
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.h b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.h
index 28b3151bf..169b2ef7f 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf52840.h
@@ -1,22 +1,32 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
- SPDX-License-Identifier: Apache-2.0
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
-Licensed under the Apache License, Version 2.0 (the License); you may
-not use this file except in compliance with the License.
-You may obtain a copy of the License at
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
- www.apache.org/licenses/LICENSE-2.0
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an AS IS BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
-NOTICE: This file has been modified by Nordic Semiconductor ASA.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
*/
@@ -27,32 +37,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
extern "C" {
#endif
-#include
-
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
+#include "system_nrf.h"
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf9160.c b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf9160.c
index 70e35ecfc..cf3f4996c 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf9160.c
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf9160.c
@@ -33,6 +33,16 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
#define __SYSTEM_CLOCK (64000000UL) /*!< nRF9160 Application core uses a fixed System Clock Frequency of 64MHz */
+#define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \
+ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \
+ (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \
+ (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \
+ (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) )
+#define TRACE_TRACECLK_PIN (21)
+#define TRACE_TRACEDATA0_PIN (22)
+#define TRACE_TRACEDATA1_PIN (23)
+#define TRACE_TRACEDATA2_PIN (24)
+#define TRACE_TRACEDATA3_PIN (25)
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
@@ -42,6 +52,13 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
#endif
+/* Global values used used in Secure mode SystemInit. */
+#if !defined(NRF_TRUSTZONE_NONSECURE)
+ /* Global values used by UICR erase fix algorithm. */
+ static uint32_t uicr_erased_value;
+ static uint32_t uicr_new_value;
+#endif
+
/* Errata are only handled in secure mode since they usually need access to FICR. */
#if !defined(NRF_TRUSTZONE_NONSECURE)
static bool uicr_HFXOSRC_erased(void);
@@ -49,6 +66,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
static bool errata_6(void);
static bool errata_14(void);
static bool errata_15(void);
+ static bool errata_20(void);
#endif
void SystemCoreClockUpdate(void)
@@ -66,8 +84,34 @@ void SystemInit(void)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
#endif
+
+ /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_6()){
+ NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos);
+ NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos);
+ }
- /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
+ /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_14()){
+ *((volatile uint32_t *)0x50004A38) = 0x01ul;
+ NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
+ }
+
+ /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_15()){
+ NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
+ }
+
+ /* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/index.jsp */
+ if (errata_20()){
+ *((volatile uint32_t *)0x5003AEE4) = 0xE;
+ }
+
+ /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
until one ADDR is not initialized. */
uint32_t index = 0;
for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
@@ -79,56 +123,96 @@ void SystemInit(void)
#pragma diag_default=Pa082
#endif
}
-
+
/* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */
if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) {
/* Wait for pending NVMC operations to finish */
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
-
+
/* Enable write mode in NVMC */
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen;
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
-
+
if (uicr_HFXOSRC_erased()){
/* Write default value to UICR->HFXOSRC */
- NRF_UICR_S->HFXOSRC = (NRF_UICR_S->HFXOSRC & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO;
+ uicr_erased_value = NRF_UICR_S->HFXOSRC;
+ uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO;
+ NRF_UICR_S->HFXOSRC = uicr_new_value;
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
}
-
+
if (uicr_HFXOCNT_erased()){
/* Write default value to UICR->HFXOCNT */
- NRF_UICR_S->HFXOCNT = (NRF_UICR_S->HFXOCNT & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20;
+ uicr_erased_value = NRF_UICR_S->HFXOCNT;
+ uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20;
+ NRF_UICR_S->HFXOCNT = uicr_new_value;
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
}
-
+
/* Enable read mode in NVMC */
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
-
+
/* Reset to apply clock select update */
NVIC_SystemReset();
}
-
- /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
- if (errata_6()){
- NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos);
- NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos);
- }
-
- /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
- if (errata_14()){
- *(uint32_t *)0x50004A38 = 0x01ul;
- NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
- }
- /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document
- for your device located at https://www.nordicsemi.com/DocLib */
- if (errata_15()){
- *(uint32_t *)0x50004A38 = 0x00ul;
- NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
- }
+ /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+ Specification to see which ones). */
+ #if defined (ENABLE_TRACE)
+ // Enable Trace And Debug peripheral
+ NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
+ NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk;
+
+ // Set up Trace pads SPU firewall
+ NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN);
+ NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN);
+ NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN);
+ NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN);
+ NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN);
+
+ // Configure trace port pads
+ NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE;
+ NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE;
+ NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE;
+ NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE;
+ NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE;
+
+ // Select trace pins
+ NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN;
+ NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN;
+ NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN;
+ NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN;
+ NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN;
+
+ // Set trace port speed to 32 MHz
+ NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz;
+
+ *((uint32_t *)(0xE0053000ul)) = 0x00000001ul;
+
+ *((uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul;
+ *((uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul;
+ *((uint32_t *)(0xE005A004ul)) = 0x00000009ul;
+ *((uint32_t *)(0xE005A000ul)) = 0x00000303ul;
+ *((uint32_t *)(0xE005AFB0ul)) = 0x00000000ul;
+
+ *((uint32_t *)(0xE005BFB0ul)) = 0xC5ACCE55ul;
+ *((uint32_t *)(0xE005B000ul)) &= 0xFFFFFF00ul;
+ *((uint32_t *)(0xE005B004ul)) = 0x00003000ul;
+ *((uint32_t *)(0xE005B000ul)) = 0x00000308ul;
+ *((uint32_t *)(0xE005BFB0ul)) = 0x00000000ul;
+
+ *((uint32_t *)(0xE0058FB0ul)) = 0xC5ACCE55ul;
+ *((uint32_t *)(0xE0058000ul)) = 0x00000000ul;
+ *((uint32_t *)(0xE0058004ul)) = 0x00000000ul;
+ *((uint32_t *)(0xE0058FB0ul)) = 0x00000000ul;
+
+ /* Rom table does not list ETB, or TPIU base addresses.
+ * Some debug probes may require manual configuration of these peripherals to enable tracing.
+ * ETB_BASE = 0xE0051000
+ * TPIU_BASE = 0xE0054000
+ */
+ #endif
/* Allow Non-Secure code to run FPU instructions.
* If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
@@ -205,6 +289,16 @@ void SystemInit(void)
return false;
}
+
+
+ bool errata_20()
+ {
+ if (((*(uint32_t *)0x00FF0004) & 0x1E) != 0x1C){
+ return true;
+ }
+
+ return false;
+ }
#endif
/*lint --flb "Leave library region" */
diff --git a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf9160.h b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf9160.h
index 2de688e93..6b3e1cbbe 100644
--- a/third_party/NordicSemiconductor/nrfx/mdk/system_nrf9160.h
+++ b/third_party/NordicSemiconductor/nrfx/mdk/system_nrf9160.h
@@ -1,22 +1,32 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
- SPDX-License-Identifier: Apache-2.0
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
-Licensed under the Apache License, Version 2.0 (the License); you may
-not use this file except in compliance with the License.
-You may obtain a copy of the License at
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
- www.apache.org/licenses/LICENSE-2.0
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an AS IS BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
-NOTICE: This file has been modified by Nordic Semiconductor ASA.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
*/
@@ -27,32 +37,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
extern "C" {
#endif
-#include
-
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
+#include "system_nrf.h"
#ifdef __cplusplus
}
diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_atomic.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_atomic.h
index c01d041e6..6cf6c0b9b 100644
--- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_atomic.h
+++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_atomic.h
@@ -50,21 +50,17 @@ extern "C" {
*/
-/**
- * @brief Atomic 32-bit unsigned type.
- */
+/** @brief Atomic 32-bit unsigned type. */
typedef volatile uint32_t nrfx_atomic_u32_t;
-/**
- * @brief Atomic 1-bit flag type (technically 32-bit).
- */
+/** @brief Atomic 1-bit flag type (technically 32-bit). */
typedef volatile uint32_t nrfx_atomic_flag_t;
/**
* @brief Function for storing a value to an atomic object and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value to store.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value to store.
*
* @return Previous value stored in the atomic object.
*/
@@ -73,8 +69,8 @@ uint32_t nrfx_atomic_u32_fetch_store(nrfx_atomic_u32_t * p_data, uint32_t value)
/**
* @brief Function for storing a value to an atomic object and returning its new value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value to store.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value to store.
*
* @return New value stored in the atomic object.
*/
@@ -84,8 +80,8 @@ uint32_t nrfx_atomic_u32_store(nrfx_atomic_u32_t * p_data, uint32_t value);
* @brief Function for running a logical OR operation on an atomic object
* and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the OR operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the OR operation.
*
* @return Previous value stored in the atomic object.
*/
@@ -95,8 +91,8 @@ uint32_t nrfx_atomic_u32_fetch_or(nrfx_atomic_u32_t * p_data, uint32_t value);
* @brief Function for running a logical OR operation on an atomic object
* and returning its new value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the OR operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the OR operation.
*
* @return New value stored in the atomic object.
*/
@@ -106,8 +102,8 @@ uint32_t nrfx_atomic_u32_or(nrfx_atomic_u32_t * p_data, uint32_t value);
* @brief Function for running a logical AND operation on an atomic object
* and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the AND operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the AND operation.
*
* @return Previous value stored in the atomic object.
*/
@@ -117,8 +113,8 @@ uint32_t nrfx_atomic_u32_fetch_and(nrfx_atomic_u32_t * p_data, uint32_t value);
* @brief Function for running a logical AND operation on an atomic object
* and returning its new value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the AND operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the AND operation.
*
* @return New value stored in the atomic object.
*/
@@ -128,8 +124,8 @@ uint32_t nrfx_atomic_u32_and(nrfx_atomic_u32_t * p_data, uint32_t value);
* @brief Function for running a logical XOR operation on an atomic object
* and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the XOR operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the XOR operation.
*
* @return Previous value stored in the atomic object.
*/
@@ -139,8 +135,8 @@ uint32_t nrfx_atomic_u32_fetch_xor(nrfx_atomic_u32_t * p_data, uint32_t value);
* @brief Function for running a logical XOR operation on an atomic object
* and returning its new value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the XOR operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the XOR operation.
*
* @return New value stored in the atomic object.
*/
@@ -150,8 +146,8 @@ uint32_t nrfx_atomic_u32_xor(nrfx_atomic_u32_t * p_data, uint32_t value);
* @brief Function for running an arithmetic ADD operation on an atomic object
* and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the ADD operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the ADD operation.
*
* @return Previous value stored in the atomic object.
*/
@@ -161,8 +157,8 @@ uint32_t nrfx_atomic_u32_fetch_add(nrfx_atomic_u32_t * p_data, uint32_t value);
* @brief Function for running an arithmetic ADD operation on an atomic object
* and returning its new value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the ADD operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the ADD operation.
*
* @return New value stored in the atomic object.
*/
@@ -172,19 +168,19 @@ uint32_t nrfx_atomic_u32_add(nrfx_atomic_u32_t * p_data, uint32_t value);
* @brief Function for running an arithmetic SUB operation on an atomic object
* and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the SUB operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the SUB operation.
*
* @return Old value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_fetch_sub(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
- * @brief Function for running an arithmetic SUB operation on an atomic object
+ * @brief Function for running an arithmetic SUB operation on an atomic object
* and returning its new value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the SUB operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the SUB operation.
*
* @return New value stored in the atomic object.
*/
@@ -211,60 +207,60 @@ bool nrfx_atomic_u32_cmp_exch(nrfx_atomic_u32_t * p_data,
/**
* @brief Function for running an arithmetic SUB operation on an atomic object
* if object >= value, and returning its previous value.
- *
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the SUB operation.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the SUB operation.
*
* @return Previous value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_fetch_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
- * @brief Function for running an arithmetic SUB operation on an atomic object
+ * @brief Function for running an arithmetic SUB operation on an atomic object
* if object >= value, and returning its new value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the SUB operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the SUB operation.
*
* @return New value stored in the atomic object.
*/
uint32_t nrfx_atomic_u32_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value);
/**
- * @brief Function for running a logical one bit flag set operation
+ * @brief Function for running a logical one bit flag set operation
* on an atomic object and returning its previous value.
*
- * @param[in] p_data Atomic flag memory pointer.
+ * @param[in] p_data Atomic flag memory pointer.
*
* @return Previous flag value.
*/
uint32_t nrfx_atomic_flag_set_fetch(nrfx_atomic_flag_t * p_data);
/**
- * @brief Function for running a logical one bit flag set operation
+ * @brief Function for running a logical one bit flag set operation
* on an atomic object and returning its new value.
*
- * @param[in] p_data Atomic flag memory pointer.
+ * @param[in] p_data Atomic flag memory pointer.
*
* @return New flag value.
*/
uint32_t nrfx_atomic_flag_set(nrfx_atomic_flag_t * p_data);
/**
- * @brief Function for running a logical one bit flag clear operation
+ * @brief Function for running a logical one bit flag clear operation
* on an atomic object and returning its previous value.
*
- * @param[in] p_data Atomic flag memory pointer.
+ * @param[in] p_data Atomic flag memory pointer.
*
* @return Previous flag value.
*/
uint32_t nrfx_atomic_flag_clear_fetch(nrfx_atomic_flag_t * p_data);
/**
- * @brief Function for running a logical one bit flag clear operation
+ * @brief Function for running a logical one bit flag clear operation
* on an atomic object and returning its new value.
*
- * @param[in] p_data Atomic flag memory pointer.
+ * @param[in] p_data Atomic flag memory pointer.
*
* @return New flag value.
*/
diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_atomic_internal.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_atomic_internal.h
index eedec48bb..c94e7a049 100644
--- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_atomic_internal.h
+++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_atomic_internal.h
@@ -45,12 +45,13 @@ extern "C" {
#if defined ( __CC_ARM )
static __asm uint32_t nrfx_atomic_internal_mov(nrfx_atomic_u32_t * p_ptr,
- uint32_t value,
- uint32_t * p_new)
+ uint32_t value,
+ uint32_t * p_new)
{
- /* The base standard specifies that arguments are passed in core registers r0-r3 and on the stack.
- * Registers r4 and r5 must be saved on the stack. Note that only even number of register pushes are
- * allowed. This is a requirement of the Procedure Call Standard for the ARM Architecture [AAPCS].
+ /* The base standard specifies that arguments are passed in the core registers
+ * r0-r3 and on the stack. Registers r4 and r5 must be saved on the stack.
+ * Only even number of register pushes are allowed. This is a requirement
+ * of the Procedure Call Standard for the ARM Architecture [AAPCS].
*/
push {r4, r5}
mov r4, r0
@@ -69,8 +70,8 @@ loop_mov
static __asm uint32_t nrfx_atomic_internal_orr(nrfx_atomic_u32_t * p_ptr,
- uint32_t value,
- uint32_t * p_new)
+ uint32_t value,
+ uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
@@ -88,8 +89,8 @@ loop_orr
}
static __asm uint32_t nrfx_atomic_internal_and(nrfx_atomic_u32_t * p_ptr,
- uint32_t value,
- uint32_t * p_new)
+ uint32_t value,
+ uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
@@ -107,8 +108,8 @@ loop_and
}
static __asm uint32_t nrfx_atomic_internal_eor(nrfx_atomic_u32_t * p_ptr,
- uint32_t value,
- uint32_t * p_new)
+ uint32_t value,
+ uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
@@ -126,8 +127,8 @@ loop_eor
}
static __asm uint32_t nrfx_atomic_internal_add(nrfx_atomic_u32_t * p_ptr,
- uint32_t value,
- uint32_t * p_new)
+ uint32_t value,
+ uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
@@ -145,8 +146,8 @@ loop_add
}
static __asm uint32_t nrfx_atomic_internal_sub(nrfx_atomic_u32_t * p_ptr,
- uint32_t value,
- uint32_t * p_new)
+ uint32_t value,
+ uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
@@ -164,8 +165,8 @@ loop_sub
}
static __asm bool nrfx_atomic_internal_cmp_exch(nrfx_atomic_u32_t * p_data,
- uint32_t * p_expected,
- uint32_t value)
+ uint32_t * p_expected,
+ uint32_t value)
{
#define RET_REG r0
#define P_EXPC r1
@@ -206,8 +207,8 @@ loop_cmp_exch
}
static __asm uint32_t nrfx_atomic_internal_sub_hs(nrfx_atomic_u32_t * p_ptr,
- uint32_t value,
- uint32_t * p_new)
+ uint32_t value,
+ uint32_t * p_new)
{
push {r4, r5}
mov r4, r0
@@ -236,10 +237,10 @@ loop_sub_ge
/**
* @brief Atomic operation generic macro.
*
- * @param[in] asm_op Operation: mov, orr, and, eor, add, sub.
- * @param[out] old_val Atomic object output (uint32_t), value before operation.
- * @param[out] new_val Atomic object output (uint32_t), value after operation.
- * @param[in] value Atomic operation operand.
+ * @param[in] asm_op Operation: mov, orr, and, eor, add, sub.
+ * @param[out] old_val Atomic object output (uint32_t); value before operation.
+ * @param[out] new_val Atomic object output (uint32_t); value after operation.
+ * @param[in] value Atomic operation operand.
*/
#define NRFX_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \
{ \
@@ -274,8 +275,8 @@ loop_sub_ge
"movlo %["#new_val"], %["#old_val"]\n"
static inline bool nrfx_atomic_internal_cmp_exch(nrfx_atomic_u32_t * p_data,
- uint32_t * p_expected,
- uint32_t value)
+ uint32_t * p_expected,
+ uint32_t value)
{
bool res = false;
/* Temporary register used in the inline asm code for getting the result
diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_coredep.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_coredep.h
index 541646254..08ccc1b86 100644
--- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_coredep.h
+++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_coredep.h
@@ -45,6 +45,13 @@
#define NRFX_DELAY_CPU_FREQ_MHZ
/** @brief Availability of Data Watchpoint and Trace (DWT) unit in the given SoC. */
#define NRFX_DELAY_DWT_PRESENT
+/**
+ * @brief Number of cycles consumed by one iteration of the internal loop
+ * in the function @ref nrfx_coredep_delay_us.
+ *
+ * This value can be specified externally (for example, when the SoC is emulated).
+ */
+#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES
#elif defined(NRF51)
#define NRFX_DELAY_CPU_FREQ_MHZ 16
@@ -52,13 +59,9 @@
#elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA)
#define NRFX_DELAY_CPU_FREQ_MHZ 64
#define NRFX_DELAY_DWT_PRESENT 0
-#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
- #define NRFX_DELAY_CPU_FREQ_MHZ 64
- #define NRFX_DELAY_DWT_PRESENT 1
-#elif defined(NRF52840_XXAA)
- #define NRFX_DELAY_CPU_FREQ_MHZ 64
- #define NRFX_DELAY_DWT_PRESENT 1
-#elif defined(NRF9160_XXAA)
+#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
+ defined(NRF52833_XXAA) || defined(NRF52840_XXAA) || \
+ defined(NRF9160_XXAA)
#define NRFX_DELAY_CPU_FREQ_MHZ 64
#define NRFX_DELAY_DWT_PRESENT 1
#else
@@ -73,6 +76,8 @@
* - For SoCs working at 64MHz: 0xFFFFFFFF/64 = 0x03FFFFFF (67108863 microseconds)
* - For SoCs working at 16MHz: 0xFFFFFFFF/16 = 0x0FFFFFFF (268435455 microseconds)
*
+ * @sa NRFX_COREDEP_DELAY_US_LOOP_CYCLES
+ *
* @param time_us Number of microseconds to wait.
*/
__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us);
@@ -116,8 +121,8 @@ __STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
DWT->CTRL = dwt_ctrl;
CoreDebug->DEMCR = core_debug;
}
-#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)
+#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)
__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
@@ -126,37 +131,35 @@ __STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
return;
}
- #if defined(NRF51)
- // The loop takes 4 cycles: 1 for SUBS, 3 for BHI.
- static const uint16_t delay_bytecode[] = {
- 0x3804, // SUBS r0, #4
- 0xd8fd, // BHI .-2
- 0x4770 // BX LR
- };
- #elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA)
- // The loop takes 7 cycles: 1 for SUBS, 2 for BHI, 2 flash wait states for each instruction.
- static const uint16_t delay_bytecode[] = {
- 0x3807, // SUBS r0, #7
- 0xd8fd, // BHI .-2
- 0x4770 // BX LR
- };
- #elif (defined(NRF52832_XXAA) || \
- defined (NRF52832_XXAB) || \
- defined(NRF52840_XXAA) || \
- defined(NRF9160_XXAA))
- // The loop takes 3 cycles: 1 for SUBS, 2 for BHI.
- // Make sure that code is cached properly, so that no extra wait states appear.
+ // Allow overriding the number of cycles per loop iteration, in case it is
+ // needed to adjust this number externally (for example, when the SoC is
+ // emulated).
+ #ifndef NRFX_COREDEP_DELAY_US_LOOP_CYCLES
+ #if defined(NRF51)
+ // The loop takes 4 cycles: 1 for SUBS, 3 for BHI.
+ #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 4
+ #elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA)
+ // The loop takes 7 cycles: 1 for SUBS, 2 for BHI, 2 wait states
+ // for each instruction.
+ #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 7
+ #else
+ // The loop takes 3 cycles: 1 for SUBS, 2 for BHI.
+ #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 3
+ #endif
+ #endif // NRFX_COREDEP_DELAY_US_LOOP_CYCLES
+ // Align the machine code, so that it can be cached properly and no extra
+ // wait states appear.
__ALIGN(16)
- static const uint16_t delay_bytecode[] = {
- 0x3803, // SUBS r0, #3
+ static const uint16_t delay_machine_code[] = {
+ 0x3800 + NRFX_COREDEP_DELAY_US_LOOP_CYCLES, // SUBS r0, #loop_cycles
0xd8fd, // BHI .-2
0x4770 // BX LR
- };
- #endif
+ };
typedef void (* delay_func_t)(uint32_t);
- // Set LSB to 1 to execute code in Thumb mode.
- const delay_func_t delay_cycles = (delay_func_t)((((uint32_t)delay_bytecode) | 1));
+ const delay_func_t delay_cycles =
+ // Set LSB to 1 to execute the code in the Thumb mode.
+ (delay_func_t)((((uint32_t)delay_machine_code) | 1));
uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
delay_cycles(cycles);
}
diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs.h
index 09612bcd6..55a8c5d35 100644
--- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs.h
+++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs.h
@@ -40,6 +40,8 @@
#include
#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
#include
+#elif defined(NRF52833_XXAA)
+ #include
#elif defined(NRF52840_XXAA)
#include
#elif defined(NRF9160_XXAA)
diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf51.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf51.h
index 03ca34d48..d32db8ea2 100644
--- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf51.h
+++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf51.h
@@ -81,6 +81,7 @@ extern "C" {
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
+#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52810.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52810.h
index a293d813d..a13686952 100644
--- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52810.h
+++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52810.h
@@ -87,6 +87,7 @@ extern "C" {
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
+#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52811.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52811.h
index 884e6172e..3ae6ac5c1 100644
--- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52811.h
+++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52811.h
@@ -90,6 +90,7 @@ extern "C" {
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
+#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52832.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52832.h
index 84a8373b6..7d42e03ac 100644
--- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52832.h
+++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52832.h
@@ -96,6 +96,7 @@ extern "C" {
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
+#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52833.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52833.h
new file mode 100644
index 000000000..508d8606e
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52833.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2019, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_IRQS_NRF52833_H__
+#define NRFX_IRQS_NRF52833_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+// POWER_CLOCK_IRQn
+#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler
+
+// RADIO_IRQn
+
+// UARTE0_UART0_IRQn
+#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED)
+#define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler
+#else
+#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler
+#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler
+#endif
+
+// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
+#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
+#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#else
+#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#endif
+
+// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
+#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
+#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#else
+#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#endif
+
+// NFCT_IRQn
+#define nrfx_nfct_irq_handler NFCT_IRQHandler
+
+// GPIOTE_IRQn
+#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler
+
+// SAADC_IRQn
+#define nrfx_saadc_irq_handler SAADC_IRQHandler
+
+// TIMER0_IRQn
+#define nrfx_timer_0_irq_handler TIMER0_IRQHandler
+
+// TIMER1_IRQn
+#define nrfx_timer_1_irq_handler TIMER1_IRQHandler
+
+// TIMER2_IRQn
+#define nrfx_timer_2_irq_handler TIMER2_IRQHandler
+
+// RTC0_IRQn
+#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
+
+// TEMP_IRQn
+#define nrfx_temp_irq_handler TEMP_IRQHandler
+
+// RNG_IRQn
+#define nrfx_rng_irq_handler RNG_IRQHandler
+
+// ECB_IRQn
+
+// CCM_AAR_IRQn
+
+// WDT_IRQn
+#define nrfx_wdt_irq_handler WDT_IRQHandler
+
+// RTC1_IRQn
+#define nrfx_rtc_1_irq_handler RTC1_IRQHandler
+
+// QDEC_IRQn
+#define nrfx_qdec_irq_handler QDEC_IRQHandler
+
+// COMP_LPCOMP_IRQn
+#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED)
+#define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler
+#else
+#define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler
+#define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler
+#endif
+
+// SWI0_EGU0_IRQn
+#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler
+
+// SWI1_EGU1_IRQn
+#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler
+
+// SWI2_EGU2_IRQn
+#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler
+
+// SWI3_EGU3_IRQn
+#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler
+
+// SWI4_EGU4_IRQn
+#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler
+
+// SWI5_EGU5_IRQn
+#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler
+
+// TIMER3_IRQn
+#define nrfx_timer_3_irq_handler TIMER3_IRQHandler
+
+// TIMER4_IRQn
+#define nrfx_timer_4_irq_handler TIMER4_IRQHandler
+
+// PWM0_IRQn
+#define nrfx_pwm_0_irq_handler PWM0_IRQHandler
+
+// PDM_IRQn
+#define nrfx_pdm_irq_handler PDM_IRQHandler
+
+// MWU_IRQn
+
+// PWM1_IRQn
+#define nrfx_pwm_1_irq_handler PWM1_IRQHandler
+
+// PWM2_IRQn
+#define nrfx_pwm_2_irq_handler PWM2_IRQHandler
+
+// SPIM2_SPIS2_SPI2_IRQn
+#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
+#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
+#else
+#define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
+#define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
+#define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler
+#endif
+
+// RTC2_IRQn
+#define nrfx_rtc_2_irq_handler RTC2_IRQHandler
+
+// I2S_IRQn
+#define nrfx_i2s_irq_handler I2S_IRQHandler
+
+// FPU_IRQn
+
+// USBD_IRQn
+#define nrfx_usbd_irq_handler USBD_IRQHandler
+
+// UARTE1_IRQn
+#define nrfx_uarte_1_irq_handler UARTE1_IRQHandler
+
+// PWM3_IRQn
+#define nrfx_pwm_3_irq_handler PWM3_IRQHandler
+
+// SPIM3_IRQn
+#define nrfx_spim_3_irq_handler SPIM3_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_IRQS_NRF52833_H__
diff --git a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52840.h b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52840.h
index b4030630c..d19a2e3dc 100644
--- a/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52840.h
+++ b/third_party/NordicSemiconductor/nrfx/soc/nrfx_irqs_nrf52840.h
@@ -96,6 +96,7 @@ extern "C" {
#define nrfx_rtc_0_irq_handler RTC0_IRQHandler
// TEMP_IRQn
+#define nrfx_temp_irq_handler TEMP_IRQHandler
// RNG_IRQn
#define nrfx_rng_irq_handler RNG_IRQHandler
diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF51/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF51/nrfx_config.h
index f87173e2c..d080e882c 100644
--- a/third_party/NordicSemiconductor/nrfx/templates/nRF51/nrfx_config.h
+++ b/third_party/NordicSemiconductor/nrfx/templates/nRF51/nrfx_config.h
@@ -358,6 +358,14 @@
//
+// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
+//==========================================================
+#ifndef NRFX_NVMC_ENABLED
+#define NRFX_NVMC_ENABLED 1
+#endif
+
+//
+
// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver
//==========================================================
#ifndef NRFX_POWER_ENABLED
@@ -1133,6 +1141,25 @@
//
+// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver
+//==========================================================
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 1
+#endif
+
+// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 3
+#endif
+
+//
+
// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
//==========================================================
#ifndef NRFX_TIMER_ENABLED
@@ -1365,7 +1392,7 @@
#ifndef NRFX_UART_ENABLED
#define NRFX_UART_ENABLED 1
#endif
-// NRFX_UART0_ENABLED - Enable UART0 instance
+// NRFX_UART0_ENABLED - Enable UART0 instance
#ifndef NRFX_UART0_ENABLED
#define NRFX_UART0_ENABLED 1
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF52810/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF52810/nrfx_config.h
index 97b00ec96..4abea9f5b 100644
--- a/third_party/NordicSemiconductor/nrfx/templates/nRF52810/nrfx_config.h
+++ b/third_party/NordicSemiconductor/nrfx/templates/nRF52810/nrfx_config.h
@@ -313,6 +313,14 @@
//
+// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
+//==========================================================
+#ifndef NRFX_NVMC_ENABLED
+#define NRFX_NVMC_ENABLED 1
+#endif
+
+//
+
// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
//==========================================================
#ifndef NRFX_PDM_ENABLED
@@ -1583,6 +1591,29 @@
#define NRFX_SYSTICK_ENABLED 1
#endif
+// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver
+//==========================================================
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 1
+#endif
+
+// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+//
+
// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
//==========================================================
#ifndef NRFX_TIMER_ENABLED
@@ -2042,7 +2073,7 @@
#ifndef NRFX_UARTE_ENABLED
#define NRFX_UARTE_ENABLED 1
#endif
-// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
+// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
#ifndef NRFX_UARTE0_ENABLED
#define NRFX_UARTE0_ENABLED 1
#endif
@@ -2163,7 +2194,7 @@
#ifndef NRFX_UART_ENABLED
#define NRFX_UART_ENABLED 1
#endif
-// NRFX_UART0_ENABLED - Enable UART0 instance
+// NRFX_UART0_ENABLED - Enable UART0 instance
#ifndef NRFX_UART0_ENABLED
#define NRFX_UART0_ENABLED 1
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF52811/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF52811/nrfx_config.h
index 961785959..96e053c83 100644
--- a/third_party/NordicSemiconductor/nrfx/templates/nRF52811/nrfx_config.h
+++ b/third_party/NordicSemiconductor/nrfx/templates/nRF52811/nrfx_config.h
@@ -313,6 +313,14 @@
//
+// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
+//==========================================================
+#ifndef NRFX_NVMC_ENABLED
+#define NRFX_NVMC_ENABLED 1
+#endif
+
+//
+
// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
//==========================================================
#ifndef NRFX_PDM_ENABLED
@@ -1598,6 +1606,29 @@
#define NRFX_SYSTICK_ENABLED 1
#endif
+// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver
+//==========================================================
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 1
+#endif
+
+// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+//
+
// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
//==========================================================
#ifndef NRFX_TIMER_ENABLED
@@ -2057,7 +2088,7 @@
#ifndef NRFX_UARTE_ENABLED
#define NRFX_UARTE_ENABLED 1
#endif
-// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
+// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
#ifndef NRFX_UARTE0_ENABLED
#define NRFX_UARTE0_ENABLED 1
#endif
@@ -2178,7 +2209,7 @@
#ifndef NRFX_UART_ENABLED
#define NRFX_UART_ENABLED 1
#endif
-// NRFX_UART0_ENABLED - Enable UART0 instance
+// NRFX_UART0_ENABLED - Enable UART0 instance
#ifndef NRFX_UART0_ENABLED
#define NRFX_UART0_ENABLED 1
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF52832/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF52832/nrfx_config.h
index a9f8b0b84..67f3c7493 100644
--- a/third_party/NordicSemiconductor/nrfx/templates/nRF52832/nrfx_config.h
+++ b/third_party/NordicSemiconductor/nrfx/templates/nRF52832/nrfx_config.h
@@ -710,6 +710,14 @@
//
+// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
+//==========================================================
+#ifndef NRFX_NVMC_ENABLED
+#define NRFX_NVMC_ENABLED 1
+#endif
+
+//
+
// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
//==========================================================
#ifndef NRFX_PDM_ENABLED
@@ -2111,6 +2119,29 @@
#define NRFX_SYSTICK_ENABLED 1
#endif
+// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver
+//==========================================================
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 1
+#endif
+
+// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+//
+
// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
//==========================================================
#ifndef NRFX_TIMER_ENABLED
@@ -2617,7 +2648,7 @@
#ifndef NRFX_UARTE_ENABLED
#define NRFX_UARTE_ENABLED 1
#endif
-// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
+// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
#ifndef NRFX_UARTE0_ENABLED
#define NRFX_UARTE0_ENABLED 1
#endif
@@ -2738,7 +2769,7 @@
#ifndef NRFX_UART_ENABLED
#define NRFX_UART_ENABLED 1
#endif
-// NRFX_UART0_ENABLED - Enable UART0 instance
+// NRFX_UART0_ENABLED - Enable UART0 instance
#ifndef NRFX_UART0_ENABLED
#define NRFX_UART0_ENABLED 1
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF52833/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF52833/nrfx_config.h
new file mode 100644
index 000000000..c946a8fb6
--- /dev/null
+++ b/third_party/NordicSemiconductor/nrfx/templates/nRF52833/nrfx_config.h
@@ -0,0 +1,3042 @@
+#ifndef NRFX_CONFIG_H__
+#define NRFX_CONFIG_H__
+
+// <<< Use Configuration Wizard in Context Menu >>>\n
+
+// nRF_Drivers
+
+// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver
+//==========================================================
+#ifndef NRFX_CLOCK_ENABLED
+#define NRFX_CLOCK_ENABLED 1
+#endif
+// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source
+
+// <0=> RC
+// <1=> XTAL
+// <2=> Synth
+// <131073=> External Low Swing
+// <196609=> External Full Swing
+
+#ifndef NRFX_CLOCK_CONFIG_LF_SRC
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#endif
+
+// NRFX_CLOCK_CONFIG_LF_CAL_ENABLED - Enables LF Clock Calibration Support
+
+#ifndef NRFX_CLOCK_CONFIG_LF_CAL_ENABLED
+#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0
+#endif
+
+// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY
+#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
+#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
+#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
+#define NRFX_CLOCK_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
+#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver
+//==========================================================
+#ifndef NRFX_COMP_ENABLED
+#define NRFX_COMP_ENABLED 1
+#endif
+// NRFX_COMP_CONFIG_REF - Reference voltage
+
+// <0=> Internal 1.2V
+// <1=> Internal 1.8V
+// <2=> Internal 2.4V
+// <4=> VDD
+// <7=> ARef
+
+#ifndef NRFX_COMP_CONFIG_REF
+#define NRFX_COMP_CONFIG_REF 1
+#endif
+
+// NRFX_COMP_CONFIG_MAIN_MODE - Main mode
+
+// <0=> Single ended
+// <1=> Differential
+
+#ifndef NRFX_COMP_CONFIG_MAIN_MODE
+#define NRFX_COMP_CONFIG_MAIN_MODE 0
+#endif
+
+// NRFX_COMP_CONFIG_SPEED_MODE - Speed mode
+
+// <0=> Low power
+// <1=> Normal
+// <2=> High speed
+
+#ifndef NRFX_COMP_CONFIG_SPEED_MODE
+#define NRFX_COMP_CONFIG_SPEED_MODE 2
+#endif
+
+// NRFX_COMP_CONFIG_HYST - Hystheresis
+
+// <0=> No
+// <1=> 50mV
+
+#ifndef NRFX_COMP_CONFIG_HYST
+#define NRFX_COMP_CONFIG_HYST 0
+#endif
+
+// NRFX_COMP_CONFIG_ISOURCE - Current Source
+
+// <0=> Off
+// <1=> 2.5 uA
+// <2=> 5 uA
+// <3=> 10 uA
+
+#ifndef NRFX_COMP_CONFIG_ISOURCE
+#define NRFX_COMP_CONFIG_ISOURCE 0
+#endif
+
+// NRFX_COMP_CONFIG_INPUT - Analog input
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_COMP_CONFIG_INPUT
+#define NRFX_COMP_CONFIG_INPUT 0
+#endif
+
+// NRFX_COMP_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY
+#define NRFX_COMP_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
+#define NRFX_COMP_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
+#define NRFX_COMP_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_COMP_CONFIG_INFO_COLOR
+#define NRFX_COMP_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR
+#define NRFX_COMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver
+//==========================================================
+#ifndef NRFX_GPIOTE_ENABLED
+#define NRFX_GPIOTE_ENABLED 1
+#endif
+// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+// NRFX_GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY
+#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
+#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
+#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
+#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
+#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver
+//==========================================================
+#ifndef NRFX_I2S_ENABLED
+#define NRFX_I2S_ENABLED 1
+#endif
+// NRFX_I2S_CONFIG_SCK_PIN - SCK pin <0-31>
+
+
+#ifndef NRFX_I2S_CONFIG_SCK_PIN
+#define NRFX_I2S_CONFIG_SCK_PIN 31
+#endif
+
+// NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin <1-31>
+
+
+#ifndef NRFX_I2S_CONFIG_LRCK_PIN
+#define NRFX_I2S_CONFIG_LRCK_PIN 30
+#endif
+
+// NRFX_I2S_CONFIG_MCK_PIN - MCK pin
+#ifndef NRFX_I2S_CONFIG_MCK_PIN
+#define NRFX_I2S_CONFIG_MCK_PIN 255
+#endif
+
+// NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31>
+
+
+#ifndef NRFX_I2S_CONFIG_SDOUT_PIN
+#define NRFX_I2S_CONFIG_SDOUT_PIN 29
+#endif
+
+// NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin <0-31>
+
+
+#ifndef NRFX_I2S_CONFIG_SDIN_PIN
+#define NRFX_I2S_CONFIG_SDIN_PIN 28
+#endif
+
+// NRFX_I2S_CONFIG_MASTER - Mode
+
+// <0=> Master
+// <1=> Slave
+
+#ifndef NRFX_I2S_CONFIG_MASTER
+#define NRFX_I2S_CONFIG_MASTER 0
+#endif
+
+// NRFX_I2S_CONFIG_FORMAT - Format
+
+// <0=> I2S
+// <1=> Aligned
+
+#ifndef NRFX_I2S_CONFIG_FORMAT
+#define NRFX_I2S_CONFIG_FORMAT 0
+#endif
+
+// NRFX_I2S_CONFIG_ALIGN - Alignment
+
+// <0=> Left
+// <1=> Right
+
+#ifndef NRFX_I2S_CONFIG_ALIGN
+#define NRFX_I2S_CONFIG_ALIGN 0
+#endif
+
+// NRFX_I2S_CONFIG_SWIDTH - Sample width (bits)
+
+// <0=> 8
+// <1=> 16
+// <2=> 24
+
+#ifndef NRFX_I2S_CONFIG_SWIDTH
+#define NRFX_I2S_CONFIG_SWIDTH 1
+#endif
+
+// NRFX_I2S_CONFIG_CHANNELS - Channels
+
+// <0=> Stereo
+// <1=> Left
+// <2=> Right
+
+#ifndef NRFX_I2S_CONFIG_CHANNELS
+#define NRFX_I2S_CONFIG_CHANNELS 1
+#endif
+
+// NRFX_I2S_CONFIG_MCK_SETUP - MCK behavior
+
+// <0=> Disabled
+// <2147483648=> 32MHz/2
+// <1342177280=> 32MHz/3
+// <1073741824=> 32MHz/4
+// <805306368=> 32MHz/5
+// <671088640=> 32MHz/6
+// <536870912=> 32MHz/8
+// <402653184=> 32MHz/10
+// <369098752=> 32MHz/11
+// <285212672=> 32MHz/15
+// <268435456=> 32MHz/16
+// <201326592=> 32MHz/21
+// <184549376=> 32MHz/23
+// <142606336=> 32MHz/30
+// <138412032=> 32MHz/31
+// <134217728=> 32MHz/32
+// <100663296=> 32MHz/42
+// <68157440=> 32MHz/63
+// <34340864=> 32MHz/125
+
+#ifndef NRFX_I2S_CONFIG_MCK_SETUP
+#define NRFX_I2S_CONFIG_MCK_SETUP 536870912
+#endif
+
+// NRFX_I2S_CONFIG_RATIO - MCK/LRCK ratio
+
+// <0=> 32x
+// <1=> 48x
+// <2=> 64x
+// <3=> 96x
+// <4=> 128x
+// <5=> 192x
+// <6=> 256x
+// <7=> 384x
+// <8=> 512x
+
+#ifndef NRFX_I2S_CONFIG_RATIO
+#define NRFX_I2S_CONFIG_RATIO 5
+#endif
+
+// NRFX_I2S_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY
+#define NRFX_I2S_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
+#define NRFX_I2S_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
+#define NRFX_I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_I2S_CONFIG_INFO_COLOR
+#define NRFX_I2S_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
+#define NRFX_I2S_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver
+//==========================================================
+#ifndef NRFX_LPCOMP_ENABLED
+#define NRFX_LPCOMP_ENABLED 1
+#endif
+// NRFX_LPCOMP_CONFIG_REFERENCE - Reference voltage
+
+// <0=> Supply 1/8
+// <1=> Supply 2/8
+// <2=> Supply 3/8
+// <3=> Supply 4/8
+// <4=> Supply 5/8
+// <5=> Supply 6/8
+// <6=> Supply 7/8
+// <8=> Supply 1/16 (nRF52)
+// <9=> Supply 3/16 (nRF52)
+// <10=> Supply 5/16 (nRF52)
+// <11=> Supply 7/16 (nRF52)
+// <12=> Supply 9/16 (nRF52)
+// <13=> Supply 11/16 (nRF52)
+// <14=> Supply 13/16 (nRF52)
+// <15=> Supply 15/16 (nRF52)
+// <7=> External Ref 0
+// <65543=> External Ref 1
+
+#ifndef NRFX_LPCOMP_CONFIG_REFERENCE
+#define NRFX_LPCOMP_CONFIG_REFERENCE 3
+#endif
+
+// NRFX_LPCOMP_CONFIG_DETECTION - Detection
+
+// <0=> Crossing
+// <1=> Up
+// <2=> Down
+
+#ifndef NRFX_LPCOMP_CONFIG_DETECTION
+#define NRFX_LPCOMP_CONFIG_DETECTION 2
+#endif
+
+// NRFX_LPCOMP_CONFIG_INPUT - Analog input
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_LPCOMP_CONFIG_INPUT
+#define NRFX_LPCOMP_CONFIG_INPUT 0
+#endif
+
+// NRFX_LPCOMP_CONFIG_HYST - Hysteresis
+
+
+#ifndef NRFX_LPCOMP_CONFIG_HYST
+#define NRFX_LPCOMP_CONFIG_HYST 0
+#endif
+
+// NRFX_LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY
+#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
+#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_LPCOMP_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
+#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR
+#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR
+#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_NFCT_ENABLED - nrfx_nfct - NFCT peripheral driver
+//==========================================================
+#ifndef NRFX_NFCT_ENABLED
+#define NRFX_NFCT_ENABLED 1
+#endif
+// NRFX_NFCT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_NFCT_CONFIG_IRQ_PRIORITY
+#define NRFX_NFCT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_NFCT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED
+#define NRFX_NFCT_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_NFCT_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL
+#define NRFX_NFCT_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_NFCT_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_NFCT_CONFIG_INFO_COLOR
+#define NRFX_NFCT_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_NFCT_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR
+#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
+//==========================================================
+#ifndef NRFX_NVMC_ENABLED
+#define NRFX_NVMC_ENABLED 1
+#endif
+
+//
+
+// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
+//==========================================================
+#ifndef NRFX_PDM_ENABLED
+#define NRFX_PDM_ENABLED 1
+#endif
+// NRFX_PDM_CONFIG_MODE - Mode
+
+// <0=> Stereo
+// <1=> Mono
+
+#ifndef NRFX_PDM_CONFIG_MODE
+#define NRFX_PDM_CONFIG_MODE 1
+#endif
+
+// NRFX_PDM_CONFIG_EDGE - Edge
+
+// <0=> Left falling
+// <1=> Left rising
+
+#ifndef NRFX_PDM_CONFIG_EDGE
+#define NRFX_PDM_CONFIG_EDGE 0
+#endif
+
+// NRFX_PDM_CONFIG_CLOCK_FREQ - Clock frequency
+
+// <134217728=> 1000k
+// <138412032=> 1032k (default)
+// <142606336=> 1067k
+
+#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ
+#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032
+#endif
+
+// NRFX_PDM_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY
+#define NRFX_PDM_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
+#define NRFX_PDM_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
+#define NRFX_PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PDM_CONFIG_INFO_COLOR
+#define NRFX_PDM_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
+#define NRFX_PDM_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver
+//==========================================================
+#ifndef NRFX_POWER_ENABLED
+#define NRFX_POWER_ENABLED 1
+#endif
+// NRFX_POWER_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_POWER_CONFIG_IRQ_PRIORITY
+#define NRFX_POWER_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator
+
+
+// This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN
+#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0
+#endif
+
+// NRFX_POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator
+
+
+// This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV
+#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0
+#endif
+
+//
+
+// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator
+//==========================================================
+#ifndef NRFX_PPI_ENABLED
+#define NRFX_PPI_ENABLED 1
+#endif
+// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_PPI_CONFIG_LOG_ENABLED
+#define NRFX_PPI_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_PPI_CONFIG_LOG_LEVEL
+#define NRFX_PPI_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PPI_CONFIG_INFO_COLOR
+#define NRFX_PPI_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR
+#define NRFX_PPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing module
+//==========================================================
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 1
+#endif
+// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module.
+
+
+#ifndef NRFX_PRS_BOX_0_ENABLED
+#define NRFX_PRS_BOX_0_ENABLED 1
+#endif
+
+// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module.
+
+
+#ifndef NRFX_PRS_BOX_1_ENABLED
+#define NRFX_PRS_BOX_1_ENABLED 1
+#endif
+
+// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module.
+
+
+#ifndef NRFX_PRS_BOX_2_ENABLED
+#define NRFX_PRS_BOX_2_ENABLED 1
+#endif
+
+// NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module.
+
+
+#ifndef NRFX_PRS_BOX_3_ENABLED
+#define NRFX_PRS_BOX_3_ENABLED 1
+#endif
+
+// NRFX_PRS_BOX_4_ENABLED - Enables box 4 in the module.
+
+
+#ifndef NRFX_PRS_BOX_4_ENABLED
+#define NRFX_PRS_BOX_4_ENABLED 1
+#endif
+
+// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
+#define NRFX_PRS_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_PRS_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
+#define NRFX_PRS_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PRS_CONFIG_INFO_COLOR
+#define NRFX_PRS_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR
+#define NRFX_PRS_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver
+//==========================================================
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 1
+#endif
+// NRFX_PWM0_ENABLED - Enable PWM0 instance
+
+
+#ifndef NRFX_PWM0_ENABLED
+#define NRFX_PWM0_ENABLED 1
+#endif
+
+// NRFX_PWM1_ENABLED - Enable PWM1 instance
+
+
+#ifndef NRFX_PWM1_ENABLED
+#define NRFX_PWM1_ENABLED 1
+#endif
+
+// NRFX_PWM2_ENABLED - Enable PWM2 instance
+
+
+#ifndef NRFX_PWM2_ENABLED
+#define NRFX_PWM2_ENABLED 1
+#endif
+
+// NRFX_PWM3_ENABLED - Enable PWM3 instance
+
+
+#ifndef NRFX_PWM3_ENABLED
+#define NRFX_PWM3_ENABLED 1
+#endif
+
+// NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31
+#endif
+
+// NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31
+#endif
+
+// NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31
+#endif
+
+// NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31
+#endif
+
+// NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK
+#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4
+#endif
+
+// NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode
+
+// <0=> Up
+// <1=> Up and Down
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0
+#endif
+
+// NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value
+#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE
+#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000
+#endif
+
+// NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode
+
+// <0=> Common
+// <1=> Grouped
+// <2=> Individual
+// <3=> Waveform
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0
+#endif
+
+// NRFX_PWM_DEFAULT_CONFIG_STEP_MODE - Step mode
+
+// <0=> Auto
+// <1=> Triggered
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0
+#endif
+
+// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PWM_CONFIG_INFO_COLOR
+#define NRFX_PWM_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
+#define NRFX_PWM_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver
+//==========================================================
+#ifndef NRFX_QDEC_ENABLED
+#define NRFX_QDEC_ENABLED 1
+#endif
+// NRFX_QDEC_CONFIG_REPORTPER - Report period
+
+// <0=> 10 Samples
+// <1=> 40 Samples
+// <2=> 80 Samples
+// <3=> 120 Samples
+// <4=> 160 Samples
+// <5=> 200 Samples
+// <6=> 240 Samples
+// <7=> 280 Samples
+
+#ifndef NRFX_QDEC_CONFIG_REPORTPER
+#define NRFX_QDEC_CONFIG_REPORTPER 0
+#endif
+
+// NRFX_QDEC_CONFIG_SAMPLEPER - Sample period
+
+// <0=> 128 us
+// <1=> 256 us
+// <2=> 512 us
+// <3=> 1024 us
+// <4=> 2048 us
+// <5=> 4096 us
+// <6=> 8192 us
+// <7=> 16384 us
+
+#ifndef NRFX_QDEC_CONFIG_SAMPLEPER
+#define NRFX_QDEC_CONFIG_SAMPLEPER 7
+#endif
+
+// NRFX_QDEC_CONFIG_PIO_A - A pin <0-31>
+
+
+#ifndef NRFX_QDEC_CONFIG_PIO_A
+#define NRFX_QDEC_CONFIG_PIO_A 31
+#endif
+
+// NRFX_QDEC_CONFIG_PIO_B - B pin <0-31>
+
+
+#ifndef NRFX_QDEC_CONFIG_PIO_B
+#define NRFX_QDEC_CONFIG_PIO_B 31
+#endif
+
+// NRFX_QDEC_CONFIG_PIO_LED - LED pin <0-31>
+
+
+#ifndef NRFX_QDEC_CONFIG_PIO_LED
+#define NRFX_QDEC_CONFIG_PIO_LED 31
+#endif
+
+// NRFX_QDEC_CONFIG_LEDPRE - LED pre
+#ifndef NRFX_QDEC_CONFIG_LEDPRE
+#define NRFX_QDEC_CONFIG_LEDPRE 511
+#endif
+
+// NRFX_QDEC_CONFIG_LEDPOL - LED polarity
+
+// <0=> Active low
+// <1=> Active high
+
+#ifndef NRFX_QDEC_CONFIG_LEDPOL
+#define NRFX_QDEC_CONFIG_LEDPOL 1
+#endif
+
+// NRFX_QDEC_CONFIG_DBFEN - Debouncing enable
+
+
+#ifndef NRFX_QDEC_CONFIG_DBFEN
+#define NRFX_QDEC_CONFIG_DBFEN 0
+#endif
+
+// NRFX_QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable
+
+
+#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN
+#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0
+#endif
+
+// NRFX_QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY
+#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
+#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
+#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_QDEC_CONFIG_INFO_COLOR
+#define NRFX_QDEC_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR
+#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver
+//==========================================================
+#ifndef NRFX_RNG_ENABLED
+#define NRFX_RNG_ENABLED 1
+#endif
+// NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction
+
+
+#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION
+#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1
+#endif
+
+// NRFX_RNG_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY
+#define NRFX_RNG_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_RNG_CONFIG_LOG_ENABLED
+#define NRFX_RNG_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_RNG_CONFIG_LOG_LEVEL
+#define NRFX_RNG_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RNG_CONFIG_INFO_COLOR
+#define NRFX_RNG_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR
+#define NRFX_RNG_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver
+//==========================================================
+#ifndef NRFX_RTC_ENABLED
+#define NRFX_RTC_ENABLED 1
+#endif
+// NRFX_RTC0_ENABLED - Enable RTC0 instance
+
+
+#ifndef NRFX_RTC0_ENABLED
+#define NRFX_RTC0_ENABLED 1
+#endif
+
+// NRFX_RTC1_ENABLED - Enable RTC1 instance
+
+
+#ifndef NRFX_RTC1_ENABLED
+#define NRFX_RTC1_ENABLED 1
+#endif
+
+// NRFX_RTC2_ENABLED - Enable RTC2 instance
+
+
+#ifndef NRFX_RTC2_ENABLED
+#define NRFX_RTC2_ENABLED 1
+#endif
+
+// NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt
+#ifndef NRFX_RTC_MAXIMUM_LATENCY_US
+#define NRFX_RTC_MAXIMUM_LATENCY_US 2000
+#endif
+
+// NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768>
+
+
+#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768
+#endif
+
+// NRFX_RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering
+
+
+#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE
+#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0
+#endif
+
+// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
+#define NRFX_RTC_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
+#define NRFX_RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RTC_CONFIG_INFO_COLOR
+#define NRFX_RTC_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
+#define NRFX_RTC_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver
+//==========================================================
+#ifndef NRFX_SAADC_ENABLED
+#define NRFX_SAADC_ENABLED 1
+#endif
+// NRFX_SAADC_CONFIG_RESOLUTION - Resolution
+
+// <0=> 8 bit
+// <1=> 10 bit
+// <2=> 12 bit
+// <3=> 14 bit
+
+#ifndef NRFX_SAADC_CONFIG_RESOLUTION
+#define NRFX_SAADC_CONFIG_RESOLUTION 1
+#endif
+
+// NRFX_SAADC_CONFIG_OVERSAMPLE - Sample period
+
+// <0=> Disabled
+// <1=> 2x
+// <2=> 4x
+// <3=> 8x
+// <4=> 16x
+// <5=> 32x
+// <6=> 64x
+// <7=> 128x
+// <8=> 256x
+
+#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE
+#define NRFX_SAADC_CONFIG_OVERSAMPLE 0
+#endif
+
+// NRFX_SAADC_CONFIG_LP_MODE - Enabling low power mode
+
+
+#ifndef NRFX_SAADC_CONFIG_LP_MODE
+#define NRFX_SAADC_CONFIG_LP_MODE 0
+#endif
+
+// NRFX_SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY
+#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
+#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
+#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SAADC_CONFIG_INFO_COLOR
+#define NRFX_SAADC_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
+#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
+//==========================================================
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 1
+#endif
+// NRFX_SPIM0_ENABLED - Enable SPIM0 instance
+
+
+#ifndef NRFX_SPIM0_ENABLED
+#define NRFX_SPIM0_ENABLED 1
+#endif
+
+// NRFX_SPIM1_ENABLED - Enable SPIM1 instance
+
+
+#ifndef NRFX_SPIM1_ENABLED
+#define NRFX_SPIM1_ENABLED 1
+#endif
+
+// NRFX_SPIM2_ENABLED - Enable SPIM2 instance
+
+
+#ifndef NRFX_SPIM2_ENABLED
+#define NRFX_SPIM2_ENABLED 1
+#endif
+
+// NRFX_SPIM3_ENABLED - Enable SPIM3 instance
+
+
+#ifndef NRFX_SPIM3_ENABLED
+#define NRFX_SPIM3_ENABLED 1
+#endif
+
+// NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features
+
+
+#ifndef NRFX_SPIM_EXTENDED_ENABLED
+#define NRFX_SPIM_EXTENDED_ENABLED 0
+#endif
+
+// NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration.
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
+
+#ifndef NRFX_SPIM_MISO_PULL_CFG
+#define NRFX_SPIM_MISO_PULL_CFG 1
+#endif
+
+// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
+#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
+#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIM_CONFIG_INFO_COLOR
+#define NRFX_SPIM_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
+#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
+//==========================================================
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 1
+#endif
+// NRFX_SPIS0_ENABLED - Enable SPIS0 instance
+
+
+#ifndef NRFX_SPIS0_ENABLED
+#define NRFX_SPIS0_ENABLED 1
+#endif
+
+// NRFX_SPIS1_ENABLED - Enable SPIS1 instance
+
+
+#ifndef NRFX_SPIS1_ENABLED
+#define NRFX_SPIS1_ENABLED 1
+#endif
+
+// NRFX_SPIS2_ENABLED - Enable SPIS2 instance
+
+
+#ifndef NRFX_SPIS2_ENABLED
+#define NRFX_SPIS2_ENABLED 1
+#endif
+
+// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255>
+
+
+#ifndef NRFX_SPIS_DEFAULT_DEF
+#define NRFX_SPIS_DEFAULT_DEF 255
+#endif
+
+// NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character <0-255>
+
+
+#ifndef NRFX_SPIS_DEFAULT_ORC
+#define NRFX_SPIS_DEFAULT_ORC 255
+#endif
+
+// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
+#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
+#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIS_CONFIG_INFO_COLOR
+#define NRFX_SPIS_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
+#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
+//==========================================================
+#ifndef NRFX_SPI_ENABLED
+#define NRFX_SPI_ENABLED 1
+#endif
+// NRFX_SPI0_ENABLED - Enable SPI0 instance
+
+
+#ifndef NRFX_SPI0_ENABLED
+#define NRFX_SPI0_ENABLED 1
+#endif
+
+// NRFX_SPI1_ENABLED - Enable SPI1 instance
+
+
+#ifndef NRFX_SPI1_ENABLED
+#define NRFX_SPI1_ENABLED 1
+#endif
+
+// NRFX_SPI2_ENABLED - Enable SPI2 instance
+
+
+#ifndef NRFX_SPI2_ENABLED
+#define NRFX_SPI2_ENABLED 1
+#endif
+
+// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration.
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
+
+#ifndef NRFX_SPI_MISO_PULL_CFG
+#define NRFX_SPI_MISO_PULL_CFG 1
+#endif
+
+// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SPI_CONFIG_LOG_ENABLED
+#define NRFX_SPI_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SPI_CONFIG_LOG_LEVEL
+#define NRFX_SPI_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPI_CONFIG_INFO_COLOR
+#define NRFX_SPI_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR
+#define NRFX_SPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator
+//==========================================================
+#ifndef NRFX_SWI_ENABLED
+#define NRFX_SWI_ENABLED 1
+#endif
+// NRFX_EGU_ENABLED - Enable EGU support
+
+
+#ifndef NRFX_EGU_ENABLED
+#define NRFX_EGU_ENABLED 1
+#endif
+
+// NRFX_SWI0_DISABLED - Exclude SWI0 from being utilized by the driver
+
+
+#ifndef NRFX_SWI0_DISABLED
+#define NRFX_SWI0_DISABLED 0
+#endif
+
+// NRFX_SWI1_DISABLED - Exclude SWI1 from being utilized by the driver
+
+
+#ifndef NRFX_SWI1_DISABLED
+#define NRFX_SWI1_DISABLED 0
+#endif
+
+// NRFX_SWI2_DISABLED - Exclude SWI2 from being utilized by the driver
+
+
+#ifndef NRFX_SWI2_DISABLED
+#define NRFX_SWI2_DISABLED 0
+#endif
+
+// NRFX_SWI3_DISABLED - Exclude SWI3 from being utilized by the driver
+
+
+#ifndef NRFX_SWI3_DISABLED
+#define NRFX_SWI3_DISABLED 0
+#endif
+
+// NRFX_SWI4_DISABLED - Exclude SWI4 from being utilized by the driver
+
+
+#ifndef NRFX_SWI4_DISABLED
+#define NRFX_SWI4_DISABLED 0
+#endif
+
+// NRFX_SWI5_DISABLED - Exclude SWI5 from being utilized by the driver
+
+
+#ifndef NRFX_SWI5_DISABLED
+#define NRFX_SWI5_DISABLED 0
+#endif
+
+// NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SWI_CONFIG_LOG_ENABLED
+#define NRFX_SWI_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_SWI_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SWI_CONFIG_LOG_LEVEL
+#define NRFX_SWI_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_SWI_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SWI_CONFIG_INFO_COLOR
+#define NRFX_SWI_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR
+#define NRFX_SWI_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver
+
+
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 1
+#endif
+
+// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver
+//==========================================================
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 1
+#endif
+
+// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+//
+
+// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
+//==========================================================
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 1
+#endif
+// NRFX_TIMER0_ENABLED - Enable TIMER0 instance
+
+
+#ifndef NRFX_TIMER0_ENABLED
+#define NRFX_TIMER0_ENABLED 1
+#endif
+
+// NRFX_TIMER1_ENABLED - Enable TIMER1 instance
+
+
+#ifndef NRFX_TIMER1_ENABLED
+#define NRFX_TIMER1_ENABLED 1
+#endif
+
+// NRFX_TIMER2_ENABLED - Enable TIMER2 instance
+
+
+#ifndef NRFX_TIMER2_ENABLED
+#define NRFX_TIMER2_ENABLED 1
+#endif
+
+// NRFX_TIMER3_ENABLED - Enable TIMER3 instance
+
+
+#ifndef NRFX_TIMER3_ENABLED
+#define NRFX_TIMER3_ENABLED 1
+#endif
+
+// NRFX_TIMER4_ENABLED - Enable TIMER4 instance
+
+
+#ifndef NRFX_TIMER4_ENABLED
+#define NRFX_TIMER4_ENABLED 1
+#endif
+
+// NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+// <8=> 62.5 kHz
+// <9=> 31.25 kHz
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0
+#endif
+
+// NRFX_TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation
+
+// <0=> Timer
+// <1=> Counter
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE
+#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0
+#endif
+
+// NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width
+
+// <0=> 16 bit
+// <1=> 8 bit
+// <2=> 24 bit
+// <3=> 32 bit
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH
+#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
+#endif
+
+// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TIMER_CONFIG_INFO_COLOR
+#define NRFX_TIMER_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
+#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver
+//==========================================================
+#ifndef NRFX_TWIM_ENABLED
+#define NRFX_TWIM_ENABLED 1
+#endif
+// NRFX_TWIM0_ENABLED - Enable TWIM0 instance
+
+
+#ifndef NRFX_TWIM0_ENABLED
+#define NRFX_TWIM0_ENABLED 1
+#endif
+
+// NRFX_TWIM1_ENABLED - Enable TWIM1 instance
+
+
+#ifndef NRFX_TWIM1_ENABLED
+#define NRFX_TWIM1_ENABLED 1
+#endif
+
+// NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY - Frequency
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
+
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688
+#endif
+
+// NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit
+
+
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT
+#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
+#endif
+
+// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
+#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
+#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIM_CONFIG_INFO_COLOR
+#define NRFX_TWIM_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
+#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver
+//==========================================================
+#ifndef NRFX_TWIS_ENABLED
+#define NRFX_TWIS_ENABLED 1
+#endif
+// NRFX_TWIS0_ENABLED - Enable TWIS0 instance
+
+
+#ifndef NRFX_TWIS0_ENABLED
+#define NRFX_TWIS0_ENABLED 1
+#endif
+
+// NRFX_TWIS1_ENABLED - Enable TWIS1 instance
+
+
+#ifndef NRFX_TWIS1_ENABLED
+#define NRFX_TWIS1_ENABLED 1
+#endif
+
+// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once
+
+
+// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
+
+#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode
+
+
+// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
+
+#ifndef NRFX_TWIS_NO_SYNC_MODE
+#define NRFX_TWIS_NO_SYNC_MODE 0
+#endif
+
+// NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0
+#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0
+#endif
+
+// NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1
+#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0
+#endif
+
+// NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
+
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL
+#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0
+#endif
+
+// NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
+
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL
+#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0
+#endif
+
+// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
+#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIS_CONFIG_INFO_COLOR
+#define NRFX_TWIS_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
+#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver
+//==========================================================
+#ifndef NRFX_TWI_ENABLED
+#define NRFX_TWI_ENABLED 1
+#endif
+// NRFX_TWI0_ENABLED - Enable TWI0 instance
+
+
+#ifndef NRFX_TWI0_ENABLED
+#define NRFX_TWI0_ENABLED 1
+#endif
+
+// NRFX_TWI1_ENABLED - Enable TWI1 instance
+
+
+#ifndef NRFX_TWI1_ENABLED
+#define NRFX_TWI1_ENABLED 1
+#endif
+
+// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
+
+#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688
+#endif
+
+// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit
+
+
+#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
+#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
+#endif
+
+// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TWI_CONFIG_LOG_ENABLED
+#define NRFX_TWI_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TWI_CONFIG_LOG_LEVEL
+#define NRFX_TWI_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWI_CONFIG_INFO_COLOR
+#define NRFX_TWI_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR
+#define NRFX_TWI_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver
+//==========================================================
+#ifndef NRFX_UARTE_ENABLED
+#define NRFX_UARTE_ENABLED 1
+#endif
+// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
+#ifndef NRFX_UARTE0_ENABLED
+#define NRFX_UARTE0_ENABLED 1
+#endif
+
+// NRFX_UARTE1_ENABLED - Enable UARTE1 instance
+#ifndef NRFX_UARTE1_ENABLED
+#define NRFX_UARTE1_ENABLED 1
+#endif
+
+// NRFX_UARTE_DEFAULT_CONFIG_HWFC - Hardware Flow Control
+
+// <0=> Disabled
+// <1=> Enabled
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC
+#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0
+#endif
+
+// NRFX_UARTE_DEFAULT_CONFIG_PARITY - Parity
+
+// <0=> Excluded
+// <14=> Included
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY
+#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0
+#endif
+
+// NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE - Default Baudrate
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <8388608=> 31250 baud
+// <10289152=> 38400 baud
+// <15007744=> 56000 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE
+#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920
+#endif
+
+// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
+#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
+#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UARTE_CONFIG_INFO_COLOR
+#define NRFX_UARTE_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
+#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver
+//==========================================================
+#ifndef NRFX_UART_ENABLED
+#define NRFX_UART_ENABLED 1
+#endif
+// NRFX_UART0_ENABLED - Enable UART0 instance
+#ifndef NRFX_UART0_ENABLED
+#define NRFX_UART0_ENABLED 1
+#endif
+
+// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control
+
+// <0=> Disabled
+// <1=> Enabled
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC
+#define NRFX_UART_DEFAULT_CONFIG_HWFC 0
+#endif
+
+// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity
+
+// <0=> Excluded
+// <14=> Included
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY
+#define NRFX_UART_DEFAULT_CONFIG_PARITY 0
+#endif
+
+// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3866624=> 14400 baud
+// <5152768=> 19200 baud
+// <7729152=> 28800 baud
+// <8388608=> 31250 baud
+// <10309632=> 38400 baud
+// <15007744=> 56000 baud
+// <15462400=> 57600 baud
+// <20615168=> 76800 baud
+// <30924800=> 115200 baud
+// <61845504=> 230400 baud
+// <67108864=> 250000 baud
+// <123695104=> 460800 baud
+// <247386112=> 921600 baud
+// <268435456=> 1000000 baud
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE
+#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800
+#endif
+
+// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_UART_CONFIG_LOG_ENABLED
+#define NRFX_UART_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_UART_CONFIG_LOG_LEVEL
+#define NRFX_UART_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UART_CONFIG_INFO_COLOR
+#define NRFX_UART_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UART_CONFIG_DEBUG_COLOR
+#define NRFX_UART_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver
+//==========================================================
+#ifndef NRFX_USBD_ENABLED
+#define NRFX_USBD_ENABLED 1
+#endif
+// NRFX_USBD_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY
+#define NRFX_USBD_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers
+
+// This option gives priority to isochronous transfers.
+// Enabling it assures that isochronous transfers are always processed,
+// even if multiple other transfers are pending.
+// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm
+// function is called, so the option is independent of the algorithm chosen.
+
+#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST
+#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1
+#endif
+
+// USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
+
+
+// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
+// Else, there will be no response.
+
+#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP
+#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0
+#endif
+
+// NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module
+//==========================================================
+#ifndef NRFX_USBD_CONFIG_LOG_ENABLED
+#define NRFX_USBD_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_USBD_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_USBD_CONFIG_LOG_LEVEL
+#define NRFX_USBD_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_USBD_CONFIG_INFO_COLOR
+#define NRFX_USBD_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR
+#define NRFX_USBD_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver
+//==========================================================
+#ifndef NRFX_WDT_ENABLED
+#define NRFX_WDT_ENABLED 1
+#endif
+// NRFX_WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode
+
+// <1=> Run in SLEEP, Pause in HALT
+// <8=> Pause in SLEEP, Run in HALT
+// <9=> Run in SLEEP and HALT
+// <0=> Pause in SLEEP and HALT
+
+#ifndef NRFX_WDT_CONFIG_BEHAVIOUR
+#define NRFX_WDT_CONFIG_BEHAVIOUR 1
+#endif
+
+// NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295>
+
+
+#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE
+#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000
+#endif
+
+// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
+
+// <0=> Include WDT IRQ handling
+// <1=> Remove WDT IRQ handling
+
+#ifndef NRFX_WDT_CONFIG_NO_IRQ
+#define NRFX_WDT_CONFIG_NO_IRQ 0
+#endif
+
+// NRFX_WDT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
+#define NRFX_WDT_CONFIG_LOG_ENABLED 0
+#endif
+// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
+#define NRFX_WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_WDT_CONFIG_INFO_COLOR
+#define NRFX_WDT_CONFIG_INFO_COLOR 0
+#endif
+
+// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
+#define NRFX_WDT_CONFIG_DEBUG_COLOR 0
+#endif
+
+//
+
+//
+
+//
+
+#endif // NRFX_CONFIG_H__
diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF52840/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF52840/nrfx_config.h
index d71a0c597..ba7b315ba 100644
--- a/third_party/NordicSemiconductor/nrfx/templates/nRF52840/nrfx_config.h
+++ b/third_party/NordicSemiconductor/nrfx/templates/nRF52840/nrfx_config.h
@@ -710,6 +710,14 @@
//
+// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
+//==========================================================
+#ifndef NRFX_NVMC_ENABLED
+#define NRFX_NVMC_ENABLED 1
+#endif
+
+//
+
// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
//==========================================================
#ifndef NRFX_PDM_ENABLED
@@ -2214,6 +2222,29 @@
#define NRFX_SYSTICK_ENABLED 1
#endif
+// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver
+//==========================================================
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 1
+#endif
+
+// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+//
+
// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
//==========================================================
#ifndef NRFX_TIMER_ENABLED
@@ -2707,12 +2738,12 @@
#ifndef NRFX_UARTE_ENABLED
#define NRFX_UARTE_ENABLED 1
#endif
-// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
+// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
#ifndef NRFX_UARTE0_ENABLED
#define NRFX_UARTE0_ENABLED 1
#endif
-// NRFX_UARTE1_ENABLED - Enable UARTE1 instance
+// NRFX_UARTE1_ENABLED - Enable UARTE1 instance
#ifndef NRFX_UARTE1_ENABLED
#define NRFX_UARTE1_ENABLED 1
#endif
@@ -2833,7 +2864,7 @@
#ifndef NRFX_UART_ENABLED
#define NRFX_UART_ENABLED 1
#endif
-// NRFX_UART0_ENABLED - Enable UART0 instance
+// NRFX_UART0_ENABLED - Enable UART0 instance
#ifndef NRFX_UART0_ENABLED
#define NRFX_UART0_ENABLED 1
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/templates/nRF9160/nrfx_config.h b/third_party/NordicSemiconductor/nrfx/templates/nRF9160/nrfx_config.h
index b7b94094c..31b6c898e 100644
--- a/third_party/NordicSemiconductor/nrfx/templates/nRF9160/nrfx_config.h
+++ b/third_party/NordicSemiconductor/nrfx/templates/nRF9160/nrfx_config.h
@@ -81,14 +81,11 @@
#endif
// NRFX_CLOCK_CONFIG_LF_SRC - LF clock source.
-// <0=> RC
-// <1=> XTAL
-// <2=> Synth
-// <131073=> External Low Swing
-// <196609=> External Full Swing
+// <1=> RC
+// <2=> XTAL
#ifndef NRFX_CLOCK_CONFIG_LF_SRC
-#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#define NRFX_CLOCK_CONFIG_LF_SRC 2
#endif
// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority.
@@ -485,6 +482,14 @@
//
+// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
+//==========================================================
+#ifndef NRFX_NVMC_ENABLED
+#define NRFX_NVMC_ENABLED 1
+#endif
+
+//
+
// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver.
//==========================================================
#ifndef NRFX_PDM_ENABLED
@@ -1838,22 +1843,22 @@
#ifndef NRFX_UARTE_ENABLED
#define NRFX_UARTE_ENABLED 1
#endif
-// NRFX_UARTE0_ENABLED - Enables UARTE0 instances
+// NRFX_UARTE0_ENABLED - Enables UARTE0 instances
#ifndef NRFX_UARTE0_ENABLED
#define NRFX_UARTE0_ENABLED 1
#endif
-// NRFX_UARTE1_ENABLED - Enables UARTE1 instance.
+// NRFX_UARTE1_ENABLED - Enables UARTE1 instance.
#ifndef NRFX_UARTE1_ENABLED
#define NRFX_UARTE1_ENABLED 1
#endif
-// NRFX_UARTE2_ENABLED - Enables UARTE2 instance.
+// NRFX_UARTE2_ENABLED - Enables UARTE2 instance.
#ifndef NRFX_UARTE2_ENABLED
#define NRFX_UARTE2_ENABLED 1
#endif
-// NRFX_UARTE3_ENABLED - Enables UARTE3 instance.
+// NRFX_UARTE3_ENABLED - Enables UARTE3 instance.
#ifndef NRFX_UARTE3_ENABLED
#define NRFX_UARTE3_ENABLED 1
#endif
diff --git a/third_party/NordicSemiconductor/nrfx/templates/nrfx_glue.h b/third_party/NordicSemiconductor/nrfx/templates/nrfx_glue.h
index 004d61dec..16c1f30c1 100644
--- a/third_party/NordicSemiconductor/nrfx/templates/nrfx_glue.h
+++ b/third_party/NordicSemiconductor/nrfx/templates/nrfx_glue.h
@@ -60,14 +60,14 @@ extern "C" {
/**
* @brief Macro for placing a runtime assertion.
*
- * @param expression Expression to evaluate.
+ * @param expression Expression to be evaluated.
*/
#define NRFX_ASSERT(expression)
/**
* @brief Macro for placing a compile time assertion.
*
- * @param expression Expression to evaluate.
+ * @param expression Expression to be evaluated.
*/
#define NRFX_STATIC_ASSERT(expression)
@@ -76,22 +76,22 @@ extern "C" {
/**
* @brief Macro for setting the priority of a specific IRQ.
*
- * @param irq_number IRQ number.
- * @param priority Priority to set.
+ * @param irq_number IRQ number.
+ * @param priority Priority to be set.
*/
#define NRFX_IRQ_PRIORITY_SET(irq_number, priority)
/**
* @brief Macro for enabling a specific IRQ.
*
- * @param irq_number IRQ number.
+ * @param irq_number IRQ number.
*/
#define NRFX_IRQ_ENABLE(irq_number)
/**
* @brief Macro for checking if a specific IRQ is enabled.
*
- * @param irq_number IRQ number.
+ * @param irq_number IRQ number.
*
* @retval true If the IRQ is enabled.
* @retval false Otherwise.
@@ -101,21 +101,21 @@ extern "C" {
/**
* @brief Macro for disabling a specific IRQ.
*
- * @param irq_number IRQ number.
+ * @param irq_number IRQ number.
*/
#define NRFX_IRQ_DISABLE(irq_number)
/**
* @brief Macro for setting a specific IRQ as pending.
*
- * @param irq_number IRQ number.
+ * @param irq_number IRQ number.
*/
#define NRFX_IRQ_PENDING_SET(irq_number)
/**
* @brief Macro for clearing the pending status of a specific IRQ.
*
- * @param irq_number IRQ number.
+ * @param irq_number IRQ number.
*/
#define NRFX_IRQ_PENDING_CLEAR(irq_number)
@@ -127,14 +127,10 @@ extern "C" {
*/
#define NRFX_IRQ_IS_PENDING(irq_number)
-/**
- * @brief Macro for entering into a critical section.
- */
+/** @brief Macro for entering into a critical section. */
#define NRFX_CRITICAL_SECTION_ENTER()
-/**
- * @brief Macro for exiting from a critical section.
- */
+/** @brief Macro for exiting from a critical section. */
#define NRFX_CRITICAL_SECTION_EXIT()
//------------------------------------------------------------------------------
@@ -156,16 +152,14 @@ extern "C" {
//------------------------------------------------------------------------------
-/**
- * @brief Atomic 32-bit unsigned type.
- */
+/** @brief Atomic 32-bit unsigned type. */
#define nrfx_atomic_t
/**
* @brief Macro for storing a value to an atomic object and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value to store.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value to store.
*
* @return Previous value of the atomic object.
*/
@@ -174,8 +168,8 @@ extern "C" {
/**
* @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the OR operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the OR operation.
*
* @return Previous value of the atomic object.
*/
@@ -185,8 +179,8 @@ extern "C" {
* @brief Macro for running a bitwise AND operation on an atomic object
* and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the AND operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the AND operation.
*
* @return Previous value of the atomic object.
*/
@@ -196,8 +190,8 @@ extern "C" {
* @brief Macro for running a bitwise XOR operation on an atomic object
* and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the XOR operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the XOR operation.
*
* @return Previous value of the atomic object.
*/
@@ -207,8 +201,8 @@ extern "C" {
* @brief Macro for running an addition operation on an atomic object
* and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the ADD operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the ADD operation.
*
* @return Previous value of the atomic object.
*/
@@ -218,8 +212,8 @@ extern "C" {
* @brief Macro for running a subtraction operation on an atomic object
* and returning its previous value.
*
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value Value of the second operand in the SUB operation.
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of the second operand in the SUB operation.
*
* @return Previous value of the atomic object.
*/
@@ -237,34 +231,22 @@ extern "C" {
//------------------------------------------------------------------------------
-/**
- * @brief Bitmask defining DPPI channels reserved to be used outside of nrfx.
- */
+/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */
#define NRFX_DPPI_CHANNELS_USED 0
-/**
- * @brief Bitmask defining DPPI groups reserved to be used outside of nrfx.
- */
+/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */
#define NRFX_DPPI_GROUPS_USED 0
-/**
- * @brief Bitmask defining PPI channels reserved to be used outside of nrfx.
- */
+/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */
#define NRFX_PPI_CHANNELS_USED 0
-/**
- * @brief Bitmask defining PPI groups reserved to be used outside of nrfx.
- */
+/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */
#define NRFX_PPI_GROUPS_USED 0
-/**
- * @brief Bitmask defining SWI instances reserved to be used outside of nrfx.
- */
+/** @brief Bitmask that defines SWI instances that are reserved for use outside of the nrfx library. */
#define NRFX_SWI_USED 0
-/**
- * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx.
- */
+/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */
#define NRFX_TIMERS_USED 0
/** @} */
diff --git a/third_party/NordicSemiconductor/nrfx/templates/nrfx_log.h b/third_party/NordicSemiconductor/nrfx/templates/nrfx_log.h
index a2710bee0..3bc1b424e 100644
--- a/third_party/NordicSemiconductor/nrfx/templates/nrfx_log.h
+++ b/third_party/NordicSemiconductor/nrfx/templates/nrfx_log.h
@@ -54,32 +54,32 @@ extern "C" {
/**
* @brief Macro for logging a message with the severity level ERROR.
*
- * @param format printf-style format string, optionally followed by arguments
- * to be formatted and inserted in the resulting string.
+ * @param format printf-style format string, optionally followed by arguments
+ * to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_ERROR(format, ...)
/**
* @brief Macro for logging a message with the severity level WARNING.
*
- * @param format printf-style format string, optionally followed by arguments
- * to be formatted and inserted in the resulting string.
+ * @param format printf-style format string, optionally followed by arguments
+ * to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_WARNING(format, ...)
/**
* @brief Macro for logging a message with the severity level INFO.
*
- * @param format printf-style format string, optionally followed by arguments
- * to be formatted and inserted in the resulting string.
+ * @param format printf-style format string, optionally followed by arguments
+ * to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_INFO(format, ...)
/**
* @brief Macro for logging a message with the severity level DEBUG.
*
- * @param format printf-style format string, optionally followed by arguments
- * to be formatted and inserted in the resulting string.
+ * @param format printf-style format string, optionally followed by arguments
+ * to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_DEBUG(format, ...)
@@ -87,32 +87,32 @@ extern "C" {
/**
* @brief Macro for logging a memory dump with the severity level ERROR.
*
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length Length of the memory region in bytes.
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length)
/**
* @brief Macro for logging a memory dump with the severity level WARNING.
*
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length Length of the memory region in bytes.
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length)
/**
* @brief Macro for logging a memory dump with the severity level INFO.
*
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length Length of the memory region in bytes.
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_INFO(p_memory, length)
/**
* @brief Macro for logging a memory dump with the severity level DEBUG.
*
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length Length of the memory region in bytes.
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length)
@@ -120,7 +120,7 @@ extern "C" {
/**
* @brief Macro for getting the textual representation of a given error code.
*
- * @param[in] error_code Error code.
+ * @param[in] error_code Error code.
*
* @return String containing the textual representation of the error code.
*/