diff --git a/examples/platforms/da15000/README.md b/examples/platforms/da15000/README.md index 63396778a..d37ac5f51 100755 --- a/examples/platforms/da15000/README.md +++ b/examples/platforms/da15000/README.md @@ -36,7 +36,7 @@ Flash Binaries: 2. Return to previous terminal window and execute a command in order to flash the board: ```bash - $ ./cli_programmer -b uartboot.bin gdbserver write_qspi 0x0 ../../../output/bin/arm-none-eabi-ot-cli-ftd.img + $ ./cli_programmer gdbserver write_qspi_exec ../../../output/bin/arm-none-eabi-ot-cli-ftd.bin ``` ## Interact: diff --git a/examples/platforms/da15000/alarm.c b/examples/platforms/da15000/alarm.c index 91d8b4d45..141ec18b9 100644 --- a/examples/platforms/da15000/alarm.c +++ b/examples/platforms/da15000/alarm.c @@ -38,21 +38,21 @@ #include "hw_gpio.h" #include "platform-da15000.h" -static bool s_is_running = false; -static uint32_t s_alarm = 0; -static uint32_t s_counter; -volatile bool s_alarm_fired = false; +static bool sIsRunning = false; +static uint32_t sAlarm = 0; +static uint32_t sCounter; +volatile bool sAlarmFired = false; static void timer0_interrupt_cb(void) { - s_counter++; + sCounter++; } void da15000AlarmProcess(otInstance *aInstance) { - if ((s_is_running) && (s_alarm <= s_counter)) + if ((sIsRunning) && (sAlarm <= sCounter)) { - s_is_running = false; + sIsRunning = false; otPlatAlarmFired(aInstance); } } @@ -70,24 +70,24 @@ void da15000AlarmInit(void) uint32_t otPlatAlarmGetNow(void) { - return s_counter; + return sCounter; } void otPlatAlarmStartAt(otInstance *aInstance, uint32_t t0, uint32_t dt) { (void)aInstance; - s_alarm = t0 + dt; - s_is_running = true; + sAlarm = t0 + dt; + sIsRunning = true; - if (s_counter == 0) + if (sCounter == 0) { hw_timer0_enable(); } - if (s_is_running == false) + if (sIsRunning == false) { - s_is_running = true; + sIsRunning = true; } hw_timer0_unfreeze(); @@ -96,7 +96,7 @@ void otPlatAlarmStartAt(otInstance *aInstance, uint32_t t0, uint32_t dt) void otPlatAlarmStop(otInstance *aInstance) { (void)aInstance; - s_is_running = false; + sIsRunning = false; hw_timer0_freeze(); } diff --git a/examples/platforms/da15000/clock.c b/examples/platforms/da15000/clock.c index 3b21260fb..52ce1c7c9 100644 --- a/examples/platforms/da15000/clock.c +++ b/examples/platforms/da15000/clock.c @@ -31,7 +31,7 @@ * Clock init for Dialog da15000. * */ -#include "global_io.h" +#include "sdk_defs.h" #include "hw_cpm.h" #include "hw_watchdog.h" diff --git a/examples/platforms/da15000/cstartup.c b/examples/platforms/da15000/cstartup.c index 020cbecb8..29d0d904c 100644 --- a/examples/platforms/da15000/cstartup.c +++ b/examples/platforms/da15000/cstartup.c @@ -37,8 +37,7 @@ * For Cortex-M cores, called from cpu/arm/cortex-m/boot/cstartup.c. */ -#include "global_io.h" -#include "bsp/include/black_orca.h" +#include "sdk_defs.h" #include "bsp/include/core_cm0.h" void __cpu_startup(void) diff --git a/examples/platforms/da15000/custom_config_qspi.h b/examples/platforms/da15000/custom_config_qspi.h index 8f4eefbfd..2d420bed7 100755 --- a/examples/platforms/da15000/custom_config_qspi.h +++ b/examples/platforms/da15000/custom_config_qspi.h @@ -36,6 +36,9 @@ #include "bsp_definitions.h" +#define dg_configBLACK_ORCA_IC_REV BLACK_ORCA_IC_REV_B +#define dg_configBLACK_ORCA_IC_STEP BLACK_ORCA_IC_STEP_A + #undef CONFIG_USE_BLE #define CONFIG_USE_FTDF @@ -45,8 +48,6 @@ #define CONFIG_RETARGET #define CONFIG_RETARGET_UART HW_UART1 -#define dg_configPOWER_CONFIG (POWER_CONFIGURATION_2) - #define dg_configUSE_LP_CLK LP_CLK_32768 #define dg_configEXEC_MODE MODE_IS_CACHED #define dg_configCODE_LOCATION NON_VOLATILE_IS_FLASH @@ -58,16 +59,15 @@ #define dg_configUSER_CAN_USE_TIMER1 (0) #define dg_configMEM_RETENTION_MODE (0x1F) -#define dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE (0x1F) #define dg_configSHUFFLING_MODE (0x3) #define dg_configUSE_WDOG (0) -#define dg_configUSE_DCDC (1) - -#define dg_configPOWER_FLASH (1) +#define dg_configFLASH_CONNECTED_TO (FLASH_CONNECTED_TO_1V8) #define dg_configFLASH_POWER_DOWN (0) -#define dg_configFLASH_POWER_OFF (0) + +#define dg_configPOWER_1V8_ACTIVE (1) +#define dg_configPOWER_1V8_SLEEP (1) #define dg_configBATTERY_TYPE (BATTERY_TYPE_LIMN2O4) #define dg_configBATTERY_CHARGE_CURRENT 2 // 30mA @@ -85,6 +85,8 @@ #define dg_configCACHEABLE_QSPI_AREA_LEN NVMS_PARAM_PART_start #define dg_configFEM_DLG_REF_BOARD (1) +#define dg_configPOWER_1V8P (1) + #define dg_configUSE_HW_TRNG (1) #define dg_configUSE_HW_TIMER0 (1) diff --git a/examples/platforms/da15000/flash.c b/examples/platforms/da15000/flash.c index 65dd23a6c..b5102712e 100644 --- a/examples/platforms/da15000/flash.c +++ b/examples/platforms/da15000/flash.c @@ -44,9 +44,7 @@ #define W25Q_STATUS1_BUSY_BIT 0 #define W25Q_STATUS1_BUSY_MASK (1 << W25Q_STATUS1_BUSY_BIT) -static uint32_t wait_status_timeout; - -#define QSPI_SECTION __attribute__ ((section ("text_retained"))) +static uint32_t sWaitStatusTimeout; QSPI_SECTION static inline uint8_t qspi_get_erase_status(void) { @@ -85,9 +83,9 @@ uint32_t utilsFlashGetSize(void) ThreadError utilsFlashStatusWait(uint32_t aTimeout) { - wait_status_timeout = otPlatAlarmGetNow(); + sWaitStatusTimeout = otPlatAlarmGetNow(); - while (qspi_get_erase_status() && ((otPlatAlarmGetNow() - wait_status_timeout) < aTimeout)); + while (qspi_get_erase_status() && ((otPlatAlarmGetNow() - sWaitStatusTimeout) < aTimeout)); if (qspi_get_erase_status()) { @@ -97,18 +95,12 @@ ThreadError utilsFlashStatusWait(uint32_t aTimeout) { return kThreadError_None; } - } ThreadError utilsFlashInit(void) { - - qspi_automode_init(); qspi_automode_flash_power_up(); - utilsFlashErasePage(0); - utilsFlashErasePage(0x1000); - if (utilsFlashStatusWait(1000) == kThreadError_Busy) { return kThreadError_Failed; diff --git a/examples/platforms/da15000/misc.c b/examples/platforms/da15000/misc.c index dd5e928d0..0d9907f60 100755 --- a/examples/platforms/da15000/misc.c +++ b/examples/platforms/da15000/misc.c @@ -28,7 +28,7 @@ #include #include -#include "black_orca.h" +#include "sdk_defs.h" void otPlatReset(otInstance *aInstance) { diff --git a/examples/platforms/da15000/platform.c b/examples/platforms/da15000/platform.c index b8018d947..9dd6001b6 100644 --- a/examples/platforms/da15000/platform.c +++ b/examples/platforms/da15000/platform.c @@ -38,16 +38,16 @@ #include "platform/alarm.h" #include #include "platform-da15000.h" -#include "black_orca.h" +#include "sdk_defs.h" #include "hw_cpm.h" #include "hw_watchdog.h" #include "ftdf.h" #include "hw_gpio.h" #include "platform/uart.h" -static bool blink = false; -static int mscounter_init; -static int mscounter; +static bool sBlink = false; +static int sMsCounterInit; +static int sMsCounter; #define LEADER_BLINK_TIME (200) #define ROUTER_BLINK_TIME (500) @@ -95,13 +95,13 @@ void ExampleProcess(otInstance *aInstance) devRole = otGetDeviceRole(aInstance); - if (blink == false && otPlatAlarmGetNow() != 0) + if (sBlink == false && otPlatAlarmGetNow() != 0) { - mscounter_init = otPlatAlarmGetNow(); - blink = true; + sMsCounterInit = otPlatAlarmGetNow(); + sBlink = true; } - mscounter = otPlatAlarmGetNow() - mscounter_init; + sMsCounter = otPlatAlarmGetNow() - sMsCounterInit; switch (devRole) { @@ -121,10 +121,10 @@ void ExampleProcess(otInstance *aInstance) thrValue = 0x00; } - if ((thrValue != 0x00) && (mscounter >= thrValue)) + if ((thrValue != 0x00) && (sMsCounter >= thrValue)) { hw_gpio_toggle(HW_GPIO_PORT_1, HW_GPIO_PIN_5); - mscounter_init = otPlatAlarmGetNow(); + sMsCounterInit = otPlatAlarmGetNow(); } if (thrValue == 0) diff --git a/examples/platforms/da15000/radio.c b/examples/platforms/da15000/radio.c index c36994266..5a14dd31f 100644 --- a/examples/platforms/da15000/radio.c +++ b/examples/platforms/da15000/radio.c @@ -31,178 +31,35 @@ * Platform abstraction for radio communication. */ -#include -#include -#include -#include -#include #include #include #include -#include #include "platform-da15000.h" -#define DEBUG_LOG_ENABLE (0) - -#include #include -#include "ad_ftdf_phy_api.h" -#include "hw_rf.h" -#include +#include +#include +#include #include -#include "black_orca.h" -#include "core_cm0.h" -#include "internal.h" #include -typedef struct __attribute__((packed)) RadioMessage -{ - uint8_t mChannel; - uint8_t mPsdu[kMaxPHYPacketSize]; -} RadioMessage; - -static PhyState s_state = kStateDisabled; -static RadioMessage s_receive_message; -static RadioMessage s_transmit_message; -static RadioMessage s_ack_message; -static RadioPacket s_receive_frame; -static RadioPacket s_transmit_frame; -static RadioPacket s_ack_frame; -static bool s_data_pending = false; -static bool SendFrameDone = false; -static uint8_t s_extended_address[OT_EXT_ADDRESS_SIZE]; -static uint16_t s_short_address; -static uint16_t s_panid; - -//static int s_sockfd; - -static bool s_promiscuous = false; - -static uint8_t sleep_init_delay = 0; -static bool SED = false; -static uint32_t sleep_const_delay; - -static otInstance *First_Instace; -uint32_t NODE_ID = 1; - #define DEFAULT_CHANNEL (11) -#define FTDF_OFFSET_CHANNEL (11) -void disable_interrupt() -{ - NVIC_DisableIRQ(FTDF_GEN_IRQn); -} +static otInstance *sThreadInstance; -void enable_interrupt() -{ - NVIC_ClearPendingIRQ(FTDF_GEN_IRQn); - NVIC_EnableIRQ(FTDF_GEN_IRQn); -} +static PhyState sRadioState = kStateDisabled; +static uint8_t sChannel = DEFAULT_CHANNEL; +static uint8_t sTransmitPsdu[kMaxPHYPacketSize]; +static RadioPacket sTransmitFrame; +static bool sSendFrameDone = false; +static bool sRadioPromiscuous = false; -void phy_power_init() -{ - // Set the radio_ldo voltage to 1.4 Volts - REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_SETVDD, 2); - // Switch on the RF LDO - REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_ENABLE, 1); - hw_rf_poweron(); -} - - -void ad_ftdf_init_phy_api_V2(void) -{ - NVIC_ClearPendingIRQ(FTDF_WAKEUP_IRQn); - NVIC_EnableIRQ(FTDF_WAKEUP_IRQn); - - NVIC_ClearPendingIRQ(FTDF_GEN_IRQn); - NVIC_EnableIRQ(FTDF_GEN_IRQn); - - volatile uint32_t *lmacReset = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMACRESET); - *lmacReset = MSK_R_FTDF_ON_OFF_REGMAP_LMACRESET; - - volatile uint32_t *controlStatus = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMAC_CONTROL_STATUS); - - while ((*controlStatus & MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP) == 0) {} - - volatile uint32_t *wakeupTimerEnableStatus = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS); - FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE, 0); - - while (*wakeupTimerEnableStatus & MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS) {} - - FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE, 1); - - while ((*wakeupTimerEnableStatus & MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS) == 0) {} -} - -void ad_ftdf_init_lmac() -{ - FTDF_SET_FIELD(ON_OFF_REGMAP_CCAIDLEWAIT, 192); - volatile uint32_t *txFlagClear = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_CLEAR); - *txFlagClear = MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR; - - volatile uint32_t *phyParams = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_PHY_PARAMETERS_2); - *phyParams = (FTDF_PHYTXSTARTUP << OFF_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP) | - (FTDF_PHYTXLATENCY << OFF_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY) | - (FTDF_PHYTXFINISH << OFF_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH) | - (FTDF_PHYTRXWAIT << OFF_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT); - - phyParams = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_PHY_PARAMETERS_3); - *phyParams = (FTDF_PHYRXSTARTUP << OFF_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP) | - (FTDF_PHYRXLATENCY << OFF_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY) | - (FTDF_PHYENABLE << OFF_F_FTDF_ON_OFF_REGMAP_PHYENABLE); - - volatile uint32_t *ftdfCm = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_FTDF_CM); - *ftdfCm = FTDF_MSK_TX_CE | FTDF_MSK_RX_CE | FTDF_MSK_SYMBOL_TMR_CE; - - volatile uint32_t *rxMask = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_RX_MASK); - *rxMask = MSK_R_FTDF_ON_OFF_REGMAP_RX_MASK; - - volatile uint32_t *lmacMask = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMAC_MASK); - *lmacMask = MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M; - - volatile uint32_t *lmacCtrlMask = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMAC_CONTROL_MASK); - *lmacCtrlMask = MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M | - MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M | - MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M; - - volatile uint32_t *txFlagClearM; - txFlagClearM = FTDF_GET_FIELD_ADDR_INDEXED(ON_OFF_REGMAP_TX_FLAG_CLEAR_M, FTDF_TX_DATA_BUFFER); - *txFlagClearM |= MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M; - txFlagClearM = FTDF_GET_FIELD_ADDR_INDEXED(ON_OFF_REGMAP_TX_FLAG_CLEAR_M, FTDF_TX_WAKEUP_BUFFER); - *txFlagClearM |= MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M; -} - - - -void otPlatRadioSetPanId(otInstance *aInstance, uint16_t panid) -{ - (void)aInstance; - - s_panid = panid; - FTDF_setValue(FTDF_PIB_PAN_ID, &panid); -} - -void otPlatRadioSetExtendedAddress(otInstance *aInstance, uint8_t *address) -{ - (void)aInstance; - - for (unsigned i = 0; i < sizeof(s_extended_address); i++) - { - s_extended_address[i] = address[i]; - } - - FTDF_setValue(FTDF_PIB_EXTENDED_ADDRESS, s_extended_address); -} - -void otPlatRadioSetShortAddress(otInstance *aInstance, uint16_t address) -{ - (void)aInstance; - - s_short_address = address; - FTDF_setValue(FTDF_PIB_SHORT_ADDRESS, &address); -} +static uint32_t sSleepInitDelay = 0; +static uint32_t sSleepConstDelay; +static bool sSED = false; +uint32_t NODE_ID = 1; void da15000RadioInit(void) { @@ -218,263 +75,19 @@ void da15000RadioInit(void) REG_SETF(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_ENABLE, 1); REG_SETF(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_DIV, 0); - phy_power_init(); + hw_rf_poweron(); hw_rf_system_init(); - hw_rf_set_recommended_settings(); - hw_rf_iff_calibration(); - - hw_rf_modulation_gain_calibration(0); //RF MODE 0 - hw_rf_dc_offset_calibration(); - - // ad_ftdf_init_phy_api(); - FTDF_pib.CCAMode = 2; - ad_ftdf_init_phy_api_V2(); - ad_ftdf_init_lmac(); -} - - -ThreadError otPlatRadioEnable(otInstance *aInstance) -{ - First_Instace = aInstance; - (void)aInstance; - ThreadError error = kThreadError_None; - uint16_t DefaultChannel = DEFAULT_CHANNEL; - uint8_t value = 1; - - FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &value); //Wake(); - FTDF_setValue(FTDF_PIB_CURRENT_CHANNEL, &DefaultChannel); //SetChannel(channel); - - uint32_t max_retries = 0; - FTDF_setValue(FTDF_PIB_MAX_FRAME_RETRIES, &max_retries); - - FTDF_Bitmap32 options = FTDF_TRANSPARENT_ENABLE_FCS_GENERATION; - options |= FTDF_TRANSPARENT_WAIT_FOR_ACK; - options |= FTDF_TRANSPARENT_AUTO_ACK; - - FTDF_enableTransparentMode(FTDF_TRUE, options); - otPlatRadioSetPromiscuous(aInstance, false); - - s_receive_frame.mPsdu = s_receive_message.mPsdu; - s_transmit_frame.mPsdu = s_transmit_message.mPsdu; - s_ack_frame.mPsdu = s_ack_message.mPsdu; - s_state = kStateReceive; - return error; -} - -ThreadError otPlatRadioDisable(otInstance *aInstance) -{ - (void)aInstance; - s_state = kStateDisabled; - return kThreadError_None; -} - -bool otPlatRadioIsEnabled(otInstance *aInstance) -{ - (void)aInstance; - return (s_state != kStateDisabled); -} - -ThreadError otPlatRadioSleep(otInstance *aInstance) -{ - ThreadError error = kThreadError_Busy; - (void)aInstance; - - - if (s_state == kStateReceive && sleep_init_delay == 0) - { - sleep_init_delay = otPlatAlarmGetNow(); - return kThreadError_None; //error; - } - else if ((otPlatAlarmGetNow() - sleep_init_delay) < 3000) - { - return kThreadError_None; //error; - } - - if (s_state == kStateSleep || s_state == kStateReceive) - { - error = kThreadError_None; - SED = true; - sleep_const_delay = otPlatAlarmGetNow(); - } - - return error; -} - -ThreadError otPlatRadioReceive(otInstance *aInstance, uint8_t aChannel) -{ - ThreadError error = kThreadError_None; - (void)aInstance; - -#if DEBUG_LOG_ENABLE - hw_uart_write_buffer(HW_UART1, "\nR", 2); -#endif - VerifyOrExit(s_state != kStateDisabled, error = kThreadError_Busy); - s_state = kStateReceive; - s_receive_frame.mChannel = aChannel; - - uint32_t phyAckAttr; - phyAckAttr = 0x08 | ((aChannel - FTDF_OFFSET_CHANNEL) & 0xf) << 4; - FTDF_SET_FIELD(ON_OFF_REGMAP_PHYRXATTR, (((aChannel - FTDF_OFFSET_CHANNEL) & 0xf) << 4)); - FTDF_SET_FIELD(ON_OFF_REGMAP_PHYACKATTR, phyAckAttr); - - FTDF_SET_FIELD(ON_OFF_REGMAP_RXALWAYSON, 1); - FTDF_SET_FIELD(ON_OFF_REGMAP_RXENABLE, 1); - -exit: - return error; -} - -RadioPacket *otPlatRadioGetTransmitBuffer(otInstance *aInstance) -{ - (void)aInstance; - return &s_transmit_frame; -} - -ThreadError otPlatRadioTransmit(otInstance *aInstance, RadioPacket *aPacket) -{ - ThreadError error = kThreadError_None; - (void)aInstance; - - FTDF_Boolean csmaSuppress = 0; - VerifyOrExit(s_state == kStateReceive, error = kThreadError_Busy); - - ad_ftdf_send_frame_simple(aPacket->mLength, aPacket->mPsdu, aPacket->mChannel, 0, csmaSuppress); //Prio 0 for all. - s_state = kStateTransmit; - s_data_pending = false; -#if DEBUG_LOG_ENABLE - hw_uart_write_buffer(HW_UART1, "\nT", 2); -#endif - -exit: - return error; -} - - -int8_t otPlatRadioGetRssi(otInstance *aInstance) -{ - (void)aInstance; - return 0; -} - -otRadioCaps otPlatRadioGetCaps(otInstance *aInstance) -{ - (void)aInstance; - return kRadioCapsNone; -} - -void otPlatRadioSetPromiscuous(otInstance *aInstance, bool aEnable) -{ - (void)aInstance; - uint8_t value; - value = aEnable; - FTDF_setValue(FTDF_PIB_PROMISCUOUS_MODE, &value); - s_promiscuous = aEnable; -} - -bool otPlatRadioGetPromiscuous(otInstance *aInstance) -{ - (void)aInstance; - return s_promiscuous; -} - -ThreadError otPlatRadioHandleTransmitDone(bool *rxPending) -{ - ThreadError error = kThreadError_None; - VerifyOrExit(s_state == kStateTransmit, error = kThreadError_InvalidState); - - s_state = kStateReceive; - - if (rxPending != NULL) - { - *rxPending = s_data_pending; - } - -exit: - return error; -} - - - - -void FTDF_sendFrameTransparentConfirm(void *handle, FTDF_Bitmap32 status) -{ - (void)handle; - (void)status; - volatile uint32_t *txStatus = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_RETURN_STATUS_1, FTDF_TX_DATA_BUFFER); - - SendFrameDone = true; - -#if DEBUG_LOG_ENABLE - hw_uart_write_buffer(HW_UART1, "\nTD", 3); -#endif -} - - - -void da15000RadioProcess(otInstance *aInstance) -{ - bool rxPending; - uint8_t bufferForFTDFconfigValue = 0; - - if (SendFrameDone) - { - FTDF_SET_FIELD(ON_OFF_REGMAP_RXENABLE, 1); - otPlatRadioHandleTransmitDone(&rxPending); - otPlatRadioTransmitDone(aInstance, &s_transmit_frame, false, kThreadError_None); - SendFrameDone = false; - } - - if ((SED) && ((otPlatAlarmGetNow() - sleep_const_delay) > 100)) - { - FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &bufferForFTDFconfigValue); - s_state = kStateSleep; - SED = false; - } -} - - - -void FTDF_rcvFrameTransparent(FTDF_DataLength frameLength, - FTDF_Octet *frame, - FTDF_Bitmap32 status, - FTDF_LinkQuality lqi) -{ - (void)status; - RadioPacket otRadioPacket; - -#if DEBUG_LOG_ENABLE - char buff[10]; - sprintf(buff, "\nlq:%d", lqi); - hw_uart_write_buffer(HW_UART1, buff, 5); -#endif - - otRadioPacket.mPower = kPhyInvalidRssi; - otRadioPacket.mLqi = lqi; - - if (s_receive_frame.mChannel == 0) - { - s_receive_frame.mChannel = DEFAULT_CHANNEL; - } - - otRadioPacket.mChannel = s_receive_frame.mChannel; - otRadioPacket.mLength = frameLength; - otRadioPacket.mPsdu = frame; - - otPlatRadioReceiveDone(First_Instace, &otRadioPacket, kThreadError_None); - - if (s_state != kStateDisabled) - { - s_state = kStateReceive; - } + ad_ftdf_init_phy_api(); } void otPlatRadioGetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64) { (void)aInstance; - aIeeeEui64[0] = 0x80; //80-EA-CA is for Dialog Semiconductor - aIeeeEui64[1] = 0xEA; - aIeeeEui64[2] = 0xCA; + + aIeeeEui64[0] = 0x18; + aIeeeEui64[1] = 0xb4; + aIeeeEui64[2] = 0x30; aIeeeEui64[3] = 0x00; aIeeeEui64[4] = (NODE_ID >> 24) & 0xff; aIeeeEui64[5] = (NODE_ID >> 16) & 0xff; @@ -482,77 +95,280 @@ void otPlatRadioGetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64) aIeeeEui64[7] = NODE_ID & 0xff; } -ThreadError otPlatRadioEnergyScan(otInstance *aInstance, uint8_t aScanChannel, uint16_t aScanDuration) +void otPlatRadioSetPanId(otInstance *aInstance, uint16_t panid) { - ThreadError error = kThreadError_NotImplemented; (void)aInstance; - (void)aScanChannel; - (void)aScanDuration; + + FTDF_setValue(FTDF_PIB_PAN_ID, &panid); +} + +void otPlatRadioSetExtendedAddress(otInstance *aInstance, uint8_t *address) +{ + (void)aInstance; + + FTDF_setValue(FTDF_PIB_EXTENDED_ADDRESS, address); +} + +void otPlatRadioSetShortAddress(otInstance *aInstance, uint16_t address) +{ + (void)aInstance; + + FTDF_setValue(FTDF_PIB_SHORT_ADDRESS, &address); +} + +ThreadError otPlatRadioEnable(otInstance *aInstance) +{ + uint8_t DefaultChannel; + uint8_t EnableRX; + uint8_t MaxRetries; + + ThreadError error = kThreadError_None; + VerifyOrExit(sRadioState == kStateDisabled, error = kThreadError_InvalidState); + + sThreadInstance = aInstance; + sTransmitFrame.mPsdu = sTransmitPsdu; + + EnableRX = 1; + FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &EnableRX); + DefaultChannel = DEFAULT_CHANNEL; + FTDF_setValue(FTDF_PIB_CURRENT_CHANNEL, &DefaultChannel); + MaxRetries = 0; + FTDF_setValue(FTDF_PIB_MAX_FRAME_RETRIES, &MaxRetries); + + FTDF_Bitmap32 options = FTDF_TRANSPARENT_ENABLE_FCS_GENERATION; + options |= FTDF_TRANSPARENT_WAIT_FOR_ACK; + options |= FTDF_TRANSPARENT_AUTO_ACK; + + FTDF_enableTransparentMode(FTDF_TRUE, options); + otPlatRadioSetPromiscuous(aInstance, false); + sRadioState = kStateSleep; + +exit: + return error; +} + +ThreadError otPlatRadioDisable(otInstance *aInstance) +{ + (void)aInstance; + + sRadioState = kStateDisabled; + + return kThreadError_None; +} + +bool otPlatRadioIsEnabled(otInstance *aInstance) +{ + (void)aInstance; + + return (sRadioState != kStateDisabled) ? true : false; +} + +ThreadError otPlatRadioSleep(otInstance *aInstance) +{ + (void)aInstance; + + if (sRadioState == kStateReceive && sSleepInitDelay == 0) + { + sSleepInitDelay = otPlatAlarmGetNow(); + return kThreadError_None; + } + else if ((otPlatAlarmGetNow() - sSleepInitDelay) < 3000) + { + return kThreadError_None; + } + + if (sRadioState == kStateSleep || sRadioState == kStateReceive) + { + sSED = true; + sSleepConstDelay = otPlatAlarmGetNow(); + } + + return kThreadError_None; +} + +ThreadError otPlatRadioReceive(otInstance *aInstance, uint8_t aChannel) +{ + (void)aInstance; + + uint8_t EnableRX; + + ThreadError error = kThreadError_None; + VerifyOrExit(sRadioState != kStateDisabled, error = kThreadError_InvalidState); + + ad_ftdf_wake_up(); + sChannel = aChannel; + FTDF_setValue(FTDF_PIB_CURRENT_CHANNEL, &aChannel); + EnableRX = 1; + FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &EnableRX); + sRadioState = kStateReceive; + +exit: return error; } void otPlatRadioEnableSrcMatch(otInstance *aInstance, bool aEnable) { - (void)aInstance; (void)aEnable; - } ThreadError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress) { - - ThreadError error = kThreadError_NotImplemented; (void)aInstance; (void)aShortAddress; - return error; - + return kThreadError_NotImplemented; } ThreadError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const uint8_t *aExtAddress) { - - ThreadError error = kThreadError_NotImplemented; (void)aInstance; (void)aExtAddress; - return error; + return kThreadError_NotImplemented; } ThreadError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress) { - - ThreadError error = kThreadError_NotImplemented; (void)aInstance; (void)aShortAddress; - return error; + return kThreadError_NotImplemented; } ThreadError otPlatRadioClearSrcMatchExtEntry(otInstance *aInstance, const uint8_t *aExtAddress) { - - ThreadError error = kThreadError_NotImplemented; (void)aExtAddress; (void)aInstance; - return error; + return kThreadError_NotImplemented; } void otPlatRadioClearSrcMatchShortEntries(otInstance *aInstance) { - (void)aInstance; } void otPlatRadioClearSrcMatchExtEntries(otInstance *aInstance) { - (void)aInstance; } +RadioPacket *otPlatRadioGetTransmitBuffer(otInstance *aInstance) +{ + (void)aInstance; + return &sTransmitFrame; +} +ThreadError otPlatRadioTransmit(otInstance *aInstance, RadioPacket *aPacket) +{ + (void)aInstance; + uint8_t csmaSuppress; + + ThreadError error = kThreadError_None; + VerifyOrExit(sRadioState != kStateDisabled, error = kThreadError_InvalidState); + + csmaSuppress = 0; + ad_ftdf_send_frame_simple(aPacket->mLength, aPacket->mPsdu, aPacket->mChannel, 0, csmaSuppress); //Prio 0 for all. + sRadioState = kStateTransmit; + +exit: + return error; +} + +int8_t otPlatRadioGetRssi(otInstance *aInstance) +{ + (void)aInstance; + + return 0; +} + +otRadioCaps otPlatRadioGetCaps(otInstance *aInstance) +{ + (void)aInstance; + + return kRadioCapsNone; +} + +bool otPlatRadioGetPromiscuous(otInstance *aInstance) +{ + (void)aInstance; + + return sRadioPromiscuous; +} + +void otPlatRadioSetPromiscuous(otInstance *aInstance, bool aEnable) +{ + (void)aInstance; + + FTDF_setValue(FTDF_PIB_PROMISCUOUS_MODE, &aEnable); + sRadioPromiscuous = aEnable; +} + +ThreadError otPlatRadioEnergyScan(otInstance *aInstance, uint8_t aScanChannel, uint16_t aScanDuration) +{ + (void)aInstance; + (void)aScanChannel; + (void)aScanDuration; + + return kThreadError_NotImplemented; +} + +void da15000RadioProcess(otInstance *aInstance) +{ + uint8_t EnableRX; + + if (sSendFrameDone) + { + sRadioState = kStateReceive; + otPlatRadioTransmitDone(aInstance, &sTransmitFrame, false, kThreadError_None); + sSendFrameDone = false; + } + + if (sSED) + { + if ((otPlatAlarmGetNow() - sSleepConstDelay) > 100) + { + EnableRX = 0; + FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &EnableRX); + ad_ftdf_sleep_when_possible(1); + sRadioState = kStateSleep; + sSED = false; + } + } +} + +void FTDF_sendFrameTransparentConfirm(void *handle, FTDF_Bitmap32 status) +{ + (void)handle; + (void)status; + + sSendFrameDone = true; +} + +void FTDF_rcvFrameTransparent(FTDF_DataLength frameLength, + FTDF_Octet *frame, + FTDF_Bitmap32 status, + FTDF_LinkQuality lqi) +{ + (void)status; + + RadioPacket otRadioPacket; + + otRadioPacket.mPower = kPhyInvalidRssi; + otRadioPacket.mLqi = lqi; + + otRadioPacket.mChannel = sChannel; + otRadioPacket.mLength = frameLength; + otRadioPacket.mPsdu = frame; + + otPlatRadioReceiveDone(sThreadInstance, &otRadioPacket, kThreadError_None); + + if (sRadioState != kStateDisabled) + { + sRadioState = kStateReceive; + } +} diff --git a/examples/platforms/da15000/random.c b/examples/platforms/da15000/random.c index 7ba2ef562..129beb517 100644 --- a/examples/platforms/da15000/random.c +++ b/examples/platforms/da15000/random.c @@ -36,7 +36,7 @@ #include #include "platform-da15000.h" -#include "black_orca.h" +#include "sdk_defs.h" #include "hw_trng.h" #include @@ -44,8 +44,8 @@ #define HW_TRNG_RAM (0x40040000) -static uint32_t s_state = 1; -static uint32_t seed; +static uint32_t sState = 1; +static uint32_t sSeed; int zhal_get_entropy(uint8_t *outEntropy, size_t inSize) { @@ -82,8 +82,8 @@ int zhal_get_entropy(uint8_t *outEntropy, size_t inSize) void da15000RandomInit(void) { - zhal_get_entropy((uint8_t *)&seed, sizeof(seed)); - s_state = seed; + zhal_get_entropy((uint8_t *)&sSeed, sizeof(sSeed)); + sState = sSeed; } uint32_t otPlatRandomGet(void) diff --git a/examples/platforms/da15000/uart.c b/examples/platforms/da15000/uart.c index 2db5d4f4f..4476dc29c 100644 --- a/examples/platforms/da15000/uart.c +++ b/examples/platforms/da15000/uart.c @@ -37,8 +37,8 @@ #include "hw_gpio.h" #include "platform-da15000.h" -static int s_in_fd; -static int s_out_fd; +static int sInFd; +static int sOutFd; void UartBuffClear(void); ThreadError otPlatUartEnable(void) @@ -72,8 +72,8 @@ ThreadError otPlatUartDisable(void) { ThreadError error = kThreadError_None; - close(s_in_fd); - close(s_out_fd); + close(sInFd); + close(sOutFd); return error; } diff --git a/third_party/dialog/DialogSDK/bsp/adapters/include/ad_rf.h b/third_party/dialog/DialogSDK/bsp/adapters/include/ad_rf.h old mode 100755 new mode 100644 index 5a748dca9..187bde671 --- a/third_party/dialog/DialogSDK/bsp/adapters/include/ad_rf.h +++ b/third_party/dialog/DialogSDK/bsp/adapters/include/ad_rf.h @@ -41,22 +41,23 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * ***************************************************************************************** */ + + + #ifndef AD_RF_H_ #define AD_RF_H_ #if dg_configRF_ADAPTER + #include #include -//#include "platform_devices.h" #include "hw_rf.h" - - - /** * @brief Performs RF adapter initialization */ @@ -111,9 +112,7 @@ static inline void ad_rf_system_init() */ static inline void ad_rf_start_calibration() { - // OS_ENTER_CRITICAL_SECTION(); ad_rf_start_and_check_calibration(); - // OS_LEAVE_CRITICAL_SECTION(); } /** @@ -125,9 +124,7 @@ static inline void ad_rf_start_calibration() */ static inline void ad_rf_request_recommended_settings(void) { - // OS_ENTER_CRITICAL_SECTION(); hw_rf_request_recommended_settings(); - // OS_LEAVE_CRITICAL_SECTION(); } /** @@ -140,9 +137,7 @@ static inline void ad_rf_request_recommended_settings(void) */ static inline void ad_rf_request_on(bool mode_ble) { - // OS_ENTER_CRITICAL_SECTION(); hw_rf_request_on(mode_ble); - // OS_LEAVE_CRITICAL_SECTION(); } /** @@ -157,11 +152,7 @@ static inline void ad_rf_request_on(bool mode_ble) */ static inline void ad_rf_request_off(bool mode_ble) { - // ad_gpadc_acquire(); - // OS_ENTER_CRITICAL_SECTION(); hw_rf_request_off(mode_ble); - // OS_LEAVE_CRITICAL_SECTION(); - // ad_gpadc_release(); } #endif /* dg_configRF_ADAPTER */ diff --git a/third_party/dialog/DialogSDK/bsp/arm_license.txt b/third_party/dialog/DialogSDK/bsp/arm_license.txt index dab1e859c..e3e89d4cb 100755 --- a/third_party/dialog/DialogSDK/bsp/arm_license.txt +++ b/third_party/dialog/DialogSDK/bsp/arm_license.txt @@ -1,26 +1,26 @@ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ \ No newline at end of file diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h b/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h old mode 100755 new mode 100644 index 18062d050..d22e149cc --- a/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h +++ b/third_party/dialog/DialogSDK/bsp/config/bsp_debug.h @@ -1,3 +1,16 @@ +/** + * \addtogroup BSP + * \{ + * \addtogroup BSP_CONFIG + * \{ + * \addtogroup BSP_DEBUG + * + * \brief Doxygen documentation is not yet available for this module. + * Please check the source code file(s) + * + * \{ +*/ + /** **************************************************************************************** * @@ -28,7 +41,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * **************************************************************************************** */ @@ -136,6 +150,10 @@ #define DEBUG_USB_CHARGER_FSM (0) #endif +#ifndef DEBUG_USB_CHARGER_PRINT +#define DEBUG_USB_CHARGER_PRINT (0) +#endif + #ifndef USB_CHARGER_TIMING_DEBUG #define USB_CHARGER_TIMING_DEBUG (0) #endif @@ -181,20 +199,36 @@ /* ---------------------------------------------------------------------------------------------- */ + +/* ------------------------------------------ Flash --------------------------------------------- */ +#ifndef FLASH_DEBUG +#define FLASH_DEBUG (0) // Requires GPIO config. +#endif + +#ifndef __DBG_QSPI_ENABLED +#define __DBG_QSPI_ENABLED (0) +#endif + /* ---------------------------------------------------------------------------------------------- */ + /* ------------------------------------------ Common -------------------------------------------- */ #ifndef CMN_TIMING_DEBUG -#define CMN_TIMING_DEBUG (0) // Requires GPIO config. +#define CMN_TIMING_DEBUG (0) // Requires GPIO config. #endif /* ---------------------------------------------------------------------------------------------- */ +/* -------------------------------------------- SPI --------------------------------------------- */ +#ifndef SPI_TIMING_DEBUG +#define SPI_TIMING_DEBUG (0) // Requires GPIO config. +#endif +/* ---------------------------------------------------------------------------------------------- */ /* ------------------------------------ GPIO configuration -------------------------------------- */ /* Enable/Disable GPIO pin assignment conflict detection */ -#define DEBUG_GPIO_ALLOC_MONITOR_ENABLED (0) +#define DEBUG_GPIO_ALLOC_MONITOR_ENABLED (0) /* Exception handling debug configuration @@ -447,6 +481,111 @@ #endif +/* Flash debug configuration + * + */ +#if (FLASH_DEBUG == 0) +// Write page (initial configuration: low) +#define FLASHDBG_PAGE_PROG_MODE_REG *(volatile int *)0x20000000 +#define FLASHDBG_PAGE_PROG_SET_REG *(volatile int *)0x20000000 +#define FLASHDBG_PAGE_PROG_RESET_REG *(volatile int *)0x20000000 +#define FLASHDBG_PAGE_PROG_PIN (0) + +// Program page wait loop (initial configuration: low) +#define FLASHDBG_PAGE_PROG_WL_MODE_REG *(volatile int *)0x20000000 +#define FLASHDBG_PAGE_PROG_WL_SET_REG *(volatile int *)0x20000000 +#define FLASHDBG_PAGE_PROG_WL_RESET_REG *(volatile int *)0x20000000 +#define FLASHDBG_PAGE_PROG_WL_PIN (0) + +// Program page wait loop - pending irq check (initial configuration: low) +#define FLASHDBG_PAGE_PROG_WL_IRQ_MODE_REG *(volatile int *)0x20000000 +#define FLASHDBG_PAGE_PROG_WL_IRQ_SET_REG *(volatile int *)0x20000000 +#define FLASHDBG_PAGE_PROG_WL_IRQ_RESET_REG *(volatile int *)0x20000000 +#define FLASHDBG_PAGE_PROG_WL_IRQ_PIN (0) + +// Suspend op (initial configuration: low) +#define FLASHDBG_SUSPEND_MODE_REG *(volatile int *)0x20000000 +#define FLASHDBG_SUSPEND_SET_REG *(volatile int *)0x20000000 +#define FLASHDBG_SUSPEND_RESET_REG *(volatile int *)0x20000000 +#define FLASHDBG_SUSPEND_PIN (0) + +// Erase sector cmd (initial configuration: low) +#define FLASHDBG_SECTOR_ERASE_MODE_REG *(volatile int *)0x20000000 +#define FLASHDBG_SECTOR_ERASE_SET_REG *(volatile int *)0x20000000 +#define FLASHDBG_SECTOR_ERASE_RESET_REG *(volatile int *)0x20000000 +#define FLASHDBG_SECTOR_ERASE_PIN (0) + +// Notify task (initial configuration: low) +#define FLASHDBG_TASK_NOTIFY_MODE_REG *(volatile int *)0x20000000 +#define FLASHDBG_TASK_NOTIFY_SET_REG *(volatile int *)0x20000000 +#define FLASHDBG_TASK_NOTIFY_RESET_REG *(volatile int *)0x20000000 +#define FLASHDBG_TASK_NOTIFY_PIN (0) + +// Suspend action (low level) (initial configuration: low) +#define FLASHDBG_SUSPEND_ACTION_MODE_REG *(volatile int *)0x20000000 +#define FLASHDBG_SUSPEND_ACTION_SET_REG *(volatile int *)0x20000000 +#define FLASHDBG_SUSPEND_ACTION_RESET_REG *(volatile int *)0x20000000 +#define FLASHDBG_SUSPEND_ACTION_PIN (0) + +// Resume op (initial configuration: low) +#define FLASHDBG_RESUME_MODE_REG *(volatile int *)0x20000000 +#define FLASHDBG_RESUME_SET_REG *(volatile int *)0x20000000 +#define FLASHDBG_RESUME_RESET_REG *(volatile int *)0x20000000 +#define FLASHDBG_RESUME_PIN (0) + +#else + +// Write page (initial configuration: low) +#define FLASHDBG_PAGE_PROG_MODE_REG GPIO->P30_MODE_REG +#define FLASHDBG_PAGE_PROG_SET_REG GPIO->P3_SET_DATA_REG +#define FLASHDBG_PAGE_PROG_RESET_REG GPIO->P3_RESET_DATA_REG +#define FLASHDBG_PAGE_PROG_PIN (1 << 0) + +// Program page wait loop (initial configuration: low) +#define FLASHDBG_PAGE_PROG_WL_MODE_REG GPIO->P31_MODE_REG +#define FLASHDBG_PAGE_PROG_WL_SET_REG GPIO->P3_SET_DATA_REG +#define FLASHDBG_PAGE_PROG_WL_RESET_REG GPIO->P3_RESET_DATA_REG +#define FLASHDBG_PAGE_PROG_WL_PIN (1 << 1) + +// Program page wait loop - pending irq check (initial configuration: low) +#define FLASHDBG_PAGE_PROG_WL_IRQ_MODE_REG GPIO->P32_MODE_REG +#define FLASHDBG_PAGE_PROG_WL_IRQ_SET_REG GPIO->P3_SET_DATA_REG +#define FLASHDBG_PAGE_PROG_WL_IRQ_RESET_REG GPIO->P3_RESET_DATA_REG +#define FLASHDBG_PAGE_PROG_WL_IRQ_PIN (1 << 2) + +// Suspend op (initial configuration: low) +#define FLASHDBG_SUSPEND_MODE_REG GPIO->P33_MODE_REG +#define FLASHDBG_SUSPEND_SET_REG GPIO->P3_SET_DATA_REG +#define FLASHDBG_SUSPEND_RESET_REG GPIO->P3_RESET_DATA_REG +#define FLASHDBG_SUSPEND_PIN (1 << 3) + +// Erase sector cmd (initial configuration: low) +#define FLASHDBG_SECTOR_ERASE_MODE_REG GPIO->P34_MODE_REG +#define FLASHDBG_SECTOR_ERASE_SET_REG GPIO->P3_SET_DATA_REG +#define FLASHDBG_SECTOR_ERASE_RESET_REG GPIO->P3_RESET_DATA_REG +#define FLASHDBG_SECTOR_ERASE_PIN (1 << 4) + +// Notify task (initial configuration: low) +#define FLASHDBG_TASK_NOTIFY_MODE_REG GPIO->P35_MODE_REG +#define FLASHDBG_TASK_NOTIFY_SET_REG GPIO->P3_SET_DATA_REG +#define FLASHDBG_TASK_NOTIFY_RESET_REG GPIO->P3_RESET_DATA_REG +#define FLASHDBG_TASK_NOTIFY_PIN (1 << 5) + +// Suspend action (low level) (initial configuration: low) +#define FLASHDBG_SUSPEND_ACTION_MODE_REG GPIO->P36_MODE_REG +#define FLASHDBG_SUSPEND_ACTION_SET_REG GPIO->P3_SET_DATA_REG +#define FLASHDBG_SUSPEND_ACTION_RESET_REG GPIO->P3_RESET_DATA_REG +#define FLASHDBG_SUSPEND_ACTION_PIN (1 << 6) + +// Resume op (initial configuration: low) +#define FLASHDBG_RESUME_MODE_REG GPIO->P37_MODE_REG +#define FLASHDBG_RESUME_SET_REG GPIO->P3_SET_DATA_REG +#define FLASHDBG_RESUME_RESET_REG GPIO->P3_RESET_DATA_REG +#define FLASHDBG_RESUME_PIN (1 << 7) + +#endif + + /* Enables the logging of stack (RW) heap memories usage. * * The feature shall only be enabled in development/debug mode @@ -455,6 +594,37 @@ #define dg_configLOG_BLE_STACK_MEM_USAGE (0) #endif +/** + * \brief Enables BLE diagnostic signals. + * + * There are 4 diagnostic signal configurations that user can choose from. To enable a specific + * configuration, simply define dg_configBLE_DIAGN_CONFIG with the perspective configuration ID. + * Configuration ID 0 disables BLE diagnostics. + * + * ------------------------------------------------------------------------------------------------------ + * | Signal | Pin | Config 1 | Config 2 | Config 3 | Config 4 | + * ------------------------------------------------------------------------------------------------------ + * | ble_diag0 | P2_0 | - | - | - | - | + * ------------------------------------------------------------------------------------------------------ + * | ble_diag1 | P2_1 | - | - | - | - | + * ------------------------------------------------------------------------------------------------------ + * | ble_diag2 | P2_2 | - | - | - | - | + * ------------------------------------------------------------------------------------------------------ + * | ble_diag3 | P1_0 | - | - | - | - | + * ------------------------------------------------------------------------------------------------------ + * | ble_diag4 | P1_1 | ble_slp_irq | radcntl_txen | radcntl_txen | radcntl_txen | + * ------------------------------------------------------------------------------------------------------ + * | ble_diag5 | P1_2 | ble_cscnt_irq | radcntl_rxen | rf_tx_en | radcntl_rxen | + * ------------------------------------------------------------------------------------------------------ + * | ble_diag6 | P1_3 | ble_finetgtim_irq | rf_rx_en | rf_tx_data | ble_rx_irq | + * ------------------------------------------------------------------------------------------------------ + * | ble_diag7 | P2_3 | ble_event_irq | rf_rx_data | rf_tx_data_valid | ble_event_irq | + * ------------------------------------------------------------------------------------------------------ + */ +#ifndef dg_configBLE_DIAGN_CONFIG +#define dg_configBLE_DIAGN_CONFIG (0) +#endif + #endif /* BSP_DEBUG_H_ */ /** diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h b/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h old mode 100755 new mode 100644 index bb4094c4b..b58268a56 --- a/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h +++ b/third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h @@ -1,9 +1,32 @@ /** -**************************************************************************************** -* -* @file bsp_defaults.h -* -* @brief Board Support Package. System Configuration file default values. + * \addtogroup BSP + * \{ + * \addtogroup BSP_CONFIG + * \{ + * \addtogroup BSP_CONFIG_DEFAULTS + * + * \brief Board support package default configuration values + * + * The following tags are used to describe the type of each configuration option. + * + * - **\bsp_config_option_build** : To be changed only in the build configuration + * of the project ("Defined symbols -D" in the + * preprocessor options). + * + * - **\bsp_config_option_app** : To be changed only in the custom_config*.h + * project files. + * + * - **\bsp_config_option_expert_only** : To be changed only by an expert user. + * \{ + */ + +/** + **************************************************************************************** + * + * @file bsp_defaults.h + * + * @brief Board Support Package. System Configuration file default values. + * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -27,57 +50,38 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * -**************************************************************************************** + * + * + *************************************************************************************** */ #ifndef BSP_DEFAULTS_H_ #define BSP_DEFAULTS_H_ + + + /** * \addtogroup POWER_SETTINGS * + * \brief Power configuration settings * \{ */ - /* -------------------------------------- Power settings ---------------------------------------- */ -/** - * \brief Controls the power-mode of the application. +/* + * This is a deprecated configuration hence not to be defined by an application. + * There's a single power configuration setup. */ -#ifndef dg_configPOWER_CONFIG -#define dg_configPOWER_CONFIG (POWER_CONFIGURATION_1) +#ifdef dg_configPOWER_CONFIG +#error "Configuration option dg_configPOWER_CONFIG is no longer supported." #endif /** - * \brief Code to disable the debugger and its pins and reset any floating GPIOs to avoid leakage. - */ -#ifndef dg_codeCUT_DEBUGGER_PINS_LEAKAGE -#define dg_codeCUT_DEBUGGER_PINS_LEAKAGE \ - do { \ - if (0) { \ - GPIO->P15_MODE_REG = 0x200; \ - GPIO->P16_MODE_REG = 0x200; \ - hw_cpm_disable_debugger(); \ - } \ - } while (0) -#endif - -/** - * \brief Code to restore the debugger and its pins after waking-up. - */ -#ifndef dg_codeRESTORE_DEBUGGER_PINS -#define dg_codeRESTORE_DEBUGGER_PINS \ - do { \ - if (0) { \ - hw_cpm_enable_debugger(); \ - } \ - } while (0) -#endif - -/** - * When set to 1, the system will go to sleep and never exit allowing for the sleep current to be - * measured. + * \brief When set to 1, the system will go to sleep and never exit allowing for the sleep current to be + * measured. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configTESTMODE_MEASURE_SLEEP_CURRENT #define dg_configTESTMODE_MEASURE_SLEEP_CURRENT (0) @@ -85,7 +89,131 @@ /* ---------------------------------------------------------------------------------------------- */ /** - * \} POWER_SETTINGS + * \} + */ + +/** + * \addtogroup IMAGE_CONFIGURATION_SETTINGS + * + * \brief Image configuration settings. + * \{ + */ +/* ------------------------------- Image configuration settings --------------------------------- */ + +/** + * \brief The chip revision that we compile for. + * + * \note There is no default value defined for the target chip revision. The application must\n + * neither explicitly set dg_configBLACK_ORCA_IC_REV, nor set\n + * dg_configUSE_AUTO_CHIP_DETECTION to 1. + * + * \bsp_default_note{\bsp_config_option_build,} + */ +#ifndef dg_configBLACK_ORCA_IC_REV +# if dg_configUSE_AUTO_CHIP_DETECTION != 1 +# error "You must either define dg_configBLACK_ORCA_IC_REV in the build configuration or set dg_configUSE_AUTO_CHIP_DETECTION to 1" +# endif +#endif + +/** + * \brief The chip stepping that we compile for. + * + * \note There is no default value defined for the target chip revision. The application must\n + * either explicitly set dg_configBLACK_ORCA_IC_STEP nor set\n + * dg_configUSE_AUTO_CHIP_DETECTION to 1. + * + * \bsp_default_note{\bsp_config_option_build,} + */ +#ifndef dg_configBLACK_ORCA_IC_STEP +# if dg_configUSE_AUTO_CHIP_DETECTION != 1 +# error "You must either define dg_configBLACK_ORCA_IC_STEP in the build configuration or set dg_configUSE_AUTO_CHIP_DETECTION to 1" +# endif +#endif + +/** + * \brief The motherboard revision we compile for. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configBLACK_ORCA_MB_REV +#define dg_configBLACK_ORCA_MB_REV BLACK_ORCA_MB_REV_D +#endif + +/* + * This is a deprecated configuration hence not to be defined by an application. + * The values of the trim registers are not anymore taken from the Flash. + * + */ +#ifdef dg_configCONFIG_HEADER_IN_FLASH +#error "Configuration option dg_configCONFIG_HEADER_IN_FLASH is no longer supported." +#endif + +/** + * \brief Controls how the image is built. + * - DEVELOPMENT_MODE: various debugging options are included. + * - PRODUCTION_MODE: all code used for debugging is removed. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configIMAGE_SETUP +#define dg_configIMAGE_SETUP DEVELOPMENT_MODE +#endif + +/** + * \brief When set to 1, the delay at the start of execution of the Reset_Handler is skipped. + * + * \details This delay is added in order to facilitate proper programming of the Flash or QSPI\n + * launcher invocation. Without it, there is no guarantee that the execution of the image\n + * will not proceed, altering the default configuration of the system from the one that the\n + * bootloader leaves it. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configSKIP_MAGIC_CHECK_AT_START +#define dg_configSKIP_MAGIC_CHECK_AT_START (0) +#endif + +/** + * \brief When set to 1, the chip version (DA14680/1-01 or DA14682/3-BA ) will be detected\n + * automatically. + * \note It cannot be used in BLE applications because of the different linker scripts\n + * that are used. + * \warning Not to be used by a generic project, applicable for uartboot only. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configUSE_AUTO_CHIP_DETECTION +#define dg_configUSE_AUTO_CHIP_DETECTION (0) +#else +# if (dg_configUSE_AUTO_CHIP_DETECTION == 1) + #undef dg_configBLACK_ORCA_IC_REV + #define dg_configBLACK_ORCA_IC_REV BLACK_ORCA_IC_REV_AUTO + #undef dg_configBLACK_ORCA_IC_STEP + #define dg_configBLACK_ORCA_IC_STEP BLACK_ORCA_IC_STEP_AUTO +# endif +#endif + +/** + * \brief When set to 1, the OTP copy will be emulated when in DEVELOPMENT_MODE. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configEMULATE_OTP_COPY +#define dg_configEMULATE_OTP_COPY (0) +#endif + +/** + * \brief When set to 1, the QSPI copy will be emulated when in DEVELOPMENT_MODE (Not Applicable!). + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configEMULATE_QSPI_COPY +#define dg_configEMULATE_QSPI_COPY (0) +#endif +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} */ /** @@ -93,9 +221,10 @@ * * \brief Doxygen documentation is not yet available for this module. * Please check the source code file(s) + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} * \{ */ - /* --------------------------------- Low-Power clock settings ----------------------------------- */ /* @@ -103,23 +232,51 @@ * * dg_configTim1Prescaler can be zero. if dg_configTim1Prescaler is not zero then * ( dg_configTim1Prescaler + 1 ) MUST be a power of 2! */ +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A #if (dg_configUSE_LP_CLK == LP_CLK_32000) #define dg_configTim1Prescaler (3) -#define dg_configMaxSleepTime (8) // msec +#define dg_configMaxSleepTime (8) // sec #elif (dg_configUSE_LP_CLK == LP_CLK_32768) #define dg_configTim1Prescaler (3) -#define dg_configMaxSleepTime (8) // msec +#define dg_configMaxSleepTime (8) // sec #elif (dg_configUSE_LP_CLK == LP_CLK_RCX) #define dg_configTim1Prescaler (0) -#define dg_configMaxSleepTime (8) // msec +#define dg_configMaxSleepTime (8) // sec +#elif (dg_configUSE_LP_CLK == LP_CLK_ANY) +/* Assuming that the frequency of the external digital clock is 32000Hz, + * period: 1/32000 = 31.25usec + * Timer1 wrap-around time: 65536 * 31.25 = 2.048sec + * With a prescaler equal to 3, the wrap around time becomes: (1 + 3) * 2.048 = ~8sec. + * If the clock frequency is too slow, i.e. 16000Hz then + * period: 1/16000 = 62.5usec + * Timer1 wrap-around time = 65536 * 62.5 = 4.096sec + * and the prescaler should be 1 so that: (1 + 1) * 4.096 = ~8sec. + * If the clock frequency is too high, i.e. 125000Hz then + * period: 1/125000 = 8usec + * Timer1 wrap-around time = 65536 * 8 = 0.524sec + * and the prescaler should be 3 so that: (1 + 3) * 0.524 = ~2sec. + * The values MUST be defined in the custom_config_<>.h file! + */ #else #error "dg_configUSE_LP_CLK has invalid setting" #endif +#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A */ +#if (dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768) || (dg_configUSE_LP_CLK == LP_CLK_RCX) +#ifdef dg_configTim1Prescaler +#warning "Timer1 prescaler is not supported in DA14682/3 chips." +#undef dg_configTim1Prescaler +#endif /* dg_configTim1Prescaler */ +#define dg_configMaxSleepTime (134217) // sec +#else +#error "dg_configUSE_LP_CLK has invalid setting" +#endif +#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A */ #if (dg_configTim1Prescaler && (((dg_configTim1Prescaler+1) / 2) * 2) != (dg_configTim1Prescaler+1)) #error "dg_configTim1Prescaler+1 is not 0 or a power of 2!" #endif +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A #if (dg_configTim1Prescaler == 0) #define dg_configTim1PrescalerBitRange (0) #elif (dg_configTim1Prescaler == 1) @@ -129,115 +286,48 @@ #else #error "dg_configTim1Prescaler is larger than 3!" #endif +#else +#ifdef dg_configTim1PrescalerBitRange +#warning "Timer1 prescaler is not supported in DA14682/3 chips." +#undef dg_configTim1PrescalerBitRange +#endif +#endif /* ---------------------------------------------------------------------------------------------- */ /** - * \} LOW_POWER_CLOCK_SETTINGS - */ - -/** - * \addtogroup IMAGE_CONFIGURATION_SETTINGS - * - * \{ - */ - -/* ------------------------------- Image configuration settings --------------------------------- */ - -/** - * \brief The chip revision that we compile for. - */ -#ifndef dg_configBLACK_ORCA_IC_REV -#define dg_configBLACK_ORCA_IC_REV BLACK_ORCA_IC_REV_A -#endif - -/** - * \brief The chip stepping that we compile for. - */ -#ifndef dg_configBLACK_ORCA_IC_STEP -#define dg_configBLACK_ORCA_IC_STEP BLACK_ORCA_IC_STEP_D -#endif - -/** - * \brief The motherboard revision we compile for. - */ -#ifndef dg_configBLACK_ORCA_MB_REV -#define dg_configBLACK_ORCA_MB_REV BLACK_ORCA_MB_REV_B -#endif - -/** - * \brief When set to 1, the execution mode and the code location are taken from the OTP Header and - * not from the bsp_config.h file. - */ -#ifndef dg_configCONFIG_VIA_OTP_HEADER -#define dg_configCONFIG_VIA_OTP_HEADER (0) -#endif - -/** - * \brief When set to 1, the values of the trim registers are taken from the Flash. - */ -#ifndef dg_configCONFIG_HEADER_IN_FLASH -#if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) \ - && (dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_D)) -#define dg_configCONFIG_HEADER_IN_FLASH (1) -#else -#define dg_configCONFIG_HEADER_IN_FLASH (0) -#endif -#endif - -/** - * \brief Controls how the image is built. - * - DEVELOPMENT_MODE: various debugging options are included. - * - PRODUCTION_MODE: all code used for debugging is removed. - */ -#ifndef dg_configIMAGE_SETUP -#define dg_configIMAGE_SETUP DEVELOPMENT_MODE -#endif - -/** - * \brief When set to 1, the application will write the proper code in the QFIS FIFO. - */ -#ifndef dg_configWRITE_QFIS_UCODE -#if ( (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) \ - || ( (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) \ - && (dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_D) ) ) -#define dg_configWRITE_QFIS_UCODE (1) -#else -#define dg_configWRITE_QFIS_UCODE (0) -#endif -#endif - -/** - * \brief When set to 1, the OTP copy will be emulated when in DEVELOPMENT_MODE. - */ -#ifndef dg_configEMULATE_OTP_COPY -#define dg_configEMULATE_OTP_COPY (0) -#endif - -/** - * \brief When set to 1, the QSPI copy will be emulated when in DEVELOPMENT_MODE (Not Applicable!). - */ -#ifndef dg_configEMULATE_QSPI_COPY -#define dg_configEMULATE_QSPI_COPY (0) -#endif - -/* ---------------------------------------------------------------------------------------------- */ - -/** - * \} IMAGE_CONFIGURATION_SETTINGS + * \} */ /** * \addtogroup SYSTEM_CONFIGURATION_SETTINGS * + * \brief System configuration settings + * * \{ */ - /* ------------------------------- System configuration settings -------------------------------- */ -#if (dg_configCONFIG_VIA_OTP_HEADER == 0) +/** + * \brief Source of Low Power clock used (LP_CLK_IS_ANALOG, LP_CLK_IS_DIGITAL) + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configLP_CLK_SOURCE +#define dg_configLP_CLK_SOURCE LP_CLK_IS_ANALOG +#endif + +# if ((dg_configLP_CLK_SOURCE == LP_CLK_IS_ANALOG) && (dg_configUSE_LP_CLK == LP_CLK_ANY)) +# error "When the LP source is analog (XTAL), the option LP_CLK_ANY is invalid!" +# endif + +# if ((dg_configLP_CLK_SOURCE == LP_CLK_IS_DIGITAL) && (dg_configUSE_LP_CLK == LP_CLK_RCX)) +# error "When the LP source is digital (External), the option LP_CLK_RCX is invalid!" +# endif /** - * \brief Low Power clock used (LP_CLK_32000, LP_CLK_32768, LP_CLK_RCX) + * \brief Low Power clock used (LP_CLK_32000, LP_CLK_32768, LP_CLK_RCX, LP_CLK_ANY) + * + * \bsp_default_note{\bsp_config_option_app,} */ # ifndef dg_configUSE_LP_CLK # define dg_configUSE_LP_CLK LP_CLK_RCX @@ -250,7 +340,7 @@ * - MODE_IS_MIRRORED * - MODE_IS_CACHED * - * \warning When #dg_configIMAGE_SETUP is set to DEVELOPMENT_MODE, this setting is overriden! + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ # ifndef dg_configEXEC_MODE # define dg_configEXEC_MODE MODE_IS_RAM @@ -262,6 +352,8 @@ * - NON_VOLATILE_IS_OTP * - NON_VOLATILE_IS_FLASH * - NON_VOLATILE_IS_NONE (RAM) + * + * \bsp_default_note{\bsp_config_option_app,} */ # ifndef dg_configCODE_LOCATION # define dg_configCODE_LOCATION NON_VOLATILE_IS_NONE @@ -269,6 +361,8 @@ /** * \brief Frequency of the crystal connected to the XTAL Oscillator: 16MHz or 32MHz. + * + * \bsp_default_note{\bsp_config_option_app,} */ # ifndef dg_configEXT_CRYSTAL_FREQ # define dg_configEXT_CRYSTAL_FREQ EXT_CRYSTAL_IS_16M @@ -280,50 +374,30 @@ * - 0: a crystal is connected to XTAL32Kp and XTALK32Km * - 1: a digital clock is provided. * - * \note the frequency of the digital clock must be 32KHz or 32.768KHz and be always running. + * \note the frequency of the digital clock must be 32KHz or 32.768KHz and be always running. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ # ifndef dg_configEXT_LP_IS_DIGITAL # define dg_configEXT_LP_IS_DIGITAL (0) # endif -#else - -# undef dg_configUSE_LP_CLK -# undef dg_configEXEC_MODE -# undef dg_configCODE_LOCATION -# undef dg_configEXT_CRYSTAL_FREQ - -// Configuration is done using variables that get initialized from the OTP -# define dg_configUSE_LP_CLK lp_clk_sel -# define dg_configEXEC_MODE code_execution_mode -# define dg_configCODE_LOCATION code_location -# define dg_configEXT_CRYSTAL_FREQ xtal16_crystal_freq - -#endif // dg_configCONFIG_VIA_OTP_HEADER == 0 - - -/** - * \brief Deep sleep configuration - * - * When set to 1, the system is forced to enter into clockless sleep during deep sleep. This has - * the following implications: - * - the 1V8 and 1V8P rails are turned off - * - the 3V3 rail can provide up to 2mA current and the voltage level is at ~2V - * - the LP clock is stopped. In case of RCX, it is restarted immediately at wake-up. In case of - * XTAL32K, dg_configINITIAL_SLEEP_DELAY_TIME must pass before the system is allowed to go to - * sleep again - * - BOD protection is not available. - * When set to 0, it is like the extended sleep mode with the difference that the Timer1 is - * disabled. - */ -#ifndef dg_configFORCE_DEEP_SLEEP -#define dg_configFORCE_DEEP_SLEEP (0) +/* + * This is a deprecated configuration hence not to be defined by an application. + * Forcing the system to enter into clockless sleep during deep sleep is no longer supported. + */ +#ifdef dg_configFORCE_DEEP_SLEEP +#error "Configuration option dg_configFORCE_DEEP_SLEEP is no longer supported." #endif /** * \brief Timer 1 usage * * When set to 0, Timer1 is reserved for the OS tick. + * + * \note A setting to 1 is meaningful only for non-RTOS projects. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configUSER_CAN_USE_TIMER1 #define dg_configUSER_CAN_USE_TIMER1 (0) @@ -331,6 +405,8 @@ /** * \brief Time needed for the settling of the LP clock, in msec. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configXTAL32K_SETTLE_TIME #define dg_configXTAL32K_SETTLE_TIME (8000) @@ -341,6 +417,8 @@ * * At startup, the system will stay active for at least this time period before it is allowed to go * to sleep, in msec. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #if (dg_configXTAL32K_SETTLE_TIME > 8000) #define dg_configINITIAL_SLEEP_DELAY_TIME (dg_configXTAL32K_SETTLE_TIME) @@ -350,21 +428,27 @@ /** * \brief XTAL16 settle time - * + * * Time needed for the settling of the XTAL16, in LP cycles. To this value, 5 LP cycles, that are * needed to start the core clock, are added since the SW powers the 1V4 rail after the execution * is resumed. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configXTAL16_SETTLE_TIME -#if (dg_configUSE_LP_CLK != LP_CLK_RCX) -#define dg_configXTAL16_SETTLE_TIME (85 + 5) -#else -#define dg_configXTAL16_SETTLE_TIME cm_rcx_us_2_lpcycles((uint32_t)((85 + 5) * 30.5)) +#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) + #define dg_configXTAL16_SETTLE_TIME (85 + 5) +#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) + #define dg_configXTAL16_SETTLE_TIME cm_rcx_us_2_lpcycles((uint32_t)((85 + 5) * 30.5)) +#else /* LP_CLK_ANY */ +// Must be defined in the custom_config_<>.h file. #endif #endif /** * \brief XTAL16 settle time RC32K + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #define dg_configXTAL16_SETTLE_TIME_RC32K (110) @@ -373,6 +457,8 @@ * * This is the maximum time, in LP cycles, needed to wake-up the chip and start executing code * using RC16. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #define dg_configWAKEUP_RC16_TIME (16) @@ -380,6 +466,8 @@ * \brief XTAL16 wakeup time * * Wake up N LP cycles before "time 0" to have XTAL16 ready when needed. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #define dg_configWAKEUP_XTAL16_TIME (dg_configXTAL16_SETTLE_TIME + dg_configWAKEUP_RC16_TIME) @@ -387,10 +475,13 @@ * \brief OS tick restore time * * This is the time, in LP cycles, required from the OS to restore the tick timer. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configOS_TICK_RESTORE_TIME #ifdef RELEASE_BUILD -#if (dg_configUSE_LP_CLK != LP_CLK_RCX) +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A +#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) #define dg_configOS_TICK_RESTORE_TIME (dg_configTim1Prescaler ? 2 + dg_configTim1Prescaler : 3) #else @@ -400,27 +491,60 @@ #define dg_configOS_TICK_RESTORE_TIME (dg_configTim1Prescaler ? 3 + dg_configTim1Prescaler : 4) #endif #endif -#else +#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(120) #else #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(120) #endif +#else /* LP_CLK_ANY */ + /* Must be defined in the custom_config_<>.h file. + * For QSPI cached, the dg_configOS_TICK_RESTORE_TIME must be ~120usec when no prescaling is + * used and ~180usec when prescaling is used. + */ #endif - +#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A */ +#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) + #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) + #define dg_configOS_TICK_RESTORE_TIME (3) + #else + #if (dg_configIMAGE_SETUP == PRODUCTION_MODE) + #define dg_configOS_TICK_RESTORE_TIME (4) + #else + #define dg_configOS_TICK_RESTORE_TIME (4) + #endif + #endif +#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) + #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) + #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(120) + #else + #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(120) + #endif +#else /* LP_CLK_ANY */ + /* Must be defined in the custom_config_<>.h file. + * For QSPI cached, the dg_configOS_TICK_RESTORE_TIME must be ~120usec when no prescaling is + * used and ~180usec when prescaling is used. + */ +#endif +#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A */ #else // RELEASE_BUILD -#if (dg_configUSE_LP_CLK != LP_CLK_RCX) +#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) #define dg_configOS_TICK_RESTORE_TIME (40) #else #define dg_configOS_TICK_RESTORE_TIME (72) #endif -#else +#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) #if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(1200) #else #define dg_configOS_TICK_RESTORE_TIME cm_rcx_us_2_lpcycles(2400) #endif +#else /* LP_CLK_ANY */ + /* Must be defined in the custom_config_<>.h file. + * Usually, the dg_configOS_TICK_RESTORE_TIME is set to a large value (i.e. 1.2 - 2.4msec) + * in order to allow for a more "relaxed" waking up of the system. + */ #endif #endif // RELEASE_BUILD #endif // dg_configOS_TICK_RESTORE_TIME @@ -432,15 +556,19 @@ * (or QSPI) to the RAM in mirrored mode. * * \warning MUST BE SMALLER THAN #dg_configMIN_SLEEP_TIME !!! + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #if (dg_configEXEC_MODE != MODE_IS_MIRRORED) -#undef dg_configIMAGE_COPY_TIME -#define dg_configIMAGE_COPY_TIME (0) + #undef dg_configIMAGE_COPY_TIME + #define dg_configIMAGE_COPY_TIME (0) #elif !defined(dg_configIMAGE_COPY_TIME) - #if (dg_configUSE_LP_CLK != LP_CLK_RCX) + #if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) #define dg_configIMAGE_COPY_TIME (64) - #else + #elif (dg_configUSE_LP_CLK == LP_CLK_RCX) #define dg_configIMAGE_COPY_TIME cm_rcx_us_2_lpcycles(1950) + #else /* LP_CLK_ANY */ + // Must be defined in the custom_config_<>.h file. #endif #endif @@ -453,36 +581,48 @@ * - bit 2 : SYSRAM3 * - bit 3 : SYSRAM4 * - bit 4 : SYSRAM5 + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + * */ #ifndef dg_configMEM_RETENTION_MODE -#define dg_configMEM_RETENTION_MODE (0) +#define dg_configMEM_RETENTION_MODE (0x1F) #endif -/** - * \brief Retention memory configuration when "no-Image copy at wake-up" is selected. +/* + * This is a deprecated configuration hence not to be defined by an application. */ -#ifndef dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE -# if (dg_configEXEC_MODE == MODE_IS_CACHED) - #define dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE dg_configMEM_RETENTION_MODE -# else - #define dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE (0) -# endif +#ifdef dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE +#error "dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE is no longer supported." #endif /** - * \brief Memory Shuffling mode. + * \brief Memory Shuffling mode. * * See SYS_CTRL_REG:REMAP_RAMS field. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configSHUFFLING_MODE #define dg_configSHUFFLING_MODE (0) #endif +/** + * \brief ECC microcode RAM retainment + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configECC_UCODE_RAM_RETAINED +#define dg_configECC_UCODE_RAM_RETAINED (0) +#endif + /** * \brief Watchdog Service * * - 1: enabled * - 0: disabled + * + * \bsp_default_note{\bsp_config_option_app,} */ #ifndef dg_configUSE_WDOG #define dg_configUSE_WDOG (0) @@ -493,15 +633,19 @@ * * - 1: used * - 0: not used + * + * \bsp_default_note{\bsp_config_option_app,} */ #ifndef dg_configUSE_BOD #define dg_configUSE_BOD (1) #endif /** - * \brief Reset value for Watchdog. + * \brief Reset value for Watchdog. * * See WATCHDOG_REG:WDOG_VAL field. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configWDOG_RESET_VALUE #define dg_configWDOG_RESET_VALUE (0xFF) @@ -512,6 +656,8 @@ * * Maximum number of tasks that the Watchdog Service can monitor. It can be larger (up to 32) than * needed, at the expense of increased Retention Memory requirement. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configWDOG_MAX_TASKS_CNT #define dg_configWDOG_MAX_TASKS_CNT (4) @@ -522,6 +668,8 @@ * * Interval (in miliseconds) for common timer which can be used to trigger tasks in order to notify * watchdog. Can be set to 0 in order to disable timer code entirely. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configWDOG_NOTIFY_TRIGGER_TMO #define dg_configWDOG_NOTIFY_TRIGGER_TMO (0) @@ -532,6 +680,8 @@ * * - 1: on * - 0: off + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configABORT_IF_SYSTICK_CLK_ERR #define dg_configABORT_IF_SYSTICK_CLK_ERR (0) @@ -542,6 +692,8 @@ * * Should be equal to the number of Adapters used by the Application. It can be larger (up to 254) * than needed, at the expense of increased Retention Memory requirements. It cannot be 0. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configPM_MAX_ADAPTERS_CNT #define dg_configPM_MAX_ADAPTERS_CNT (16) @@ -551,13 +703,17 @@ * \brief Maximum sleep defer time * * The maximum time sleep can be deferred via a call to pm_defer_sleep_for(). It is in clock cycles - * in the case of the XTAL32K and in msec in the case of RCX. + * in the case of the XTAL32K and in usec in the case of RCX. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configPM_MAX_ADAPTER_DEFER_TIME -#if (dg_configUSE_LP_CLK != LP_CLK_RCX) +#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) #define dg_configPM_MAX_ADAPTER_DEFER_TIME (128) -#else +#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) #define dg_configPM_MAX_ADAPTER_DEFER_TIME cm_rcx_us_2_lpcycles(4000) +#else /* LP_CLK_ANY */ + // Must be defined in the custom_config_<>.h file. It should be > 3.5msec. #endif #endif @@ -565,64 +721,117 @@ * \brief Minimum sleep time * * No power savings if we enter sleep when the sleep time is less than N LP cycles + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configMIN_SLEEP_TIME -#if (dg_configUSE_LP_CLK != LP_CLK_RCX) +#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) #define dg_configMIN_SLEEP_TIME (33*3) // 3 msec -#else +#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) #define dg_configMIN_SLEEP_TIME cm_rcx_us_2_lpcycles_low_acc(3000) // 3 msec +#else /* LP_CLK_ANY */ + // Must be defined in the custom_config_<>.h file. It should be ~3msec but this may vary. #endif #endif /** * \brief Recharge period + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configSET_RECHARGE_PERIOD -#if (dg_configUSE_LP_CLK != LP_CLK_RCX) -#define dg_configSET_RECHARGE_PERIOD 3000 /* number of Low Power clock cycles for - sampling and / or refreshing. */ -#else -#define dg_configSET_RECHARGE_PERIOD 90000 /* number of msec for sampling and / or - refreshing */ +#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) +#define dg_configSET_RECHARGE_PERIOD (3000) /** number of Low Power clock cycles for + sampling and / or refreshing. */ +#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) +#define dg_configSET_RECHARGE_PERIOD (90000) /** number of msec for sampling and / or + refreshing */ +#else /* LP_CLK_ANY */ + // Must be defined in the custom_config_<>.h file. #endif #endif /* dg_configSET_RECHARGE_PERIOD */ /** * \brief When set to 1, the DCDC is used. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configUSE_DCDC -#define dg_configUSE_DCDC (0) +#define dg_configUSE_DCDC (1) +#endif + +/* + * This is a deprecated configuration hence not to be defined by an application. + * The semantics of dg_configUSE_ADC replaced by dg_configUSE_HW_GPADC. + */ +#ifdef dg_configUSE_ADC +#error "Configuration option dg_configUSE_ADC is no longer supported. Use dg_configUSE_HW_GPADC instead." #endif /** - * \brief When set to 1, the ADC is used. + * \brief Apply ADC Gain Error correction. + * - 1: used + * - 0: not used * - * The ADC is also used when at least one of the following is true: - * - the USB Charger is used - * - the RF recalibration is enabled - * Both these cases are covered later on in this file. + * The default setting is: 1. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ -#ifndef dg_configUSE_ADC -#define dg_configUSE_ADC (0) +#ifndef dg_configUSE_ADC_GAIN_ERROR_CORRECTION +#define dg_configUSE_ADC_GAIN_ERROR_CORRECTION (1) #endif -#ifndef dg_configBATTERY_TYPE +/** + * \brief When set to 1, the USB interface is used. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configUSE_USB +#define dg_configUSE_USB (0) +#endif + +/** + * \addtogroup CHARGER_SETTINGS + * + * \brief Charger configuration settings + * \{ + */ +/* -------------------------------------- Charger settings -------------------------------------- */ + /** * \brief Battery type + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ +#ifndef dg_configBATTERY_TYPE #define dg_configBATTERY_TYPE (BATTERY_TYPE_NO_BATTERY) /** * \brief Battery charge voltage + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #define dg_configBATTERY_CHARGE_VOLTAGE (0) /** * \brief Battery charge current + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #define dg_configBATTERY_CHARGE_CURRENT (0) /** * \brief Battery charge NTC + * + * 0: NTC is enabled, 1: NTC is disabled + * + * Note that when NTC is enabled, the P14 and P16 are controlled by the charger and cannot be used + * by the application. P14 is set high (at 3.3V) when the charging starts while P16 is an input. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #define dg_configBATTERY_CHARGE_NTC (0) + +#if (dg_configBATTERY_CHARGE_NTC > 1) +#error "dg_configBATTERY_CHARGE_NTC must be either 0 or 1." +#endif /** * \brief Battery pre-charge current * @@ -644,49 +853,68 @@ * - 27 : 11.3mA * - 28 : 13.3mA * - 29 : 15.3mA + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #define dg_configBATTERY_PRECHARGE_CURRENT (0) #endif -/** - * \brief When set to 1, the USB interface is used. - */ -#ifndef dg_configUSE_USB -#define dg_configUSE_USB (0) -#endif - /** * \brief When set to 1, the USB Charger is used to charge the battery. + * + * \bsp_default_note{\bsp_config_option_app,} */ #ifndef dg_configUSE_USB_CHARGER #define dg_configUSE_USB_CHARGER (0) #else -# if (dg_configUSE_USB_CHARGER == 1) -# undef dg_configUSE_ADC -# define dg_configUSE_ADC (1) -# undef dg_configUSE_USB -# define dg_configUSE_USB (1) -# undef dg_configGPADC_ADAPTER -# define dg_configGPADC_ADAPTER (1) -# undef dg_configBATTERY_ADAPTER -# define dg_configBATTERY_ADAPTER (1) -# endif +#if (dg_configUSE_USB_CHARGER == 1) + #undef dg_configUSE_HW_GPADC + #define dg_configUSE_HW_GPADC (1) + #undef dg_configUSE_USB + #define dg_configUSE_USB (1) + #undef dg_configGPADC_ADAPTER + #define dg_configGPADC_ADAPTER (1) + #undef dg_configBATTERY_ADAPTER + #define dg_configBATTERY_ADAPTER (1) +#endif #endif /** * \brief When set to 1, the USB Charger will try to enumerate, if possible. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configUSE_USB_ENUMERATION #define dg_configUSE_USB_ENUMERATION (0) #else -# if (dg_configUSE_USB_ENUMERATION == 1) -# undef dg_configUSE_USB -# define dg_configUSE_USB (1) -# endif +#if (dg_configUSE_USB_ENUMERATION == 1) + #undef dg_configUSE_USB + #define dg_configUSE_USB (1) +#endif +#endif + +/** + * \brief Controls how the system will behave when the USB i/f is suspended. + * + * \details When the USB Node is suspended by the USB Host, the application may have to act in + * order to comply with the USB specification (consume less than 2.5mA). The available + * options are: + * 0: do nothing + * 1: pause system clock => the LP clock is stopped and only VBUS and USB irqs are handled + * 2: pause application => The system is not paused but the application must stop all + * timers and make sure all tasks are blocked. + * + * Both in modes 1 and 2, the application must make sure that all external peripherals are + * either powered off or placed in the lowest power consumption mode. + */ +#ifndef dg_configUSB_SUSPEND_MODE +#define dg_configUSB_SUSPEND_MODE (0) #endif /** * \brief When set to 1, the USB Charger will start charging with less than 100mA until enumerated. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configALLOW_CHARGING_NOT_ENUM #define dg_configALLOW_CHARGING_NOT_ENUM (0) @@ -694,7 +922,9 @@ /** * \brief When set to 1, the USB charger will stop charging from an SDP port (if - * #dg_configALLOW_CHARGING_NOT_ENUM is set to 1) after 45 minutes, if not enumerated. + * #dg_configALLOW_CHARGING_NOT_ENUM is set to 1) after 45 minutes, if not enumerated. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configUSE_NOT_ENUM_CHARGING_TIMEOUT #define dg_configUSE_NOT_ENUM_CHARGING_TIMEOUT (1) @@ -706,6 +936,8 @@ * This is the time to wait (N x 10 ms) before doing the first voltage measurement after starting * pre-charging. This is to ensure that an initial battery voltage overshoot will not trigger the * charger to stop pre-charging and move to normal charging. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configPRECHARGING_INITIAL_MEASURE_DELAY #define dg_configPRECHARGING_INITIAL_MEASURE_DELAY (3) @@ -718,21 +950,25 @@ * * The value must be calculated using this equation: * - * y[ADC units] = 820.32 * Vbat[Volts] - 5.343 + * y[ADC units] = (4095 * Vbat[Volts]) / 5 + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configPRECHARGING_THRESHOLD #define dg_configPRECHARGING_THRESHOLD (0) #endif /** - * \brief Charginf threshold + * \brief Charging threshold * * When Vbat is at or above this threshold (in ADC measurement units), pre-charging stops and * charging starts. * * The value must be calculated using this equation: * - * y[ADC units] = 820.32 * Vbat[Volts] - 5.343 + * y[ADC units] = (4095 * Vbat[Volts]) / 5 + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configCHARGING_THRESHOLD #define dg_configCHARGING_THRESHOLD (0) @@ -742,6 +978,8 @@ * \brief Pre-charging timeout * * If after this period, the Vbat is not higher than 3.0V then pre-charging stops (N x 10msec). + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configPRECHARGING_TIMEOUT #define dg_configPRECHARGING_TIMEOUT (15 * 60 * 100) @@ -752,7 +990,9 @@ * * If after this period, the charger is still charging then charging stops (N x 10msec). This * timeout has priority over the next two timeouts. If it is not zero then it is the only one taken - * into account. + * into account. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configCHARGING_TIMEOUT #define dg_configCHARGING_TIMEOUT (0) @@ -762,6 +1002,8 @@ * \brief Charging CC timeout * * If after this period, the charger is still in CC mode then charging stops (N x 10msec). + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configCHARGING_CC_TIMEOUT #define dg_configCHARGING_CC_TIMEOUT (180 * 60 * 100) @@ -771,6 +1013,8 @@ * \brief Charging CV timeout * * If after this period, the charger is still in CC mode then charging stops (N x 10msec). + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configCHARGING_CV_TIMEOUT #define dg_configCHARGING_CV_TIMEOUT (360 * 60 * 100) @@ -781,6 +1025,8 @@ * * While being attached to a USB cable and the battery has been charged, this is the interval * (N x 10msec) that the Vbat is polled to decide whether a new charge cycle will be started. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configUSB_CHARGER_POLLING_INTERVAL #define dg_configUSB_CHARGER_POLLING_INTERVAL (100) @@ -794,30 +1040,26 @@ * * The value must be calculated using this equation: * - * y[ADC units] = 820.32 * Vbat[Volts] - 5.343 + * y[ADC units] = (4095 * Vbat[Volts]) / 5 + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configBATTERY_LOW_LEVEL -#define dg_configBATTERY_LOW_LEVEL (2291) // 2.8V + #if (dg_configBATTERY_TYPE == BATTERY_TYPE_NO_BATTERY) || (dg_configBATTERY_TYPE == BATTERY_TYPE_NO_RECHARGE) + #define dg_configBATTERY_LOW_LEVEL (0) + #else + #define dg_configBATTERY_LOW_LEVEL (2293) // 2.8V + #endif #endif -/** - * \brief Low VBAT handling - * - * Choose whether the Low Power clock will be available when the system enters hibernation mode due - * to low battery. The options are: - * - 0 : Low Power clock is disabled - the system reboots only via an interrupt from the WKUP Ctrl - * - 1 : Low Power clock is enabled - the system wakes up from i.e. the VBUS interrupt. - * The default setting is: 1. - * - * \warning Do not use 0 for AD chips. +/* + * This is a deprecated configuration hence not to be defined by an application. + * When entering hibernation mode then: + * A DA14680/1-01 system reboots only via an interrupt from the WKUP Ctrl or VBUS. + * A DA14682/3-BA system reboots only via an interrupt from the WKUP Ctrl. */ -#ifndef dg_configLOW_VBAT_HANDLING -#define dg_configLOW_VBAT_HANDLING (1) -#elif (dg_configLOW_VBAT_HANDLING == 0) -#if ( (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) \ - && (dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_D) ) -#error "dg_configLOW_VBAT_HANDLING cannot be 0 when AD is used" -#endif +#ifdef dg_configLOW_VBAT_HANDLING +#error "Configuration option dg_configLOW_VBAT_HANDLING is no longer supported." #endif /** @@ -829,11 +1071,13 @@ * * The value must be calculated using this equation: * - * y[ADC units] = 820.32 * Vbat[Volts] - 5.343 + * y[ADC units] = (4095 * Vbat[Volts]) / 5 + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #if (dg_configBATTERY_TYPE == BATTERY_TYPE_CUSTOM) #ifndef dg_configBATTERY_TYPE_CUSTOM_ADC_VOLTAGE -#define dg_configBATTERY_TYPE_CUSTOM_ADC_VOLTAGE (1553) +#define dg_configBATTERY_TYPE_CUSTOM_ADC_VOLTAGE (1556) #endif #endif @@ -845,7 +1089,9 @@ * * The value must be calculated using this equation: * - * y[ADC units] = 820.32 * Vbat[Volts] - 5.343 + * y[ADC units] = (4095 * Vbat[Volts]) / 5 + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configBATTERY_CHARGE_GAP #define dg_configBATTERY_CHARGE_GAP (82) @@ -859,11 +1105,19 @@ * * The value must be calculated using this equation: * - * y[ADC units] = 820.32 * Vbat[Volts] - 5.343 + * y[ADC units] = (4095 * Vbat[Volts]) / 5 + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configBATTERY_REPLENISH_GAP #define dg_configBATTERY_REPLENISH_GAP (82*2) #endif +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} CHARGER_SETTINGS + */ + /** * \brief The Rsense of the SOC in multiples of 0.1Ohm. The default value is (1 x 0.1Ohm). @@ -874,142 +1128,281 @@ /** * \brief When set to 1, the ProDK is used (controls specific settings for this board). + * + * \bsp_default_note{\bsp_config_option_app,} */ #ifndef dg_configUSE_ProDK #define dg_configUSE_ProDK (0) #endif /** - * \brief When set to 1, the 1V8 for the QSPI FLASH is powered, when active. + * \brief When set to 1, State of Charge function is enabled. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ -#ifndef dg_configPOWER_FLASH -#define dg_configPOWER_FLASH (0) +#ifndef dg_configUSE_SOC +#define dg_configUSE_SOC (0) +#else +# if (dg_configUSE_SOC == 1) +# undef dg_configUSE_HW_SOC +# define dg_configUSE_HW_SOC (1) +# endif #endif /** - * \brief When set to 1, the QSPI FLASH is put to power-down state during sleep (applies to W25Q80EW). + * \addtogroup FLASH_SETTINGS + * + * \brief Flash configuration settings + * + * \{ + */ +/* -------------------------------------- Flash settings ---------------------------------------- */ + +/** + * \brief The rail from which the Flash is powered, if a Flash is used. + * + * - FLASH_IS_NOT_CONNECTED + * - FLASH_CONNECTED_TO_1V8 + * - FLASH_CONNECTED_TO_1V8P + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configFLASH_CONNECTED_TO +#error "dg_configFLASH_CONNECTED_TO is not defined!" +#endif + +/* Backward compatibility checks */ +#if defined(dg_configPOWER_EXT_1V8_PERIPHERALS) || defined(dg_configPOWER_FLASH) \ + || defined(dg_configFLASH_POWER_OFF) +#define PRINT_POWER_RAIL_SETUP +#endif + +#if defined(dg_configPOWER_EXT_1V8_PERIPHERALS) && defined(dg_configPOWER_1V8P) +#error "Both dg_configPOWER_EXT_1V8_PERIPHERALS and dg_configPOWER_1V8P are defined! Please use dg_configPOWER_1V8P only!" +#endif + +#ifdef dg_configPOWER_EXT_1V8_PERIPHERALS + #warning "dg_configPOWER_EXT_1V8_PERIPHERALS will be deprecated! Use dg_configPOWER_1V8P instead!" + + #if (dg_configPOWER_EXT_1V8_PERIPHERALS == 0) \ + && (dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8P) + #error "Flash is connected to 1V8P but dg_configPOWER_EXT_1V8_PERIPHERALS is 0..." + #endif + + #if (dg_configPOWER_EXT_1V8_PERIPHERALS == 1) + #define dg_configPOWER_1V8P (1) + #else + #define dg_configPOWER_1V8P (0) + #endif + #undef dg_configPOWER_EXT_1V8_PERIPHERALS +#endif + +#if defined(dg_configPOWER_FLASH) && defined(dg_configPOWER_1V8_ACTIVE) +#error "Both dg_configPOWER_FLASH and dg_configPOWER_1V8_ACTIVE are defined! Please use dg_configPOWER_1V8_ACTIVE only!" +#endif + +#if defined(dg_configFLASH_POWER_OFF) && defined(dg_configPOWER_1V8_SLEEP) +#error "Both dg_configFLASH_POWER_OFF and dg_configPOWER_1V8_SLEEP are defined! Please use dg_configPOWER_1V8_SLEEP only!" +#endif + +#ifdef dg_configPOWER_FLASH +#warning "dg_configPOWER_FLASH is deprecated! Use dg_configPOWER_1V8_ACTIVE instead!" +#endif +/* End of backward compatibility checks */ + +/** + * \brief When set to 1, the 1V8 rail is powered, when the system is in active state. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configPOWER_1V8_ACTIVE +#ifndef dg_configPOWER_FLASH + #define dg_configPOWER_1V8_ACTIVE (0) +#else + #if (dg_configPOWER_FLASH == 0) + #if (dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8) + #error "Flash is connected to the 1V8 rail but the rail is turned off (1)..." + #else + #define dg_configPOWER_1V8_ACTIVE (0) + #endif + #else + #define dg_configPOWER_1V8_ACTIVE (1) + #endif +#endif +#endif + +/** + * \brief When set to 1, the 1V8 is powered during sleep. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configPOWER_1V8_SLEEP +#ifndef dg_configFLASH_POWER_OFF + #define dg_configPOWER_1V8_SLEEP (0) +#else + #if (dg_configFLASH_POWER_OFF == 0) + #define dg_configPOWER_1V8_SLEEP (1) + #else + #define dg_configPOWER_1V8_SLEEP (0) + #endif +#endif +#endif + +/** + * \brief When set to 1, the Flash (connected to the 1V8 rail) is powered off during sleep. + * + * \note This is an internal define and cannot be overridden! + */ +#undef dg_configFLASH_POWER_OFF +#define dg_configFLASH_POWER_OFF ((dg_configFLASH_CONNECTED_TO == FLASH_CONNECTED_TO_1V8) \ + && (dg_configPOWER_1V8_SLEEP == 0)) + +/** + * \brief When set to 1, the 1V8P rail is powered. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configPOWER_1V8P +#define dg_configPOWER_1V8P (0) +#endif + +/** + * \brief When set to 1, the QSPI FLASH is put to power-down state during sleep. + * + * \bsp_default_note{\bsp_config_option_app,} */ #ifndef dg_configFLASH_POWER_DOWN #define dg_configFLASH_POWER_DOWN (0) #endif /** - * \brief When set to 1, the QSPI FLASH is turned off during sleep (applies to W25Q80EW). + * \brief Enable the Flash Autodetection mode + * + * \warning THIS WILL GREATLY INCREASE THE CODE SIZE AND RETRAM USAGE!!! MAKE SURE YOUR PROJECT + * CAN SUPPORT THIS. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ -#ifndef dg_configFLASH_POWER_OFF -#define dg_configFLASH_POWER_OFF (0) +#ifndef dg_configFLASH_AUTODETECT +#define dg_configFLASH_AUTODETECT (0) #endif +#if dg_configFLASH_AUTODETECT == 0 /** - * \brief uCode for handling the QSPI FLASH activation from power off. + * \brief The Flash Driver header file to include + * + * The header file must be in the include path of the compiler + * + * \bsp_default_note{\bsp_config_option_app,} */ -#ifndef dg_ucodeFLASH_POWER_OFF - /* - * Should work with all Winbond flashes -- verified with W25Q80EW. - * - * Delay 10usec - * 0x01 // CMD_NBYTES = 0, CMD_TX_MD = 0 (Single), CMD_VALID = 1 - * 0xA0 // CMD_WT_CNT_LS = 160 --> 10000 / 62.5 = 160 = 10usec - * 0x00 // CMD_WT_CNT_MS = 0 - * Exit from Fast Read mode - * 0x09 // CMD_NBYTES = 1, CMD_TX_MD = 0 (Single), CMD_VALID = 1 - * 0x00 // CMD_WT_CNT_LS = 0 - * 0x00 // CMD_WT_CNT_MS = 0 - * 0xFF // Enable Reset - * (up to 16 words) - */ -#define dg_ucodeFLASH_POWER_OFF \ - const uint32_t ucode_wakeup[] = { \ - 0x0900A001, \ - 0x00FF0000, \ - } +#ifndef dg_configFLASH_HEADER_FILE +#define dg_configFLASH_HEADER_FILE "qspi_w25q80ew.h" #endif /** - * \brief uCode for handling the QSPI FLASH release from power-down. + * \brief The Flash Manufacturer ID + * + * This must be defined inside the driver header file + * + * \bsp_default_note{\bsp_config_option_app,} */ -#ifndef dg_ucodeFLASH_POWER_DOWN - /* - * Should work with all Winbond flashes -- verified with W25Q80EW. - * - * 0x09 // CMD_NBYTES = 1, CMD_TX_MD = 0 (Single), CMD_VALID = 1 - * 0x30 // CMD_WT_CNT_LS = 48 --> 3000 / 62.5 = 48 = 3usec - * 0x00 // CMD_WT_CNT_MS = 0 - * 0xAB // Release Power Down - * (up to 16 words) - */ -#define dg_ucodeFLASH_POWER_DOWN \ - const uint32_t ucode_wakeup[] = { \ - 0xAB003009, \ - } - -/** - * \brief C code for handling the QSPI FLASH release from power-down. - */ -#define dg_configFLASH_POWER_DOWN_C_CODE \ -{ \ - for (volatile int delay = 0; delay < 12; delay++); \ - \ - hw_qspi_set_automode(false); \ - hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); \ - \ - hw_qspi_cs_enable(); \ - hw_qspi_write8(0xAB); \ - hw_qspi_cs_disable(); \ - \ - hw_qspi_set_automode(true); \ - \ - for (volatile int delay = 0; delay < 12; delay++); \ -} +#ifndef dg_configFLASH_MANUFACTURER_ID +#define dg_configFLASH_MANUFACTURER_ID WINBOND_ID #endif /** - * \brief uCode for handling the QSPI FLASH exit from the "Continuous Read Mode". + * \brief The Flash Device Type ID + * + * This must be defined inside the driver header file + * + * \bsp_default_note{\bsp_config_option_app,} */ -#ifndef dg_ucodeFLASH_ALWAYS_ACTIVE - /* - * Should work with all Winbond flashes -- verified with W25Q80EW. - * - * 0x25 // CMD_NBYTES = 4, CMD_TX_MD = 2 (Quad), CMD_VALID = 1 - * 0x00 // CMD_WT_CNT_LS = 0 - * 0x00 // CMD_WT_CNT_MS = 0 - * 0x55 // Clocks 0-1 (A23-16) - * 0x55 // Clocks 2-3 (A15-8) - * 0x55 // Clocks 4-5 (A7-0) - * 0x55 // Clocks 6-7 (M7-0) : M5-4 != '10' ==> Disable "Continuous Read Mode" - * (up to 16 words) - */ -#define dg_ucodeFLASH_ALWAYS_ACTIVE \ - const uint32_t ucode_wakeup[] = { \ - 0x55000025, \ - 0x00555555, \ - } +#ifndef dg_configFLASH_DEVICE_TYPE +#define dg_configFLASH_DEVICE_TYPE W25Q80EW #endif /** - * \brief When set to 1, the chip provides power to external peripherals. + * \brief The Flash Device Density ID + * + * This must be defined inside the driver header file + * + * \bsp_default_note{\bsp_config_option_app,} */ -#ifndef dg_configPOWER_EXT_1V8_PERIPHERALS -#define dg_configPOWER_EXT_1V8_PERIPHERALS (0) +#ifndef dg_configFLASH_DENSITY +#define dg_configFLASH_DENSITY W25Q_8Mb_SIZE #endif +#endif /* dg_configFLASH_AUTODETECT == 0 */ + +/** + * \brief Offset of the image if not placed at the beginning of QSPI Flash. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configIMAGE_FLASH_OFFSET +#define dg_configIMAGE_FLASH_OFFSET (0) +#endif + +/** + * \brief Set the flash page size. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configFLASH_MAX_WRITE_SIZE +#define dg_configFLASH_MAX_WRITE_SIZE (128) +#endif + +/** + * \brief Disable background operations. + * + * When enabled, outstanding QSPI operations will take place during sleep time + * increasing the efficiency. + * + * - 1 : Disabled + * - 0 : Enabled + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configDISABLE_BACKGROUND_FLASH_OPS +#define dg_configDISABLE_BACKGROUND_FLASH_OPS (0) +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/** + * \addtogroup DEBUG_SETTINGS + * + * \brief Debugging settings + * + * \{ + */ +/* -------------------------------------- Debug settings ---------------------------------------- */ + /** * \brief Enable debugger + * + * \bsp_default_note{\bsp_config_option_app,} */ #ifndef dg_configENABLE_DEBUGGER -#define dg_configENABLE_DEBUGGER (1) +#define dg_configENABLE_DEBUGGER (1) #endif /** * \brief Use SW cursor + * + * \bsp_default_note{\bsp_config_option_app,} */ #ifndef dg_configUSE_SW_CURSOR # define dg_configUSE_SW_CURSOR (0) # define SW_CURSOR_PORT (0) # define SW_CURSOR_PIN (0) #else -# if dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_B +# if dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D # if !defined SW_CURSOR_PORT && !defined SW_CURSOR_PIN # define SW_CURSOR_PORT (0) # define SW_CURSOR_PIN (7) @@ -1078,6 +1471,19 @@ (SW_CURSOR_PORT == 2 ? &(GPIO->P2_RESET_DATA_REG) : \ (SW_CURSOR_PORT == 3 ? &(GPIO->P3_RESET_DATA_REG) : \ &(GPIO->P4_RESET_DATA_REG))))) +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/** + * \addtogroup CACHE_SETTINGS + * + * \brief Cache configuration settings + * \{ + */ +/* -------------------------------------- Cache settings ---------------------------------------- */ /** * \brief Set the size (in bytes) of the QSPI flash cacheable area. @@ -1089,232 +1495,636 @@ * The size must be 64KB-aligned, due to the granularity of CACHE_CTRL2_REG[CACHE_LEN]. * * Special values: - * 0: turn off cache - * -1: don't configure cacheable area size (i.e. leave as set by booter) + * * 0 : Turn off cache. + * * -1 : Don't configure cacheable area size (i.e. leave as set by booter). + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} */ #ifndef dg_configCACHEABLE_QSPI_AREA_LEN #define dg_configCACHEABLE_QSPI_AREA_LEN (-1) #endif -#if (dg_configCACHEABLE_QSPI_AREA_LEN != -1) && (dg_configCACHEABLE_QSPI_AREA_LEN & 0xFFFF) -#error "dg_configCACHEABLE_QSPI_AREA_LEN must be 64KB-aligned!" + +/** + * \brief Set the associativity of the cache. + * + * Available values: + * - CACHE_ASSOC_AS_IS + * - CACHE_ASSOC_DIRECT_MAP + * - CACHE_ASSOC_2_WAY + * - CACHE_ASSOC_4_WAY + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configCACHE_ASSOCIATIVITY +#define dg_configCACHE_ASSOCIATIVITY CACHE_ASSOC_4_WAY +#endif + +/** + * \brief Set the line size of the cache. + * + * \bsp_default_note{\bsp_config_option_app,} + * + * Available values: + * - CACHE_LINESZ_AS_IS + * - CACHE_LINESZ_8_BYTES + * - CACHE_LINESZ_16_BYTES + * - CACHE_LINESZ_32_BYTES + */ +#ifndef dg_configCACHE_LINESZ +#define dg_configCACHE_LINESZ CACHE_LINESZ_8_BYTES +#endif +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/** + * \addtogroup ARBITER_SETTINGS + * + * \brief Arbiter configuration settings + * \{ + */ +/* ------------------------------- Arbiter configuration settings ------------------------------- */ + +/** + * \brief Custom arbiter configuration support. + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configCOEX_ENABLE_CONFIG +#define dg_configCOEX_ENABLE_CONFIG (0) +#endif + +/** + * \brief Arbiter statistics + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configCOEX_ENABLE_STATS +#define dg_configCOEX_ENABLE_STATS (0) +#endif +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/** + * \addtogroup PERIPHERAL_SELECTION + * + * \brief Peripheral selection + * + * When enabled the specific low level driver is included in the compilation of the SDK. + * - 0 : Disabled + * - 1 : Enabled + * + * The default option can be overridden in the application configuration file. + * + * \{ + Driver | Setting | Default option + ------------------------------ | -------------------------------------- | :------------------: + AES HASH | dg_configUSE_HW_AES_HASH | 0 + Radio MAC Arbiter | dg_configUSE_HW_COEX | 0 + Clock and Power Manager | dg_configUSE_HW_CPM | 1 + Direct Memory Access | dg_configUSE_HW_DMA | 1 + Elliptic Curve Controller | dg_configUSE_HW_ECC | 1 + Analog to Digital Converter | dg_configUSE_HW_GPADC | 1 + General Purpose I/O | dg_configUSE_HW_GPIO | 1 + Inter-Integrated Circuit | dg_configUSE_HW_I2C | 0 + Infra Red Generator | dg_configUSE_HW_IRGEN | 0 + Keyboard scanner | dg_configUSE_HW_KEYBOARD_SCANNER | 0 + OTP controller | dg_configUSE_HW_OTPC | 1 + QSPI controller | dg_configUSE_HW_QSPI | 1 + Quadrature decoder | dg_configUSE_HW_QUAD | 0 + Radio module | dg_configUSE_HW_RF | 1 + State of charge module | dg_configUSE_HW_SOC | 0 + Timer 0 | dg_configUSE_HW_TIMER0 | 0 + Timer 1 | dg_configUSE_HW_TIMER1 | 1 + Timer 2 | dg_configUSE_HW_TIMER2 | 0 + True Random Generator | dg_configUSE_HW_TRNG | 1 + UART | dg_configUSE_HW_UART | 1 + USB charger | dg_configUSE_HW_USB_CHARGER | 1 + Wakeup timer | dg_configUSE_HW_WKUP | 1 + PDM interface | dg_configUSE_IF_PDM | 0 + * + * \bsp_default_note{\bsp_config_option_app,} + */ + +/* -------------------------------- Peripherals (hw_*) selection -------------------------------- */ + +#ifndef dg_configUSE_HW_AES_HASH +#define dg_configUSE_HW_AES_HASH (0) +#endif + +#ifndef dg_configUSE_HW_COEX +#define dg_configUSE_HW_COEX (0) +#endif + +#ifndef dg_configUSE_HW_CPM +#define dg_configUSE_HW_CPM (1) +#endif + +#ifndef dg_configUSE_HW_DMA +#define dg_configUSE_HW_DMA (1) +#endif + +#ifndef dg_configUSE_HW_ECC +#define dg_configUSE_HW_ECC (1) +#endif + +#ifndef dg_configUSE_HW_GPADC +#define dg_configUSE_HW_GPADC (1) +#endif + +#ifndef dg_configUSE_HW_GPIO +#define dg_configUSE_HW_GPIO (1) +#endif + +#ifndef dg_configUSE_HW_I2C +#define dg_configUSE_HW_I2C (0) +#endif + +#ifndef dg_configUSE_HW_IRGEN +#define dg_configUSE_HW_IRGEN (0) +#endif + +#ifndef dg_configUSE_HW_KEYBOARD_SCANNER +#define dg_configUSE_HW_KEYBOARD_SCANNER (0) +#endif + +#ifndef dg_configUSE_HW_OTPC +#define dg_configUSE_HW_OTPC (1) +#endif + +#ifndef dg_configUSE_HW_QSPI +#define dg_configUSE_HW_QSPI (1) +#endif + +#ifndef dg_configUSE_HW_QUAD +#define dg_configUSE_HW_QUAD (0) +#endif + +#ifndef dg_configUSE_HW_RF +#define dg_configUSE_HW_RF (1) +#endif + +#ifndef dg_configUSE_HW_SOC +#define dg_configUSE_HW_SOC (0) +#endif + +#ifndef dg_configUSE_HW_SPI +#define dg_configUSE_HW_SPI (0) +#endif + +#ifndef dg_configUSE_HW_TEMPSENS +#define dg_configUSE_HW_TEMPSENS (1) +#endif + +#ifndef dg_configUSE_HW_TIMER0 +#define dg_configUSE_HW_TIMER0 (0) +#endif + +#ifndef dg_configUSE_HW_TIMER1 +#define dg_configUSE_HW_TIMER1 (1) +#endif + +#ifndef dg_configUSE_HW_TIMER2 +#define dg_configUSE_HW_TIMER2 (0) +#endif + +#ifndef dg_configUSE_HW_TRNG +#define dg_configUSE_HW_TRNG (1) +#endif + +#ifndef dg_configUSE_HW_UART +#define dg_configUSE_HW_UART (1) +#endif + +#ifndef dg_configUSE_HW_USB_CHARGER +#define dg_configUSE_HW_USB_CHARGER (1) +#endif + +#ifndef dg_configUSE_HW_WKUP +#define dg_configUSE_HW_WKUP (1) +#endif + +#ifndef dg_configUSE_HW_USB +#define dg_configUSE_HW_USB (0) +#endif + +#ifndef dg_configUSE_IF_PDM +#define dg_configUSE_IF_PDM (0) +#endif +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/* ------------------------------- WKUP settings ------------------------------------------------ */ + +/** + * \addtogroup WKUP_SETTINGS + * + * \brief WKUP configuration settings + * \{ + */ + +/* ------------------------------- LATCH settings ------------------------------------------------ */ + +/** + * \addtogroup WKUP_LATCH_SETTINGS + * + * \brief WKUP LATCH configuration settings + * \{ + */ + +/** + * \brief WKUP latch wakeup (io) source support + * + * \note In chip revision DA14680/1-01, this feature is implemented in s/w + * \note In chip revision DA14682/3-BA, this feature is implemented in h/w + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#if (!defined(dg_configLATCH_WKUP_SOURCE)) || (dg_configUSE_HW_WKUP == 0) + #undef dg_configLATCH_WKUP_SOURCE + #define dg_configLATCH_WKUP_SOURCE (0) #endif /* ---------------------------------------------------------------------------------------------- */ /** - * \} + * \} */ -/* ------------------------------- Arbiter configuration settings ------------------------------- */ +/* ---------------------------------------------------------------------------------------------- */ -/* Custom arbiter configuration support. */ -#ifndef dg_configCOEX_ENABLE_CONFIG -#define dg_configCOEX_ENABLE_CONFIG (0) -#endif +/** + * \} + */ -/* Arbiter statistics */ -#ifndef dg_configCOEX_ENABLE_STATS -#define dg_configCOEX_ENABLE_STATS (0) -#endif +/* ------------------------------- UART settings ------------------------------------------------ */ -/* -------------------------------- Peripherals (hw_*) selection -------------------------------- */ +/** + * \addtogroup UART_SETTINGS + * + * \brief UART FIFO configuration settings + * \{ + */ -#ifndef dg_configUSE_HW_AES_HASH -# define dg_configUSE_HW_AES_HASH (0) -#endif +/* ------------------------------- FIFO settings ------------------------------------------------ */ -#ifndef dg_configUSE_HW_COEX -# define dg_configUSE_HW_COEX (0) -#endif - -#ifndef dg_configUSE_HW_CPM -# define dg_configUSE_HW_CPM (1) -#endif - -#ifndef dg_configUSE_HW_DMA -# define dg_configUSE_HW_DMA (1) -#endif - -#ifndef dg_configUSE_HW_GPADC -# define dg_configUSE_HW_GPADC (1) -#endif - -#ifndef dg_configUSE_HW_GPIO -# define dg_configUSE_HW_GPIO (1) -#endif - -#ifndef dg_configUSE_HW_I2C -# define dg_configUSE_HW_I2C (0) -#endif - -#ifndef dg_configUSE_HW_IRGEN -# define dg_configUSE_HW_IRGEN (0) -#endif - -#ifndef dg_configUSE_HW_KEYBOARD_SCANNER -# define dg_configUSE_HW_KEYBOARD_SCANNER (0) -#endif - -#ifndef dg_configUSE_HW_OTPC -# define dg_configUSE_HW_OTPC (1) -#endif - -#ifndef dg_configUSE_HW_QSPI -# define dg_configUSE_HW_QSPI (1) -#endif - -#ifndef dg_configUSE_HW_QUAD -# define dg_configUSE_HW_QUAD (0) -#endif - -#ifndef dg_configUSE_HW_RF -# define dg_configUSE_HW_RF (1) -#endif - -#ifndef dg_configUSE_HW_SOC -# define dg_configUSE_HW_SOC (0) -#endif - -#ifndef dg_configUSE_HW_SPI -#define dg_configUSE_HW_SPI (0) -#endif - -#ifndef dg_configUSE_HW_TEMPSENS -# define dg_configUSE_HW_TEMPSENS (1) -#endif - -#ifndef dg_configUSE_HW_TIMER0 -# define dg_configUSE_HW_TIMER0 (0) -#endif - -#ifndef dg_configUSE_HW_TIMER1 -# define dg_configUSE_HW_TIMER1 (1) -#endif - -#ifndef dg_configUSE_HW_TIMER2 -# define dg_configUSE_HW_TIMER2 (0) -#endif - -#ifndef dg_configUSE_HW_TRNG -# define dg_configUSE_HW_TRNG (0) -#endif - -#ifndef dg_configUSE_HW_UART -# define dg_configUSE_HW_UART (1) -#endif +/** + * \addtogroup UART_FIFO_SETTINGS + * + * \brief UART FIFO configuration settings + * \{ + */ +/** + * \brief Software FIFO support + * + * \bsp_default_note{\bsp_config_option_app,} + */ #ifndef dg_configUART_SOFTWARE_FIFO -# define dg_configUART_SOFTWARE_FIFO (0) +#define dg_configUART_SOFTWARE_FIFO (0) #endif -#ifndef dg_configUSE_HW_USB_CHARGER -# define dg_configUSE_HW_USB_CHARGER (1) +/** + * \brief UART1's software FIFO size + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configUART1_SOFTWARE_FIFO_SIZE +# define dg_configUART1_SOFTWARE_FIFO_SIZE (0) #endif -#ifndef dg_configUSE_HW_USB_WKUP -# define dg_configUSE_HW_USB_WKUP (1) +/** + * \brief UART2's software FIFO size + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configUART2_SOFTWARE_FIFO_SIZE +# define dg_configUART2_SOFTWARE_FIFO_SIZE (0) +#endif +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/* ------------------------------- Circular DMA for RX settings --------------------------------- */ + +/** + * \addtogroup UART_CIRCULAR_DMA_FOR_RX_SETTINGS + * + * \brief UART FIFO configuration settings + * \{ + */ + +/** + * \brief Circular DMA support for RX + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configUART_RX_CIRCULAR_DMA +#define dg_configUART_RX_CIRCULAR_DMA (0) #endif -#ifndef dg_configUSE_HW_USB -# define dg_configUSE_HW_USB (0) +/** + * \brief UART1's Circular DMA buffer size for RX + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE +#define dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE (0) +#endif + +/** + * \brief UART2's Circular DMA buffer size for RX + * + * \bsp_default_note{\bsp_config_option_app,} + */ +#ifndef dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE +#define dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE (0) #endif /* ---------------------------------------------------------------------------------------------- */ +/** + * \} + */ + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/** + * \addtogroup ADAPTER_SELECTION + * + * \brief Adapter selection + * + * When enabled the specific adapter is included in the compilation of the SDK. + * - 0 : Disabled + * - 1 : Enabled + * + * The default option can be overridden in the application configuration file. + * + * \{ + Adapter | Setting | Default option + ------------------------------ | -------------------------------------- | :------------------: + Flash | dg_configFLASH_ADAPTER | 1 + Inter-Integrated Circuit | dg_configI2C_ADAPTER | 0 + Non Volatile Memory Storage | dg_configNVMS_ADAPTER | 1 + Virtual EERPOM Storage | dg_configNVMS_VES | 1 + Radio | dg_configRF_ADAPTER | 1 + Serial Peripheral Interface | dg_configSPI_ADAPTER | 0 + UART | dg_configUART_ADAPTER | 0 + UART for BLE | dg_configUART_BLE_ADAPTER | 0 + Analog to Digital Converter | dg_configGPADC_ADAPTER | 0 + Temperature Sensor | dg_configTEMPSENS_ADAPTER | 0 + Battery | dg_configBATTERY_ADAPTER | 0 + Non Volatile Parameters | dg_configNVPARAM_ADAPTER | 0 + Crypto | dg_configCRYPTO_ADAPTER | 1 + Keyboard scanner | dg_configKEYBOARD_SCANNER_ADAPTER | 0 + * + * + * \bsp_default_note{\bsp_config_option_app,} + */ + /* -------------------------------- Adapters (ad_*) selection -------------------------------- */ -/* - * Set to 1/0 to, by default, include/exclude the specific adapter when compiling the SDK. - * It can be overridden in the application configuration file. - */ - #ifndef dg_configFLASH_ADAPTER -# define dg_configFLASH_ADAPTER (1) +#define dg_configFLASH_ADAPTER (1) #endif -#ifndef dg_configIMAGE_FLASH_OFFSET -# define dg_configIMAGE_FLASH_OFFSET (0) -#endif - -#ifndef dg_configFLASH_MAX_WRITE_SIZE -# define dg_configFLASH_MAX_WRITE_SIZE (256) -#endif - - #ifndef dg_configI2C_ADAPTER -# define dg_configI2C_ADAPTER (0) +#define dg_configI2C_ADAPTER (0) #endif #ifndef dg_configNVMS_ADAPTER -# define dg_configNVMS_ADAPTER (1) +#define dg_configNVMS_ADAPTER (1) #endif #ifndef dg_configNVMS_FLASH_CACHE -# define dg_configNVMS_FLASH_CACHE (0) +#define dg_configNVMS_FLASH_CACHE (0) #endif #ifndef dg_configNVMS_VES -# define dg_configNVMS_VES (1) +#define dg_configNVMS_VES (1) #endif #ifndef dg_configRF_ADAPTER -# define dg_configRF_ADAPTER (1) +#define dg_configRF_ADAPTER (1) #endif #ifndef dg_configSPI_ADAPTER -# define dg_configSPI_ADAPTER (0) +#define dg_configSPI_ADAPTER (0) #endif #ifndef dg_configUART_ADAPTER -# define dg_configUART_ADAPTER (0) +#define dg_configUART_ADAPTER (0) #endif #ifndef dg_configUART_BLE_ADAPTER -# define dg_configUART_BLE_ADAPTER (0) +#define dg_configUART_BLE_ADAPTER (0) #endif #ifndef dg_configGPADC_ADAPTER -# define dg_configGPADC_ADAPTER (0) +#define dg_configGPADC_ADAPTER (0) #endif #ifndef dg_configTEMPSENS_ADAPTER -# define dg_configTEMPSENS_ADAPTER (0) +#define dg_configTEMPSENS_ADAPTER (0) #endif #ifndef dg_configBATTERY_ADAPTER -# define dg_configBATTERY_ADAPTER (0) +#define dg_configBATTERY_ADAPTER (0) #endif #ifndef dg_configNVPARAM_ADAPTER -# define dg_configNVPARAM_ADAPTER (0) +#define dg_configNVPARAM_ADAPTER (0) +#endif + +#ifndef dg_configCRYPTO_ADAPTER +#define dg_configCRYPTO_ADAPTER (1) +#endif + +#ifndef dg_configKEYBOARD_SCANNER_ADAPTER +#define dg_configKEYBOARD_SCANNER_ADAPTER (0) #endif /* ---------------------------------------------------------------------------------------------- */ +/** + * \} + */ + +/** + * \addtogroup CONSOLE_IO_SETTINGS + * + * \brief Console IO configuration settings + * + * \{ + Description | Setting | Default option + ----------------------------------------- | -------------------------- | :---------------: + Enable serial console module | dg_configUSE_CONSOLE | 0 + Enable serial console stubbed API | dg_configUSE_CONSOLE_STUBS | 0 + Enable Command Line Interface module | dg_configUSE_CLI | 0 + Enable Command Line Interface stubbed API | dg_configUSE_CLI_STUBS | 0 + + \see console.h cli.h + + \note CLI module requires dg_configUSE_CONSOLE to be enabled. + * + * \bsp_default_note{\bsp_config_option_app,} + */ + +/* -------------------------------------- Console IO configuration settings --------------------- */ + +#ifndef dg_configUSE_CONSOLE +#define dg_configUSE_CONSOLE (0) +#endif + +#ifndef dg_configUSE_CONSOLE_STUBS +#define dg_configUSE_CONSOLE_STUBS (0) +#endif + +#ifndef dg_configUSE_CLI +#define dg_configUSE_CLI (0) +#endif + +#ifndef dg_configUSE_CLI_STUBS +#define dg_configUSE_CLI_STUBS (0) +#endif +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/* ----------------------------- DGTL ----------------------------------------------------------- */ + +/** + * \brief Enable D.GTL interface + * + * When this macro is enabled, the DGTL framework is available for use. + * The framework must furthermore be initialized in the application using + * dgtl_init(). Additionally, the UART adapter must be initialized accordingly. + * + * Please see sdk/middleware/dgtl/include/ for further DGTL configuration + * (in dgtl_config.h) and API. + * + * \bsp_default_note{\bsp_config_option_app,} + * + */ +#ifndef dg_configUSE_DGTL +#define dg_configUSE_DGTL (0) +#endif + +/** + * \addtogroup DEBUG_SETTINGS + * \{ + * \addtogroup SYSTEM_VIEW + * + * \brief System View configuration settings + * \{ + */ + /* ----------------------------- Segger System View configuration ------------------------------- */ -/* - * Set to 1/0 to enable/disable Segger System View. When enabled the application should also call - * SEGGER_SYSVIEW_Conf() to enable system monitoring. - * */ +/** + * \brief Segger's System View + * + * When enabled the application should also call SEGGER_SYSVIEW_Conf() to enable system monitoring. + * configTOTAL_HEAP_SIZE should be increased by dg_configSYSTEMVIEW_STACK_OVERHEAD bytes for each system task. + * For example, if there are 8 system tasks configTOTAL_HEAP_SIZE should be increased by + * (8 * dg_configSYSTEMVIEW_STACK_OVERHEAD) bytes. + * + * - 0 : Disabled + * - 1 : Enabled + * + * \bsp_default_note{\bsp_config_option_app,} + * + */ #ifndef dg_configSYSTEMVIEW -# define dg_configSYSTEMVIEW (0) +#define dg_configSYSTEMVIEW (0) #endif -/* - * This is the stack size overhead when System View API is used. +/** + * \brief Stack size overhead when System View API is used + * * All thread stack sizes plus the the stack of IRQ handlers will be increased by that amount * to avoid stack overflow when System View is monitoring the system. - * */ + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ #ifndef dg_configSYSTEMVIEW_STACK_OVERHEAD -# define dg_configSYSTEMVIEW_STACK_OVERHEAD (512) +#define dg_configSYSTEMVIEW_STACK_OVERHEAD (256) #endif +/* + * Enable/Disable System View monitoring time critical interrupt handlers (BLE, CPM, USB). + * Disabling ISR monitoring could help reducing assertions triggered by System View monitoring overhead. + * + */ +/** + * \brief Let System View monitor BLE related ISRs (BLE_GEN_Handler / BLE_WAKEUP_LP_Handler). + * + * - 0 : Disabled + * - 1 : Enabled + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configSYSTEMVIEW_MONITOR_BLE_ISR +#define dg_configSYSTEMVIEW_MONITOR_BLE_ISR (1) +#endif + +/** + * \brief Let System View monitor CPM related ISRs (SWTIM1_Handler / WKUP_GPIO_Handler). + * + * - 0 : Disabled + * - 1 : Enabled + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configSYSTEMVIEW_MONITOR_CPM_ISR +#define dg_configSYSTEMVIEW_MONITOR_CPM_ISR (1) +#endif + +/** + * \brief Let System View monitor USB related ISRs (USB_Handler / VBUS_Handler). + * + * - 0 : Disabled + * - 1 : Enabled + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef dg_configSYSTEMVIEW_MONITOR_USB_ISR +#define dg_configSYSTEMVIEW_MONITOR_USB_ISR (1) +#endif /* ---------------------------------------------------------------------------------------------- */ +/** + * \} + * \} + */ -/* ------------------------------- RF driver configuration settings -------------------------------- */ +/** + * \addtogroup RF_DRIVER_SETTINGS + * + * \brief Doxygen documentation is not yet available for this module. + * Please check the source code file(s) + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + * \{ + */ +/* ------------------------------- RF driver configuration settings ----------------------------- */ /* Set to 1 to enable the recalibration procedure */ #ifndef dg_configRF_ENABLE_RECALIBRATION @@ -1323,36 +2133,38 @@ /* If RF recalibration is enabled, we need to enable GPADC as well */ #if dg_configRF_ENABLE_RECALIBRATION -#undef dg_configUSE_ADC -#define dg_configUSE_ADC (1) +#undef dg_configUSE_HW_GPADC +#define dg_configUSE_HW_GPADC (1) #undef dg_configGPADC_ADAPTER -#define dg_configGPADC_ADAPTER (1) +#define dg_configGPADC_ADAPTER (1) #undef dg_configTEMPSENS_ADAPTER -#define dg_configTEMPSENS_ADAPTER (1) +#define dg_configTEMPSENS_ADAPTER (1) #endif /* If RF is enabled, we need to enable GPADC adapter as well */ #if dg_configRF_ADAPTER #undef dg_configGPADC_ADAPTER -#define dg_configGPADC_ADAPTER (1) +#define dg_configGPADC_ADAPTER (1) #endif /* Minimum time before performing an RF recalibration, in FreeRTOS scheduler ticks */ #ifndef dg_configRF_MIN_RECALIBRATION_TIMEOUT -# if (dg_configUSE_LP_CLK == LP_CLK_32000) -# define dg_configRF_MIN_RECALIBRATION_TIMEOUT 1000 // ~2 secs -# elif (dg_configUSE_LP_CLK == LP_CLK_32768) -# define dg_configRF_MIN_RECALIBRATION_TIMEOUT 1024 // ~2 secs -# else -# define dg_configRF_MIN_RECALIBRATION_TIMEOUT 1000 -# endif +#if (dg_configUSE_LP_CLK == LP_CLK_32000) +#define dg_configRF_MIN_RECALIBRATION_TIMEOUT (1000) // ~2 secs +#elif (dg_configUSE_LP_CLK == LP_CLK_32768) +#define dg_configRF_MIN_RECALIBRATION_TIMEOUT (1024) // ~2 secs +#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) +#define dg_configRF_MIN_RECALIBRATION_TIMEOUT (1000) +#else /* LP_CLK_ANY */ +// Must be defined in the custom_config_<>.h file. Should result in ~2sec. +#endif #endif /* Maximum time before performing an RF recalibration, in FreeRTOS scheduler ticks * If this time has elapsed, and RF is about to be powered off, recalibration will * be done unconditionally. Set to 0 to disable this functionality */ #ifndef dg_configRF_MAX_RECALIBRATION_TIMEOUT -# define dg_configRF_MAX_RECALIBRATION_TIMEOUT 0 // Disabled +#define dg_configRF_MAX_RECALIBRATION_TIMEOUT (0) // Disabled #endif /* Timeout value (in FreeRTOS scheduler ticks) for timer to initiate RF recalibration. @@ -1364,51 +2176,279 @@ * * Set to 0 to disable this functionality */ #ifndef dg_configRF_RECALIBRATION_TIMER_TIMEOUT -# define dg_configRF_RECALIBRATION_TIMER_TIMEOUT 0 // Disabled +#define dg_configRF_RECALIBRATION_TIMER_TIMEOUT (0) // Disabled #endif /* Minimum temp difference before performing an RF recalibration, in oC*/ #ifndef dg_configRF_MIN_RECALIBRATION_TEMP_DIFF -# ifdef CONFIG_USE_FTDF -# define dg_configRF_MIN_RECALIBRATION_TEMP_DIFF (5) -# else -# define dg_configRF_MIN_RECALIBRATION_TEMP_DIFF (10) -# endif +#ifdef CONFIG_USE_FTDF + #define dg_configRF_MIN_RECALIBRATION_TEMP_DIFF (5) +#else + #define dg_configRF_MIN_RECALIBRATION_TEMP_DIFF (10) +#endif #endif /* Duration of recalibration procedure, in lp clk cycles */ #ifndef dg_configRF_RECALIBRATION_DURATION # if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) -# if (dg_configUSE_LP_CLK != LP_CLK_RCX) -# define dg_configRF_RECALIBRATION_DURATION 230 -# else +# if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) +# define dg_configRF_RECALIBRATION_DURATION (230) +# elif (dg_configUSE_LP_CLK == LP_CLK_RCX) # define dg_configRF_RECALIBRATION_DURATION cm_rcx_us_2_lpcycles((uint32_t)(230 * 30.5)) +# else /* LP_CLK_ANY */ + // Must be defined in the custom_config_<>.h file. It should be ~7msec. # endif # else -# if (dg_configUSE_LP_CLK != LP_CLK_RCX) -# define dg_configRF_RECALIBRATION_DURATION 131 -# else +# if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) +# define dg_configRF_RECALIBRATION_DURATION (131) +# elif (dg_configUSE_LP_CLK == LP_CLK_RCX) # define dg_configRF_RECALIBRATION_DURATION cm_rcx_us_2_lpcycles((uint32_t)(131 * 30.5)) +# else /* LP_CLK_ANY */ + // Must be defined in the custom_config_<>.h file. It should be ~4msec. # endif # endif #endif #ifndef dg_configRF_IFF_CALIBRATION_TIMEOUT -# if (dg_configUSE_LP_CLK != LP_CLK_RCX) -# define dg_configRF_IFF_CALIBRATION_TIMEOUT 40 -# else -# define dg_configRF_IFF_CALIBRATION_TIMEOUT cm_rcx_us_2_lpcycles((uint32_t)(40 * 30.5)) +#if ((dg_configUSE_LP_CLK == LP_CLK_32000) || (dg_configUSE_LP_CLK == LP_CLK_32768)) + #define dg_configRF_IFF_CALIBRATION_TIMEOUT (40) +#elif (dg_configUSE_LP_CLK == LP_CLK_RCX) + #define dg_configRF_IFF_CALIBRATION_TIMEOUT cm_rcx_us_2_lpcycles((uint32_t)(40 * 30.5)) +#else /* LP_CLK_ANY */ +// Must be defined in the custom_config_<>.h file. It should be ~1.2msec. # endif #endif +/* ---------------------------------------------------------------------------------------------- */ +/** + * \} + */ + +/** + * \addtogroup BLE_EVENT_NOTIFICATIONS + * + * \brief Doxygen documentation is not yet available for this module. + * Please check the source code file(s) + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + * + * \{ + */ +/* -----------------------------------BLE event notifications configuration --------------------- */ + +/* + * BLE ISR event Notifications + * + * This facility enables the user app to receive notifications for BLE + * ISR events. These events can be received either directly from inside + * the BLE ISR, or as task notifications to the Application Task + * registered to the BLE manager. + * + * To enable, define dg_configBLE_EVENT_NOTIF_TYPE to either + * BLE_EVENT_NOTIF_USER_ISR or BLE_EVENT_NOTIF_USER_TASK. + * + * - When dg_configBLE_EVENT_NOTIF_TYPE == BLE_EVENT_NOTIF_USER_ISR, the user + * can define the following macros on his app configuration: + * + * dg_configBLE_EVENT_NOTIF_HOOK_END_EVENT : The BLE End Event + * dg_configBLE_EVENT_NOTIF_HOOK_CSCNT_EVENT : The BLE CSCNT Event + * dg_configBLE_EVENT_NOTIF_HOOK_FINE_EVENT : The BLE FINE Event + * + * These macros must be actually set to the names of functions defined inside + * the user application, having a prototype of + * + * void func(void); + * + * (The user app does not need to explicitly define the prototype). + * + * If one of these macros is not defined, the respective notification + * will be suppressed. + * + * Note that these functions will be called in ISR context, directly from the + * BLE ISR. They should therefore be very fast and should NEVER block. + * + * - When dg_configBLE_EVENT_NOTIF_TYPE == BLE_EVENT_NOTIF_USER_TASK, the user + * app will receive task notifications on the task registered to the BLE + * manager. + * + * Notifications will be received using the following bit masks: + * + * - dg_configBLE_EVENT_NOTIF_MASK_END_EVENT: End Event Mask (Def: bit 24) + * - dg_configBLE_EVENT_NOTIF_MASK_CSCNT_EVENT: CSCNT Event Mask (Def: bit 25) + * - dg_configBLE_EVENT_NOTIF_MASK_FINE_EVENT: FINE Event Mask (Def: bit 26) + * + * These macros, defining the task notification bit masks, can be redefined as + * needed. + * + * If one of the macros for callback functions presented in the previous + * section (for direct ISR notifications) is defined, while in this mode, + * the function with the same name will be called directly from the isr + * instead of sending a task notification for this particular event to + * the app task. + * + * Macro dg_configBLE_EVENT_NOTIF_RUNTIME_CONTROL (Default: 1) enables/disables + * runtime control/masking of notifications. + * + * If dg_configBLE_EVENT_NOTIF_RUNTIME_CONTROL == 1, then task notifications + * must be enabled/disabled using the + * ble_event_notif_[enable|disable]_[end|cscnt|fine]_event() functions. + * By default all notifications are disabled. + * + * If dg_configBLE_EVENT_NOTIF_RUNTIME_CONTROL == 0, all notifications will + * be sent unconditionally to the application task. + * + */ +#ifndef dg_configBLE_EVENT_NOTIF_TYPE +# define dg_configBLE_EVENT_NOTIF_TYPE BLE_EVENT_NOTIF_USER_ISR +#endif + +#if dg_configBLE_EVENT_NOTIF_TYPE == BLE_EVENT_NOTIF_USER_TASK + +/* Default implementation of BLE event task notifications. This + * implementation allows a user task to register for notifications, + * and to get task notifications for the available events + */ + +/* Default task notification masks for the various events for which + * the framework provides notifications + */ +# ifndef dg_configBLE_EVENT_NOTIF_MASK_END_EVENT +# define dg_configBLE_EVENT_NOTIF_MASK_END_EVENT (1 << 24) +# endif + +# ifndef dg_configBLE_EVENT_NOTIF_MASK_CSCNT_EVENT +# define dg_configBLE_EVENT_NOTIF_MASK_CSCNT_EVENT (1 << 25) +# endif + +# ifndef dg_configBLE_EVENT_NOTIF_MASK_FINE_EVENT +# define dg_configBLE_EVENT_NOTIF_MASK_FINE_EVENT (1 << 26) +# endif + +/* Implement event hook functions */ +# ifndef dg_configBLE_EVENT_NOTIF_HOOK_END_EVENT +# define dg_configBLE_EVENT_NOTIF_HOOK_END_EVENT ble_event_notif_app_task_end_event +# endif + +# ifndef dg_configBLE_EVENT_NOTIF_HOOK_CSCNT_EVENT +# define dg_configBLE_EVENT_NOTIF_HOOK_CSCNT_EVENT ble_event_notif_app_task_cscnt_event +# endif + +# ifndef dg_configBLE_EVENT_NOTIF_HOOK_FINE_EVENT +# define dg_configBLE_EVENT_NOTIF_HOOK_FINE_EVENT ble_event_notif_app_task_fine_event +# endif + +/* + * Allow runtime control of (un)masking notifications + */ +# ifndef dg_configBLE_EVENT_NOTIF_RUNTIME_CONTROL +# define dg_configBLE_EVENT_NOTIF_RUNTIME_CONTROL 1 +# endif + +#endif +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/* ----------------------------------- BLE hooks configuration ---------------------------------- */ + +/* Name of the function that is called to block BLE from sleeping under certain conditions + * + * The function must be declared as: + * unsigned char my_block_sleep(void); + * The return value of the function controls whether the BLE will be allowed to go to sleep or not, + * 0: the BLE may go to sleep, if possible + * 1: the BLE is not allowed to go to sleep. The caller (BLE Adapter) may block or not, + * depending on the BLE stack status. + * + * dg_configBLE_HOOK_BLOCK_SLEEP should be set to my_block_sleep in this example. + */ +#ifndef dg_configBLE_HOOK_BLOCK_SLEEP +/* Already undefined - Nothing to do. */ +#endif + +/* Name of the function that is called to modify the PTI value (Payload Type Indication) when + * arbitration is used + * + * Arbitration is needed only when another external radio is present. The function must be declared + * as: + * unsigned char my_pti_modify(void); + * Details for the implementation of such a function will be provided when the external radio + * arbitration functionality is integrated. + * + * dg_configBLE_HOOK_PTI_MODIFY should be set to my_pti_modify in this example. + * + * See also the comment about the in ble_config.h for more info. + */ +#ifndef dg_configBLE_HOOK_PTI_MODIFY +/* Already undefined - Nothing to do. */ +#endif /* ---------------------------------------------------------------------------------------------- */ -/* -----------------------------------OS related configuration ---------------------------------- */ +/** + * \addtogroup DEBUG_SETTINGS + * + * \{ + */ +/* ---------------------------------- OS related configuration ---------------------------------- */ + +/** + * \brief Monitor OS heap allocations + * + * \bsp_default_note{\bsp_config_option_app,} + */ #ifndef dg_configTRACK_OS_HEAP -# define dg_configTRACK_OS_HEAP (0) +#define dg_configTRACK_OS_HEAP (0) #endif + +/* ---------------------------------------------------------------------------------------------- */ + +/** + * \} + */ + +/* ---------------------------------- Heap size configuration ----------------------------------- */ + +/** + * \brief Heap size for used libc malloc() + * + * Specifies the amount of RAM that will be used as heap for libc malloc() function. + * It can be configured in bare metal projects to match application's requirements. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef __HEAP_SIZE +# if defined (CONFIG_RETARGET) || defined (CONFIG_RTT) +# define __HEAP_SIZE 0x0600 +# else +# define __HEAP_SIZE 0x0100 +# endif +#endif + +/* flag used by linker scripts */ +#if (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A) +#define __HEAP_IS_LESS_THAN_0x200 (__HEAP_SIZE < 0x200) +#endif + +/* ---------------------------------------------------------------------------------------------- */ + +/* --------------------------------- Stack size configuration ----------------------------------- */ + +/** + * \brief Stack size for main() function and interrupt handlers. + * + * Specifies the amount of RAM that will be used as stack for the main() function and the interrupt + * handlers. + * + * \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only} + */ +#ifndef __STACK_SIZE +#define __STACK_SIZE 0x0200 +#endif + /* ---------------------------------------------------------------------------------------------- */ /* ----------------------------------- RF FEM CONFIGURATION ------------------------------------- */ @@ -1425,6 +2465,7 @@ /* ---------------------------------------------------------------------------------------------- */ + #endif /* BSP_DEFAULTS_H_ */ /** diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h b/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h old mode 100755 new mode 100644 index 04230f711..e64160c3b --- a/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h +++ b/third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h @@ -1,3 +1,16 @@ +/** + * \addtogroup BSP + * \{ + * \addtogroup BSP_CONFIG + * \{ + * \addtogroup BSP_CONFIG_DEFINITIONS + * + * \brief Doxygen documentation is not yet available for this module. + * Please check the source code file(s) + * + *\{ + */ + /** **************************************************************************************** * @@ -28,7 +41,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * **************************************************************************************** */ @@ -38,17 +52,17 @@ /* ------------------------------------ Generic definitions ------------------------------------- */ -#define POWER_CONFIGURATION_1 0 -#define POWER_CONFIGURATION_2 1 -#define POWER_CONFIGURATION_3 2 - #define LP_CLK_32000 0 #define LP_CLK_32768 1 #define LP_CLK_RCX 2 +#define LP_CLK_ANY 3 + +#define LP_CLK_IS_ANALOG 0 +#define LP_CLK_IS_DIGITAL 1 #define MODE_IS_MIRRORED 0 #define MODE_IS_CACHED 1 -#define MODE_IS_RAM MODE_IS_CACHED +#define MODE_IS_RAM MODE_IS_MIRRORED #define NON_VOLATILE_IS_OTP 0 // Code is in OTP #define NON_VOLATILE_IS_FLASH 1 // Code is in QSPI Flash @@ -60,6 +74,10 @@ #define DEVELOPMENT_MODE 0 // Code is built for debugging #define PRODUCTION_MODE 1 // Code is built for production +#define FLASH_IS_NOT_CONNECTED 0 +#define FLASH_CONNECTED_TO_1V8 1 +#define FLASH_CONNECTED_TO_1V8P 2 + #define BATTERY_TYPE_2xNIMH 0 #define BATTERY_TYPE_3xNIMH 1 #define BATTERY_TYPE_LICOO2 2 // 2.5V discharge voltage, 4.20V charge voltage @@ -71,33 +89,57 @@ #define BATTERY_TYPE_NO_RECHARGE 8 #define BATTERY_TYPE_NO_BATTERY 9 -#define BATTERY_TYPE_2xNIMH_ADC_VOLTAGE (2784) +#define BATTERY_TYPE_2xNIMH_ADC_VOLTAGE (2785) #define BATTERY_TYPE_3xNIMH_ADC_VOLTAGE (4013) -#define BATTERY_TYPE_LICOO2_ADC_VOLTAGE (3439) -#define BATTERY_TYPE_LIMN2O4_ADC_VOLTAGE (3439) -#define BATTERY_TYPE_NMC_ADC_VOLTAGE (3439) -#define BATTERY_TYPE_LIFEPO4_ADC_VOLTAGE (2947) -#define BATTERY_TYPE_LINICOAIO2_ADC_VOLTAGE (3439) - +#define BATTERY_TYPE_LICOO2_ADC_VOLTAGE (3440) +#define BATTERY_TYPE_LIMN2O4_ADC_VOLTAGE (3440) +#define BATTERY_TYPE_NMC_ADC_VOLTAGE (3440) +#define BATTERY_TYPE_LIFEPO4_ADC_VOLTAGE (2989) +#define BATTERY_TYPE_LINICOAIO2_ADC_VOLTAGE (3440) /* * The supported chip revisions. */ +#define BLACK_ORCA_IC_REV_AUTO (-1) #define BLACK_ORCA_IC_REV_A 0 +#define BLACK_ORCA_IC_REV_B 1 /* * The supported chip steppings. */ +#define BLACK_ORCA_IC_STEP_AUTO (-1) #define BLACK_ORCA_IC_STEP_A 0 #define BLACK_ORCA_IC_STEP_B 1 #define BLACK_ORCA_IC_STEP_C 2 #define BLACK_ORCA_IC_STEP_D 3 +#define BLACK_ORCA_IC_STEP_E 7 /* - * The supported DK motherboards. + * Legacy DK motherboards, which are not supported by the SDK. + * The definitions exist just so that we don't break compilation of old projects. */ #define BLACK_ORCA_MB_REV_A 0 #define BLACK_ORCA_MB_REV_B 1 +/* + * The supported DK motherboards. + */ +#define BLACK_ORCA_MB_REV_D 2 + +/* + * The cache associtivity options. + */ +#define CACHE_ASSOC_AS_IS (-1) /// leave as set by the ROM booter +#define CACHE_ASSOC_DIRECT_MAP 0 /// direct-mapped +#define CACHE_ASSOC_2_WAY 1 /// 2-way set associative +#define CACHE_ASSOC_4_WAY 2 /// 4-way set associative + +/* + * The cache line size options. + */ +#define CACHE_LINESZ_AS_IS (-1) /// leave as set by the ROM booter +#define CACHE_LINESZ_8_BYTES 0 /// 8 bytes +#define CACHE_LINESZ_16_BYTES 1 /// 16 bytes +#define CACHE_LINESZ_32_BYTES 2 /// 32 bytes /* * The supported RF Front-End Modules @@ -105,6 +147,12 @@ #define FEM_NOFEM 0 #define FEM_SKY66112_11 1 +/* + * The BLE event notification user hook types + */ +#define BLE_EVENT_NOTIF_USER_ISR 0 /// User-defined hooks directly from ISR context +#define BLE_EVENT_NOTIF_USER_TASK 1 /// Notification of the user task, using task notifications. + #endif /* BSP_DEFINITIONS_H_ */ /** diff --git a/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h b/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h old mode 100755 new mode 100644 index 5780e6c18..3ce3c0c5b --- a/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h +++ b/third_party/dialog/DialogSDK/bsp/config/bsp_fem.h @@ -1,5 +1,17 @@ - /** - **************************************************************************************** +/** + * \addtogroup BSP + * \{ + * \addtogroup BSP_CONFIG + * \{ + * \addtogroup RF_FEM + * + * \brief RF Front-End module confguration + * + *\{ + */ + +/** + *************************************************************************************** * * @file bsp_fem.h * @@ -28,9 +40,10 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************** - */ + * + * + *************************************************************************************** +*/ #ifndef BSP_FEM_H_ #define BSP_FEM_H_ @@ -39,16 +52,12 @@ #ifdef dg_configFEM_DLG_REF_BOARD -#undef dg_configBLACK_ORCA_IC_STEP -#define dg_configBLACK_ORCA_IC_STEP BLACK_ORCA_IC_STEP_D - #define dg_configFEM FEM_SKY66112_11 -#ifndef dg_configPOWER_EXT_1V8_PERIPHERALS -#if dg_configPOWER_EXT_1V8_PERIPHERALS == 0 -#warning Setting dg_configPOWER_EXT_1V8_PERIPHERALS to 1 for FEM to work -#define dg_configPOWER_EXT_1V8_PERIPHERALS 1 -#endif +#if dg_configPOWER_1V8P == 0 +#warning Setting dg_configPOWER_1V8P to 1 for FEM to work +#undef dg_configPOWER_1V8P +#define dg_configPOWER_1V8P 1 #endif #define dg_configFEM_SKY66112_11_FEM_BIAS_V18P @@ -59,7 +68,7 @@ #endif #ifndef dg_configFEM_SKY66112_11_CSD_PIN -#define dg_configFEM_SKY66112_11_CSD_PIN HW_GPIO_PIN_2 +#define dg_configFEM_SKY66112_11_CSD_PIN HW_GPIO_PIN_3 #endif #ifndef dg_configFEM_SKY66112_11_CPS_PORT @@ -67,7 +76,7 @@ #endif #ifndef dg_configFEM_SKY66112_11_CPS_PIN -#define dg_configFEM_SKY66112_11_CPS_PIN HW_GPIO_PIN_7 +#define dg_configFEM_SKY66112_11_CPS_PIN HW_GPIO_PIN_6 #endif #ifndef dg_configFEM_SKY66112_11_CRX_PORT @@ -75,7 +84,7 @@ #endif #ifndef dg_configFEM_SKY66112_11_CRX_PIN -#define dg_configFEM_SKY66112_11_CRX_PIN HW_GPIO_PIN_4 +#define dg_configFEM_SKY66112_11_CRX_PIN HW_GPIO_PIN_2 #endif #ifndef dg_configFEM_SKY66112_11_CTX_PORT @@ -83,7 +92,7 @@ #endif #ifndef dg_configFEM_SKY66112_11_CTX_PIN -#define dg_configFEM_SKY66112_11_CTX_PIN HW_GPIO_PIN_6 +#define dg_configFEM_SKY66112_11_CTX_PIN HW_GPIO_PIN_5 #endif #ifndef dg_configFEM_SKY66112_11_CHL_PORT @@ -91,7 +100,7 @@ #endif #ifndef dg_configFEM_SKY66112_11_CHL_PIN -#define dg_configFEM_SKY66112_11_CHL_PIN HW_GPIO_PIN_5 +#define dg_configFEM_SKY66112_11_CHL_PIN HW_GPIO_PIN_4 #endif #ifndef dg_configFEM_SKY66112_11_ANTSEL_PORT @@ -99,7 +108,7 @@ #endif #ifndef dg_configFEM_SKY66112_11_ANTSEL_PIN -#define dg_configFEM_SKY66112_11_ANTSEL_PIN HW_GPIO_PIN_3 +#define dg_configFEM_SKY66112_11_ANTSEL_PIN HW_GPIO_PIN_0 #endif #endif /* dg_configFEM_DLG_REF_BOARD */ diff --git a/third_party/dialog/DialogSDK/bsp/include/ARMCM0.h b/third_party/dialog/DialogSDK/bsp/include/ARMCM0.h old mode 100755 new mode 100644 index c5ae6a8c4..22e3be182 --- a/third_party/dialog/DialogSDK/bsp/include/ARMCM0.h +++ b/third_party/dialog/DialogSDK/bsp/include/ARMCM0.h @@ -36,65 +36,8 @@ #ifndef ARMCM0_H #define ARMCM0_H -#include "global_io.h" -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - #include /* Cortex-M0 processor and core peripherals */ #include "system_ARMCM0.h" /* System Header */ - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -/*--------------------- General Purpose Input and Ouptut ---------------------*/ -typedef union -{ - __IO uint32_t WORD; - __IO uint8_t BYTE[4]; -} GPIO_Data_TypeDef; - -typedef struct -{ - GPIO_Data_TypeDef DATA[256]; - __O uint32_t DIR; - uint32_t RESERVED[3]; - __O uint32_t IE; -} ARM_GPIO_TypeDef; - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Peripheral and SRAM base address */ -#define ARM_SRAM_BASE (( uint32_t)0x20000000UL) -#define ARM_PERIPH_BASE (( uint32_t)0x40000000UL) - -/* Peripheral memory map */ -#define ARM_GPIO_BASE ARM_PERIPH_BASE - -#define ARM_GPIO0_BASE (ARM_GPIO_BASE) -#define ARM_GPIO1_BASE (ARM_GPIO_BASE + 0x0800UL) -#define ARM_GPIO2_BASE (ARM_GPIO_BASE + 0x1000UL) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define ARM_GPIO0 ((ARM_GPIO_TypeDef *) ARM_GPIO0_BASE) -#define ARM_GPIO1 ((ARM_GPIO_TypeDef *) ARM_GPIO1_BASE) -#define ARM_GPIO2 ((ARM_GPIO_TypeDef *) ARM_GPIO2_BASE) - - #endif /* ARMCM0_H */ diff --git a/third_party/dialog/DialogSDK/bsp/include/DA14680AD.h b/third_party/dialog/DialogSDK/bsp/include/DA14680BA.h old mode 100755 new mode 100644 similarity index 91% rename from third_party/dialog/DialogSDK/bsp/include/DA14680AD.h rename to third_party/dialog/DialogSDK/bsp/include/DA14680BA.h index f1fcd52b5..66febdf9e --- a/third_party/dialog/DialogSDK/bsp/include/DA14680AD.h +++ b/third_party/dialog/DialogSDK/bsp/include/DA14680BA.h @@ -1,21 +1,4 @@ - -/****************************************************************************************************//** - * @file DA14680AD.h - * - * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for - * DA14680AD from Dialog. - * - * @version V1.2 - * @date 18. February 2016 - * - * @note Generated with SVDConv V2.87g - * from CMSIS SVD File 'DA14680AD.xml' Version 1.2, - * - * @par Dialog GmbH (DLG) is supplying this software for use with Cortex-M - * processor based microcontroller, but can be equally used for other - * suitable processor architectures. This file can be freely distributed. - * Modifications to this file shall be clearly marked. - * +/* * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -39,8 +22,15 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************************************/ + * + * @file DA14680BA.h + * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for DA14680BA from Dialog. + * @version V1.2 + * @date 9. August 2016 + * @note Generated with SVDConv V2.87g + * from CMSIS SVD File 'DA14680BA.xml' + * Version 1.2 + */ @@ -48,12 +38,13 @@ * @{ */ -/** @addtogroup DA14680AD + +/** @addtogroup DA14680BA * @{ */ -#ifndef DA14680AD_H -#define DA14680AD_H +#ifndef DA14680BA_H +#define DA14680BA_H #ifdef __cplusplus extern "C" { @@ -74,7 +65,7 @@ typedef enum { SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* -------------------- DA14680AD Specific Interrupt Numbers -------------------- */ +/* -------------------- DA14680BA Specific Interrupt Numbers -------------------- */ BLE_WAKEUP_LP_IRQn = 0, /*!< 0 BLE_WAKEUP_LP */ BLE_GEN_IRQn = 1, /*!< 1 BLE_GEN */ FTDF_WAKEUP_IRQn = 2, /*!< 2 FTDF_WAKEUP */ @@ -106,11 +97,11 @@ typedef enum { TRNG_IRQn = 28, /*!< 28 TRNG */ DCDC_IRQn = 29, /*!< 29 DCDC */ XTAL16RDY_IRQn = 30, /*!< 30 XTAL16RDY */ - RESERVED31_IRQn = 31 /*!< 31 RESERVED31 */ + PLL_LOCK_IRQn = 31 /*!< 31 PLL_LOCK */ } IRQn_Type; -/** @addtogroup Configuration_of_CMSIS +/** @addtogroup Configuration_of_CMSIS_DA14680BA * @{ */ @@ -127,7 +118,7 @@ typedef enum { /** @} */ /* End of group Configuration_of_CMSIS */ #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ -#include "system_DA14680.h" /*!< DA14680AD System */ +#include "system_DA14680.h" /*!< DA14680BA System */ /* ================================================================================ */ @@ -135,7 +126,7 @@ typedef enum { /* ================================================================================ */ -/** @addtogroup Device_Peripheral_Registers +/** @addtogroup Device_Peripheral_Registers_DA14680BA * @{ */ @@ -335,8 +326,7 @@ typedef struct { /*!< (@ 0x40000000) BLE Stru __IO uint32_t BLE_COEXIFCNTL1_REG; /*!< (@ 0x40000104) Coexistence interface Control 1 Register */ __IO uint32_t BLE_BLEMPRIO0_REG; /*!< (@ 0x40000108) Coexistence interface Priority 0 Register */ __IO uint32_t BLE_BLEMPRIO1_REG; /*!< (@ 0x4000010C) Coexistence interface Priority 1 Register */ - __IO uint32_t BLE_BLEPRIOSCHARB_REG; /*!< (@ 0x40000110) Priority Scheduling Arbiter Control Register */ - __I uint32_t RESERVED7[59]; + __I uint32_t RESERVED7[60]; __IO uint32_t BLE_CNTL2_REG; /*!< (@ 0x40000200) BLE Control Register 2 */ __I uint32_t RESERVED8; __IO uint32_t BLE_EM_BASE_REG; /*!< (@ 0x40000208) Exchange Memory Base Register */ @@ -393,6 +383,7 @@ typedef struct { /*!< (@ 0x50003200) CHIP_VER __I uint16_t RESERVED; __IO uint8_t CHIP_TEST1_REG; /*!< (@ 0x5000320A) Chip test register 1. */ __IO uint8_t CHIP_TEST2_REG; /*!< (@ 0x5000320B) Chip test register 2. */ + __IO uint8_t CHIP_TEST3_REG; /*!< (@ 0x5000320C) Chip test register 3. */ } CHIP_VERSION_Type; @@ -408,11 +399,11 @@ typedef struct { /*!< (@ 0x50003200) CHIP_VER typedef struct { /*!< (@ 0x50002F00) COEX Structure */ __IO uint16_t COEX_CTRL_REG; /*!< (@ 0x50002F00) COEX Control Register */ __IO uint16_t COEX_STAT_REG; /*!< (@ 0x50002F02) COEX Status Register */ - __IO uint16_t COEX_INT_MASK_REG; /*!< (@ 0x50002F04) COEX Interrupt Mask Register */ - __IO uint16_t COEX_INT_STAT_REG; /*!< (@ 0x50002F06) COEX Interrupt Status Register */ - __IO uint16_t COEX_BLE_PTI_REG; /*!< (@ 0x50002F08) COEX BLE PTI Control Register */ - __IO uint16_t COEX_FTDF_PTI_REG; /*!< (@ 0x50002F0A) COEX FTDF PTI Control Register */ - __IO uint16_t COEX_DIAG_REG; /*!< (@ 0x50002F0C) COEX Diagnostic Monitor Register */ + __IO uint16_t COEX_STAT2_REG; /*!< (@ 0x50002F04) COEX Status 2 Register */ + __IO uint16_t COEX_INT_MASK_REG; /*!< (@ 0x50002F06) COEX Interrupt Mask Register */ + __IO uint16_t COEX_INT_STAT_REG; /*!< (@ 0x50002F08) COEX Interrupt Status Register */ + __IO uint16_t COEX_BLE_PTI_REG; /*!< (@ 0x50002F0A) COEX BLE PTI Control Register */ + __IO uint16_t COEX_FTDF_PTI_REG; /*!< (@ 0x50002F0C) COEX FTDF PTI Control Register */ __I uint16_t RESERVED[2]; __IO uint16_t COEX_PRI1_REG; /*!< (@ 0x50002F12) COEX Priority Register */ __IO uint16_t COEX_PRI2_REG; /*!< (@ 0x50002F14) COEX Priority Register */ @@ -429,8 +420,6 @@ typedef struct { /*!< (@ 0x50002F00) COEX Str __IO uint16_t COEX_PRI13_REG; /*!< (@ 0x50002F2A) COEX Priority Register */ __IO uint16_t COEX_PRI14_REG; /*!< (@ 0x50002F2C) COEX Priority Register */ __IO uint16_t COEX_PRI15_REG; /*!< (@ 0x50002F2E) COEX Priority Register */ - __IO uint16_t COEX_PRI16_REG; /*!< (@ 0x50002F30) COEX Priority Register */ - __IO uint16_t COEX_PRI17_REG; /*!< (@ 0x50002F32) COEX Priority Register */ } COEX_Type; @@ -477,9 +466,7 @@ typedef struct { /*!< (@ 0x50000000) CRG_TOP __IO uint16_t SYS_CTRL_REG; /*!< (@ 0x50000012) System Control register */ __IO uint16_t SYS_STAT_REG; /*!< (@ 0x50000014) System status register */ __IO uint16_t TRIM_CTRL_REG; /*!< (@ 0x50000016) Control trimming of the XTAL16M */ - __IO uint16_t DIVN_SYNC_REG; /*!< (@ 0x50000018) Trigger to sync DIVN with the RF clock divider - in case of 32 MHz crystal */ - __I uint16_t RESERVED2[3]; + __I uint32_t RESERVED2[2]; __IO uint16_t CLK_32K_REG; /*!< (@ 0x50000020) 32 kHz oscillator register */ __IO uint16_t CLK_16M_REG; /*!< (@ 0x50000022) 16 MHz RC and xtal oscillator register */ __IO uint16_t CLK_RCX20K_REG; /*!< (@ 0x50000024) 20KHz RXC-oscillator control register */ @@ -497,14 +484,24 @@ typedef struct { /*!< (@ 0x50000000) CRG_TOP __IO uint16_t LDO_CTRL2_REG; /*!< (@ 0x5000003C) LDO control register */ __IO uint16_t SLEEP_TIMER_REG; /*!< (@ 0x5000003E) Timer for regulated sleep */ __IO uint16_t POWER_CTRL_REG; /*!< (@ 0x50000040) Power control register */ - __I uint16_t RESERVED5[7]; + __IO uint16_t POR_VBAT_CTRL_REG; /*!< (@ 0x50000042) Controls the POR on VBAT */ + __I uint32_t RESERVED5[3]; __IO uint16_t XTALRDY_CTRL_REG; /*!< (@ 0x50000050) Control register for XTALRDY IRQ */ __IO uint16_t XTALRDY_STAT_REG; /*!< (@ 0x50000052) Difference between XTAL_OK and XTALRDY_IRQ in LP clock cycles */ - __I uint32_t RESERVED6[3]; + __IO uint16_t LDO_CTRL3_REG; /*!< (@ 0x50000054) Retention LDO control register */ + __I uint16_t RESERVED6; + __IO uint16_t XTAL16M_START_REG; /*!< (@ 0x50000058) Xtal frequency trimming register during startup */ + __IO uint16_t XTAL16M_RAMP_REG; /*!< (@ 0x5000005A) Xtal frequency trimming register during ramping */ + __IO uint16_t XTAL16M_TRSTAT_REG; /*!< (@ 0x5000005C) Read back value of current XTAL trimming */ + __IO uint16_t RESET_STAT_REG; /*!< (@ 0x5000005E) Reset status register */ __IO uint16_t FORCE_SLEEP_REG; /*!< (@ 0x50000060) Force FTDF/BLE to sleep */ __IO uint16_t LDOS_DISABLE_REG; /*!< (@ 0x50000062) Force off all LDOs */ __IO uint16_t AON_SPARE_REG; /*!< (@ 0x50000064) Spare register */ + __IO uint16_t SECURE_BOOT_REG; /*!< (@ 0x50000066) Controls secure booting */ + __IO uint16_t PMU_RESET_RAIL_REG; /*!< (@ 0x50000068) Controls rail resetting when RST is pulsed */ + __IO uint16_t DISCHARGE_RAIL_REG; /*!< (@ 0x5000006A) Immediate rail resetting. There is no LDO/DCDC + gating */ } CRG_TOP_Type; @@ -596,6 +593,8 @@ typedef struct { /*!< (@ 0x50002E00) DEM Stru __IO uint16_t RF_FSSS_I_RESULT_REG; /*!< (@ 0x50002E50) RF_FSSS_I_RESULT_REG */ __IO uint16_t RF_FSSS_Q_RESULT_REG; /*!< (@ 0x50002E52) RF_FSSS_Q_RESULT_REG */ __IO uint16_t RF_FSSS_MAG_RESULT_REG; /*!< (@ 0x50002E54) RF_FSSS_MAG_RESULT_REG */ + __IO uint16_t RF_CCA_RSSITH_REG; /*!< (@ 0x50002E56) RF_CCA_RSSITH_REG */ + __IO uint16_t RF_FTDF_SIGDET_CTRL_REG; /*!< (@ 0x50002E58) RF_FTDF_SIGDET_CTRL_REG */ } DEM_Type; @@ -694,8 +693,6 @@ typedef struct { /*!< (@ 0x50006000) ECC Stru __IO uint32_t ECC_CONTROL_REG; /*!< (@ 0x50006008) Control register */ __IO uint32_t ECC_STATUS_REG; /*!< (@ 0x5000600C) Status register */ __IO uint32_t ECC_VERSION_REG; /*!< (@ 0x50006010) Version register */ - __IO uint32_t ECC_LOADMICROCODE_REG; /*!< (@ 0x50006014) Used to upload Crypto Code from CPU into the - uCode ram */ } ECC_Type; @@ -879,7 +876,8 @@ typedef struct { /*!< (@ 0x40080000) FTDF Str __IO uint32_t FTDF_MACFCSERRORCOUNT_REG; /*!< (@ 0x40090340) Lmac FCS error register */ __I uint32_t RESERVED43[7]; __IO uint32_t FTDF_LMACRESET_REG; /*!< (@ 0x40090360) Lmax reset register */ - __I uint32_t RESERVED44[7]; + __IO uint32_t FTDF_WAKEUP_CONTROL_OS_REG; /*!< (@ 0x40090364) FTDF_WAKEUP_CONTROL_OS_REG */ + __I uint32_t RESERVED44[6]; __IO uint32_t FTDF_SYMBOLTIMETHR_REG; /*!< (@ 0x40090380) Symboltime threshold register 1 */ __IO uint32_t FTDF_SYMBOLTIME2THR_REG; /*!< (@ 0x40090384) Symboltime threshold register 2 */ __I uint32_t RESERVED45[2]; @@ -918,8 +916,11 @@ typedef struct { /*!< (@ 0x40080000) FTDF Str __IO uint32_t FTDF_TX_SET_OS_REG; /*!< (@ 0x40090480) One shot register to set flag */ __IO uint32_t FTDF_TX_CLEAR_OS_REG; /*!< (@ 0x40090484) One shot register to clear flag */ __I uint32_t RESERVED55[734]; - __IO uint32_t FTDF_WAKEUPINTTHR_REG; /*!< (@ 0x40091000) Treshold value Wakeup timer */ - __IO uint32_t FTDF_WAKEUP_CONTROL_REG; /*!< (@ 0x40091004) Wakeup timer vcontrol register */ + __IO uint32_t FTDF_WAKEUP_CONTROL_REG; /*!< (@ 0x40091000) Wakeup timer vcontrol register */ + __I uint32_t RESERVED56[1023]; + __IO uint32_t FTDF_LONG_ADDR_0_0_REG; /*!< (@ 0x40092000) FTDF_LONG_ADDR_0_0_REG */ + __IO uint32_t FTDF_LONG_ADDR_1_0_REG; /*!< (@ 0x40092004) FTDF_LONG_ADDR_1_0_REG */ + __IO uint32_t FTDF_SIZE_AND_VAL_0_REG; /*!< (@ 0x40092008) FTDF_SIZE_AND_VAL_0_REG */ } FTDF_Type; @@ -1047,9 +1048,10 @@ typedef struct { /*!< (@ 0x50003000) GPIO Str __IO uint16_t BIST_CTRL_REG; /*!< (@ 0x500030E0) BIST_CTRL_REG */ __IO uint16_t RAMBIST_STATUS1_REG; /*!< (@ 0x500030E2) RAMBIST_STATUS1_REG */ __IO uint16_t RAMBIST_STATUS2_REG; /*!< (@ 0x500030E4) RAMBIST_STATUS2_REG */ - __IO uint16_t ROMBIST_RESULTL_REG; /*!< (@ 0x500030E6) ROMBIST_RESULTL_REG */ - __IO uint16_t ROMBIST_RESULTH_REG; /*!< (@ 0x500030E8) ROMBIST_RESULTH_REG */ - __I uint16_t RESERVED4[3]; + __IO uint16_t RAMBIST_STATUS3_REG; /*!< (@ 0x500030E6) RAMBIST_STATUS3_REG */ + __IO uint16_t ROMBIST_RESULTL_REG; /*!< (@ 0x500030E8) ROMBIST_RESULTL_REG */ + __IO uint16_t ROMBIST_RESULTH_REG; /*!< (@ 0x500030EA) ROMBIST_RESULTH_REG */ + __I uint32_t RESERVED4; __IO uint16_t TEST_CTRL_REG; /*!< (@ 0x500030F0) TEST_CTRL_REG */ __IO uint16_t TEST_CTRL2_REG; /*!< (@ 0x500030F2) TEST_CTRL2_REG */ __IO uint16_t TEST_CTRL3_REG; /*!< (@ 0x500030F4) TEST_CTRL3_REG */ @@ -1077,7 +1079,8 @@ typedef struct { /*!< (@ 0x50003300) GPREG St __IO uint16_t GP_CONTROL_REG; /*!< (@ 0x50003308) General purpose system control register. */ __IO uint16_t ECC_BASE_ADDR_REG; /*!< (@ 0x5000330A) Base address of the ECC Crypto memory register. */ __IO uint16_t LED_CONTROL_REG; /*!< (@ 0x5000330C) Controls muxing and enabling of the LEDs. */ - __I uint16_t RESERVED; + __IO uint16_t BLE_FINECNT_SAMP_REG; /*!< (@ 0x5000330E) BLE FINECNT sampled value while in deep sleep + state. */ __IO uint16_t PLL_SYS_CTRL1_REG; /*!< (@ 0x50003310) System PLL control register 1. */ __IO uint16_t PLL_SYS_CTRL2_REG; /*!< (@ 0x50003312) System PLL control register 2. */ __IO uint16_t PLL_SYS_CTRL3_REG; /*!< (@ 0x50003314) System PLL control register 3. */ @@ -1101,77 +1104,75 @@ typedef struct { /*!< (@ 0x50001400) I2C Stru __IO uint16_t I2C_TAR_REG; /*!< (@ 0x50001404) I2C Target Address Register */ __I uint16_t RESERVED1; __IO uint16_t I2C_SAR_REG; /*!< (@ 0x50001408) I2C Slave Address Register */ - __I uint16_t RESERVED2; - __IO uint16_t I2C_HS_MADDR_REG; /*!< (@ 0x5000140C) I2C High Speed Master Mode Code Address Register */ - __I uint16_t RESERVED3; + __I uint16_t RESERVED2[3]; __IO uint16_t I2C_DATA_CMD_REG; /*!< (@ 0x50001410) I2C Rx/Tx Data Buffer and Command Register */ - __I uint16_t RESERVED4; + __I uint16_t RESERVED3; __IO uint16_t I2C_SS_SCL_HCNT_REG; /*!< (@ 0x50001414) Standard Speed I2C Clock SCL High Count Register */ - __I uint16_t RESERVED5; + __I uint16_t RESERVED4; __IO uint16_t I2C_SS_SCL_LCNT_REG; /*!< (@ 0x50001418) Standard Speed I2C Clock SCL Low Count Register */ - __I uint16_t RESERVED6; + __I uint16_t RESERVED5; __IO uint16_t I2C_FS_SCL_HCNT_REG; /*!< (@ 0x5000141C) Fast Speed I2C Clock SCL High Count Register */ - __I uint16_t RESERVED7; + __I uint16_t RESERVED6; __IO uint16_t I2C_FS_SCL_LCNT_REG; /*!< (@ 0x50001420) Fast Speed I2C Clock SCL Low Count Register */ - __I uint16_t RESERVED8[5]; + __I uint16_t RESERVED7[5]; __IO uint16_t I2C_INTR_STAT_REG; /*!< (@ 0x5000142C) I2C Interrupt Status Register */ - __I uint16_t RESERVED9; + __I uint16_t RESERVED8; __IO uint16_t I2C_INTR_MASK_REG; /*!< (@ 0x50001430) I2C Interrupt Mask Register */ - __I uint16_t RESERVED10; + __I uint16_t RESERVED9; __IO uint16_t I2C_RAW_INTR_STAT_REG; /*!< (@ 0x50001434) I2C Raw Interrupt Status Register */ - __I uint16_t RESERVED11; + __I uint16_t RESERVED10; __IO uint16_t I2C_RX_TL_REG; /*!< (@ 0x50001438) I2C Receive FIFO Threshold Register */ - __I uint16_t RESERVED12; + __I uint16_t RESERVED11; __IO uint16_t I2C_TX_TL_REG; /*!< (@ 0x5000143C) I2C Transmit FIFO Threshold Register */ - __I uint16_t RESERVED13; + __I uint16_t RESERVED12; __IO uint16_t I2C_CLR_INTR_REG; /*!< (@ 0x50001440) Clear Combined and Individual Interrupt Register */ - __I uint16_t RESERVED14; + __I uint16_t RESERVED13; __IO uint16_t I2C_CLR_RX_UNDER_REG; /*!< (@ 0x50001444) Clear RX_UNDER Interrupt Register */ - __I uint16_t RESERVED15; + __I uint16_t RESERVED14; __IO uint16_t I2C_CLR_RX_OVER_REG; /*!< (@ 0x50001448) Clear RX_OVER Interrupt Register */ - __I uint16_t RESERVED16; + __I uint16_t RESERVED15; __IO uint16_t I2C_CLR_TX_OVER_REG; /*!< (@ 0x5000144C) Clear TX_OVER Interrupt Register */ - __I uint16_t RESERVED17; + __I uint16_t RESERVED16; __IO uint16_t I2C_CLR_RD_REQ_REG; /*!< (@ 0x50001450) Clear RD_REQ Interrupt Register */ - __I uint16_t RESERVED18; + __I uint16_t RESERVED17; __IO uint16_t I2C_CLR_TX_ABRT_REG; /*!< (@ 0x50001454) Clear TX_ABRT Interrupt Register */ - __I uint16_t RESERVED19; + __I uint16_t RESERVED18; __IO uint16_t I2C_CLR_RX_DONE_REG; /*!< (@ 0x50001458) Clear RX_DONE Interrupt Register */ - __I uint16_t RESERVED20; + __I uint16_t RESERVED19; __IO uint16_t I2C_CLR_ACTIVITY_REG; /*!< (@ 0x5000145C) Clear ACTIVITY Interrupt Register */ - __I uint16_t RESERVED21; + __I uint16_t RESERVED20; __IO uint16_t I2C_CLR_STOP_DET_REG; /*!< (@ 0x50001460) Clear STOP_DET Interrupt Register */ - __I uint16_t RESERVED22; + __I uint16_t RESERVED21; __IO uint16_t I2C_CLR_START_DET_REG; /*!< (@ 0x50001464) Clear START_DET Interrupt Register */ - __I uint16_t RESERVED23; + __I uint16_t RESERVED22; __IO uint16_t I2C_CLR_GEN_CALL_REG; /*!< (@ 0x50001468) Clear GEN_CALL Interrupt Register */ - __I uint16_t RESERVED24; + __I uint16_t RESERVED23; __IO uint16_t I2C_ENABLE_REG; /*!< (@ 0x5000146C) I2C Enable Register */ - __I uint16_t RESERVED25; + __I uint16_t RESERVED24; __IO uint16_t I2C_STATUS_REG; /*!< (@ 0x50001470) I2C Status Register */ - __I uint16_t RESERVED26; + __I uint16_t RESERVED25; __IO uint16_t I2C_TXFLR_REG; /*!< (@ 0x50001474) I2C Transmit FIFO Level Register */ - __I uint16_t RESERVED27; + __I uint16_t RESERVED26; __IO uint16_t I2C_RXFLR_REG; /*!< (@ 0x50001478) I2C Receive FIFO Level Register */ - __I uint16_t RESERVED28; + __I uint16_t RESERVED27; __IO uint16_t I2C_SDA_HOLD_REG; /*!< (@ 0x5000147C) I2C SDA Hold Time Length Register */ - __I uint16_t RESERVED29; + __I uint16_t RESERVED28; __IO uint16_t I2C_TX_ABRT_SOURCE_REG; /*!< (@ 0x50001480) I2C Transmit Abort Source Register */ - __I uint16_t RESERVED30[3]; + __I uint16_t RESERVED29[3]; __IO uint16_t I2C_DMA_CR_REG; /*!< (@ 0x50001488) DMA Control Register */ - __I uint16_t RESERVED31; + __I uint16_t RESERVED30; __IO uint16_t I2C_DMA_TDLR_REG; /*!< (@ 0x5000148C) DMA Transmit Data Level Register */ - __I uint16_t RESERVED32; + __I uint16_t RESERVED31; __IO uint16_t I2C_DMA_RDLR_REG; /*!< (@ 0x50001490) I2C Receive Data Level Register */ - __I uint16_t RESERVED33; + __I uint16_t RESERVED32; __IO uint16_t I2C_SDA_SETUP_REG; /*!< (@ 0x50001494) I2C SDA Setup Register */ - __I uint16_t RESERVED34; + __I uint16_t RESERVED33; __IO uint16_t I2C_ACK_GENERAL_CALL_REG; /*!< (@ 0x50001498) I2C ACK General Call Register */ - __I uint16_t RESERVED35; + __I uint16_t RESERVED34; __IO uint16_t I2C_ENABLE_STATUS_REG; /*!< (@ 0x5000149C) I2C Enable Status Register */ - __I uint16_t RESERVED36; + __I uint16_t RESERVED35; __IO uint16_t I2C_IC_FS_SPKLEN_REG; /*!< (@ 0x500014A0) I2C SS and FS spike suppression limit Size */ - __I uint16_t RESERVED37[41]; + __I uint16_t RESERVED36[41]; __IO uint16_t I2C_COMP_PARAM1_REG; /*!< (@ 0x500014F4) Component Parameter Register */ __IO uint16_t I2C_COMP_PARAM2_REG; /*!< (@ 0x500014F6) Component Parameter Register 2 */ __IO uint16_t I2C_COMP_VERSION_REG; /*!< (@ 0x500014F8) I2C Component Version Register */ @@ -1196,77 +1197,75 @@ typedef struct { /*!< (@ 0x50001500) I2C2 Str __IO uint16_t I2C2_TAR_REG; /*!< (@ 0x50001504) I2C Target Address Register */ __I uint16_t RESERVED1; __IO uint16_t I2C2_SAR_REG; /*!< (@ 0x50001508) I2C Slave Address Register */ - __I uint16_t RESERVED2; - __IO uint16_t I2C2_HS_MADDR_REG; /*!< (@ 0x5000150C) I2C High Speed Master Mode Code Address Register */ - __I uint16_t RESERVED3; + __I uint16_t RESERVED2[3]; __IO uint16_t I2C2_DATA_CMD_REG; /*!< (@ 0x50001510) I2C Rx/Tx Data Buffer and Command Register */ - __I uint16_t RESERVED4; + __I uint16_t RESERVED3; __IO uint16_t I2C2_SS_SCL_HCNT_REG; /*!< (@ 0x50001514) Standard Speed I2C Clock SCL High Count Register */ - __I uint16_t RESERVED5; + __I uint16_t RESERVED4; __IO uint16_t I2C2_SS_SCL_LCNT_REG; /*!< (@ 0x50001518) Standard Speed I2C Clock SCL Low Count Register */ - __I uint16_t RESERVED6; + __I uint16_t RESERVED5; __IO uint16_t I2C2_FS_SCL_HCNT_REG; /*!< (@ 0x5000151C) Fast Speed I2C Clock SCL High Count Register */ - __I uint16_t RESERVED7; + __I uint16_t RESERVED6; __IO uint16_t I2C2_FS_SCL_LCNT_REG; /*!< (@ 0x50001520) Fast Speed I2C Clock SCL Low Count Register */ - __I uint16_t RESERVED8[5]; + __I uint16_t RESERVED7[5]; __IO uint16_t I2C2_INTR_STAT_REG; /*!< (@ 0x5000152C) I2C Interrupt Status Register */ - __I uint16_t RESERVED9; + __I uint16_t RESERVED8; __IO uint16_t I2C2_INTR_MASK_REG; /*!< (@ 0x50001530) I2C Interrupt Mask Register */ - __I uint16_t RESERVED10; + __I uint16_t RESERVED9; __IO uint16_t I2C2_RAW_INTR_STAT_REG; /*!< (@ 0x50001534) I2C Raw Interrupt Status Register */ - __I uint16_t RESERVED11; + __I uint16_t RESERVED10; __IO uint16_t I2C2_RX_TL_REG; /*!< (@ 0x50001538) I2C Receive FIFO Threshold Register */ - __I uint16_t RESERVED12; + __I uint16_t RESERVED11; __IO uint16_t I2C2_TX_TL_REG; /*!< (@ 0x5000153C) I2C Transmit FIFO Threshold Register */ - __I uint16_t RESERVED13; + __I uint16_t RESERVED12; __IO uint16_t I2C2_CLR_INTR_REG; /*!< (@ 0x50001540) Clear Combined and Individual Interrupt Register */ - __I uint16_t RESERVED14; + __I uint16_t RESERVED13; __IO uint16_t I2C2_CLR_RX_UNDER_REG; /*!< (@ 0x50001544) Clear RX_UNDER Interrupt Register */ - __I uint16_t RESERVED15; + __I uint16_t RESERVED14; __IO uint16_t I2C2_CLR_RX_OVER_REG; /*!< (@ 0x50001548) Clear RX_OVER Interrupt Register */ - __I uint16_t RESERVED16; + __I uint16_t RESERVED15; __IO uint16_t I2C2_CLR_TX_OVER_REG; /*!< (@ 0x5000154C) Clear TX_OVER Interrupt Register */ - __I uint16_t RESERVED17; + __I uint16_t RESERVED16; __IO uint16_t I2C2_CLR_RD_REQ_REG; /*!< (@ 0x50001550) Clear RD_REQ Interrupt Register */ - __I uint16_t RESERVED18; + __I uint16_t RESERVED17; __IO uint16_t I2C2_CLR_TX_ABRT_REG; /*!< (@ 0x50001554) Clear TX_ABRT Interrupt Register */ - __I uint16_t RESERVED19; + __I uint16_t RESERVED18; __IO uint16_t I2C2_CLR_RX_DONE_REG; /*!< (@ 0x50001558) Clear RX_DONE Interrupt Register */ - __I uint16_t RESERVED20; + __I uint16_t RESERVED19; __IO uint16_t I2C2_CLR_ACTIVITY_REG; /*!< (@ 0x5000155C) Clear ACTIVITY Interrupt Register */ - __I uint16_t RESERVED21; + __I uint16_t RESERVED20; __IO uint16_t I2C2_CLR_STOP_DET_REG; /*!< (@ 0x50001560) Clear STOP_DET Interrupt Register */ - __I uint16_t RESERVED22; + __I uint16_t RESERVED21; __IO uint16_t I2C2_CLR_START_DET_REG; /*!< (@ 0x50001564) Clear START_DET Interrupt Register */ - __I uint16_t RESERVED23; + __I uint16_t RESERVED22; __IO uint16_t I2C2_CLR_GEN_CALL_REG; /*!< (@ 0x50001568) Clear GEN_CALL Interrupt Register */ - __I uint16_t RESERVED24; + __I uint16_t RESERVED23; __IO uint16_t I2C2_ENABLE_REG; /*!< (@ 0x5000156C) I2C Enable Register */ - __I uint16_t RESERVED25; + __I uint16_t RESERVED24; __IO uint16_t I2C2_STATUS_REG; /*!< (@ 0x50001570) I2C Status Register */ - __I uint16_t RESERVED26; + __I uint16_t RESERVED25; __IO uint16_t I2C2_TXFLR_REG; /*!< (@ 0x50001574) I2C Transmit FIFO Level Register */ - __I uint16_t RESERVED27; + __I uint16_t RESERVED26; __IO uint16_t I2C2_RXFLR_REG; /*!< (@ 0x50001578) I2C Receive FIFO Level Register */ - __I uint16_t RESERVED28; + __I uint16_t RESERVED27; __IO uint16_t I2C2_SDA_HOLD_REG; /*!< (@ 0x5000157C) I2C SDA Hold Time Length Register */ - __I uint16_t RESERVED29; + __I uint16_t RESERVED28; __IO uint16_t I2C2_TX_ABRT_SOURCE_REG; /*!< (@ 0x50001580) I2C Transmit Abort Source Register */ - __I uint16_t RESERVED30[3]; + __I uint16_t RESERVED29[3]; __IO uint16_t I2C2_DMA_CR_REG; /*!< (@ 0x50001588) DMA Control Register */ - __I uint16_t RESERVED31; + __I uint16_t RESERVED30; __IO uint16_t I2C2_DMA_TDLR_REG; /*!< (@ 0x5000158C) DMA Transmit Data Level Register */ - __I uint16_t RESERVED32; + __I uint16_t RESERVED31; __IO uint16_t I2C2_DMA_RDLR_REG; /*!< (@ 0x50001590) I2C Receive Data Level Register */ - __I uint16_t RESERVED33; + __I uint16_t RESERVED32; __IO uint16_t I2C2_SDA_SETUP_REG; /*!< (@ 0x50001594) I2C SDA Setup Register */ - __I uint16_t RESERVED34; + __I uint16_t RESERVED33; __IO uint16_t I2C2_ACK_GENERAL_CALL_REG; /*!< (@ 0x50001598) I2C ACK General Call Register */ - __I uint16_t RESERVED35; + __I uint16_t RESERVED34; __IO uint16_t I2C2_ENABLE_STATUS_REG; /*!< (@ 0x5000159C) I2C Enable Status Register */ - __I uint16_t RESERVED36; + __I uint16_t RESERVED35; __IO uint16_t I2C2_IC_FS_SPKLEN_REG; /*!< (@ 0x500015A0) I2C SS and FS spike suppression limit Size */ - __I uint16_t RESERVED37[41]; + __I uint16_t RESERVED36[41]; __IO uint16_t I2C2_COMP_PARAM1_REG; /*!< (@ 0x500015F4) Component Parameter Register */ __IO uint16_t I2C2_COMP_PARAM2_REG; /*!< (@ 0x500015F6) Component Parameter Register 2 */ __IO uint16_t I2C2_COMP_VERSION_REG; /*!< (@ 0x500015F8) I2C Component Version Register */ @@ -1382,6 +1381,7 @@ typedef struct { /*!< (@ 0x07F40000) OTPC Str be programmed, when the MPROG mode is used. */ __IO uint32_t OTPC_TIM1_REG; /*!< (@ 0x07F40028) Various timing parameters of the OTP cell. */ __IO uint32_t OTPC_TIM2_REG; /*!< (@ 0x07F4002C) Various timing parameters of the OTP cell. */ + __IO uint32_t OTPC_TEST_REG; /*!< (@ 0x07F40030) OTPC_TEST_REG */ } OTPC_Type; @@ -1480,8 +1480,9 @@ typedef struct { /*!< (@ 0x50002D00) PLLDIG S __IO uint16_t RF_VCO_CALCAP_BIT14_REG; /*!< (@ 0x50002D12) RF_VCO_CALCAP_BIT14_REG */ __IO uint16_t RF_VCO_CALCAP_BIT15_REG; /*!< (@ 0x50002D14) RF_VCO_CALCAP_BIT15_REG */ __IO uint16_t RF_BMCW_REG; /*!< (@ 0x50002D16) RF_BMCW_REG */ - __IO uint16_t RF_KMOD_ALPHA_REG; /*!< (@ 0x50002D18) RF_KMOD_ALPHA_REG */ - __I uint16_t RESERVED[2]; + __IO uint16_t RF_KMOD_ALPHA_BLE_REG; /*!< (@ 0x50002D18) RF_KMOD_ALPHA_BLE_REG */ + __IO uint16_t RF_KMOD_ALPHA_FTDF_REG; /*!< (@ 0x50002D1A) RF_KMOD_ALPHA_FTDF_REG */ + __I uint16_t RESERVED; __IO uint16_t RF_SYNTH_RESULT_BLE_REG; /*!< (@ 0x50002D1E) Must be Retained */ __IO uint16_t RF_SYNTH_RESULT_FTDF_REG; /*!< (@ 0x50002D20) Must be Retained */ __IO uint16_t RF_SYNTH_RESULT2_BLE_REG; /*!< (@ 0x50002D22) Must be Retained */ @@ -1489,18 +1490,22 @@ typedef struct { /*!< (@ 0x50002D00) PLLDIG S __IO uint16_t RF_SYNTH_RESULT3_FTDF_REG; /*!< (@ 0x50002D26) RF_SYNTH_RESULT3_FTDF_REG */ __IO uint16_t RF_CALCAP1_REG; /*!< (@ 0x50002D28) RF_CALCAP1_REG */ __IO uint16_t RF_CALCAP2_REG; /*!< (@ 0x50002D2A) RF_CALCAP2_REG */ - __I uint16_t RESERVED1[2]; + __IO uint16_t RF_NMD_OFFSET_REG; /*!< (@ 0x50002D2C) Offset values for phase alignment after VCO calibration. */ + __I uint16_t RESERVED1; __IO uint16_t RF_FTDF_PHYATTR_REG; /*!< (@ 0x50002D30) RF_FTDF_PHYATTR_REG */ __IO uint16_t RF_CALTRIM_STEP1_REG; /*!< (@ 0x50002D32) RF_CALTRIM_STEP1_REG */ __IO uint16_t RF_CALTRIM_STEP2_REG; /*!< (@ 0x50002D34) RF_CALTRIM_STEP2_REG */ __IO uint16_t RF_CALTRIM_STEP3_REG; /*!< (@ 0x50002D36) RF_CALTRIM_STEP3_REG */ __IO uint16_t RF_CALTRIM_STEP4_REG; /*!< (@ 0x50002D38) RF_CALTRIM_STEP4_REG */ - __I uint16_t RESERVED2[3]; - __IO uint16_t RF_MSKMOD_CTRL1_REG; /*!< (@ 0x50002D40) MSK modulator control register */ - __IO uint16_t RF_MSKMOD_CTRL2_REG; /*!< (@ 0x50002D42) MSK modulator control register */ + __IO uint16_t RF_MGAIN_CTRL3_REG; /*!< (@ 0x50002D3A) RF_MGAIN_CTRL3_REG */ + __IO uint16_t RF_VCO_FREQ_EST_REG; /*!< (@ 0x50002D3C) RF_VCO_FREQ_EST_REG */ + __I uint16_t RESERVED2; + __IO uint16_t RF_SYNTH_SPARE_REG; /*!< (@ 0x50002D40) MSK modulator control register */ + __IO uint16_t RF_MSKMOD_CTRL1_REG; /*!< (@ 0x50002D42) MSK modulator control register */ __IO uint16_t RF_MSKMOD_CHIPL_REG; /*!< (@ 0x50002D44) MSK modulator CHIP control lower 16 bit */ __IO uint16_t RF_MSKMOD_CHIPH_REG; /*!< (@ 0x50002D46) MSK modulator CHIP control upper 16 bit */ - __I uint16_t RESERVED3[4]; + __IO uint16_t RF_TXDAC_TEST_REG; /*!< (@ 0x50002D48) Register to provide value to TXDAC */ + __I uint16_t RESERVED3[3]; __IO uint16_t RF_MGAIN_COMP_VAL0_REG; /*!< (@ 0x50002D50) RF_MGAIN_COMP_VAL0_REG */ __IO uint16_t RF_MGAIN_COMP_VAL1_REG; /*!< (@ 0x50002D52) RF_MGAIN_COMP_VAL1_REG */ __IO uint16_t RF_MGAIN_COMP_VAL2_REG; /*!< (@ 0x50002D54) RF_MGAIN_COMP_VAL2_REG */ @@ -1508,6 +1513,16 @@ typedef struct { /*!< (@ 0x50002D00) PLLDIG S __IO uint16_t RF_MGAIN_COMP_VAL4_REG; /*!< (@ 0x50002D58) RF_MGAIN_COMP_VAL4_REG */ __IO uint16_t RF_MGAIN_COMP_VAL5_REG; /*!< (@ 0x50002D5A) RF_MGAIN_COMP_VAL5_REG */ __IO uint16_t RF_MGAIN_COMP_VAL6_REG; /*!< (@ 0x50002D5C) RF_MGAIN_COMP_VAL6_REG */ + __IO uint16_t RF_MGAIN_COMP_VAL7_REG; /*!< (@ 0x50002D5E) RF_MGAIN_COMP_VAL7_REG */ + __IO uint16_t RF_PULSE_TBL_0_REG; /*!< (@ 0x50002D60) RF_PULSE_TBL_0_REG */ + __IO uint16_t RF_PULSE_TBL_1_REG; /*!< (@ 0x50002D62) RF_PULSE_TBL_1_REG */ + __IO uint16_t RF_PULSE_TBL_2_REG; /*!< (@ 0x50002D64) RF_PULSE_TBL_2_REG */ + __IO uint16_t RF_PULSE_TBL_3_REG; /*!< (@ 0x50002D66) RF_PULSE_TBL_3_REG */ + __IO uint16_t RF_PULSE_TBL_4_REG; /*!< (@ 0x50002D68) RF_PULSE_TBL_4_REG */ + __IO uint16_t RF_PULSE_TBL_5_REG; /*!< (@ 0x50002D6A) RF_PULSE_TBL_5_REG */ + __IO uint16_t RF_PULSE_TBL_6_REG; /*!< (@ 0x50002D6C) RF_PULSE_TBL_6_REG */ + __IO uint16_t RF_PULSE_TBL_7_REG; /*!< (@ 0x50002D6E) RF_PULSE_TBL_7_REG */ + __IO uint16_t RF_PULSE_CTRL_REG; /*!< (@ 0x50002D70) RF_PULSE_CTRL_REG */ } PLLDIG_Type; @@ -1579,7 +1594,8 @@ typedef struct { /*!< (@ 0x50002000) RFCU Str __IO uint16_t RF_DIAGIRQ01_REG; /*!< (@ 0x50002012) BLE/RF Diagnostic IRQ Control Register */ __IO uint16_t RF_DIAGIRQ23_REG; /*!< (@ 0x50002014) BLE/RF Diagnostic IRQ Control Register */ __IO uint16_t RF_DIAGIRQ_STAT_REG; /*!< (@ 0x50002016) BLE/RF Diagnostic IRQ Status Register */ - __I uint32_t RESERVED1[2]; + __IO uint16_t RF_AGC_EXT1_LUT_REG; /*!< (@ 0x50002018) RF_AGC_EXT1_LUT_REG */ + __I uint16_t RESERVED1[3]; __IO uint16_t RF_CALSTATE_REG; /*!< (@ 0x50002020) RF_CALSTATE_REG */ __I uint16_t RESERVED2[15]; __IO uint16_t RF_SCAN_FEEDBACK_REG; /*!< (@ 0x50002040) RF_SCAN_FEEDBACK_REG */ @@ -1619,22 +1635,25 @@ typedef struct { /*!< (@ 0x50002000) RFCU Str __IO uint16_t RF_LNA_CTRL1_REG; /*!< (@ 0x500020AC) RF_LNA_CTRL1_REG */ __IO uint16_t RF_LNA_CTRL2_REG; /*!< (@ 0x500020AE) RF_LNA_CTRL2_REG */ __IO uint16_t RF_LNA_CTRL3_REG; /*!< (@ 0x500020B0) RF_LNA_CTRL3_REG */ - __I uint16_t RESERVED7[7]; - __IO uint16_t RF_TX_PWR_REG; /*!< (@ 0x500020C0) TX Power setting */ + __IO uint16_t RF_VCO_AMP_CTRL1_REG; /*!< (@ 0x500020B2) RF_VCO_AMP_CTRL1_REG */ + __IO uint16_t RF_VCO_AMP_CTRL2_REG; /*!< (@ 0x500020B4) RF_VCO_AMP_CTRL2_REG */ + __I uint16_t RESERVED7[5]; + __IO uint16_t RF_TX_PWR_BLE_REG; /*!< (@ 0x500020C0) TX Power setting */ __IO uint16_t RF_TX_PWR_LUT_1_REG; /*!< (@ 0x500020C2) TX Power setting 1 */ __IO uint16_t RF_TX_PWR_LUT_2_REG; /*!< (@ 0x500020C4) TX Power setting 2 */ __IO uint16_t RF_TX_PWR_LUT_3_REG; /*!< (@ 0x500020C6) TX Power setting 3 */ __IO uint16_t RF_TX_PWR_LUT_4_REG; /*!< (@ 0x500020C8) TX Power setting 4 */ __IO uint16_t RF_TX_PWR_LUT_5_REG; /*!< (@ 0x500020CA) TX Power setting 5 */ - __IO uint16_t RF_TX_PWR_LUT_7_REG; /*!< (@ 0x500020CC) TX Power setting 7 */ - __IO uint16_t RF_TX_PWR_LUT_6_REG; /*!< (@ 0x500020CE) TX Power setting 6 */ - __IO uint16_t RF_TX_PWR_LUT_RD_REG; /*!< (@ 0x500020D0) TX Power read back */ - __IO uint16_t RF_DIV_IQ_RX_REG; /*!< (@ 0x500020D2) Bias trimming of IQ divider */ - __IO uint16_t RF_DIV_IQ_TX_REG; /*!< (@ 0x500020D4) Bias trimming of IQ divider */ - __I uint16_t RESERVED8; + __IO uint16_t RF_TX_PWR_LUT_6_REG; /*!< (@ 0x500020CC) TX Power setting 6 */ + __IO uint16_t RF_TX_PWR_LUT_7_REG; /*!< (@ 0x500020CE) TX Power setting 7 */ + __IO uint16_t RF_TX_PWR_FTDF_REG; /*!< (@ 0x500020D0) TX Power setting */ + __IO uint16_t RF_TX_PWR_LUT_RD_REG; /*!< (@ 0x500020D2) TX Power read back */ + __IO uint16_t RF_DIV_IQ_RX_REG; /*!< (@ 0x500020D4) Bias trimming of IQ divider */ + __IO uint16_t RF_DIV_IQ_TX_REG; /*!< (@ 0x500020D6) Bias trimming of IQ divider */ __IO uint16_t RF_LO_IQ_TRIM_REG; /*!< (@ 0x500020D8) Trim settings for IQ LO path */ __IO uint16_t RF_TXDAC_CTRL_REG; /*!< (@ 0x500020DA) Control settings for the TXDAC */ - __I uint32_t RESERVED9; + __IO uint16_t RF_TXDAC_CAL_CAP_STAT_REG; /*!< (@ 0x500020DC) Current CAL CAP value for TXDAC */ + __I uint16_t RESERVED8; __IO uint16_t RF_IFF_RESULT_REG; /*!< (@ 0x500020E0) Not retained */ __IO uint16_t RF_IFF_CC_BLE_SET1_REG; /*!< (@ 0x500020E2) Must be retained */ __IO uint16_t RF_IFF_CC_BLE_SET2_REG; /*!< (@ 0x500020E4) Must be retained */ @@ -1656,108 +1675,74 @@ typedef struct { /*!< (@ 0x50002000) RFCU Str */ typedef struct { /*!< (@ 0x50002200) RFCU_POWER Structure */ - __IO uint16_t RF_ENABLE_CONFIG0_BLE_REG; /*!< (@ 0x50002200) RF_ENABLE_CONFIG0_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG1_BLE_REG; /*!< (@ 0x50002202) RF_ENABLE_CONFIG1_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG2_BLE_REG; /*!< (@ 0x50002204) RF_ENABLE_CONFIG2_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG3_BLE_REG; /*!< (@ 0x50002206) RF_ENABLE_CONFIG3_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG4_BLE_REG; /*!< (@ 0x50002208) RF_ENABLE_CONFIG4_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG5_BLE_REG; /*!< (@ 0x5000220A) RF_ENABLE_CONFIG5_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG6_BLE_REG; /*!< (@ 0x5000220C) RF_ENABLE_CONFIG6_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG7_BLE_REG; /*!< (@ 0x5000220E) RF_ENABLE_CONFIG7_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG8_BLE_REG; /*!< (@ 0x50002210) RF_ENABLE_CONFIG8_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG9_BLE_REG; /*!< (@ 0x50002212) RF_ENABLE_CONFIG9_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG10_BLE_REG; /*!< (@ 0x50002214) RF_ENABLE_CONFIG10_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG11_BLE_REG; /*!< (@ 0x50002216) RF_ENABLE_CONFIG11_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG12_BLE_REG; /*!< (@ 0x50002218) RF_ENABLE_CONFIG12_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG13_BLE_REG; /*!< (@ 0x5000221A) RF_ENABLE_CONFIG13_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG14_BLE_REG; /*!< (@ 0x5000221C) RF_ENABLE_CONFIG14_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG15_BLE_REG; /*!< (@ 0x5000221E) RF_ENABLE_CONFIG15_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG16_BLE_REG; /*!< (@ 0x50002220) RF_ENABLE_CONFIG16_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG17_BLE_REG; /*!< (@ 0x50002222) RF_ENABLE_CONFIG17_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG18_BLE_REG; /*!< (@ 0x50002224) RF_ENABLE_CONFIG18_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG19_BLE_REG; /*!< (@ 0x50002226) RF_ENABLE_CONFIG19_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG20_BLE_REG; /*!< (@ 0x50002228) RF_ENABLE_CONFIG20_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG21_BLE_REG; /*!< (@ 0x5000222A) RF_ENABLE_CONFIG21_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG22_BLE_REG; /*!< (@ 0x5000222C) RF_ENABLE_CONFIG22_BLE_REG */ + __IO uint16_t RF_ENABLE_CONFIG0_REG; /*!< (@ 0x50002200) RF_ENABLE_CONFIG0_REG */ + __IO uint16_t RF_ENABLE_CONFIG1_REG; /*!< (@ 0x50002202) RF_ENABLE_CONFIG1_REG */ + __IO uint16_t RF_ENABLE_CONFIG2_REG; /*!< (@ 0x50002204) RF_ENABLE_CONFIG2_REG */ + __IO uint16_t RF_ENABLE_CONFIG3_REG; /*!< (@ 0x50002206) RF_ENABLE_CONFIG3_REG */ + __IO uint16_t RF_ENABLE_CONFIG4_REG; /*!< (@ 0x50002208) RF_ENABLE_CONFIG4_REG */ + __IO uint16_t RF_ENABLE_CONFIG5_REG; /*!< (@ 0x5000220A) RF_ENABLE_CONFIG5_REG */ + __IO uint16_t RF_ENABLE_CONFIG6_REG; /*!< (@ 0x5000220C) RF_ENABLE_CONFIG6_REG */ + __IO uint16_t RF_ENABLE_CONFIG7_REG; /*!< (@ 0x5000220E) RF_ENABLE_CONFIG7_REG */ + __IO uint16_t RF_ENABLE_CONFIG8_REG; /*!< (@ 0x50002210) RF_ENABLE_CONFIG8_REG */ + __IO uint16_t RF_ENABLE_CONFIG9_REG; /*!< (@ 0x50002212) RF_ENABLE_CONFIG9_REG */ + __IO uint16_t RF_ENABLE_CONFIG10_REG; /*!< (@ 0x50002214) RF_ENABLE_CONFIG10_REG */ + __IO uint16_t RF_ENABLE_CONFIG11_REG; /*!< (@ 0x50002216) RF_ENABLE_CONFIG11_REG */ + __IO uint16_t RF_ENABLE_CONFIG12_REG; /*!< (@ 0x50002218) RF_ENABLE_CONFIG12_REG */ + __IO uint16_t RF_ENABLE_CONFIG13_REG; /*!< (@ 0x5000221A) RF_ENABLE_CONFIG13_REG */ + __IO uint16_t RF_ENABLE_CONFIG14_REG; /*!< (@ 0x5000221C) RF_ENABLE_CONFIG14_REG */ + __IO uint16_t RF_ENABLE_CONFIG15_REG; /*!< (@ 0x5000221E) RF_ENABLE_CONFIG15_REG */ + __IO uint16_t RF_ENABLE_CONFIG16_REG; /*!< (@ 0x50002220) RF_ENABLE_CONFIG16_REG */ + __IO uint16_t RF_ENABLE_CONFIG17_REG; /*!< (@ 0x50002222) RF_ENABLE_CONFIG17_REG */ + __IO uint16_t RF_ENABLE_CONFIG18_REG; /*!< (@ 0x50002224) RF_ENABLE_CONFIG18_REG */ + __IO uint16_t RF_ENABLE_CONFIG19_REG; /*!< (@ 0x50002226) RF_ENABLE_CONFIG19_REG */ + __IO uint16_t RF_ENABLE_CONFIG20_REG; /*!< (@ 0x50002228) RF_ENABLE_CONFIG20_REG */ + __IO uint16_t RF_ENABLE_CONFIG21_REG; /*!< (@ 0x5000222A) RF_ENABLE_CONFIG21_REG */ + __IO uint16_t RF_ENABLE_CONFIG22_REG; /*!< (@ 0x5000222C) RF_ENABLE_CONFIG22_REG */ __IO uint16_t RF_ENABLE_CONFIG23_BLE_REG; /*!< (@ 0x5000222E) RF_ENABLE_CONFIG23_BLE_REG */ __IO uint16_t RF_ENABLE_CONFIG24_BLE_REG; /*!< (@ 0x50002230) RF_ENABLE_CONFIG24_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG25_BLE_REG; /*!< (@ 0x50002232) RF_ENABLE_CONFIG25_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG26_BLE_REG; /*!< (@ 0x50002234) RF_ENABLE_CONFIG26_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG27_BLE_REG; /*!< (@ 0x50002236) RF_ENABLE_CONFIG27_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG28_BLE_REG; /*!< (@ 0x50002238) RF_ENABLE_CONFIG28_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG29_BLE_REG; /*!< (@ 0x5000223A) RF_ENABLE_CONFIG29_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG30_BLE_REG; /*!< (@ 0x5000223C) RF_ENABLE_CONFIG30_BLE_REG */ + __IO uint16_t RF_ENABLE_CONFIG25_REG; /*!< (@ 0x50002232) RF_ENABLE_CONFIG25_REG */ + __IO uint16_t RF_ENABLE_CONFIG26_REG; /*!< (@ 0x50002234) RF_ENABLE_CONFIG26_REG */ + __IO uint16_t RF_ENABLE_CONFIG27_REG; /*!< (@ 0x50002236) RF_ENABLE_CONFIG27_REG */ + __IO uint16_t RF_ENABLE_CONFIG28_REG; /*!< (@ 0x50002238) RF_ENABLE_CONFIG28_REG */ + __IO uint16_t RF_ENABLE_CONFIG29_REG; /*!< (@ 0x5000223A) RF_ENABLE_CONFIG29_REG */ + __IO uint16_t RF_ENABLE_CONFIG30_REG; /*!< (@ 0x5000223C) RF_ENABLE_CONFIG30_REG */ __IO uint16_t RF_ENABLE_CONFIG31_BLE_REG; /*!< (@ 0x5000223E) RF_ENABLE_CONFIG31_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG32_BLE_REG; /*!< (@ 0x50002240) RF_ENABLE_CONFIG32_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG33_BLE_REG; /*!< (@ 0x50002242) RF_ENABLE_CONFIG33_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG34_BLE_REG; /*!< (@ 0x50002244) RF_ENABLE_CONFIG34_BLE_REG */ + __IO uint16_t RF_ENABLE_CONFIG32_REG; /*!< (@ 0x50002240) RF_ENABLE_CONFIG32_REG */ + __IO uint16_t RF_ENABLE_CONFIG33_REG; /*!< (@ 0x50002242) RF_ENABLE_CONFIG33_REG */ + __IO uint16_t RF_ENABLE_CONFIG34_REG; /*!< (@ 0x50002244) RF_ENABLE_CONFIG34_REG */ __IO uint16_t RF_ENABLE_CONFIG35_BLE_REG; /*!< (@ 0x50002246) RF_ENABLE_CONFIG35_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG36_BLE_REG; /*!< (@ 0x50002248) RF_ENABLE_CONFIG36_BLE_REG */ + __IO uint16_t RF_ENABLE_CONFIG36_REG; /*!< (@ 0x50002248) RF_ENABLE_CONFIG36_REG */ __IO uint16_t RF_ENABLE_CONFIG37_BLE_REG; /*!< (@ 0x5000224A) RF_ENABLE_CONFIG37_BLE_REG */ __IO uint16_t RF_ENABLE_CONFIG38_BLE_REG; /*!< (@ 0x5000224C) RF_ENABLE_CONFIG38_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG39_BLE_REG; /*!< (@ 0x5000224E) RF_ENABLE_CONFIG39_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG40_BLE_REG; /*!< (@ 0x50002250) RF_ENABLE_CONFIG40_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG41_BLE_REG; /*!< (@ 0x50002252) RF_ENABLE_CONFIG41_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG42_BLE_REG; /*!< (@ 0x50002254) RF_ENABLE_CONFIG42_BLE_REG */ - __IO uint16_t RF_ENABLE_CONFIG43_BLE_REG; /*!< (@ 0x50002256) RF_ENABLE_CONFIG43_BLE_REG */ + __IO uint16_t RF_ENABLE_CONFIG39_REG; /*!< (@ 0x5000224E) RF_ENABLE_CONFIG39_REG */ + __IO uint16_t RF_ENABLE_CONFIG40_REG; /*!< (@ 0x50002250) RF_ENABLE_CONFIG40_REG */ + __IO uint16_t RF_ENABLE_CONFIG41_REG; /*!< (@ 0x50002252) RF_ENABLE_CONFIG41_REG */ + __IO uint16_t RF_ENABLE_CONFIG42_REG; /*!< (@ 0x50002254) RF_ENABLE_CONFIG42_REG */ + __IO uint16_t RF_ENABLE_CONFIG43_REG; /*!< (@ 0x50002256) RF_ENABLE_CONFIG43_REG */ __IO uint16_t RF_ENABLE_CONFIG44_BLE_REG; /*!< (@ 0x50002258) RF_ENABLE_CONFIG44_BLE_REG */ __IO uint16_t RF_ENABLE_CONFIG45_BLE_REG; /*!< (@ 0x5000225A) RF_ENABLE_CONFIG45_BLE_REG */ __IO uint16_t RF_ENABLE_CONFIG46_BLE_REG; /*!< (@ 0x5000225C) RF_ENABLE_CONFIG46_BLE_REG */ __IO uint16_t RF_ENABLE_CONFIG47_BLE_REG; /*!< (@ 0x5000225E) RF_ENABLE_CONFIG47_BLE_REG */ __IO uint16_t RF_ENABLE_CONFIG48_BLE_REG; /*!< (@ 0x50002260) RF_ENABLE_CONFIG48_BLE_REG */ __IO uint16_t RF_ENABLE_CONFIG49_BLE_REG; /*!< (@ 0x50002262) RF_ENABLE_CONFIG49_BLE_REG */ - __I uint32_t RESERVED[7]; - __IO uint16_t RF_ENABLE_CONFIG0_FTDF_REG; /*!< (@ 0x50002280) RF_ENABLE_CONFIG0_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG1_FTDF_REG; /*!< (@ 0x50002282) RF_ENABLE_CONFIG1_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG2_FTDF_REG; /*!< (@ 0x50002284) RF_ENABLE_CONFIG2_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG3_FTDF_REG; /*!< (@ 0x50002286) RF_ENABLE_CONFIG3_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG4_FTDF_REG; /*!< (@ 0x50002288) RF_ENABLE_CONFIG4_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG5_FTDF_REG; /*!< (@ 0x5000228A) RF_ENABLE_CONFIG5_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG6_FTDF_REG; /*!< (@ 0x5000228C) RF_ENABLE_CONFIG6_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG7_FTDF_REG; /*!< (@ 0x5000228E) RF_ENABLE_CONFIG7_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG8_FTDF_REG; /*!< (@ 0x50002290) RF_ENABLE_CONFIG8_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG9_FTDF_REG; /*!< (@ 0x50002292) RF_ENABLE_CONFIG9_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG10_FTDF_REG; /*!< (@ 0x50002294) RF_ENABLE_CONFIG10_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG11_FTDF_REG; /*!< (@ 0x50002296) RF_ENABLE_CONFIG11_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG12_FTDF_REG; /*!< (@ 0x50002298) RF_ENABLE_CONFIG12_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG13_FTDF_REG; /*!< (@ 0x5000229A) RF_ENABLE_CONFIG13_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG14_FTDF_REG; /*!< (@ 0x5000229C) RF_ENABLE_CONFIG14_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG15_FTDF_REG; /*!< (@ 0x5000229E) RF_ENABLE_CONFIG15_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG16_FTDF_REG; /*!< (@ 0x500022A0) RF_ENABLE_CONFIG16_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG17_FTDF_REG; /*!< (@ 0x500022A2) RF_ENABLE_CONFIG17_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG18_FTDF_REG; /*!< (@ 0x500022A4) RF_ENABLE_CONFIG18_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG19_FTDF_REG; /*!< (@ 0x500022A6) RF_ENABLE_CONFIG19_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG20_FTDF_REG; /*!< (@ 0x500022A8) RF_ENABLE_CONFIG20_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG21_FTDF_REG; /*!< (@ 0x500022AA) RF_ENABLE_CONFIG21_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG22_FTDF_REG; /*!< (@ 0x500022AC) RF_ENABLE_CONFIG22_FTDF_REG */ + __I uint16_t RESERVED[37]; __IO uint16_t RF_ENABLE_CONFIG23_FTDF_REG; /*!< (@ 0x500022AE) RF_ENABLE_CONFIG23_FTDF_REG */ __IO uint16_t RF_ENABLE_CONFIG24_FTDF_REG; /*!< (@ 0x500022B0) RF_ENABLE_CONFIG24_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG25_FTDF_REG; /*!< (@ 0x500022B2) RF_ENABLE_CONFIG25_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG26_FTDF_REG; /*!< (@ 0x500022B4) RF_ENABLE_CONFIG26_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG27_FTDF_REG; /*!< (@ 0x500022B6) RF_ENABLE_CONFIG27_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG28_FTDF_REG; /*!< (@ 0x500022B8) RF_ENABLE_CONFIG28_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG29_FTDF_REG; /*!< (@ 0x500022BA) RF_ENABLE_CONFIG29_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG30_FTDF_REG; /*!< (@ 0x500022BC) RF_ENABLE_CONFIG30_FTDF_REG */ + __I uint16_t RESERVED1[6]; __IO uint16_t RF_ENABLE_CONFIG31_FTDF_REG; /*!< (@ 0x500022BE) RF_ENABLE_CONFIG31_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG32_FTDF_REG; /*!< (@ 0x500022C0) RF_ENABLE_CONFIG32_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG33_FTDF_REG; /*!< (@ 0x500022C2) RF_ENABLE_CONFIG33_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG34_FTDF_REG; /*!< (@ 0x500022C4) RF_ENABLE_CONFIG34_FTDF_REG */ + __I uint16_t RESERVED2[3]; __IO uint16_t RF_ENABLE_CONFIG35_FTDF_REG; /*!< (@ 0x500022C6) RF_ENABLE_CONFIG35_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG36_FTDF_REG; /*!< (@ 0x500022C8) RF_ENABLE_CONFIG36_FTDF_REG */ + __I uint16_t RESERVED3; __IO uint16_t RF_ENABLE_CONFIG37_FTDF_REG; /*!< (@ 0x500022CA) RF_ENABLE_CONFIG37_FTDF_REG */ __IO uint16_t RF_ENABLE_CONFIG38_FTDF_REG; /*!< (@ 0x500022CC) RF_ENABLE_CONFIG38_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG39_FTDF_REG; /*!< (@ 0x500022CE) RF_ENABLE_CONFIG39_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG40_FTDF_REG; /*!< (@ 0x500022D0) RF_ENABLE_CONFIG40_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG41_FTDF_REG; /*!< (@ 0x500022D2) RF_ENABLE_CONFIG41_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG42_FTDF_REG; /*!< (@ 0x500022D4) RF_ENABLE_CONFIG42_FTDF_REG */ - __IO uint16_t RF_ENABLE_CONFIG43_FTDF_REG; /*!< (@ 0x500022D6) RF_ENABLE_CONFIG43_FTDF_REG */ + __I uint16_t RESERVED4[5]; __IO uint16_t RF_ENABLE_CONFIG44_FTDF_REG; /*!< (@ 0x500022D8) RF_ENABLE_CONFIG44_FTDF_REG */ __IO uint16_t RF_ENABLE_CONFIG45_FTDF_REG; /*!< (@ 0x500022DA) RF_ENABLE_CONFIG45_FTDF_REG */ __IO uint16_t RF_ENABLE_CONFIG46_FTDF_REG; /*!< (@ 0x500022DC) RF_ENABLE_CONFIG46_FTDF_REG */ __IO uint16_t RF_ENABLE_CONFIG47_FTDF_REG; /*!< (@ 0x500022DE) RF_ENABLE_CONFIG47_FTDF_REG */ __IO uint16_t RF_ENABLE_CONFIG48_FTDF_REG; /*!< (@ 0x500022E0) RF_ENABLE_CONFIG48_FTDF_REG */ __IO uint16_t RF_ENABLE_CONFIG49_FTDF_REG; /*!< (@ 0x500022E2) RF_ENABLE_CONFIG49_FTDF_REG */ - __I uint16_t RESERVED1[15]; + __I uint16_t RESERVED5[15]; __IO uint16_t RF_CNTRL_TIMER_1_REG; /*!< (@ 0x50002302) RF_CNTRL_TIMER_1_REG */ __IO uint16_t RF_CNTRL_TIMER_2_REG; /*!< (@ 0x50002304) RF_CNTRL_TIMER_2_REG */ __IO uint16_t RF_CNTRL_TIMER_3_REG; /*!< (@ 0x50002306) RF_CNTRL_TIMER_3_REG */ @@ -1789,13 +1774,14 @@ typedef struct { /*!< (@ 0x50002200) RFCU_POW __IO uint16_t RF_CNTRL_TIMER_29_REG; /*!< (@ 0x5000233A) RF_CNTRL_TIMER_29_REG */ __IO uint16_t RF_CNTRL_TIMER_30_REG; /*!< (@ 0x5000233C) RF_CNTRL_TIMER_30_REG */ __IO uint16_t RF_CNTRL_TIMER_31_REG; /*!< (@ 0x5000233E) RF_CNTRL_TIMER_31_REG */ - __I uint32_t RESERVED2[16]; + __I uint32_t RESERVED6[16]; __IO uint16_t RF_ALWAYS_EN1_REG; /*!< (@ 0x50002380) RF_ALWAYS_EN1_REG */ __IO uint16_t RF_ALWAYS_EN2_REG; /*!< (@ 0x50002382) RF_ALWAYS_EN2_REG */ __IO uint16_t RF_ALWAYS_EN3_REG; /*!< (@ 0x50002384) RF_ALWAYS_EN3_REG */ __IO uint16_t RF_ALWAYS_EN4_REG; /*!< (@ 0x50002386) RF_ALWAYS_EN4_REG */ - __IO uint16_t RF_PORT_EN_REG; /*!< (@ 0x50002388) RF_PORT_EN_REG */ - __IO uint16_t RF_PORT_POL_REG; /*!< (@ 0x5000238A) RF_PORT_POL_REG */ + __IO uint16_t RF_PORT_EN_BLE_REG; /*!< (@ 0x50002388) RF_PORT_EN_BLE_REG */ + __IO uint16_t RF_PORT_EN_FTDF_REG; /*!< (@ 0x5000238A) RF_PORT_EN_FTDF_REG */ + __IO uint16_t RF_PORT_POL_REG; /*!< (@ 0x5000238C) RF_PORT_POL_REG */ } RFCU_POWER_Type; @@ -1878,10 +1864,14 @@ typedef struct { /*!< (@ 0x50000200) TIMER1 S __IO uint16_t CAPTIM_CAPTURE_GPIO1_REG; /*!< (@ 0x50000210) Capture Timer value for event on GPIO1 */ __IO uint16_t CAPTIM_CAPTURE_GPIO2_REG; /*!< (@ 0x50000212) Capture Timer value for event on GPIO2 */ __IO uint16_t CAPTIM_PRESCALER_VAL_REG; /*!< (@ 0x50000214) Capture Timer interrupt status register */ - __IO uint16_t CAPTIM_PWM_FREQ_REG; /*!< (@ 0x50000216) Capture Timer pwm frequency register. PWM5 period - is defined by the reference clock frequency multiplied by this - value. */ + __IO uint16_t CAPTIM_PWM_FREQ_REG; /*!< (@ 0x50000216) Capture Timer pwm frequency register */ __IO uint16_t CAPTIM_PWM_DC_REG; /*!< (@ 0x50000218) Capture Timer pwm dc register */ + __IO uint16_t CAPTIM_TIMER_HVAL_REG; /*!< (@ 0x5000021A) Capture Timer counter high value */ + __IO uint16_t CAPTIM_RELOAD_HIGH_REG; /*!< (@ 0x5000021C) Capture Timer reload high value and Delay in + shot mode */ + __IO uint16_t CAPTIM_CAPTURE_HIGH_GPIO1_REG; /*!< (@ 0x5000021E) Capture Timer high value for event on GPIO01 */ + __IO uint16_t CAPTIM_CAPTURE_HIGH_GPIO2_REG; /*!< (@ 0x50000220) Capture Timer high value for event on GPIO02 */ + __IO uint16_t CAPTIM_SHOTWIDTH_HIGH_REG; /*!< (@ 0x50000222) Capture Timer Shot high duration in shot mode */ } TIMER1_Type; @@ -2123,10 +2113,9 @@ typedef struct { /*!< (@ 0x50001800) USB Stru typedef struct { /*!< (@ 0x50000100) WAKEUP Structure */ __IO uint16_t WKUP_CTRL_REG; /*!< (@ 0x50000100) Control register for the wakeup counter */ - __IO uint16_t WKUP_COMPARE_REG; /*!< (@ 0x50000102) Number of events before wakeup interrupt */ + __I uint16_t RESERVED; __IO uint16_t WKUP_RESET_IRQ_REG; /*!< (@ 0x50000104) Reset wakeup interrupt */ - __IO uint16_t WKUP_COUNTER_REG; /*!< (@ 0x50000106) Actual number of events of the wakeup counter */ - __IO uint16_t WKUP_RESET_CNTR_REG; /*!< (@ 0x50000108) Reset the event counter */ + __I uint16_t RESERVED1[2]; __IO uint16_t WKUP_SELECT_P0_REG; /*!< (@ 0x5000010A) select which inputs from P0 port can trigger wkup counter */ __IO uint16_t WKUP_SELECT_P1_REG; /*!< (@ 0x5000010C) select which inputs from P1 port can trigger @@ -2142,6 +2131,22 @@ typedef struct { /*!< (@ 0x50000100) WAKEUP S __IO uint16_t WKUP_POL_P2_REG; /*!< (@ 0x50000118) select the sesitivity polarity for each P2 input */ __IO uint16_t WKUP_POL_P3_REG; /*!< (@ 0x5000011A) select the sesitivity polarity for each P3 input */ __IO uint16_t WKUP_POL_P4_REG; /*!< (@ 0x5000011C) select the sesitivity polarity for each P3 input */ + __IO uint16_t WKUP_STATUS_0_REG; /*!< (@ 0x5000011E) Event status register for P0 and P1 */ + __IO uint16_t WKUP_STATUS_1_REG; /*!< (@ 0x50000120) Event status register for P2 */ + __IO uint16_t WKUP_STATUS_2_REG; /*!< (@ 0x50000122) Event status register for P3 and P4 */ + __IO uint16_t WKUP_CLEAR_0_REG; /*!< (@ 0x50000124) Clear event register for P0 and P1 */ + __IO uint16_t WKUP_CLEAR_1_REG; /*!< (@ 0x50000126) Clear event register for P2 */ + __IO uint16_t WKUP_CLEAR_2_REG; /*!< (@ 0x50000128) Clear event register for P3 and P4 */ + __IO uint16_t WKUP_SEL_GPIO_P0_REG; /*!< (@ 0x5000012A) select which inputs from P0 port can trigger + interrupt */ + __IO uint16_t WKUP_SEL_GPIO_P1_REG; /*!< (@ 0x5000012C) select which inputs from P1 port can trigger + interrupt */ + __IO uint16_t WKUP_SEL_GPIO_P2_REG; /*!< (@ 0x5000012E) select which inputs from P2 port can trigger + interrupt */ + __IO uint16_t WKUP_SEL_GPIO_P3_REG; /*!< (@ 0x50000130) select which inputs from P3 port can trigger + interrupt */ + __IO uint16_t WKUP_SEL_GPIO_P4_REG; /*!< (@ 0x50000132) select which inputs from P3 port can trigger + interrupt */ } WAKEUP_Type; @@ -2811,6 +2816,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define APU_SRC1_CTRL_REG_SRC_OUT_US_Msk (0x30000UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_US (Bitfield-Mask: 0x03) */ #define APU_SRC1_CTRL_REG_SRC_OUT_OK_Pos (18UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_OK (Bit 18) */ #define APU_SRC1_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_OK (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_RESYNC_Pos (19UL) /*!< APU SRC1_CTRL_REG: SRC_RESYNC (Bit 19) */ +#define APU_SRC1_CTRL_REG_SRC_RESYNC_Msk (0x80000UL) /*!< APU SRC1_CTRL_REG: SRC_RESYNC (Bitfield-Mask: 0x01) */ #define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL) /*!< APU SRC1_CTRL_REG: SRC_IN_OVFLOW (Bit 20) */ #define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL) /*!< APU SRC1_CTRL_REG: SRC_IN_OVFLOW (Bitfield-Mask: 0x01) */ #define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL) /*!< APU SRC1_CTRL_REG: SRC_IN_UNFLOW (Bit 21) */ @@ -2823,8 +2830,12 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL) /*!< APU SRC1_CTRL_REG: SRC_IN_FLOWCLR (Bitfield-Mask: 0x01) */ #define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_FLOWCLR (Bit 25) */ #define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL) /*!< APU SRC1_CTRL_REG: SRC_OUT_FLOWCLR (Bitfield-Mask: 0x01) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos (26UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_DI_DEL (Bit 26) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk (0xc000000UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_DI_DEL (Bitfield-Mask: 0x03) */ #define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Pos (28UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_MODE (Bit 28) */ #define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_MODE (Bitfield-Mask: 0x03) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos (30UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_DO_DEL (Bit 30) */ +#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk (0xc0000000UL) /*!< APU SRC1_CTRL_REG: SRC_PDM_DO_DEL (Bitfield-Mask: 0x03) */ /* ----------------------------- APU_SRC1_IN_FS_REG ----------------------------- */ #define APU_SRC1_IN_FS_REG_SRC_IN_FS_Pos (0UL) /*!< APU SRC1_IN_FS_REG: SRC_IN_FS (Bit 0) */ @@ -3244,6 +3255,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define BLE_BLE_SWPROFILING_REG_SWPROFVAL_Pos (0UL) /*!< BLE BLE_SWPROFILING_REG: SWPROFVAL (Bit 0) */ #define BLE_BLE_SWPROFILING_REG_SWPROFVAL_Msk (0xffffffffUL) /*!< BLE BLE_SWPROFILING_REG: SWPROFVAL (Bitfield-Mask: 0xffffffff) */ +/* --------------------------- BLE_BLE_RADIOCNTL0_REG --------------------------- */ +#define BLE_BLE_RADIOCNTL0_REG_field246rsv_Pos (2UL) /*!< BLE BLE_RADIOCNTL0_REG: field246rsv (Bit 2) */ +#define BLE_BLE_RADIOCNTL0_REG_field246rsv_Msk (0x1cUL) /*!< BLE BLE_RADIOCNTL0_REG: field246rsv (Bitfield-Mask: 0x07) */ + /* --------------------------- BLE_BLE_RADIOCNTL1_REG --------------------------- */ #define BLE_BLE_RADIOCNTL1_REG_XRFSEL_Pos (16UL) /*!< BLE BLE_RADIOCNTL1_REG: XRFSEL (Bit 16) */ #define BLE_BLE_RADIOCNTL1_REG_XRFSEL_Msk (0x1f0000UL) /*!< BLE BLE_RADIOCNTL1_REG: XRFSEL (Bitfield-Mask: 0x1f) */ @@ -3412,12 +3427,6 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Pos (28UL) /*!< BLE BLE_BLEMPRIO1_REG: BLEMDEFAULT (Bit 28) */ #define BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Msk (0xf0000000UL) /*!< BLE BLE_BLEMPRIO1_REG: BLEMDEFAULT (Bitfield-Mask: 0x0f) */ -/* -------------------------- BLE_BLE_BLEPRIOSCHARB_REG ------------------------- */ -#define BLE_BLE_BLEPRIOSCHARB_REG_BLEMARGIN_Pos (0UL) /*!< BLE BLE_BLEPRIOSCHARB_REG: BLEMARGIN (Bit 0) */ -#define BLE_BLE_BLEPRIOSCHARB_REG_BLEMARGIN_Msk (0xffUL) /*!< BLE BLE_BLEPRIOSCHARB_REG: BLEMARGIN (Bitfield-Mask: 0xff) */ -#define BLE_BLE_BLEPRIOSCHARB_REG_BLEPRIOMODE_Pos (15UL) /*!< BLE BLE_BLEPRIOSCHARB_REG: BLEPRIOMODE (Bit 15) */ -#define BLE_BLE_BLEPRIOSCHARB_REG_BLEPRIOMODE_Msk (0x8000UL) /*!< BLE BLE_BLEPRIOSCHARB_REG: BLEPRIOMODE (Bitfield-Mask: 0x01) */ - /* ------------------------------ BLE_BLE_CNTL2_REG ----------------------------- */ #define BLE_BLE_CNTL2_REG_EMACCERRSTAT_Pos (0UL) /*!< BLE BLE_CNTL2_REG: EMACCERRSTAT (Bit 0) */ #define BLE_BLE_CNTL2_REG_EMACCERRSTAT_Msk (0x1UL) /*!< BLE BLE_CNTL2_REG: EMACCERRSTAT (Bitfield-Mask: 0x01) */ @@ -3425,6 +3434,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define BLE_BLE_CNTL2_REG_EMACCERRACK_Msk (0x2UL) /*!< BLE BLE_CNTL2_REG: EMACCERRACK (Bitfield-Mask: 0x01) */ #define BLE_BLE_CNTL2_REG_EMACCERRMSK_Pos (2UL) /*!< BLE BLE_CNTL2_REG: EMACCERRMSK (Bit 2) */ #define BLE_BLE_CNTL2_REG_EMACCERRMSK_Msk (0x4UL) /*!< BLE BLE_CNTL2_REG: EMACCERRMSK (Bitfield-Mask: 0x01) */ +#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Pos (3UL) /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR (Bit 3) */ +#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Msk (0x8UL) /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR (Bitfield-Mask: 0x01) */ +#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Pos (4UL) /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR_SEL (Bit 4) */ +#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Msk (0x30UL) /*!< BLE BLE_CNTL2_REG: BLE_DIAG_OVR_SEL (Bitfield-Mask: 0x03) */ #define BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Pos (6UL) /*!< BLE BLE_CNTL2_REG: BLE_CLK_STAT (Bit 6) */ #define BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Msk (0x40UL) /*!< BLE BLE_CNTL2_REG: BLE_CLK_STAT (Bitfield-Mask: 0x01) */ #define BLE_BLE_CNTL2_REG_MON_LP_CLK_Pos (7UL) /*!< BLE BLE_CNTL2_REG: MON_LP_CLK (Bit 7) */ @@ -3433,12 +3446,22 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Msk (0x100UL) /*!< BLE BLE_CNTL2_REG: RADIO_PWRDN_ALLOW (Bitfield-Mask: 0x01) */ #define BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Pos (9UL) /*!< BLE BLE_CNTL2_REG: BLE_CLK_SEL (Bit 9) */ #define BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Msk (0x7e00UL) /*!< BLE BLE_CNTL2_REG: BLE_CLK_SEL (Bitfield-Mask: 0x3f) */ +#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Pos (15UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_SRC (Bit 15) */ +#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Msk (0x8000UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_SRC (Bitfield-Mask: 0x01) */ +#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Pos (16UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_MODE (Bit 16) */ +#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Msk (0x10000UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_MODE (Bitfield-Mask: 0x01) */ +#define BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Pos (17UL) /*!< BLE BLE_CNTL2_REG: BLE_PTI_SOURCE_SEL (Bit 17) */ +#define BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Msk (0x20000UL) /*!< BLE BLE_CNTL2_REG: BLE_PTI_SOURCE_SEL (Bitfield-Mask: 0x01) */ +#define BLE_BLE_CNTL2_REG_BB_ONLY_Pos (18UL) /*!< BLE BLE_CNTL2_REG: BB_ONLY (Bit 18) */ +#define BLE_BLE_CNTL2_REG_BB_ONLY_Msk (0x40000UL) /*!< BLE BLE_CNTL2_REG: BB_ONLY (Bitfield-Mask: 0x01) */ #define BLE_BLE_CNTL2_REG_SW_RPL_SPI_Pos (19UL) /*!< BLE BLE_CNTL2_REG: SW_RPL_SPI (Bit 19) */ #define BLE_BLE_CNTL2_REG_SW_RPL_SPI_Msk (0x80000UL) /*!< BLE BLE_CNTL2_REG: SW_RPL_SPI (Bitfield-Mask: 0x01) */ #define BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Pos (20UL) /*!< BLE BLE_CNTL2_REG: WAKEUPLPSTAT (Bit 20) */ #define BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Msk (0x100000UL) /*!< BLE BLE_CNTL2_REG: WAKEUPLPSTAT (Bitfield-Mask: 0x01) */ #define BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Pos (21UL) /*!< BLE BLE_CNTL2_REG: BLE_RSSI_SEL (Bit 21) */ #define BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Msk (0x200000UL) /*!< BLE BLE_CNTL2_REG: BLE_RSSI_SEL (Bitfield-Mask: 0x01) */ +#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Pos (22UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_START (Bit 22) */ +#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Msk (0xffc00000UL) /*!< BLE BLE_CNTL2_REG: BLE_TRANSACTION_START (Bitfield-Mask: 0x3ff) */ /* ----------------------------- BLE_BLE_EM_BASE_REG ---------------------------- */ #define BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Pos (10UL) /*!< BLE BLE_EM_BASE_REG: BLE_EM_BASE_16_10 (Bit 10) */ @@ -3615,6 +3638,12 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* ----------------------------- COEX_COEX_CTRL_REG ----------------------------- */ #define COEX_COEX_CTRL_REG_PRGING_ARBITER_Pos (0UL) /*!< COEX COEX_CTRL_REG: PRGING_ARBITER (Bit 0) */ #define COEX_COEX_CTRL_REG_PRGING_ARBITER_Msk (0x1UL) /*!< COEX COEX_CTRL_REG: PRGING_ARBITER (Bitfield-Mask: 0x01) */ +#define COEX_COEX_CTRL_REG_DECISION_SW_ALL_Pos (1UL) /*!< COEX COEX_CTRL_REG: DECISION_SW_ALL (Bit 1) */ +#define COEX_COEX_CTRL_REG_DECISION_SW_ALL_Msk (0x2UL) /*!< COEX COEX_CTRL_REG: DECISION_SW_ALL (Bitfield-Mask: 0x01) */ +#define COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Pos (2UL) /*!< COEX COEX_CTRL_REG: TXRX_MON_FTDF_ALL (Bit 2) */ +#define COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Msk (0x4UL) /*!< COEX COEX_CTRL_REG: TXRX_MON_FTDF_ALL (Bitfield-Mask: 0x01) */ +#define COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Pos (3UL) /*!< COEX COEX_CTRL_REG: TXRX_MON_BLE_ALL (Bit 3) */ +#define COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Msk (0x8UL) /*!< COEX COEX_CTRL_REG: TXRX_MON_BLE_ALL (Bitfield-Mask: 0x01) */ #define COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Pos (4UL) /*!< COEX COEX_CTRL_REG: SMART_ACT_IMPL (Bit 4) */ #define COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Msk (0x10UL) /*!< COEX COEX_CTRL_REG: SMART_ACT_IMPL (Bitfield-Mask: 0x01) */ #define COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Pos (5UL) /*!< COEX COEX_CTRL_REG: SEL_COEX_DIAG (Bit 5) */ @@ -3623,6 +3652,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Msk (0x80UL) /*!< COEX COEX_CTRL_REG: SEL_FTDF_CCA (Bitfield-Mask: 0x01) */ #define COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Pos (8UL) /*!< COEX COEX_CTRL_REG: SEL_FTDF_PTI (Bit 8) */ #define COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Msk (0x100UL) /*!< COEX COEX_CTRL_REG: SEL_FTDF_PTI (Bitfield-Mask: 0x01) */ +#define COEX_COEX_CTRL_REG_SEL_BLE_PTI_Pos (9UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_PTI (Bit 9) */ +#define COEX_COEX_CTRL_REG_SEL_BLE_PTI_Msk (0x200UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_PTI (Bitfield-Mask: 0x01) */ #define COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Pos (10UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_WLAN_TX_RX (Bit 10) */ #define COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Msk (0x400UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_WLAN_TX_RX (Bitfield-Mask: 0x01) */ #define COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Pos (11UL) /*!< COEX COEX_CTRL_REG: SEL_BLE_RADIO_BUSY (Bit 11) */ @@ -3636,11 +3667,11 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* ----------------------------- COEX_COEX_STAT_REG ----------------------------- */ #define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Pos (0UL) /*!< COEX COEX_STAT_REG: COEX_DECISION_PTR (Bit 0) */ -#define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Msk (0x1fUL) /*!< COEX COEX_STAT_REG: COEX_DECISION_PTR (Bitfield-Mask: 0x1f) */ +#define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Msk (0xfUL) /*!< COEX COEX_STAT_REG: COEX_DECISION_PTR (Bitfield-Mask: 0x0f) */ #define COEX_COEX_STAT_REG_COEX_DECISION_Pos (5UL) /*!< COEX COEX_STAT_REG: COEX_DECISION (Bit 5) */ #define COEX_COEX_STAT_REG_COEX_DECISION_Msk (0x60UL) /*!< COEX COEX_STAT_REG: COEX_DECISION (Bitfield-Mask: 0x03) */ -#define COEX_COEX_STAT_REG_COEX_DECISION_CLOSING_Pos (7UL) /*!< COEX COEX_STAT_REG: COEX_DECISION_CLOSING (Bit 7) */ -#define COEX_COEX_STAT_REG_COEX_DECISION_CLOSING_Msk (0x80UL) /*!< COEX COEX_STAT_REG: COEX_DECISION_CLOSING (Bitfield-Mask: 0x01) */ +#define COEX_COEX_STAT_REG_COEX_CLOSING_Pos (7UL) /*!< COEX COEX_STAT_REG: COEX_CLOSING (Bit 7) */ +#define COEX_COEX_STAT_REG_COEX_CLOSING_Msk (0x80UL) /*!< COEX COEX_STAT_REG: COEX_CLOSING (Bitfield-Mask: 0x01) */ #define COEX_COEX_STAT_REG_SMART_ACT_Pos (8UL) /*!< COEX COEX_STAT_REG: SMART_ACT (Bit 8) */ #define COEX_COEX_STAT_REG_SMART_ACT_Msk (0x100UL) /*!< COEX COEX_STAT_REG: SMART_ACT (Bitfield-Mask: 0x01) */ #define COEX_COEX_STAT_REG_SMART_PRI_Pos (9UL) /*!< COEX COEX_STAT_REG: SMART_PRI (Bit 9) */ @@ -3658,73 +3689,47 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Pos (15UL) /*!< COEX COEX_STAT_REG: IGNORE_BLE_STAT (Bit 15) */ #define COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Msk (0x8000UL) /*!< COEX COEX_STAT_REG: IGNORE_BLE_STAT (Bitfield-Mask: 0x01) */ +/* ----------------------------- COEX_COEX_STAT2_REG ---------------------------- */ +#define COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Pos (0UL) /*!< COEX COEX_STAT2_REG: COEX_DECISION_WITH_CLOSING (Bit 0) */ +#define COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Msk (0x7UL) /*!< COEX COEX_STAT2_REG: COEX_DECISION_WITH_CLOSING (Bitfield-Mask: 0x07) */ +#define COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Pos (3UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_ACTIVE (Bit 3) */ +#define COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Msk (0x8UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_ACTIVE (Bitfield-Mask: 0x01) */ +#define COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Pos (4UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_RX_EN (Bit 4) */ +#define COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Msk (0x10UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_RX_EN (Bitfield-Mask: 0x01) */ +#define COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Pos (5UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_TX_EN (Bit 5) */ +#define COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Msk (0x20UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_TX_EN (Bitfield-Mask: 0x01) */ +#define COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Pos (6UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_PTI_INT (Bit 6) */ +#define COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Msk (0x1c0UL) /*!< COEX COEX_STAT2_REG: COEX_FTDF_PTI_INT (Bitfield-Mask: 0x07) */ +#define COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Pos (9UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_ACTIVE (Bit 9) */ +#define COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Msk (0x200UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_ACTIVE (Bitfield-Mask: 0x01) */ +#define COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Pos (10UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_RX_EN (Bit 10) */ +#define COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Msk (0x400UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_RX_EN (Bitfield-Mask: 0x01) */ +#define COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Pos (11UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_TX_EN (Bit 11) */ +#define COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Msk (0x800UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_TX_EN (Bitfield-Mask: 0x01) */ +#define COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Pos (12UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_PTI_INT (Bit 12) */ +#define COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Msk (0x7000UL) /*!< COEX COEX_STAT2_REG: COEX_BLE_PTI_INT (Bitfield-Mask: 0x07) */ +#define COEX_COEX_STAT2_REG_COEX_EXT_ACT_Pos (15UL) /*!< COEX COEX_STAT2_REG: COEX_EXT_ACT (Bit 15) */ +#define COEX_COEX_STAT2_REG_COEX_EXT_ACT_Msk (0x8000UL) /*!< COEX COEX_STAT2_REG: COEX_EXT_ACT (Bitfield-Mask: 0x01) */ + /* --------------------------- COEX_COEX_INT_MASK_REG --------------------------- */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_MASK_Pos (0UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_MASK (Bit 0) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_MASK_Msk (0x1UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_MASK (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_SMART_ACT_R_Pos (1UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_SMART_ACT_R (Bit 1) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_SMART_ACT_R_Msk (0x2UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_SMART_ACT_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_SMART_ACT_F_Pos (2UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_SMART_ACT_F (Bit 2) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_SMART_ACT_F_Msk (0x4UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_SMART_ACT_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_SMART_PRI_R_Pos (3UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_SMART_PRI_R (Bit 3) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_SMART_PRI_R_Msk (0x8UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_SMART_PRI_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_SMART_PRI_F_Pos (4UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_SMART_PRI_F (Bit 4) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_SMART_PRI_F_Msk (0x10UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_SMART_PRI_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_EXT_ACT_R_Pos (5UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_EXT_ACT_R (Bit 5) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_EXT_ACT_R_Msk (0x20UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_EXT_ACT_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_EXT_ACT_F_Pos (6UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_EXT_ACT_F (Bit 6) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_EXT_ACT_F_Msk (0x40UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_EXT_ACT_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_FTDF_ACTIVE_R_Pos (7UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_FTDF_ACTIVE_R (Bit 7) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_FTDF_ACTIVE_R_Msk (0x80UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_FTDF_ACTIVE_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_FTDF_ACTIVE_F_Pos (8UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_FTDF_ACTIVE_F (Bit 8) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_FTDF_ACTIVE_F_Msk (0x100UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_FTDF_ACTIVE_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_BLE_ACTIVE_R_Pos (9UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_BLE_ACTIVE_R (Bit 9) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_BLE_ACTIVE_R_Msk (0x200UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_BLE_ACTIVE_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_BLE_ACTIVE_F_Pos (10UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_BLE_ACTIVE_F (Bit 10) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_BLE_ACTIVE_F_Msk (0x400UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_BLE_ACTIVE_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_RADIO_BUSY_R_Pos (11UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_RADIO_BUSY_R (Bit 11) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_RADIO_BUSY_R_Msk (0x800UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_RADIO_BUSY_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_RADIO_BUSY_F_Pos (12UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_RADIO_BUSY_F (Bit 12) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_RADIO_BUSY_F_Msk (0x1000UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_RADIO_BUSY_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_CLOSING_BRK_Pos (13UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_CLOSING_BRK (Bit 13) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_CLOSING_BRK_Msk (0x2000UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_CLOSING_BRK (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_START_MID_Pos (14UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_START_MID (Bit 14) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_START_MID_Msk (0x4000UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_START_MID (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_DECISION_SW_Pos (15UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_DECISION_SW (Bit 15) */ -#define COEX_COEX_INT_MASK_REG_COEX_IRQ_ON_DECISION_SW_Msk (0x8000UL) /*!< COEX COEX_INT_MASK_REG: COEX_IRQ_ON_DECISION_SW (Bitfield-Mask: 0x01) */ +#define COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Pos (8UL) /*!< COEX COEX_INT_MASK_REG: IRQ_TXRX_MON (Bit 8) */ +#define COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Msk (0x100UL) /*!< COEX COEX_INT_MASK_REG: IRQ_TXRX_MON (Bitfield-Mask: 0x01) */ +#define COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Pos (9UL) /*!< COEX COEX_INT_MASK_REG: IRQ_DECISION_SW (Bit 9) */ +#define COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Msk (0x200UL) /*!< COEX COEX_INT_MASK_REG: IRQ_DECISION_SW (Bitfield-Mask: 0x01) */ /* --------------------------- COEX_COEX_INT_STAT_REG --------------------------- */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_STAT_Pos (0UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_STAT (Bit 0) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_STAT_Msk (0x1UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_STAT (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_SMART_ACT_R_Pos (1UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_SMART_ACT_R (Bit 1) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_SMART_ACT_R_Msk (0x2UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_SMART_ACT_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_SMART_ACT_F_Pos (2UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_SMART_ACT_F (Bit 2) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_SMART_ACT_F_Msk (0x4UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_SMART_ACT_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_SMART_PRI_R_Pos (3UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_SMART_PRI_R (Bit 3) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_SMART_PRI_R_Msk (0x8UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_SMART_PRI_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_SMART_PRI_F_Pos (4UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_SMART_PRI_F (Bit 4) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_SMART_PRI_F_Msk (0x10UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_SMART_PRI_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_EXT_ACT_R_Pos (5UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_EXT_ACT_R (Bit 5) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_EXT_ACT_R_Msk (0x20UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_EXT_ACT_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_EXT_ACT_F_Pos (6UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_EXT_ACT_F (Bit 6) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_EXT_ACT_F_Msk (0x40UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_EXT_ACT_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_FTDF_ACTIVE_R_Pos (7UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_FTDF_ACTIVE_R (Bit 7) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_FTDF_ACTIVE_R_Msk (0x80UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_FTDF_ACTIVE_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_FTDF_ACTIVE_F_Pos (8UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_FTDF_ACTIVE_F (Bit 8) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_FTDF_ACTIVE_F_Msk (0x100UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_FTDF_ACTIVE_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_BLE_ACTIVE_R_Pos (9UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_BLE_ACTIVE_R (Bit 9) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_BLE_ACTIVE_R_Msk (0x200UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_BLE_ACTIVE_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_BLE_ACTIVE_F_Pos (10UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_BLE_ACTIVE_F (Bit 10) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_BLE_ACTIVE_F_Msk (0x400UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_BLE_ACTIVE_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_RADIO_BUSY_R_Pos (11UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_RADIO_BUSY_R (Bit 11) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_RADIO_BUSY_R_Msk (0x800UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_RADIO_BUSY_R (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_RADIO_BUSY_F_Pos (12UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_RADIO_BUSY_F (Bit 12) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_RADIO_BUSY_F_Msk (0x1000UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_RADIO_BUSY_F (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_CLOSING_BRK_Pos (13UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_CLOSING_BRK (Bit 13) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_CLOSING_BRK_Msk (0x2000UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_CLOSING_BRK (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_START_MID_Pos (14UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_START_MID (Bit 14) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_START_MID_Msk (0x4000UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_START_MID (Bitfield-Mask: 0x01) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_DECISION_SW_Pos (15UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_DECISION_SW (Bit 15) */ -#define COEX_COEX_INT_STAT_REG_COEX_IRQ_ON_DECISION_SW_Msk (0x8000UL) /*!< COEX COEX_INT_STAT_REG: COEX_IRQ_ON_DECISION_SW (Bitfield-Mask: 0x01) */ +#define COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Pos (0UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PTR (Bit 0) */ +#define COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Msk (0xfUL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PTR (Bitfield-Mask: 0x0f) */ +#define COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Pos (5UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_TX (Bit 5) */ +#define COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Msk (0x20UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_TX (Bitfield-Mask: 0x01) */ +#define COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Pos (6UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PASSED (Bit 6) */ +#define COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Msk (0x40UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_PASSED (Bitfield-Mask: 0x01) */ +#define COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Pos (7UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_OVWR (Bit 7) */ +#define COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Msk (0x80UL) /*!< COEX COEX_INT_STAT_REG: TXRX_MON_OVWR (Bitfield-Mask: 0x01) */ +#define COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Pos (8UL) /*!< COEX COEX_INT_STAT_REG: IRQ_TXRX_MON (Bit 8) */ +#define COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Msk (0x100UL) /*!< COEX COEX_INT_STAT_REG: IRQ_TXRX_MON (Bitfield-Mask: 0x01) */ +#define COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Pos (9UL) /*!< COEX COEX_INT_STAT_REG: IRQ_DECISION_SW (Bit 9) */ +#define COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Msk (0x200UL) /*!< COEX COEX_INT_STAT_REG: IRQ_DECISION_SW (Bitfield-Mask: 0x01) */ /* ---------------------------- COEX_COEX_BLE_PTI_REG --------------------------- */ #define COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Pos (0UL) /*!< COEX COEX_BLE_PTI_REG: COEX_BLE_PTI (Bit 0) */ @@ -3734,10 +3739,6 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Pos (0UL) /*!< COEX COEX_FTDF_PTI_REG: COEX_FTDF_PTI (Bit 0) */ #define COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Msk (0x7UL) /*!< COEX COEX_FTDF_PTI_REG: COEX_FTDF_PTI (Bitfield-Mask: 0x07) */ -/* ----------------------------- COEX_COEX_DIAG_REG ----------------------------- */ -#define COEX_COEX_DIAG_REG_COEX_DIAG_MON_Pos (0UL) /*!< COEX COEX_DIAG_REG: COEX_DIAG_MON (Bit 0) */ -#define COEX_COEX_DIAG_REG_COEX_DIAG_MON_Msk (0xffffUL) /*!< COEX COEX_DIAG_REG: COEX_DIAG_MON (Bitfield-Mask: 0xffff) */ - /* ----------------------------- COEX_COEX_PRI1_REG ----------------------------- */ #define COEX_COEX_PRI1_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI1_REG: COEX_PRI_PTI (Bit 0) */ #define COEX_COEX_PRI1_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI1_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ @@ -3828,18 +3829,6 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define COEX_COEX_PRI15_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI15_REG: COEX_PRI_MAC (Bit 3) */ #define COEX_COEX_PRI15_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI15_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ -/* ----------------------------- COEX_COEX_PRI16_REG ---------------------------- */ -#define COEX_COEX_PRI16_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI16_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI16_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI16_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI16_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI16_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI16_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI16_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - -/* ----------------------------- COEX_COEX_PRI17_REG ---------------------------- */ -#define COEX_COEX_PRI17_REG_COEX_PRI_PTI_Pos (0UL) /*!< COEX COEX_PRI17_REG: COEX_PRI_PTI (Bit 0) */ -#define COEX_COEX_PRI17_REG_COEX_PRI_PTI_Msk (0x7UL) /*!< COEX COEX_PRI17_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07) */ -#define COEX_COEX_PRI17_REG_COEX_PRI_MAC_Pos (3UL) /*!< COEX COEX_PRI17_REG: COEX_PRI_MAC (Bit 3) */ -#define COEX_COEX_PRI17_REG_COEX_PRI_MAC_Msk (0x18UL) /*!< COEX COEX_PRI17_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03) */ - /* ================================================================================ */ /* ================ struct 'CRG_PER' Position & Mask ================ */ @@ -3969,6 +3958,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Msk (0x80UL) /*!< CRG_TOP CLK_CTRL_REG: DIVN_SYNC_LEVEL (Bitfield-Mask: 0x01) */ #define CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Pos (8UL) /*!< CRG_TOP CLK_CTRL_REG: CLK32K_SOURCE (Bit 8) */ #define CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Msk (0x300UL) /*!< CRG_TOP CLK_CTRL_REG: CLK32K_SOURCE (Bitfield-Mask: 0x03) */ +#define CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Pos (10UL) /*!< CRG_TOP CLK_CTRL_REG: DIVN_SHIFT_SEL (Bit 10) */ +#define CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Msk (0x400UL) /*!< CRG_TOP CLK_CTRL_REG: DIVN_SHIFT_SEL (Bitfield-Mask: 0x01) */ #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Pos (12UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_32K (Bit 12) */ #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Msk (0x1000UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_32K (Bitfield-Mask: 0x01) */ #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Pos (13UL) /*!< CRG_TOP CLK_CTRL_REG: RUNNING_AT_RC16M (Bit 13) */ @@ -4013,6 +4004,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Msk (0x4UL) /*!< CRG_TOP PMU_CTRL_REG: BLE_SLEEP (Bitfield-Mask: 0x01) */ #define CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos (3UL) /*!< CRG_TOP PMU_CTRL_REG: FTDF_SLEEP (Bit 3) */ #define CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Msk (0x8UL) /*!< CRG_TOP PMU_CTRL_REG: FTDF_SLEEP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos (4UL) /*!< CRG_TOP PMU_CTRL_REG: MAP_BANDGAP_EN (Bit 4) */ +#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk (0x10UL) /*!< CRG_TOP PMU_CTRL_REG: MAP_BANDGAP_EN (Bitfield-Mask: 0x01) */ #define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos (5UL) /*!< CRG_TOP PMU_CTRL_REG: RESET_ON_WAKEUP (Bit 5) */ #define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk (0x20UL) /*!< CRG_TOP PMU_CTRL_REG: RESET_ON_WAKEUP (Bitfield-Mask: 0x01) */ #define CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Pos (6UL) /*!< CRG_TOP PMU_CTRL_REG: OTP_COPY_DIV (Bit 6) */ @@ -4063,10 +4056,14 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk (0x4UL) /*!< CRG_TOP SYS_STAT_REG: PER_IS_DOWN (Bitfield-Mask: 0x01) */ #define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos (3UL) /*!< CRG_TOP SYS_STAT_REG: PER_IS_UP (Bit 3) */ #define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk (0x8UL) /*!< CRG_TOP SYS_STAT_REG: PER_IS_UP (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Pos (4UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_SW2 (Bit 4) */ +#define CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Msk (0x10UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_SW2 (Bitfield-Mask: 0x01) */ #define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos (5UL) /*!< CRG_TOP SYS_STAT_REG: DBG_IS_ACTIVE (Bit 5) */ #define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk (0x20UL) /*!< CRG_TOP SYS_STAT_REG: DBG_IS_ACTIVE (Bitfield-Mask: 0x01) */ #define CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Pos (6UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_TRIM_READY (Bit 6) */ #define CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Msk (0x40UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_TRIM_READY (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Pos (7UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_SETTLE_READY (Bit 7) */ +#define CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Msk (0x80UL) /*!< CRG_TOP SYS_STAT_REG: XTAL16_SETTLE_READY (Bitfield-Mask: 0x01) */ #define CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Pos (8UL) /*!< CRG_TOP SYS_STAT_REG: BLE_IS_DOWN (Bit 8) */ #define CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Msk (0x100UL) /*!< CRG_TOP SYS_STAT_REG: BLE_IS_DOWN (Bitfield-Mask: 0x01) */ #define CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Pos (9UL) /*!< CRG_TOP SYS_STAT_REG: BLE_IS_UP (Bit 9) */ @@ -4081,10 +4078,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Msk (0x3fUL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_COUNT_N (Bitfield-Mask: 0x3f) */ #define CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Pos (6UL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_TRIM_SELECT (Bit 6) */ #define CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Msk (0xc0UL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_TRIM_SELECT (Bitfield-Mask: 0x03) */ - -/* ---------------------------- CRG_TOP_DIVN_SYNC_REG --------------------------- */ -#define CRG_TOP_DIVN_SYNC_REG_DIVN_SYNC_Pos (0UL) /*!< CRG_TOP DIVN_SYNC_REG: DIVN_SYNC (Bit 0) */ -#define CRG_TOP_DIVN_SYNC_REG_DIVN_SYNC_Msk (0x1UL) /*!< CRG_TOP DIVN_SYNC_REG: DIVN_SYNC (Bitfield-Mask: 0x01) */ +#define CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Pos (8UL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_SETTLE_N (Bit 8) */ +#define CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Msk (0x3f00UL) /*!< CRG_TOP TRIM_CTRL_REG: XTAL_SETTLE_N (Bitfield-Mask: 0x3f) */ /* ----------------------------- CRG_TOP_CLK_32K_REG ---------------------------- */ #define CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Pos (0UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_ENABLE (Bit 0) */ @@ -4099,6 +4094,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_CLK_32K_REG_RC32K_TRIM_Msk (0xf00UL) /*!< CRG_TOP CLK_32K_REG: RC32K_TRIM (Bitfield-Mask: 0x0f) */ #define CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Pos (12UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_DISABLE_AMPREG (Bit 12) */ #define CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Msk (0x1000UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_DISABLE_AMPREG (Bitfield-Mask: 0x01) */ +#define CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Pos (13UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_XTAL1_BIAS_DISABLE (Bit 13) */ +#define CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Msk (0x2000UL) /*!< CRG_TOP CLK_32K_REG: XTAL32K_XTAL1_BIAS_DISABLE (Bitfield-Mask: 0x01) */ /* ----------------------------- CRG_TOP_CLK_16M_REG ---------------------------- */ #define CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Pos (0UL) /*!< CRG_TOP CLK_16M_REG: RC16M_ENABLE (Bit 0) */ @@ -4139,8 +4136,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk (0x3e0UL) /*!< CRG_TOP BANDGAP_REG: BGR_ITRIM (Bitfield-Mask: 0x1f) */ #define CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Pos (10UL) /*!< CRG_TOP BANDGAP_REG: LDO_SLEEP_TRIM (Bit 10) */ #define CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Msk (0x3c00UL) /*!< CRG_TOP BANDGAP_REG: LDO_SLEEP_TRIM (Bitfield-Mask: 0x0f) */ -#define CRG_TOP_BANDGAP_REG_BYPASS_COLD_BOOT_DISABLE_Pos (14UL) /*!< CRG_TOP BANDGAP_REG: BYPASS_COLD_BOOT_DISABLE (Bit 14) */ -#define CRG_TOP_BANDGAP_REG_BYPASS_COLD_BOOT_DISABLE_Msk (0x4000UL) /*!< CRG_TOP BANDGAP_REG: BYPASS_COLD_BOOT_DISABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Pos (14UL) /*!< CRG_TOP BANDGAP_REG: LDO_SUPPLY_USE_BGREF (Bit 14) */ +#define CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Msk (0x4000UL) /*!< CRG_TOP BANDGAP_REG: LDO_SUPPLY_USE_BGREF (Bitfield-Mask: 0x01) */ /* --------------------------- CRG_TOP_ANA_STATUS_REG --------------------------- */ #define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Pos (0UL) /*!< CRG_TOP ANA_STATUS_REG: LDO_RADIO_OK (Bit 0) */ @@ -4179,8 +4176,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* ------------------------- CRG_TOP_STARTUP_STATUS_REG ------------------------- */ #define CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Pos (0UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_BANDGAP_OK (Bit 0) */ #define CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Msk (0x1UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_BANDGAP_OK (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_VBUS_AVAILABLE_Pos (1UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_VBUS_AVAILABLE (Bit 1) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_VBUS_AVAILABLE_Msk (0x2UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_VBUS_AVAILABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Pos (1UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_NEWBAT (Bit 1) */ +#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Msk (0x2UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_NEWBAT (Bitfield-Mask: 0x01) */ #define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Pos (2UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_SUPPLY_VBAT_OK (Bit 2) */ #define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Msk (0x4UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_SUPPLY_VBAT_OK (Bitfield-Mask: 0x01) */ #define CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Pos (3UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LOD_SUPPLY_USB_OK (Bit 3) */ @@ -4201,10 +4198,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Msk (0x400UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_PA_HIGH (Bitfield-Mask: 0x01) */ #define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Pos (11UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_FLASH_HIGH (Bit 11) */ #define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Msk (0x800UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_FLASH_HIGH (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Pos (12UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_NEWBAT (Bit 12) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Msk (0x1000UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_NEWBAT (Bitfield-Mask: 0x01) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Pos (13UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_FLASH_OK (Bit 13) */ -#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Msk (0x2000UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_FLASH_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Pos (12UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_FLASH_OK (Bit 12) */ +#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Msk (0x1000UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_FLASH_OK (Bitfield-Mask: 0x01) */ +#define CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Pos (13UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_BOD_STATUS (Bit 13) */ +#define CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Msk (0xe000UL) /*!< CRG_TOP STARTUP_STATUS_REG: SU_BOD_STATUS (Bitfield-Mask: 0x07) */ /* -------------------------- CRG_TOP_VBUS_IRQ_MASK_REG ------------------------- */ #define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Pos (0UL) /*!< CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_FALL (Bit 0) */ @@ -4219,10 +4216,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* ---------------------------- CRG_TOP_BOD_CTRL_REG ---------------------------- */ #define CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Pos (0UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_TRIM (Bit 0) */ #define CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Msk (0x3UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_TRIM (Bitfield-Mask: 0x03) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_FLASH_TRIM_Pos (2UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V8_FLASH_TRIM (Bit 2) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_FLASH_TRIM_Msk (0xcUL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V8_FLASH_TRIM (Bitfield-Mask: 0x03) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_PA_TRIM_Pos (4UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V8_PA_TRIM (Bit 4) */ -#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_PA_TRIM_Msk (0x30UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V8_PA_TRIM (Bitfield-Mask: 0x03) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Pos (2UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V8_TRIM (Bit 2) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Msk (0xcUL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V8_TRIM (Bitfield-Mask: 0x03) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Pos (4UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V4_TRIM (Bit 4) */ +#define CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Msk (0x30UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_1V4_TRIM (Bitfield-Mask: 0x03) */ #define CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Pos (6UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_V33_TRIM (Bit 6) */ #define CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Msk (0xc0UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_V33_TRIM (Bitfield-Mask: 0x03) */ #define CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Pos (8UL) /*!< CRG_TOP BOD_CTRL_REG: BOD_VDD_LVL (Bit 8) */ @@ -4241,6 +4238,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Msk (0x10UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_1V8_FLASH_EN (Bitfield-Mask: 0x01) */ #define CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Pos (5UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_VBAT_EN (Bit 5) */ #define CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Msk (0x20UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_VBAT_EN (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Pos (6UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_V14_EN (Bit 6) */ +#define CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Msk (0x40UL) /*!< CRG_TOP BOD_CTRL2_REG: BOD_V14_EN (Bitfield-Mask: 0x01) */ /* --------------------------- CRG_TOP_BOD_STATUS_REG --------------------------- */ #define CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Pos (0UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_VDD_LOW (Bit 0) */ @@ -4253,6 +4252,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Msk (0x8UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_V33_LOW (Bitfield-Mask: 0x01) */ #define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Pos (4UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_VBAT_LOW (Bit 4) */ #define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Msk (0x10UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_VBAT_LOW (Bitfield-Mask: 0x01) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Pos (5UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_V14_LOW (Bit 5) */ +#define CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Msk (0x20UL) /*!< CRG_TOP BOD_STATUS_REG: BOD_V14_LOW (Bitfield-Mask: 0x01) */ /* ---------------------------- CRG_TOP_LDO_CTRL1_REG --------------------------- */ #define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Pos (0UL) /*!< CRG_TOP LDO_CTRL1_REG: LDO_CORE_CURLIM (Bit 0) */ @@ -4294,6 +4295,18 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Pos (0UL) /*!< CRG_TOP POWER_CTRL_REG: TRIM_NEWBAT (Bit 0) */ #define CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Msk (0x7UL) /*!< CRG_TOP POWER_CTRL_REG: TRIM_NEWBAT (Bitfield-Mask: 0x07) */ +/* -------------------------- CRG_TOP_POR_VBAT_CTRL_REG ------------------------- */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Pos (0UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_LOW (Bit 0) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Msk (0xfUL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_LOW (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Pos (4UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_HIGH (Bit 4) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Msk (0xf0UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_HIGH (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Pos (8UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_HYST_LOW (Bit 8) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Msk (0xf00UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_HYST_LOW (Bitfield-Mask: 0x0f) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Pos (12UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_ENABLE (Bit 12) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Msk (0x1000UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Pos (13UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_MASK_N (Bit 13) */ +#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Msk (0x2000UL) /*!< CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_MASK_N (Bitfield-Mask: 0x01) */ + /* -------------------------- CRG_TOP_XTALRDY_CTRL_REG -------------------------- */ #define CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Pos (0UL) /*!< CRG_TOP XTALRDY_CTRL_REG: XTALRDY_CNT (Bit 0) */ #define CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk (0xffUL) /*!< CRG_TOP XTALRDY_CTRL_REG: XTALRDY_CNT (Bitfield-Mask: 0xff) */ @@ -4302,6 +4315,48 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Pos (0UL) /*!< CRG_TOP XTALRDY_STAT_REG: XTALRDY_STAT (Bit 0) */ #define CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Msk (0xffUL) /*!< CRG_TOP XTALRDY_STAT_REG: XTALRDY_STAT (Bitfield-Mask: 0xff) */ +/* ---------------------------- CRG_TOP_LDO_CTRL3_REG --------------------------- */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Pos (0UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_ENABLE (Bit 0) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Msk (0x1UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Pos (1UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_VREF_HOLD (Bit 1) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Msk (0x2UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_VREF_HOLD (Bitfield-Mask: 0x01) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Pos (2UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_ENABLE (Bit 2) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Msk (0x4UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Pos (3UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_VREF_HOLD (Bit 3) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Msk (0x8UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_VREF_HOLD (Bitfield-Mask: 0x01) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Pos (4UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_ENABLE (Bit 4) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Msk (0x10UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_ENABLE (Bitfield-Mask: 0x01) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Pos (5UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bit 5) */ +#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Msk (0x20UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bitfield-Mask: 0x01) */ + +/* -------------------------- CRG_TOP_XTAL16M_START_REG ------------------------- */ +#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Pos (0UL) /*!< CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bit 0) */ +#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Msk (0xffUL) /*!< CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bitfield-Mask: 0xff) */ +#define CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Pos (8UL) /*!< CRG_TOP XTAL16M_START_REG: COARSE_ADJ (Bit 8) */ +#define CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Msk (0x700UL) /*!< CRG_TOP XTAL16M_START_REG: COARSE_ADJ (Bitfield-Mask: 0x07) */ + +/* -------------------------- CRG_TOP_XTAL16M_RAMP_REG -------------------------- */ +#define CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Pos (0UL) /*!< CRG_TOP XTAL16M_RAMP_REG: FINE_ADJ (Bit 0) */ +#define CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Msk (0xffUL) /*!< CRG_TOP XTAL16M_RAMP_REG: FINE_ADJ (Bitfield-Mask: 0xff) */ +#define CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Pos (8UL) /*!< CRG_TOP XTAL16M_RAMP_REG: COARSE_ADJ (Bit 8) */ +#define CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Msk (0x700UL) /*!< CRG_TOP XTAL16M_RAMP_REG: COARSE_ADJ (Bitfield-Mask: 0x07) */ + +/* ------------------------- CRG_TOP_XTAL16M_TRSTAT_REG ------------------------- */ +#define CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Pos (0UL) /*!< CRG_TOP XTAL16M_TRSTAT_REG: XTAL16M_TRSTAT (Bit 0) */ +#define CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Msk (0x7fffUL) /*!< CRG_TOP XTAL16M_TRSTAT_REG: XTAL16M_TRSTAT (Bitfield-Mask: 0x7fff) */ + +/* --------------------------- CRG_TOP_RESET_STAT_REG --------------------------- */ +#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos (0UL) /*!< CRG_TOP RESET_STAT_REG: PORESET_STAT (Bit 0) */ +#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk (0x1UL) /*!< CRG_TOP RESET_STAT_REG: PORESET_STAT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos (1UL) /*!< CRG_TOP RESET_STAT_REG: HWRESET_STAT (Bit 1) */ +#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk (0x2UL) /*!< CRG_TOP RESET_STAT_REG: HWRESET_STAT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos (2UL) /*!< CRG_TOP RESET_STAT_REG: SWRESET_STAT (Bit 2) */ +#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk (0x4UL) /*!< CRG_TOP RESET_STAT_REG: SWRESET_STAT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos (3UL) /*!< CRG_TOP RESET_STAT_REG: WDOGRESET_STAT (Bit 3) */ +#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk (0x8UL) /*!< CRG_TOP RESET_STAT_REG: WDOGRESET_STAT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos (4UL) /*!< CRG_TOP RESET_STAT_REG: SWD_HWRESET_STAT (Bit 4) */ +#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk (0x10UL) /*!< CRG_TOP RESET_STAT_REG: SWD_HWRESET_STAT (Bitfield-Mask: 0x01) */ + /* --------------------------- CRG_TOP_FORCE_SLEEP_REG -------------------------- */ #define CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Pos (0UL) /*!< CRG_TOP FORCE_SLEEP_REG: FORCE_FTDF_SLEEP (Bit 0) */ #define CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Msk (0x1UL) /*!< CRG_TOP FORCE_SLEEP_REG: FORCE_FTDF_SLEEP (Bitfield-Mask: 0x01) */ @@ -4322,6 +4377,28 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Pos (3UL) /*!< CRG_TOP AON_SPARE_REG: EN_BUSSYS_RET (Bit 3) */ #define CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Msk (0x8UL) /*!< CRG_TOP AON_SPARE_REG: EN_BUSSYS_RET (Bitfield-Mask: 0x01) */ +/* --------------------------- CRG_TOP_SECURE_BOOT_REG -------------------------- */ +#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos (0UL) /*!< CRG_TOP SECURE_BOOT_REG: SECURE_BOOT (Bit 0) */ +#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk (0x1UL) /*!< CRG_TOP SECURE_BOOT_REG: SECURE_BOOT (Bitfield-Mask: 0x01) */ +#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Pos (1UL) /*!< CRG_TOP SECURE_BOOT_REG: FORCE_DEBUGGER_OFF (Bit 1) */ +#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Msk (0x2UL) /*!< CRG_TOP SECURE_BOOT_REG: FORCE_DEBUGGER_OFF (Bitfield-Mask: 0x01) */ + +/* ------------------------- CRG_TOP_PMU_RESET_RAIL_REG ------------------------- */ +#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Pos (0UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V14 (Bit 0) */ +#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Msk (0x1UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V14 (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Pos (1UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18 (Bit 1) */ +#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Msk (0x2UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18 (Bitfield-Mask: 0x01) */ +#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Pos (2UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18P (Bit 2) */ +#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Msk (0x4UL) /*!< CRG_TOP PMU_RESET_RAIL_REG: RESET_V18P (Bitfield-Mask: 0x01) */ + +/* ------------------------- CRG_TOP_DISCHARGE_RAIL_REG ------------------------- */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Pos (0UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V14 (Bit 0) */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Msk (0x1UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V14 (Bitfield-Mask: 0x01) */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Pos (1UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18 (Bit 1) */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Msk (0x2UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18 (Bitfield-Mask: 0x01) */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Pos (2UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18P (Bit 2) */ +#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Msk (0x4UL) /*!< CRG_TOP DISCHARGE_RAIL_REG: RESET_V18P (Bitfield-Mask: 0x01) */ + /* ================================================================================ */ /* ================ struct 'DCDC' Position & Mask ================ */ @@ -4583,6 +4660,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Msk (0x3e0UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_V18P (Bitfield-Mask: 0x1f) */ #define DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Pos (10UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_LV_MODE (Bit 10) */ #define DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Msk (0x400UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_LV_MODE (Bitfield-Mask: 0x01) */ +#define DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Pos (11UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_STARTUP_COMPLETE (Bit 11) */ +#define DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Msk (0x800UL) /*!< DCDC DCDC_STATUS_3_REG: DCDC_STARTUP_COMPLETE (Bitfield-Mask: 0x01) */ /* --------------------------- DCDC_DCDC_STATUS_4_REG --------------------------- */ #define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Pos (0UL) /*!< DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V14 (Bit 0) */ @@ -4669,6 +4748,12 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Msk (0x80UL) /*!< DEM RF_DEM_CTRL_REG: BLE_DDC_EN (Bitfield-Mask: 0x01) */ #define DEM_RF_DEM_CTRL_REG_IQCORR_EN_Pos (8UL) /*!< DEM RF_DEM_CTRL_REG: IQCORR_EN (Bit 8) */ #define DEM_RF_DEM_CTRL_REG_IQCORR_EN_Msk (0x100UL) /*!< DEM RF_DEM_CTRL_REG: IQCORR_EN (Bitfield-Mask: 0x01) */ +#define DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Pos (9UL) /*!< DEM RF_DEM_CTRL_REG: CFE_DOUBLE_EN (Bit 9) */ +#define DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Msk (0x200UL) /*!< DEM RF_DEM_CTRL_REG: CFE_DOUBLE_EN (Bitfield-Mask: 0x01) */ +#define DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Pos (10UL) /*!< DEM RF_DEM_CTRL_REG: CFE_MEDIAN_EN (Bit 10) */ +#define DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Msk (0x400UL) /*!< DEM RF_DEM_CTRL_REG: CFE_MEDIAN_EN (Bitfield-Mask: 0x01) */ +#define DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Pos (11UL) /*!< DEM RF_DEM_CTRL_REG: CFE_PPOLE (Bit 11) */ +#define DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Msk (0x3800UL) /*!< DEM RF_DEM_CTRL_REG: CFE_PPOLE (Bitfield-Mask: 0x07) */ /* ---------------------------- DEM_RF_AGC_LUT_01_REG --------------------------- */ #define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Pos (0UL) /*!< DEM RF_AGC_LUT_01_REG: VGA2_GAIN0 (Bit 0) */ @@ -4767,6 +4852,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DEM_RF_AFC_CTRL_REG_POLE1_Msk (0x30UL) /*!< DEM RF_AFC_CTRL_REG: POLE1 (Bitfield-Mask: 0x03) */ #define DEM_RF_AFC_CTRL_REG_POLE2_Pos (6UL) /*!< DEM RF_AFC_CTRL_REG: POLE2 (Bit 6) */ #define DEM_RF_AFC_CTRL_REG_POLE2_Msk (0xc0UL) /*!< DEM RF_AFC_CTRL_REG: POLE2 (Bitfield-Mask: 0x03) */ +#define DEM_RF_AFC_CTRL_REG_PAD_MODE_Pos (8UL) /*!< DEM RF_AFC_CTRL_REG: PAD_MODE (Bit 8) */ +#define DEM_RF_AFC_CTRL_REG_PAD_MODE_Msk (0x300UL) /*!< DEM RF_AFC_CTRL_REG: PAD_MODE (Bitfield-Mask: 0x03) */ +#define DEM_RF_AFC_CTRL_REG_APD_MODE_Pos (10UL) /*!< DEM RF_AFC_CTRL_REG: APD_MODE (Bit 10) */ +#define DEM_RF_AFC_CTRL_REG_APD_MODE_Msk (0x1c00UL) /*!< DEM RF_AFC_CTRL_REG: APD_MODE (Bitfield-Mask: 0x07) */ /* ------------------------- DEM_RF_DC_OFFSET_CTRL1_REG ------------------------- */ #define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Pos (0UL) /*!< DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_I_WR (Bit 0) */ @@ -4787,6 +4876,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Msk (0x180UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCNGAIN (Bitfield-Mask: 0x03) */ #define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Pos (9UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_INIT (Bit 9) */ #define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Msk (0x200UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_INIT (Bitfield-Mask: 0x01) */ +#define DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Pos (10UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCVGA1SCALE_EN (Bit 10) */ +#define DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Msk (0x400UL) /*!< DEM RF_DC_OFFSET_CTRL2_REG: DCVGA1SCALE_EN (Bitfield-Mask: 0x01) */ /* ------------------------- DEM_RF_DC_OFFSET_CTRL3_REG ------------------------- */ #define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Pos (0UL) /*!< DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_I (Bit 0) */ @@ -4922,7 +5013,7 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* --------------------------- DEM_RF_DEM_TESTMODE_REG -------------------------- */ #define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Pos (0UL) /*!< DEM RF_DEM_TESTMODE_REG: DEM_TESTMODE (Bit 0) */ -#define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Msk (0xffUL) /*!< DEM RF_DEM_TESTMODE_REG: DEM_TESTMODE (Bitfield-Mask: 0xff) */ +#define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Msk (0x3ffUL) /*!< DEM RF_DEM_TESTMODE_REG: DEM_TESTMODE (Bitfield-Mask: 0x3ff) */ /* -------------------------- DEM_RF_DEM_IQCORRECT_REG -------------------------- */ #define DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Pos (0UL) /*!< DEM RF_DEM_IQCORRECT_REG: IQCORR_BETA (Bit 0) */ @@ -4956,6 +5047,26 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Pos (0UL) /*!< DEM RF_FSSS_MAG_RESULT_REG: FSSS_MAG_RD (Bit 0) */ #define DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Msk (0xffffUL) /*!< DEM RF_FSSS_MAG_RESULT_REG: FSSS_MAG_RD (Bitfield-Mask: 0xffff) */ +/* ---------------------------- DEM_RF_CCA_RSSITH_REG --------------------------- */ +#define DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Pos (0UL) /*!< DEM RF_CCA_RSSITH_REG: CCA_RSSITH (Bit 0) */ +#define DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Msk (0x1fffUL) /*!< DEM RF_CCA_RSSITH_REG: CCA_RSSITH (Bitfield-Mask: 0x1fff) */ +#define DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Pos (13UL) /*!< DEM RF_CCA_RSSITH_REG: SIGDET_TIMEOUT_LEN (Bit 13) */ +#define DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Msk (0xe000UL) /*!< DEM RF_CCA_RSSITH_REG: SIGDET_TIMEOUT_LEN (Bitfield-Mask: 0x07) */ + +/* ------------------------- DEM_RF_FTDF_SIGDET_CTRL_REG ------------------------ */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Pos (0UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_MODE (Bit 0) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Msk (0x3UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_MODE (Bitfield-Mask: 0x03) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Pos (2UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_THRESHOLD (Bit 2) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Msk (0xfcUL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_THRESHOLD (Bitfield-Mask: 0x3f) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Pos (8UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DIFF (Bit 8) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Msk (0x100UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DIFF (Bitfield-Mask: 0x01) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Pos (9UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR2 (Bit 9) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Msk (0x600UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR2 (Bitfield-Mask: 0x03) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Pos (11UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR1 (Bit 11) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Msk (0x1800UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR1 (Bitfield-Mask: 0x03) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Pos (13UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DELAY (Bit 13) */ +#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Msk (0x6000UL) /*!< DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DELAY (Bitfield-Mask: 0x03) */ + /* ================================================================================ */ /* ================ struct 'DMA' Position & Mask ================ */ @@ -5007,6 +5118,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA0_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ #define DMA_DMA0_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA0_CTRL_REG: DMA_INIT (Bit 12) */ #define DMA_DMA0_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA0_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA0_CTRL_REG: REQ_SENSE (Bit 13) */ +#define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA0_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ /* ------------------------------ DMA_DMA0_IDX_REG ------------------------------ */ #define DMA_DMA0_IDX_REG_DMA0_IDX_Pos (0UL) /*!< DMA DMA0_IDX_REG: DMA0_IDX (Bit 0) */ @@ -5057,6 +5170,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA1_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ #define DMA_DMA1_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA1_CTRL_REG: DMA_INIT (Bit 12) */ #define DMA_DMA1_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA1_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA1_CTRL_REG: REQ_SENSE (Bit 13) */ +#define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA1_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ /* ------------------------------ DMA_DMA1_IDX_REG ------------------------------ */ #define DMA_DMA1_IDX_REG_DMA1_IDX_Pos (0UL) /*!< DMA DMA1_IDX_REG: DMA1_IDX (Bit 0) */ @@ -5107,6 +5222,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA2_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ #define DMA_DMA2_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA2_CTRL_REG: DMA_INIT (Bit 12) */ #define DMA_DMA2_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA2_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA2_CTRL_REG: REQ_SENSE (Bit 13) */ +#define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA2_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ /* ------------------------------ DMA_DMA2_IDX_REG ------------------------------ */ #define DMA_DMA2_IDX_REG_DMA2_IDX_Pos (0UL) /*!< DMA DMA2_IDX_REG: DMA2_IDX (Bit 0) */ @@ -5157,6 +5274,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA3_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ #define DMA_DMA3_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA3_CTRL_REG: DMA_INIT (Bit 12) */ #define DMA_DMA3_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA3_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA3_CTRL_REG: REQ_SENSE (Bit 13) */ +#define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA3_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ /* ------------------------------ DMA_DMA3_IDX_REG ------------------------------ */ #define DMA_DMA3_IDX_REG_DMA3_IDX_Pos (0UL) /*!< DMA DMA3_IDX_REG: DMA3_IDX (Bit 0) */ @@ -5207,6 +5326,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA4_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ #define DMA_DMA4_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA4_CTRL_REG: DMA_INIT (Bit 12) */ #define DMA_DMA4_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA4_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA4_CTRL_REG: REQ_SENSE (Bit 13) */ +#define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA4_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ /* ------------------------------ DMA_DMA4_IDX_REG ------------------------------ */ #define DMA_DMA4_IDX_REG_DMA4_IDX_Pos (0UL) /*!< DMA DMA4_IDX_REG: DMA4_IDX (Bit 0) */ @@ -5257,6 +5378,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA5_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ #define DMA_DMA5_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA5_CTRL_REG: DMA_INIT (Bit 12) */ #define DMA_DMA5_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA5_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA5_CTRL_REG: REQ_SENSE (Bit 13) */ +#define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA5_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ /* ------------------------------ DMA_DMA5_IDX_REG ------------------------------ */ #define DMA_DMA5_IDX_REG_DMA5_IDX_Pos (0UL) /*!< DMA DMA5_IDX_REG: DMA5_IDX (Bit 0) */ @@ -5307,6 +5430,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DMA_DMA6_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA6_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ #define DMA_DMA6_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA6_CTRL_REG: DMA_INIT (Bit 12) */ #define DMA_DMA6_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA6_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA6_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA6_CTRL_REG: REQ_SENSE (Bit 13) */ +#define DMA_DMA6_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA6_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ /* ------------------------------ DMA_DMA6_IDX_REG ------------------------------ */ #define DMA_DMA6_IDX_REG_DMA6_IDX_Pos (0UL) /*!< DMA DMA6_IDX_REG: DMA6_IDX (Bit 0) */ @@ -5357,6 +5482,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define DMA_DMA7_CTRL_REG_DMA_IDLE_Msk (0x800UL) /*!< DMA DMA7_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01) */ #define DMA_DMA7_CTRL_REG_DMA_INIT_Pos (12UL) /*!< DMA DMA7_CTRL_REG: DMA_INIT (Bit 12) */ #define DMA_DMA7_CTRL_REG_DMA_INIT_Msk (0x1000UL) /*!< DMA DMA7_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01) */ +#define DMA_DMA7_CTRL_REG_REQ_SENSE_Pos (13UL) /*!< DMA DMA7_CTRL_REG: REQ_SENSE (Bit 13) */ +#define DMA_DMA7_CTRL_REG_REQ_SENSE_Msk (0x2000UL) /*!< DMA DMA7_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01) */ /* ------------------------------ DMA_DMA7_IDX_REG ------------------------------ */ #define DMA_DMA7_IDX_REG_DMA7_IDX_Pos (0UL) /*!< DMA DMA7_IDX_REG: DMA7_IDX (Bit 0) */ @@ -5468,12 +5595,6 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define ECC_ECC_VERSION_REG_ECC_HVN_Pos (8UL) /*!< ECC ECC_VERSION_REG: ECC_HVN (Bit 8) */ #define ECC_ECC_VERSION_REG_ECC_HVN_Msk (0xff00UL) /*!< ECC ECC_VERSION_REG: ECC_HVN (Bitfield-Mask: 0xff) */ -/* -------------------------- ECC_ECC_LOADMICROCODE_REG ------------------------- */ -#define ECC_ECC_LOADMICROCODE_REG_ECC_uCode_Pos (0UL) /*!< ECC ECC_LOADMICROCODE_REG: ECC_uCode (Bit 0) */ -#define ECC_ECC_LOADMICROCODE_REG_ECC_uCode_Msk (0x3ffffUL) /*!< ECC ECC_LOADMICROCODE_REG: ECC_uCode (Bitfield-Mask: 0x3ffff) */ -#define ECC_ECC_LOADMICROCODE_REG_ECC_FirstWord_Pos (18UL) /*!< ECC ECC_LOADMICROCODE_REG: ECC_FirstWord (Bit 18) */ -#define ECC_ECC_LOADMICROCODE_REG_ECC_FirstWord_Msk (0x40000UL) /*!< ECC ECC_LOADMICROCODE_REG: ECC_FirstWord (Bitfield-Mask: 0x01) */ - /* ================================================================================ */ /* ================ struct 'FTDF' Position & Mask ================ */ @@ -5921,8 +6042,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Msk (0x1fffffeUL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXONDURATION (Bitfield-Mask: 0xffffff) */ #define FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Pos (25UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXALWAYSON (Bit 25) */ #define FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Msk (0x2000000UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: RXALWAYSON (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_Pos (27UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: PTI (Bit 27) */ -#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_Msk (0x78000000UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: PTI (Bitfield-Mask: 0x0f) */ +#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Pos (27UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: PTI_RX (Bit 27) */ +#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Msk (0x78000000UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: PTI_RX (Bitfield-Mask: 0x0f) */ #define FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Pos (31UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: KEEP_PHY_EN (Bit 31) */ #define FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Msk (0x80000000UL) /*!< FTDF FTDF_LMAC_CONTROL_0_REG: KEEP_PHY_EN (Bitfield-Mask: 0x01) */ @@ -5961,6 +6082,14 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Msk (0xffffUL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: MACMAXFRAMETOTALWAITTIME (Bitfield-Mask: 0xffff) */ #define FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: CCAIDLEWAIT (Bit 16) */ #define FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Msk (0xff0000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: CCAIDLEWAIT (Bitfield-Mask: 0xff) */ +#define FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Pos (24UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: ADDR_TAB_MATCH_FP_VALUE (Bit 24) */ +#define FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Msk (0x1000000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: ADDR_TAB_MATCH_FP_VALUE (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Pos (25UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_OVERRIDE (Bit 25) */ +#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Msk (0x2000000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_OVERRIDE (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Pos (26UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_FORCE_VALUE (Bit 26) */ +#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Msk (0x4000000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FP_FORCE_VALUE (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Pos (27UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FTDF_LPDP_ENABLE (Bit 27) */ +#define FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Msk (0x8000000UL) /*!< FTDF FTDF_LMAC_CONTROL_3_REG: FTDF_LPDP_ENABLE (Bitfield-Mask: 0x01) */ /* ------------------------ FTDF_FTDF_LMAC_CONTROL_OS_REG ----------------------- */ #define FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Pos (0UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: GETGENERATORVAL (Bit 0) */ @@ -5969,6 +6098,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Msk (0x2UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: RXENABLE (Bitfield-Mask: 0x01) */ #define FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Pos (2UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: SINGLECCA (Bit 2) */ #define FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Msk (0x4UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: SINGLECCA (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Pos (3UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_SET (Bit 3) */ +#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Msk (0x8UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_SET (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Pos (4UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_CLEAR (Bit 4) */ +#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Msk (0x10UL) /*!< FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_CLEAR (Bitfield-Mask: 0x01) */ /* ---------------------- FTDF_FTDF_LMAC_CONTROL_STATUS_REG --------------------- */ #define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Pos (1UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: LMACREADY4SLEEP (Bit 1) */ @@ -5979,10 +6112,16 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Msk (0x40UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: WAKEUPTIMERENABLESTATUS (Bitfield-Mask: 0x01) */ #define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Pos (8UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: EDSCANVALUE (Bit 8) */ #define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Msk (0xff00UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: EDSCANVALUE (Bitfield-Mask: 0xff) */ +#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_NB_STAT (Bit 16) */ +#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Msk (0x70000UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_NB_STAT (Bitfield-Mask: 0x07) */ +#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Pos (19UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_RESUME_STAT (Bit 19) */ +#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Msk (0x80000UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_RESUME_STAT (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Pos (24UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_BO_STAT (Bit 24) */ +#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Msk (0xff000000UL) /*!< FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_BO_STAT (Bitfield-Mask: 0xff) */ /* ------------------------- FTDF_FTDF_EVENTCURRVAL_REG ------------------------- */ #define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Pos (0UL) /*!< FTDF FTDF_EVENTCURRVAL_REG: EVENTCURRVAL (Bit 0) */ -#define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Msk (0xffffffffUL) /*!< FTDF FTDF_EVENTCURRVAL_REG: EVENTCURRVAL (Bitfield-Mask: 0xffffffff) */ +#define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Msk (0x1ffffffUL) /*!< FTDF FTDF_EVENTCURRVAL_REG: EVENTCURRVAL (Bitfield-Mask: 0x1ffffff) */ /* ----------------------- FTDF_FTDF_TIMESTAMPCURRVAL_REG ----------------------- */ #define FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Pos (0UL) /*!< FTDF FTDF_TIMESTAMPCURRVAL_REG: TIMESTAMPCURRVAL (Bit 0) */ @@ -6033,6 +6172,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Msk (0xffffUL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACRXTOTALCYCLETIME (Bitfield-Mask: 0xffff) */ #define FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Pos (16UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACDISCARXOFFTORZ (Bit 16) */ #define FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Msk (0x10000UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: MACDISCARXOFFTORZ (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Pos (17UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_NB_VAL (Bit 17) */ +#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Msk (0xe0000UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_NB_VAL (Bitfield-Mask: 0x07) */ +#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Pos (24UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_BO_THRESHOLD (Bit 24) */ +#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Msk (0xff000000UL) /*!< FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_BO_THRESHOLD (Bitfield-Mask: 0xff) */ /* ---------------------- FTDF_FTDF_LMAC_CONTROL_DELTA_REG ---------------------- */ #define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Pos (1UL) /*!< FTDF FTDF_LMAC_CONTROL_DELTA_REG: LMACREADY4SLEEP_D (Bit 1) */ @@ -6077,6 +6220,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Msk (0x2UL) /*!< FTDF FTDF_LMAC_EVENT_REG: CCASTAT_E (Bitfield-Mask: 0x01) */ #define FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Pos (2UL) /*!< FTDF FTDF_LMAC_EVENT_REG: RXTIMEREXPIRED_E (Bit 2) */ #define FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Msk (0x4UL) /*!< FTDF FTDF_LMAC_EVENT_REG: RXTIMEREXPIRED_E (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Pos (3UL) /*!< FTDF FTDF_LMAC_EVENT_REG: CSMA_CA_BO_THR_E (Bit 3) */ +#define FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Msk (0x8UL) /*!< FTDF FTDF_LMAC_EVENT_REG: CSMA_CA_BO_THR_E (Bitfield-Mask: 0x01) */ /* --------------------------- FTDF_FTDF_LMAC_MASK_REG -------------------------- */ #define FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Pos (0UL) /*!< FTDF FTDF_LMAC_MASK_REG: EDSCANREADY_M (Bit 0) */ @@ -6085,6 +6230,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Msk (0x2UL) /*!< FTDF FTDF_LMAC_MASK_REG: CCASTAT_M (Bitfield-Mask: 0x01) */ #define FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Pos (2UL) /*!< FTDF FTDF_LMAC_MASK_REG: RXTIMEREXPIRED_M (Bit 2) */ #define FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Msk (0x4UL) /*!< FTDF FTDF_LMAC_MASK_REG: RXTIMEREXPIRED_M (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Pos (3UL) /*!< FTDF FTDF_LMAC_MASK_REG: CSMA_CA_BO_THR_M (Bit 3) */ +#define FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Msk (0x8UL) /*!< FTDF FTDF_LMAC_MASK_REG: CSMA_CA_BO_THR_M (Bitfield-Mask: 0x01) */ /* ------------------------- FTDF_FTDF_LMAC_MANUAL_1_REG ------------------------ */ #define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Pos (0UL) /*!< FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_MODE (Bit 0) */ @@ -6287,6 +6434,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Msk (0xff00UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXLATENCY (Bitfield-Mask: 0xff) */ #define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Pos (16UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYENABLE (Bit 16) */ #define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Msk (0xff0000UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: PHYENABLE (Bitfield-Mask: 0xff) */ +#define FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Pos (24UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: USE_LEGACY_PHY_EN (Bit 24) */ +#define FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Msk (0x1000000UL) /*!< FTDF FTDF_PHY_PARAMETERS_3_REG: USE_LEGACY_PHY_EN (Bitfield-Mask: 0x01) */ /* ------------------------- FTDF_FTDF_RX_CONTROL_0_REG ------------------------- */ #define FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Pos (0UL) /*!< FTDF FTDF_RX_CONTROL_0_REG: DBGRXTRANSPARENTMODE (Bit 0) */ @@ -6384,7 +6533,7 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* ----------------------- FTDF_FTDF_SYNCTIMESTAMPTHR_REG ----------------------- */ #define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Pos (0UL) /*!< FTDF FTDF_SYNCTIMESTAMPTHR_REG: SYNCTIMESTAMPTHR (Bit 0) */ -#define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Msk (0xffffffffUL) /*!< FTDF FTDF_SYNCTIMESTAMPTHR_REG: SYNCTIMESTAMPTHR (Bitfield-Mask: 0xffffffff) */ +#define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Msk (0x1ffffffUL) /*!< FTDF FTDF_SYNCTIMESTAMPTHR_REG: SYNCTIMESTAMPTHR (Bitfield-Mask: 0x1ffffff) */ /* ----------------------- FTDF_FTDF_SYNCTIMESTAMPVAL_REG ----------------------- */ #define FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Pos (0UL) /*!< FTDF FTDF_SYNCTIMESTAMPVAL_REG: SYNCTIMESTAMPVAL (Bit 0) */ @@ -6440,6 +6589,12 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Pos (16UL) /*!< FTDF FTDF_LMACRESET_REG: LMACGLOBRESET_COUNT (Bit 16) */ #define FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Msk (0x10000UL) /*!< FTDF FTDF_LMACRESET_REG: LMACGLOBRESET_COUNT (Bitfield-Mask: 0x01) */ +/* ----------------------- FTDF_FTDF_WAKEUP_CONTROL_OS_REG ---------------------- */ +#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Pos (0UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_SET (Bit 0) */ +#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Msk (0x1UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_SET (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Pos (1UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_CLEAR (Bit 1) */ +#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Msk (0x2UL) /*!< FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_CLEAR (Bitfield-Mask: 0x01) */ + /* ------------------------- FTDF_FTDF_SYMBOLTIMETHR_REG ------------------------ */ #define FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Pos (0UL) /*!< FTDF FTDF_SYMBOLTIMETHR_REG: SYMBOLTIMETHR (Bit 0) */ #define FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Msk (0xffffffffUL) /*!< FTDF FTDF_SYMBOLTIMETHR_REG: SYMBOLTIMETHR (Bitfield-Mask: 0xffffffff) */ @@ -6481,6 +6636,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Msk (0xfUL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */ #define FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Pos (4UL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: ISWAKEUP (Bit 4) */ #define FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Msk (0x10UL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: ISWAKEUP (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Pos (8UL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: PTI_TX (Bit 8) */ +#define FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Msk (0xf00UL) /*!< FTDF FTDF_TX_PRIORITY_0_REG: PTI_TX (Bitfield-Mask: 0x0f) */ /* -------------------------- FTDF_FTDF_TX_FLAG_S_1_REG ------------------------- */ #define FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_S_1_REG: TX_FLAG_STAT (Bit 0) */ @@ -6499,6 +6656,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Msk (0xfUL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */ #define FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Pos (4UL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: ISWAKEUP (Bit 4) */ #define FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Msk (0x10UL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: ISWAKEUP (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Pos (8UL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: PTI_TX (Bit 8) */ +#define FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Msk (0xf00UL) /*!< FTDF FTDF_TX_PRIORITY_1_REG: PTI_TX (Bitfield-Mask: 0x0f) */ /* -------------------------- FTDF_FTDF_TX_FLAG_S_2_REG ------------------------- */ #define FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_S_2_REG: TX_FLAG_STAT (Bit 0) */ @@ -6517,6 +6676,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Msk (0xfUL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */ #define FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Pos (4UL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: ISWAKEUP (Bit 4) */ #define FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Msk (0x10UL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: ISWAKEUP (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Pos (8UL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: PTI_TX (Bit 8) */ +#define FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Msk (0xf00UL) /*!< FTDF FTDF_TX_PRIORITY_2_REG: PTI_TX (Bitfield-Mask: 0x0f) */ /* -------------------------- FTDF_FTDF_TX_FLAG_S_3_REG ------------------------- */ #define FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Pos (0UL) /*!< FTDF FTDF_TX_FLAG_S_3_REG: TX_FLAG_STAT (Bit 0) */ @@ -6535,6 +6696,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Msk (0xfUL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: TX_PRIORITY (Bitfield-Mask: 0x0f) */ #define FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Pos (4UL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: ISWAKEUP (Bit 4) */ #define FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Msk (0x10UL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: ISWAKEUP (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Pos (8UL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: PTI_TX (Bit 8) */ +#define FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Msk (0xf00UL) /*!< FTDF FTDF_TX_PRIORITY_3_REG: PTI_TX (Bitfield-Mask: 0x0f) */ /* --------------------------- FTDF_FTDF_TX_SET_OS_REG -------------------------- */ #define FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Pos (0UL) /*!< FTDF FTDF_TX_SET_OS_REG: TX_FLAG_SET (Bit 0) */ @@ -6544,15 +6707,27 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Pos (0UL) /*!< FTDF FTDF_TX_CLEAR_OS_REG: TX_FLAG_CLEAR (Bit 0) */ #define FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Msk (0xfUL) /*!< FTDF FTDF_TX_CLEAR_OS_REG: TX_FLAG_CLEAR (Bitfield-Mask: 0x0f) */ -/* ------------------------- FTDF_FTDF_WAKEUPINTTHR_REG ------------------------- */ -#define FTDF_FTDF_WAKEUPINTTHR_REG_WAKEUPINTTHR_Pos (0UL) /*!< FTDF FTDF_WAKEUPINTTHR_REG: WAKEUPINTTHR (Bit 0) */ -#define FTDF_FTDF_WAKEUPINTTHR_REG_WAKEUPINTTHR_Msk (0xffffffffUL) /*!< FTDF FTDF_WAKEUPINTTHR_REG: WAKEUPINTTHR (Bitfield-Mask: 0xffffffff) */ - /* ------------------------ FTDF_FTDF_WAKEUP_CONTROL_REG ------------------------ */ -#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPTIMERENABLE_Pos (0UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPTIMERENABLE (Bit 0) */ -#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPTIMERENABLE_Msk (0x1UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPTIMERENABLE (Bitfield-Mask: 0x01) */ -#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Pos (1UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPENABLE (Bit 1) */ -#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Msk (0x2UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPENABLE (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Pos (0UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPINTTHR (Bit 0) */ +#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Msk (0x1ffffffUL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPINTTHR (Bitfield-Mask: 0x1ffffff) */ +#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Pos (29UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPENABLE (Bit 29) */ +#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Msk (0x20000000UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPENABLE (Bitfield-Mask: 0x01) */ +#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Pos (30UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUP_MODE (Bit 30) */ +#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Msk (0xc0000000UL) /*!< FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUP_MODE (Bitfield-Mask: 0x03) */ + +/* ------------------------- FTDF_FTDF_LONG_ADDR_0_0_REG ------------------------ */ +#define FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Pos (0UL) /*!< FTDF FTDF_LONG_ADDR_0_0_REG: EXP_SA_L (Bit 0) */ +#define FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Msk (0xffffffffUL) /*!< FTDF FTDF_LONG_ADDR_0_0_REG: EXP_SA_L (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------- FTDF_FTDF_LONG_ADDR_1_0_REG ------------------------ */ +#define FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Pos (0UL) /*!< FTDF FTDF_LONG_ADDR_1_0_REG: EXP_SA_H (Bit 0) */ +#define FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Msk (0xffffffffUL) /*!< FTDF FTDF_LONG_ADDR_1_0_REG: EXP_SA_H (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------ FTDF_FTDF_SIZE_AND_VAL_0_REG ------------------------ */ +#define FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Pos (0UL) /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: VALID_SA (Bit 0) */ +#define FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Msk (0xfUL) /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: VALID_SA (Bitfield-Mask: 0x0f) */ +#define FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Pos (4UL) /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: SHORT_LONGNOT (Bit 4) */ +#define FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Msk (0x10UL) /*!< FTDF FTDF_SIZE_AND_VAL_0_REG: SHORT_LONGNOT (Bitfield-Mask: 0x01) */ /* ================================================================================ */ @@ -6617,6 +6792,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Msk (0x2UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: SW_PAUSE_EN (Bitfield-Mask: 0x01) */ #define GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Pos (2UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: HW_PAUSE_EN (Bit 2) */ #define GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Msk (0x4UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: HW_PAUSE_EN (Bitfield-Mask: 0x01) */ +#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Pos (3UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_CLK_SEL (Bit 3) */ +#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Msk (0x8UL) /*!< GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_CLK_SEL (Bitfield-Mask: 0x01) */ /* -------------------------- GP_TIMERS_BREATH_CFG_REG -------------------------- */ #define GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Pos (0UL) /*!< GP_TIMERS BREATH_CFG_REG: BRTH_DIV (Bit 0) */ @@ -7174,6 +7351,14 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Pos (14UL) /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_BUSY (Bit 14) */ #define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Msk (0x4000UL) /*!< GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_BUSY (Bitfield-Mask: 0x01) */ +/* -------------------------- GPIO_RAMBIST_STATUS3_REG -------------------------- */ +#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Pos (0UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_LINE_FAIL (Bit 0) */ +#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Msk (0x1UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01) */ +#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Pos (1UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_FAIL (Bit 1) */ +#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Msk (0x2UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_FAIL (Bitfield-Mask: 0x01) */ +#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Pos (2UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_BUSY (Bit 2) */ +#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Msk (0x4UL) /*!< GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_BUSY (Bitfield-Mask: 0x01) */ + /* -------------------------- GPIO_ROMBIST_RESULTL_REG -------------------------- */ #define GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Pos (0UL) /*!< GPIO ROMBIST_RESULTL_REG: ROMBIST_RESULTL (Bit 0) */ #define GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Msk (0xffffUL) /*!< GPIO ROMBIST_RESULTL_REG: ROMBIST_RESULTL (Bitfield-Mask: 0xffff) */ @@ -7201,6 +7386,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Msk (0x80UL) /*!< GPIO TEST_CTRL_REG: SHOW_TXDAC_MOD (Bitfield-Mask: 0x01) */ #define GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Pos (8UL) /*!< GPIO TEST_CTRL_REG: SHOW_PWR_TST_OUT (Bit 8) */ #define GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Msk (0x700UL) /*!< GPIO TEST_CTRL_REG: SHOW_PWR_TST_OUT (Bitfield-Mask: 0x07) */ +#define GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Pos (12UL) /*!< GPIO TEST_CTRL_REG: XTAL16M_TST_SYS (Bit 12) */ +#define GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Msk (0x3000UL) /*!< GPIO TEST_CTRL_REG: XTAL16M_TST_SYS (Bitfield-Mask: 0x03) */ +#define GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Pos (14UL) /*!< GPIO TEST_CTRL_REG: XTAL16M_TRIM_TEST_EN (Bit 14) */ +#define GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Msk (0x4000UL) /*!< GPIO TEST_CTRL_REG: XTAL16M_TRIM_TEST_EN (Bitfield-Mask: 0x01) */ /* ----------------------------- GPIO_TEST_CTRL2_REG ---------------------------- */ #define GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Pos (0UL) /*!< GPIO TEST_CTRL2_REG: ANA_TESTMUX_CTRL (Bit 0) */ @@ -7211,8 +7400,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* ----------------------------- GPIO_TEST_CTRL3_REG ---------------------------- */ #define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Pos (0UL) /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_SEL (Bit 0) */ #define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Msk (0x3fUL) /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_SEL (Bitfield-Mask: 0x3f) */ -#define GPIO_TEST_CTRL3_REG_USBCOMP_TEST_Pos (6UL) /*!< GPIO TEST_CTRL3_REG: USBCOMP_TEST (Bit 6) */ -#define GPIO_TEST_CTRL3_REG_USBCOMP_TEST_Msk (0x40UL) /*!< GPIO TEST_CTRL3_REG: USBCOMP_TEST (Bitfield-Mask: 0x01) */ +#define GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Pos (6UL) /*!< GPIO TEST_CTRL3_REG: VBUS_COMPARATOR_TEST (Bit 6) */ +#define GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Msk (0x40UL) /*!< GPIO TEST_CTRL3_REG: VBUS_COMPARATOR_TEST (Bitfield-Mask: 0x01) */ #define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Pos (8UL) /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_PARAM (Bit 8) */ #define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Msk (0xff00UL) /*!< GPIO TEST_CTRL3_REG: RF_TEST_OUT_PARAM (Bitfield-Mask: 0xff) */ @@ -7251,6 +7440,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Msk (0x1000UL) /*!< GPIO TEST_CTRL5_REG: TEST_VCONT_A (Bitfield-Mask: 0x01) */ #define GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Pos (13UL) /*!< GPIO TEST_CTRL5_REG: TEST_VREF_1V2_A (Bit 13) */ #define GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Msk (0x2000UL) /*!< GPIO TEST_CTRL5_REG: TEST_VREF_1V2_A (Bitfield-Mask: 0x01) */ +#define GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Pos (14UL) /*!< GPIO TEST_CTRL5_REG: TEST_POR_VBAT_NOK_AVD (Bit 14) */ +#define GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Msk (0x4000UL) /*!< GPIO TEST_CTRL5_REG: TEST_POR_VBAT_NOK_AVD (Bitfield-Mask: 0x01) */ /* ================================================================================ */ @@ -7309,8 +7500,6 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Msk (0x2UL) /*!< GPREG GP_CONTROL_REG: BLE_H2H_BRIDGE_BYPASS (Bitfield-Mask: 0x01) */ #define GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Pos (2UL) /*!< GPREG GP_CONTROL_REG: BLE_WAKEUP_LP_IRQ (Bit 2) */ #define GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Msk (0x4UL) /*!< GPREG GP_CONTROL_REG: BLE_WAKEUP_LP_IRQ (Bitfield-Mask: 0x01) */ -#define GPREG_GP_CONTROL_REG_BLE_DEEPSLDUR_MONITOR_Pos (8UL) /*!< GPREG GP_CONTROL_REG: BLE_DEEPSLDUR_MONITOR (Bit 8) */ -#define GPREG_GP_CONTROL_REG_BLE_DEEPSLDUR_MONITOR_Msk (0xff00UL) /*!< GPREG GP_CONTROL_REG: BLE_DEEPSLDUR_MONITOR (Bitfield-Mask: 0xff) */ /* --------------------------- GPREG_ECC_BASE_ADDR_REG -------------------------- */ #define GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Pos (0UL) /*!< GPREG ECC_BASE_ADDR_REG: ECC_BASE_ADDR (Bit 0) */ @@ -7329,6 +7518,12 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define GPREG_LED_CONTROL_REG_LED2_EN_Msk (0x10UL) /*!< GPREG LED_CONTROL_REG: LED2_EN (Bitfield-Mask: 0x01) */ #define GPREG_LED_CONTROL_REG_LED3_EN_Pos (5UL) /*!< GPREG LED_CONTROL_REG: LED3_EN (Bit 5) */ #define GPREG_LED_CONTROL_REG_LED3_EN_Msk (0x20UL) /*!< GPREG LED_CONTROL_REG: LED3_EN (Bitfield-Mask: 0x01) */ +#define GPREG_LED_CONTROL_REG_LED_TRIM_Pos (6UL) /*!< GPREG LED_CONTROL_REG: LED_TRIM (Bit 6) */ +#define GPREG_LED_CONTROL_REG_LED_TRIM_Msk (0x3c0UL) /*!< GPREG LED_CONTROL_REG: LED_TRIM (Bitfield-Mask: 0x0f) */ + +/* ------------------------- GPREG_BLE_FINECNT_SAMP_REG ------------------------- */ +#define GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Pos (0UL) /*!< GPREG BLE_FINECNT_SAMP_REG: BLE_FINECNT_SAMP (Bit 0) */ +#define GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Msk (0x3ffUL) /*!< GPREG BLE_FINECNT_SAMP_REG: BLE_FINECNT_SAMP (Bitfield-Mask: 0x3ff) */ /* --------------------------- GPREG_PLL_SYS_CTRL1_REG -------------------------- */ #define GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Pos (0UL) /*!< GPREG PLL_SYS_CTRL1_REG: PLL_EN (Bit 0) */ @@ -7416,15 +7611,15 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define I2C_I2C_SAR_REG_IC_SAR_Pos (0UL) /*!< I2C I2C_SAR_REG: IC_SAR (Bit 0) */ #define I2C_I2C_SAR_REG_IC_SAR_Msk (0x3ffUL) /*!< I2C I2C_SAR_REG: IC_SAR (Bitfield-Mask: 0x3ff) */ -/* ---------------------------- I2C_I2C_HS_MADDR_REG ---------------------------- */ -#define I2C_I2C_HS_MADDR_REG_IIC_HS_MAR_Pos (0UL) /*!< I2C I2C_HS_MADDR_REG: IIC_HS_MAR (Bit 0) */ -#define I2C_I2C_HS_MADDR_REG_IIC_HS_MAR_Msk (0x7UL) /*!< I2C I2C_HS_MADDR_REG: IIC_HS_MAR (Bitfield-Mask: 0x07) */ - /* ---------------------------- I2C_I2C_DATA_CMD_REG ---------------------------- */ #define I2C_I2C_DATA_CMD_REG_DAT_Pos (0UL) /*!< I2C I2C_DATA_CMD_REG: DAT (Bit 0) */ #define I2C_I2C_DATA_CMD_REG_DAT_Msk (0xffUL) /*!< I2C I2C_DATA_CMD_REG: DAT (Bitfield-Mask: 0xff) */ #define I2C_I2C_DATA_CMD_REG_CMD_Pos (8UL) /*!< I2C I2C_DATA_CMD_REG: CMD (Bit 8) */ #define I2C_I2C_DATA_CMD_REG_CMD_Msk (0x100UL) /*!< I2C I2C_DATA_CMD_REG: CMD (Bitfield-Mask: 0x01) */ +#define I2C_I2C_DATA_CMD_REG_STOP_Pos (9UL) /*!< I2C I2C_DATA_CMD_REG: STOP (Bit 9) */ +#define I2C_I2C_DATA_CMD_REG_STOP_Msk (0x200UL) /*!< I2C I2C_DATA_CMD_REG: STOP (Bitfield-Mask: 0x01) */ +#define I2C_I2C_DATA_CMD_REG_RESTART_Pos (10UL) /*!< I2C I2C_DATA_CMD_REG: RESTART (Bit 10) */ +#define I2C_I2C_DATA_CMD_REG_RESTART_Msk (0x400UL) /*!< I2C I2C_DATA_CMD_REG: RESTART (Bitfield-Mask: 0x01) */ /* --------------------------- I2C_I2C_SS_SCL_HCNT_REG -------------------------- */ #define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL) /*!< I2C I2C_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bit 0) */ @@ -7525,8 +7720,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define I2C_I2C_RX_TL_REG_RX_TL_Msk (0x1fUL) /*!< I2C I2C_RX_TL_REG: RX_TL (Bitfield-Mask: 0x1f) */ /* ------------------------------ I2C_I2C_TX_TL_REG ----------------------------- */ -#define I2C_I2C_TX_TL_REG_RX_TL_Pos (0UL) /*!< I2C I2C_TX_TL_REG: RX_TL (Bit 0) */ -#define I2C_I2C_TX_TL_REG_RX_TL_Msk (0x1fUL) /*!< I2C I2C_TX_TL_REG: RX_TL (Bitfield-Mask: 0x1f) */ +#define I2C_I2C_TX_TL_REG_TX_TL_Pos (0UL) /*!< I2C I2C_TX_TL_REG: TX_TL (Bit 0) */ +#define I2C_I2C_TX_TL_REG_TX_TL_Msk (0x1fUL) /*!< I2C I2C_TX_TL_REG: TX_TL (Bitfield-Mask: 0x1f) */ /* ---------------------------- I2C_I2C_CLR_INTR_REG ---------------------------- */ #define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos (0UL) /*!< I2C I2C_CLR_INTR_REG: CLR_INTR (Bit 0) */ @@ -7728,15 +7923,15 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define I2C2_I2C2_SAR_REG_IC_SAR_Pos (0UL) /*!< I2C2 I2C2_SAR_REG: IC_SAR (Bit 0) */ #define I2C2_I2C2_SAR_REG_IC_SAR_Msk (0x3ffUL) /*!< I2C2 I2C2_SAR_REG: IC_SAR (Bitfield-Mask: 0x3ff) */ -/* --------------------------- I2C2_I2C2_HS_MADDR_REG --------------------------- */ -#define I2C2_I2C2_HS_MADDR_REG_IIC_HS_MAR_Pos (0UL) /*!< I2C2 I2C2_HS_MADDR_REG: IIC_HS_MAR (Bit 0) */ -#define I2C2_I2C2_HS_MADDR_REG_IIC_HS_MAR_Msk (0x7UL) /*!< I2C2 I2C2_HS_MADDR_REG: IIC_HS_MAR (Bitfield-Mask: 0x07) */ - /* --------------------------- I2C2_I2C2_DATA_CMD_REG --------------------------- */ #define I2C2_I2C2_DATA_CMD_REG_DAT_Pos (0UL) /*!< I2C2 I2C2_DATA_CMD_REG: DAT (Bit 0) */ #define I2C2_I2C2_DATA_CMD_REG_DAT_Msk (0xffUL) /*!< I2C2 I2C2_DATA_CMD_REG: DAT (Bitfield-Mask: 0xff) */ #define I2C2_I2C2_DATA_CMD_REG_CMD_Pos (8UL) /*!< I2C2 I2C2_DATA_CMD_REG: CMD (Bit 8) */ #define I2C2_I2C2_DATA_CMD_REG_CMD_Msk (0x100UL) /*!< I2C2 I2C2_DATA_CMD_REG: CMD (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_DATA_CMD_REG_STOP_Pos (9UL) /*!< I2C2 I2C2_DATA_CMD_REG: STOP (Bit 9) */ +#define I2C2_I2C2_DATA_CMD_REG_STOP_Msk (0x200UL) /*!< I2C2 I2C2_DATA_CMD_REG: STOP (Bitfield-Mask: 0x01) */ +#define I2C2_I2C2_DATA_CMD_REG_RESTART_Pos (10UL) /*!< I2C2 I2C2_DATA_CMD_REG: RESTART (Bit 10) */ +#define I2C2_I2C2_DATA_CMD_REG_RESTART_Msk (0x400UL) /*!< I2C2 I2C2_DATA_CMD_REG: RESTART (Bitfield-Mask: 0x01) */ /* -------------------------- I2C2_I2C2_SS_SCL_HCNT_REG ------------------------- */ #define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL) /*!< I2C2 I2C2_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bit 0) */ @@ -7837,8 +8032,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define I2C2_I2C2_RX_TL_REG_RX_TL_Msk (0x1fUL) /*!< I2C2 I2C2_RX_TL_REG: RX_TL (Bitfield-Mask: 0x1f) */ /* ----------------------------- I2C2_I2C2_TX_TL_REG ---------------------------- */ -#define I2C2_I2C2_TX_TL_REG_RX_TL_Pos (0UL) /*!< I2C2 I2C2_TX_TL_REG: RX_TL (Bit 0) */ -#define I2C2_I2C2_TX_TL_REG_RX_TL_Msk (0x1fUL) /*!< I2C2 I2C2_TX_TL_REG: RX_TL (Bitfield-Mask: 0x1f) */ +#define I2C2_I2C2_TX_TL_REG_TX_TL_Pos (0UL) /*!< I2C2 I2C2_TX_TL_REG: TX_TL (Bit 0) */ +#define I2C2_I2C2_TX_TL_REG_TX_TL_Msk (0x1fUL) /*!< I2C2 I2C2_TX_TL_REG: TX_TL (Bitfield-Mask: 0x1f) */ /* --------------------------- I2C2_I2C2_CLR_INTR_REG --------------------------- */ #define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Pos (0UL) /*!< I2C2 I2C2_CLR_INTR_REG: CLR_INTR (Bit 0) */ @@ -8493,6 +8688,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* ---------------------------- OTPC_OTPC_CELADR_REG ---------------------------- */ #define OTPC_OTPC_CELADR_REG_OTPC_CELADR_Pos (0UL) /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR (Bit 0) */ #define OTPC_OTPC_CELADR_REG_OTPC_CELADR_Msk (0x3fffUL) /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR (Bitfield-Mask: 0x3fff) */ +#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Pos (16UL) /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR_LV (Bit 16) */ +#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Msk (0x3fff0000UL) /*!< OTPC OTPC_CELADR_REG: OTPC_CELADR_LV (Bitfield-Mask: 0x3fff) */ /* ---------------------------- OTPC_OTPC_NWORDS_REG ---------------------------- */ #define OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Pos (0UL) /*!< OTPC OTPC_NWORDS_REG: OTPC_NWORDS (Bit 0) */ @@ -8536,6 +8733,16 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Pos (23UL) /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_RDENL_PROT (Bit 23) */ #define OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Msk (0x800000UL) /*!< OTPC OTPC_TIM2_REG: OTPC_TIM2_RDENL_PROT (Bitfield-Mask: 0x01) */ +/* ----------------------------- OTPC_OTPC_TEST_REG ----------------------------- */ +#define OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Pos (0UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_COR_DIS (Bit 0) */ +#define OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Msk (0x1UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_COR_DIS (Bitfield-Mask: 0x01) */ +#define OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Pos (16UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_RAW_ECC (Bit 16) */ +#define OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Msk (0xff0000UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_RAW_ECC (Bitfield-Mask: 0xff) */ +#define OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Pos (24UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_STAT (Bit 24) */ +#define OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Msk (0x3000000UL) /*!< OTPC OTPC_TEST_REG: OTPC_SECDED_STAT (Bitfield-Mask: 0x03) */ +#define OTPC_OTPC_TEST_REG_OTPC_USED_RR_Pos (26UL) /*!< OTPC OTPC_TEST_REG: OTPC_USED_RR (Bit 26) */ +#define OTPC_OTPC_TEST_REG_OTPC_USED_RR_Msk (0x4000000UL) /*!< OTPC OTPC_TEST_REG: OTPC_USED_RR (Bitfield-Mask: 0x01) */ + /* ================================================================================ */ /* ================ struct 'PATCH' Position & Mask ================ */ @@ -8787,8 +8994,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Msk (0xcUL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_TX (Bitfield-Mask: 0x03) */ #define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Pos (4UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: MODINDEX (Bit 4) */ #define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Msk (0x30UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: MODINDEX (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_DELAY_Pos (6UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: DELAY (Bit 6) */ -#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_DELAY_Msk (0xc0UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: DELAY (Bitfield-Mask: 0x03) */ +#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Pos (6UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_DELAY (Bit 6) */ +#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Msk (0xc0UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_DELAY (Bitfield-Mask: 0x03) */ #define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Pos (8UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_INV (Bit 8) */ #define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Msk (0x100UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_INV (Bitfield-Mask: 0x01) */ #define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Pos (9UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_86 (Bit 9) */ @@ -8799,16 +9006,22 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Msk (0x800UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: EO_PACKET_DIS (Bitfield-Mask: 0x01) */ #define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Pos (12UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BT_SEL (Bit 12) */ #define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Msk (0x1000UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BT_SEL (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Pos (13UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BLE_DAC_SEL (Bit 13) */ +#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Msk (0x2000UL) /*!< PLLDIG RF_SYNTH_CTRL2_BLE_REG: BLE_DAC_SEL (Bitfield-Mask: 0x01) */ /* ----------------------- PLLDIG_RF_SYNTH_CTRL2_FTDF_REG ----------------------- */ #define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Pos (0UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_RX (Bit 0) */ #define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Msk (0x3UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_RX (Bitfield-Mask: 0x03) */ #define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Pos (2UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_TX (Bit 2) */ #define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Msk (0xcUL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_TX (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_DELAY_Pos (6UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: DELAY (Bit 6) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_DELAY_Msk (0xc0UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: DELAY (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_FTDF_MODINDEX_Pos (8UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: FTDF_MODINDEX (Bit 8) */ -#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_FTDF_MODINDEX_Msk (0x3f00UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: FTDF_MODINDEX (Bitfield-Mask: 0x3f) */ +#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Pos (4UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: MODINDEX (Bit 4) */ +#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Msk (0x30UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: MODINDEX (Bitfield-Mask: 0x03) */ +#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Pos (6UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDAC_DELAY (Bit 6) */ +#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Msk (0x40UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDAC_DELAY (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Pos (8UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: GAUSS_INV (Bit 8) */ +#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Msk (0x100UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: GAUSS_INV (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Pos (10UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDATA_INV (Bit 10) */ +#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Msk (0x400UL) /*!< PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDATA_INV (Bitfield-Mask: 0x01) */ /* -------------------------- PLLDIG_RF_SYNTH_CTRL3_REG ------------------------- */ #define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Pos (0UL) /*!< PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_WR (Bit 0) */ @@ -8825,6 +9038,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Msk (0x30UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_SEL (Bitfield-Mask: 0x03) */ #define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Pos (6UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_PERIOD (Bit 6) */ #define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Msk (0xc0UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_PERIOD (Bitfield-Mask: 0x03) */ +#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Pos (8UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_MD_STATE_DLY_SEL (Bit 8) */ +#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Msk (0x100UL) /*!< PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_MD_STATE_DLY_SEL (Bitfield-Mask: 0x01) */ /* ------------------------ PLLDIG_RF_MGAIN_CTRL_BLE_REG ------------------------ */ #define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Pos (0UL) /*!< PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_WR (Bit 0) */ @@ -8840,15 +9055,19 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* ------------------------ PLLDIG_RF_MGAIN_CTRL_FTDF_REG ----------------------- */ #define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Pos (0UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_WR (Bit 0) */ -#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Msk (0x3fUL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_WR (Bitfield-Mask: 0x3f) */ -#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Pos (6UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_SEL (Bit 6) */ -#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Msk (0x40UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_SEL (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Msk (0x7fUL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_WR (Bitfield-Mask: 0x7f) */ +#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Pos (7UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_SEL (Bit 7) */ +#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Msk (0x80UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_SEL (Bitfield-Mask: 0x01) */ #define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Pos (8UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_OFFSET (Bit 8) */ -#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Msk (0x3f00UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_OFFSET (Bitfield-Mask: 0x3f) */ +#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Msk (0xff00UL) /*!< PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_OFFSET (Bitfield-Mask: 0xff) */ /* -------------------------- PLLDIG_RF_MGAIN_CTRL2_REG ------------------------- */ #define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Pos (0UL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_TRANSMIT_LENGTH (Bit 0) */ #define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Msk (0x7fUL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_TRANSMIT_LENGTH (Bitfield-Mask: 0x7f) */ +#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Pos (7UL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_MODE_SEL (Bit 7) */ +#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Msk (0x80UL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_MODE_SEL (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Pos (8UL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MSK_GAINCAL_LONG (Bit 8) */ +#define PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Msk (0x100UL) /*!< PLLDIG RF_MGAIN_CTRL2_REG: MSK_GAINCAL_LONG (Bitfield-Mask: 0x01) */ /* ----------------------- PLLDIG_RF_VCO_CALCAP_BIT14_REG ----------------------- */ #define PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Pos (0UL) /*!< PLLDIG RF_VCO_CALCAP_BIT14_REG: VCO_CALCAP_BIT14 (Bit 0) */ @@ -8868,11 +9087,15 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define PLLDIG_RF_BMCW_REG_HSI_SEL_Pos (8UL) /*!< PLLDIG RF_BMCW_REG: HSI_SEL (Bit 8) */ #define PLLDIG_RF_BMCW_REG_HSI_SEL_Msk (0x100UL) /*!< PLLDIG RF_BMCW_REG: HSI_SEL (Bitfield-Mask: 0x01) */ -/* -------------------------- PLLDIG_RF_KMOD_ALPHA_REG -------------------------- */ -#define PLLDIG_RF_KMOD_ALPHA_REG_KMOD_ALPHA_BLE_Pos (0UL) /*!< PLLDIG RF_KMOD_ALPHA_REG: KMOD_ALPHA_BLE (Bit 0) */ -#define PLLDIG_RF_KMOD_ALPHA_REG_KMOD_ALPHA_BLE_Msk (0x3fUL) /*!< PLLDIG RF_KMOD_ALPHA_REG: KMOD_ALPHA_BLE (Bitfield-Mask: 0x3f) */ -#define PLLDIG_RF_KMOD_ALPHA_REG_KMOD_ALPHA_FTDF_Pos (6UL) /*!< PLLDIG RF_KMOD_ALPHA_REG: KMOD_ALPHA_FTDF (Bit 6) */ -#define PLLDIG_RF_KMOD_ALPHA_REG_KMOD_ALPHA_FTDF_Msk (0xfc0UL) /*!< PLLDIG RF_KMOD_ALPHA_REG: KMOD_ALPHA_FTDF (Bitfield-Mask: 0x3f) */ +/* ------------------------ PLLDIG_RF_KMOD_ALPHA_BLE_REG ------------------------ */ +#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Pos (0UL) /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_GAUSSDAC (Bit 0) */ +#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Msk (0x3fUL) /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_GAUSSDAC (Bitfield-Mask: 0x3f) */ +#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Pos (6UL) /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_TXDAC (Bit 6) */ +#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Msk (0xfc0UL) /*!< PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_TXDAC (Bitfield-Mask: 0x3f) */ + +/* ------------------------ PLLDIG_RF_KMOD_ALPHA_FTDF_REG ----------------------- */ +#define PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Pos (0UL) /*!< PLLDIG RF_KMOD_ALPHA_FTDF_REG: KMOD_ALPHA_FTDF (Bit 0) */ +#define PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Msk (0x3fUL) /*!< PLLDIG RF_KMOD_ALPHA_FTDF_REG: KMOD_ALPHA_FTDF (Bitfield-Mask: 0x3f) */ /* ----------------------- PLLDIG_RF_SYNTH_RESULT_BLE_REG ----------------------- */ #define PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT_BLE_REG: GAUSS_GAIN_CAL_RD (Bit 0) */ @@ -8882,7 +9105,7 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* ----------------------- PLLDIG_RF_SYNTH_RESULT_FTDF_REG ---------------------- */ #define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT_FTDF_REG: MSK_GAIN_CAL_RD (Bit 0) */ -#define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Msk (0x3fUL) /*!< PLLDIG RF_SYNTH_RESULT_FTDF_REG: MSK_GAIN_CAL_RD (Bitfield-Mask: 0x3f) */ +#define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Msk (0x7fUL) /*!< PLLDIG RF_SYNTH_RESULT_FTDF_REG: MSK_GAIN_CAL_RD (Bitfield-Mask: 0x7f) */ /* ----------------------- PLLDIG_RF_SYNTH_RESULT2_BLE_REG ---------------------- */ #define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT2_BLE_REG: GAUSS_GAIN_RD (Bit 0) */ @@ -8891,10 +9114,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Msk (0x3f00UL) /*!< PLLDIG RF_SYNTH_RESULT2_BLE_REG: CN_CAL_RD (Bitfield-Mask: 0x3f) */ /* ---------------------- PLLDIG_RF_SYNTH_RESULT2_FTDF_REG ---------------------- */ -#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_LOWER_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_LOWER_RD (Bit 0) */ -#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_LOWER_RD_Msk (0x3fUL) /*!< PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_LOWER_RD (Bitfield-Mask: 0x3f) */ -#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_UPPER_RD_Pos (6UL) /*!< PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_UPPER_RD (Bit 6) */ -#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_UPPER_RD_Msk (0xfc0UL) /*!< PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_UPPER_RD (Bitfield-Mask: 0x3f) */ +#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_RD (Bit 0) */ +#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Msk (0xffUL) /*!< PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_RD (Bitfield-Mask: 0xff) */ /* ---------------------- PLLDIG_RF_SYNTH_RESULT3_FTDF_REG ---------------------- */ #define PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Pos (0UL) /*!< PLLDIG RF_SYNTH_RESULT3_FTDF_REG: CN_CAL_FTDF_RD (Bit 0) */ @@ -8908,6 +9129,12 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Pos (0UL) /*!< PLLDIG RF_CALCAP2_REG: VCO_CALCAP_HIGH (Bit 0) */ #define PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Msk (0x3UL) /*!< PLLDIG RF_CALCAP2_REG: VCO_CALCAP_HIGH (Bitfield-Mask: 0x03) */ +/* -------------------------- PLLDIG_RF_NMD_OFFSET_REG -------------------------- */ +#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Pos (0UL) /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_XTAL16M (Bit 0) */ +#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Msk (0xffUL) /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_XTAL16M (Bitfield-Mask: 0xff) */ +#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Pos (8UL) /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_PLL96M (Bit 8) */ +#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Msk (0xff00UL) /*!< PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_PLL96M (Bitfield-Mask: 0xff) */ + /* ------------------------- PLLDIG_RF_FTDF_PHYATTR_REG ------------------------- */ #define PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Pos (0UL) /*!< PLLDIG RF_FTDF_PHYATTR_REG: FTDF_PHYATTR (Bit 0) */ #define PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Msk (0xffffUL) /*!< PLLDIG RF_FTDF_PHYATTR_REG: FTDF_PHYATTR (Bitfield-Mask: 0xffff) */ @@ -8928,31 +9155,35 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Pos (0UL) /*!< PLLDIG RF_CALTRIM_STEP4_REG: MDSTATE_RD (Bit 0) */ #define PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Msk (0xffffUL) /*!< PLLDIG RF_CALTRIM_STEP4_REG: MDSTATE_RD (Bitfield-Mask: 0xffff) */ -/* ------------------------- PLLDIG_RF_MSKMOD_CTRL1_REG ------------------------- */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DAC_DELAY_Pos (0UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_DAC_DELAY (Bit 0) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DAC_DELAY_Msk (0x3UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_DAC_DELAY (Bitfield-Mask: 0x03) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_INV_DAC_POL_Pos (2UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: INV_DAC_POL (Bit 2) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_INV_DAC_POL_Msk (0x4UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: INV_DAC_POL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_INV_SDM_POL_Pos (3UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: INV_SDM_POL (Bit 3) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_INV_SDM_POL_Msk (0x8UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: INV_SDM_POL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_DISABLE_DAC_Pos (4UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: DISABLE_DAC (Bit 4) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_DISABLE_DAC_Msk (0x10UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: DISABLE_DAC (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_DISABLE_SDM_Pos (5UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: DISABLE_SDM (Bit 5) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_DISABLE_SDM_Msk (0x20UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: DISABLE_SDM (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Pos (6UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_MOD_FROM_GPIO (Bit 6) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Msk (0x40UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_MOD_FROM_GPIO (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Pos (7UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_BYPASS_PHASE (Bit 7) */ -#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Msk (0x80UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_BYPASS_PHASE (Bitfield-Mask: 0x01) */ +/* -------------------------- PLLDIG_RF_MGAIN_CTRL3_REG ------------------------- */ +#define PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Pos (0UL) /*!< PLLDIG RF_MGAIN_CTRL3_REG: GFSK_GAIN_OFFSET (Bit 0) */ +#define PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Msk (0xffUL) /*!< PLLDIG RF_MGAIN_CTRL3_REG: GFSK_GAIN_OFFSET (Bitfield-Mask: 0xff) */ -/* ------------------------- PLLDIG_RF_MSKMOD_CTRL2_REG ------------------------- */ -#define PLLDIG_RF_MSKMOD_CTRL2_REG_TX_DATA_Pos (0UL) /*!< PLLDIG RF_MSKMOD_CTRL2_REG: TX_DATA (Bit 0) */ -#define PLLDIG_RF_MSKMOD_CTRL2_REG_TX_DATA_Msk (0xfUL) /*!< PLLDIG RF_MSKMOD_CTRL2_REG: TX_DATA (Bitfield-Mask: 0x0f) */ -#define PLLDIG_RF_MSKMOD_CTRL2_REG_TX_VALID_Pos (4UL) /*!< PLLDIG RF_MSKMOD_CTRL2_REG: TX_VALID (Bit 4) */ -#define PLLDIG_RF_MSKMOD_CTRL2_REG_TX_VALID_Msk (0x10UL) /*!< PLLDIG RF_MSKMOD_CTRL2_REG: TX_VALID (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL2_REG_MSK_TX_SEL_Pos (5UL) /*!< PLLDIG RF_MSKMOD_CTRL2_REG: MSK_TX_SEL (Bit 5) */ -#define PLLDIG_RF_MSKMOD_CTRL2_REG_MSK_TX_SEL_Msk (0x20UL) /*!< PLLDIG RF_MSKMOD_CTRL2_REG: MSK_TX_SEL (Bitfield-Mask: 0x01) */ -#define PLLDIG_RF_MSKMOD_CTRL2_REG_MSK_ALW_EN_Pos (6UL) /*!< PLLDIG RF_MSKMOD_CTRL2_REG: MSK_ALW_EN (Bit 6) */ -#define PLLDIG_RF_MSKMOD_CTRL2_REG_MSK_ALW_EN_Msk (0x40UL) /*!< PLLDIG RF_MSKMOD_CTRL2_REG: MSK_ALW_EN (Bitfield-Mask: 0x01) */ +/* ------------------------- PLLDIG_RF_VCO_FREQ_EST_REG ------------------------- */ +#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Pos (0UL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_EN (Bit 0) */ +#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Msk (0x1UL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_EN (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Pos (1UL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_LEN (Bit 1) */ +#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Msk (0xfeUL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_LEN (Bitfield-Mask: 0x7f) */ +#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Pos (8UL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_UPPER_RD (Bit 8) */ +#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Msk (0x700UL) /*!< PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_UPPER_RD (Bitfield-Mask: 0x07) */ + +/* -------------------------- PLLDIG_RF_SYNTH_SPARE_REG ------------------------- */ +#define PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Pos (0UL) /*!< PLLDIG RF_SYNTH_SPARE_REG: SPARE (Bit 0) */ +#define PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Msk (0xffUL) /*!< PLLDIG RF_SYNTH_SPARE_REG: SPARE (Bitfield-Mask: 0xff) */ + +/* ------------------------- PLLDIG_RF_MSKMOD_CTRL1_REG ------------------------- */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Pos (0UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_DATA (Bit 0) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Msk (0xfUL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_DATA (Bitfield-Mask: 0x0f) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Pos (4UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_VALID (Bit 4) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Msk (0x10UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_VALID (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Pos (5UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_TX_SEL (Bit 5) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Msk (0x20UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_TX_SEL (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Pos (6UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_ALW_EN (Bit 6) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Msk (0x40UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_ALW_EN (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Pos (7UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_MOD_FROM_GPIO (Bit 7) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Msk (0x80UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: TX_MOD_FROM_GPIO (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Pos (8UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_BYPASS_PHASE (Bit 8) */ +#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Msk (0x100UL) /*!< PLLDIG RF_MSKMOD_CTRL1_REG: MSK_BYPASS_PHASE (Bitfield-Mask: 0x01) */ /* ------------------------- PLLDIG_RF_MSKMOD_CHIPL_REG ------------------------- */ #define PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Pos (0UL) /*!< PLLDIG RF_MSKMOD_CHIPL_REG: MSK_CHIPL (Bit 0) */ @@ -8962,6 +9193,12 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Pos (0UL) /*!< PLLDIG RF_MSKMOD_CHIPH_REG: MSK_CHIPH (Bit 0) */ #define PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Msk (0xffffUL) /*!< PLLDIG RF_MSKMOD_CHIPH_REG: MSK_CHIPH (Bitfield-Mask: 0xffff) */ +/* -------------------------- PLLDIG_RF_TXDAC_TEST_REG -------------------------- */ +#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Pos (0UL) /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_WR (Bit 0) */ +#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Msk (0xffUL) /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_WR (Bitfield-Mask: 0xff) */ +#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Pos (8UL) /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_SEL (Bit 8) */ +#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Msk (0x100UL) /*!< PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_SEL (Bitfield-Mask: 0x01) */ + /* ------------------------ PLLDIG_RF_MGAIN_COMP_VAL0_REG ----------------------- */ #define PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL0_REG: MGAIN_COMP_VAL (Bit 0) */ #define PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL0_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ @@ -8990,6 +9227,52 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL6_REG: MGAIN_COMP_VAL (Bit 0) */ #define PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL6_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ +/* ------------------------ PLLDIG_RF_MGAIN_COMP_VAL7_REG ----------------------- */ +#define PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Pos (0UL) /*!< PLLDIG RF_MGAIN_COMP_VAL7_REG: MGAIN_COMP_VAL (Bit 0) */ +#define PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Msk (0x1fUL) /*!< PLLDIG RF_MGAIN_COMP_VAL7_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f) */ + +/* -------------------------- PLLDIG_RF_PULSE_TBL_0_REG ------------------------- */ +#define PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_0_REG: FTDF_PULSE_VAL (Bit 0) */ +#define PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_0_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ + +/* -------------------------- PLLDIG_RF_PULSE_TBL_1_REG ------------------------- */ +#define PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_1_REG: FTDF_PULSE_VAL (Bit 0) */ +#define PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_1_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ + +/* -------------------------- PLLDIG_RF_PULSE_TBL_2_REG ------------------------- */ +#define PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_2_REG: FTDF_PULSE_VAL (Bit 0) */ +#define PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_2_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ + +/* -------------------------- PLLDIG_RF_PULSE_TBL_3_REG ------------------------- */ +#define PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_3_REG: FTDF_PULSE_VAL (Bit 0) */ +#define PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_3_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ + +/* -------------------------- PLLDIG_RF_PULSE_TBL_4_REG ------------------------- */ +#define PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_4_REG: FTDF_PULSE_VAL (Bit 0) */ +#define PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_4_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ + +/* -------------------------- PLLDIG_RF_PULSE_TBL_5_REG ------------------------- */ +#define PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_5_REG: FTDF_PULSE_VAL (Bit 0) */ +#define PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_5_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ + +/* -------------------------- PLLDIG_RF_PULSE_TBL_6_REG ------------------------- */ +#define PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_6_REG: FTDF_PULSE_VAL (Bit 0) */ +#define PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_6_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ + +/* -------------------------- PLLDIG_RF_PULSE_TBL_7_REG ------------------------- */ +#define PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Pos (0UL) /*!< PLLDIG RF_PULSE_TBL_7_REG: FTDF_PULSE_VAL (Bit 0) */ +#define PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Msk (0x7ffUL) /*!< PLLDIG RF_PULSE_TBL_7_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff) */ + +/* -------------------------- PLLDIG_RF_PULSE_CTRL_REG -------------------------- */ +#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Pos (0UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_SEL (Bit 0) */ +#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Msk (0x1UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_SEL (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Pos (1UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GATE (Bit 1) */ +#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Msk (0x6UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GATE (Bitfield-Mask: 0x03) */ +#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Pos (3UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_LOWPASS_EN (Bit 3) */ +#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Msk (0x8UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_LOWPASS_EN (Bitfield-Mask: 0x01) */ +#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Pos (4UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GAIN (Bit 4) */ +#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Msk (0xf0UL) /*!< PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GAIN (Bitfield-Mask: 0x0f) */ + /* ================================================================================ */ /* ================ struct 'QSPIC' Position & Mask ================ */ @@ -9278,6 +9561,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Pos (3UL) /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_3 (Bit 3) */ #define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Msk (0x8UL) /*!< RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_3 (Bitfield-Mask: 0x01) */ +/* -------------------------- RFCU_RF_AGC_EXT1_LUT_REG -------------------------- */ +#define RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Pos (0UL) /*!< RFCU RF_AGC_EXT1_LUT_REG: AGC_EXT_LUT (Bit 0) */ +#define RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Msk (0x3ffUL) /*!< RFCU RF_AGC_EXT1_LUT_REG: AGC_EXT_LUT (Bitfield-Mask: 0x3ff) */ + /* ---------------------------- RFCU_RF_CALSTATE_REG ---------------------------- */ #define RFCU_RF_CALSTATE_REG_CALSTATE_Pos (0UL) /*!< RFCU RF_CALSTATE_REG: CALSTATE (Bit 0) */ #define RFCU_RF_CALSTATE_REG_CALSTATE_Msk (0xfUL) /*!< RFCU RF_CALSTATE_REG: CALSTATE (Bitfield-Mask: 0x0f) */ @@ -9337,10 +9624,12 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk (0x2UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_XTAL_PLL_DXTAL16_TEST (Bitfield-Mask: 0x01) */ #define RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos (2UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_VTUNE_TO_ADC_TEST_EN (Bit 2) */ #define RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk (0x4UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_VTUNE_TO_ADC_TEST_EN (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_BLE_REG_RFCU_TXRX_EN_OLD_Pos (7UL) /*!< RFCU RF_SPARE1_BLE_REG: RFCU_TXRX_EN_OLD (Bit 7) */ -#define RFCU_RF_SPARE1_BLE_REG_RFCU_TXRX_EN_OLD_Msk (0x80UL) /*!< RFCU RF_SPARE1_BLE_REG: RFCU_TXRX_EN_OLD (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_BLE_REG_VCO_AMPL_SET_TX_Pos (8UL) /*!< RFCU RF_SPARE1_BLE_REG: VCO_AMPL_SET_TX (Bit 8) */ -#define RFCU_RF_SPARE1_BLE_REG_VCO_AMPL_SET_TX_Msk (0xff00UL) /*!< RFCU RF_SPARE1_BLE_REG: VCO_AMPL_SET_TX (Bitfield-Mask: 0xff) */ +#define RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Pos (3UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_TXDAC_CLK_POL_SEL (Bit 3) */ +#define RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Msk (0x8UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_TXDAC_CLK_POL_SEL (Bitfield-Mask: 0x01) */ +#define RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Pos (4UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_GDAC_CUR_SET (Bit 4) */ +#define RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Msk (0x30UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_GDAC_CUR_SET (Bitfield-Mask: 0x03) */ +#define RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Pos (6UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_SPARE_REG (Bit 6) */ +#define RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Msk (0xffc0UL) /*!< RFCU RF_SPARE1_BLE_REG: RF_SPARE_REG (Bitfield-Mask: 0x3ff) */ /* --------------------------- RFCU_RF_SPARE1_FTDF_REG -------------------------- */ #define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Pos (0UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_XTAL_RFCLK_TEST (Bit 0) */ @@ -9349,14 +9638,12 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk (0x2UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_XTAL_PLL_DXTAL16_TEST (Bitfield-Mask: 0x01) */ #define RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos (2UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_VTUNE_TO_ADC_TEST_EN (Bit 2) */ #define RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk (0x4UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_VTUNE_TO_ADC_TEST_EN (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_FTDF_REG_DEM_AFC_ACTIVATION_MODE_Pos (11UL) /*!< RFCU RF_SPARE1_FTDF_REG: DEM_AFC_ACTIVATION_MODE (Bit 11) */ -#define RFCU_RF_SPARE1_FTDF_REG_DEM_AFC_ACTIVATION_MODE_Msk (0x800UL) /*!< RFCU RF_SPARE1_FTDF_REG: DEM_AFC_ACTIVATION_MODE (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_FTDF_REG_VCO_COARSECAL_DELAY_Pos (12UL) /*!< RFCU RF_SPARE1_FTDF_REG: VCO_COARSECAL_DELAY (Bit 12) */ -#define RFCU_RF_SPARE1_FTDF_REG_VCO_COARSECAL_DELAY_Msk (0x3000UL) /*!< RFCU RF_SPARE1_FTDF_REG: VCO_COARSECAL_DELAY (Bitfield-Mask: 0x03) */ -#define RFCU_RF_SPARE1_FTDF_REG_DEM_PAD_WRAP_Pos (14UL) /*!< RFCU RF_SPARE1_FTDF_REG: DEM_PAD_WRAP (Bit 14) */ -#define RFCU_RF_SPARE1_FTDF_REG_DEM_PAD_WRAP_Msk (0x4000UL) /*!< RFCU RF_SPARE1_FTDF_REG: DEM_PAD_WRAP (Bitfield-Mask: 0x01) */ -#define RFCU_RF_SPARE1_FTDF_REG_DEM_PAD_SAT_TO_ZERO_Pos (15UL) /*!< RFCU RF_SPARE1_FTDF_REG: DEM_PAD_SAT_TO_ZERO (Bit 15) */ -#define RFCU_RF_SPARE1_FTDF_REG_DEM_PAD_SAT_TO_ZERO_Msk (0x8000UL) /*!< RFCU RF_SPARE1_FTDF_REG: DEM_PAD_SAT_TO_ZERO (Bitfield-Mask: 0x01) */ +#define RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Pos (3UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_TXDAC_CLK_POL_SEL (Bit 3) */ +#define RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Msk (0x8UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_TXDAC_CLK_POL_SEL (Bitfield-Mask: 0x01) */ +#define RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Pos (4UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_GDAC_CUR_SET (Bit 4) */ +#define RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Msk (0x30UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_GDAC_CUR_SET (Bitfield-Mask: 0x03) */ +#define RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Pos (6UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_SPARE_REG (Bit 6) */ +#define RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Msk (0xffc0UL) /*!< RFCU RF_SPARE1_FTDF_REG: RF_SPARE_REG (Bitfield-Mask: 0x3ff) */ /* ------------------------- RFCU_RF_BIAS_CTRL1_BLE_REG ------------------------- */ #define RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Pos (0UL) /*!< RFCU RF_BIAS_CTRL1_BLE_REG: MIX_BIAS_BLE_SET (Bit 0) */ @@ -9415,8 +9702,12 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Msk (0xff00UL) /*!< RFCU RF_ADC_CTRL3_REG: ADC_OFFN_Q_WR (Bitfield-Mask: 0xff) */ /* ----------------------------- RFCU_RF_PA_CTRL_REG ---------------------------- */ -#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_Pos (5UL) /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED (Bit 5) */ -#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_Msk (0x60UL) /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED (Bitfield-Mask: 0x03) */ +#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Pos (5UL) /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_DOWN (Bit 5) */ +#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Msk (0x60UL) /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_DOWN (Bitfield-Mask: 0x03) */ +#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Pos (7UL) /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_UP (Bit 7) */ +#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Msk (0x180UL) /*!< RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_UP (Bitfield-Mask: 0x03) */ +#define RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Pos (9UL) /*!< RFCU RF_PA_CTRL_REG: PA_FAST_DISCHARGE_EN (Bit 9) */ +#define RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Msk (0x200UL) /*!< RFCU RF_PA_CTRL_REG: PA_FAST_DISCHARGE_EN (Bitfield-Mask: 0x01) */ #define RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Pos (11UL) /*!< RFCU RF_PA_CTRL_REG: LEVEL_LDO_RFPA (Bit 11) */ #define RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Msk (0x7800UL) /*!< RFCU RF_PA_CTRL_REG: LEVEL_LDO_RFPA (Bitfield-Mask: 0x0f) */ @@ -9511,20 +9802,24 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Msk (0xf000UL) /*!< RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_SPARE (Bitfield-Mask: 0x0f) */ /* --------------------------- RFCU_RF_MIXER_CTRL2_REG -------------------------- */ -#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_Pos (0UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR (Bit 0) */ -#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_Msk (0x1fUL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Pos (0UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_BLE (Bit 0) */ +#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Msk (0x1fUL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f) */ #define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Pos (5UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_SELECT (Bit 5) */ #define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Msk (0x20UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_SELECT (Bitfield-Mask: 0x01) */ +#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Pos (6UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_FTDF (Bit 6) */ +#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Msk (0x7c0UL) /*!< RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f) */ /* ----------------------------- RFCU_RF_LF_CTRL_REG ---------------------------- */ -#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_Pos (0UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR (Bit 0) */ -#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_Msk (0x1fUL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Pos (0UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_BLE (Bit 0) */ +#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Msk (0x1fUL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f) */ #define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Pos (5UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_SEL (Bit 5) */ #define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Msk (0x20UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_SEL (Bitfield-Mask: 0x01) */ #define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Pos (6UL) /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_BLE (Bit 6) */ #define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Msk (0x40UL) /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_BLE (Bitfield-Mask: 0x01) */ #define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Pos (7UL) /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_FTDF (Bit 7) */ #define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Msk (0x80UL) /*!< RFCU RF_LF_CTRL_REG: LF_SHORT_R4_FTDF (Bitfield-Mask: 0x01) */ +#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Pos (8UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_FTDF (Bit 8) */ +#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Msk (0x1f00UL) /*!< RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f) */ /* ---------------------------- RFCU_RF_TDC_CTRL_REG ---------------------------- */ #define RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Pos (0UL) /*!< RFCU RF_TDC_CTRL_REG: CTRL_FAST (Bit 0) */ @@ -9560,9 +9855,19 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Pos (0UL) /*!< RFCU RF_LNA_CTRL3_REG: LNA_TRIM_CGS (Bit 0) */ #define RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Msk (0x1fUL) /*!< RFCU RF_LNA_CTRL3_REG: LNA_TRIM_CGS (Bitfield-Mask: 0x1f) */ -/* ----------------------------- RFCU_RF_TX_PWR_REG ----------------------------- */ -#define RFCU_RF_TX_PWR_REG_TX_POWER_SET_Pos (0UL) /*!< RFCU RF_TX_PWR_REG: TX_POWER_SET (Bit 0) */ -#define RFCU_RF_TX_PWR_REG_TX_POWER_SET_Msk (0x7UL) /*!< RFCU RF_TX_PWR_REG: TX_POWER_SET (Bitfield-Mask: 0x07) */ +/* -------------------------- RFCU_RF_VCO_AMP_CTRL1_REG ------------------------- */ +#define RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Pos (0UL) /*!< RFCU RF_VCO_AMP_CTRL1_REG: VCO_AMPL_MODE (Bit 0) */ +#define RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Msk (0x7fUL) /*!< RFCU RF_VCO_AMP_CTRL1_REG: VCO_AMPL_MODE (Bitfield-Mask: 0x7f) */ + +/* -------------------------- RFCU_RF_VCO_AMP_CTRL2_REG ------------------------- */ +#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Pos (0UL) /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_TX (Bit 0) */ +#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Msk (0xffUL) /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_TX (Bitfield-Mask: 0xff) */ +#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Pos (8UL) /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_RX (Bit 8) */ +#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Msk (0xff00UL) /*!< RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_RX (Bitfield-Mask: 0xff) */ + +/* --------------------------- RFCU_RF_TX_PWR_BLE_REG --------------------------- */ +#define RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Pos (0UL) /*!< RFCU RF_TX_PWR_BLE_REG: TX_POWER_SET (Bit 0) */ +#define RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Msk (0x7UL) /*!< RFCU RF_TX_PWR_BLE_REG: TX_POWER_SET (Bitfield-Mask: 0x07) */ /* -------------------------- RFCU_RF_TX_PWR_LUT_1_REG -------------------------- */ #define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ @@ -9571,6 +9876,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ #define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ #define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ +#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ /* -------------------------- RFCU_RF_TX_PWR_LUT_2_REG -------------------------- */ #define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ @@ -9579,6 +9886,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ #define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ #define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ +#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ /* -------------------------- RFCU_RF_TX_PWR_LUT_3_REG -------------------------- */ #define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ @@ -9587,6 +9896,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ #define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ #define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ +#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ /* -------------------------- RFCU_RF_TX_PWR_LUT_4_REG -------------------------- */ #define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ @@ -9595,6 +9906,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ #define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ #define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ +#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ /* -------------------------- RFCU_RF_TX_PWR_LUT_5_REG -------------------------- */ #define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ @@ -9603,14 +9916,8 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ #define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ #define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ - -/* -------------------------- RFCU_RF_TX_PWR_LUT_7_REG -------------------------- */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ -#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ +#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ /* -------------------------- RFCU_RF_TX_PWR_LUT_6_REG -------------------------- */ #define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ @@ -9619,10 +9926,26 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ #define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ #define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ +#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ + +/* -------------------------- RFCU_RF_TX_PWR_LUT_7_REG -------------------------- */ +#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0) */ +#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Msk (0x3UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03) */ +#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Pos (2UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2) */ +#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Msk (0x3cUL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f) */ +#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos (6UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6) */ +#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk (0x7c0UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos (11UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11) */ +#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk (0x800UL) /*!< RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01) */ + +/* --------------------------- RFCU_RF_TX_PWR_FTDF_REG -------------------------- */ +#define RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Pos (0UL) /*!< RFCU RF_TX_PWR_FTDF_REG: TX_POWER_SET (Bit 0) */ +#define RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Msk (0x7UL) /*!< RFCU RF_TX_PWR_FTDF_REG: TX_POWER_SET (Bitfield-Mask: 0x07) */ /* -------------------------- RFCU_RF_TX_PWR_LUT_RD_REG ------------------------- */ #define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Pos (0UL) /*!< RFCU RF_TX_PWR_LUT_RD_REG: RF_TX_PWR_LUT_RD (Bit 0) */ -#define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Msk (0x7ffUL) /*!< RFCU RF_TX_PWR_LUT_RD_REG: RF_TX_PWR_LUT_RD (Bitfield-Mask: 0x7ff) */ +#define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Msk (0xfffUL) /*!< RFCU RF_TX_PWR_LUT_RD_REG: RF_TX_PWR_LUT_RD (Bitfield-Mask: 0xfff) */ /* ---------------------------- RFCU_RF_DIV_IQ_RX_REG --------------------------- */ #define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Pos (0UL) /*!< RFCU RF_DIV_IQ_RX_REG: DIV2_OFFN_TRIM_RX (Bit 0) */ @@ -9645,8 +9968,20 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Msk (0xffffUL) /*!< RFCU RF_LO_IQ_TRIM_REG: RF_LO_IQ_TRIM (Bitfield-Mask: 0xffff) */ /* --------------------------- RFCU_RF_TXDAC_CTRL_REG --------------------------- */ -#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAP_SEL_Pos (0UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAP_SEL (Bit 0) */ -#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAP_SEL_Msk (0xfUL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAP_SEL (Bitfield-Mask: 0x0f) */ +#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Pos (0UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_BLE (Bit 0) */ +#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Msk (0x1fUL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Pos (5UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_SEL (Bit 5) */ +#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Msk (0x20UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_SEL (Bitfield-Mask: 0x01) */ +#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Pos (6UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_FIXED_CAP_ON (Bit 6) */ +#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Msk (0x40UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_FIXED_CAP_ON (Bitfield-Mask: 0x01) */ +#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Pos (7UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_FTDF (Bit 7) */ +#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Msk (0xf80UL) /*!< RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f) */ + +/* ----------------------- RFCU_RF_TXDAC_CAL_CAP_STAT_REG ----------------------- */ +#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Pos (0UL) /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_CAL_CAP_RD (Bit 0) */ +#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Msk (0x1fUL) /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_CAL_CAP_RD (Bitfield-Mask: 0x1f) */ +#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Pos (5UL) /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_FIXED_CAP_ON_RD (Bit 5) */ +#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Msk (0x20UL) /*!< RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_FIXED_CAP_ON_RD (Bitfield-Mask: 0x01) */ /* --------------------------- RFCU_RF_IFF_RESULT_REG --------------------------- */ #define RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Pos (0UL) /*!< RFCU RF_IFF_RESULT_REG: IF_CAL_CAP_RD (Bit 0) */ @@ -9688,143 +10023,143 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /* ================================================================================ */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG0_BLE_REG -------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_BLE_REG_lna_ldo_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_BLE_REG: lna_ldo_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_BLE_REG_lna_ldo_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_BLE_REG: lna_ldo_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_BLE_REG_lna_ldo_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_BLE_REG: lna_ldo_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_BLE_REG_lna_ldo_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_BLE_REG: lna_ldo_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG0_REG ---------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG1_BLE_REG -------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_BLE_REG_lna_core_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_BLE_REG: lna_core_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_BLE_REG_lna_core_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_BLE_REG: lna_core_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_BLE_REG_lna_core_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_BLE_REG: lna_core_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_BLE_REG_lna_core_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_BLE_REG: lna_core_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG1_REG ---------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG2_BLE_REG -------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_BLE_REG_lna_cgm_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_BLE_REG: lna_cgm_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_BLE_REG_lna_cgm_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_BLE_REG: lna_cgm_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_BLE_REG_lna_cgm_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_BLE_REG: lna_cgm_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_BLE_REG_lna_cgm_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_BLE_REG: lna_cgm_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG2_REG ---------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG3_BLE_REG -------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_BLE_REG_mix_ldo_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_BLE_REG: mix_ldo_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_BLE_REG_mix_ldo_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_BLE_REG: mix_ldo_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_BLE_REG_mix_ldo_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_BLE_REG: mix_ldo_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_BLE_REG_mix_ldo_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_BLE_REG: mix_ldo_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG3_REG ---------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG4_BLE_REG -------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_BLE_REG_iff_ldo_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_BLE_REG: iff_ldo_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_BLE_REG_iff_ldo_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_BLE_REG: iff_ldo_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_BLE_REG_iff_ldo_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_BLE_REG: iff_ldo_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_BLE_REG_iff_ldo_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_BLE_REG: iff_ldo_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG4_REG ---------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG5_BLE_REG -------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_BLE_REG_iffadc_ldo_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_BLE_REG: iffadc_ldo_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_BLE_REG_iffadc_ldo_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_BLE_REG: iffadc_ldo_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_BLE_REG_iffadc_ldo_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_BLE_REG: iffadc_ldo_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_BLE_REG_iffadc_ldo_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_BLE_REG: iffadc_ldo_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG5_REG ---------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG6_BLE_REG -------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_BLE_REG_vco_ldo_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_BLE_REG: vco_ldo_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_BLE_REG_vco_ldo_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_BLE_REG: vco_ldo_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_BLE_REG_vco_ldo_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_BLE_REG: vco_ldo_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_BLE_REG_vco_ldo_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_BLE_REG: vco_ldo_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG6_REG ---------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG7_BLE_REG -------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_BLE_REG_md_ldo_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_BLE_REG: md_ldo_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_BLE_REG_md_ldo_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_BLE_REG: md_ldo_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_BLE_REG_md_ldo_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_BLE_REG: md_ldo_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_BLE_REG_md_ldo_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_BLE_REG: md_ldo_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG7_REG ---------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG8_BLE_REG -------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_BLE_REG_pfd_ldo_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_BLE_REG: pfd_ldo_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_BLE_REG_pfd_ldo_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_BLE_REG: pfd_ldo_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_BLE_REG_pfd_ldo_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_BLE_REG: pfd_ldo_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_BLE_REG_pfd_ldo_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_BLE_REG: pfd_ldo_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG8_REG ---------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG9_BLE_REG -------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_BLE_REG_pa_ldo_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_BLE_REG: pa_ldo_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_BLE_REG_pa_ldo_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_BLE_REG: pa_ldo_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_BLE_REG_pa_ldo_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_BLE_REG: pa_ldo_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_BLE_REG_pa_ldo_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_BLE_REG: pa_ldo_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG9_REG ---------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG10_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_BLE_REG_cp_switch_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_BLE_REG: cp_switch_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_BLE_REG_cp_switch_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_BLE_REG: cp_switch_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_BLE_REG_cp_switch_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_BLE_REG: cp_switch_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_BLE_REG_cp_switch_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_BLE_REG: cp_switch_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG10_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG11_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_BLE_REG_vco_bias_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_BLE_REG: vco_bias_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_BLE_REG_vco_bias_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_BLE_REG: vco_bias_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_BLE_REG_vco_bias_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_BLE_REG: vco_bias_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_BLE_REG_vco_bias_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_BLE_REG: vco_bias_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG11_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG12_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_BLE_REG_cp_bias_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_BLE_REG: cp_bias_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_BLE_REG_cp_bias_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_BLE_REG: cp_bias_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_BLE_REG_cp_bias_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_BLE_REG: cp_bias_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_BLE_REG_cp_bias_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_BLE_REG: cp_bias_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG12_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG13_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_BLE_REG_lna_ldo_zero_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_BLE_REG: lna_ldo_zero_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_BLE_REG_lna_ldo_zero_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_BLE_REG: lna_ldo_zero_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_BLE_REG_lna_ldo_zero_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_BLE_REG: lna_ldo_zero_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_BLE_REG_lna_ldo_zero_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_BLE_REG: lna_ldo_zero_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG13_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG14_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_BLE_REG_pa_ramp_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_BLE_REG: pa_ramp_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_BLE_REG_pa_ramp_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_BLE_REG: pa_ramp_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_BLE_REG_pa_ramp_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_BLE_REG: pa_ramp_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_BLE_REG_pa_ramp_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_BLE_REG: pa_ramp_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG14_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG15_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_BLE_REG_pa_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_BLE_REG: pa_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_BLE_REG_pa_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_BLE_REG: pa_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_BLE_REG_pa_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_BLE_REG: pa_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_BLE_REG_pa_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_BLE_REG: pa_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG15_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG16_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_BLE_REG_mix_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_BLE_REG: mix_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_BLE_REG_mix_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_BLE_REG: mix_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_BLE_REG_mix_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_BLE_REG: mix_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_BLE_REG_mix_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_BLE_REG: mix_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG16_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG17_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_BLE_REG_iff_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_BLE_REG: iff_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_BLE_REG_iff_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_BLE_REG: iff_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_BLE_REG_iff_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_BLE_REG: iff_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_BLE_REG_iff_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_BLE_REG: iff_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG17_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG18_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_BLE_REG_adc_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_BLE_REG: adc_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_BLE_REG_adc_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_BLE_REG: adc_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_BLE_REG_adc_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_BLE_REG: adc_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_BLE_REG_adc_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_BLE_REG: adc_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG18_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG19_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_BLE_REG_vco_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_BLE_REG: vco_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_BLE_REG_vco_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_BLE_REG: vco_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_BLE_REG_vco_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_BLE_REG: vco_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_BLE_REG_vco_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_BLE_REG: vco_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG19_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG20_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_BLE_REG_lobuf_md_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_BLE_REG: lobuf_md_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_BLE_REG_lobuf_md_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_BLE_REG: lobuf_md_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_BLE_REG_lobuf_md_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_BLE_REG: lobuf_md_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_BLE_REG_lobuf_md_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_BLE_REG: lobuf_md_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG20_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG21_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_BLE_REG_cp_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_BLE_REG: cp_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_BLE_REG_cp_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_BLE_REG: cp_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_BLE_REG_cp_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_BLE_REG: cp_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_BLE_REG_cp_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_BLE_REG: cp_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG21_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG22_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_BLE_REG_pfd_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_BLE_REG: pfd_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_BLE_REG_pfd_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_BLE_REG: pfd_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_BLE_REG_pfd_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_BLE_REG: pfd_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_BLE_REG_pfd_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_BLE_REG: pfd_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG22_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_tx (Bitfield-Mask: 0x1f) */ /* -------------------- RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG ------------------- */ #define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_rx (Bit 0) */ @@ -9838,41 +10173,41 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG25_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_BLE_REG_lobuf_pa_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_BLE_REG: lobuf_pa_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_BLE_REG_lobuf_pa_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_BLE_REG: lobuf_pa_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_BLE_REG_lobuf_pa_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_BLE_REG: lobuf_pa_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_BLE_REG_lobuf_pa_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_BLE_REG: lobuf_pa_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG25_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG26_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_BLE_REG_lobuf_rxiq_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_BLE_REG: lobuf_rxiq_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_BLE_REG_lobuf_rxiq_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_BLE_REG: lobuf_rxiq_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_BLE_REG_lobuf_rxiq_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_BLE_REG: lobuf_rxiq_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_BLE_REG_lobuf_rxiq_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_BLE_REG: lobuf_rxiq_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG26_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG27_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_BLE_REG_div2_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_BLE_REG: div2_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_BLE_REG_div2_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_BLE_REG: div2_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_BLE_REG_div2_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_BLE_REG: div2_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_BLE_REG_div2_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_BLE_REG: div2_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG27_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG28_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_BLE_REG_cp_bias_sh_open_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_BLE_REG: cp_bias_sh_open_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_BLE_REG_cp_bias_sh_open_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_BLE_REG: cp_bias_sh_open_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_BLE_REG_cp_bias_sh_open_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_BLE_REG: cp_bias_sh_open_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_BLE_REG_cp_bias_sh_open_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_BLE_REG: cp_bias_sh_open_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG28_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG29_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_BLE_REG_vco_bias_sh_open_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_BLE_REG: vco_bias_sh_open_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_BLE_REG_vco_bias_sh_open_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_BLE_REG: vco_bias_sh_open_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_BLE_REG_vco_bias_sh_open_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_BLE_REG: vco_bias_sh_open_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_BLE_REG_vco_bias_sh_open_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_BLE_REG: vco_bias_sh_open_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG29_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG30_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_BLE_REG_iffmix_bias_sh_open_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_BLE_REG: iffmix_bias_sh_open_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_BLE_REG_iffmix_bias_sh_open_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_BLE_REG: iffmix_bias_sh_open_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_BLE_REG_iffmix_bias_sh_open_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_BLE_REG: iffmix_bias_sh_open_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_BLE_REG_iffmix_bias_sh_open_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_BLE_REG: iffmix_bias_sh_open_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG30_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f) */ /* -------------------- RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG ------------------- */ #define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_rx (Bit 0) */ @@ -9880,23 +10215,23 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG32_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_BLE_REG_mix_bias_sh_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_BLE_REG: mix_bias_sh_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_BLE_REG_mix_bias_sh_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_BLE_REG: mix_bias_sh_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_BLE_REG_mix_bias_sh_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_BLE_REG: mix_bias_sh_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_BLE_REG_mix_bias_sh_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_BLE_REG: mix_bias_sh_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG32_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG33_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_BLE_REG_pll_dig_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_BLE_REG: pll_dig_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_BLE_REG_pll_dig_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_BLE_REG: pll_dig_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_BLE_REG_pll_dig_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_BLE_REG: pll_dig_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_BLE_REG_pll_dig_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_BLE_REG: pll_dig_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG33_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG34_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_BLE_REG_pllclosed_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_BLE_REG: pllclosed_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_BLE_REG_pllclosed_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_BLE_REG: pllclosed_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_BLE_REG_pllclosed_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_BLE_REG: pllclosed_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_BLE_REG_pllclosed_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_BLE_REG: pllclosed_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG34_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_tx (Bitfield-Mask: 0x1f) */ /* -------------------- RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG ------------------- */ #define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_rx (Bit 0) */ @@ -9904,11 +10239,11 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG36_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_BLE_REG_ldo_zero_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_BLE_REG: ldo_zero_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_BLE_REG_ldo_zero_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_BLE_REG: ldo_zero_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_BLE_REG_ldo_zero_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_BLE_REG: ldo_zero_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_BLE_REG_ldo_zero_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_BLE_REG: ldo_zero_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG36_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_tx (Bitfield-Mask: 0x1f) */ /* -------------------- RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG ------------------- */ #define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_rx (Bit 0) */ @@ -9922,35 +10257,35 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG39_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_BLE_REG_ldo_rfio_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_BLE_REG: ldo_rfio_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_BLE_REG_ldo_rfio_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_BLE_REG: ldo_rfio_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_BLE_REG_ldo_rfio_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_BLE_REG: ldo_rfio_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_BLE_REG_ldo_rfio_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_BLE_REG: ldo_rfio_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG39_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG40_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_BLE_REG_rfio_bias_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_BLE_REG: rfio_bias_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_BLE_REG_rfio_bias_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_BLE_REG: rfio_bias_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_BLE_REG_rfio_bias_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_BLE_REG: rfio_bias_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_BLE_REG_rfio_bias_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_BLE_REG: rfio_bias_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG40_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG41_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_BLE_REG_rfio_bias_sh_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_BLE_REG: rfio_bias_sh_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_BLE_REG_rfio_bias_sh_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_BLE_REG: rfio_bias_sh_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_BLE_REG_rfio_bias_sh_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_BLE_REG: rfio_bias_sh_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_BLE_REG_rfio_bias_sh_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_BLE_REG: rfio_bias_sh_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG41_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG42_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_BLE_REG_ldo_radio_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_BLE_REG: ldo_radio_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_BLE_REG_ldo_radio_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_BLE_REG: ldo_radio_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_BLE_REG_ldo_radio_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_BLE_REG: ldo_radio_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_BLE_REG_ldo_radio_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_BLE_REG: ldo_radio_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG42_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG43_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_BLE_REG_adc_clk_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_BLE_REG: adc_clk_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_BLE_REG_adc_clk_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_BLE_REG: adc_clk_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_BLE_REG_adc_clk_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_BLE_REG: adc_clk_en_ble_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_BLE_REG_adc_clk_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_BLE_REG: adc_clk_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ +/* ---------------------- RFCU_POWER_RF_ENABLE_CONFIG43_REG --------------------- */ +#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_tx (Bit 5) */ +#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_tx (Bitfield-Mask: 0x1f) */ /* -------------------- RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG ------------------- */ #define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_rx (Bit 0) */ @@ -9965,20 +10300,20 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ /* -------------------- RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dcparcal_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: dcparcal_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dcparcal_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: dcparcal_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: dem_dcparcal_en_ble_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: dem_dcparcal_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ #define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: spare2_en_ble_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: spare2_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ /* -------------------- RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_agcunfreeze_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: agcunfreeze_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_agcunfreeze_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: agcunfreeze_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: dem_agcunfreeze_en_ble_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: dem_agcunfreeze_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ #define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: spare3_en_ble_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: spare3_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ /* -------------------- RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_sigdetect_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: sigdetect_en_ble_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_sigdetect_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: sigdetect_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: dem_sigdetect_en_ble_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: dem_sigdetect_en_ble_dcf_rx (Bitfield-Mask: 0x1f) */ #define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: spare4_en_ble_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: spare4_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ @@ -9988,144 +10323,6 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_tx (Bitfield-Mask: 0x1f) */ -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG0_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_FTDF_REG_lna_ldo_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_FTDF_REG: lna_ldo_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_FTDF_REG_lna_ldo_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_FTDF_REG: lna_ldo_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_FTDF_REG_lna_ldo_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_FTDF_REG: lna_ldo_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG0_FTDF_REG_lna_ldo_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG0_FTDF_REG: lna_ldo_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG1_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_FTDF_REG_lna_core_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_FTDF_REG: lna_core_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_FTDF_REG_lna_core_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_FTDF_REG: lna_core_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_FTDF_REG_lna_core_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_FTDF_REG: lna_core_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG1_FTDF_REG_lna_core_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG1_FTDF_REG: lna_core_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG2_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_FTDF_REG_lna_cgm_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_FTDF_REG: lna_cgm_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_FTDF_REG_lna_cgm_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_FTDF_REG: lna_cgm_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_FTDF_REG_lna_cgm_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_FTDF_REG: lna_cgm_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG2_FTDF_REG_lna_cgm_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG2_FTDF_REG: lna_cgm_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG3_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_FTDF_REG_mix_ldo_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_FTDF_REG: mix_ldo_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_FTDF_REG_mix_ldo_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_FTDF_REG: mix_ldo_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_FTDF_REG_mix_ldo_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_FTDF_REG: mix_ldo_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG3_FTDF_REG_mix_ldo_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG3_FTDF_REG: mix_ldo_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG4_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_FTDF_REG_iff_ldo_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_FTDF_REG: iff_ldo_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_FTDF_REG_iff_ldo_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_FTDF_REG: iff_ldo_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_FTDF_REG_iff_ldo_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_FTDF_REG: iff_ldo_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG4_FTDF_REG_iff_ldo_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG4_FTDF_REG: iff_ldo_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG5_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_FTDF_REG_iffadc_ldo_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_FTDF_REG: iffadc_ldo_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_FTDF_REG_iffadc_ldo_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_FTDF_REG: iffadc_ldo_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_FTDF_REG_iffadc_ldo_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_FTDF_REG: iffadc_ldo_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG5_FTDF_REG_iffadc_ldo_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG5_FTDF_REG: iffadc_ldo_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG6_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_FTDF_REG_vco_ldo_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_FTDF_REG: vco_ldo_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_FTDF_REG_vco_ldo_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_FTDF_REG: vco_ldo_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_FTDF_REG_vco_ldo_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_FTDF_REG: vco_ldo_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG6_FTDF_REG_vco_ldo_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG6_FTDF_REG: vco_ldo_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG7_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_FTDF_REG_md_ldo_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_FTDF_REG: md_ldo_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_FTDF_REG_md_ldo_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_FTDF_REG: md_ldo_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_FTDF_REG_md_ldo_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_FTDF_REG: md_ldo_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG7_FTDF_REG_md_ldo_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG7_FTDF_REG: md_ldo_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG8_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_FTDF_REG_pfd_ldo_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_FTDF_REG: pfd_ldo_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_FTDF_REG_pfd_ldo_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_FTDF_REG: pfd_ldo_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_FTDF_REG_pfd_ldo_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_FTDF_REG: pfd_ldo_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG8_FTDF_REG_pfd_ldo_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG8_FTDF_REG: pfd_ldo_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* -------------------- RFCU_POWER_RF_ENABLE_CONFIG9_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_FTDF_REG_pa_ldo_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_FTDF_REG: pa_ldo_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_FTDF_REG_pa_ldo_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_FTDF_REG: pa_ldo_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_FTDF_REG_pa_ldo_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_FTDF_REG: pa_ldo_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG9_FTDF_REG_pa_ldo_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG9_FTDF_REG: pa_ldo_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG10_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_FTDF_REG_cp_switch_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_FTDF_REG: cp_switch_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_FTDF_REG_cp_switch_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_FTDF_REG: cp_switch_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_FTDF_REG_cp_switch_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_FTDF_REG: cp_switch_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG10_FTDF_REG_cp_switch_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG10_FTDF_REG: cp_switch_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG11_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_FTDF_REG_vco_bias_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_FTDF_REG: vco_bias_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_FTDF_REG_vco_bias_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_FTDF_REG: vco_bias_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_FTDF_REG_vco_bias_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_FTDF_REG: vco_bias_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG11_FTDF_REG_vco_bias_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG11_FTDF_REG: vco_bias_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG12_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_FTDF_REG_cp_bias_en_tfdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_FTDF_REG: cp_bias_en_tfdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_FTDF_REG_cp_bias_en_tfdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_FTDF_REG: cp_bias_en_tfdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_FTDF_REG_cp_bias_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_FTDF_REG: cp_bias_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG12_FTDF_REG_cp_bias_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG12_FTDF_REG: cp_bias_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG13_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_FTDF_REG_lna_ldo_zero_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_FTDF_REG: lna_ldo_zero_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_FTDF_REG_lna_ldo_zero_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_FTDF_REG: lna_ldo_zero_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_FTDF_REG_lna_ldo_zero_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_FTDF_REG: lna_ldo_zero_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG13_FTDF_REG_lna_ldo_zero_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG13_FTDF_REG: lna_ldo_zero_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG14_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_FTDF_REG_pa_ramp_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_FTDF_REG: pa_ramp_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_FTDF_REG_pa_ramp_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_FTDF_REG: pa_ramp_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_FTDF_REG_pa_ramp_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_FTDF_REG: pa_ramp_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG14_FTDF_REG_pa_ramp_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG14_FTDF_REG: pa_ramp_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG15_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_FTDF_REG_pa_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_FTDF_REG: pa_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_FTDF_REG_pa_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_FTDF_REG: pa_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_FTDF_REG_pa_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_FTDF_REG: pa_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG15_FTDF_REG_pa_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG15_FTDF_REG: pa_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG16_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_FTDF_REG_mix_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_FTDF_REG: mix_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_FTDF_REG_mix_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_FTDF_REG: mix_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_FTDF_REG_mix_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_FTDF_REG: mix_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG16_FTDF_REG_mix_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG16_FTDF_REG: mix_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG17_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_FTDF_REG_iff_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_FTDF_REG: iff_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_FTDF_REG_iff_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_FTDF_REG: iff_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_FTDF_REG_iff_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_FTDF_REG: iff_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG17_FTDF_REG_iff_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG17_FTDF_REG: iff_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG18_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_FTDF_REG_adc_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_FTDF_REG: adc_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_FTDF_REG_adc_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_FTDF_REG: adc_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_FTDF_REG_adc_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_FTDF_REG: adc_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG18_FTDF_REG_adc_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG18_FTDF_REG: adc_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG19_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_FTDF_REG_vco_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_FTDF_REG: vco_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_FTDF_REG_vco_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_FTDF_REG: vco_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_FTDF_REG_vco_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_FTDF_REG: vco_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG19_FTDF_REG_vco_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG19_FTDF_REG: vco_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG20_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_FTDF_REG_lobuf_md_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_FTDF_REG: lobuf_md_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_FTDF_REG_lobuf_md_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_FTDF_REG: lobuf_md_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_FTDF_REG_lobuf_md_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_FTDF_REG: lobuf_md_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG20_FTDF_REG_lobuf_md_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG20_FTDF_REG: lobuf_md_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG21_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_FTDF_REG_cp_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_FTDF_REG: cp_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_FTDF_REG_cp_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_FTDF_REG: cp_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_FTDF_REG_cp_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_FTDF_REG: cp_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG21_FTDF_REG_cp_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG21_FTDF_REG: cp_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG22_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_FTDF_REG_pfd_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_FTDF_REG: pfd_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_FTDF_REG_pfd_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_FTDF_REG: pfd_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_FTDF_REG_pfd_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_FTDF_REG: pfd_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG22_FTDF_REG_pfd_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG22_FTDF_REG: pfd_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - /* ------------------- RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG ------------------- */ #define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_rx (Bit 0) */ #define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ @@ -10138,78 +10335,18 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG25_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_FTDF_REG_lobuf_pa_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_FTDF_REG: lobuf_pa_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_FTDF_REG_lobuf_pa_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_FTDF_REG: lobuf_pa_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_FTDF_REG_lobuf_pa_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_FTDF_REG: lobuf_pa_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG25_FTDF_REG_lobuf_pa_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG25_FTDF_REG: lobuf_pa_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG26_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_FTDF_REG_lobuf_rxiq_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_FTDF_REG: lobuf_rxiq_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_FTDF_REG_lobuf_rxiq_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_FTDF_REG: lobuf_rxiq_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_FTDF_REG_lobuf_rxiq_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_FTDF_REG: lobuf_rxiq_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG26_FTDF_REG_lobuf_rxiq_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG26_FTDF_REG: lobuf_rxiq_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG27_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_FTDF_REG_div2_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_FTDF_REG: div2_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_FTDF_REG_div2_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_FTDF_REG: div2_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_FTDF_REG_div2_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_FTDF_REG: div2_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG27_FTDF_REG_div2_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG27_FTDF_REG: div2_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG28_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_FTDF_REG_cp_bias_sh_open_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_FTDF_REG: cp_bias_sh_open_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_FTDF_REG_cp_bias_sh_open_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_FTDF_REG: cp_bias_sh_open_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_FTDF_REG_cp_bias_sh_open_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_FTDF_REG: cp_bias_sh_open_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG28_FTDF_REG_cp_bias_sh_open_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG28_FTDF_REG: cp_bias_sh_open_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG29_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_FTDF_REG_vco_bias_sh_open_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_FTDF_REG: vco_bias_sh_open_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_FTDF_REG_vco_bias_sh_open_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_FTDF_REG: vco_bias_sh_open_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_FTDF_REG_vco_bias_sh_open_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_FTDF_REG: vco_bias_sh_open_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG29_FTDF_REG_vco_bias_sh_open_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG29_FTDF_REG: vco_bias_sh_open_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG30_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_FTDF_REG_iffmix_bias_sh_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_FTDF_REG: iffmix_bias_sh_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_FTDF_REG_iffmix_bias_sh_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_FTDF_REG: iffmix_bias_sh_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_FTDF_REG_iffmix_bias_sh_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_FTDF_REG: iffmix_bias_sh_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG30_FTDF_REG_iffmix_bias_sh_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG30_FTDF_REG: iffmix_bias_sh_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - /* ------------------- RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG ------------------- */ #define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_rx (Bit 0) */ #define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ #define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG32_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_FTDF_REG_mix_bias_sh_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_FTDF_REG: mix_bias_sh_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_FTDF_REG_mix_bias_sh_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_FTDF_REG: mix_bias_sh_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_FTDF_REG_mix_bias_sh_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_FTDF_REG: mix_bias_sh_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG32_FTDF_REG_mix_bias_sh_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG32_FTDF_REG: mix_bias_sh_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG33_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_FTDF_REG_pll_dig_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_FTDF_REG: pll_dig_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_FTDF_REG_pll_dig_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_FTDF_REG: pll_dig_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_FTDF_REG_pll_dig_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_FTDF_REG: pll_dig_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG33_FTDF_REG_pll_dig_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG33_FTDF_REG: pll_dig_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG34_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_FTDF_REG_pllclosed_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_FTDF_REG: pllclosed_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_FTDF_REG_pllclosed_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_FTDF_REG: pllclosed_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_FTDF_REG_pllclosed_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_FTDF_REG: pllclosed_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG34_FTDF_REG_pllclosed_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG34_FTDF_REG: pllclosed_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - /* ------------------- RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG ------------------- */ #define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_rx (Bit 0) */ #define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ #define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG36_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_FTDF_REG_ldo_zero_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_FTDF_REG: ldo_zero_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_FTDF_REG_ldo_zero_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_FTDF_REG: ldo_zero_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_FTDF_REG_ldo_zero_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_FTDF_REG: ldo_zero_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG36_FTDF_REG_ldo_zero_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG36_FTDF_REG: ldo_zero_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - /* ------------------- RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG ------------------- */ #define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_rx (Bit 0) */ #define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ @@ -10222,36 +10359,6 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG39_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_FTDF_REG_ldo_rfio_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_FTDF_REG: ldo_rfio_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_FTDF_REG_ldo_rfio_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_FTDF_REG: ldo_rfio_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_FTDF_REG_ldo_rfio_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_FTDF_REG: ldo_rfio_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG39_FTDF_REG_ldo_rfio_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG39_FTDF_REG: ldo_rfio_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG40_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_FTDF_REG_rfio_bias_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_FTDF_REG: rfio_bias_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_FTDF_REG_rfio_bias_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_FTDF_REG: rfio_bias_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_FTDF_REG_rfio_bias_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_FTDF_REG: rfio_bias_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG40_FTDF_REG_rfio_bias_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG40_FTDF_REG: rfio_bias_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG41_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_FTDF_REG_rfio_bias_sh_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_FTDF_REG: rfio_bias_sh_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_FTDF_REG_rfio_bias_sh_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_FTDF_REG: rfio_bias_sh_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_FTDF_REG_rfio_bias_sh_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_FTDF_REG: rfio_bias_sh_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG41_FTDF_REG_rfio_bias_sh_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG41_FTDF_REG: rfio_bias_sh_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG42_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_FTDF_REG_ldo_radio_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_FTDF_REG: ldo_radio_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_FTDF_REG_ldo_radio_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_FTDF_REG: ldo_radio_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_FTDF_REG_ldo_radio_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_FTDF_REG: ldo_radio_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG42_FTDF_REG_ldo_radio_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG42_FTDF_REG: ldo_radio_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - -/* ------------------- RFCU_POWER_RF_ENABLE_CONFIG43_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_FTDF_REG_adc_clk_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_FTDF_REG: adc_clk_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_FTDF_REG_adc_clk_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_FTDF_REG: adc_clk_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_FTDF_REG_adc_clk_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_FTDF_REG: adc_clk_en_ftdf_dcf_tx (Bit 5) */ -#define RFCU_POWER_RF_ENABLE_CONFIG43_FTDF_REG_adc_clk_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG43_FTDF_REG: adc_clk_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ - /* ------------------- RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG ------------------- */ #define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_rx (Bit 0) */ #define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ @@ -10265,20 +10372,20 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ /* ------------------- RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dcparcal_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: dcparcal_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dcparcal_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: dcparcal_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: dem_dcparcal_en_ftdf_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: dem_dcparcal_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ #define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: spare2_en_ftdf_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: spare2_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ /* ------------------- RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_agcunfreeze_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: agcunfreeze_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_agcunfreeze_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: agcunfreeze_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: dem_agcunfreeze_en_ftdf_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: dem_agcunfreeze_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ #define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: spare3_en_ftdf_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: spare3_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ /* ------------------- RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG ------------------- */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_sigdetect_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: sigdetect_en_ftdf_dcf_rx (Bit 0) */ -#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_sigdetect_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: sigdetect_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ +#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Pos (0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: dem_sigdetect_en_ftdf_dcf_rx (Bit 0) */ +#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Msk (0x1fUL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: dem_sigdetect_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f) */ #define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Pos (5UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: spare4_en_ftdf_dcf_tx (Bit 5) */ #define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Msk (0x3e0UL) /*!< RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: spare4_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f) */ @@ -10582,27 +10689,49 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Pos (1UL) /*!< RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_DEM_FTDF_EN (Bit 1) */ #define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Msk (0x2UL) /*!< RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_DEM_FTDF_EN (Bitfield-Mask: 0x01) */ -/* -------------------------- RFCU_POWER_RF_PORT_EN_REG ------------------------- */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT0_RX_Pos (0UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT0_RX (Bit 0) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT0_RX_Msk (0x1UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT0_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT0_TX_Pos (1UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT0_TX (Bit 1) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT0_TX_Msk (0x2UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT0_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT1_RX_Pos (2UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT1_RX (Bit 2) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT1_RX_Msk (0x4UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT1_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT1_TX_Pos (3UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT1_TX (Bit 3) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT1_TX_Msk (0x8UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT1_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT2_RX_Pos (4UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT2_RX (Bit 4) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT2_RX_Msk (0x10UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT2_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT2_TX_Pos (5UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT2_TX (Bit 5) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT2_TX_Msk (0x20UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT2_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_RX_Pos (6UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT3_RX (Bit 6) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_RX_Msk (0x40UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT3_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_TX_Pos (7UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT3_TX (Bit 7) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_TX_Msk (0x80UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT3_TX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_RX_Pos (8UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT4_RX (Bit 8) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_RX_Msk (0x100UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT4_RX (Bitfield-Mask: 0x01) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Pos (9UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT4_TX (Bit 9) */ -#define RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Msk (0x200UL) /*!< RFCU_POWER RF_PORT_EN_REG: RF_PORT4_TX (Bitfield-Mask: 0x01) */ +/* ------------------------ RFCU_POWER_RF_PORT_EN_BLE_REG ----------------------- */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Pos (0UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_RX (Bit 0) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Msk (0x1UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_RX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Pos (1UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_TX (Bit 1) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Msk (0x2UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_TX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Pos (2UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_RX (Bit 2) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Msk (0x4UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_RX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Pos (3UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_TX (Bit 3) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Msk (0x8UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_TX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Pos (4UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_RX (Bit 4) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Msk (0x10UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_RX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Pos (5UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_TX (Bit 5) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Msk (0x20UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_TX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Pos (6UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_RX (Bit 6) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk (0x40UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_RX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Pos (7UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_TX (Bit 7) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk (0x80UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_TX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Pos (8UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_RX (Bit 8) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Msk (0x100UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_RX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Pos (9UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_TX (Bit 9) */ +#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Msk (0x200UL) /*!< RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_TX (Bitfield-Mask: 0x01) */ + +/* ----------------------- RFCU_POWER_RF_PORT_EN_FTDF_REG ----------------------- */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Pos (0UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_RX (Bit 0) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Msk (0x1UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_RX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Pos (1UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_TX (Bit 1) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Msk (0x2UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_TX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Pos (2UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_RX (Bit 2) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Msk (0x4UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_RX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Pos (3UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_TX (Bit 3) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Msk (0x8UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_TX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Pos (4UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_RX (Bit 4) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Msk (0x10UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_RX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Pos (5UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_TX (Bit 5) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Msk (0x20UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_TX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Pos (6UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_RX (Bit 6) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk (0x40UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_RX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Pos (7UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_TX (Bit 7) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk (0x80UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_TX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Pos (8UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_RX (Bit 8) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Msk (0x100UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_RX (Bitfield-Mask: 0x01) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Pos (9UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_TX (Bit 9) */ +#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Msk (0x200UL) /*!< RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_TX (Bitfield-Mask: 0x01) */ /* ------------------------- RFCU_POWER_RF_PORT_POL_REG ------------------------- */ #define RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Pos (0UL) /*!< RFCU_POWER RF_PORT_POL_REG: RF_PORT0_POL (Bit 0) */ @@ -10856,6 +10985,26 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Pos (0UL) /*!< TIMER1 CAPTIM_PWM_DC_REG: CAPTIM_PWM_DC (Bit 0) */ #define TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Msk (0xffffUL) /*!< TIMER1 CAPTIM_PWM_DC_REG: CAPTIM_PWM_DC (Bitfield-Mask: 0xffff) */ +/* ------------------------ TIMER1_CAPTIM_TIMER_HVAL_REG ------------------------ */ +#define TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Pos (0UL) /*!< TIMER1 CAPTIM_TIMER_HVAL_REG: CAPTIM_TIMER_HVALUE (Bit 0) */ +#define TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Msk (0xffffUL) /*!< TIMER1 CAPTIM_TIMER_HVAL_REG: CAPTIM_TIMER_HVALUE (Bitfield-Mask: 0xffff) */ + +/* ------------------------ TIMER1_CAPTIM_RELOAD_HIGH_REG ----------------------- */ +#define TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Pos (0UL) /*!< TIMER1 CAPTIM_RELOAD_HIGH_REG: CAPTIM_RELOAD_HIGH (Bit 0) */ +#define TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Msk (0xffffUL) /*!< TIMER1 CAPTIM_RELOAD_HIGH_REG: CAPTIM_RELOAD_HIGH (Bitfield-Mask: 0xffff) */ + +/* -------------------- TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG -------------------- */ +#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Pos (0UL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO1_REG: CAPTIM_CAPTURE_HIGH_GPIO1 (Bit 0) */ +#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Msk (0xffffUL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO1_REG: CAPTIM_CAPTURE_HIGH_GPIO1 (Bitfield-Mask: 0xffff) */ + +/* -------------------- TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG -------------------- */ +#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Pos (0UL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO2_REG: CAPTIM_CAPTURE_HIGH_GPIO2 (Bit 0) */ +#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Msk (0xffffUL) /*!< TIMER1 CAPTIM_CAPTURE_HIGH_GPIO2_REG: CAPTIM_CAPTURE_HIGH_GPIO2 (Bitfield-Mask: 0xffff) */ + +/* ---------------------- TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG ---------------------- */ +#define TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Pos (0UL) /*!< TIMER1 CAPTIM_SHOTWIDTH_HIGH_REG: CAPTIM_SHOTWIDTH_HIGH (Bit 0) */ +#define TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Msk (0xffffUL) /*!< TIMER1 CAPTIM_SHOTWIDTH_HIGH_REG: CAPTIM_SHOTWIDTH_HIGH (Bitfield-Mask: 0xffff) */ + /* ================================================================================ */ /* ================ struct 'TRNG' Position & Mask ================ */ @@ -11756,22 +11905,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos (7UL) /*!< WAKEUP WKUP_CTRL_REG: WKUP_ENABLE_IRQ (Bit 7) */ #define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk (0x80UL) /*!< WAKEUP WKUP_CTRL_REG: WKUP_ENABLE_IRQ (Bitfield-Mask: 0x01) */ -/* --------------------------- WAKEUP_WKUP_COMPARE_REG -------------------------- */ -#define WAKEUP_WKUP_COMPARE_REG_COMPARE_Pos (0UL) /*!< WAKEUP WKUP_COMPARE_REG: COMPARE (Bit 0) */ -#define WAKEUP_WKUP_COMPARE_REG_COMPARE_Msk (0xffUL) /*!< WAKEUP WKUP_COMPARE_REG: COMPARE (Bitfield-Mask: 0xff) */ - /* -------------------------- WAKEUP_WKUP_RESET_IRQ_REG ------------------------- */ #define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos (0UL) /*!< WAKEUP WKUP_RESET_IRQ_REG: WKUP_IRQ_RST (Bit 0) */ #define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk (0xffffUL) /*!< WAKEUP WKUP_RESET_IRQ_REG: WKUP_IRQ_RST (Bitfield-Mask: 0xffff) */ -/* --------------------------- WAKEUP_WKUP_COUNTER_REG -------------------------- */ -#define WAKEUP_WKUP_COUNTER_REG_EVENT_VALUE_Pos (0UL) /*!< WAKEUP WKUP_COUNTER_REG: EVENT_VALUE (Bit 0) */ -#define WAKEUP_WKUP_COUNTER_REG_EVENT_VALUE_Msk (0xffUL) /*!< WAKEUP WKUP_COUNTER_REG: EVENT_VALUE (Bitfield-Mask: 0xff) */ - -/* ------------------------- WAKEUP_WKUP_RESET_CNTR_REG ------------------------- */ -#define WAKEUP_WKUP_RESET_CNTR_REG_WKUP_CNTR_RST_Pos (0UL) /*!< WAKEUP WKUP_RESET_CNTR_REG: WKUP_CNTR_RST (Bit 0) */ -#define WAKEUP_WKUP_RESET_CNTR_REG_WKUP_CNTR_RST_Msk (0xffffUL) /*!< WAKEUP WKUP_RESET_CNTR_REG: WKUP_CNTR_RST (Bitfield-Mask: 0xffff) */ - /* -------------------------- WAKEUP_WKUP_SELECT_P0_REG ------------------------- */ #define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos (0UL) /*!< WAKEUP WKUP_SELECT_P0_REG: WKUP_SELECT_P0 (Bit 0) */ #define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk (0xffUL) /*!< WAKEUP WKUP_SELECT_P0_REG: WKUP_SELECT_P0 (Bitfield-Mask: 0xff) */ @@ -11812,6 +11949,58 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #define WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Pos (0UL) /*!< WAKEUP WKUP_POL_P4_REG: WKUP_POL_P4 (Bit 0) */ #define WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Msk (0xffUL) /*!< WAKEUP WKUP_POL_P4_REG: WKUP_POL_P4 (Bitfield-Mask: 0xff) */ +/* -------------------------- WAKEUP_WKUP_STATUS_0_REG -------------------------- */ +#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Pos (0UL) /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P0 (Bit 0) */ +#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Msk (0xffUL) /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P0 (Bitfield-Mask: 0xff) */ +#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Pos (8UL) /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P1 (Bit 8) */ +#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Msk (0xff00UL) /*!< WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P1 (Bitfield-Mask: 0xff) */ + +/* -------------------------- WAKEUP_WKUP_STATUS_1_REG -------------------------- */ +#define WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Pos (0UL) /*!< WAKEUP WKUP_STATUS_1_REG: WKUP_STAT_P2 (Bit 0) */ +#define WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Msk (0x1fUL) /*!< WAKEUP WKUP_STATUS_1_REG: WKUP_STAT_P2 (Bitfield-Mask: 0x1f) */ + +/* -------------------------- WAKEUP_WKUP_STATUS_2_REG -------------------------- */ +#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Pos (0UL) /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P3 (Bit 0) */ +#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Msk (0xffUL) /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P3 (Bitfield-Mask: 0xff) */ +#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Pos (8UL) /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P4 (Bit 8) */ +#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Msk (0xff00UL) /*!< WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P4 (Bitfield-Mask: 0xff) */ + +/* --------------------------- WAKEUP_WKUP_CLEAR_0_REG -------------------------- */ +#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Pos (0UL) /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P0 (Bit 0) */ +#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Msk (0xffUL) /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P0 (Bitfield-Mask: 0xff) */ +#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Pos (8UL) /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P1 (Bit 8) */ +#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Msk (0xff00UL) /*!< WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P1 (Bitfield-Mask: 0xff) */ + +/* --------------------------- WAKEUP_WKUP_CLEAR_1_REG -------------------------- */ +#define WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Pos (0UL) /*!< WAKEUP WKUP_CLEAR_1_REG: WKUP_CLEAR_P2 (Bit 0) */ +#define WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Msk (0x1fUL) /*!< WAKEUP WKUP_CLEAR_1_REG: WKUP_CLEAR_P2 (Bitfield-Mask: 0x1f) */ + +/* --------------------------- WAKEUP_WKUP_CLEAR_2_REG -------------------------- */ +#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Pos (0UL) /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P3 (Bit 0) */ +#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Msk (0xffUL) /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P3 (Bitfield-Mask: 0xff) */ +#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Pos (8UL) /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P4 (Bit 8) */ +#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Msk (0xff00UL) /*!< WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P4 (Bitfield-Mask: 0xff) */ + +/* ------------------------- WAKEUP_WKUP_SEL_GPIO_P0_REG ------------------------ */ +#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos (0UL) /*!< WAKEUP WKUP_SEL_GPIO_P0_REG: WKUP_SEL_GPIO_P0 (Bit 0) */ +#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk (0xffUL) /*!< WAKEUP WKUP_SEL_GPIO_P0_REG: WKUP_SEL_GPIO_P0 (Bitfield-Mask: 0xff) */ + +/* ------------------------- WAKEUP_WKUP_SEL_GPIO_P1_REG ------------------------ */ +#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos (0UL) /*!< WAKEUP WKUP_SEL_GPIO_P1_REG: WKUP_SEL_GPIO_P1 (Bit 0) */ +#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk (0xffUL) /*!< WAKEUP WKUP_SEL_GPIO_P1_REG: WKUP_SEL_GPIO_P1 (Bitfield-Mask: 0xff) */ + +/* ------------------------- WAKEUP_WKUP_SEL_GPIO_P2_REG ------------------------ */ +#define WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Pos (0UL) /*!< WAKEUP WKUP_SEL_GPIO_P2_REG: WKUP_SEL_GPIO_P2 (Bit 0) */ +#define WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Msk (0x1fUL) /*!< WAKEUP WKUP_SEL_GPIO_P2_REG: WKUP_SEL_GPIO_P2 (Bitfield-Mask: 0x1f) */ + +/* ------------------------- WAKEUP_WKUP_SEL_GPIO_P3_REG ------------------------ */ +#define WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Pos (0UL) /*!< WAKEUP WKUP_SEL_GPIO_P3_REG: WKUP_SEL_GPIO_P3 (Bit 0) */ +#define WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Msk (0xffUL) /*!< WAKEUP WKUP_SEL_GPIO_P3_REG: WKUP_SEL_GPIO_P3 (Bitfield-Mask: 0xff) */ + +/* ------------------------- WAKEUP_WKUP_SEL_GPIO_P4_REG ------------------------ */ +#define WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Pos (0UL) /*!< WAKEUP WKUP_SEL_GPIO_P4_REG: WKUP_SEL_GPIO_P4 (Bit 0) */ +#define WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Msk (0xffUL) /*!< WAKEUP WKUP_SEL_GPIO_P4_REG: WKUP_SEL_GPIO_P4 (Bitfield-Mask: 0xff) */ + /* ================================================================================ */ /* ================ struct 'WDOG' Position & Mask ================ */ @@ -11923,7 +12112,7 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str /** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group DA14680AD */ +/** @} */ /* End of group DA14680BA */ /** @} */ /* End of group Dialog */ #ifdef __cplusplus @@ -11931,5 +12120,5 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str #endif -#endif /* DA14680AD_H */ +#endif /* DA14680BA_H */ diff --git a/third_party/dialog/DialogSDK/bsp/include/black_orca.h b/third_party/dialog/DialogSDK/bsp/include/black_orca.h deleted file mode 100755 index 257580490..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/black_orca.h +++ /dev/null @@ -1,287 +0,0 @@ -/** - * \addtogroup BSP - * \{ - * \addtogroup SYSTEM - * \{ - * \addtogroup PLATFORM - * - * \brief Black Orca Platform definitions - * - * \{ - */ - -/** - ***************************************************************************************** - * - * @file black_orca.h - * - * @brief Central include header file for the Dialog Black Orca platform. - * - * @version 1.0 - * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************************** - */ - -#ifndef __BLACK_ORCA_H__ -#define __BLACK_ORCA_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifdef __GNUC__ -# define GCC_VERSION (__GNUC__ * 10000 \ - + __GNUC_MINOR__ * 100 \ - + __GNUC_PATCHLEVEL__) -/* assert gcc version is at least 4.9.3 */ -# if GCC_VERSION < 40903 -# error "Please use gcc version 4.9.3 or newer!" -# endif -#endif - -#include "global_io.h" - -#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A -# if dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_D -# include "DA14680AD.h" -# elif dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_C -# include "DA14680AC.h" -# elif dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_A -# include "DA14680AA.h" -# else -# error "Unknown chip stepping for revision A -- check the value of dg_configBLACK_ORCA_IC_STEP" -# endif -#else -# error "Unknown chip revision -- check the value of dg_configBLACK_ORCA_IC_REV" -#endif - -#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ -#include "system_DA14680.h" /* DA14680AA System */ - - -/************************ - * Black Orca Memory map - ************************/ - -/** - * \brief Remapped device address range. - */ -#define MEMORY_REMAPPED_BASE 0x00000000 -#define MEMORY_REMAPPED_END 0x04000000 - -/** - * \brief Remapped device memory size (64MiB). - */ -#define MEMORY_REMAPPED_SIZE (MEMORY_REMAPPED_END - MEMORY_REMAPPED_BASE) - -/** - * \brief ROM address range. - */ -#define MEMORY_ROM_BASE 0x07F00000 -#define MEMORY_ROM_END 0x07F40000 - -/** - * \brief ROM memory size (256KiB). - */ -#define MEMORY_ROM_SIZE (MEMORY_ROM_END - MEMORY_ROM_BASE) - -/** - * \brief OTP Controller address range. - */ -#define MEMORY_OTPC_BASE 0x07F40000 -#define MEMORY_OTPC_END 0x07F80000 - -/** - * \brief OTP memory address range. - */ -#define MEMORY_OTP_BASE 0x07F80000 -#define MEMORY_OTP_END 0x07FC0000 - -/** - * \brief OTP memory size (256KiB). - */ -#define MEMORY_OTP_SIZE (MEMORY_OTP_END - MEMORY_OTP_BASE) - -/** - * \brief SYSTEM RAM address range. - */ -#define MEMORY_SYSRAM_BASE 0x07FC0000 -#define MEMORY_SYSRAM_END 0x07FE0000 - -/** - * \brief SYSTEM RAM size (128KiB). - */ -#define MEMORY_SYSRAM_SIZE (MEMORY_SYSRAM_END - MEMORY_SYSRAM_BASE) - -/** - * \brief CACHE RAM address range. - */ -#define MEMORY_CACHERAM_BASE 0x07FE0000 -#define MEMORY_CACHERAM_END 0x08000000 - -/** - * \brief CACHE RAM size (128KiB). - */ -#define MEMORY_CACHERAM_SIZE (MEMORY_CACHERAM_END - MEMORY_CACHERAM_BASE) - -/** - * \brief QSPI Flash address range. - */ -#define MEMORY_QSPIF_BASE 0x08000000 -#define MEMORY_QSPIF_END 0x0BF00000 - -/** - * \brief QSPI Flash memory size (63MiB). - */ -#define MEMORY_QSPIF_SIZE (MEMORY_QSPIF_END - MEMORY_QSPIF_BASE) - -/** - * \brief QSPI Controller address range. - */ -#define MEMORY_QSPIC_BASE 0x0C000000 -#define MEMORY_QSPIC_END 0x0C100000 - -#define WITHIN_RANGE(_a, _s, _e) (((uint32_t)(_a) >= (uint32_t)(_s)) && ((uint32_t)(_a) < (uint32_t)(_e))) - -/** - * \brief Address is in the remapped memory region - */ -#define IS_REMAPPED_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_REMAPPED_BASE, MEMORY_REMAPPED_END) - -/** - * \brief Address is in the ROM region - */ -#define IS_ROM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_ROM_BASE, MEMORY_ROM_END) - -/** - * \brief Address is in the OTP memory region - */ -#define IS_OTP_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_OTP_BASE, MEMORY_OTP_END) - -/** - * \brief Address is in the OTP Controller memory region - */ -#define IS_OTPC_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_OTPC_BASE, MEMORY_OTPC_END) - -/** - * \brief Address is in the SYSTEM RAM region - */ -#define IS_SYSRAM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_SYSRAM_BASE, MEMORY_SYSRAM_END) - -/** - * \brief Address is in the CACHE RAM region - */ -#define IS_CACHERAM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_CACHERAM_BASE, MEMORY_CACHERAM_END) - -/** - * \brief Address is in the QSPI Flash memory region - */ -#define IS_QSPIF_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_QSPIF_BASE, MEMORY_QSPIF_END) - -/** - * \brief Address is in the QSPI Controller memory region - */ -#define IS_QSPIC_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_QSPIC_BASE, MEMORY_QSPIC_END) - -#define _BLACK_ORCA_IC_VERSION(revision, stepping) \ - ((((uint32_t)(revision)) << 8) | ((uint32_t)(stepping))) - -/** - * \brief Convenience macro to create the full chip version from revision and stepping. - * It takes letters as arguments. - */ -#define BLACK_ORCA_IC_VERSION(revision, stepping) \ - _BLACK_ORCA_IC_VERSION(BLACK_ORCA_IC_REV_##revision, \ - BLACK_ORCA_IC_STEP_##stepping) - -/** - * \brief The chip version that we compile for. - */ -#define BLACK_ORCA_TARGET_IC \ - _BLACK_ORCA_IC_VERSION(dg_configBLACK_ORCA_IC_REV, dg_configBLACK_ORCA_IC_STEP) - - -/** - * \brief Get the chip version of the system, at runtime. - */ -__STATIC_INLINE uint32_t black_orca_get_chip_version(void) -{ - uint32_t rev = CHIP_VERSION->CHIP_REVISION_REG - 'A'; - uint32_t step = CHIP_VERSION->CHIP_TEST1_REG; - - return _BLACK_ORCA_IC_VERSION(rev, step); -} - -// Forward declaration -__RETAINED_CODE void hw_cpm_assert_trigger_gpio(void); - -#define ASSERT(a) { if (!(a)) while (1); } - -#define ASSERT_WARNING(a) \ - { \ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ - if (!(a)) { \ - __asm volatile ( " cpsid i " ); \ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ - hw_cpm_assert_trigger_gpio(); \ - do {} while(1); \ - } \ - } \ - } - - - -#define ASSERT_ERROR(a) \ - { \ - if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ - if (!(a)) { \ - __asm volatile ( " cpsid i " ); \ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ - hw_cpm_assert_trigger_gpio(); \ - do {} while(1); \ - } \ - } \ - else { \ - if (!(a)) { \ - __asm volatile ( " cpsid i " ); \ - __asm volatile ( " bkpt 2 " ); \ - } \ - } \ - } - - -#ifdef __cplusplus -} -#endif - -#endif /* __BLACK_ORCA_H__ */ - -/** - * \} - * \} - * \} - */ diff --git a/third_party/dialog/DialogSDK/bsp/include/cmsis_gcc.h b/third_party/dialog/DialogSDK/bsp/include/cmsis_gcc.h new file mode 100644 index 000000000..bb89fbba9 --- /dev/null +++ b/third_party/dialog/DialogSDK/bsp/include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/third_party/dialog/DialogSDK/bsp/include/core_cm0.h b/third_party/dialog/DialogSDK/bsp/include/core_cm0.h old mode 100755 new mode 100644 index 0aebb1cd5..21ae4f9ba --- a/third_party/dialog/DialogSDK/bsp/include/core_cm0.h +++ b/third_party/dialog/DialogSDK/bsp/include/core_cm0.h @@ -1,17 +1,10 @@ -/** \addtogroup ARM - * \brief ARM core documentation - * \{ - */ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * + * @version V4.30 + * @date 20. October 2015 ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -39,18 +32,23 @@ ---------------------------------------------------------------------------*/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
@@ -67,69 +65,107 @@ /******************************************************************************* * CMSIS definitions ******************************************************************************/ -/** \ingroup Cortex_M0 +/** + \ingroup Cortex_M0 @{ */ /* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ #if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + #elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler #endif -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all */ -#define __FPU_USED 0 +#define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + #endif -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif #endif /* __CORE_CM0_H_GENERIC */ @@ -138,20 +174,24 @@ #ifndef __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT +#ifdef __cplusplus + extern "C" { +#endif + /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV - #define __CM0_REV 0x0000 + #define __CM0_REV 0x0000U #warning "__CM0_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 + #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 + #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif @@ -165,12 +205,17 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ + #define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ + #define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M0 */ @@ -184,300 +229,364 @@ - Core SCB Register - Core SysTick Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). +/** + \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ -/** \brief Union type to access the Interrupt Program Status Register (IPSR). +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ -/** \brief Union type to access the Control Registers (CONTROL). +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + /*@} end of group CMSIS_CORE */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). +/** + \brief Structure type to access the System Control Block (SCB). */ typedef struct { - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). +/** + \brief Structure type to access the System Timer (SysTick). */ typedef struct { - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M0 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ @@ -491,144 +600,145 @@ typedef struct - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ */ - -#include "black_orca.h" /* Declares IRQn_Type */ - +#include "sdk_defs.h" /* Declares IRQn_Type */ /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } } -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } } -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } } /*@} end of CMSIS_Core_NVICFunctions */ @@ -636,40 +746,40 @@ __STATIC_INLINE void NVIC_SystemReset(void) /* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. @{ */ -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. +#if (__Vendor_SysTickConfig == 0U) +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -677,15 +787,12 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) /*@} end of CMSIS_Core_SysTickFunctions */ -#endif /* __CORE_CM0_H_DEPENDANT */ -#endif /* __CMSIS_GENERIC */ #ifdef __cplusplus } #endif -/** -\} end of ARM group -*/ +#endif /* __CORE_CM0_H_DEPENDANT */ +#endif /* __CMSIS_GENERIC */ diff --git a/third_party/dialog/DialogSDK/bsp/include/core_cmFunc.h b/third_party/dialog/DialogSDK/bsp/include/core_cmFunc.h old mode 100755 new mode 100644 index 9e7875de5..652a48af0 --- a/third_party/dialog/DialogSDK/bsp/include/core_cmFunc.h +++ b/third_party/dialog/DialogSDK/bsp/include/core_cmFunc.h @@ -1,17 +1,10 @@ -/** \addtogroup ARM - * \{ - */ - /**************************************************************************//** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * + * @version V4.30 + * @date 20. October 2015 ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -39,6 +32,12 @@ ---------------------------------------------------------------------------*/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + #ifndef __CORE_CMFUNC_H #define __CORE_CMFUNC_H @@ -47,599 +46,42 @@ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include #endif /*@} end of CMSIS_Core_RegAccFunctions */ - #endif /* __CORE_CMFUNC_H */ - -/** -\} end of ARM group -*/ - diff --git a/third_party/dialog/DialogSDK/bsp/include/core_cmInstr.h b/third_party/dialog/DialogSDK/bsp/include/core_cmInstr.h old mode 100755 new mode 100644 index a45c4b768..f474b0e6f --- a/third_party/dialog/DialogSDK/bsp/include/core_cmInstr.h +++ b/third_party/dialog/DialogSDK/bsp/include/core_cmInstr.h @@ -1,17 +1,10 @@ -/** \addtogroup ARM - * \{ - */ - /**************************************************************************//** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * + * @version V4.30 + * @date 20. October 2015 ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -39,6 +32,12 @@ ---------------------------------------------------------------------------*/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + #ifndef __CORE_CMINSTR_H #define __CORE_CMINSTR_H @@ -49,649 +48,40 @@ @{ */ -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include #endif /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ #endif /* __CORE_CMINSTR_H */ - -/** -\} end of ARM group -*/ - diff --git a/third_party/dialog/DialogSDK/bsp/include/global_io.h b/third_party/dialog/DialogSDK/bsp/include/global_io.h deleted file mode 100755 index 40a7642b0..000000000 --- a/third_party/dialog/DialogSDK/bsp/include/global_io.h +++ /dev/null @@ -1,362 +0,0 @@ -#ifndef IO_H_INCLUDED -#define IO_H_INCLUDED - -/* - *---------------------------------------------------------------------------------------------------------------------------------------- - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - * Description : IO, data type definitions and memory map selector. - * - * Remark(s) : None. - * - *---------------------------------------------------------------------------------------------------------------------------------------- - * - * Synchronicity keywords: - * - * Id : $Id: global_io.h.rca 1.1 Wed Oct 24 09:42:42 2012 wroovers Experimental wroovers $ - * Source : $Source: /services/syncdata/hazelaar/8500/server_vault/applab/14580/sw/keil/keil_full_emb_SWHL6V16LL6V32_24okt_crosstest_OK_fpga14b/src/inc/global_io.h.rca $ - * - *---------------------------------------------------------------------------------------------------------------------------------------- - * - * Synchronicity history: - * - * Log : $Log: global_io.h.rca $ - * Log : - * Log : Revision: 1.1 Mon Oct 1 11:08:33 2012 wroovers - * Log : First Working set - * Log : - * Log : Revision: 1.2 Mon Mar 19 11:52:13 2012 snijders - * Log : Updated the '*int*' typedef's. Put the 'bool' (C++ only) typedef in comment, see comment. - * Log : Added typedef HWORD and updated the already existing WORD and DWORD (according to the ARM data type definitions). - * Log : Removed the IAR depending '__far' and 'inline' defines (obsolete). - * Log : Removed the CR16C_SW_V4 depending '__far' define (obsolete). - * Log : Removed the 'NULL' define (most probably also obsolete). - * Log : - * Log : Revision: 1.1 Tue Mar 6 11:00:42 2012 snijders - * Log : Initial check in for Project bbtester. Copied from "../sitel_io.h" and renamed to "global_io.h". - * Log : Updated the header, no further changes yet. - * - *---------------------------------------------------------------------------------------------------------------------------------------- - * - * History: - * - * sc14580a - * -------- - * 19-mar-2012/HS: Updated the '*int*' typedef's. Put the 'bool' (C++ only) typedef in comment, see comment. - * Added typedef HWORD and updated the already existing WORD and DWORD (according to the ARM data type definitions). - * Removed the IAR depending '__far' and 'inline' defines (obsolete). - * Removed the CR16C_SW_V4 depending '__far' define (obsolete). - * Removed the 'NULL' define (most probably also obsolete). - * 06-mar-2012/HS: Initial check in for Project bbtester. Copied from "../sitel_io.h" and renamed to "global_io.h". - * Updated the header, no further changes yet. - * - *---------------------------------------------------------------------------------------------------------------------------------------- -*/ - -#include - -typedef unsigned char uint8; // 8 bits -typedef char int8; // 8 bits -typedef unsigned short uint16; // 16 bits -typedef short int16; // 16 bits -typedef unsigned long uint32; // 32 bits -typedef long int32; // 32 bits -typedef unsigned long long uint64; // 64 bits -typedef long long int64; // 64 bits - -/* See also "Data Types" on pag. 21 of the (Doulos) Cortex-M0 / SoC 1.0 training documentation. */ -typedef unsigned char BYTE; // 8 bits = Byte -typedef unsigned short HWORD; // 16 bits = Halfword -typedef unsigned long WORD; // 32 bits = Word -typedef long long DWORD; // 64 bits = Doubleword - -// Retention memory attributes -#define __RETAINED __attribute__((section("retention_mem_zi"))) -#define __RETAINED_RW __attribute__((section("retention_mem_rw"))) -#define __RETAINED_UNINIT __attribute__((section("retention_mem_uninit"))) -#if ((dg_configCODE_LOCATION == NON_VOLATILE_IS_FLASH) && (dg_configEXEC_MODE == MODE_IS_CACHED)) -#define __RETAINED_CODE __attribute__((section("text_retained"))) __attribute__((noinline)) -#else -#define __RETAINED_CODE -#endif - -// Interrupt macros -#define GLOBAL_INT_DISABLE() \ - do { \ - uint32 __l_irq_rest = __get_PRIMASK(); \ - __set_PRIMASK(1); \ - DBG_CONFIGURE_HIGH(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); - - -#define GLOBAL_INT_RESTORE() \ - if (__l_irq_rest == 0) { \ - DBG_CONFIGURE_LOW(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); \ - __set_PRIMASK(0); \ - } \ - else { \ - __set_PRIMASK(1); \ - } \ - } while(0) - - - -#ifndef offsetof -#if defined(__GNUC__) -#define offsetof(type, member) __builtin_offsetof(type, member) -#else -#define offsetof(type,member) ((size_t)(&((type *)0)->member)) -#endif -#endif - -#define containingoffset(address, type, field) ((type*)((uint8*)(address)-(size_t)(&((type*)0)->field))) - - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) - -#define BIT0 0x01 -#define BIT1 0x02 -#define BIT2 0x04 -#define BIT3 0x08 -#define BIT4 0x10 -#define BIT5 0x20 -#define BIT6 0x40 -#define BIT7 0x80 - -#define BIT8 0x0100 -#define BIT9 0x0200 -#define BIT10 0x0400 -#define BIT11 0x0800 -#define BIT12 0x1000 -#define BIT13 0x2000 -#define BIT14 0x4000 -#define BIT15 0x8000 - -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 - -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -#if defined(__GNUC__) -#define SWAP16(a) __builtin_bswap16(a) -#define SWAP32(a) __builtin_bswap32(a) -#else -#define SWAP16(a) ((a<<8) | (a>>8)) -#define SWAP32(a) ((a>>24 & 0xff) | (a>>8 & 0xff00) | (a<<8 & 0xff0000) | (a<<24 & 0xff000000)) -#endif - -#if defined(__GNUC__) -#define DEPRECATED __attribute__ ((deprecated)) -#define DEPRECATED_MSG(msg) __attribute__ ((deprecated(msg))) -#else -#warning Deprecated macro must be implemented for this compiler -#define DEPRECATED -#define DEPRECATED_MSG(msg) -#endif - -/** - * \brief Access register field mask. - * - * Returns a register field mask (aimed to be used with local variables). - * e.g. - * \code - * uint16_t tmp; - * - * tmp = CRG_TOP->SYS_STAT_REG; - * - * if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, XTAL16_TRIM_READY)) { - * ... - * \endcode - */ -#define REG_MSK(base, reg, field) \ - (base ## _ ## reg ## _ ## field ## _Msk) - -/** - * \brief Access register field position. - * - * Returns a register field position (aimed to be used with local variables). - */ -#define REG_POS(base, reg, field) \ - (base ## _ ## reg ## _ ## field ## _Pos) - -/** - * \brief Access register field value. - * - * Returns a register field value (aimed to be used with local variables). - * e.g. - * \code - * uint16_t tmp; - * int counter; - * tmp = CRG_TOP->TRIM_CTRL_REG; - * counter = REG_GET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp); - * ... - * \endcode - */ -#define REG_GET_FIELD(base, reg, field, var) \ - ((var & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ - (base ## _ ## reg ## _ ## field ## _Pos)) - -/** - * \brief Set register field value. - * - * Sets a register field value (aimed to be used with local variables). - * e.g. - * \code - * uint16_t tmp; - * - * tmp = CRG_TOP->TRIM_CTRL_REG; - * REG_SET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp, 10); - * REG_SET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_TRIM_SELECT, tmp, 2); - * CRG_TOP->TRIM_CTRL_REG = tmp; - * ... - * \endcode - */ -#define REG_SET_FIELD(base, reg, field, var, val) \ - var = ((var & ~((base ## _ ## reg ## _ ## field ## _Msk))) | \ - ((val << (base ## _ ## reg ## _ ## field ## _Pos)) & \ - (base ## _ ## reg ## _ ## field ## _Msk))) - -/** - * \brief Clear register field value. - * - * Clears a register field value (aimed to be used with local variables). - * e.g. - * \code - * uint16_t tmp; - * - * tmp = CRG_TOP->TRIM_CTRL_REG; - * REG_CLR_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp); - * REG_CLR_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_TRIM_SELECT, tmp); - * CRG_TOP->TRIM_CTRL_REG = tmp; - * ... - * \endcode - */ -#define REG_CLR_FIELD(base, reg, field, var) \ - var &= ~(base ## _ ## reg ## _ ## field ## _Msk) - - -/** - * \brief Return the value of a register field. - * - * e.g. - * \code - * uint16_t val; - * - * val = REG_GETF(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N); - * ... - * \endcode - */ -#define REG_GETF(base, reg, field) \ - (((base->reg) & (base##_##reg##_##field##_Msk)) >> (base##_##reg##_##field##_Pos)) - -/** - * \brief Set the value of a register field. - * - * e.g. - * \code - * - * REG_SETF(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, new_value); - * ... - * \endcode - */ -#define REG_SETF(base, reg, field, new_val) \ - base->reg = ((base->reg & ~(base##_##reg##_##field##_Msk)) | \ - ((base##_##reg##_##field##_Msk) & ((new_val) << (base##_##reg##_##field##_Pos)))) - -/** - * \brief Set a bit of a register. - * - * e.g. - * \code - * - * REG_SET_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); - * ... - * \endcode - */ -#define REG_SET_BIT(base, reg, field) \ - do { \ - base->reg |= (1 << (base##_##reg##_##field##_Pos)); \ - } while (0) - -/** - * \brief Clear a bit of a register. - * - * e.g. - * \code - * - * REG_CLR_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); - * ... - * \endcode - */ -#define REG_CLR_BIT(base, reg, field) \ - do { \ - base->reg &= ~(base##_##reg##_##field##_Msk); \ - } while (0) - -/** - * \brief Sets register bits, indicated by the mask, to a value. - * - * e.g. - * \code - * REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818); - * \endcode - */ -#define REG_SET_MASKED(base, reg, mask, value) \ - do { \ - base->reg = (base->reg & ~(mask)) | ((value) & (mask)); \ - } while (0) - -#define ENABLE_DEBUGGER \ - do { \ - REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); \ - } while(0) - -#define DISABLE_DEBUGGER \ - do { \ - REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); \ - } while(0) - - -#define SWRESET \ - do { \ - REG_SET_BIT(GPREG, DEBUG_REG, SW_RESET); \ - } while (0) - - -#endif diff --git a/third_party/dialog/DialogSDK/bsp/include/interrupts.h b/third_party/dialog/DialogSDK/bsp/include/interrupts.h old mode 100755 new mode 100644 index 45e59487e..af902cce2 --- a/third_party/dialog/DialogSDK/bsp/include/interrupts.h +++ b/third_party/dialog/DialogSDK/bsp/include/interrupts.h @@ -40,7 +40,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ @@ -118,20 +119,27 @@ static inline bool in_interrupt(void) */ extern const int8_t __dialog_interrupt_priorities[]; + +#if (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A) && (dg_configUSE_AUTO_CHIP_DETECTION != 1) + #define LAST_IRQn PLL_LOCK_IRQn +#else + #define LAST_IRQn RESERVED31_IRQn +#endif + /* * Following macros allow easy way to build table with interrupt priorities. * See example in set_interrupt_priorities function description. */ #define INTERRUPT_PRIORITY_CONFIG_START(name) const int8_t name[] = { -#define PRIORITY_0 (RESERVED31_IRQn + 1) -#define PRIORITY_1 (RESERVED31_IRQn + 2) -#define PRIORITY_2 (RESERVED31_IRQn + 3) -#define PRIORITY_3 (RESERVED31_IRQn + 4) -#define PRIORITY_TABLE_END (RESERVED31_IRQn + 5) +#define PRIORITY_0 (LAST_IRQn + 1) +#define PRIORITY_1 (LAST_IRQn + 2) +#define PRIORITY_2 (LAST_IRQn + 3) +#define PRIORITY_3 (LAST_IRQn + 4) +#define PRIORITY_TABLE_END (LAST_IRQn + 5) #define INTERRUPT_PRIORITY_CONFIG_END PRIORITY_TABLE_END }; #ifdef __cplusplus -extern } +} #endif #endif /* INTERRUPTS_H_ */ diff --git a/third_party/dialog/DialogSDK/bsp/include/sdk_defs.h b/third_party/dialog/DialogSDK/bsp/include/sdk_defs.h new file mode 100644 index 000000000..abc162bc2 --- /dev/null +++ b/third_party/dialog/DialogSDK/bsp/include/sdk_defs.h @@ -0,0 +1,777 @@ +/** + * \addtogroup BSP + * \{ + * \addtogroup SYSTEM + * \{ + * \addtogroup PLATFORM + * + * \brief Platform definitions + * + * \{ + */ + +/** + ***************************************************************************************** + * + * @file sdk_defs.h + * + * @brief Central include header file with platform definitions. + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************************** + */ + +#ifndef __SDK_DEFS_H__ +#define __SDK_DEFS_H__ + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __GNUC__ +# define GCC_VERSION (__GNUC__ * 10000 \ + + __GNUC_MINOR__ * 100 \ + + __GNUC_PATCHLEVEL__) +/* assert gcc version is at least 4.9.3 */ +# if GCC_VERSION < 40903 +# error "Please use gcc version 4.9.3 or newer!" +# endif +#endif + +#if (dg_configUSE_AUTO_CHIP_DETECTION == 1) + + /* use a register description that is generic enough for our needs */ +# include "DA14680AE.h" + +#else + +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A +# if dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_E +# include "DA14680AE.h" +# else +# error "Unknown chip stepping for revision A -- check the value of dg_configBLACK_ORCA_IC_STEP" +# endif +#elif dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B +# if dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_A +# include "DA14680BA.h" +# else +# error "Unknown chip stepping for revision B -- check the value of dg_configBLACK_ORCA_IC_STEP" +# endif +#else +# error "Unknown chip revision -- check the value of dg_configBLACK_ORCA_IC_REV" +#endif + +#endif + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_DA14680.h" /* DA14680AA System */ + +/************************ + * Memory map + ************************/ + +/** + * \brief Remapped device base address. + */ +#define MEMORY_REMAPPED_BASE 0x00000000UL +#define MEMORY_REMAPPED_END 0x04000000UL + +/** + * \brief Remapped device memory size (64MiB). + */ +#define MEMORY_REMAPPED_SIZE (MEMORY_REMAPPED_END - MEMORY_REMAPPED_BASE) + +/** + * \brief ROM base address. + */ +#define MEMORY_ROM_BASE 0x07F00000UL +#define MEMORY_ROM_END 0x07F40000UL + +/** + * \brief ROM memory size (256KiB). + */ +#define MEMORY_ROM_SIZE (MEMORY_ROM_END - MEMORY_ROM_BASE) + +/** + * \brief OTP Controller base address. + */ +#define MEMORY_OTPC_BASE 0x07F40000UL +#define MEMORY_OTPC_END 0x07F80000UL + +/** + * \brief OTP memory base address. + */ +#define MEMORY_OTP_BASE 0x07F80000UL +#define MEMORY_OTP_END 0x07FC0000UL + +/** + * \brief OTP memory size (256KiB). + */ +#define MEMORY_OTP_SIZE (MEMORY_OTP_END - MEMORY_OTP_BASE) + +/** + * \brief SYSTEM RAM base address. + */ +#define MEMORY_SYSRAM_BASE 0x07FC0000UL +#define MEMORY_SYSRAM_END 0x07FE0000UL + +/** + * \brief SYSTEM RAM size (128KiB). + */ +#define MEMORY_SYSRAM_SIZE (MEMORY_SYSRAM_END - MEMORY_SYSRAM_BASE) + +/** + * \brief CACHE RAM base address. + */ +#define MEMORY_CACHERAM_BASE 0x07FE0000UL +#define MEMORY_CACHERAM_END 0x08000000UL + +/** + * \brief CACHE RAM size (128KiB). + */ +#define MEMORY_CACHERAM_SIZE (MEMORY_CACHERAM_END - MEMORY_CACHERAM_BASE) + +/** + * \brief QSPI Flash base address. + */ +#define MEMORY_QSPIF_BASE 0x08000000UL +#define MEMORY_QSPIF_END 0x0BF00000UL + +/** + * \brief QSPI Flash memory size (63MiB). + */ +#define MEMORY_QSPIF_SIZE (MEMORY_QSPIF_END - MEMORY_QSPIF_BASE) + +/** + * \brief QSPI Controller base address. + */ +#define MEMORY_QSPIC_BASE 0x0C000000UL +#define MEMORY_QSPIC_END 0x0C100000UL + +/** + * \brief ECC engine microcode base address. + */ +#define MEMORY_ECC_UCODE_BASE 0x40030000UL + +/** + * \brief TRNG FIFO address + */ +#define MEMORY_TRNG_FIFO 0x40040000UL + +#define WITHIN_RANGE(_a, _s, _e) (((uint32_t)(_a) >= (uint32_t)(_s)) && ((uint32_t)(_a) < (uint32_t)(_e))) + +/** + * \brief Address is in the remapped memory region + */ +#define IS_REMAPPED_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_REMAPPED_BASE, MEMORY_REMAPPED_END) + +/** + * \brief Address is in the ROM region + */ +#define IS_ROM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_ROM_BASE, MEMORY_ROM_END) + +/** + * \brief Address is in the OTP memory region + */ +#define IS_OTP_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_OTP_BASE, MEMORY_OTP_END) + +/** + * \brief Address is in the OTP Controller memory region + */ +#define IS_OTPC_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_OTPC_BASE, MEMORY_OTPC_END) + +/** + * \brief Address is in the SYSTEM RAM region + */ +#define IS_SYSRAM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_SYSRAM_BASE, MEMORY_SYSRAM_END) + +/** + * \brief Address is in the CACHE RAM region + */ +#define IS_CACHERAM_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_CACHERAM_BASE, MEMORY_CACHERAM_END) + +/** + * \brief Address is in the QSPI Flash memory region + */ +#define IS_QSPIF_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_QSPIF_BASE, MEMORY_QSPIF_END) + +/** + * \brief Address is in the QSPI Controller memory region + */ +#define IS_QSPIC_ADDRESS(_a) WITHIN_RANGE((_a), MEMORY_QSPIC_BASE, MEMORY_QSPIC_END) + +#define _BLACK_ORCA_IC_VERSION(revision, stepping) \ + (((revision) << 8) | (stepping)) + +/** + * \brief Convenience macro to create the full chip version from revision and stepping. + * It takes letters as arguments. + */ +#define BLACK_ORCA_IC_VERSION(revision, stepping) \ + _BLACK_ORCA_IC_VERSION(BLACK_ORCA_IC_REV_##revision, \ + BLACK_ORCA_IC_STEP_##stepping) + +/** + * \brief The chip version that we compile for. + */ +#define BLACK_ORCA_TARGET_IC \ + _BLACK_ORCA_IC_VERSION(dg_configBLACK_ORCA_IC_REV, dg_configBLACK_ORCA_IC_STEP) + + +/** + * \brief Zero-initialized data retained memory attribute + */ +#define __RETAINED __attribute__((section("retention_mem_zi"))) // RetRAM0 +#define __RETAINED_1 __attribute__((section("retention_mem_1_zi"))) // RetRAM1 + +/** + * \brief Initialized data retained memory attribute + */ +#define __RETAINED_RW __attribute__((section("retention_mem_init"))) + +/** + * \brief Uninitialized data retained memory attribute + */ +#define __RETAINED_UNINIT __attribute__((section("retention_mem_uninit"))) + + /** + * \brief Constant data retained memory attribute + */ + #define __RETAINED_CONST_INIT __attribute__((section("retention_mem_const"))) + +/** + * \brief Text retained memory attribute + */ +#if ((dg_configCODE_LOCATION == NON_VOLATILE_IS_FLASH) && (dg_configEXEC_MODE == MODE_IS_CACHED)) +#define __RETAINED_CODE __attribute__((section("text_retained"))) __attribute__((noinline)) __attribute__((optimize ("no-tree-switch-conversion"))) +#else +#define __RETAINED_CODE +#endif + +/** + * \brief Attribute to tell the compiler to consider a symbol as used + */ +#define __USED __attribute__((used)) + +/** + * \brief Attribute to tell the compiler to consider a symbol as externally visible (for LTO) + */ +#define __LTO_EXT __attribute__((externally_visible)) + +extern uint32_t black_orca_chip_version; + +#define CHIP_IS_AE (black_orca_chip_version == BLACK_ORCA_IC_VERSION(A, E)) +#define CHIP_IS_BA (black_orca_chip_version == BLACK_ORCA_IC_VERSION(B, A)) + +/** + * \brief Get the chip version of the system, at runtime. + */ +__STATIC_INLINE uint32_t black_orca_get_chip_version(void) +{ + uint32_t rev = CHIP_VERSION->CHIP_REVISION_REG - 'A'; + uint32_t step = CHIP_VERSION->CHIP_TEST1_REG; + + return _BLACK_ORCA_IC_VERSION(rev, step); +} + +// Forward declaration +__RETAINED_CODE void hw_cpm_assert_trigger_gpio(void); + +/** + * \brief Assert as warning macro + * + * \note Active only while in development mode + */ +#define ASSERT_WARNING(a) \ + { \ + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ + if (!(a)) { \ + __asm volatile ( " cpsid i " ); \ + GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ + hw_cpm_assert_trigger_gpio(); \ + do {} while(1); \ + } \ + } \ + } + +/** + * \brief Assert as error macro + * + */ +#define ASSERT_ERROR(a) \ + { \ + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ + if (!(a)) { \ + __asm volatile ( " cpsid i " ); \ + GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ + hw_cpm_assert_trigger_gpio(); \ + do {} while(1); \ + } \ + } \ + else { \ + if (!(a)) { \ + __asm volatile ( " cpsid i " ); \ + __asm volatile ( " bkpt 2 " ); \ + } \ + } \ + } + +/** + * \brief Assert as warning macro when the system is still uninitialized + * + * \note Active only while in development mode. The SW cursor is not activated. + */ +#define ASSERT_WARNING_UNINIT(a) \ + { \ + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ + if (!(a)) { \ + __asm volatile ( " cpsid i " ); \ + GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ + do {} while(1); \ + } \ + } \ + } + +/** + * \brief Assert as error macro when the system is still uninitialized + * + * \note The SW cursor is not activated. + */ +#define ASSERT_ERROR_UNINIT(a) \ + { \ + if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \ + if (!(a)) { \ + __asm volatile ( " cpsid i " ); \ + GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \ + do {} while(1); \ + } \ + } \ + else { \ + if (!(a)) { \ + __asm volatile ( " cpsid i " ); \ + __asm volatile ( " bkpt 2 " ); \ + } \ + } \ + } + +/** + * \brief Macro to disable all interrupts + * + * This macro must always be used with GLOBAL_INT_RESTORE(). E.g. + * + * \code{.c} + * GLOBAL_INT_DISABLE(); + * ... code to be executed with interrupts disabled ... + * GLOBAL_INT_RESTORE(); + * \endcode + * + * \sa GLOBAL_INT_RESTORE + */ +#define GLOBAL_INT_DISABLE() \ + do { \ + unsigned int __l_irq_rest; \ + __asm volatile ("mrs %0, primask \n\t" \ + "mov r1, $1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (__l_irq_rest) \ + : \ + : "r1" \ + ); \ + DBG_CONFIGURE_HIGH(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); + +/** + * \brief Macro to restore all interrupts + * + * This macro must always be used after GLOBAL_INT_DISABLE(). E.g. + * + * \code{.c} + * GLOBAL_INT_DISABLE(); + * ... code to be executed with interrupts disabled ... + * GLOBAL_INT_RESTORE(); + * \endcode + * + * \sa GLOBAL_INT_DISABLE + */ +#define GLOBAL_INT_RESTORE() \ + if (__l_irq_rest == 0) { \ + DBG_CONFIGURE_LOW(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); \ + } \ + __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (__l_irq_rest) \ + : \ + ); \ + } while(0) + +#define containingoffset(address, type, field) ((type*)((uint8*)(address)-(size_t)(&((type*)0)->field))) + +/** + * \brief Macro the minimum of two values + * + * \param[in] a First value + * \param[in] b Second value + */ +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) + +/** + * \brief Macro the maximum of two values + * + * \param[in] a First value + * \param[in] b Second value + */ +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + +/** + * \brief Macro to swap the bytes of a 16-bit variable + * + * \param[in] a The 16-bit variable + */ +#if defined(__GNUC__) +#define SWAP16(a) __builtin_bswap16(a) +#else +#define SWAP16(a) ((a<<8) | (a>>8)) +#endif + +/** + * \brief Macro to swap the bytes of a 32-bit variable + * + * \param[in] a The 32-bit variable + */ +#if defined(__GNUC__) +#define SWAP32(a) __builtin_bswap32(a) +#else +#define SWAP32(a) ((a>>24 & 0xff) | (a>>8 & 0xff00) | (a<<8 & 0xff0000) | (a<<24 & 0xff000000)) +#endif + +#if defined(__GNUC__) +#define DEPRECATED __attribute__ ((deprecated)) +#else +#warning Deprecated macro must be implemented for this compiler +#define DEPRECATED +#endif + +#if defined(__GNUC__) +#define DEPRECATED_MSG(msg) __attribute__ ((deprecated(msg))) +#else +#warning Deprecated macro must be implemented for this compiler +#define DEPRECATED_MSG(msg) +#endif + +/* The following exist in ROM code */ +void __aeabi_memcpy(void *dest, const void *src, size_t n); +void __aeabi_memmove(void *dest, const void *src, size_t n); +void __aeabi_memset(void *dest, size_t n, int c); + +/** + * \brief Optimized memcpy + */ +#define OPT_MEMCPY __aeabi_memcpy + +/** + * \brief Optimized memmove + */ +#define OPT_MEMMOVE __aeabi_memmove + +/** + * \brief Optimized memset + */ +#define OPT_MEMSET(s, c, n) __aeabi_memset(s, n, c) + +/** + * \brief Access register field mask. + * + * Returns a register field mask (aimed to be used with local variables). + * e.g. + * \code + * uint16_t tmp; + * + * tmp = CRG_TOP->SYS_STAT_REG; + * + * if (tmp & REG_MSK(CRG_TOP, SYS_STAT_REG, XTAL16_TRIM_READY)) { + * ... + * \endcode + */ +#define REG_MSK(base, reg, field) \ + (base ## _ ## reg ## _ ## field ## _Msk) + +/** + * \brief Access register field position. + * + * Returns a register field position (aimed to be used with local variables). + */ +#define REG_POS(base, reg, field) \ + (base ## _ ## reg ## _ ## field ## _Pos) + +/** + * \brief Access register field value. + * + * Returns a register field value (aimed to be used with local variables). + * e.g. + * \code + * uint16_t tmp; + * int counter; + * tmp = CRG_TOP->TRIM_CTRL_REG; + * counter = REG_GET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp); + * ... + * \endcode + */ +#define REG_GET_FIELD(base, reg, field, var) \ + ((var & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ + (base ## _ ## reg ## _ ## field ## _Pos)) + +/** + * \brief Set register field value. + * + * Sets a register field value (aimed to be used with local variables). + * e.g. + * \code + * uint16_t tmp; + * + * tmp = CRG_TOP->TRIM_CTRL_REG; + * REG_SET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp, 10); + * REG_SET_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_TRIM_SELECT, tmp, 2); + * CRG_TOP->TRIM_CTRL_REG = tmp; + * ... + * \endcode + */ +#define REG_SET_FIELD(base, reg, field, var, val) \ + var = ((var & ~((base ## _ ## reg ## _ ## field ## _Msk))) | \ + (((val) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ + (base ## _ ## reg ## _ ## field ## _Msk))) + +/** + * \brief Clear register field value. + * + * Clears a register field value (aimed to be used with local variables). + * e.g. + * \code + * uint16_t tmp; + * + * tmp = CRG_TOP->TRIM_CTRL_REG; + * REG_CLR_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp); + * REG_CLR_FIELD(CRG_TOP, TRIM_CTRL_REG, XTAL_TRIM_SELECT, tmp); + * CRG_TOP->TRIM_CTRL_REG = tmp; + * ... + * \endcode + */ +#define REG_CLR_FIELD(base, reg, field, var) \ + var &= ~(base ## _ ## reg ## _ ## field ## _Msk) + + +/** + * \brief Return the value of a register field. + * + * e.g. + * \code + * uint16_t val; + * + * val = REG_GETF(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N); + * ... + * \endcode + */ +#define REG_GETF(base, reg, field) \ + (((base->reg) & (base##_##reg##_##field##_Msk)) >> (base##_##reg##_##field##_Pos)) + +/** + * \brief Set the value of a register field. + * + * e.g. + * \code + * + * REG_SETF(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, new_value); + * ... + * \endcode + */ +#define REG_SETF(base, reg, field, new_val) \ + base->reg = ((base->reg & ~(base##_##reg##_##field##_Msk)) | \ + ((base##_##reg##_##field##_Msk) & ((new_val) << (base##_##reg##_##field##_Pos)))) + +/** + * \brief Set a bit of a register. + * + * e.g. + * \code + * + * REG_SET_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); + * ... + * \endcode + */ +#define REG_SET_BIT(base, reg, field) \ + do { \ + base->reg |= (1 << (base##_##reg##_##field##_Pos)); \ + } while (0) + +/** + * \brief Clear a bit of a register. + * + * e.g. + * \code + * + * REG_CLR_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); + * ... + * \endcode + */ +#define REG_CLR_BIT(base, reg, field) \ + do { \ + base->reg &= ~(base##_##reg##_##field##_Msk); \ + } while (0) + +/** + * \brief Sets register bits, indicated by the mask, to a value. + * + * e.g. + * \code + * REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818); + * \endcode + */ +#define REG_SET_MASKED(base, reg, mask, value) \ + do { \ + base->reg = (base->reg & ~(mask)) | ((value) & (mask)); \ + } while (0) + +/** + * \brief Sets 16-bit wide register bits, indicated by the field, to a value v. + */ +#define BITS16(base, reg, field, v) \ + ((uint16) (((uint16) (v) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ + (base ## _ ## reg ## _ ## field ## _Msk))) + +/** + * \brief Sets 32-bit wide register bits, indicated by the field, to a value v. + */ +#define BITS32(base, reg, field, v) \ + ((uint32) (((uint32) (v) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ + (base ## _ ## reg ## _ ## field ## _Msk))) + +/** + * \brief Reads 16-bit wide register bits, indicated by the field, to a variable v. + */ +#define GETBITS16(base, reg, v, field) \ + ((uint16) (((uint16) (v)) & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ + (base ## _ ## reg ## _ ## field ## _Pos)) + +/** + * \brief Reads 32-bit wide register bits, indicated by the field, to a variable v. + */ +#define GETBITS32(base, reg, v, field) \ + ((uint32) (((uint32) (v)) & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ + (base ## _ ## reg ## _ ## field ## _Pos)) + +/** + * \brief Macro to enable the debugger + * + */ +#define ENABLE_DEBUGGER \ + do { \ + REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); \ + } while(0) + +/** + * \brief Macro to disable the debugger + * + */ +#define DISABLE_DEBUGGER \ + do { \ + REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); \ + } while(0) + + +/** + * \brief Macro to cause a software reset + * + */ +#define SWRESET \ + do { \ + REG_SET_BIT(GPREG, DEBUG_REG, SW_RESET); \ + } while (0) + +#define BIT0 0x01 +#define BIT1 0x02 +#define BIT2 0x04 +#define BIT3 0x08 +#define BIT4 0x10 +#define BIT5 0x20 +#define BIT6 0x40 +#define BIT7 0x80 + +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 + +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +typedef unsigned char uint8; // 8 bits +typedef char int8; // 8 bits +typedef unsigned short uint16; // 16 bits +typedef short int16; // 16 bits +typedef unsigned long uint32; // 32 bits +typedef long int32; // 32 bits +typedef unsigned long long uint64; // 64 bits +typedef long long int64; // 64 bits + +/* See also "Data Types" on pag. 21 of the (Doulos) Cortex-M0 / SoC 1.0 training documentation. */ +typedef unsigned char BYTE; // 8 bits = Byte +typedef unsigned short HWORD; // 16 bits = Halfword +typedef unsigned long WORD; // 32 bits = Word +typedef long long DWORD; // 64 bits = Doubleword + + +#ifdef __cplusplus +} +#endif + +#endif /* __SDK_DEFS_H__ */ + +/** + * \} + * \} + * \} + */ + diff --git a/third_party/dialog/DialogSDK/bsp/include/suota.h b/third_party/dialog/DialogSDK/bsp/include/suota.h old mode 100755 new mode 100644 index dc4937e2e..7862f4229 --- a/third_party/dialog/DialogSDK/bsp/include/suota.h +++ b/third_party/dialog/DialogSDK/bsp/include/suota.h @@ -41,6 +41,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * ***************************************************************************************** */ @@ -49,11 +50,16 @@ #include -#define SUOTA_VERSION_1_0 10 #define SUOTA_VERSION_1_1 11 +#define SUOTA_VERSION_1_2 12 +#define SUOTA_VERSION_1_3 13 #ifndef SUOTA_VERSION -#define SUOTA_VERSION SUOTA_VERSION_1_1 +#define SUOTA_VERSION SUOTA_VERSION_1_3 +#endif + +#if SUOTA_PSM && (SUOTA_VERSION < SUOTA_VERSION_1_2) +# error "SUOTA_PSM is only applicable to SUOTA_VERSION >= 1.2" #endif /** @@ -61,6 +67,8 @@ * * \brief SUOTA 1.1 product header as defined by Dialog SUOTA specification. * + * \note the same header is used for any SUOTA version newer than 1.1 + * */ typedef struct { uint8_t signature[2]; @@ -68,37 +76,18 @@ typedef struct { uint32_t current_image_location; uint32_t update_image_location; uint8_t reserved[8]; -} suota_1_1_product_header_t; +} __attribute__((packed)) suota_1_1_product_header_t; #define SUOTA_1_1_PRODUCT_HEADER_SIGNATURE_B1 0x70 #define SUOTA_1_1_PRODUCT_HEADER_SIGNATURE_B2 0x62 -#define SUOTA_1_0_PRODUCT_HEADER_SIGNATURE_B1 0x70 -#define SUOTA_1_0_PRODUCT_HEADER_SIGNATURE_B2 0x52 - -/** - * \struct suota_1_0_image_header_t - * - * \brief SUOTA 1.0 image header as defined by Dialog SUOTA specification. - * - */ -typedef struct { - uint8_t signature[2]; - uint8_t valid_flag; - uint8_t image_id; - uint32_t code_size; - uint32_t crc; - uint8_t version[16]; - uint32_t timestamp; - uint8_t encryption; - uint8_t reserved[31]; -} suota_1_0_image_header_t; - /** * \struct suota_1_1_image_header_t * * \brief SUOTA 1.1 image header as defined by Dialog SUOTA specification. * + * \note the same header is used for any SUOTA version newer than 1.1 + * */ typedef struct { uint8_t signature[2]; @@ -108,24 +97,17 @@ typedef struct { uint8_t version[16]; uint32_t timestamp; uint32_t exec_location; -} suota_1_1_image_header_t; +} __attribute__((packed)) suota_1_1_image_header_t; #define SUOTA_1_1_IMAGE_HEADER_SIGNATURE_B1 0x70 #define SUOTA_1_1_IMAGE_HEADER_SIGNATURE_B2 0x61 -#define SUOTA_1_0_IMAGE_HEADER_SIGNATURE_B1 0x70 -#define SUOTA_1_0_IMAGE_HEADER_SIGNATURE_B2 0x51 - #define SUOTA_1_1_IMAGE_FLAG_FORCE_CRC 0x01 #define SUOTA_1_1_IMAGE_FLAG_VALID 0x02 #define SUOTA_1_1_IMAGE_FLAG_RETRY1 0x04 #define SUOTA_1_1_IMAGE_FLAG_RETRY2 0x08 -#if (SUOTA_VERSION == SUOTA_VERSION_1_0) -typedef suota_1_0_image_header_t suota_image_header_t; -#else typedef suota_1_1_image_header_t suota_image_header_t; -#endif #endif /* SUOTA_H_ */ diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h old mode 100755 new mode 100644 index 4b41c366b..179089588 --- a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h +++ b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h @@ -4,8 +4,6 @@ * \addtogroup SYSTEM * \{ * \addtogroup MEMORY - * - * \brief QSPI flash access when running in auto mode * * \{ */ @@ -17,6 +15,14 @@ * * @brief Access QSPI flash when running in auto mode * + * The QSPI controller allows to execute code directly from QSPI flash. + * When code is executing from flash, it is not possible to reprogram the flash. + * To be able to modify the flash when it is used for code execution, it must me assured that + * for the time needed to erase/write, no code is running from flash. + * To achieve this, the code in this module is executed from the RAM. + * Code in this module will not access any other functions or constant variables that could reside + * in flash. + * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -41,6 +47,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -50,21 +57,43 @@ #include #include #include -#include +#include #include +#include "hw_cpm.h" +/* + * Debug options + */ +#if __DBG_QSPI_ENABLED +#define __DBG_QSPI_VOLATILE__ volatile +#pragma message "Automode: Debugging is on!" +#else +#define __DBG_QSPI_VOLATILE__ +#endif + + +/* + * Defines (generic) + */ + +/* Macros to put functions that need to be copied to ram in one section (retained) */ +#define QSPI_SECTION __attribute__((section ("text_retained"), optimize ("no-tree-switch-conversion"))) +#define QSPI_SECTION_NO_INLINE __attribute__ ((section ("text_retained"))) __attribute__ ((noinline)) + +typedef struct qspi_ucode_s { + const uint32_t *code; + uint8_t size; +} qspi_ucode_t; + +/* + * Flash specific defines + */ /** - * QSPI controller allows to execute code directly from QSPI flash. - * When code is executing from flash there is no possibility to reprogram it. - * To be able to modify flash memory while it is used for code execution it must me assured that - * for time needed for erase/write no code is running from flash. - * To achieve this code in this file allows to copy programming functions to RAM and execute it - * from there. - * Great flexibility is achieved by putting all code needed for flash modification in one section - * that will be copied to RAM. - * Code in this section will not access any other functions or constant variables (that could reside - * in flash). + * \brief SUS bit delay after SUSPEND command (in μsec) + * */ +#define FLASH_SUS_DELAY (20) + /** * \brief Get size of RAM buffer needed for code to modify QSPI flash. @@ -120,6 +149,11 @@ size_t qspi_automode_write_flash_page(uint32_t addr, const uint8_t *buf, size_t */ void qspi_automode_erase_flash_sector(uint32_t addr); +/** + * \brief Erase whole chip + */ +void qspi_automode_erase_chip(void); + /** * \brief Read flash memory * @@ -138,6 +172,8 @@ size_t qspi_automode_read(uint32_t addr, uint8_t *buf, size_t len); * * \returns address in CPU address space where data is located */ +static inline const void *qspi_automode_addr(uint32_t addr) __attribute__((always_inline)); + static inline const void *qspi_automode_addr(uint32_t addr) { return (const void *) (MEMORY_QSPIF_BASE + addr); @@ -146,15 +182,134 @@ static inline const void *qspi_automode_addr(uint32_t addr) /** * \brief Power up flash */ -void qspi_automode_flash_power_up(void); +QSPI_SECTION void qspi_automode_flash_power_up(void); + +/** + * \brief Set QSPI Flash into power down mode + */ +QSPI_SECTION void qspi_automode_flash_power_down(void); /** * \brief Init QSPI controller */ -bool qspi_automode_init(void); +__RETAINED_CODE bool qspi_automode_init(void); + +#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) +/** + * \brief Check if a program or sector erase operation is in progress + * + * \return bool True if the BUSY bit is set else false. + * + * \warning This function checks the value of the BUSY bit in the Status Register 1 of the Flash. It + * is the responsibility of the caller to call the function in the right context. The + * function must be called with interrupts disabled. + * + */ +__RETAINED_CODE bool qspi_check_program_erase_in_progress(void); + +/** + * \brief Suspend a Flash program or erase operation + * + * \details This function will try to suspend an ongoing program or erase procedure. The SUS bit is + * checked and the actual status is returned to the caller. Note that the program or erase + * procedure may have been completed before the suspend command is processed by the Flash. In + * this case the SUS bit will be left to 0. + * + * \return bool True if the procedure has been suspended. False if the procedure was not suspended + * successfully or had finished before the suspend command was processed by the Flash. + * + * \warning After the call to this function, the QSPI controller is set to auto mode and the Flash + * access to quad mode (if QUAD_MODE is 1). The function must be called with interrupts + * disabled. + * + */ +__RETAINED_CODE bool qspi_check_and_suspend(void); + +/** + * \brief Resume a Flash program or sector erase operation + * + * \warning After the call to this function, the QSPI controller is set to manual mode and the Flash + * access to single mode. The function must be called with interrupts disabled. + * + */ +__RETAINED_CODE void qspi_resume(void); + +/** + * \brief Erase a sector of the Flash in manual mode + * + * \param[in] addr The address of the sector to be erased. + * + * \warning This function does not block until the Flash has processed the command! The QSPI + * controller is left to manual mode after the call to this function. The function must be + * called with interrupts disabled. + * + */ +__RETAINED_CODE void flash_erase_sector_manual_mode(uint32_t addr); + +/** + * \brief Program data into a page of the Flash in manual mode + * + * \param[in] addr The address of the Flash where the data will be written. It may be anywhere in a + * page. + * \param[in] buf Pointer to the beginning of the buffer that contains the data to be written. + * \param[in] len The number of bytes to be written. + * + * \return size_t The number of bytes written. + * + * \warning The boundary of the page where addr belongs to, will not be crossed! The caller should + * issue another flash_program_page_manual_mode() call in order to write the remaining data + * to the next page. The QSPI controller is left to manual mode after the call to this + * function. The function must be called with interrupts disabled. + * + */ +__RETAINED_CODE size_t flash_program_page_manual_mode(uint32_t addr, const uint8_t *buf, + uint16_t len); +#endif + +/** + * \brief Activate Flash command entry mode + * + * \note After the call to this function, the QSPI controller is set to manual mode and the Flash + * access to single mode. + * + * \warning The function must be called with interrupts disabled. + * + */ +__RETAINED_CODE void flash_activate_command_entry_mode(void); + +/** + * \brief Deactivate Flash command entry mode + * + * \note After the call to this function, the QSPI controller is set to auto mode and the Flash + * access to quad mode (if QUAD_MODE is 1). + * + * \warning The function must be called with interrupts disabled. + * + */ +__RETAINED_CODE void flash_deactivate_command_entry_mode(void); + +/** + * \brief Configure Flash and QSPI controller for system clock frequency + * + * This function is used to change the Flash configuration of the QSPI controller + * to work with the system clock frequency defined in sys_clk. Dummy clock + * cycles could be changed here to support higher clock frequencies. + * QSPI controller clock divider could also be changed if the Flash + * maximum frequency is smaller than the system clock frequency. + * This function must be called before changing system clock frequency. + * + * \param [in] sys_clk System clock frequency + * + */ +__RETAINED_CODE void qspi_automode_sys_clock_cfg(sys_clk_t sys_clk); + +/** + * \brief Get ucode required for wake-up sequence + * \return qspi_ucode_t Pointer to the structure containing the ucode and ucode size + */ +const qspi_ucode_t *qspi_automode_get_ucode(void); #endif /* QSPI_AUTOMODE_H_ */ - /** * \} * \} diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h new file mode 100644 index 000000000..8b11078f2 --- /dev/null +++ b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h @@ -0,0 +1,173 @@ +/** + * \addtogroup BSP + * \{ + * \addtogroup SYSTEM + * \{ + * \addtogroup MEMORY + * + * \brief QSPI flash driver framework + * \{ + */ + +/** + **************************************************************************************** + * + * @file qspi_common.h + * + * @brief QSPI flash driver common definitions + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** + */ +#ifndef _QSPI_COMMON_H_ +#define _QSPI_COMMON_H_ + +#include "qspi_automode.h" + +/* + * Flash Commands + * + * Note: Default command issuing mode is single mode! If commands specific to other modes have to be + * issued then the mode must be changed! + */ +#define CMD_WRITE_STATUS_REGISTER 0x01 +#define CMD_WRITE_DISABLE 0x04 +#define CMD_READ_STATUS_REGISTER 0x05 +#define CMD_WRITE_ENABLE 0x06 +#define CMD_SECTOR_ERASE 0x20 +#define CMD_QUAD_PAGE_PROGRAM 0x32 +#define CMD_QUAD_IO_PAGE_PROGRAM 0x38 +#define CMD_BLOCK_ERASE 0x52 +#define CMD_CHIP_ERASE 0xC7 +#define CMD_FAST_READ_QUAD 0xEB +#define CMD_READ_JEDEC_ID 0x9F +#define CMD_EXIT_CONTINUOUS_MODE 0xFF +#define CMD_RELEASE_POWER_DOWN 0xAB +#define CMD_ENTER_POWER_DOWN 0xB9 + +#define CMD_FAST_READ_QUAD_4B 0xEC +#define CMD_SECTOR_ERASE_4B 0x21 +#define CMD_QUAD_PAGE_PROGRAM_4B 0x34 +#define CMD_QUAD_IO_PAGE_PROGRAM_4B 0x3E + +/* Erase/Write in progress */ +#define FLASH_STATUS_BUSY_BIT 0 +#define FLASH_STATUS_BUSY_MASK (1 << FLASH_STATUS_BUSY_BIT) + +/* WE Latch bit */ +#define FLASH_STATUS_WEL_BIT 1 +#define FLASH_STATUS_WEL_MASK (1 << FLASH_STATUS_WEL_BIT) + +typedef bool (*is_suspended_cb_t)(void); +typedef void (*initialize_cb_t)(uint8_t device_type, uint8_t device_density); +typedef void (*deactivate_command_entry_mode_cb_t)(void); +typedef void (*sys_clk_cfg_cb_t)(sys_clk_t type); +typedef uint8_t (*get_dummy_bytes_cb_t)(void); + +/** + * \brief QSPI Flash configuration structure + * + * This struct is used to define a driver for a specific QSPI flash. + * + * \note The struct instance must be declared as static const for this to work + */ +typedef struct qspi_flash_config { + // Function pointers + initialize_cb_t initialize; /**< Flash-specific initialization */ + is_suspended_cb_t is_suspended; /**< Check if flash is in erase/program + suspend state */ + deactivate_command_entry_mode_cb_t + deactivate_command_entry_mode; /**< Perform extra steps needed when command + entry mode is deactivated */ + sys_clk_cfg_cb_t sys_clk_cfg; /**< Perform Flash configuration when system clock + is changed (e.g. change dummy bytes or QSPIC + clock divider */ + get_dummy_bytes_cb_t get_dummy_bytes; /**< Return the number of dummy bytes currently + needed (they may e.g. change when the clock + changes) */ + uint8_t manufacturer_id; /**< The Flash JEDEC vendor ID (Cmd 0x9F, 1st byte) + This (and the device_type/device_density) + are needed for flash autodetection */ + uint8_t device_type; /**< The Flash JEDEC device type (Cmd 0x9F, 2nd byte) */ + uint8_t device_density; /**< The Flash JEDEC device type (Cmd 0x9F, 3rd byte) */ + uint8_t erase_opcode; /**< The Flash erase opcode to use */ + uint8_t erase_suspend_opcode; /**< The Flash erase suspend opcode to use */ + uint8_t erase_resume_opcode; /**< The Flash erase resume opcode to use */ + uint8_t page_program_opcode; /**< The Flash page program opcode to use */ + bool quad_page_program_address; /**< If true, the address will be transmitted in + QUAD mode when writing a page. Otherwise, it + will be transmitted in single mode */ + uint8_t read_erase_progress_opcode; /**< The opcode to use to check if erase is in progress + (Usually the Read Status Reg opcode (0x5)) */ + + uint8_t erase_in_progress_bit; /**< The bit to check when reading the erase progress */ + bool erase_in_progress_bit_high_level; /**< The active state (true: high, false: low) of the bit + above */ + uint8_t send_once; /**< If set to 1, the "Performance mode" (or burst, or + continuous; differs per vendor) will be used for read + accesses. In this mode, the read opcode is only sent + once, and subsequent accesses only transfer the address */ + uint8_t extra_byte; /**< The extra byte to transmit, when in "Performance mode" + (send once is 1), that tells the flash that it should + stay in this continuous, performance mode */ + HW_QSPI_ADDR_SIZE address_size; /**< Whether the flash works in 24- or 32-bit addressing mode */ + HW_QSPI_BREAK_SEQ_SIZE break_seq_size; /**< Whether the break sequence, that puts flash out of the + continuous mode, is one or two bytes long (the break byte is + 0xFF) */ + qspi_ucode_t ucode_wakeup; /**< The QSPIC microcode to use to setup the flash on wakeup. This + is automatically used by the QSPI Controller after wakeup, and + before CPU starts code execution. This is different based on + whether flash was active, in deep power down or completely off + while the system was sleeping */ + uint16_t power_down_delay; /**< This is the time, in usec, needed for the flash to go to power + down, after the Power Down command is issued */ + uint16_t release_power_down_delay; /**< This is the time, in usec, needed for the flash to exit the power + down mode, after the Release Power Down command is issued */ +} qspi_flash_config_t; + +extern const qspi_flash_config_t* flash_config_init; +#if (FLASH_AUTODETECT == 1) +extern qspi_flash_config_t *flash_config; +#else +extern const qspi_flash_config_t * const flash_config; +#endif + +static void qspi_write(const uint8_t *wbuf, size_t wlen); +static void qspi_transact(const uint8_t *wbuf, size_t wlen, uint8_t *rbuf, size_t rlen); +static uint8_t flash_read_status_register(void); +static void flash_write_status_register(uint8_t value); +static void flash_write_enable(void); +static void qspi_automode_set_dummy_bytes_count(uint8_t count); +static bool flash_is_busy(void); +static inline bool flash_erase_program_in_progress(void); + +#endif /* _QSPI_COMMON_H_ */ +/** + * \} + * \} + * \} + */ diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h new file mode 100644 index 000000000..eb37fd3bb --- /dev/null +++ b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h @@ -0,0 +1,114 @@ +/** + * \addtogroup BSP + * \{ + * \addtogroup SYSTEM + * \{ + * \addtogroup MEMORY + * + * \{ + */ + +/** + **************************************************************************************** + * + * @file qspi_w25q80ew.h + * + * @brief QSPI flash driver for the Winbond W25Q80EW + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************** + */ +#ifndef _QSPI_W32Q80EW_H_ +#define _QSPI_W32Q80EW_H_ + +#ifndef WINBOND_ID +#define WINBOND_ID 0xEF +#endif + +// Device type using command 0x9F +#define W25Q80EW 0x60 + +#ifndef W25Q_8Mb_SIZE +#define W25Q_8Mb_SIZE 0x14 +#endif + +#if (FLASH_AUTODETECT == 1) || (dg_configFLASH_MANUFACTURER_ID == WINBOND_ID && \ + dg_configFLASH_DEVICE_TYPE == W25Q80EW && dg_configFLASH_DENSITY == W25Q_8Mb_SIZE) + +#include "qspi_common.h" + +#include "qspi_winbond.h" + +static void flash_w25q80ew_sys_clock_cfg(sys_clk_t sys_clk); +static uint8_t flash_w25q80ew_get_dummy_bytes(void); + +static const qspi_flash_config_t flash_w25q80ew_config = { + .manufacturer_id = WINBOND_ID, + .device_type = W25Q80EW, + .device_density = W25Q_8Mb_SIZE, + .is_suspended = flash_w25q_is_suspended, + .initialize = flash_w25q_initialize, + .deactivate_command_entry_mode = flash_w25q_deactivate_command_entry_mode, + .sys_clk_cfg = flash_w25q80ew_sys_clock_cfg, + .get_dummy_bytes = flash_w25q80ew_get_dummy_bytes, + .break_seq_size = HW_QSPI_BREAK_SEQ_SIZE_1B, + .address_size = HW_QSPI_ADDR_SIZE_24, + .page_program_opcode = CMD_QUAD_PAGE_PROGRAM, + .quad_page_program_address = false, + .erase_opcode = CMD_SECTOR_ERASE, + .erase_suspend_opcode = W25Q_ERASE_PROGRAM_SUSPEND, + .erase_resume_opcode = W25Q_ERASE_PROGRAM_RESUME, + .read_erase_progress_opcode = CMD_READ_STATUS_REGISTER, + .erase_in_progress_bit = FLASH_STATUS_BUSY_BIT, + .erase_in_progress_bit_high_level = true, + .send_once = 1, + .extra_byte = 0xA0, + .ucode_wakeup = {w25q_ucode_wakeup, sizeof(w25q_ucode_wakeup)}, + .power_down_delay = W25Q_POWER_DOWN_DELAY_US, + .release_power_down_delay = W25Q_RELEASE_POWER_DOWN_DELAY_US, +}; + +#if (FLASH_AUTODETECT == 0) + const qspi_flash_config_t* const flash_config = &flash_w25q80ew_config; +#endif + +QSPI_SECTION static void flash_w25q80ew_sys_clock_cfg(sys_clk_t sys_clk) +{ + +} + +QSPI_SECTION static uint8_t flash_w25q80ew_get_dummy_bytes(void) +{ + return 2; +} +#endif + +#endif /* _QSPI_W32Q80EW_H_ */ +/** + * \} + * \} + * \} + */ diff --git a/third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h new file mode 100644 index 000000000..38e6eb07d --- /dev/null +++ b/third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h @@ -0,0 +1,236 @@ +/** + * \addtogroup BSP + * \{ + * \addtogroup SYSTEM + * \{ + * \addtogroup MEMORY + * + * \{ + */ + +/** + **************************************************************************************** + * + * @file qspi_winbond.h + * + * @brief QSPI flash driver for Winbond flashes - common code + * + * Copyright (c) 2016, Dialog Semiconductor + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + **************************************************************************************** + */ +#ifndef _QSPI_WINBOND_H_ +#define _QSPI_WINBOND_H_ + +#define WINBOND_ID 0xEF + +#if (FLASH_AUTODETECT == 1) || (dg_configFLASH_MANUFACTURER_ID == WINBOND_ID) +#include "qspi_common.h" + +#define W25Q_ERASE_PROGRAM_SUSPEND 0x75 +#define W25Q_ERASE_PROGRAM_RESUME 0x7A + +#define W25Q_WRITE_STATUS_REGISTER2 0x31 +#define W25Q_PAGE_PROGRAM 0x02 +#define W25Q_WRITE_ENABLE_NON_VOL 0x50 +#define W25Q_READ_STATUS_REGISTER2 0x35 +#define W25Q_BLOCK_ERASE_64K 0xD8 +#define W25Q_FAST_READ_QPI 0x0B +#define W25Q_READ_DEVICE_ID_SINGLE 0x90 // Requires single mode for the command entry! +#define W25Q_READ_DEVICE_ID_DUAL 0x92 // Requires dual mode for the command entry! +#define W25Q_READ_DEVICE_ID_QUAD 0x94 +#define W25Q_READ_UNIQUE_ID 0x4B // Requires single mode for the command entry! +#define W25Q_READ_SFDP_REG 0x5A // Requires single mode for the command entry! +#define W25Q_ERASE_SECURITY_REGS 0x44 // Requires single mode for the command entry! +#define W25Q_PROGR_SECURITY_REGS 0x42 // Requires single mode for the command entry! +#define W25Q_READ_SECURITY_REGS 0x48 // Requires single mode for the command entry! +#define W25Q_ENTER_QPI_MODE 0x38 // Requires single mode for the command entry! +#define W25Q_EXIT_QPI_MODE 0xFF // Requires quad mode for the command entry! + +/* Suspend */ +#define W25Q_STATUS2_SUS_BIT 7 +#define W25Q_STATUS2_SUS_MASK (1 << W25Q_STATUS2_SUS_BIT) + +/* QPI Enable */ +#define W25Q_STATUS2_QE_BIT 1 +#define W25Q_STATUS2_QE_MASK (1 << W25Q_STATUS2_QE_BIT) + +// Flash power up/down timings +#define W25Q_POWER_DOWN_DELAY_US 3 +#define W25Q_RELEASE_POWER_DOWN_DELAY_US 3 +#define W25Q_POWER_UP_DELAY_US 10 + +#if (dg_configFLASH_POWER_OFF == 1) +/** + * \brief uCode for handling the QSPI FLASH activation from power off. + */ + /* + * Should work with all Winbond flashes -- verified with W25Q80EW. + * + * Delay 10usec + * 0x01 // CMD_NBYTES = 0, CMD_TX_MD = 0 (Single), CMD_VALID = 1 + * 0xA0 // CMD_WT_CNT_LS = 160 --> 10000 / 62.5 = 160 = 10usec + * 0x00 // CMD_WT_CNT_MS = 0 + * Exit from Fast Read mode + * 0x09 // CMD_NBYTES = 1, CMD_TX_MD = 0 (Single), CMD_VALID = 1 + * 0x00 // CMD_WT_CNT_LS = 0 + * 0x00 // CMD_WT_CNT_MS = 0 + * 0xFF // Enable Reset + * (up to 16 words) + */ + const uint32_t w25q_ucode_wakeup[] = { + 0x09000001 | (((uint16_t)(W25Q_POWER_UP_DELAY_US*1000/62.5) & 0xFFFF) << 8), + 0x00FF0000, + }; +#elif (dg_configFLASH_POWER_DOWN == 1) +/** + * \brief uCode for handling the QSPI FLASH release from power-down. + */ + /* + * Should work with all Winbond flashes -- verified with W25Q80EW. + * + * 0x09 // CMD_NBYTES = 1, CMD_TX_MD = 0 (Single), CMD_VALID = 1 + * 0x30 // CMD_WT_CNT_LS = 3000 / 62.5 = 48 // 3usec + * 0x00 // CMD_WT_CNT_MS = 0 + * 0xAB // Release Power Down + * (up to 16 words) + */ + const uint32_t w25q_ucode_wakeup[] = { + 0xAB000009 | (((uint16_t)(W25Q_RELEASE_POWER_DOWN_DELAY_US*1000/62.5) & 0xFFFF) << 8), + }; +#else +/** + * \brief uCode for handling the QSPI FLASH exit from the "Continuous Read Mode". + */ + /* + * Should work with all Winbond flashes -- verified with W25Q80EW. + * + * 0x25 // CMD_NBYTES = 4, CMD_TX_MD = 2 (Quad), CMD_VALID = 1 + * 0x00 // CMD_WT_CNT_LS = 0 + * 0x00 // CMD_WT_CNT_MS = 0 + * 0x55 // Clocks 0-1 (A23-16) + * 0x55 // Clocks 2-3 (A15-8) + * 0x55 // Clocks 4-5 (A7-0) + * 0x55 // Clocks 6-7 (M7-0) : M5-4 != '10' ==> Disable "Continuous Read Mode" + * (up to 16 words) + */ + const uint32_t w25q_ucode_wakeup[] = { + 0x55000025, + 0x00555555, + }; +#endif + +static bool flash_w25q_is_suspended(void); +static void flash_w25q_initialize(uint8_t device_type, uint8_t device_density); +static void flash_w25q_deactivate_command_entry_mode(void); + +/** + * \brief Enable volatile writes to Status Register bits + * \details When this command is issued, any writes to any of the Status Registers of the Flash are + * done as volatile writes. This command is valid only when the Write Status Register command + * follows. + * + * \note This function blocks until the Flash has processed the command. + */ +QSPI_SECTION __attribute__((unused)) static inline void flash_w25q_wre_volatile(void) +{ + uint8_t cmd[] = { W25Q_WRITE_ENABLE_NON_VOL }; + + qspi_write(cmd, 1); + + /* Verify */ + while (flash_is_busy()); +} + +QSPI_SECTION __attribute__((unused)) static inline uint8_t flash_w25q_read_status_register_2(void) +{ + __DBG_QSPI_VOLATILE__ uint8_t status; + uint8_t cmd[] = { W25Q_READ_STATUS_REGISTER2 }; + + qspi_transact(cmd, 1, &status, 1); + + return status; +} + +/** + * \brief Write the Status Register 2 of the Flash + * + * \param[in] value The value to be written. + * + * \note This function blocks until the Flash has processed the command. No verification that the + * value has been actually written is done though. It is up to the caller to decide whether + * such verification is needed or not and execute it on its own. + */ +QSPI_SECTION __attribute__((unused)) static inline void flash_w25q_write_status_register_2(uint8_t value) +{ + uint8_t cmd[] = { W25Q_WRITE_STATUS_REGISTER2, value }; + + qspi_write(cmd, 2); + + /* Wait for the Flash to process the command */ + while (flash_is_busy()); +} + +QSPI_SECTION static inline void flash_w25q_enable_quad_mode(void) +{ + uint8_t status; + + status = flash_w25q_read_status_register_2(); + if (!(status & W25Q_STATUS2_QE_MASK)) { + flash_write_enable(); + flash_w25q_write_status_register_2(status | W25Q_STATUS2_QE_MASK); + } +} + +QSPI_SECTION static bool flash_w25q_is_suspended(void) +{ + __DBG_QSPI_VOLATILE__ uint8_t status; + + status = flash_w25q_read_status_register_2(); + return (status & W25Q_STATUS2_SUS_MASK) != 0; +} + +QSPI_SECTION static void flash_w25q_initialize(uint8_t device_type, uint8_t device_density) +{ + flash_activate_command_entry_mode(); + + flash_w25q_enable_quad_mode(); + + flash_deactivate_command_entry_mode(); +} + +QSPI_SECTION static void flash_w25q_deactivate_command_entry_mode(void) +{ +} + +#endif + +#endif /* _QSPI_WINBOND_H_ */ +/** + * \} + * \} + * \} + */ diff --git a/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c b/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c index da2cdbb9a..7fe7ab474 100644 --- a/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c +++ b/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c @@ -29,249 +29,380 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ #include #include #include -#include -#include +#include "sdk_defs.h" + +#include "hw_cpm.h" + +#include "hw_qspi.h" +#include "qspi_automode.h" /* * QSPI controller allows to execute code directly from QSPI flash. * When code is executing from flash there is no possibility to reprogram it. * To be able to modify flash memory while it is used for code execution it must me assured that - * for time needed for erase/write no code is running from flash. - * To achieve this code in this file allows to copy programming functions to RAM and execute it - * from there. - * Great flexibility is achieved by putting all code needed for flash modification in one section - * that will be copied to RAM. - * Code in this section will not access any other functions or constant variables (that could reside - * in flash). + * during the time needed for erase/write no code is running from flash. */ -/* Erase/Write in progress */ -#define W25Q_STATUS1_BUSY_BIT 0 -#define W25Q_STATUS1_BUSY_MASK (1 << W25Q_STATUS1_BUSY_BIT) +/* + * Flash specific defines + */ -#define W25Q_STATUS1_WEL_BIT 1 -#define W25Q_STATUS1_WEL_MASK (1 << W25Q_STATUS1_WEL_BIT) +/* SUS bit delay after SUSPEND command */ +#define FLASH_SUS_DELAY (20) // in usec -#define W25Q_WRITE_STATUS_REGISTER 0x01 -#define W25Q_PAGE_PROGRAM 0x02 -#define W25Q_WRITE_DISABLE 0x04 -#define W25Q_READ_STATUS_REGISTER1 0x05 -#define W25Q_WRITE_ENABLE 0x06 -#define W25Q_SECTOR_ERASE 0x20 -#define W25Q_QUAD_PAGE_PROGRAM 0x32 -#define W25Q_READ_STATUS_REGISTER2 0x35 -#define W25Q_BLOCK_ERASE 0x52 -#define W25Q_ERASE_PROGRAM_SUSPEND 0x75 -#define W25Q_ERASE_PROGRAM_RESUME 0x7A -#define W25Q_BLOCK_ERASE_64K 0xD8 -#define W25Q_CHIP_ERASE 0xC7 -#define W25Q_RELEASE_POWER_DOWN 0xAB -#define W25Q_FAST_READ_QUAD 0xEB - -#define FLASH_MAX_WRITE_SIZE dg_configFLASH_MAX_WRITE_SIZE +/* Flash page size */ +#define FLASH_MAX_WRITE_SIZE dg_configFLASH_MAX_WRITE_SIZE /* * Use QUAD mode for page write. - * If flash does not support QUAD mode or it is not connected for QUAD mode set it to 0. + * + * Note: If the flash does not support QUAD mode or it is not connected for QUAD mode set it to 0 + * (single mode). */ #ifndef QUAD_MODE -#define QUAD_MODE 1 +#define QUAD_MODE 1 #endif #ifndef ERASE_IN_AUTOMODE -#define ERASE_IN_AUTOMODE 1 +#define ERASE_IN_AUTOMODE 1 +#endif + +#ifndef FLASH_FORCE_24BIT_ADDRESSING +#define FLASH_FORCE_24BIT_ADDRESSING 0 // Force 24 bit addressing for devices > 128Mbits #endif /* - * Macros to put functions that need to be copied to ram in one section. + * WARNING: The Autodetect mode will greatly increase both the code and the used RetRAM size!!!! + * Use with extreme caution!! */ -#define QSPI_SECTION __attribute__ ((section ("text_retained"))) -#define QSPI_SECTION_NOINLINE __attribute__ ((section ("text_retained"), noinline)) +#if dg_configFLASH_AUTODETECT == 1 +#define FLASH_AUTODETECT 1 // Enable Flash auto-detection +#else +#if !defined(dg_configFLASH_MANUFACTURER_ID) +#error Please define dg_configFLASH_MANUFACTURER_ID !!! +#endif +#if !defined(dg_configFLASH_DEVICE_TYPE) +#error Please define dg_configFLASH_DEVICE_TYPE !!! +#endif +#if !defined(dg_configFLASH_DENSITY) +#error Please define dg_configFLASH_DENSITY !!! +#endif +#define FLASH_AUTODETECT 0 +#endif + +#if FLASH_AUTODETECT == 1 +#include "qspi_w25q80ew.h" +#include "qspi_mx25u51245.h" +#include "qspi_gd25lq80b.h" +#else +#ifndef dg_configFLASH_HEADER_FILE +#error Please define macro dg_configFLASH_HEADER_FILE to the header file name that contains the respective implementation +#endif +#include dg_configFLASH_HEADER_FILE +#endif + +#if (FLASH_AUTODETECT == 1) + +static const qspi_flash_config_t *flash_config_table[] = +{ + &flash_w25q80ew_config, // This is the default one + &flash_mx25u51245_config, + &flash_gd25lq80b_config, +}; + +__RETAINED static qspi_flash_config_t flash_autodetect_config; + +__RETAINED qspi_flash_config_t *flash_config; + +#endif + -QSPI_SECTION static uint8_t flash_read_status_register_1(void); /* - * Set bus mode to single or QUAD mode. - * Flash does not support DUAL page program so it is not supported here. + * Function definitions */ -QSPI_SECTION static inline void qspi_set_bus_mode(HW_QSPI_BUS_MODE mode) + +/** + * \brief Set bus mode to single or QUAD mode. + * + * \param[in] mode Can be single (HW_QSPI_BUS_MODE_SINGLE) or quad (HW_QSPI_BUS_MODE_QUAD) mode. + * + * \note DUAL mode page program so is not supported by this function. + */ +static inline void qspi_set_bus_mode(HW_QSPI_BUS_MODE mode) __attribute__((always_inline)); + +static inline void qspi_set_bus_mode(HW_QSPI_BUS_MODE mode) { if (mode == HW_QSPI_BUS_MODE_SINGLE) { QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_SINGLE); + QSPIC->QSPIC_CTRLMODE_REG |= + BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, 1) | + BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_DAT, 1) | + BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, 1) | + BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_DAT, 1); } else { #if QUAD_MODE QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_QUAD); + QSPIC->QSPIC_CTRLMODE_REG &= + ~(BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, 1) | + BITS32(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, 1)); #endif } } -/* - * Enable CS +/** + * \brief Set the mode of the QSPI controller (manual or auto) + * + * \param[in] automode True for auto and false for manual mode setting. */ -QSPI_SECTION static inline void qspi_cs_enable(void) -{ - QSPIC->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk; -} +static inline void qspi_set_automode(bool automode) __attribute__((always_inline)); -/* - * Disable CS - */ -QSPI_SECTION static inline void qspi_cs_disable(void) -{ - QSPIC->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk; -} - -/* - * Write 8 bits to QSPI bus. - */ -QSPI_SECTION static inline void qspi_write8(uint8_t data) -{ - *((volatile uint8_t *) & (QSPIC->QSPIC_WRITEDATA_REG)) = data; -} - -/* - * Write 32 bits to QSPI bus. - * It creates more efficient transmission then 8 bits write. - */ -QSPI_SECTION static inline void qspi_write32(uint32_t data) -{ - QSPIC->QSPIC_WRITEDATA_REG = data; -} - -/* - * Read byte from QSPI bus. - */ -QSPI_SECTION static inline uint8_t qspi_read8(void) -{ - return *((volatile uint8_t *) & (QSPIC->QSPIC_READDATA_REG)); -} - -/* - * Escape continues read mode that could be programmed in auto mode. - * Without this when controller is switched to manual mode it could treat incoming - * commands as addresses. - */ -QSPI_SECTION static inline void flash_reset_continuous_mode(void) -{ - qspi_cs_enable(); - qspi_write8(0xFF); - qspi_cs_disable(); -} - -QSPI_SECTION uint8_t flash_release_power_down(void) -{ - uint8_t id; - - qspi_cs_enable(); - qspi_write32(0x000000AB); - id = qspi_read8(); - qspi_cs_disable(); - - while (flash_read_status_register_1() & W25Q_STATUS1_BUSY_MASK); - - return id; -} - -/* - * Get auto mode state of controller. - */ -QSPI_SECTION static inline bool qspi_get_automode(void) -{ - return REG_GETF(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_AUTO_MD); -} - -/* - * Set auto or manual mode - */ -QSPI_SECTION static inline void qspi_set_automode(bool automode) +static inline void qspi_set_automode(bool automode) { REG_SETF(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_AUTO_MD, automode); } -/* - * Write bytes on QSPI bus. +/** + * \brief Write to the Flash the contents of a buffer + * + * \param[in] wbuf Pointer to the beginning of the buffer + * \param[in] wlen The number of bytes to be written + * + * \note The data are transferred as bytes (8 bits wide). No optimization is done in trying to use + * faster access methods (i.e. transfer words instead of bytes whenever it is possible). */ QSPI_SECTION static void qspi_write(const uint8_t *wbuf, size_t wlen) { size_t i; - qspi_cs_enable(); + hw_qspi_cs_enable(); for (i = 0; i < wlen; ++i) { - qspi_write8(wbuf[i]); + hw_qspi_write8(wbuf[i]); } - qspi_cs_disable(); + hw_qspi_cs_disable(); } -/* - * Do write then read transaction on QSPI bus. +/** + * \brief Write an arbitrary number of bytes to the Flash and then read an arbitrary number of bytes + * from the Flash in one transaction + * + * \param[in] wbuf Pointer to the beginning of the buffer that contains the data to be written + * \param[in] wlen The number of bytes to be written + * \param[in] rbuf Pointer to the beginning of the buffer than the read data are stored + * \param[in] rlen The number of bytes to be read + * + * \note The data are transferred as bytes (8 bits wide). No optimization is done in trying to use + * faster access methods (i.e. transfer words instead of bytes whenever it is possible). */ -QSPI_SECTION static void qspi_transact(const uint8_t *wbuf, size_t wlen, uint8_t *rbuf, - size_t rlen) +QSPI_SECTION static void qspi_transact(const uint8_t *wbuf, size_t wlen, uint8_t *rbuf, size_t rlen) { size_t i; - qspi_cs_enable(); + hw_qspi_cs_enable(); for (i = 0; i < wlen; ++i) { - qspi_write8(wbuf[i]); + hw_qspi_write8(wbuf[i]); } for (i = 0; i < rlen; ++i) { - rbuf[i] = qspi_read8(); + rbuf[i] = hw_qspi_read8(); } - qspi_cs_disable(); + hw_qspi_cs_disable(); } +QSPI_SECTION static inline bool flash_erase_program_in_progress(void) __attribute__((always_inline)); -/* - * Enable write to flash. - * Must be called before every write and erase. +QSPI_SECTION static inline bool flash_erase_program_in_progress(void) +{ + __DBG_QSPI_VOLATILE__ uint8_t status; + uint8_t cmd[] = { flash_config->read_erase_progress_opcode }; + + qspi_transact(cmd, 1, &status, 1); + + return ((status & (1 << flash_config->erase_in_progress_bit)) != 0) == flash_config->erase_in_progress_bit_high_level; +} + +QSPI_SECTION static inline bool flash_is_busy(void) __attribute__((always_inline)); + +QSPI_SECTION static inline bool flash_is_busy(void) +{ + return (flash_read_status_register() & FLASH_STATUS_BUSY_MASK) != 0; +} + +/** + * \brief Exit from continuous mode. + */ +QSPI_SECTION static inline void flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE break_seq_size) __attribute__(( + always_inline)); + +QSPI_SECTION static inline void flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE break_seq_size) +{ + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_EXIT_CONTINUOUS_MODE); + + if (break_seq_size == HW_QSPI_BREAK_SEQ_SIZE_2B) + { + hw_qspi_write8(CMD_EXIT_CONTINUOUS_MODE); + } + + hw_qspi_cs_disable(); + + while (flash_is_busy()); +} + +/** + * \brief Get Device ID when Flash is not in Power Down mode + * + * \return uint8_t The Device ID of the Flash + * + * \note The function blocks until the Flash executes the command. + */ +QSPI_SECTION __attribute__((unused)) static uint8_t flash_get_id(void) +{ + uint8_t id; + + hw_qspi_cs_enable(); + hw_qspi_write32(CMD_RELEASE_POWER_DOWN); + id = hw_qspi_read8(); + hw_qspi_cs_disable(); + + while (flash_is_busy()); + + return id; +} + +/** + * \brief Set WEL (Write Enable Latch) bit of the Status Register of the Flash + * \details The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, + * Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers + * instruction. In the case of Write Status Register command, any status bits will be written + * as non-volatile bits. + * + * \note This function blocks until the Flash has processed the command and it will be repeated if, + * for any reason, the command was not successfully executed by the Flash. */ QSPI_SECTION static void flash_write_enable(void) { - uint8_t status; - uint8_t cmd[] = { W25Q_WRITE_ENABLE }; + __DBG_QSPI_VOLATILE__ uint8_t status; + uint8_t cmd[] = { CMD_WRITE_ENABLE }; do { qspi_write(cmd, 1); + /* Verify */ do { - status = flash_read_status_register_1(); + status = flash_read_status_register(); } - while (status & W25Q_STATUS1_BUSY_MASK); + while (status & FLASH_STATUS_BUSY_MASK); } - while (!(status & W25Q_STATUS1_WEL_MASK)); + while (!(status & FLASH_STATUS_WEL_MASK)); } +/** + * \brief Read the Status Register 1 of the Flash + * + * \return uint8_t The value of the Status Register 1 of the Flash. + */ +QSPI_SECTION static uint8_t flash_read_status_register(void) +{ + __DBG_QSPI_VOLATILE__ uint8_t status; + uint8_t cmd[] = { CMD_READ_STATUS_REGISTER }; + + qspi_transact(cmd, 1, &status, 1); + + return status; +} + +/** + * \brief Write the Status Register 1 of the Flash + * + * \param[in] value The value to be written. + * + * \note This function blocks until the Flash has processed the command. No verification that the + * value has been actually written is done though. It is up to the caller to decide whether + * such verification is needed or not and execute it on its own. + */ +QSPI_SECTION __attribute__((unused)) static void flash_write_status_register(uint8_t value) +{ + uint8_t cmd[2] = { CMD_WRITE_STATUS_REGISTER, value }; + + qspi_write(cmd, 2); + + /* Wait for the Flash to process the command */ + while (flash_is_busy()); +} + +/** + * \brief Fast copy of a buffer to a FIFO + * \details Implementation of a fast copy of the contents of a buffer to a FIFO in assembly. All + * addresses are word aligned. + * + * \param[in] start Pointer to the beginning of the buffer + * \param[in] end Pointer to the end of the buffer + * \param[in] Pointer to the FIFO + * + * \warning No validity checks are made! It is the responsibility of the caller to make sure that + * sane values are passed to this function. + */ +static inline +void fast_write_to_fifo32(uint32_t start, uint32_t end, uint32_t dest) __attribute__((always_inline)); + +static inline void fast_write_to_fifo32(uint32_t start, uint32_t end, uint32_t dest) +{ + __asm volatile("copy: \n" + " ldmia %[start]!, {r3} \n" + " str r3, [%[dest]] \n" + " cmp %[start], %[end] \n" + " blt copy \n" + : + : /* output */ + [start] "l"(start), [end] "r"(end), [dest] "l"(dest) : /* inputs (%0, %1, %2) */ + "r3"); /* registers that are destroyed */ +} + +/** + * \brief Write data (up to 1 page) to Flash + * + * \param[in] addr The address of the Flash where the data will be written. It may be anywhere in a + * page. + * \param[in] buf Pointer to the beginning of the buffer that contains the data to be written. + * \param[in] size The number of bytes to be written. + * + * \return size_t The number of bytes written. + * + * \warning The boundary of the page where addr belongs to, will not be crossed! The caller should + * issue another flash_write_page() call in order to write the remaining data to the next + * page. + */ QSPI_SECTION static size_t flash_write_page(uint32_t addr, const uint8_t *buf, uint16_t size) { size_t i = 0; size_t odd = ((uint32_t) buf) & 3; + size_t size_aligned32; + size_t tmp; + + DBG_SET_HIGH(FLASH_DEBUG, FLASHDBG_PAGE_PROG); flash_write_enable(); - qspi_cs_enable(); - - qspi_write32((QUAD_MODE ? W25Q_QUAD_PAGE_PROGRAM : W25Q_PAGE_PROGRAM) | - ((addr >> 8) & 0xFF00) | ((addr << 8) & 0xFF0000) | (addr << 24)); - /* Reduce max write size, that can reduce interrupt latency time */ if (size > FLASH_MAX_WRITE_SIZE) { @@ -279,14 +410,55 @@ QSPI_SECTION static size_t flash_write_page(uint32_t addr, const uint8_t *buf, u } /* Make sure write will not cross page boundary */ - if ((addr & 0xFF) + size > 256) + tmp = 256 - (addr & 0xFF); + + if (size > tmp) { - size = 256 - ((addr + 256) & 0xFF); + size = tmp; } + hw_qspi_cs_enable(); + + if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) + { + hw_qspi_write8(flash_config->page_program_opcode); #if QUAD_MODE - qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + + if (flash_config->quad_page_program_address == true) + { + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + } + #endif + hw_qspi_write32((addr >> 24) | ((addr >> 8) & 0xFF00) | ((addr << 8) & 0xFF0000) | (addr << 24)); +#if QUAD_MODE + + if (flash_config->quad_page_program_address == false) + { + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); + } + +#endif + } + else + { + if (flash_config->quad_page_program_address == true) + { + hw_qspi_write8(flash_config->page_program_opcode); +#if QUAD_MODE + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); +#endif + hw_qspi_write16(((addr >> 16) & 0xFF) | (addr & 0xFF00)); + hw_qspi_write8(addr & 0xFF); + } + else + { + hw_qspi_write32(CMD_QUAD_PAGE_PROGRAM | ((addr >> 8) & 0xFF00) | ((addr << 8) & 0xFF0000) | (addr << 24)); +#if QUAD_MODE + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); +#endif + } + } if (odd) { @@ -294,102 +466,91 @@ QSPI_SECTION static size_t flash_write_page(uint32_t addr, const uint8_t *buf, u for (i = 0; i < odd && i < size; ++i) { - qspi_write8(buf[i]); + hw_qspi_write8(buf[i]); } } - for (; i + 3 < size; i += 4) + size_aligned32 = ((size - i) & ~0x3); + + if (size_aligned32) { - qspi_write32(*((uint32_t *) &buf[i])); + fast_write_to_fifo32((uint32_t)(buf + i), (uint32_t)(buf + i + size_aligned32), + (uint32_t) & (QSPIC->QSPIC_WRITEDATA_REG)); + i += size_aligned32; } for (; i < size; i++) { - qspi_write8(*((uint8_t *) &buf[i])); + hw_qspi_write8(buf[i]); } + hw_qspi_cs_disable(); + + DBG_SET_LOW(FLASH_DEBUG, FLASHDBG_PAGE_PROG); + #if QUAD_MODE qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); #endif - qspi_cs_disable(); - return i; } -/* - * Read flash status register. - * It is important not to go to auto mode before flash finishes write or erase. +/** + * \brief Erase a sector of the Flash + * + * \param[in] addr The address of the sector to be erased. + * + * \note This function blocks until the Flash has processed the command. */ -QSPI_SECTION static uint8_t flash_read_status_register_1(void) +QSPI_SECTION __attribute__((unused)) static void flash_erase_sector(uint32_t addr) { - uint8_t status; - uint8_t cmd[] = { W25Q_READ_STATUS_REGISTER1 }; - - qspi_transact(cmd, 1, &status, 1); - - return status; -} - -#if !ERASE_IN_AUTOMODE -/* - * Erase flash sector 4KB command. - */ -QSPI_SECTION static void flash_erase_sector(uint32_t addr) -{ - uint8_t cmd[4] = { W25Q_SECTOR_ERASE, addr >> 16, addr >> 8, addr }; - flash_write_enable(); - qspi_write(cmd, 4); -} -#endif + if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) + { + uint8_t cmd[5] = { flash_config->erase_opcode, addr >> 24, addr >> 16, addr >> 8, addr }; + qspi_write(cmd, 5); + } + else + { + uint8_t cmd[4] = { flash_config->erase_opcode, addr >> 16, addr >> 8, addr }; + qspi_write(cmd, 4); + } -QSPI_SECTION static inline uint8_t qspi_get_erase_status(void) -{ - QSPIC->QSPIC_CHCKERASE_REG = 0; - return HW_QSPIC_REG_GETF(ERASECTRL, ERS_STATE); + + /* Wait for the Flash to process the command */ + while (flash_erase_program_in_progress()); } -QSPI_SECTION static inline HW_QSPI_ADDR_SIZE qspi_get_address_size(void) +/** + * \brief Check if the Flash can accept commands + * + * \return bool True if the Flash is not busy else false. + * + */ +QSPI_SECTION_NO_INLINE static bool qspi_writable(void) { - return (HW_QSPI_ADDR_SIZE)HW_QSPIC_REG_GETF(CTRLMODE, USE_32BA); -} - -QSPI_SECTION_NOINLINE static bool qspi_writable(void) -{ - bool am = qspi_get_automode(); bool writable; /* - * From now on QSPI may not be available, turn of interrupts. + * From now on QSPI may not be available, turn off interrupts. */ GLOBAL_INT_DISABLE(); /* - * Turn off auto mode to allow write. + * Turn on command entry mode. */ - qspi_set_automode(false); - - /* - * Set default mode for commands. - */ - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - - /* - * Exit continues mode, after this flash will interpret commands again. - */ - flash_reset_continuous_mode(); + flash_activate_command_entry_mode(); /* * Check if flash is ready. */ - writable = !(flash_read_status_register_1() & W25Q_STATUS1_BUSY_MASK); + writable = !(flash_is_busy()); /* * Restore auto mode. */ - qspi_set_automode(am); + flash_deactivate_command_entry_mode(); /* * Let other code to be executed including QSPI one. @@ -399,10 +560,211 @@ QSPI_SECTION_NOINLINE static bool qspi_writable(void) return writable; } -/* - * Erase sector using QSPI controller. +/** + * \brief Get the status of an Erase when it is done automatically by the QSPI controller + * + * \return uint8_t The status of the Erase + * 0: No Erase + * 1: Pending erase request + * 2: Erase procedure is running + * 3: Suspended Erase procedure + * 4: Finishing the Erase procedure */ -QSPI_SECTION static void qspi_erase_sector(uint32_t addr) +QSPI_SECTION static uint8_t qspi_get_erase_status(void) +{ + QSPIC->QSPIC_CHCKERASE_REG = 0; + + return HW_QSPIC_REG_GETF(ERASECTRL, ERS_STATE); +} + +/** + * \brief Get the address size used by the QSPI controller + * + * \return The address size used (HW_QSPI_ADDR_SIZE_24 or HW_QSPI_ADDR_SIZE_32). + */ +static inline HW_QSPI_ADDR_SIZE qspi_get_address_size(void) __attribute__((always_inline)); + +static inline HW_QSPI_ADDR_SIZE qspi_get_address_size(void) +{ + return (HW_QSPI_ADDR_SIZE)HW_QSPIC_REG_GETF(CTRLMODE, USE_32BA); +} + +__RETAINED_CODE void flash_activate_command_entry_mode(void) +{ + /* + * Turn off auto mode to allow write. + */ + qspi_set_automode(false); + + /* + * Switch to single mode for command entry. + */ + qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); + + /* + * Exit continuous mode (QPI mode), after this the flash will interpret commands again. + */ + if (flash_config->send_once != 0) + { + flash_reset_continuous_mode(flash_config->break_seq_size); + } +} + + +__RETAINED_CODE void flash_deactivate_command_entry_mode(void) +{ + flash_config->deactivate_command_entry_mode(); + +#if QUAD_MODE + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); +#endif + qspi_set_automode(true); +} + +#if (dg_configDISABLE_BACKGROUND_FLASH_OPS == 0) +__RETAINED_CODE void flash_erase_sector_manual_mode(uint32_t addr) +{ + /* + * Turn on command entry mode. + */ + flash_activate_command_entry_mode(); + + /* + * Issue the erase sector command. + */ + flash_write_enable(); + + if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) + { + uint8_t cmd[5] = { flash_config->erase_opcode, addr >> 24, addr >> 16, addr >> 8, addr }; + qspi_write(cmd, 5); + } + else + { + uint8_t cmd[4] = { flash_config->erase_opcode, addr >> 16, addr >> 8, addr }; + qspi_write(cmd, 4); + } + + /* + * Flash stays in manual mode. + */ +} + +__RETAINED_CODE size_t flash_program_page_manual_mode(uint32_t addr, const uint8_t *buf, uint16_t size) +{ + size_t written = flash_write_page(addr, buf, size); + + /* + * Flash stays in manual mode. + */ + + return written; +} + +__RETAINED_CODE bool qspi_check_program_erase_in_progress(void) +{ + return flash_is_busy(); +} + +__RETAINED_CODE bool qspi_check_and_suspend(void) +{ + uint8_t cmd[] = { flash_config->erase_suspend_opcode }; + bool am = hw_qspi_get_automode(); + bool ret = true; + + if (am) + { + /* + * Turn on command entry mode. + */ + flash_activate_command_entry_mode(); + } + + /* + * Suspend action. + */ + DBG_SET_HIGH(FLASH_DEBUG, FLASHDBG_SUSPEND_ACTION); + + /* + * Check if an operation is ongoing. + */ + while (flash_erase_program_in_progress()) + { + qspi_write(cmd, 1); + } + + hw_cpm_delay_usec(FLASH_SUS_DELAY); // Wait for SUS bit to be updated + + DBG_SET_LOW(FLASH_DEBUG, FLASHDBG_SUSPEND_ACTION); + + if (flash_config->is_suspended() == false) + { + ret = false; + } + + /* + * Restore auto mode. + */ + flash_deactivate_command_entry_mode(); + + return ret; +} + +__RETAINED_CODE void qspi_resume(void) +{ + uint8_t cmd[] = { flash_config->erase_resume_opcode }; + + do + { + /* + * Turn on command entry mode. + */ + flash_activate_command_entry_mode(); + + /* + * Check if suspended. + */ + if (flash_config->is_suspended() == false) + { + break; + } + + /* + * Wait for flash to become ready again. + */ + do + { + /* + * Resume action. + */ + qspi_write(cmd, 1); + + /* + * Check if SUS bit is cleared. + */ + } + while (flash_config->is_suspended()); + } + while (0); + + /* + * Flash stays in manual mode. + */ +} +#endif + +/** + * \brief Erase sector (via CPM background processing or using the QSPI controller) + * + * \details This function will execute a Flash sector erase operation. The operation will either be + * carried out immediately (dg_configDISABLE_BACKGROUND_FLASH_OPS is set to 1) or it will be + * deferred to be executed by the CPM when the system becomes idle (when + * dg_configDISABLE_BACKGROUND_FLASH_OPS is set to 0, default value). In the latter case, the + * caller will block until the CPM completes the registered erase operation. + * + * \param[in] addr The address of the sector to be erased. + */ +QSPI_SECTION_NO_INLINE static void qspi_erase_sector(uint32_t addr) { /* Wait for previous erase to end */ while (qspi_get_erase_status() != 0) @@ -420,19 +782,32 @@ QSPI_SECTION static void qspi_erase_sector(uint32_t addr) /* Setup erase block page */ HW_QSPIC_REG_SETF(ERASECTRL, ERS_ADDR, addr); + /* Fire erase */ HW_QSPIC_REG_SETF(ERASECTRL, ERASE_EN, 1); } -/* - * Write page to flash. - * This function blocks interrupts switches to manual mode, writes page (or less) of data. - * Then it waits for flash to become ready before switching back to auto mode. - * Make sure that buf does not point to QSPI mapped memory. +/** + * \brief Write data to a page in the Flash (via CPM background processing or using the QSPI + * controller) + * + * \details This function will execute a Flash program page operation. The operation will either be + * carried out immediately (dg_configDISABLE_BACKGROUND_FLASH_OPS is set to 1) or it will be + * deferred to be executed by the CPM when the system becomes idle (when + * dg_configDISABLE_BACKGROUND_FLASH_OPS is set to 0, default value). In the latter case, the + * caller will block until the CPM completes the registered page program operation. + * + * \param[in] addr The address of the Flash where the data will be written. It may be anywhere in a + * page. + * \param[in] buf Pointer to the beginning of the buffer that contains the data to be written. + * \param[in] size The number of bytes to be written. + * + * \return size_t The number of bytes written. + * + * \warning The caller should ensure that buf does not point to QSPI mapped memory. */ -QSPI_SECTION_NOINLINE static size_t write_page(uint32_t addr, const uint8_t *buf, uint16_t size) +QSPI_SECTION_NO_INLINE static size_t write_page(uint32_t addr, const uint8_t *buf, uint16_t size) { - bool am = qspi_get_automode(); size_t written; /* @@ -441,36 +816,22 @@ QSPI_SECTION_NOINLINE static size_t write_page(uint32_t addr, const uint8_t *buf GLOBAL_INT_DISABLE(); /* - * Turn off auto mode to allow write. + * Turn on command entry mode. */ - qspi_set_automode(false); + flash_activate_command_entry_mode(); /* - * Set default mode for commands. - */ - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - - /* - * Exit continues mode, after this flash will interpret commands again. - */ - flash_reset_continuous_mode(); - - while (flash_read_status_register_1() & W25Q_STATUS1_BUSY_MASK); - - /* - * Write page of data. + * Write data into the page of the Flash. */ written = flash_write_page(addr, buf, size); - /* - * Wait for flash to become ready again. - */ - while (flash_read_status_register_1() & W25Q_STATUS1_BUSY_MASK); + /* Wait for the Flash to process the command */ + while (flash_erase_program_in_progress()); /* * Restore auto mode. */ - qspi_set_automode(am); + flash_deactivate_command_entry_mode(); /* * Let other code to be executed including QSPI one. @@ -480,12 +841,21 @@ QSPI_SECTION_NOINLINE static size_t write_page(uint32_t addr, const uint8_t *buf return written; } -/* - * Erase flash sector. - * This function blocks interrupts switches to manual mode, erases sector. - * Then it waits for flash to become ready before switching back to auto mode. +/** + * \brief Erase a sector of the Flash + * + * \details The time and the way that the operation will be carried out depends on the following + * settings: + * ERASE_IN_AUTOMODE = 0: the command is issued immediately in manual mode + * ERASE_IN_AUTOMODE = 1: + * dg_configDISABLE_BACKGROUND_FLASH_OPS = 0: the operation is executed manually by the + * CPM when the system becomes idle + * dg_configDISABLE_BACKGROUND_FLASH_OPS = 1: the operation is executed automatically + * by the QSPI controller. + * + * \param[in] addr The address of the sector to be erased. */ -QSPI_SECTION_NOINLINE static void erase_sector(uint32_t addr) +QSPI_SECTION_NO_INLINE static void erase_sector(uint32_t addr) { #if ERASE_IN_AUTOMODE /* @@ -501,8 +871,6 @@ QSPI_SECTION_NOINLINE static void erase_sector(uint32_t addr) } #else - bool am = qspi_get_automode(); - /* * From now on QSPI may not be available, turn of interrupts. */ @@ -513,34 +881,27 @@ QSPI_SECTION_NOINLINE static void erase_sector(uint32_t addr) */ qspi_set_automode(false); - /* - * Set default mode for commands. - */ qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); + /* + * Get the Flash out of Power Down mode. + */ flash_release_power_down(); /* - * Exit continues mode, after this flash will interpret commands again. + * Exit continuous mode, after this the flash will interpret commands again. */ - flash_reset_continuous_mode(); - - while (flash_read_status_register_1() & W25Q_STATUS1_BUSY_MASK); + flash_reset_continuous_mode(flash_config->break_seq_size); /* * Execute erase command. */ flash_erase_sector(addr); - /* - * Wait for flash to become ready again. - */ - while (flash_read_status_register_1() & W25Q_STATUS1_BUSY_MASK); - /* * Restore auto mode. */ - qspi_set_automode(am); + flash_deactivate_command_entry_mode(); /* * Let other code to be executed including QSPI one. @@ -583,6 +944,28 @@ void qspi_automode_erase_flash_sector(uint32_t addr) erase_sector(addr); } +void qspi_automode_erase_chip(void) +{ + flash_activate_command_entry_mode(); + + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_WRITE_ENABLE); + hw_qspi_cs_disable(); + + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_CHIP_ERASE); + hw_qspi_cs_disable(); + + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_READ_STATUS_REGISTER); + + while (hw_qspi_read8() & FLASH_STATUS_BUSY_MASK); + + hw_qspi_cs_disable(); + + flash_deactivate_command_entry_mode(); +} + size_t qspi_automode_read(uint32_t addr, uint8_t *buf, size_t len) { memcpy(buf, (void *)(MEMORY_QSPIF_BASE + addr), len); @@ -590,62 +973,193 @@ size_t qspi_automode_read(uint32_t addr, uint8_t *buf, size_t len) return len; } -void qspi_automode_flash_power_up(void) +QSPI_SECTION void qspi_automode_flash_power_up(void) { - if (dg_configCODE_LOCATION != NON_VOLATILE_IS_FLASH) - { - bool am = qspi_get_automode(); + hw_cpm_delay_usec(flash_config->power_down_delay); - /* - * Turn off auto mode to allow write. - */ - qspi_set_automode(false); + /* Interrupts must be turned off since the flash goes in manual mode, and + * code (e.g. for an ISR) cannot be fetched from flash during this time + */ + GLOBAL_INT_DISABLE(); - /* - * Set default mode for commands. - */ - qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); + // Do not call flash_activate_command_entry_mode(). This function will call + // flash_reset_continuous_mode which will try to send break sequence to the QSPI Flash + // which is in power-down mode. + qspi_set_automode(false); + qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); - flash_release_power_down(); + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_RELEASE_POWER_DOWN); + hw_qspi_cs_disable(); - /* - * Restore auto mode. - */ - qspi_set_automode(am); - } + flash_deactivate_command_entry_mode(); + + /* + * The flash is in auto mode again. Re-enable the interrupts + */ + GLOBAL_INT_RESTORE(); + + hw_cpm_delay_usec(flash_config->release_power_down_delay); } -static const qspi_config qspi_cfg = +QSPI_SECTION void qspi_automode_flash_power_down(void) +{ + flash_activate_command_entry_mode(); + + hw_qspi_cs_enable(); + hw_qspi_write8(CMD_ENTER_POWER_DOWN); + hw_qspi_cs_disable(); + +// Do not call flash_deactivate_command_entry_mode(). This function will call +// flash_config->deactivate_command_entry_mode() which will try to send commands to the QSPI Flash +// which has already been set in power-down mode. + +// flash_deactivate_command_entry_mode(); + +#if QUAD_MODE + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); +#endif + qspi_set_automode(true); +} + +static qspi_config qspi_cfg = { HW_QSPI_ADDR_SIZE_24, HW_QSPI_POL_HIGH, HW_QSPI_SAMPLING_EDGE_NEGATIVE }; -bool qspi_automode_init(void) +/** + * \brief Read the JEDEC manufacturer ID, device type and device density using command 0x9F + * + * \param[in] manufacturer_id Pointer to the variable where the manufacturer ID will be returned + * \param[in] device_type Pointer to the variable where the device type will be returned + * \param[in] density Pointer to the variable where the device density will be returned + */ +#if FLASH_AUTODETECT +QSPI_SECTION static void flash_read_jedec_id(uint8_t *manufacturer_id, uint8_t *device_type, uint8_t *density) { + uint8_t cmd[] = { CMD_READ_JEDEC_ID }; + uint8_t buffer[3]; + + qspi_set_automode(false); + qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE); + + // reset continuous mode using both one and two break bytes to cover all cases + flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE_2B); + flash_reset_continuous_mode(HW_QSPI_BREAK_SEQ_SIZE_1B); + + qspi_transact(cmd, 1, buffer, 3); + *manufacturer_id = buffer[0]; + *device_type = buffer[1]; + *density = buffer[2]; + +#if QUAD_MODE + qspi_set_bus_mode(HW_QSPI_BUS_MODE_QUAD); +#endif + qspi_set_automode(true); +} +#endif + +/** + * \brief Configure dummy bytes in QSPI controller + * + * \param[in] count Number of dummy bytes (not including extra byte) + */ +QSPI_SECTION __attribute__((unused)) static void qspi_automode_set_dummy_bytes_count(uint8_t count) +{ + if (count == 3) + { + HW_QSPIC_REG_SETF(BURSTCMDB, DMY_FORCE, 1); + } + else + { + QSPIC->QSPIC_BURSTCMDB_REG = + (QSPIC->QSPIC_BURSTCMDB_REG & + ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE) | + REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM))) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, + dummy_num[count]); + } +} + +__RETAINED_CODE bool qspi_automode_init(void) +{ + uint8_t device_type; + uint8_t device_density; + hw_qspi_enable_clock(); + +#if __DBG_QSPI_ENABLED + REG_SETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV, 3); +#endif + +#if FLASH_AUTODETECT + uint8_t manufacturer_id; + uint8_t i; + + + flash_read_jedec_id(&manufacturer_id, &device_type, &device_density); + + const qspi_flash_config_t *flash_config_init = flash_config_table[0]; // default to first entry. + + for (i = 0; i < sizeof(flash_config_table) / sizeof(qspi_flash_config_t *); i++) + { + if ((flash_config_table[i]->manufacturer_id == manufacturer_id) && + (flash_config_table[i]->device_type == device_type) && + (flash_config_table[i]->device_density == device_density)) + { + flash_config_init = flash_config_table[i]; + break; + } + } + + flash_autodetect_config = *flash_config_init; + flash_config = &flash_autodetect_config; +#else + device_type = dg_configFLASH_DEVICE_TYPE; + device_density = dg_configFLASH_DENSITY; +#endif + + /* + * Copy the selected flash struct from flash into retram + */ + flash_config->initialize(device_type, device_density); + + uint8_t read_opcode; + + if (flash_config->address_size == HW_QSPI_ADDR_SIZE_32) + { + read_opcode = CMD_FAST_READ_QUAD_4B; + qspi_cfg.address_size = HW_QSPI_ADDR_SIZE_32; // It will be set when hw_qspi_init() is called + } + else + { + read_opcode = CMD_FAST_READ_QUAD; + } + /* * Setup erase instruction that will be sent by QSPI controller to erase sector in automode. */ - hw_qspi_set_erase_instruction(W25Q_SECTOR_ERASE, HW_QSPI_BUS_MODE_SINGLE, - HW_QSPI_BUS_MODE_SINGLE, 8, 5); + hw_qspi_set_erase_instruction(flash_config->erase_opcode, HW_QSPI_BUS_MODE_SINGLE, + HW_QSPI_BUS_MODE_SINGLE, 15, 5); /* * Setup instruction pair that will temporarily suspend erase operation to allow read. */ - hw_qspi_set_suspend_resume_instructions(W25Q_ERASE_PROGRAM_SUSPEND, HW_QSPI_BUS_MODE_SINGLE, - W25Q_ERASE_PROGRAM_RESUME, HW_QSPI_BUS_MODE_SINGLE, 7); + hw_qspi_set_suspend_resume_instructions(flash_config->erase_suspend_opcode, HW_QSPI_BUS_MODE_SINGLE, + flash_config->erase_resume_opcode, HW_QSPI_BUS_MODE_SINGLE, 7); /* * QSPI controller must send write enable before erase, this sets it up. */ - hw_qspi_set_write_enable_instruction(W25Q_WRITE_ENABLE, HW_QSPI_BUS_MODE_SINGLE); + hw_qspi_set_write_enable_instruction(CMD_WRITE_ENABLE, HW_QSPI_BUS_MODE_SINGLE); /* * Setup instruction that will be used to periodically check erase operation status. * Check LSB which is 1 when erase is in progress. */ - hw_qspi_set_read_status_instruction(W25Q_READ_STATUS_REGISTER1, HW_QSPI_BUS_MODE_SINGLE, - HW_QSPI_BUS_MODE_SINGLE, W25Q_STATUS1_BUSY_BIT, 1, 20, 0); + hw_qspi_set_read_status_instruction(flash_config->read_erase_progress_opcode, HW_QSPI_BUS_MODE_SINGLE, + HW_QSPI_BUS_MODE_SINGLE, flash_config->erase_in_progress_bit, flash_config->erase_in_progress_bit_high_level ? 1 : 0, + 20, 0); /* * This sequence is necessary if flash is working in continuous read mode, when instruction @@ -655,7 +1169,7 @@ bool qspi_automode_init(void) * If flash is working in DUAL bus mode sequence should be 0xFFFF and size should be * HW_QSPI_BREAK_SEQ_SIZE_2B. */ - hw_qspi_set_break_sequence(0xFFFF, HW_QSPI_BUS_MODE_SINGLE, HW_QSPI_BREAK_SEQ_SIZE_1B, 0); + hw_qspi_set_break_sequence(0xFFFF, HW_QSPI_BUS_MODE_SINGLE, flash_config->break_seq_size, 0); /* * If application starts from FLASH then bootloader must have set read instruction. @@ -664,17 +1178,43 @@ bool qspi_automode_init(void) { hw_qspi_init(&qspi_cfg); hw_qspi_set_div(HW_QSPI_DIV_1); - flash_reset_continuous_mode(); - hw_qspi_set_read_instruction(W25Q_FAST_READ_QUAD, 1, 2, HW_QSPI_BUS_MODE_SINGLE, - HW_QSPI_BUS_MODE_QUAD, HW_QSPI_BUS_MODE_QUAD, - HW_QSPI_BUS_MODE_QUAD); - - hw_qspi_set_extra_byte(0xA0, HW_QSPI_BUS_MODE_QUAD, 1); - - hw_qspi_set_automode(true); } - HW_QSPIC_REG_SETF(BURSTCMDB, CS_HIGH_MIN, 1); +#ifdef ENABLE_AUTOMODE_CONFIGURATION_FOR_READ + flash_activate_command_entry_mode(); + + hw_qspi_set_read_instruction(read_opcode, flash_config->send_once, flash_config->get_dummy_bytes(), + HW_QSPI_BUS_MODE_SINGLE, + HW_QSPI_BUS_MODE_QUAD, HW_QSPI_BUS_MODE_QUAD, + HW_QSPI_BUS_MODE_QUAD); + hw_qspi_set_extra_byte(flash_config->extra_byte, HW_QSPI_BUS_MODE_QUAD, 0); + hw_qspi_set_address_size(flash_config->address_size); + + flash_deactivate_command_entry_mode(); + + HW_QSPIC_REG_SETF(BURSTCMDB, CS_HIGH_MIN, 0); +#else + (void) read_opcode; +#endif return true; } + +QSPI_SECTION void qspi_automode_sys_clock_cfg(sys_clk_t sys_clk) +{ + if ((CRG_TOP->CLK_AMBA_REG & (1 << REG_POS(CRG_TOP, CLK_AMBA_REG, QSPI_ENABLE))) != 0) // If clock is enabled + { + /* Some of the sys_clk_cfg() implementations put the flash in command entry mode, where the flash is + * not available for code execution. We must make sure that no interrupt (that may cause a cache miss) + * hits during this time. + */ + GLOBAL_INT_DISABLE(); + flash_config->sys_clk_cfg(sys_clk); + GLOBAL_INT_RESTORE(); + } +} + +const qspi_ucode_t *qspi_automode_get_ucode(void) +{ + return &flash_config->ucode_wakeup; +} diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h old mode 100755 new mode 100644 index c3b5c4478..835820d1d --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h @@ -5,15 +5,16 @@ \{ \addtogroup CPM \{ +\brief Clock and Power Manager */ /** **************************************************************************************** -* -* @file hw_cpm.h -* -* @brief Clock and Power Manager header file. -* + * + * @file hw_cpm.h + * + * @brief Clock and Power Manager header file. + * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -38,6 +39,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -46,12 +48,7 @@ #if dg_configUSE_HW_CPM -#include "black_orca.h" - -#define PRIVILEGED_DATA __attribute__((section("privileged_data_zi"))) - - - +#include "sdk_defs.h" #define SYS_CLK_IS_XTAL16M (0) #define SYS_CLK_IS_RC16 (1) @@ -61,6 +58,7 @@ #define LP_CLK_IS_RC32K (0) #define LP_CLK_IS_RCX (1) #define LP_CLK_IS_XTAL32K (2) +#define LP_CLK_IS_EXTERNAL (3) #define DCDC_IS_READY \ (REG_MSK(DCDC, DCDC_STATUS_1_REG, DCDC_VDD_AVAILABLE)) @@ -100,9 +98,9 @@ typedef enum ahbdiv_type { ahb_div16, //!< Divide by 16 } ahb_div_t; - ahb_div_t cm_ahbclk; sys_clk_t cm_sysclk; + /** * \brief The AMBA Peripheral Bus (APB) clock divider * @@ -134,6 +132,14 @@ typedef enum cpu_clk_type { } cpu_clk_t; +/** + * \brief The TCS setting for the BOD control. + * \details If it is zero then the hard-coded SDK code for the BOD setup is used. It it is not zero, + * this is the value that is written to the BOD_CTRL2_REG. + */ +extern uint16_t hw_cpm_bod_enabled_in_tcs; + + /** * \brief Turn on the 1.2V LDO. * @@ -165,13 +171,26 @@ __STATIC_INLINE void hw_cpm_set_cache_retained(void) GLOBAL_INT_RESTORE(); } +/** + * \brief Enable ECC microcode RAM retainment. + * + */ +__STATIC_INLINE void hw_cpm_set_eccram_retained(void) +{ + GLOBAL_INT_DISABLE(); + REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RETAIN_ECCRAM); + GLOBAL_INT_RESTORE(); +} + /** * \brief Enable QSPI initialization after wake-up. * */ __STATIC_INLINE void hw_cpm_enable_qspi_init(void) { + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, QSPI_INIT); + GLOBAL_INT_RESTORE(); } /** @@ -185,61 +204,50 @@ __STATIC_INLINE void hw_cpm_setup_retmem(void) GLOBAL_INT_RESTORE(); } -/** - * \brief Setup the Retention Memory configuration when the image data have to be retained. - * - */ -__STATIC_INLINE void hw_cpm_setup_retmem_no_img_copy(void) -{ - GLOBAL_INT_DISABLE(); - REG_SETF(CRG_TOP, PMU_CTRL_REG, RETAIN_RAM, dg_configMEM_RETENTION_MODE_PRESERVE_IMAGE); - GLOBAL_INT_RESTORE(); -} - /** * \brief Disable memory retention. * - * \warning Interrupts must be disabled by the caller! - * */ __STATIC_INLINE void hw_cpm_no_retmem(void) { - CRG_TOP->PMU_CTRL_REG &= ~(REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_RAM) | - REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_CACHE) | + GLOBAL_INT_DISABLE(); + CRG_TOP->PMU_CTRL_REG &= ~(REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_RAM) | + REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_CACHE) | REG_MSK(CRG_TOP, PMU_CTRL_REG, RETAIN_ECCRAM)); + GLOBAL_INT_RESTORE(); } /** * \brief Enable the clock-less sleep mode. * - * \warning Interrupts must be disabled by the caller! - * */ __STATIC_INLINE void hw_cpm_enable_clockless(void) { + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, ENABLE_CLKLESS); + GLOBAL_INT_RESTORE(); } /** * \brief Disable the clock-less sleep mode. * - * \warning Interrupts must be disabled by the caller! - * */ __STATIC_INLINE void hw_cpm_disable_clockless(void) { + GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, ENABLE_CLKLESS); + GLOBAL_INT_RESTORE(); } /** * \brief Activate the "Reset on wake-up" functionality. * - * \warning Interrupts must be disabled by the caller! - * */ __STATIC_INLINE void hw_cpm_enable_reset_on_wup(void) { + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RESET_ON_WAKEUP); + GLOBAL_INT_RESTORE(); } /** @@ -254,6 +262,14 @@ __RETAINED_CODE void hw_cpm_activate_bod_protection(void); */ void hw_cpm_activate_bod_protection_at_init(void); +/** + * \brief Configure BOD protection. + * + * \note Not applicable for DA14680/1-00 chips. + * + */ +void hw_cpm_configure_bod_protection(void); + /** * \brief Deactivate BOD protection. * @@ -265,6 +281,32 @@ __STATIC_INLINE void hw_cpm_deactivate_bod_protection(void) CRG_TOP->BOD_CTRL2_REG = 0; } +/** + * \brief Activate BOD protection for 1V4 rail (only for DA14682/3-BA chips!). + * + */ +__STATIC_INLINE void hw_cpm_activate_1v4_bod_protection(void) __attribute__((always_inline)); + +__STATIC_INLINE void hw_cpm_activate_1v4_bod_protection(void) +{ +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) + REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_V14_EN); +#endif +} + +/** + * \brief Deactivate BOD protection for 1V4 rail (only for DA14682/3-BA chips!). + * + */ +__STATIC_INLINE void hw_cpm_deactivate_1v4_bod_protection(void) __attribute__((always_inline)); + +__STATIC_INLINE void hw_cpm_deactivate_1v4_bod_protection(void) +{ +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) + REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_V14_EN); +#endif +} + /** * \brief Power down the Radio Power Domain. * @@ -279,14 +321,14 @@ __STATIC_INLINE void hw_cpm_power_down_radio(void) /** * \brief Power down the Peripheral Power Domain. * - * \warning Interrupts must be disabled by the caller! - * */ __STATIC_INLINE void hw_cpm_power_down_periph_pd(void) __attribute__((always_inline)); __STATIC_INLINE void hw_cpm_power_down_periph_pd(void) { + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, PERIPH_SLEEP); + GLOBAL_INT_RESTORE(); } /** @@ -314,14 +356,14 @@ __STATIC_INLINE void hw_cpm_wait_per_power_down(void) /** * \brief Power up the Peripherals Power Domain. * - * \warning Interrupts must be disabled by the caller! - * */ __STATIC_INLINE void hw_cpm_power_up_per_pd(void) __attribute__((always_inline)); __STATIC_INLINE void hw_cpm_power_up_per_pd(void) { + GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, PERIPH_SLEEP); + GLOBAL_INT_RESTORE(); while ((CRG_TOP->SYS_STAT_REG & REG_MSK(CRG_TOP, SYS_STAT_REG, PER_IS_UP)) == 0); } @@ -381,7 +423,9 @@ __STATIC_INLINE void hw_cpm_activate_pad_latches(void) __attribute__((always_inl __STATIC_INLINE void hw_cpm_activate_pad_latches(void) { + GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, PAD_LATCH_EN); + GLOBAL_INT_RESTORE(); } /** @@ -392,7 +436,9 @@ __STATIC_INLINE void hw_cpm_deactivate_pad_latches(void) __attribute__((always_i __STATIC_INLINE void hw_cpm_deactivate_pad_latches(void) { + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, PAD_LATCH_EN); + GLOBAL_INT_RESTORE(); } /** @@ -469,7 +515,10 @@ __STATIC_INLINE uint32_t hw_cpm_check_xtal16m_status(void) */ __STATIC_INLINE void hw_cpm_enable_xtal16m(void) { + GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, CLK_CTRL_REG, XTAL16M_DISABLE); + GLOBAL_INT_RESTORE(); + } /** @@ -503,6 +552,18 @@ __STATIC_INLINE void hw_cpm_set_sleep_flag(void) GPIO->GPIO_CLK_SEL = 1; } +/** + * \brief Prepare RESET type tracking. + */ +__STATIC_INLINE void hw_cpm_track_reset_type(void) __attribute__((always_inline)); + +__STATIC_INLINE void hw_cpm_track_reset_type(void) +{ +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) + CRG_TOP->RESET_STAT_REG = 0; +#endif +} + /** * \brief Check if the system entered sleep. * @@ -589,6 +650,8 @@ __STATIC_INLINE uint32_t hw_cpm_get_sysclk(void) * \retval 3 Divide by 16 * */ +__STATIC_INLINE uint32_t hw_cpm_get_hclk_div(void) __attribute__((always_inline)); + __STATIC_INLINE uint32_t hw_cpm_get_hclk_div(void) { return REG_GETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV); @@ -598,9 +661,13 @@ __STATIC_INLINE uint32_t hw_cpm_get_hclk_div(void) * \brief Set the divider of the AMBA High Speed Bus. * */ +__STATIC_INLINE void hw_cpm_set_hclk_div(uint32_t div) __attribute__((always_inline)); + __STATIC_INLINE void hw_cpm_set_hclk_div(uint32_t div) { + GLOBAL_INT_DISABLE(); REG_SETF(CRG_TOP, CLK_AMBA_REG, HCLK_DIV, div); + GLOBAL_INT_RESTORE(); } /** @@ -621,9 +688,13 @@ __STATIC_INLINE uint32_t hw_cpm_get_pclk_div(void) * \brief Set the divider of the AMBA Peripheral Bus. * */ +__STATIC_INLINE void hw_cpm_set_pclk_div(uint32_t div) __attribute__((always_inline)); + __STATIC_INLINE void hw_cpm_set_pclk_div(uint32_t div) { + GLOBAL_INT_DISABLE(); REG_SETF(CRG_TOP, CLK_AMBA_REG, PCLK_DIV, div); + GLOBAL_INT_RESTORE(); } /** @@ -689,7 +760,7 @@ __STATIC_INLINE bool hw_cpm_mac_is_active(void) */ __STATIC_INLINE bool hw_cpm_lp_is_rc32k(void) { - return REG_GETF(CRG_TOP, CLK_32K_REG, RC32K_ENABLE) && + return REG_GETF(CRG_TOP, CLK_32K_REG, RC32K_ENABLE) && (REG_GETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE) == LP_CLK_IS_RC32K); } @@ -709,15 +780,35 @@ __STATIC_INLINE void hw_cpm_lp_set_rcx(void) * \brief Set XTAL32K as the Low Power clock. * * \warning The XTAL32K must have been enabled before calling this function! + * Interrupts must have been disabled before calling this function! */ __STATIC_INLINE void hw_cpm_lp_set_xtal32k(void) { + ASSERT_WARNING(__get_PRIMASK() == 1); ASSERT_WARNING(REG_GETF(CRG_TOP, CLK_32K_REG, XTAL32K_ENABLE) == 1); REG_SETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE, LP_CLK_IS_XTAL32K); } -/** +/** + * \brief Configure pin to connect an external digital clock. + * + */ +void hw_cpm_configure_ext32k_pins(void); + +/** + * \brief Set an external digital clock as the Low Power clock. + * + * \warning Interrupts must have been disabled before calling this function! + */ +__STATIC_INLINE void hw_cpm_lp_set_ext32k(void) +{ + ASSERT_WARNING(__get_PRIMASK() == 1); + + REG_SETF(CRG_TOP, CLK_CTRL_REG, CLK32K_SOURCE, LP_CLK_IS_EXTERNAL); +} + +/** * \brief Enable RC32K. * */ @@ -954,6 +1045,43 @@ __STATIC_INLINE void hw_cpm_3v3_clamp_off(void) REG_CLR_BIT(CRG_TOP, AON_SPARE_REG, EN_BATSYS_RET); } +/** + * \brief Enable OSC16M amplitude regulation + */ +__STATIC_INLINE void hw_cpm_enable_osc16m_amp_reg(void) __attribute__((always_inline)); + +__STATIC_INLINE void hw_cpm_enable_osc16m_amp_reg(void) +{ + REG_CLR_BIT(CRG_TOP, AON_SPARE_REG, OSC16_HOLD_AMP_REG); +} + +/** + * \brief Disable OSC16M amplitude regulation + */ +__STATIC_INLINE void hw_cpm_disable_osc16m_amp_reg(void) __attribute__((always_inline)); + +__STATIC_INLINE void hw_cpm_disable_osc16m_amp_reg(void) +{ + REG_SET_BIT(CRG_TOP, AON_SPARE_REG, OSC16_HOLD_AMP_REG); +} + +/** + * \brief Sets the state of the 1v8 rail. + * + * \param[in] state true, the 1v8 rail is controlled via dg_config macros + * false, the 1v8 rail is off + * + */ +void hw_cpm_set_1v8_state(bool state); + +/** + * \brief Returns the state of the 1v8 rail. + * + * \return false if the 1v8 rail is off, true if it is controlled via dg_config macros + * + */ +__RETAINED_CODE bool hw_cpm_get_1v8_state(void); + /** * \brief Enable the LDO_VBAT_RET. * @@ -982,11 +1110,17 @@ __STATIC_INLINE void hw_cpm_ldo_io_ret_off(void) { uint32_t reg = CRG_TOP->LDO_CTRL2_REG; - if (dg_configFLASH_POWER_OFF == 0) { + if (dg_configPOWER_1V8_SLEEP == 1) { + if (dg_configUSE_BOD == 1) { + REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); + } REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, reg, 1); } - if (dg_configPOWER_EXT_1V8_PERIPHERALS == 1) { + if (dg_configPOWER_1V8P == 1) { + if (dg_configUSE_BOD == 1) { + REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN); + } REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_RET_DISABLE, reg, 1); } @@ -1010,13 +1144,16 @@ __STATIC_INLINE void hw_cpm_start_ldos(void) __attribute__((always_inline)); __STATIC_INLINE void hw_cpm_start_ldos(void) { uint32_t reg = CRG_TOP->LDO_CTRL2_REG; - + if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) && + (dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_A)) { + REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_VBAT_RET_LEVEL, 0); + } REG_SET_BIT(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_ENABLE); REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V2_ON, reg, 1); - if (dg_configPOWER_FLASH == 1) { + if ((dg_configPOWER_1V8_ACTIVE == 1) && hw_cpm_get_1v8_state()) { REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, reg, 1); - if (dg_configFLASH_POWER_OFF == 1) { + if (dg_configPOWER_1V8_SLEEP == 0) { REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, reg, 1); } else { @@ -1028,7 +1165,7 @@ __STATIC_INLINE void hw_cpm_start_ldos(void) REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, reg, 1); } - if (dg_configPOWER_EXT_1V8_PERIPHERALS == 1) { + if (dg_configPOWER_1V8P == 1) { REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_ON, reg, 1); REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_PA_RET_DISABLE, reg); } @@ -1086,11 +1223,6 @@ __STATIC_INLINE void hw_cpm_dcdc_off(void) // Enable the LDOs hw_cpm_start_ldos(); - // Turn off LDO_RADIO (newer chip versions do this automatically!) - if (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, A)) { - REG_CLR_BIT(CRG_TOP, LDO_CTRL1_REG, LDO_RADIO_ENABLE); - } - // Turn off DCDC DCDC->DCDC_CTRL_0_REG &= ~REG_MSK(DCDC, DCDC_CTRL_0_REG, DCDC_MODE); } @@ -1174,7 +1306,9 @@ __STATIC_INLINE void hw_cpm_rfcu_clk_off(void) __attribute__((always_inline)); __STATIC_INLINE void hw_cpm_rfcu_clk_off(void) { + GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, CLK_RADIO_REG, RFCU_ENABLE); + GLOBAL_INT_RESTORE(); } /** @@ -1185,7 +1319,9 @@ __STATIC_INLINE void hw_cpm_enable_debugger(void) __attribute__((always_inline)) __STATIC_INLINE void hw_cpm_enable_debugger(void) { + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); + GLOBAL_INT_RESTORE(); } /** @@ -1196,9 +1332,25 @@ __STATIC_INLINE void hw_cpm_disable_debugger(void) __attribute__((always_inline) __STATIC_INLINE void hw_cpm_disable_debugger(void) { + GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, DEBUGGER_ENABLE); + GLOBAL_INT_RESTORE(); } +/** + * \brief Check if the debugger is attached. + * + * \return true, if the debugger is attached, else false. + * + */ +__STATIC_INLINE bool hw_cpm_is_debugger_attached(void) __attribute__((always_inline)); + +__STATIC_INLINE bool hw_cpm_is_debugger_attached(void) +{ + return (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE) != 0); +} + + /** * \brief Check if any DMA channel is active. * @@ -1259,7 +1411,8 @@ __RETAINED_CODE void hw_cpm_reboot_system(void); */ __RETAINED_CODE void hw_cpm_delay_usec(uint32_t usec); -/** \brief Trigger a GPIO when ASSERT_WARNING() or ASSERT_ERROR() hits. +/** + * \brief Trigger a GPIO when ASSERT_WARNING() or ASSERT_ERROR() hits. * */ __RETAINED_CODE void hw_cpm_assert_trigger_gpio(void); diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_dma.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_dma.h old mode 100755 new mode 100644 index d64345a0a..01fc6344c --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_dma.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_dma.h @@ -5,6 +5,7 @@ * \{ * \addtogroup DMA * \{ + * \brief DMA Controller */ /** @@ -38,6 +39,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -47,7 +49,7 @@ #if dg_configUSE_HW_DMA #include -#include +#include /* * ENUMERATION DEFINITIONS @@ -257,6 +259,56 @@ typedef struct { */ void hw_dma_channel_initialization(DMA_setup *channel_setup); +/** + * \brief Update DMA source address and length + * + * When DMA is configured for some peripheral, it could be enough to setup only source address + * and data length. Other parameters most likely do not change for same type of transmission + * for values that ware specified in \p hw_dma_channel_initialization(). + * This function should speed up DMA start time when only address and size changes from previous + * transmission. + * + * \param [in] channel DMA channel number to modify + * \param [in] addr new source address + * \param [in] length new data transfer length + * \param [in] cb function to call after transmission finishes + * + */ +void hw_dma_channel_update_source(HW_DMA_CHANNEL channel, void* addr, uint16_t length, + hw_dma_transfer_cb cb); + +/** + * \brief Update DMA destination address and length + * + * When DMA is configured for some peripheral, it could be enough to setup only destination address + * and data length. Other parameters most likely do not change for same type of transmission + * for values that ware specified in \p hw_dma_channel_initialization(). + * This function should speed up DMA start time when only address and size changes from previous + * transmission. + * + * \param [in] channel DMA channel number to modify + * \param [in] addr new source address + * \param [in] length new data transfer length + * \param [in] cb function to call after transmission finishes + * + */ +void hw_dma_channel_update_destination(HW_DMA_CHANNEL channel, void *addr, uint16_t length, + hw_dma_transfer_cb cb); + +/** + * \brief Update DMA interrupt trigger index + * + * DMA channel can trigger an interrupt after arbitrary transfer has finished. + * Usually interrupt is triggered after transmission finishes but for cyclic mode, + * where DMA never stops, it is convenient trigger interrupt at other times. + * This function allows to specify the number of transfers after which the interrupt is triggered. + * + * \param [in] channel DMA channel number to modify + * \param [in] int_ix Number of transfers until the interrupt is triggered + * + */ +void hw_dma_channel_update_int_ix(HW_DMA_CHANNEL channel, uint16_t int_ix); + /** * \brief Enable or disable a DMA channel * diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_fem_sky66112-11.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_fem_sky66112-11.h old mode 100755 new mode 100644 index 3e78dc959..cb9209282 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_fem_sky66112-11.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_fem_sky66112-11.h @@ -5,6 +5,7 @@ * \{ * \addtogroup FEM * \{ + * \brief Front End Module for SKYWORKS SKY66112-11 */ /** @@ -24,6 +25,16 @@ * CHL : dg_configFEM_SKY66112_11_CHL_PORT/PIN * ANTSEL: dg_configFEM_SKY66112_11_ANTSEL_PORT/PIN * + * In order to control an external PA, three GPIOs can be used. These are called RF_ANT_TRIMx, x=0,1,2. Each one of + * these bits is enabled if the corresponding PORT/PIN macros are set: + * + * RF_ANT_TRIM0 : dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT/PIN + * RF_ANT_TRIM1 : dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT/PIN + * RF_ANT_TRIM2 : dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT/PIN + * + * The actual GPIO values for RF_ANT_TRIMx are set by the corresponding MAC, whenever it gains access by the arbiter + * to the RF. This driver only handles the GPIO initialization. + * * FEM BIAS Voltage control is enabled by the following macros: * * V18 : dg_configFEM_SKY66112_11_FEM_BIAS_V18 @@ -31,6 +42,8 @@ * * If none of them is set, FEM BIAS will not be controlled by this driver. * + *************************************************************************************** + * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -54,7 +67,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ @@ -70,13 +84,23 @@ /* Configuration/state structure (actually just a byte) */ typedef struct __attribute__ ((__packed__)) { +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A uint8_t tx_power: 1; uint8_t tx_bypass: 1; uint8_t rx_bypass: 1; +#else + uint8_t tx_power_ble: 1; + uint8_t tx_bypass_ble: 1; + uint8_t rx_bypass_ble: 1; + uint8_t tx_power_ftdf: 1; + uint8_t tx_bypass_ftdf: 1; + uint8_t rx_bypass_ftdf: 1; +#endif uint8_t antsel: 1; uint8_t started: 1; } hw_fem_config; +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A /** * \brief Configures FEM TX Power * @@ -85,14 +109,6 @@ typedef struct __attribute__ ((__packed__)) { */ void hw_fem_set_txpower(bool high); -/** - * \brief Configures FEM Antenna to use - * - * \param [in] one false: antenna 0, true: antenna 1 - * - */ -void hw_fem_set_antenna(bool one); - /** * \brief Configures FEM TX bypass mode * @@ -117,14 +133,6 @@ void hw_fem_set_rx_bypass(bool enable); */ bool hw_fem_get_txpower(void); -/** - * \brief Gets the selected antenna - * - * \return false: antenna 1, true: antenna 2 - * - */ -bool hw_fem_get_antenna(void); - /** * \brief Gets the TX bypass mode * @@ -141,6 +149,179 @@ bool hw_fem_get_tx_bypass(void); */ bool hw_fem_get_rx_bypass(void); +#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ +#ifdef CONFIG_USE_BLE +/** + * \brief Configures FEM TX Power for BLE + * + * \param [in] high Set true to enable high TX power + * + */ +void hw_fem_set_txpower_ble(bool high); + +/** + * \brief Configures FEM TX bypass mode for BLE + * + * \param [in] enable false: Use PA, true: bypass + * + */ +void hw_fem_set_tx_bypass_ble(bool enable); + +/** + * \brief Configures FEM RX bypass mode for BLE + * + * \param [in] enable false: Use LNA, true: bypass + * + */ +void hw_fem_set_rx_bypass_ble(bool enable); + +/** + * \brief Gets the TX Power setting for BLE + * + * \return true, if TX Power is high, false if low + * + */ +bool hw_fem_get_txpower_ble(void); + +/** + * \brief Gets the TX bypass mode for BLE + * + * \return false: No TX bypass, true: TX bypass + * + */ +bool hw_fem_get_tx_bypass_ble(void); + +/** + * \brief Gets the RX bypass mode for BLE + * + * \return false: No RX bypass, true: RX bypass + * + */ +bool hw_fem_get_rx_bypass_ble(void); +#endif /* CONFIG_USE_BLE */ + +#ifdef CONFIG_USE_FTDF +/** + * \brief Configures FEM TX Power for FTDF + * + * \param [in] high Set true to enable high TX power + * + */ +void hw_fem_set_txpower_ftdf(bool high); + +/** + * \brief Configures FEM TX bypass mode for FTDF + * + * \param [in] enable false: Use PA, true: bypass + * + */ +void hw_fem_set_tx_bypass_ftdf(bool enable); + +/** + * \brief Configures FEM RX bypass mode for FTDF + * + * \param [in] enable false: Use LNA, true: bypass + * + */ +void hw_fem_set_rx_bypass_ftdf(bool enable); + +/** + * \brief Gets the TX Power setting for FTDF + * + * \return true, if TX Power is high, false if low + * + */ +bool hw_fem_get_txpower_ftdf(void); + +/** + * \brief Gets the TX bypass mode for FTDF + * + * \return false: No TX bypass, true: TX bypass + * + */ +bool hw_fem_get_tx_bypass_ftdf(void); + +/** + * \brief Gets the RX bypass mode for FTDF + * + * \return false: No RX bypass, true: RX bypass + * + */ +bool hw_fem_get_rx_bypass_ftdf(void); +#endif /* CONFIG_USE_FTDF */ + +/** + * \brief Configures FEM TX Power + * + * \param [in] high Set true to enable high TX power + * + * \deprecated Use the BLE/FTDF specific functions instead + */ +void hw_fem_set_txpower(bool high) DEPRECATED; + +/** + * \brief Configures FEM TX bypass mode + * + * \param [in] enable false: Use PA, true: bypass + * + * \deprecated Use the BLE/FTDF specific functions instead + */ +void hw_fem_set_tx_bypass(bool enable) DEPRECATED; + +/** + * \brief Configures FEM RX bypass mode + * + * \param [in] enable false: Use LNA, true: bypass + * + * \deprecated Use the BLE/FTDF specific functions instead + */ +void hw_fem_set_rx_bypass(bool enable) DEPRECATED; + +/** + * \brief Gets the TX Power setting + * + * \return true, if TX Power is high, false if low + * + * \deprecated Use the BLE/FTDF specific functions instead + */ +bool hw_fem_get_txpower(void) DEPRECATED; + +/** + * \brief Gets the TX bypass mode + * + * \return false: No TX bypass, true: TX bypass + * + * \deprecated Use the BLE/FTDF specific functions instead + */ +bool hw_fem_get_tx_bypass(void) DEPRECATED; + +/** + * \brief Gets the RX bypass mode + * + * \return false: No RX bypass, true: RX bypass + * + * \deprecated Use the BLE/FTDF specific functions instead + */ +bool hw_fem_get_rx_bypass(void) DEPRECATED; +#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ + + +/** + * \brief Configures FEM Antenna to use + * + * \param [in] one false: antenna 0, true: antenna 1 + * + */ +void hw_fem_set_antenna(bool one); + +/** + * \brief Gets the selected antenna + * + * \return false: antenna 1, true: antenna 2 + * + */ +bool hw_fem_get_antenna(void); + /** * \brief Sets the FEM Bias * diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpadc.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpadc.h old mode 100755 new mode 100644 index 20dfda265..fd918e33b --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpadc.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpadc.h @@ -5,6 +5,7 @@ * \{ * \addtogroup GPADC * \{ + * \brief General Purpose ADC */ /** @@ -37,7 +38,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ @@ -48,7 +50,10 @@ #include #include -#include +#include + +extern int16_t hw_gpadc_differential_gain_error; +extern int16_t hw_gpadc_single_ended_gain_error; /** * \brief ADC input mode @@ -310,7 +315,7 @@ static inline void hw_gpadc_set_input(HW_GPADC_INPUT input) */ static inline HW_GPADC_INPUT hw_gpadc_get_input(void) { - return REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_SEL); + return (HW_GPADC_INPUT) REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_SEL); } /** @@ -332,7 +337,7 @@ static inline void hw_gpadc_set_input_mode(HW_GPADC_INPUT_MODE mode) */ static inline HW_GPADC_INPUT_MODE hw_gpadc_get_input_mode(void) { - return REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_SE); + return (HW_GPADC_INPUT_MODE) REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_SE); } /** @@ -354,7 +359,7 @@ static inline void hw_gpadc_set_clock(HW_GPADC_CLOCK clock) */ static inline HW_GPADC_CLOCK hw_gpadc_get_clock(void) { - return REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_CLK_SEL); + return (HW_GPADC_CLOCK) REG_GETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_CLK_SEL); } /** @@ -652,6 +657,43 @@ static inline uint16_t hw_gpadc_get_offset_negative(void) return GPADC->GP_ADC_OFFN_REG & REG_MSK(GPADC, GP_ADC_OFFN_REG, GP_ADC_OFFN); } +/** + * \brief Store Single Ended ADC Gain Error + * + * \param [in] single ADC Single Ended Gain Error + * + */ +static inline void hw_gpadc_store_se_gain_error(int16_t single) +{ + hw_gpadc_single_ended_gain_error = single; +} + +/** + * \brief Store Differential ADC Gain Error + * + * \param [in] diff ADC Differential Gain Error + * + */ +static inline void hw_gpadc_store_diff_gain_error(int16_t diff) +{ + hw_gpadc_differential_gain_error = diff; +} + +/** + * \brief Check the availability of ADC Gain Error + * + * \return ADC Gain Error availability + * + */ +static inline bool hw_gpadc_pre_check_for_gain_error(void) +{ + if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) { + return (hw_gpadc_single_ended_gain_error && hw_gpadc_differential_gain_error); + } + + return false; +} + /** * \brief Get raw conversion result value * @@ -664,10 +706,7 @@ static inline uint16_t hw_gpadc_get_offset_negative(void) * \sa hw_gpadc_get_value * */ -static inline uint16_t hw_gpadc_get_raw_value(void) -{ - return GPADC->GP_ADC_RESULT_REG; -} +uint16_t hw_gpadc_get_raw_value(void); /** * \brief Get conversion result value @@ -686,6 +725,18 @@ static inline uint16_t hw_gpadc_get_value(void) return hw_gpadc_get_raw_value() >> (6 - MIN(6, hw_gpadc_get_oversampling())); } +/** + * \brief Get conversion result value without gain compensation and over sampling. + * + * \return conversion result value + * + */ +static inline uint16_t hw_gpadc_get_value_without_gain(void) +{ + uint16_t adc_raw_res = GPADC->GP_ADC_RESULT_REG; + return adc_raw_res; +} + /** * \brief Start a measurement and wait for the result. * diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpio.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpio.h old mode 100755 new mode 100644 index f37ff2413..862193ea3 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpio.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_gpio.h @@ -5,6 +5,7 @@ * \{ * \addtogroup GPIO * \{ + * \brief GPIO Control */ /** @@ -37,7 +38,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ @@ -48,7 +50,7 @@ #include #include -#include +#include /* GPIO layout definitions */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_hard_fault.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_hard_fault.h old mode 100755 new mode 100644 index 9316d05df..b233fad73 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_hard_fault.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_hard_fault.h @@ -1,10 +1,11 @@ /** * \addtogroup BSP * \{ - * \addtogroup DEVICES + * \addtogroup SYSTEM * \{ * \addtogroup Exception_Handlers * \{ + * \brief Generic Exception Handlers */ /** @@ -37,7 +38,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ @@ -47,7 +49,7 @@ #include #include -#include +#include #define HARDFAULT_MAGIC_NUMBER 0xBADC0FFE diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_led.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_led.h old mode 100755 new mode 100644 index 6d54f4424..1f4c484be --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_led.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_led.h @@ -5,6 +5,7 @@ * \{ * \addtogroup LED * \{ + * \brief LED Controller */ /** @@ -38,13 +39,14 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * ***************************************************************************************** */ #ifndef HW_LED_H_ #define HW_LED_H_ -#include +#include /** * \brief Source for LED1 diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_otpc.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_otpc.h old mode 100755 new mode 100644 index 748eccf87..291568601 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_otpc.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_otpc.h @@ -5,6 +5,7 @@ * \{ * \addtogroup OTPC * \{ + * \brief OTP Memory Controller */ /** @@ -38,6 +39,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -48,7 +50,7 @@ #include #include -#include +#include /** @@ -191,25 +193,29 @@ __RETAINED_CODE HW_OTPC_SYS_CLK_FREQ hw_otpc_convert_sys_clk_mhz(uint32_t clk_fr */ static inline void hw_otpc_init(void) { -#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) - /* - * Reset OTP controller - */ - OTPC->OTPC_MODE_REG = HW_OTPC_MODE_STBY; // Set OTPC to standby - REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, OTPC_RESET_REQ); // Reset the OTP Controller - REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, OTPC_RESET_REQ);// Get the OTP Controller out of Reset + GLOBAL_INT_DISABLE(); + if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE))) { + /* + * Reset OTP controller + */ + OTPC->OTPC_MODE_REG = HW_OTPC_MODE_STBY; // Set OTPC to standby + REG_SET_BIT(CRG_TOP, SYS_CTRL_REG, OTPC_RESET_REQ); // Reset the OTPC + REG_CLR_BIT(CRG_TOP, SYS_CTRL_REG, OTPC_RESET_REQ); // Get the OTPC out of Reset + + /* + * Initialize the POR registers + */ + OTPC->OTPC_NWORDS_REG = OTPC_NWORDS_REG_RESET; + OTPC->OTPC_TIM1_REG = OTPC_TIM1_REG_RESET; + OTPC->OTPC_TIM2_REG = OTPC_TIM2_REG_RESET; + } - /* - * Initialize the POR registers - */ - OTPC->OTPC_NWORDS_REG = OTPC_NWORDS_REG_RESET; - OTPC->OTPC_TIM1_REG = OTPC_TIM1_REG_RESET; - OTPC->OTPC_TIM2_REG = OTPC_TIM2_REG_RESET; -#endif /* * Enable OTPC clock */ CRG_TOP->CLK_AMBA_REG |= 1 << REG_POS(CRG_TOP, CLK_AMBA_REG, OTP_ENABLE); + GLOBAL_INT_RESTORE(); } /** @@ -221,7 +227,9 @@ static inline void hw_otpc_close(void) /* * Disable OTPC clock */ + GLOBAL_INT_DISABLE(); CRG_TOP->CLK_AMBA_REG &= ~REG_MSK(CRG_TOP, CLK_AMBA_REG, OTP_ENABLE); + GLOBAL_INT_RESTORE(); } /** @@ -235,7 +243,7 @@ static inline uint32_t hw_otpc_is_active(void) __attribute__((always_inline)); static inline uint32_t hw_otpc_is_active(void) { /* - * Disable OTPC clock + * Check if the OTPC clock is enabled */ return !!(CRG_TOP->CLK_AMBA_REG & REG_MSK(CRG_TOP, CLK_AMBA_REG, OTP_ENABLE)); } diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_qspi.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_qspi.h old mode 100755 new mode 100644 index 8b90db8d7..b1e967e9f --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_qspi.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_qspi.h @@ -5,6 +5,7 @@ * \{ * \addtogroup QSPI * \{ + * \brief QSPI Flash Memory Controller */ /** @@ -37,7 +38,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ @@ -48,7 +50,7 @@ #include #include -#include +#include /** @@ -96,6 +98,8 @@ ((QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk) & ((new_val) << (QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos)))) +extern uint8_t dummy_num[]; + /* * ENUMERATION DEFINITIONS ***************************************************************************************** @@ -216,9 +220,8 @@ typedef struct { * Use this in manual mode. * */ -#if (dg_configFLASH_POWER_DOWN == 1) -__attribute__((section("text_retained"))) -#endif +static inline void hw_qspi_cs_enable(void) __attribute__((always_inline)); + static inline void hw_qspi_cs_enable(void) { QSPIC->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk; @@ -230,9 +233,8 @@ static inline void hw_qspi_cs_enable(void) * Use this in manual mode. * */ -#if (dg_configFLASH_POWER_DOWN == 1) -__attribute__((section("text_retained"))) -#endif +static inline void hw_qspi_cs_disable(void) __attribute__((always_inline)); + static inline void hw_qspi_cs_disable(void) { QSPIC->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk; @@ -257,6 +259,8 @@ void hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE mode); * 1 - SPI Bus is active. ReadData, WriteData or DummyData activity is in progress * */ +static inline uint8_t hw_qspi_is_busy(void) __attribute__((always_inline)); + static inline uint8_t hw_qspi_is_busy(void) { return (uint8_t) QSPIC->QSPIC_STATUS_REG; @@ -271,6 +275,8 @@ static inline uint8_t hw_qspi_is_busy(void) * \return data read during read transfer * */ +static inline uint32_t hw_qspi_read32(void) __attribute__((always_inline)); + static inline uint32_t hw_qspi_read32(void) { return QSPIC->QSPIC_READDATA_REG; @@ -285,6 +291,8 @@ static inline uint32_t hw_qspi_read32(void) * \return data read during read transfer * */ +static inline uint16_t hw_qspi_read16(void) __attribute__((always_inline)); + static inline uint16_t hw_qspi_read16(void) { return *((volatile uint16_t *) &(QSPIC->QSPIC_READDATA_REG)); @@ -299,6 +307,8 @@ static inline uint16_t hw_qspi_read16(void) * \return data read during read transfer * */ +static inline uint8_t hw_qspi_read8(void) __attribute__((always_inline)); + static inline uint8_t hw_qspi_read8(void) { return *((volatile uint8_t *) &(QSPIC->QSPIC_READDATA_REG)); @@ -313,6 +323,8 @@ static inline uint8_t hw_qspi_read8(void) * param [in] data data to transfer * */ +static inline void hw_qspi_write32(uint32_t data) __attribute__((always_inline)); + static inline void hw_qspi_write32(uint32_t data) { QSPIC->QSPIC_WRITEDATA_REG = data; @@ -327,6 +339,8 @@ static inline void hw_qspi_write32(uint32_t data) * param [in] data data to transfer * */ +static inline void hw_qspi_write16(uint16_t data) __attribute__((always_inline)); + static inline void hw_qspi_write16(uint16_t data) { *((volatile uint16_t *) &(QSPIC->QSPIC_WRITEDATA_REG)) = data; @@ -341,9 +355,8 @@ static inline void hw_qspi_write16(uint16_t data) * param [in] data data to transfer * */ -#if (dg_configFLASH_POWER_DOWN == 1) -__attribute__((section("text_retained"))) -#endif +static inline void hw_qspi_write8(uint8_t data) __attribute__((always_inline)); + static inline void hw_qspi_write8(uint8_t data) { *((volatile uint8_t *) &(QSPIC->QSPIC_WRITEDATA_REG)) = data; @@ -356,6 +369,8 @@ static inline void hw_qspi_write8(uint8_t data) * Number of pulses depends on selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). * */ +static inline void hw_qspi_dummy32(void) __attribute__((always_inline)); + static inline void hw_qspi_dummy32(void) { QSPIC->QSPIC_DUMMYDATA_REG = 0; @@ -368,6 +383,8 @@ static inline void hw_qspi_dummy32(void) * Number of pulses depends on selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). * */ +static inline void hw_qspi_dummy16(void) __attribute__((always_inline)); + static inline void hw_qspi_dummy16(void) { *((volatile uint16_t *) &(QSPIC->QSPIC_DUMMYDATA_REG)) = 0; @@ -380,6 +397,8 @@ static inline void hw_qspi_dummy16(void) * Number of pulses depends on selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). * */ +static inline void hw_qspi_dummy8(void) __attribute__((always_inline)); + static inline void hw_qspi_dummy8(void) { *((volatile uint8_t *) &(QSPIC->QSPIC_DUMMYDATA_REG)) = 0; @@ -393,6 +412,8 @@ static inline void hw_qspi_dummy8(void) * \param [in] size selects 32 or 24 address size * */ +static inline void hw_qspi_set_address_size(HW_QSPI_ADDR_SIZE size) __attribute__((always_inline)); + static inline void hw_qspi_set_address_size(HW_QSPI_ADDR_SIZE size) { HW_QSPIC_REG_SETF(CTRLMODE, USE_32BA, (size == HW_QSPI_ADDR_SIZE_32 ? 1 : 0)); @@ -408,6 +429,8 @@ static inline void hw_qspi_set_address_size(HW_QSPI_ADDR_SIZE size) * \sa hw_qspi_set_address_size * */ +static inline HW_QSPI_ADDR_SIZE hw_qspi_get_address_size(void) __attribute__((always_inline)); + static inline HW_QSPI_ADDR_SIZE hw_qspi_get_address_size(void) { return (HW_QSPI_ADDR_SIZE) HW_QSPIC_REG_GETF(CTRLMODE, USE_32BA); @@ -430,6 +453,8 @@ static inline HW_QSPI_ADDR_SIZE hw_qspi_get_address_size(void) * respect to QSPIC_FORCENSEQ_EN=0 at cost of performance * */ +static inline void hw_qspi_force_nseq(uint8_t force) __attribute__((always_inline)); + static inline void hw_qspi_force_nseq(uint8_t force) { HW_QSPIC_REG_SETF(CTRLMODE, FORCENSEQ_EN, force); @@ -462,6 +487,8 @@ void hw_qspi_set_automode(bool automode); * false manual mode is selected * */ +static inline bool hw_qspi_get_automode(void) __attribute__((always_inline)); + static inline bool hw_qspi_get_automode(void) { return HW_QSPIC_REG_GETF(CTRLMODE, AUTO_MD); @@ -473,6 +500,8 @@ static inline bool hw_qspi_get_automode(void) * \return read pipe clock delay relative to the falling edge of QSPI_SCK * */ +static inline uint8_t hw_qspi_get_read_pipe_clock_delay(void) __attribute__((always_inline)); + static inline uint8_t hw_qspi_get_read_pipe_clock_delay(void) { return HW_QSPIC_REG_GETF(CTRLMODE, PCLK_MD); @@ -485,6 +514,8 @@ static inline uint8_t hw_qspi_get_read_pipe_clock_delay(void) * value should be in range 0..7 * */ +static inline void hw_qspi_set_read_pipe_clock_delay(uint8_t delay) __attribute__((always_inline)); + static inline void hw_qspi_set_read_pipe_clock_delay(uint8_t delay) { HW_QSPIC_REG_SETF(CTRLMODE, PCLK_MD, delay); @@ -496,6 +527,8 @@ static inline void hw_qspi_set_read_pipe_clock_delay(uint8_t delay) * \return 1 if read pipe is enabled, 0 otherwise * */ +static inline uint8_t hw_qspi_is_read_pipe_clock_enabled(void) __attribute__((always_inline)); + static inline uint8_t hw_qspi_is_read_pipe_clock_enabled(void) { return HW_QSPIC_REG_GETF(CTRLMODE, RPIPE_EN); @@ -508,6 +541,8 @@ static inline uint8_t hw_qspi_is_read_pipe_clock_enabled(void) * 0 disable read pipe * */ +static inline void hw_qspi_enable_readpipe(uint8_t enable) __attribute__((always_inline)); + static inline void hw_qspi_enable_readpipe(uint8_t enable) { HW_QSPIC_REG_SETF(CTRLMODE, RPIPE_EN, enable); @@ -519,6 +554,8 @@ static inline void hw_qspi_enable_readpipe(uint8_t enable) * \return type of QSPI_CLK edge for sampling received data * */ +static inline HW_QSPI_SAMPLING_EDGE hw_qspi_get_read_sampling_edge(void) __attribute__((always_inline)); + static inline HW_QSPI_SAMPLING_EDGE hw_qspi_get_read_sampling_edge(void) { return HW_QSPIC_REG_GETF(CTRLMODE, RXD_NEG); @@ -531,6 +568,8 @@ static inline HW_QSPI_SAMPLING_EDGE hw_qspi_get_read_sampling_edge(void) * of QSPI_SCK * */ +static inline void hw_qspi_set_read_sampling_edge(HW_QSPI_SAMPLING_EDGE edge) __attribute__((always_inline)); + static inline void hw_qspi_set_read_sampling_edge(HW_QSPI_SAMPLING_EDGE edge) { HW_QSPIC_REG_SETF(CTRLMODE, RXD_NEG, edge); @@ -547,6 +586,8 @@ static inline void hw_qspi_set_read_sampling_edge(HW_QSPI_SAMPLING_EDGE edge) * activity at the SPI bus * */ +static inline uint8_t hw_qspi_is_hready_enabled(void) __attribute__((always_inline)); + static inline uint8_t hw_qspi_is_hready_enabled(void) { return HW_QSPIC_REG_GETF(CTRLMODE, HRDY_MD); @@ -559,6 +600,8 @@ static inline uint8_t hw_qspi_is_hready_enabled(void) * QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers * */ +static inline void hw_qspi_enable_hready(uint8_t enable) __attribute__((always_inline)); + static inline void hw_qspi_enable_hready(uint8_t enable) { HW_QSPIC_REG_SETF(CTRLMODE, HRDY_MD, enable); @@ -571,6 +614,8 @@ static inline void hw_qspi_enable_hready(uint8_t enable) * 1 - SPI mode 3 is used for QSPI_CLK, the QSPI_SCK is high when QSPI_CS is high (idle) * */ +static inline uint8_t hw_qspi_get_clock_mode(void) __attribute__((always_inline)); + static inline uint8_t hw_qspi_get_clock_mode(void) { return HW_QSPIC_REG_GETF(CTRLMODE, CLK_MD); @@ -585,6 +630,8 @@ static inline uint8_t hw_qspi_get_clock_mode(void) * The QSPI_SCK is high when QSPI_CS is high (idle) * */ +static inline void hw_qspi_set_clock_mode(HW_QSPI_POL mode) __attribute__((always_inline)); + static inline void hw_qspi_set_clock_mode(HW_QSPI_POL mode) { HW_QSPIC_REG_SETF(CTRLMODE, CLK_MD, mode); @@ -603,6 +650,8 @@ static inline void hw_qspi_set_clock_mode(HW_QSPI_POL mode) #if (dg_configFLASH_POWER_DOWN == 1) __attribute__((section("text_retained"))) #endif +static inline void hw_qspi_set_io2_output(bool output) __attribute__((always_inline)); + static inline void hw_qspi_set_io2_output(bool output) { HW_QSPIC_REG_SETF(CTRLMODE, IO2_OEN, output); @@ -621,6 +670,8 @@ static inline void hw_qspi_set_io2_output(bool output) #if (dg_configFLASH_POWER_DOWN == 1) __attribute__((section("text_retained"))) #endif +static inline void hw_qspi_set_io3_output(bool output) __attribute__((always_inline)); + static inline void hw_qspi_set_io3_output(bool output) { HW_QSPIC_REG_SETF(CTRLMODE, IO3_OEN, output); @@ -634,6 +685,8 @@ static inline void hw_qspi_set_io3_output(bool output) * \sa hw_qspi_set_io2_direction * */ +static inline void hw_qspi_set_io2(uint8_t val) __attribute__((always_inline)); + static inline void hw_qspi_set_io2(uint8_t val) { HW_QSPIC_REG_SETF(CTRLMODE, IO2_DAT, val); @@ -647,6 +700,8 @@ static inline void hw_qspi_set_io2(uint8_t val) * \sa hw_qspi_set_io3_direction * */ +static inline void hw_qspi_set_io3(uint8_t val) __attribute__((always_inline)); + static inline void hw_qspi_set_io3(uint8_t val) { HW_QSPIC_REG_SETF(CTRLMODE, IO3_DAT, val); @@ -658,6 +713,8 @@ static inline void hw_qspi_set_io3(uint8_t val) * \return value of IO2 pin (0 or 1) * */ +static inline uint8_t hw_qspi_get_io2(void) __attribute__((always_inline)); + static inline uint8_t hw_qspi_get_io2(void) { return HW_QSPIC_REG_GETF(CTRLMODE, IO2_DAT); @@ -669,6 +726,8 @@ static inline uint8_t hw_qspi_get_io2(void) * \return value of IO3 pin (0 or 1) * */ +static inline uint8_t hw_qspi_get_io3(void) __attribute__((always_inline)); + static inline uint8_t hw_qspi_get_io3(void) { return HW_QSPIC_REG_GETF(CTRLMODE, IO3_DAT); @@ -697,11 +756,35 @@ static inline uint8_t hw_qspi_get_io3(void) * \sa hw_qspi_set_wrapping_burst_instruction * */ -void hw_qspi_set_read_instruction(uint8_t inst, uint8_t send_once, uint8_t dummy_count, - HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE addr_phase, - HW_QSPI_BUS_MODE dummy_phase, - HW_QSPI_BUS_MODE data_phase); +static inline void hw_qspi_set_read_instruction(uint8_t inst, + uint8_t send_once, + uint8_t dummy_count, + HW_QSPI_BUS_MODE inst_phase, + HW_QSPI_BUS_MODE addr_phase, + HW_QSPI_BUS_MODE dummy_phase, + HW_QSPI_BUS_MODE data_phase) + __attribute((always_inline)); + +static inline void hw_qspi_set_read_instruction(uint8_t inst, + uint8_t send_once, + uint8_t dummy_count, + HW_QSPI_BUS_MODE inst_phase, + HW_QSPI_BUS_MODE addr_phase, + HW_QSPI_BUS_MODE dummy_phase, + HW_QSPI_BUS_MODE data_phase) +{ + QSPIC->QSPIC_BURSTCMDA_REG = + BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST, inst) | + BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST_TX_MD, inst_phase) | + BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_ADR_TX_MD, addr_phase) | + BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_DMY_TX_MD, dummy_phase); + + QSPIC->QSPIC_BURSTCMDB_REG = + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DAT_RX_MD, data_phase) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_INST_MD, send_once) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE, (dummy_count == 3 ? 1 : 0)) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, dummy_num[dummy_count]); +} /** * \brief Set wrapping burst read instructions for QSPI flash @@ -732,8 +815,26 @@ void hw_qspi_set_wrapping_burst_instruction(uint8_t inst, HW_QSPI_WRAP_LEN len, * \sa hw_qspi_set_read_instruction * */ -void hw_qspi_set_extra_byte(uint8_t extra_byte, HW_QSPI_BUS_MODE bus_mode, - uint8_t half_disable_out); +static inline void hw_qspi_set_extra_byte(uint8_t extra_byte, HW_QSPI_BUS_MODE bus_mode, + uint8_t half_disable_out) __attribute__((always_inline)); + +static inline void hw_qspi_set_extra_byte(uint8_t extra_byte, HW_QSPI_BUS_MODE bus_mode, + uint8_t half_disable_out) +{ + QSPIC->QSPIC_BURSTCMDA_REG = + (QSPIC->QSPIC_BURSTCMDA_REG & + ~(REG_MSK(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_BYTE) | + REG_MSK(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_TX_MD))) | + BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_BYTE, extra_byte) | + BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_TX_MD, bus_mode); + + QSPIC->QSPIC_BURSTCMDB_REG = + (QSPIC->QSPIC_BURSTCMDB_REG & + ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_BYTE_EN) | + REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_HF_DS))) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_BYTE_EN, 1) | + BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_HF_DS, half_disable_out ? 1 : 0); +} /** * \brief Set dummy byte count @@ -754,6 +855,8 @@ void hw_qspi_set_dummy_bytes_count(uint8_t count); * register for an exception * */ +static inline void hw_qspi_set_min_cs_high(uint8_t clock_count) __attribute__((always_inline)); + static inline void hw_qspi_set_min_cs_high(uint8_t clock_count) { HW_QSPIC_REG_SETF(BURSTCMDB, CS_HIGH_MIN, clock_count); @@ -777,8 +880,25 @@ static inline void hw_qspi_set_min_cs_high(uint8_t clock_count) * \sa hw_qspi_erase_block * */ -void hw_qspi_set_erase_instruction(uint8_t inst, HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE addr_phase, uint8_t hclk_cycles, uint8_t cs_hi_cycles); +static inline void hw_qspi_set_erase_instruction(uint8_t inst, HW_QSPI_BUS_MODE inst_phase, + HW_QSPI_BUS_MODE addr_phase, uint8_t hclk_cycles, uint8_t cs_hi_cycles) + __attribute__((always_inline)); + +static inline void hw_qspi_set_erase_instruction(uint8_t inst, HW_QSPI_BUS_MODE inst_phase, + HW_QSPI_BUS_MODE addr_phase, uint8_t hclk_cycles, uint8_t cs_hi_cycles) +{ + HW_QSPIC_REG_SETF(ERASECMDA, ERS_INST, inst); + QSPIC->QSPIC_ERASECMDB_REG = + (QSPIC->QSPIC_ERASECMDB_REG & + ~(REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_TX_MD) | + REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_EAD_TX_MD) | + REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERSRES_HLD) | + REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_CS_HI))) | + BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_TX_MD, inst_phase) | + BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_EAD_TX_MD, addr_phase) | + BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERSRES_HLD, hclk_cycles) | + BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_CS_HI, cs_hi_cycles); +} /** * \brief Set up write enable instruction @@ -792,7 +912,16 @@ void hw_qspi_set_erase_instruction(uint8_t inst, HW_QSPI_BUS_MODE inst_phase, * \sa hw_qspi_set_erase_instruction * */ -void hw_qspi_set_write_enable_instruction(uint8_t write_enable, HW_QSPI_BUS_MODE inst_phase); +static inline void hw_qspi_set_write_enable_instruction(uint8_t write_enable, + HW_QSPI_BUS_MODE inst_phase) + __attribute((always_inline)); + +static inline void hw_qspi_set_write_enable_instruction(uint8_t write_enable, + HW_QSPI_BUS_MODE inst_phase) +{ + HW_QSPIC_REG_SETF(ERASECMDA, WEN_INST, write_enable); + HW_QSPIC_REG_SETF(ERASECMDB, WEN_TX_MD, inst_phase); +} /** * \brief Set up erase suspend/resume instructions @@ -813,11 +942,34 @@ void hw_qspi_set_write_enable_instruction(uint8_t write_enable, HW_QSPI_BUS_MODE * the end of the previous erase resume * */ -void hw_qspi_set_suspend_resume_instructions(uint8_t erase_suspend_inst, +static inline void hw_qspi_set_suspend_resume_instructions(uint8_t erase_suspend_inst, HW_QSPI_BUS_MODE suspend_inst_phase, uint8_t erase_resume_inst, HW_QSPI_BUS_MODE resume_inst_phase, - uint8_t minimum_delay); + uint8_t minimum_delay) + __attribute((always_inline)); + +static inline void hw_qspi_set_suspend_resume_instructions(uint8_t erase_suspend_inst, + HW_QSPI_BUS_MODE suspend_inst_phase, + uint8_t erase_resume_inst, + HW_QSPI_BUS_MODE resume_inst_phase, + uint8_t minimum_delay) +{ + QSPIC->QSPIC_ERASECMDA_REG = + (QSPIC->QSPIC_ERASECMDA_REG & + ~(REG_MSK(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_SUS_INST) | + REG_MSK(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_RES_INST))) | + BITS32(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_SUS_INST, erase_suspend_inst) | + BITS32(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_RES_INST, erase_resume_inst); + QSPIC->QSPIC_ERASECMDB_REG = + (QSPIC->QSPIC_ERASECMDB_REG & + ~(REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_SUS_TX_MD) | + REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RES_TX_MD) | + REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RESSUS_DLY))) | + BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_SUS_TX_MD, suspend_inst_phase) | + BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RES_TX_MD, resume_inst_phase) | + BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RESSUS_DLY, minimum_delay); +} /** * \brief Set status command @@ -856,12 +1008,32 @@ void hw_qspi_set_suspend_resume_instructions(uint8_t erase_suspend_inst, * \sa hw_qspi_get_erase_status * */ -void hw_qspi_set_read_status_instruction(uint8_t inst, HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE receive_phase, - uint8_t busy_pos, - uint8_t busy_val, - uint8_t read_delay, - uint8_t sts_delay); +static inline void hw_qspi_set_read_status_instruction(uint8_t inst, + HW_QSPI_BUS_MODE inst_phase, + HW_QSPI_BUS_MODE receive_phase, + uint8_t busy_pos, + uint8_t busy_val, + uint8_t read_delay, + uint8_t sts_delay) + __attribute((always_inline)); + +static inline void hw_qspi_set_read_status_instruction(uint8_t inst, + HW_QSPI_BUS_MODE inst_phase, + HW_QSPI_BUS_MODE receive_phase, + uint8_t busy_pos, + uint8_t busy_val, + uint8_t read_delay, + uint8_t sts_delay) +{ + QSPIC->QSPIC_STATUSCMD_REG = + BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_BUSY_VAL, busy_val) | + BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_BUSY_POS , busy_pos) | + BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_RX_MD, receive_phase) | + BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_TX_MD, inst_phase) | + BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_INST, inst) | + BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_STSDLY_SEL, sts_delay) | + BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RESSTS_DLY, read_delay); +} /** * \brief Erase block/sector of flash memory @@ -897,6 +1069,8 @@ void hw_qspi_erase_block(uint32_t addr); * 4 = finishing the erase procedure * */ +static inline uint8_t hw_qspi_get_erase_status(void) __attribute__((always_inline)); + static inline uint8_t hw_qspi_get_erase_status(void) { QSPIC->QSPIC_CHCKERASE_REG = 0; @@ -917,13 +1091,27 @@ static inline uint8_t hw_qspi_get_erase_status(void) * of the sequence[3:0] * */ -void hw_qspi_set_break_sequence(uint16_t sequence, HW_QSPI_BUS_MODE mode, - HW_QSPI_BREAK_SEQ_SIZE size, uint8_t dis_out); +static inline void hw_qspi_set_break_sequence(uint16_t sequence, HW_QSPI_BUS_MODE mode, + HW_QSPI_BREAK_SEQ_SIZE size, uint8_t dis_out) + __attribute__((always_inline)); + +static inline void hw_qspi_set_break_sequence(uint16_t sequence, HW_QSPI_BUS_MODE mode, + HW_QSPI_BREAK_SEQ_SIZE size, uint8_t dis_out) +{ + QSPIC->QSPIC_BURSTBRK_REG = + BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_SEC_HF_DS, dis_out) | + BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_SZ, size) | + BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_TX_MD, mode) | + BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_EN, 1) | + BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_WRD, sequence); +} /** * \brief Disable burst break sequence * */ +static inline void hw_qspi_disable_burst_break_sequence(void) __attribute__((always_inline)); + static inline void hw_qspi_disable_burst_break_sequence(void) { HW_QSPIC_REG_SETF(BURSTBRK, BRK_EN, 0); @@ -952,18 +1140,26 @@ void hw_qspi_init(const qspi_config *cfg); * \brief Enable QSPI controller clock * */ +static inline void hw_qspi_enable_clock(void) __attribute__((always_inline)); + static inline void hw_qspi_enable_clock(void) { + GLOBAL_INT_DISABLE(); CRG_TOP->CLK_AMBA_REG |= 1 << REG_POS(CRG_TOP, CLK_AMBA_REG, QSPI_ENABLE); + GLOBAL_INT_RESTORE(); } /** * \brief Disable QSPI controller clock * */ +static inline void hw_qspi_disable_clock(void) __attribute__((always_inline)); + static inline void hw_qspi_disable_clock(void) { + GLOBAL_INT_DISABLE(); CRG_TOP->CLK_AMBA_REG &= ~REG_MSK(CRG_TOP, CLK_AMBA_REG, QSPI_ENABLE); + GLOBAL_INT_RESTORE(); } /** @@ -973,7 +1169,14 @@ static inline void hw_qspi_disable_clock(void) * * \sa HW_QSPI_DIV */ -void hw_qspi_set_div(HW_QSPI_DIV div); +static inline void hw_qspi_set_div(HW_QSPI_DIV div) __attribute__((always_inline)); + +static inline void hw_qspi_set_div(HW_QSPI_DIV div) +{ + GLOBAL_INT_DISABLE(); + REG_SETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV, div); + GLOBAL_INT_RESTORE(); +} /** * \brief Get the QSPI clock divider @@ -982,6 +1185,8 @@ void hw_qspi_set_div(HW_QSPI_DIV div); * * \sa HW_QSPI_DIV */ +static inline HW_QSPI_DIV hw_qspi_get_div(void) __attribute__((always_inline)); + static inline HW_QSPI_DIV hw_qspi_get_div(void) { return REG_GETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV); diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h old mode 100755 new mode 100644 index 8fb87cf2c..928f4a2e0 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h @@ -5,6 +5,7 @@ * \{ * \addtogroup RF * \{ + * \brief Radio Control */ /** @@ -58,14 +59,14 @@ * * @note * ~~~{.c} - * uint32_t hw_rf_get_start_iff_time(void) + * uint64_t hw_rf_get_start_iff_time(void) * ~~~ * * @note Called to get the time when IFF calibration starts * * @note * ~~~{.c} - * bool hw_rf_check_iff_timeout(uint32_t start_time) + * bool hw_rf_check_iff_timeout(uint64_t start_time) * ~~~ * * @note Called to check if IFF calibration has timed-out (i.e. took too long). It takes argument the @@ -97,7 +98,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ #ifndef HW_RF_H_ @@ -106,7 +108,7 @@ #if dg_configUSE_HW_RF #include -#include "black_orca.h" +#include "sdk_defs.h" #include "hw_cpm.h" @@ -114,6 +116,25 @@ #include "hw_fem_sky66112-11.h" #endif +typedef struct __attribute__ ((__packed__)) { + uint8_t tx_power_ble: 4; + uint8_t tx_power_ftdf: 4; +} hw_rf_tx_power_luts_t; + +extern hw_rf_tx_power_luts_t rf_tx_power_luts; + +/** + * \brief Power LUT setting + * + */ +typedef enum { + HW_RF_PWR_LUT_0dbm = 0, /**< TX PWR attenuation 0 dbm */ + HW_RF_PWR_LUT_m1dbm = 1, /**< TX PWR attenuation -1 dbm */ + HW_RF_PWR_LUT_m2dbm = 2, /**< TX PWR attenuation -2 dbm */ + HW_RF_PWR_LUT_m3dbm = 3, /**< TX PWR attenuation -3 dbm */ + HW_RF_PWR_LUT_m4dbm = 4, /**< TX PWR attenuation -4 dbm */ +} HW_RF_PWR_LUT_SETTING; + /** * \brief Initializes RF system, and performs the initial calibration * @@ -122,17 +143,12 @@ * \return True, if iff calib is successful, false otherwise */ bool hw_rf_system_init(void); -/** +/** * \brief Sets parameters according to their recommended values. */ void hw_rf_set_recommended_settings(void); -/** - * \brief (Re)calibrates Intermediate Frequency Filter (IFF). - */ -bool hw_rf_iff_calibration(void); - /** * \brief (Re)calibrates RF DC offset. */ @@ -161,7 +177,70 @@ bool hw_rf_calibration(void); * \return True if calibration was successful, false if not (i.e. iff calib hang) * */ -bool hw_rf_start_calibration(); +bool hw_rf_start_calibration(void); + +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A +/** + * \brief Set TX Power + * + * This actually sets the index of the RF_TX_PWER_LUT_X_REG to use. + * + * \param [in] lut The TX power attenuation setting + * + * \warning Do not call this function before recommended settings are applied + */ +void hw_rf_set_tx_power(HW_RF_PWR_LUT_SETTING lut); +#else + +#ifdef CONFIG_USE_BLE +/** + * \brief Set TX Power for BLE + * + * This actually sets the index of the RF_TX_PWR_LUT_X_REG to use. + * + * \param [in] lut The TX power attenuation setting + * + * \warning Do not call this function before recommended settings are applied + */ +void hw_rf_set_tx_power_ble(HW_RF_PWR_LUT_SETTING lut); +#endif + +#ifdef CONFIG_USE_FTDF +/** + * \brief Set TX Power for FTDF + * + * This actually sets the index of the RF_TX_PWR_LUT_X_REG to use. + * + * \param [in] lut The TX power attenuation setting + * + * \warning Do not call this function before recommended settings are applied + */ +void hw_rf_set_tx_power_ftdf(HW_RF_PWR_LUT_SETTING lut); +#endif + +/** + * \brief Set TX Power + * + * This actually sets the index of the RF_TX_PWR_LUT_X_REG to use. + * + * \param [in] lut The TX power attenuation setting + * + * \deprecated This function is deprecated since it can only set + * BLE and FTDF TX power with the same value. Use hw_rf_set_tx_power_ble() + * and hw_rf_set_tx_power_ftdf() instead. + * + * \warning Do not call this function before recommended settings are applied + */ +static inline void hw_rf_set_tx_power(HW_RF_PWR_LUT_SETTING lut) +{ +#ifdef CONFIG_USE_BLE + hw_rf_set_tx_power_ble(lut); +#endif +#ifdef CONFIG_USE_FTDF + hw_rf_set_tx_power_ftdf(lut); +#endif +} +#endif /** * \brief Turns on RF module. @@ -170,33 +249,39 @@ static inline void hw_rf_poweron(void) __attribute__((always_inline)); static inline void hw_rf_poweron(void) { -#if ( (dg_configUSE_BOD == 1) && (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) \ - && (dg_configBLACK_ORCA_IC_STEP <= BLACK_ORCA_IC_STEP_D)) - hw_cpm_deactivate_bod_protection(); -#endif + if ((dg_configUSE_BOD == 1) && ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)))) { + hw_cpm_deactivate_bod_protection(); + } /* If PD_RAD is up, make sure to power it down to issue a reset */ if (REG_GETF(CRG_TOP, SYS_STAT_REG, RAD_IS_UP)) { -#if ( (dg_configUSE_BOD == 1) && (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) \ - && (dg_configBLACK_ORCA_IC_STEP <= BLACK_ORCA_IC_STEP_D)) - hw_cpm_delay_usec(30); -#endif + if ((dg_configUSE_BOD == 1) && ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)))) { + hw_cpm_delay_usec(30); + } + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RADIO_SLEEP); + GLOBAL_INT_RESTORE(); while (REG_GETF(CRG_TOP, SYS_STAT_REG, RAD_IS_DOWN) == 0x0); } + GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, RADIO_SLEEP); + GLOBAL_INT_RESTORE(); while (!REG_GETF(CRG_TOP, SYS_STAT_REG, RAD_IS_UP)); -#if ( (dg_configUSE_BOD == 1) && (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) \ - && (dg_configBLACK_ORCA_IC_STEP <= BLACK_ORCA_IC_STEP_D)) + if ((dg_configUSE_BOD == 1) && ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)))) { hw_cpm_delay_usec(30); hw_cpm_activate_bod_protection(); -#endif + } // Enable the PLLdig/RFCU clock + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, RFCU_ENABLE); REG_SETF(CRG_TOP, CLK_RADIO_REG, RFCU_DIV, 1); + GLOBAL_INT_RESTORE(); #if dg_configFEM == FEM_SKY66112_11 hw_fem_start(); @@ -212,20 +297,22 @@ static inline void hw_rf_poweroff() hw_fem_stop(); #endif -#if ( (dg_configUSE_BOD == 1) && (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) \ - && (dg_configBLACK_ORCA_IC_STEP <= BLACK_ORCA_IC_STEP_D)) - hw_cpm_deactivate_bod_protection(); - hw_cpm_delay_usec(30); -#endif + if ((dg_configUSE_BOD == 1) && ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)))) { + hw_cpm_deactivate_bod_protection(); + hw_cpm_delay_usec(30); + } + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, RADIO_SLEEP); + GLOBAL_INT_RESTORE(); while (!REG_GETF(CRG_TOP, SYS_STAT_REG, RAD_IS_DOWN)); -#if ( (dg_configUSE_BOD == 1) && (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) \ - && (dg_configBLACK_ORCA_IC_STEP <= BLACK_ORCA_IC_STEP_D)) - hw_cpm_delay_usec(30); - hw_cpm_activate_bod_protection(); -#endif + if ((dg_configUSE_BOD == 1) && ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)))) { + hw_cpm_delay_usec(30); + hw_cpm_activate_bod_protection(); + } } /** @@ -260,7 +347,7 @@ __RETAINED_CODE void hw_rf_request_on(bool mode_ble); */ void hw_rf_request_off(bool mode_ble); -/* +/** * \brief Start transmitting a continuous wave (unmodulated transmission) * * \param [in] mode is the mode to use. 1: BLE, 2 or 3: FTDF (0: Normal, use hw_rf_stop_*) @@ -273,26 +360,12 @@ void hw_rf_request_off(bool mode_ble); */ void hw_rf_start_continuous_wave(uint8_t mode, uint8_t ch); -/* +/** * \brief Stop transmitting a continuous wave (unmodulated transmission) * */ void hw_rf_stop_continuous_wave(void); -/* - * \brief Set TX Power - * - * This actually sets the index of the RF_TX_PWER_LUT_X_REG to use. - * - * \param [in] lut The index of the LUT to use. 0 disables this functionality. - * 1: 0dbm, 2: -1dbm, 3: -2dbm, 4: -3dbm, 5: -4dbm - */ -static inline void hw_rf_set_tx_power(uint8_t lut) -{ - RFCU->RF_TX_PWR_REG = lut; -} - - #endif /* dg_configUSE_HW_RF */ #endif /* HW_RF_H_ */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer0.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer0.h old mode 100755 new mode 100644 index 0d085a0ed..c5dc23a56 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer0.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer0.h @@ -5,6 +5,7 @@ * \{ * \addtogroup Timer0 * \{ + * \brief Timer0 */ /** @@ -37,7 +38,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ @@ -48,7 +50,7 @@ #include #include -#include +#include /** @@ -232,7 +234,9 @@ static inline HW_TIMER0_CLK_SRC hw_timer0_get_clock_source(void) */ static inline void hw_timer0_set_fast_clock_div(HW_TIMER0_FAST_CLK_DIV div) { + GLOBAL_INT_DISABLE(); REG_SETF(CRG_TOP, CLK_TMR_REG, TMR0_DIV, div); + GLOBAL_INT_RESTORE(); } /** diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer1.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer1.h old mode 100755 new mode 100644 index d7931850f..3a56baaa7 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer1.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_timer1.h @@ -5,6 +5,7 @@ * \{ * \addtogroup Timer1 * \{ + * \brief Timer1 */ /** @@ -37,7 +38,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ @@ -48,7 +50,7 @@ #include #include -#include +#include /** @@ -268,9 +270,10 @@ typedef struct { HW_TIMER1_CLK_SRC clk_src; /**< clock source */ uint16_t prescaler; /**< clock prescaler */ + union { timer1_config_timer_capture timer; /**< configuration for timer/capture mode */ timer1_config_oneshot oneshot; /**< configuration for oneshot mode */ - + }; timer1_config_pwm pwm; /**< PWM configuration */ } timer1_config; @@ -323,6 +326,35 @@ void hw_timer1_configure_timer(const timer1_config_timer_capture *cfg); */ void hw_timer1_configure_oneshot(const timer1_config_oneshot *cfg); +/** + * \brief Freeze timer + * + */ +static inline void hw_timer1_freeze(void) +{ + GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk; +} + +/** + * \brief Unfreeze timer + * + */ +static inline void hw_timer1_unfreeze(void) +{ + GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Msk; +} + +/** + * \brief Check if timer is frozen + * + * \return true if it is frozen else false + * + */ +static inline bool hw_timer1_frozen(void) +{ + return GPREG->SET_FREEZE_REG & GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk ? true : false; +} + /** * \brief Set clock source of the timer * @@ -356,11 +388,24 @@ static inline void hw_timer1_set_prescaler(uint16_t value) * \param [in] value reload value * * \sa hw_timer1_set_oneshot_delay - * + * \note For DA14682/3 chips, setting the reload value will also freeze the timer until both + * reload registers are set. */ static inline void hw_timer1_set_reload(uint32_t value) { +#if (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A) && (dg_configUSE_AUTO_CHIP_DETECTION != 1) + bool timer1_frozen = hw_timer1_frozen(); + if (!timer1_frozen) { + hw_timer1_freeze(); + } TIMER1->CAPTIM_RELOAD_REG = (uint16_t) value; + TIMER1->CAPTIM_RELOAD_HIGH_REG = (uint16_t) value >> 16; + if (!timer1_frozen) { + hw_timer1_unfreeze(); + } +#else + TIMER1->CAPTIM_RELOAD_REG = (uint16_t) value; +#endif } /** @@ -626,7 +671,18 @@ static inline HW_TIMER1_MODE hw_timer1_get_mode(void) */ static inline uint32_t hw_timer1_get_count(void) { +#if (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A) && (dg_configUSE_AUTO_CHIP_DETECTION != 1) + uint32_t lo, hi; + GLOBAL_INT_DISABLE(); + do { + lo = TIMER1->CAPTIM_TIMER_VAL_REG; + hi = TIMER1->CAPTIM_TIMER_HVAL_REG; + } while (lo != TIMER1->CAPTIM_TIMER_VAL_REG); + GLOBAL_INT_RESTORE(); + return (hi << 16) | lo; +#else return TIMER1->CAPTIM_TIMER_VAL_REG; +#endif } /** @@ -695,32 +751,20 @@ void hw_timer1_register_int(hw_timer1_handler_cb handler); */ void hw_timer1_unregister_int(void); -/** - * \brief Freeze timer - * - */ -static inline void hw_timer1_freeze(void) -{ - GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk; -} - -/** - * \brief Unfreeze timer - * - */ -static inline void hw_timer1_unfreeze(void) -{ - GPREG->RESET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk; -} - - #else // (dg_configUSER_CAN_USE_TIMER1 == 0) - +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A #define LP_CNT_REG_RANGE ( 16 ) -#define LP_CNT_MAX_VALUE ( (1 << LP_CNT_REG_RANGE) - 1 ) +#else +#define LP_CNT_REG_RANGE ( 32 ) +#endif +#define LP_CNT_MAX_VALUE ( (1ULL << LP_CNT_REG_RANGE) - 1 ) #define LP_CNT_PRESCALED_MASK ( LP_CNT_MAX_VALUE ) -#define LP_CNT_NATIVE_MASK ( (1 << (LP_CNT_REG_RANGE + dg_configTim1PrescalerBitRange)) - 1 ) +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A +#define LP_CNT_NATIVE_MASK ( (1ULL << (LP_CNT_REG_RANGE + dg_configTim1PrescalerBitRange)) - 1 ) +#else +#define LP_CNT_NATIVE_MASK ( (1ULL << (LP_CNT_REG_RANGE)) - 1 ) +#endif /** * \brief Configure timer as tick timer @@ -745,6 +789,8 @@ void hw_timer1_lp_clk_init(void); * \return void * */ +static inline void hw_timer1_int_enable(void) __attribute__((always_inline)); + static inline void hw_timer1_int_enable(void) { HW_TIMER1_REG_SETF(CTRL, CAPTIM_IRQ_EN, 1); @@ -759,6 +805,8 @@ static inline void hw_timer1_int_enable(void) * \return void * */ +static inline void hw_timer1_int_disable(void) __attribute__((always_inline)); + static inline void hw_timer1_int_disable(void) { NVIC_DisableIRQ(SWTIM1_IRQn); @@ -776,7 +824,18 @@ static inline uint32_t hw_timer1_get_value(void) __attribute__((always_inline)); static inline uint32_t hw_timer1_get_value(void) { +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A return TIMER1->CAPTIM_TIMER_VAL_REG; +#else + uint32_t lo, hi; + GLOBAL_INT_DISABLE(); + do { + lo = TIMER1->CAPTIM_TIMER_VAL_REG; + hi = TIMER1->CAPTIM_TIMER_HVAL_REG; + } while (lo != TIMER1->CAPTIM_TIMER_VAL_REG); + GLOBAL_INT_RESTORE(); + return (hi << 16) | lo; +#endif } @@ -795,8 +854,10 @@ static inline uint32_t hw_timer1_get_value(void) * respectively), so the time becomes {1, 0} * - the reading of the prescaler's value will give 0 but {0, 0} is earlier than {0, 3} (when * the operation started) and this may result in errors in time computations. + * \note This macro should be used inside a critical section. * */ +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A #define HW_TIMER1_GET_INSTANT(prescaled, fine) \ do { \ if (dg_configTim1Prescaler != 0) { \ @@ -814,17 +875,45 @@ do { fine = prescaled; \ } \ } while (0) - +#else +#define HW_TIMER1_GET_INSTANT(prescaled, fine) \ +do { \ + uint32_t lo, hi; \ + do { \ + lo = TIMER1->CAPTIM_TIMER_VAL_REG; \ + hi = TIMER1->CAPTIM_TIMER_HVAL_REG; \ + } while (lo != TIMER1->CAPTIM_TIMER_VAL_REG); \ + prescaled = fine = (hi << 16) | lo; \ +} while (0) +#endif /** * \brief Macro to set the trigger value. The previous trigger value is returned to the caller. - * + * \note For DA14682/3 chips, this macro will disable timer1 interrupt until reload registers + * programmed so that false interrupts are avoided. */ +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A #define HW_TIMER1_SET_TRIGGER(value, last_value) \ do { \ last_value = TIMER1->CAPTIM_RELOAD_REG; \ TIMER1->CAPTIM_RELOAD_REG = value; \ } while (0) - +#else +#define HW_TIMER1_SET_TRIGGER(value, last_value) \ +do { \ + bool timer1_irq_en = \ + TIMER1->CAPTIM_CTRL_REG & TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk ? true : false; \ + last_value = TIMER1->CAPTIM_RELOAD_REG | \ + ((uint32_t) TIMER1->CAPTIM_RELOAD_HIGH_REG) << 16; \ + if (timer1_irq_en) { \ + TIMER1->CAPTIM_CTRL_REG &= ~TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk; \ + } \ + TIMER1->CAPTIM_RELOAD_REG = (uint16_t) value; \ + TIMER1->CAPTIM_RELOAD_HIGH_REG = (uint16_t) ((value) >> 16); \ + if (timer1_irq_en) { \ + TIMER1->CAPTIM_CTRL_REG |= TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk; \ + } \ +} while (0) +#endif /** * \brief Get trigger value @@ -834,7 +923,11 @@ do { \ */ static inline uint32_t hw_timer1_get_trigger(void) { +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A return TIMER1->CAPTIM_RELOAD_REG; +#else + return TIMER1->CAPTIM_RELOAD_REG | ((uint32_t) TIMER1->CAPTIM_RELOAD_HIGH_REG) << 16; +#endif } /** @@ -865,7 +958,9 @@ static inline void hw_timer1_invalidate_trigger(void) static inline void hw_timer1_enable(void) { HW_TIMER1_REG_SETF(CTRL, CAPTIM_EN, 1); + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); + GLOBAL_INT_RESTORE(); } /** @@ -875,7 +970,9 @@ static inline void hw_timer1_enable(void) static inline void hw_timer1_disable(void) { HW_TIMER1_REG_SETF(CTRL, CAPTIM_EN, 0); + GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, CLK_TMR_REG, TMR1_ENABLE); + GLOBAL_INT_RESTORE(); } /** diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_trng.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_trng.h old mode 100755 new mode 100644 index b036cf377..9b092433e --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_trng.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_trng.h @@ -29,12 +29,16 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * ***************************************************************************************** */ +#ifndef HW_TRNG_H_ +#define HW_TRNG_H_ + #if dg_configUSE_HW_TRNG -#include +#include /** * \brief TRNG callback. @@ -64,9 +68,24 @@ typedef void (*hw_trng_cb)(void); void hw_trng_enable(hw_trng_cb callback); /** - * \brief TRNG get numbers. + * \brief Get a random number from TRNG. * - * This function reads the random number from the TRNG FIFO. + * This function reads a random number from the TRNG FIFO. + * + * \return A 32-bit unsigned random number. + * + * \warning This function does not check for number availability in the FIFO + * + */ +__attribute__((always_inline)) static inline uint32_t hw_trng_get_number(void) +{ + return *((volatile uint32_t *)MEMORY_TRNG_FIFO); +} + +/** + * \brief Get random numbers from TRNG. + * + * This function fills a buffer with random numbers read from the TRNG FIFO. * * \param [in] buffer The buffer to write the numbers to. * \param [in] size The size of the buffer (max 32). @@ -74,6 +93,8 @@ void hw_trng_enable(hw_trng_cb callback); * \note Do not forget to disable the TRNG after reading the amount of numbers needed to save * power. * + * \warning This function does not check for number availability in the FIFO + * */ void hw_trng_get_numbers(uint32_t* buffer, uint8_t size); @@ -85,14 +106,40 @@ void hw_trng_get_numbers(uint32_t* buffer, uint8_t size); * \return The current level of the TRNG FIFO. * */ -uint8_t hw_trng_get_fifo_level(void); +__RETAINED_CODE uint8_t hw_trng_get_fifo_level(void); /** * \brief TRNG disable. * - * This function disables the TRNG and its interrupt. + * This function stops TRNG, disables its clock and its interrupt. * */ void hw_trng_disable(void); +/** + * \brief Stop TRNG operation. + */ +static inline void hw_trng_stop(void) +{ + REG_CLR_BIT(TRNG, TRNG_CTRL_REG, TRNG_ENABLE); +} + +/** + * \brief Disable TRNG clock. + */ +void hw_trng_disable_clk(void); + +/** + * \brief Disable TRNG interrupt. + */ +void hw_trng_disable_interrupt(void); + +/** + * \brief Clear TRNG pending interrupt. + */ +void hw_trng_clear_pending(void); + #endif /* dg_configUSE_HW_TRNG */ + +#endif /* HW_TRNG_H_ */ + diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_uart.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_uart.h old mode 100755 new mode 100644 index d728a9f94..ea8853320 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_uart.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_uart.h @@ -5,6 +5,7 @@ * \{ * \addtogroup UART * \{ + * \brief UART Controller */ /** @@ -37,7 +38,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ @@ -48,7 +50,7 @@ #include #include -#include +#include #include "hw_dma.h" #ifndef HW_UART_USE_DMA_SUPPORT @@ -263,6 +265,18 @@ void hw_uart_set_isr(HW_UART_ID uart, hw_uart_interrupt_isr isr); typedef void (*hw_uart_tx_callback)(void *user_data, uint16_t written); typedef void (*hw_uart_rx_callback)(void *user_data, uint16_t read); +//======================= Status functions ==================================== + +/** + * \brief Check if a serial transfer is inprogress + * + * \return true or false + */ +static inline bool hw_uart_is_busy(HW_UART_ID uart) +{ + return HW_UART_REG_GETF(uart, USR, UART_BUSY); +} + //===================== Read/Write functions =================================== /** @@ -300,8 +314,10 @@ void hw_uart_write(HW_UART_ID uart, uint8_t data); * * \param [in] uart identifies UART to use * + * \return number of bytes actually received + * */ -void hw_uart_abort_receive(HW_UART_ID uart); +uint16_t hw_uart_abort_receive(HW_UART_ID uart); /** * \brief Get number of bytes currently received by asynchronous read @@ -398,8 +414,6 @@ void hw_uart_read_buffer(HW_UART_ID uart, void *data, uint16_t len); void hw_uart_receive(HW_UART_ID uart, void *data, uint16_t len, hw_uart_rx_callback cb, void *user_data); -void hw_uart_register_simple_rx_callback(void (*callback) (void), HW_UART_ID uart ); - #if HW_UART_USE_DMA_SUPPORT /** @@ -504,6 +518,35 @@ static inline HW_UART_INT hw_uart_get_interrupt_id(HW_UART_ID uart) return (HW_UART_INT) (UBA(uart)->UART2_IIR_FCR_REG & 0xF); } +/** + * \brief Write Scratch pad register + * + * \param [in] uart identifies UART to use + * \param [in] value the value to be written + * + * /warning Reserved when retarget is used else it is free to use. + * + */ +static inline void hw_uart_write_scr(HW_UART_ID uart, uint8_t value) +{ + UBA(uart)->UART2_SCR_REG = value; +} + +/** + * \brief Read Scratch pad register + * + * \param [in] uart identifies UART to use + * + * \return register value + * + * \warning Reserved when retarget is used else it is free to use. + * + */ +static inline uint8_t hw_uart_read_scr(HW_UART_ID uart) +{ + return UBA(uart)->UART2_SCR_REG; +} + //==================== Configuration functions ================================= /** @@ -1162,6 +1205,40 @@ bool hw_uart_tx_in_progress(HW_UART_ID uart); */ bool hw_uart_rx_in_progress(HW_UART_ID uart); +#if dg_configUART_RX_CIRCULAR_DMA + +/** + * \brief Enable circular RX DMA for UART + * + * This reconfigures RX DMA channel to use circular buffer for incoming data and enabled it + * immediately. Incoming data will be read by DMA to intermediate buffer. Subsequent calls to + * hw_uart_receive() will fire callback as soon as enough data are available in buffer to be read, + * but the actual read from intermediate buffer has to be done using hw_uart_copy_rx_circular_dma_buffer(). + * + * Recommended way to move between DMA buffer and user buffer is to call hw_uart_abort_receive() + * that will copy the amount specified on read or the actual number of received bytes if + * hw_uart_abort_receive() was called before requested the amount was received. + * + * \note + * This can be only called for an UART which is configured using \p dg_configUARTx_RX_CIRCULAR_DMA_BUF_SIZE. + * + * \param [in] uart identifies UART to use + * + */ +void hw_uart_enable_rx_circular_dma(HW_UART_ID uart); + +/** + * \brief Copy data from circular RX DMA buffer to user buffer + * + * \param [in] uart identifies UART to use + * \param [in] buf buffer to copy data to + * \param [in] len length of data to copy to buffer + * + */ +void hw_uart_copy_rx_circular_dma_buffer(HW_UART_ID uart, uint8_t *buf, uint16_t len); + +#endif /* dg_configUART_RX_CIRCULAR_DMA */ + #endif /* dg_configUSE_HW_UART */ #endif /* HW_UART_H_ */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_watchdog.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_watchdog.h old mode 100755 new mode 100644 index 729903d47..db969baee --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_watchdog.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_watchdog.h @@ -5,6 +5,7 @@ * \{ * \addtogroup Watchdog_Timer * \{ + * \brief Watchdog Timer */ /** @@ -37,7 +38,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ @@ -47,7 +49,7 @@ #include #include -#include +#include #define NMI_MAGIC_NUMBER 0xDEADBEEF diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_wkup.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_wkup.h old mode 100755 new mode 100644 index 2af016564..5aa83328d --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_wkup.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/hw_wkup.h @@ -5,6 +5,7 @@ * \{ * \addtogroup Wakeup_Timer * \{ + * \brief Wakeup Timer */ /** @@ -37,21 +38,41 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * ***************************************************************************************** */ #ifndef HW_WKUP_H_ #define HW_WKUP_H_ -#if dg_configUSE_HW_USB_WKUP +#if dg_configUSE_HW_WKUP #include #include -#include +#include #include "hw_gpio.h" +#if (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE +#define WKUP_SEL_P0_BASE_REG (volatile uint16_t *)(&WAKEUP->WKUP_SEL_GPIO_P0_REG) +#else +#define WKUP_SEL_P0_BASE_REG (volatile uint16_t *)(&WAKEUP->WKUP_SELECT_P0_REG) +#endif + +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE +/** + * \brief Wakeup timer configuration + * + */ +typedef struct { + uint8_t pin_state[HW_GPIO_NUM_PORTS]; /**< pin states in each port, 1: enabled, 0: disabled */ + uint8_t pin_trigger[HW_GPIO_NUM_PORTS]; /**< pin triggers in each port, 1: low, 0: high */ +} wkup_pin_config_t; +extern volatile wkup_pin_config_t wkup_pin_config; /**< stores wkup pin configuration */ +extern volatile uint8_t wkup_status[HW_GPIO_NUM_PORTS]; /**< stores wakeup sources */ +#endif + /** * \brief Get the mask of a field of an WKUP register. * @@ -96,6 +117,7 @@ WAKEUP->WKUP_##reg##_REG = ((WAKEUP->WKUP_##reg##_REG & ~(WAKEUP_WKUP_##reg##_REG_##field##_Msk)) | \ ((WAKEUP_WKUP_##reg##_REG_##field##_Msk) & ((new_val) << (WAKEUP_WKUP_##reg##_REG_##field##_Pos)))) + /** * \brief Pin state which increments event counter * @@ -110,9 +132,17 @@ typedef enum { * */ typedef struct { - uint8_t threshold; /**< counter threshold */ +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A + /** + * counter threshold + * + * \warning Supported only in DA14680/1 chips + */ + uint8_t threshold; +#endif +#if !((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) uint8_t debounce; /**< debounce time in ms */ - +#endif uint8_t pin_state[HW_GPIO_NUM_PORTS]; /**< pin states in each port, see hw_wkup_configure_port */ uint8_t pin_trigger[HW_GPIO_NUM_PORTS]; /**< pin triggers in each port, see hw_wkup_configure_port */ } wkup_config; @@ -149,7 +179,7 @@ void hw_wkup_configure(const wkup_config *cfg); * Callback function is called when interrupt is generated, i.e. event counter reaches configured * value. Interrupt is automatically enabled after calling this function. Application should reset * interrupt in callback function using hw_wkup_reset_interrupt(). If no callback is specified, - * interrupt will be automatically cleared by driver. + * interrupt will be automatically cleared by the driver. * * \param [in] cb callback function * \param [in] prio the priority of the interrupt @@ -187,23 +217,25 @@ static inline void hw_wkup_reset_interrupt(void) */ void hw_wkup_handler(void); +#if !((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) /** * \brief Set debounce time * * Setting debounce time to 0 will disable hardware debouncing. Maximum debounce time is 63ms. * - * \param [in] time_ms debounce time in miliseconds + * \param [in] time_ms debounce time in milliseconds * */ static inline void hw_wkup_set_debounce_time(uint8_t time_ms) { HW_WKUP_REG_SETF(CTRL, WKUP_DEB_VALUE, time_ms); } +#endif //!((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) /** * \brief Get current debounce time * - * \return debounce time in miliseconds + * \return debounce time in milliseconds * */ static inline uint8_t hw_wkup_get_debounce_time(void) @@ -211,6 +243,7 @@ static inline uint8_t hw_wkup_get_debounce_time(void) return HW_WKUP_REG_GETF(CTRL, WKUP_DEB_VALUE); } +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A /** * \brief Set threshold for event counter * @@ -218,6 +251,7 @@ static inline uint8_t hw_wkup_get_debounce_time(void) * * \param [in] level number of events * + * \warning Supported only in DA14680/1 chips * \sa hw_wkup_register_interrupt * \sa hw_wkup_get_counter * @@ -232,6 +266,7 @@ static inline void hw_wkup_set_counter_threshold(uint8_t level) * * \return number of events * + * \warning Supported only in DA14680/1 chips */ static inline uint8_t hw_wkup_get_counter_threshold(void) { @@ -247,6 +282,8 @@ static inline uint8_t hw_wkup_get_counter_threshold(void) * * \note The counter is automatically reset by the hardware when the interrupt is generated. * + * \warning Supported only in DA14680/1 chips + * * \sa hw_wkup_reset_counter * */ @@ -261,11 +298,13 @@ static inline uint8_t hw_wkup_get_counter(void) * There is no need to reset counter manually in interrupt callback - it's reset automatically by * hardware. * + * \warning Supported only in DA14680/1 chips */ static inline void hw_wkup_reset_counter(void) { WAKEUP->WKUP_RESET_CNTR_REG = 1; } +#endif /** * \brief Set GPIO pin event counting state @@ -284,10 +323,14 @@ static inline void hw_wkup_reset_counter(void) */ static inline void hw_wkup_set_pin_state(HW_GPIO_PORT port, HW_GPIO_PIN pin, bool enabled) { - uint16_t sel_rx_reg = *((volatile uint16_t *)WAKEUP_BASE + 5 + port); - sel_rx_reg &= ~(1 << pin); - sel_rx_reg |= (!!enabled) << pin; - *((volatile uint16_t *)WAKEUP_BASE + 5 + port) = sel_rx_reg; + volatile uint16_t *wkup_pin_enable_reg = WKUP_SEL_P0_BASE_REG + port; + uint16_t wkup_pin_enable_val = *wkup_pin_enable_reg; + wkup_pin_enable_val &= ~(1 << pin); + wkup_pin_enable_val |= (!!enabled) << pin; + *wkup_pin_enable_reg = wkup_pin_enable_val; +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE + wkup_pin_config.pin_state[port] = wkup_pin_enable_val; +#endif } /** \brief Get GPIO pin event counting state @@ -302,8 +345,8 @@ static inline void hw_wkup_set_pin_state(HW_GPIO_PORT port, HW_GPIO_PIN pin, boo */ static inline bool hw_wkup_get_pin_state(HW_GPIO_PORT port, HW_GPIO_PIN pin) { - uint16_t sel_rx_reg = *((volatile uint16_t *)WAKEUP_BASE + 5 + port); - return (sel_rx_reg & (1 << pin)) >> pin; + uint16_t wkup_pin_enable_val = *(WKUP_SEL_P0_BASE_REG + port); + return (wkup_pin_enable_val & (1 << pin)) >> pin; } /** @@ -323,10 +366,13 @@ static inline bool hw_wkup_get_pin_state(HW_GPIO_PORT port, HW_GPIO_PIN pin) static inline void hw_wkup_set_pin_trigger(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_WKUP_PIN_STATE state) { - uint16_t pol_rx_reg = *((volatile uint16_t *)WAKEUP_BASE + 10 + port); + uint16_t pol_rx_reg = *((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + port); pol_rx_reg &= ~(1 << pin); pol_rx_reg |= (!!state) << pin; - *((volatile uint16_t *)WAKEUP_BASE + 10 + port) = pol_rx_reg; + *((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + port) = pol_rx_reg; +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE + wkup_pin_config.pin_trigger[port] = pol_rx_reg; +#endif } /** \brief Get GPIO pin state which triggers event @@ -341,7 +387,7 @@ static inline void hw_wkup_set_pin_trigger(HW_GPIO_PORT port, HW_GPIO_PIN pin, */ static inline HW_WKUP_PIN_STATE hw_wkup_get_pin_trigger(HW_GPIO_PORT port, HW_GPIO_PIN pin) { - uint16_t pol_rx_reg = *((volatile uint16_t *)WAKEUP_BASE + 10 + port); + uint16_t pol_rx_reg = *((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + port); return (pol_rx_reg & (1 << pin)) >> pin; } @@ -387,12 +433,16 @@ static inline void hw_wkup_configure_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin, boo */ static inline void hw_wkup_configure_port(HW_GPIO_PORT port, uint8_t enabled, uint8_t state) { - *((volatile uint16_t *)WAKEUP_BASE + 10 + port) = ~state; // register has inverted logic than state bitmask - *((volatile uint16_t *)WAKEUP_BASE + 5 + port) = enabled; + *((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + port) = ~state; // register has inverted logic than state bitmask + *(WKUP_SEL_P0_BASE_REG + port) = enabled; +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE + wkup_pin_config.pin_state[port] = enabled; + wkup_pin_config.pin_trigger[port] = ~state; +#endif } /** - * \brief Get event counting state of all pins in GPIO port + * \brief Get state (enabled/disabled) of all pins in GPIO port * * Meaning of bits in returned bitmask is the same as in hw_wkup_configure_port(). * @@ -403,7 +453,15 @@ static inline void hw_wkup_configure_port(HW_GPIO_PORT port, uint8_t enabled, ui */ static inline uint8_t hw_wkup_get_port_state(HW_GPIO_PORT port) { - return *((volatile uint16_t *)WAKEUP_BASE + 5 + port); +#if dg_configLATCH_WKUP_SOURCE +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A + return wkup_pin_config.pin_state[port]; +#else + return *((volatile uint16_t *)(&WAKEUP->WKUP_SEL_GPIO_P0_REG) + port); +#endif +#else + return *((volatile uint16_t *)(&WAKEUP->WKUP_SELECT_P0_REG) + port); +#endif } /** @@ -418,7 +476,11 @@ static inline uint8_t hw_wkup_get_port_state(HW_GPIO_PORT port) */ static inline uint8_t hw_wkup_get_port_trigger(HW_GPIO_PORT port) { - return ~(*((volatile uint16_t *)WAKEUP_BASE + 10 + port)); // register has inverted logic that returned bitmask +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE + return wkup_pin_config.pin_trigger[port]; +#else + return ~(*((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + port)); // register has inverted logic that returned bitmask +#endif } /** @@ -451,8 +513,84 @@ static inline void hw_wkup_unfreeze(void) GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk; } -#endif /* dg_configUSE_HW_USB_WKUP */ +/** + * \brief Get port status on last wake up + * + * Meaning of bits in returned bitmask is the same as in hw_wkup_configure_port(). + * + * \return port pin event counter state bitmask + * + * \sa hw_wkup_configure_port + * + */ +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE +static inline uint8_t hw_wkup_get_status(HW_GPIO_PORT port) +{ + return wkup_status[port]; +} +#elif dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +static inline uint8_t hw_wkup_get_status(HW_GPIO_PORT port) +{ + switch (port) { + case HW_GPIO_PORT_0: + return HW_WKUP_REG_GETF(STATUS_0, WKUP_STAT_P0); + case HW_GPIO_PORT_1: + return HW_WKUP_REG_GETF(STATUS_0, WKUP_STAT_P1); + case HW_GPIO_PORT_2: + return HW_WKUP_REG_GETF(STATUS_1, WKUP_STAT_P2); + case HW_GPIO_PORT_3: + return HW_WKUP_REG_GETF(STATUS_2, WKUP_STAT_P3); + case HW_GPIO_PORT_4: + return HW_WKUP_REG_GETF(STATUS_2, WKUP_STAT_P4); + default: + ASSERT_WARNING(0);//Invalid argument + } +} +#endif +/** + * \brief Clear latch status + * + * This function MUST be called by any user-specified interrupt callback, + * to clear the interrupt latch status. + * + * \param [in] port port number + * \param [in] status pin status bitmask + * + * \sa hw_wkup_get_status + */ +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) && dg_configLATCH_WKUP_SOURCE +static inline void hw_wkup_clear_status(HW_GPIO_PORT port, uint8_t status) +{ + ASSERT_WARNING((port>=HW_GPIO_PORT_0) && (port<=HW_GPIO_PORT_4)) + wkup_status[port] &= ~status; +} +#elif dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +static inline void hw_wkup_clear_status(HW_GPIO_PORT port, uint8_t status) +{ + switch (port) { + case HW_GPIO_PORT_0: + HW_WKUP_REG_SETF(CLEAR_0, WKUP_CLEAR_P0, status); + break; + case HW_GPIO_PORT_1: + HW_WKUP_REG_SETF(CLEAR_0, WKUP_CLEAR_P1, status); + break; + case HW_GPIO_PORT_2: + HW_WKUP_REG_SETF(CLEAR_1, WKUP_CLEAR_P2, status); + break; + case HW_GPIO_PORT_3: + HW_WKUP_REG_SETF(CLEAR_2, WKUP_CLEAR_P3, status); + break; + case HW_GPIO_PORT_4: + HW_WKUP_REG_SETF(CLEAR_2, WKUP_CLEAR_P4, status); + break; + default: + ASSERT_WARNING(0);//Invalid argument + } +} +#endif + +#endif /* dg_configUSE_HW_WKUP */ #endif /* HW_WKUP_H_ */ /** diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h b/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h old mode 100755 new mode 100644 index 3e4b4f635..62ec2d8a5 --- a/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h +++ b/third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h @@ -17,30 +17,31 @@ * * @brief TCS Handler header file. * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * +* Copyright (c) 2016, Dialog Semiconductor +* All rights reserved. +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +* **************************************************************************************** */ @@ -48,7 +49,7 @@ #define SYS_TCS_H_ #include -#include "black_orca.h" +#include "sdk_defs.h" typedef enum sys_tcs_area_type { #ifdef CONFIG_USE_BLE @@ -63,8 +64,20 @@ typedef enum sys_tcs_area_type { tcs_system, /* Last area. Add any missing areas above this! */ } sys_tcs_area_t; -extern bool is_calibrated_chip; +/** + * \brief Flag to check whether the TCS is written or not. + * \details true, the TCS is written (the BANDGAP_REG value exists in the TCS) + * false, the TCS is empty + */ +extern bool sys_tcs_is_calibrated_chip; +/** + * \brief The XTAL16M settling time (in TCS). + * \details XTAL32K, the settling time is expressed in clock cycles + * RCX, not applicable; the SDK hard-coded value is used + * If it is zero, the hard-coded value (dg_configXTAL16_SETTLE_TIME) is applied. + */ +extern uint16_t sys_tcs_xtal16m_settling_time; /** * \brief Initialize the variables used from the TCS handling module. diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c index 063f6a50b..0d2d466a6 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c @@ -14,30 +14,31 @@ * * @brief Clock and Power Manager Driver * - * Copyright (c) 2016, Dialog Semiconductor - * All rights reserved. - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * +* Copyright (c) 2016, Dialog Semiconductor +* All rights reserved. +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +* **************************************************************************************** */ @@ -54,7 +55,19 @@ */ extern sys_clk_t cm_sysclk; extern ahb_div_t cm_ahbclk; -\ + + +/* + * Global variables + */ +__RETAINED_UNINIT uint16_t hw_cpm_bod_enabled_in_tcs; + +#if (dg_configPOWER_1V8_ACTIVE == 1) +__RETAINED_RW static bool cpm_1v8_state = true; +#else +static const bool cpm_1v8_state = false; +#endif + /* * Local variables @@ -117,7 +130,9 @@ void hw_cpm_set_divn(bool freq) REG_SET_FIELD(CRG_TOP, CLK_CTRL_REG, DIVN_XTAL32M_MODE, regval, val); REG_SET_FIELD(CRG_TOP, CLK_CTRL_REG, XTAL32M_MODE, regval, val); CRG_TOP->CLK_CTRL_REG = regval; +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) CRG_TOP->DIVN_SYNC_REG = val; +#endif } @@ -329,7 +344,7 @@ void hw_cpm_pll_sys_off(void) } -void hw_cpm_start_calibration(cal_clk_t clk_type, uint32_t cycles) +__RETAINED_CODE void hw_cpm_start_calibration(cal_clk_t clk_type, uint32_t cycles) { ASSERT_WARNING(REG_GETF(ANAMISC, CLK_REF_SEL_REG, REF_CAL_START) == 0); // Must be disabled @@ -386,24 +401,25 @@ void hw_cpm_dcdc_config(void) REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_FAST_RAMPING)); REG_SETF(DCDC, DCDC_VDD_1_REG, DCDC_VDD_CUR_LIM_MAX_LV, 0xD); + + REG_SETF(DCDC, DCDC_V14_0_REG, DCDC_V14_VOLTAGE, 0x7); + + if (dg_configPOWER_1V8_ACTIVE == 1) + { + REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, 0x16); + } + + if (dg_configPOWER_1V8P == 1) + { + REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, 0x16); + } + // End of preferred settings DCDC->DCDC_VDD_1_REG |= ((1 << REG_POS(DCDC, DCDC_VDD_1_REG, DCDC_VDD_ENABLE_HV)) | (1 << REG_POS(DCDC, DCDC_VDD_1_REG, DCDC_VDD_ENABLE_LV))); - REG_SETF(DCDC, DCDC_V14_0_REG, DCDC_V14_VOLTAGE, 0x7); - - if (dg_configPOWER_FLASH == 1) - { - REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, 0x16); - } - - if (dg_configPOWER_EXT_1V8_PERIPHERALS == 1) - { - REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, 0x16); - } - - if (dg_configPOWER_FLASH == 1) + if ((dg_configPOWER_1V8_ACTIVE == 1) && cpm_1v8_state) { DCDC->DCDC_V18_1_REG |= (1 << REG_POS(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV)); DCDC->DCDC_V18_1_REG &= ~REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV); @@ -414,7 +430,7 @@ void hw_cpm_dcdc_config(void) REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV)); } - if (dg_configPOWER_EXT_1V8_PERIPHERALS == 1) + if (dg_configPOWER_1V8P == 1) { DCDC->DCDC_V18P_1_REG |= (1 << REG_POS(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_HV)); DCDC->DCDC_V18P_1_REG &= ~REG_MSK(DCDC, DCDC_V18P_1_REG, DCDC_V18P_ENABLE_LV); @@ -464,11 +480,9 @@ void hw_cpm_set_preferred_values(void) CRG_TOP->CLK_16M_REG = reg; REG_SETF(CRG_TOP, BANDGAP_REG, LDO_SLEEP_TRIM, 0x8); - - if (BLACK_ORCA_TARGET_IC >= BLACK_ORCA_IC_VERSION(A, C)) - { - REG_SETF(CRG_TOP, BANDGAP_REG, BYPASS_COLD_BOOT_DISABLE, 1); // Last review date: Feb 15, 2016 - 12:25:47 - } +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A + REG_SETF(CRG_TOP, BANDGAP_REG, BYPASS_COLD_BOOT_DISABLE, 1); // Last review date: Feb 15, 2016 - 12:25:47 +#endif } void hw_cpm_configure_xtal32k_pins(void) @@ -477,13 +491,16 @@ void hw_cpm_configure_xtal32k_pins(void) GPIO->P21_MODE_REG = 0x26; } +void hw_cpm_configure_ext32k_pins(void) +{ + GPIO->P20_MODE_REG = 0x0; +} + void hw_cpm_trigger_sw_cursor(void) { - volatile int i; - if (dg_configUSE_SW_CURSOR == 1) { - if (dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_B) + if (dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D) { SW_CURSOR_SET = 1 << SW_CURSOR_PIN; } @@ -494,11 +511,9 @@ void hw_cpm_trigger_sw_cursor(void) SW_CURSOR_GPIO = 0x300; - for (i = 0; i < 100; i++) - { - } + hw_cpm_delay_usec(50); - if (dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_B) + if (dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_D) { SW_CURSOR_RESET = 1 << SW_CURSOR_PIN; } @@ -533,7 +548,12 @@ void hw_cpm_assert_trigger_gpio(void) { if (EXCEPTION_DEBUG == 1) { - if (dg_configUSE_LP_CLK != LP_CLK_RCX) + if (dg_configLP_CLK_SOURCE == LP_CLK_IS_DIGITAL) + { + hw_cpm_configure_ext32k_pins(); + } + else if ((dg_configUSE_LP_CLK == LP_CLK_32000) + || (dg_configUSE_LP_CLK == LP_CLK_32768)) { hw_cpm_configure_xtal32k_pins(); } @@ -549,27 +569,27 @@ void hw_cpm_assert_trigger_gpio(void) do { \ uint16_t val = 0; \ \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL_REG, BOD_VDD_LVL, val, 1); /* VDD Level (700mV) */ \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL_REG, BOD_V33_TRIM, val, 2); /* V33 trim */ \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL_REG, BOD_1V8_PA_TRIM, val, 2); /* 1V8P trim */ \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL_REG, BOD_1V8_FLASH_TRIM, val, 2); /* 1V8 trim */ \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL_REG, BOD_VDD_TRIM, val, 2); /* VDD trim */ \ - CRG_TOP->BOD_CTRL_REG = val; \ + REG_SETF(CRG_TOP, BOD_CTRL_REG, BOD_VDD_LVL, 1); /* VDD Level (700mV) */ \ \ - val = 0; \ - /* 1V8 Flash enable */ \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_VBAT_EN, val, 1); \ - /* 1V8 Flash enable */ \ - if ((dg_configPOWER_FLASH == 1) && (dg_configFLASH_POWER_OFF == 0)) { \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN, val, 1); \ + if (hw_cpm_bod_enabled_in_tcs == 0) { \ + val = 0; \ + /* VBAT enable */ \ + REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_VBAT_EN, val, 1); \ + /* 1V8 Flash enable */ \ + if ((dg_configPOWER_1V8_ACTIVE == 1) && (dg_configPOWER_1V8_SLEEP == 1)) { \ + REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN, val, 1); \ + } \ + /* 1V8P enable */ \ + if (dg_configPOWER_1V8P == 1) { \ + REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN, val, 1); \ + } \ + REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_VDD_EN, val, 1); /* VDD enable */ \ + REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_RESET_EN, val, 1); /* Reset enable */\ + CRG_TOP->BOD_CTRL2_REG = val; \ } \ - /* 1V8P enable */ \ - if (dg_configPOWER_EXT_1V8_PERIPHERALS == 1) { \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN, val, 1); \ + else { \ + CRG_TOP->BOD_CTRL2_REG = hw_cpm_bod_enabled_in_tcs; \ } \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_VDD_EN, val, 1); /* VDD enable */ \ - REG_SET_FIELD(CRG_TOP, BOD_CTRL2_REG, BOD_RESET_EN, val, 1); /* Reset enable */ \ - CRG_TOP->BOD_CTRL2_REG = val; \ } while (0); void hw_cpm_activate_bod_protection(void) @@ -582,6 +602,137 @@ void hw_cpm_activate_bod_protection_at_init(void) HW_CPM_ACTIVATE_BOD_PROTECTION } +void hw_cpm_configure_bod_protection(void) +{ + REG_SETF(CRG_TOP, BOD_CTRL_REG, BOD_VDD_LVL, 1); /* VDD Level (700mV) */ + + if (hw_cpm_bod_enabled_in_tcs == 0) + { + /* VBAT enable */ + REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_VBAT_EN); + + /* 1V8 Flash enable */ + if ((dg_configPOWER_1V8_ACTIVE == 1) && (dg_configPOWER_1V8_SLEEP == 1)) + { + REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); + } + else + { + REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); + } + + /* 1V8P enable */ + if (dg_configPOWER_1V8P == 1) + { + REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN); + } + else + { + REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_PA_EN); + } + + /* Generate Reset on a BOD event */ + REG_SET_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_RESET_EN); + } + else + { + CRG_TOP->BOD_CTRL2_REG = hw_cpm_bod_enabled_in_tcs; + } +} + +void hw_cpm_set_1v8_state(bool state) +{ + if ((dg_configPOWER_1V8_ACTIVE == 1) && (cpm_1v8_state != state)) + { + uint32_t reg; + uint32_t dcdc_state; + + GLOBAL_INT_DISABLE(); + + reg = CRG_TOP->LDO_CTRL2_REG; + dcdc_state = (uint32_t)REG_GETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE); + +#if (dg_configPOWER_1V8_ACTIVE == 1) + cpm_1v8_state = state; +#endif + + if (!cpm_1v8_state) + { + // Disable BOD for the 1V8 rail + if (dg_configUSE_BOD == 1) + { + REG_CLR_BIT(CRG_TOP, BOD_CTRL2_REG, BOD_1V8_FLASH_EN); + } + + // Deactivate 1V8 rail in LDOs + REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, reg); + + if (dg_configPOWER_1V8_SLEEP == 1) + { + REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, + reg, 1); + } + + CRG_TOP->LDO_CTRL2_REG = reg; + + // Deactivate 1V8 rail in DCDC + if (dg_configUSE_DCDC == 1) + { + // Disable DCDC to apply change + REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, 0); + + DCDC->DCDC_V18_1_REG &= + ~(REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_HV) | + REG_MSK(DCDC, DCDC_V18_1_REG, DCDC_V18_ENABLE_LV)); + + // Restore DCDC + REG_SETF(DCDC, DCDC_CTRL_0_REG, DCDC_MODE, dcdc_state); + } + } + else + { + // Restore 1V8 rail in LDOs + /* But not when DCDC is running... */ + if (dcdc_state != 1) + { + REG_SET_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_ON, + reg, 1); + } + + if (dg_configPOWER_1V8_SLEEP == 1) + { + REG_CLR_FIELD(CRG_TOP, LDO_CTRL2_REG, LDO_1V8_FLASH_RET_DISABLE, + reg); + } + + CRG_TOP->LDO_CTRL2_REG = reg; + + // Restore 1V8 rail in DCDC + if (dg_configUSE_DCDC == 1) + { + DCDC->DCDC_V18_1_REG |= (1 << REG_POS(DCDC, DCDC_V18_1_REG, + DCDC_V18_ENABLE_HV)); + DCDC->DCDC_V18_1_REG &= ~REG_MSK(DCDC, DCDC_V18_1_REG, + DCDC_V18_ENABLE_LV); + } + + // Restore BOD setup + if (dg_configUSE_BOD == 1) + { + hw_cpm_delay_usec(200); + hw_cpm_configure_bod_protection(); + } + } + + GLOBAL_INT_RESTORE(); + } +} + +bool hw_cpm_get_1v8_state(void) +{ + return cpm_1v8_state; +} + void hw_cpm_delay_usec(uint32_t usec) { sys_clk_t sclk; diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c index d9f5199b8..35726b9b3 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c @@ -12,6 +12,8 @@ * * @file hw_dma.c * + * @brief Implementation of the DMA Low Level Driver. + * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -42,8 +44,6 @@ #if dg_configUSE_HW_DMA -#include -#include #include #include @@ -60,7 +60,7 @@ static struct hw_dma_callback_data void *user_data; } dma_callbacks_user_data[8]; -#define DMA_CHN_REG(reg, chan) ((uint16 *) (((int) &(reg)) + ((chan) << 4))) +#define DMA_CHN_REG(reg, chan) ((volatile uint16 *)(&(reg)) + ((chan) * 8)) /** * \brief Initialize DMA Channel @@ -127,29 +127,95 @@ void hw_dma_channel_initialization(DMA_setup *channel_setup) { case HW_DMA_CHANNEL_0: case HW_DMA_CHANNEL_1: + GLOBAL_INT_DISABLE(); REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, channel_setup->dma_req_mux); + GLOBAL_INT_RESTORE(); break; case HW_DMA_CHANNEL_2: case HW_DMA_CHANNEL_3: + GLOBAL_INT_DISABLE(); REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, channel_setup->dma_req_mux); + GLOBAL_INT_RESTORE(); break; case HW_DMA_CHANNEL_4: case HW_DMA_CHANNEL_5: + GLOBAL_INT_DISABLE(); REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, channel_setup->dma_req_mux); + GLOBAL_INT_RESTORE(); break; case HW_DMA_CHANNEL_6: case HW_DMA_CHANNEL_7: + GLOBAL_INT_DISABLE(); REG_SETF(DMA, DMA_REQ_MUX_REG, DMA67_SEL, channel_setup->dma_req_mux); + GLOBAL_INT_RESTORE(); break; default: break; } + +#if dg_configDMA_DYNAMIC_MUX || (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + /* + * When different DMA channels are used for same device it is important + * that only one trigger is set for specific device at a time. + * Having same trigger for different channels can cause unpredictable results. + * Following code also should help when SPI1 is assigned to non 0 channel. + */ + GLOBAL_INT_DISABLE(); + + switch (channel_setup->channel_number) + { + case HW_DMA_CHANNEL_6: + case HW_DMA_CHANNEL_7: + if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL) == channel_setup->dma_req_mux) + { + REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, HW_DMA_TRIG_NONE); + } + + /* no break */ + case HW_DMA_CHANNEL_4: + case HW_DMA_CHANNEL_5: + if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL) == channel_setup->dma_req_mux) + { + REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, HW_DMA_TRIG_NONE); + } + + /* no break */ + case HW_DMA_CHANNEL_2: + case HW_DMA_CHANNEL_3: + if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL) == channel_setup->dma_req_mux) + { + REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, HW_DMA_TRIG_NONE); + } + + break; + + case HW_DMA_CHANNEL_0: + case HW_DMA_CHANNEL_1: + default: + break; + } + + GLOBAL_INT_RESTORE(); +#endif } +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B) + + //Set REQ_SENSE bit of i2c and Uart peripherals TX path + if (((channel_setup->dma_req_mux == HW_DMA_TRIG_UART_RXTX) || + (channel_setup->dma_req_mux == HW_DMA_TRIG_UART2_RXTX) || + (channel_setup->dma_req_mux == HW_DMA_TRIG_I2C_RXTX) || + (channel_setup->dma_req_mux == HW_DMA_TRIG_I2C2_RXTX)) && + (channel_setup->channel_number & 1)) //odd channels used for TX + { + REG_SET_FIELD(DMA, DMA0_CTRL_REG, REQ_SENSE, *dma_x_ctrl_reg, 1); + } + +#endif src_address = black_orca_phy_addr(channel_setup->src_address); dest_address = black_orca_phy_addr(channel_setup->dest_address); @@ -188,6 +254,69 @@ void hw_dma_channel_initialization(DMA_setup *channel_setup) dma_callbacks_user_data[channel_setup->channel_number].user_data = channel_setup->user_data; } +void hw_dma_channel_update_source(HW_DMA_CHANNEL channel, void *addr, uint16_t length, + hw_dma_transfer_cb cb) +{ + uint32_t phy_addr = black_orca_phy_addr((uint32_t) addr); + + dma_callbacks_user_data[channel].callback = cb; + + // Look up DMAx_A_STARTL_REG address + volatile uint16 *dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel); + + // Look up DMAx_A_STARTH_REG address + volatile uint16 *dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel); + + // Look up DMAX_LEN_REG address + volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel); + + + volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); + + // Set source address registers + *dma_x_a_start_low_reg = (phy_addr & 0xffff); + *dma_x_a_start_high_reg = (phy_addr >> 16); + + *dma_x_int_reg = length - 1; + + // Set the transfer length + *dma_x_len_reg = length - 1; +} + +void hw_dma_channel_update_destination(HW_DMA_CHANNEL channel, void *addr, uint16_t length, + hw_dma_transfer_cb cb) +{ + uint32_t phy_addr = black_orca_phy_addr((uint32_t) addr); + + dma_callbacks_user_data[channel].callback = cb; + + // Look up DMAx_B_STARTL_REG address + volatile uint16 *dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel); + + // Look up DMAx_B_STARTH_REG address + volatile uint16 *dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel); + + // Look up DMAX_LEN_REG address + volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel); + volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); + + // Set destination address registers + *dma_x_b_start_low_reg = (phy_addr & 0xffff); + *dma_x_b_start_high_reg = (phy_addr >> 16); + + *dma_x_int_reg = length - 1; + + // Set the transfer length + *dma_x_len_reg = length - 1; +} + +void hw_dma_channel_update_int_ix(HW_DMA_CHANNEL channel, uint16_t int_ix) +{ + volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel); + + *dma_x_int_reg = int_ix; +} + /** * \brief Enable or disable a DMA channel * @@ -264,7 +393,7 @@ bool hw_dma_channel_active(void) } /** - * \brief Capture Timer Interrupt Handler + * \brief Capture DMA Interrupt Handler * * Calls user interrupt handler * @@ -318,13 +447,13 @@ void DMA_Handler(void) void hw_dma_channel_stop(HW_DMA_CHANNEL channel_number) { // Stopping DMA will clear DMAx_IDX_REG so read it before - uint16 *dma_x_idx_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number); + volatile uint16 *dma_x_idx_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number); dma_helper(channel_number, *dma_x_idx_reg, true); } uint16_t hw_dma_transfered_bytes(HW_DMA_CHANNEL channel_number) { - uint16 *dma_x_int_reg = dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number); + volatile uint16 *dma_x_int_reg = dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number); return *dma_x_int_reg; } diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c index 4ecd46d88..1a606356c 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c @@ -38,13 +38,14 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * ***************************************************************************************** */ #if dg_configFEM == FEM_SKY66112_11 #include "stdint.h" -#include "black_orca.h" +#include "sdk_defs.h" #include "hw_gpio.h" #include "hw_fem_sky66112-11.h" @@ -70,10 +71,6 @@ int hw_fem_set_bias(uint16_t voltage) value = (voltage - 1200) / 27.5; -// /* Value is actually one lower than computed */ -// if (value > 0) -// value--; - #ifdef dg_configFEM_SKY66112_11_FEM_BIAS_V18P REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, value); return 0; @@ -111,6 +108,7 @@ int hw_fem_set_bias2(uint16_t voltage) return 0; } +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A void hw_fem_set_txpower(bool high) { #if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN) @@ -213,6 +211,260 @@ void hw_fem_set_rx_bypass(bool enable) #endif } +bool hw_fem_get_txpower(void) +{ + return fem_config.tx_power; +} + +bool hw_fem_get_tx_bypass(void) +{ + return fem_config.tx_bypass; +} + +bool hw_fem_get_rx_bypass(void) +{ + return fem_config.rx_bypass; +} + +#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ + +#ifdef CONFIG_USE_BLE +bool hw_fem_get_txpower_ble(void) +{ + return fem_config.tx_power_ble; +} + +bool hw_fem_get_tx_bypass_ble(void) +{ + return fem_config.tx_bypass_ble; +} + +bool hw_fem_get_rx_bypass_ble(void) +{ + return fem_config.rx_bypass_ble; +} +#endif /* CONFIG_USE_BLE */ + +#ifdef CONFIG_USE_FTDF +bool hw_fem_get_txpower_ftdf(void) +{ + return fem_config.tx_power_ftdf; +} + +bool hw_fem_get_tx_bypass_ftdf(void) +{ + return fem_config.tx_bypass_ftdf; +} + +bool hw_fem_get_rx_bypass_ftdf(void) +{ + return fem_config.rx_bypass_ftdf; +} +#endif /* CONFIG_USE_FTDF */ + +bool hw_fem_get_txpower(void) +{ + return fem_config.tx_power_ble; +} + +bool hw_fem_get_tx_bypass(void) +{ + return fem_config.tx_bypass_ble; +} + +bool hw_fem_get_rx_bypass(void) +{ + return fem_config.rx_bypass_ble; +} + +static void set_txpower(void) +{ + if (!fem_config.started) + { + return; + } + + /* CHL is always 0 on RX */ + REG_CLR_BIT(RFCU_POWER, RF_PORT_EN_BLE_REG, RF_PORT4_RX); + REG_CLR_BIT(RFCU_POWER, RF_PORT_EN_FTDF_REG, RF_PORT4_RX); + + if (fem_config.tx_power_ble) + { + REG_SET_BIT(RFCU_POWER, RF_PORT_EN_BLE_REG, RF_PORT4_TX); + } + + if (fem_config.tx_power_ftdf) + { + REG_SET_BIT(RFCU_POWER, RF_PORT_EN_FTDF_REG, RF_PORT4_TX); + } + + if (fem_config.tx_power_ble || fem_config.tx_power_ftdf) + { + /* TX Power high. Configure GPIO for DCF. Enable DCF on TX. */ + hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CHL_PORT, + dg_configFEM_SKY66112_11_CHL_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT4_DCF); + } + else + { + /* TX Power low. Stop DCF, set GPIO to low */ + hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CHL_PORT, + dg_configFEM_SKY66112_11_CHL_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); + } +} + + +void hw_fem_set_txpower_ble(bool high) +{ +#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN) + GLOBAL_INT_DISABLE(); + fem_config.tx_power_ble = high; + set_txpower(); + GLOBAL_INT_RESTORE(); +#endif +} + +void hw_fem_set_txpower_ftdf(bool high) +{ +#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN) + GLOBAL_INT_DISABLE(); + fem_config.tx_power_ftdf = high; + set_txpower(); + GLOBAL_INT_RESTORE(); +#endif +} + +void hw_fem_set_txpower(bool high) +{ + hw_fem_set_txpower_ble(high); +} + + + +static void set_bypass(void) +{ + uint16_t m_ble = 0; + uint16_t m_ftdf = 0; + + if (fem_config.tx_bypass_ble) + { + m_ble = RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk; + } + + if (fem_config.rx_bypass_ble) + { + m_ble |= RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk; + } + + if (fem_config.tx_bypass_ftdf) + { + m_ftdf = RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk; + } + + if (fem_config.rx_bypass_ftdf) + { + m_ftdf |= RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk; + } + + REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_BLE_REG, + RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk | + RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk, m_ble); + REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_FTDF_REG, + RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk | + RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk, m_ftdf); + + if (m_ble == 0 && m_ftdf == 0) + { + /* No RX/TX bypass. Drive the interface line to low */ + hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CPS_PORT, + dg_configFEM_SKY66112_11_CPS_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); + } + else + { + /* At least one of TX/RX needs bypass */ + hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CPS_PORT, + dg_configFEM_SKY66112_11_CPS_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT3_DCF); + } +} + +#ifdef CONFIG_USE_BLE +void hw_fem_set_tx_bypass_ble(bool enable) +{ +#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) + GLOBAL_INT_DISABLE(); + fem_config.tx_bypass_ble = enable; + + if (fem_config.started) + { + set_bypass(); + } + + GLOBAL_INT_RESTORE(); +#endif +} + +void hw_fem_set_rx_bypass_ble(bool enable) +{ +#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) + GLOBAL_INT_DISABLE(); + fem_config.rx_bypass_ble = enable; + + if (fem_config.started) + { + set_bypass(); + } + + GLOBAL_INT_RESTORE(); +#endif +} +#endif /* CONFIG_USE_BLE */ + +#ifdef CONFIG_USE_FTDF +void hw_fem_set_tx_bypass_ftdf(bool enable) +{ +#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) + GLOBAL_INT_DISABLE(); + fem_config.tx_bypass_ftdf = enable; + + if (fem_config.started) + { + set_bypass(); + } + + GLOBAL_INT_RESTORE(); +#endif +} + +void hw_fem_set_rx_bypass_ftdf(bool enable) +{ +#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN) + GLOBAL_INT_DISABLE(); + fem_config.rx_bypass_ftdf = enable; + + if (fem_config.started) + { + set_bypass(); + } + + GLOBAL_INT_RESTORE(); +#endif +} +#endif /* CONFIG_USE_FTDF */ + +void hw_fem_set_tx_bypass(bool enable) +{ + hw_fem_set_tx_bypass_ftdf(enable); +} + +void hw_fem_set_rx_bypass(bool enable) +{ + hw_fem_set_rx_bypass_ftdf(enable); +} +#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ + void hw_fem_set_antenna(bool one) { #if defined(dg_configFEM_SKY66112_11_ANTSEL_PORT) && defined(dg_configFEM_SKY66112_11_ANTSEL_PIN) @@ -231,26 +483,11 @@ void hw_fem_set_antenna(bool one) #endif } -bool hw_fem_get_txpower(void) -{ - return fem_config.tx_power; -} - bool hw_fem_get_antenna(void) { return fem_config.antsel; } -bool hw_fem_get_tx_bypass(void) -{ - return fem_config.tx_bypass; -} - -bool hw_fem_get_rx_bypass(void) -{ - return fem_config.rx_bypass; -} - void hw_fem_start(void) { GLOBAL_INT_DISABLE(); @@ -291,6 +528,28 @@ void hw_fem_start(void) HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, fem_config.antsel); #endif + /****************************************************** + * Setup RF_ANT_TRIM GPIOs + */ + + /* RF_ANT_TRIM_0 Config */ +#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN) + hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM0); +#endif + + /* RF_ANT_TRIM_1 Config */ +#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN) + hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM1); +#endif + + /* RF_ANT_TRIM_2 Config */ +#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN) + hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM2); +#endif + /****************************************************** * Setup DCFs */ @@ -339,9 +598,15 @@ void hw_fem_start(void) REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_31_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_TXRESET_DCF); /* Enable DCFs */ +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A RFCU_POWER->RF_PORT_EN_REG = rf_port_en; - hw_fem_set_txpower(fem_config.tx_power); +#else + RFCU_POWER->RF_PORT_EN_BLE_REG = rf_port_en; + RFCU_POWER->RF_PORT_EN_FTDF_REG = rf_port_en; + + set_txpower(); +#endif set_bypass(); GLOBAL_INT_RESTORE(); @@ -353,7 +618,12 @@ void hw_fem_stop(void) fem_config.started = false; /* Stop DCF Timers */ +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A RFCU_POWER->RF_PORT_EN_REG = 0x0; +#else + RFCU_POWER->RF_PORT_EN_BLE_REG = 0x0; + RFCU_POWER->RF_PORT_EN_FTDF_REG = 0x0; +#endif /* Set all FEM interface outputs to GPIO mode, and value 0, in order to get the minimum * possible power consumption from FEM @@ -384,6 +654,21 @@ void hw_fem_stop(void) HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); #endif +#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN) + hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); +#endif + +#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN) + hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); +#endif + +#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN) + hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false); +#endif + GLOBAL_INT_RESTORE(); } #endif /* dg_configFEM == FEM_SKY66112_11 */ diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c index 16c867314..9bbde9fc7 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c @@ -38,6 +38,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -48,15 +49,15 @@ #include /* Register adresses */ -#define PX_DATA_REG_ADDR(_port) ((uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_DATA_REG)) + _port) +#define PX_DATA_REG_ADDR(_port) ((volatile uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_DATA_REG)) + _port) #define PX_DATA_REG(_port) *PX_DATA_REG_ADDR(_port) -#define PX_SET_DATA_REG_ADDR(_port) ((uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_SET_DATA_REG)) + _port) +#define PX_SET_DATA_REG_ADDR(_port) ((volatile uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_SET_DATA_REG)) + _port) #define PX_SET_DATA_REG(_port) *PX_SET_DATA_REG_ADDR(_port) -#define PX_RESET_DATA_REG_ADDR(_port) ((uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_RESET_DATA_REG)) + _port) +#define PX_RESET_DATA_REG_ADDR(_port) ((volatile uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_RESET_DATA_REG)) + _port) #define PX_RESET_DATA_REG(_port) *PX_RESET_DATA_REG_ADDR(_port) -#define PXX_MODE_REG_ADDR(_port, _pin) ((uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P00_MODE_REG)) + (_port * 8) + _pin) +#define PXX_MODE_REG_ADDR(_port, _pin) ((volatile uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P00_MODE_REG)) + (_port * 8) + _pin) #define PXX_MODE_REG(_port, _pin) *PXX_MODE_REG_ADDR(_port, _pin) -#define PX_PADPWR_CTRL_REG_ADDR(_port) ((uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_PADPWR_CTRL_REG)) + _port) +#define PX_PADPWR_CTRL_REG_ADDR(_port) ((volatile uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_PADPWR_CTRL_REG)) + _port) #define PX_PADPWR_CTRL_REG(_port) *PX_PADPWR_CTRL_REG_ADDR(_port) /* on FPGA we cannot read the state of an output GPIO */ @@ -87,7 +88,7 @@ void hw_gpio_configure(const gpio_config cfg[]) { #if dg_configIMAGE_SETUP == DEVELOPMENT_MODE int num_pins = 0; - uint8_t set_mask[HW_GPIO_NUM_PORTS]; // = { }; + uint8_t set_mask[HW_GPIO_NUM_PORTS]; #endif if (!cfg) diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c index d88f5d403..d40d28b6a 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c @@ -38,11 +38,12 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ #include #include -#include "black_orca.h" +#include "sdk_defs.h" #include "hw_hard_fault.h" #include "hw_watchdog.h" #include "hw_cpm.h" @@ -125,15 +126,15 @@ void HardFault_HandlerC(unsigned long *hardfault_args) if (VERBOSE_HARDFAULT) { - printf("HardFault Handler:\n\r"); - printf("- R0 = 0x%08lx\n\r", hardfault_args[0]); - printf("- R1 = 0x%08lx\n\r", hardfault_args[1]); - printf("- R2 = 0x%08lx\n\r", hardfault_args[2]); - printf("- R3 = 0x%08lx\n\r", hardfault_args[3]); - printf("- R12 = 0x%08lx\n\r", hardfault_args[4]); - printf("- LR = 0x%08lx\n\r", hardfault_args[5]); - printf("- PC = 0x%08lx\n\r", hardfault_args[6]); - printf("- xPSR= 0x%08lx\n\r", hardfault_args[7]); + printf("HardFault Handler:\r\n"); + printf("- R0 = 0x%08lx\r\n", hardfault_args[0]); + printf("- R1 = 0x%08lx\r\n", hardfault_args[1]); + printf("- R2 = 0x%08lx\r\n", hardfault_args[2]); + printf("- R3 = 0x%08lx\r\n", hardfault_args[3]); + printf("- R12 = 0x%08lx\r\n", hardfault_args[4]); + printf("- LR = 0x%08lx\r\n", hardfault_args[5]); + printf("- PC = 0x%08lx\r\n", hardfault_args[6]); + printf("- xPSR= 0x%08lx\r\n", hardfault_args[7]); } hw_cpm_assert_trigger_gpio(); diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c index 3e2167c9f..e85461e34 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c @@ -38,6 +38,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -247,7 +248,7 @@ __STATIC_INLINE bool have_prog_error(void) * Function definitions */ -HW_OTPC_SYS_CLK_FREQ hw_otpc_convert_sys_clk_mhz(uint32_t clk_freq) +__RETAINED_CODE HW_OTPC_SYS_CLK_FREQ hw_otpc_convert_sys_clk_mhz(uint32_t clk_freq) { HW_OTPC_SYS_CLK_FREQ f; @@ -376,7 +377,7 @@ void hw_otpc_disable(void) } -void hw_otpc_set_speed(HW_OTPC_SYS_CLK_FREQ clk_speed) +__RETAINED_CODE void hw_otpc_set_speed(HW_OTPC_SYS_CLK_FREQ clk_speed) { ASSERT_WARNING_OTP_CLK_ENABLED; @@ -757,10 +758,19 @@ bool hw_otpc_dma_prog(const uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD (IS_REMAPPED_ADDRESS(p_data) && (remap_type == 0x3))) { OTPC->OTPC_AHBADR_REG = black_orca_phy_addr((uint32_t)p_data); +#if dg_configEXEC_MODE != MODE_IS_CACHED + } + else if (IS_CACHERAM_ADDRESS(p_data)) + { + OTPC->OTPC_AHBADR_REG = black_orca_phy_addr((uint32_t)p_data); +#endif } else { - /* Only RAM addresses are accepted */ + /* + * Destination address can only reside in RAM or Cache RAM, but in case of remapped + * address, REMAP_ADR0 cannot be 0x6 (Cache Data RAM) + */ ASSERT_WARNING(0); } @@ -822,10 +832,19 @@ void hw_otpc_dma_read(uint32_t *p_data, uint32_t cell_offset, HW_OTPC_WORD cell_ (IS_REMAPPED_ADDRESS(p_data) && (remap_type == 0x3))) { OTPC->OTPC_AHBADR_REG = black_orca_phy_addr((uint32_t)p_data); +#if dg_configEXEC_MODE != MODE_IS_CACHED + } + else if (IS_CACHERAM_ADDRESS(p_data)) + { + OTPC->OTPC_AHBADR_REG = black_orca_phy_addr((uint32_t)p_data); +#endif } else { - /* Only RAM addresses are accepted */ + /* + * Destination address can only reside in RAM or Cache RAM, but in case of remapped + * address, REMAP_ADR0 cannot be 0x6 (Cache Data RAM) + */ ASSERT_WARNING(0); } diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c index cd020c124..acef29507 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c @@ -38,33 +38,16 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ #if dg_configUSE_HW_QSPI - - #include -#include +#include "hw_qspi.h" -#define BITS16(base, reg, field, v) \ - ((uint16) (((uint16) (v) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ - (base ## _ ## reg ## _ ## field ## _Msk))) - -#define BITS32(base, reg, field, v) \ - ((uint32) (((uint32) (v) << (base ## _ ## reg ## _ ## field ## _Pos)) & \ - (base ## _ ## reg ## _ ## field ## _Msk))) - -#define GETBITS16(base, reg, v, field) \ - ((uint16) (((uint16) (v)) & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ - (base ## _ ## reg ## _ ## field ## _Pos)) - -#define GETBITS32(base, reg, v, field) \ - ((uint32) (((uint32) (v)) & (base ## _ ## reg ## _ ## field ## _Msk)) >> \ - (base ## _ ## reg ## _ ## field ## _Pos)) - -static const uint8_t dummy_num[] = { 0, 1, 2, 0, 3 }; +__RETAINED_RW uint8_t dummy_num[] = { 0, 1, 2, 0, 3 }; #if (dg_configFLASH_POWER_DOWN == 1) __attribute__((section("text_retained"))) @@ -89,10 +72,7 @@ void hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE mode) } } -#if (dg_configFLASH_POWER_DOWN == 1) -__attribute__((section("text_retained"))) -#endif -void hw_qspi_set_automode(bool automode) +__attribute__((section("text_retained"))) void hw_qspi_set_automode(bool automode) { if (automode) { @@ -125,25 +105,6 @@ void hw_qspi_set_automode(bool automode) HW_QSPIC_REG_SETF(CTRLMODE, AUTO_MD, automode); } -void hw_qspi_set_read_instruction(uint8_t inst, uint8_t send_once, uint8_t dummy_count, - HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE addr_phase, - HW_QSPI_BUS_MODE dummy_phase, - HW_QSPI_BUS_MODE data_phase) -{ - QSPIC->QSPIC_BURSTCMDA_REG = - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST, inst) | - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST_TX_MD, inst_phase) | - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_ADR_TX_MD, addr_phase) | - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_DMY_TX_MD, dummy_phase); - - QSPIC->QSPIC_BURSTCMDB_REG = - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DAT_RX_MD, data_phase) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_INST_MD, send_once) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE, (dummy_count == 3 ? 1 : 0)) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, dummy_num[dummy_count]); -} - void hw_qspi_set_wrapping_burst_instruction(uint8_t inst, HW_QSPI_WRAP_LEN len, HW_QSPI_WRAP_SIZE size) { @@ -157,23 +118,6 @@ void hw_qspi_set_wrapping_burst_instruction(uint8_t inst, HW_QSPI_WRAP_LEN len, BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_MD, 1); } -void hw_qspi_set_extra_byte(uint8_t extra_byte, HW_QSPI_BUS_MODE bus_mode, uint8_t half_disable_out) -{ - QSPIC->QSPIC_BURSTCMDA_REG = - (QSPIC->QSPIC_BURSTCMDA_REG & - ~(REG_MSK(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_BYTE) | - REG_MSK(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_TX_MD))) | - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_BYTE, extra_byte) | - BITS32(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_TX_MD, bus_mode); - - QSPIC->QSPIC_BURSTCMDB_REG = - (QSPIC->QSPIC_BURSTCMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_BYTE_EN) | - REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_HF_DS))) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_BYTE_EN, 1) | - BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_HF_DS, half_disable_out ? 1 : 0); -} - void hw_qspi_set_dummy_bytes_count(uint8_t count) { if (count == 3) @@ -191,68 +135,6 @@ void hw_qspi_set_dummy_bytes_count(uint8_t count) } } -void hw_qspi_set_read_status_instruction(uint8_t inst, HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE receive_phase, - uint8_t busy_pos, - uint8_t busy_val, - uint8_t reset_delay, - uint8_t sts_delay) -{ - QSPIC->QSPIC_STATUSCMD_REG = - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_BUSY_VAL, busy_val) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_BUSY_POS , busy_pos) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_RX_MD, receive_phase) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_TX_MD, inst_phase) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_INST, inst) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_STSDLY_SEL, sts_delay) | - BITS32(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RESSTS_DLY, reset_delay); -} - -void hw_qspi_set_erase_instruction(uint8_t inst, HW_QSPI_BUS_MODE inst_phase, - HW_QSPI_BUS_MODE addr_phase, uint8_t hclk_cycles, - uint8_t cs_hi_cycles) -{ - HW_QSPIC_REG_SETF(ERASECMDA, ERS_INST, inst); - QSPIC->QSPIC_ERASECMDB_REG = - (QSPIC->QSPIC_ERASECMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_TX_MD) | - REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_EAD_TX_MD) | - REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERSRES_HLD) | - REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_CS_HI))) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_TX_MD, inst_phase) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_EAD_TX_MD, addr_phase) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERSRES_HLD, hclk_cycles) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_CS_HI, cs_hi_cycles); -} - -void hw_qspi_set_write_enable_instruction(uint8_t write_enable, HW_QSPI_BUS_MODE inst_phase) -{ - HW_QSPIC_REG_SETF(ERASECMDA, WEN_INST, write_enable); - HW_QSPIC_REG_SETF(ERASECMDB, WEN_TX_MD, inst_phase); -} - -void hw_qspi_set_suspend_resume_instructions(uint8_t erase_suspend_inst, - HW_QSPI_BUS_MODE suspend_inst_phase, - uint8_t erase_resume_inst, - HW_QSPI_BUS_MODE resume_inst_phase, - uint8_t minimum_delay) -{ - QSPIC->QSPIC_ERASECMDA_REG = - (QSPIC->QSPIC_ERASECMDA_REG & - ~(REG_MSK(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_SUS_INST) | - REG_MSK(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_RES_INST))) | - BITS32(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_SUS_INST, erase_suspend_inst) | - BITS32(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_RES_INST, erase_resume_inst); - QSPIC->QSPIC_ERASECMDB_REG = - (QSPIC->QSPIC_ERASECMDB_REG & - ~(REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_SUS_TX_MD) | - REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RES_TX_MD) | - REG_MSK(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RESSUS_DLY))) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_SUS_TX_MD, suspend_inst_phase) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RES_TX_MD, resume_inst_phase) | - BITS32(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RESSUS_DLY, minimum_delay); -} - void hw_qspi_erase_block(uint32_t addr) { if (!hw_qspi_get_automode()) @@ -280,17 +162,6 @@ void hw_qspi_erase_block(uint32_t addr) HW_QSPIC_REG_SETF(ERASECTRL, ERASE_EN, 1); } -void hw_qspi_set_break_sequence(uint16_t sequence, HW_QSPI_BUS_MODE mode, - HW_QSPI_BREAK_SEQ_SIZE size, uint8_t dis_out) -{ - QSPIC->QSPIC_BURSTBRK_REG = - BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_SEC_HF_DS, dis_out) | - BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_SZ, size) | - BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_TX_MD, mode) | - BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_EN, 1) | - BITS32(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_WRD, sequence); -} - void hw_qspi_set_pads(HW_QSPI_SLEW_RATE rate, HW_QSPI_DRIVE_CURRENT current) { QSPIC->QSPIC_GP_REG = @@ -316,11 +187,6 @@ void hw_qspi_init(const qspi_config *cfg) } } -__RETAINED_CODE void hw_qspi_set_div(HW_QSPI_DIV div) -{ - REG_SETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV, div); -} - #endif /* dg_configUSE_HW_QSPI */ /** * \} diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c index f33a6b32e..cc2c6c71e 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c @@ -38,6 +38,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * ***************************************************************************************** */ @@ -45,8 +46,9 @@ #include "hw_rf.h" -#include "black_orca.h" +#include "sdk_defs.h" #include "hw_cpm.h" +#include "hw_gpio.h" #if (dg_configSYSTEMVIEW) # include "SEGGER_SYSVIEW_FreeRTOS.h" @@ -59,23 +61,24 @@ #include "hw_coex.h" #endif +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A #define KMODE_ALPHA_ACAD_PREF 0x0410 #define KMODE_ALPHA_AA_PREF 0x0416 +#define DF1_DAC_CHECK_VALUE 32 +#define DF1_DGAIN_THR0 16 +#define DF1_DGAIN_THR1 24 +#define DF1_DGAIN_THR2 32 +#endif + /* User callbacks (defined as weak functions) definitions */ bool hw_rf_preoff_cb(void) __attribute__((weak)); void hw_rf_postconf_cb(void) __attribute__((weak)); void hw_rf_precalib_cb(void) __attribute__((weak)); void hw_rf_postcalib_cb(void) __attribute__((weak)); void hw_rf_apply_tcs_cb(void) __attribute__((weak)); -uint32_t hw_rf_get_start_iff_time(void) __attribute__((weak)); -bool hw_rf_check_iff_timeout(uint32_t start_time) __attribute__((weak)); - -#if ( (dg_configUSE_BOD == 1) && (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) \ - && (dg_configBLACK_ORCA_IC_STEP <= BLACK_ORCA_IC_STEP_D)) -//# include "sys_clock_mgr.h" -#endif - +uint64_t hw_rf_get_start_iff_time(void) __attribute__((weak)); +bool hw_rf_check_iff_timeout(uint64_t start_time) __attribute__((weak)); #if dg_configFEM == FEM_SKY66112_11 #include "hw_fem_sky66112-11.h" @@ -90,6 +93,29 @@ typedef enum rf_states_e RF_ST_WAIT_NEXT2 } rf_states_e; +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +typedef enum +{ + IFF_MODE_CTRL_BLE = 0, + IFF_MODE_CTRL_FTDF = 1, + IFF_MODE_CTRL_COMBO = 2 +} iff_mode_ctrl_e; + +typedef enum +{ + IFF_MODE_OVR_BLE = 1, + IFF_MODE_OVR_FTDF = 2 +} iff_mode_ovr_e; + +typedef enum +{ + MGC_MODE_CTRL_BLE_GAUSSDAC = 0, + MGC_MODE_CTRL_BLE_TXDAC = 1, + MGC_MODE_CTRL_FTDF = 2 +} mgc_mode_ctrl_e; + +#endif + /** RF status bitmap. */ typedef uint8_t rf_request_t; @@ -100,28 +126,38 @@ typedef uint8_t rf_request_t; #define RF_REQUEST_BLE_ON (1 << 1) + static rf_request_t rf_request __RETAINED; static rf_states_e rf_state __RETAINED; - -static uint8_t kmoda_cal __RETAINED; - +hw_rf_tx_power_luts_t rf_tx_power_luts __RETAINED; /* Variables used for holding previous reg values during gain calib */ static uint32_t rf_cntrl_timer14_reg_set_offset; static uint32_t rf_cntrl_timer_7_reg_value; -static uint32_t rf_enable_config14_ble_reg_value; -static uint32_t rf_enable_config15_ble_reg_value; -static uint32_t rf_enable_config14_ftdf_reg_value; -static uint32_t rf_enable_config15_ftdf_reg_value; static uint32_t rf_cal_ctrl_reg_value; static uint32_t rf_mgain_ctrl_reg_value; static uint32_t rf_mgain_ctrl2_reg_value; static uint16_t rf_synth_ctrl2_ble_reg_value; static uint16_t rf_synth_ctrl2_ftdf_reg_value; + +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A +static uint8_t kmoda_cal __RETAINED; +__RETAINED_RW static uint32_t gg_cal_modified = 128; +static uint32_t rf_enable_config14_ble_reg_value; +static uint32_t rf_enable_config15_ble_reg_value; +static uint32_t rf_enable_config14_ftdf_reg_value; +static uint32_t rf_enable_config15_ftdf_reg_value; static uint16_t rf_bmcw_reg_value; static uint16_t rf_vcocal_ctrl_reg_value; - - +#else +static uint16_t rf_enable_config14_reg_value; +static uint16_t rf_enable_config15_reg_value; +static uint16_t rf_overrule_reg_value; +static uint16_t rf_enable_config23_ble_reg_value; +static uint16_t rf_enable_config23_ftdf_reg_value; +static uint16_t rf_enable_config45_ble_reg_value; +static uint16_t rf_enable_config45_ftdf_reg_value; +#endif bool hw_rf_system_init(void) { bool calib_succeeded; @@ -129,24 +165,21 @@ bool hw_rf_system_init(void) rf_state = RF_ST_OFF; rf_request = 0; +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A + /* Initially set kmoda_cal to its preferred settings value */ - if ((BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, C)) || - (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, D))) + if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) + && (CHIP_IS_AE))) { - kmoda_cal = KMODE_ALPHA_ACAD_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE); - } - else if (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, A)) - { - kmoda_cal = KMODE_ALPHA_AA_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE); - } - else - { - /* Currently, only AA, AC and AD supported */ - ASSERT_WARNING(0); + kmoda_cal = KMODE_ALPHA_ACAD_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, + KMOD_ALPHA_BLE); } -#if dg_configUSE_HW_COEX == 1 - hw_coex_enable(); +#endif + +#if dg_configCOEX_ENABLE_CONFIG == 1 + hw_coex_init(); #endif /* Apply tcs and preferred settings */ hw_rf_apply_tcs_cb(); @@ -166,7 +199,6 @@ bool hw_rf_system_init(void) /* System is ready to be used */ return calib_succeeded; - } /** @@ -183,14 +215,15 @@ void hw_rf_set_recommended_settings(void) // Last change item : Register: RF_KMOD_ALPHA_REG, Field: KMOD_ALPHA_FTDF, Value: 0x10 // File date : June 18, 2015 - 19:16:16 - if ((BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, C)) || - (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, D))) +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A + if (((dg_configUSE_AUTO_CHIP_DETECTION == 1) && (CHIP_IS_AE)) + || (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, E))) { REG_SET_MASKED(DEM, RF_AFC_CTRL_REG, 0x0030, 0x00F5); REG_SET_MASKED(DEM, RF_AGC_CTRL2_REG, 0x003F, 0x0049); // MP - REG_SET_MASKED(DEM, RF_AGC_CTRL1_REG, 0x007F, 0x000A); + REG_SET_MASKED(DEM, RF_AGC_CTRL1_REG, 0x007F, 0x950A); REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_10_REG, 0xFF00, 0x182E); REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_11_REG, 0xFF00, 0x1830); RFCU_POWER->RF_CNTRL_TIMER_12_REG = 0x3C; @@ -209,7 +242,10 @@ void hw_rf_set_recommended_settings(void) REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_3_REG, 0xFF00, 0x1A10); REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818); REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_7_REG, 0xFF00, 0x1818); + REG_SET_MASKED(RFCU, RF_CP_CTRL_BLE_REG, 0x0F0F, 0x7575); + REG_SET_MASKED(RFCU, RF_CP_CTRL_FTDF_REG, 0x0F0F, 0x7575); REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL2_REG, 0x0202, 0x01D0); + REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL3_REG, 0x00FF, 0xDCE4); REG_SET_MASKED(RFCU, RF_DIV_IQ_TX_REG, 0x00FF, 0x00A1); REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG11_BLE_REG, 0x001F, 0x0054); REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG11_FTDF_REG, 0x001F, 0x0054); @@ -252,17 +288,21 @@ void hw_rf_set_recommended_settings(void) REG_SET_MASKED(DEM, RF_FTDF_LOOP_GAIN_PD_REG, 0x00FF, 0x0060); PLLDIG->RF_KMOD_ALPHA_REG = KMODE_ALPHA_ACAD_PREF; REG_SET_MASKED(RFCU, RF_LF_CTRL_REG, 0x001F, 0x00C0); + REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_BLE_REG, 0x0F0F, 0x7474); + REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_FTDF_REG, 0x0F0F, 0x7474); PLLDIG->RF_MGAIN_CTRL2_REG = 0x0006; REG_SET_MASKED(PLLDIG, RF_MGAIN_CTRL_BLE_REG, 0x1C00, 0x1403); - REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_BLE_REG, 0x000F, 0x0001); + REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_BLE_REG, 0x000F, 0x0031); + REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_FTDF_REG, 0x000F, 0x0031); REG_SET_MASKED(RFCU, RF_MIXER_CTRL2_REG, 0x001F, 0x0000); REG_SET_MASKED(PLLDIG, RF_MSKMOD_CTRL1_REG, 0x0003, 0x0003); REG_SET_MASKED(RFCU, RF_REF_OSC_BLE_REG, 0x7FC0, 0x302C); REG_SET_MASKED(RFCU, RF_REF_OSC_FTDF_REG, 0x7FC0, 0x302C); + REG_SET_MASKED(DEM, RF_RSSI_COMP_CTRL_REG, 0xF000, 0x9777); REG_SET_MASKED(RFCU, RF_SPARE1_FTDF_REG, 0x4800, 0x4000); REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, 0x14C0, 0x108B); @@ -276,91 +316,71 @@ void hw_rf_set_recommended_settings(void) /* FTDF specific */ REG_SETF(DEM, RF_FTDF_CTRL5_REG, RSSITH, 1800); } - else if (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, A)) - { - REG_SET_MASKED(DEM, RF_AFC_CTRL_REG, 0x0030, 0x00C5); - - - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_10_REG, 0xFF00, 0x182E); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_11_REG, 0xFF00, 0x1830); - RFCU_POWER->RF_CNTRL_TIMER_12_REG = 0x003C; - RFCU_POWER->RF_CNTRL_TIMER_13_REG = 0x163C; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_15_REG, 0xFF00, 0x1800); - RFCU_POWER->RF_CNTRL_TIMER_16_REG = 0x2207; - RFCU_POWER->RF_CNTRL_TIMER_17_REG = 0x0410; - RFCU_POWER->RF_CNTRL_TIMER_18_REG = 0x0218; - RFCU_POWER->RF_CNTRL_TIMER_19_REG = 0x0218; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_1_REG, 0xFF00, 0x1E00); - RFCU_POWER->RF_CNTRL_TIMER_20_REG = 0x0508; - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_2_REG, 0xFF00, 0x1B08); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_3_REG, 0xFF00, 0x1A10); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818); - REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_7_REG, 0xFF00, 0x1818); - REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL2_REG, 0x0200, 0x01D2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG11_BLE_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG11_FTDF_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG12_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG12_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG15_BLE_REG, 0x03E0, 0x01E0); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG15_FTDF_REG, 0x03E0, 0x01E0); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG19_BLE_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG19_FTDF_REG, 0x001F, 0x0054); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG20_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG20_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG21_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG21_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG22_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG22_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG24_FTDF_REG, 0x03E0, 0x01A0); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG25_FTDF_REG, 0x03E0, 0x0060); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG27_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG27_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG28_BLE_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG28_FTDF_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG29_BLE_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG29_FTDF_REG, 0x001F, 0x00B2); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG33_BLE_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG33_FTDF_REG, 0x001F, 0x0071); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG34_BLE_REG, 0x001F, 0x00F3); - REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG34_FTDF_REG, 0x001F, 0x00F3); - RFCU_POWER->RF_ENABLE_CONFIG42_BLE_REG = 0x0210; - RFCU_POWER->RF_ENABLE_CONFIG42_FTDF_REG = 0x0210; - REG_SET_MASKED(DEM, RF_FTDF_CTRL5_REG, 0x1FFF, 0x4708); - PLLDIG->RF_KMOD_ALPHA_REG = KMODE_ALPHA_AA_PREF; - REG_SET_MASKED(RFCU, RF_LF_CTRL_REG, 0x001F, 0x00C0); - - - - PLLDIG->RF_MGAIN_CTRL2_REG = 0x0006; - REG_SET_MASKED(PLLDIG, RF_MGAIN_CTRL_BLE_REG, 0x1C00, 0x1403); - - - REG_SET_MASKED(RFCU, RF_MIXER_CTRL2_REG, 0x001F, 0x0000); - REG_SET_MASKED(PLLDIG, RF_MSKMOD_CTRL1_REG, 0x0003, 0x0003); - REG_SET_MASKED(RFCU, RF_REF_OSC_BLE_REG, 0x7FC0, 0x302C); - REG_SET_MASKED(RFCU, RF_REF_OSC_FTDF_REG, 0x7FC0, 0x302C); - REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, 0x14C0, 0x108B); - REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, 0x00C0, 0x009B); - REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_1_REG, 0x003F, 0x003B); - REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_2_REG, 0x003F, 0x0037); - RFCU->RF_TX_PWR_LUT_3_REG = 0x01F6; - REG_SET_MASKED(RFCU, RF_TX_PWR_LUT_4_REG, 0x003F, 0x0036); - PLLDIG->RF_VCO_CALCAP_BIT14_REG = 0xD59D; - - /* FTDF specific */ - REG_SETF(DEM, RF_FTDF_CTRL5_REG, RSSITH, 1800); - } - else - { - /* No recommended settings added for the configured chip version. */ - ASSERT_WARNING(0); - } REG_SETF(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE, kmoda_cal); + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_WR, gg_cal_modified); + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); +#else + REG_SET_MASKED(DEM, RF_AFC_CTRL_REG, 0x0330, 0x01F5); + REG_SET_MASKED(DEM, RF_AGC_CTRL1_REG, 0x007F, 0x950A); + REG_SET_MASKED(DEM, RF_AGC_CTRL2_REG, 0x003F, 0x0049); + REG_SET_MASKED(DEM, RF_CCA_RSSITH_REG, 0xE000, 0xE708); + + RFCU_POWER->RF_CNTRL_TIMER_10_REG = 0x0A42; + RFCU_POWER->RF_CNTRL_TIMER_11_REG = 0x0A44; + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_12_REG, 0x00FF, 0x0050); + RFCU_POWER->RF_CNTRL_TIMER_13_REG = 0x0850; + RFCU_POWER->RF_CNTRL_TIMER_14_REG = 0x1858; + RFCU_POWER->RF_CNTRL_TIMER_15_REG = 0x0A50; + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_16_REG, 0xFF00, 0x1207); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_1_REG, 0xFF00, 0x0F00); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_21_REG, 0x00FF, 0x0044); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_22_REG, 0x00FF, 0x0040); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_23_REG, 0x00FF, 0x0052); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_2_REG, 0xFF00, 0x0D08); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_3_REG, 0xFF00, 0x0C10); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x0A18); + REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_7_REG, 0xFF00, 0x0A18); + RFCU->RF_CP_CTRL_BLE_REG = 0x3535; + REG_SET_MASKED(RFCU, RF_CP_CTRL_FTDF_REG, 0x0F0F, 0x7575); + REG_SET_MASKED(DEM, RF_DC_OFFSET_CTRL2_REG, 0x0402, 0x05D0); + REG_SET_MASKED(RFCU, RF_DIV_IQ_TX_REG, 0x00FF, 0x00A1); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG16_REG, 0x001F, 0x0014); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, 0x03E0, 0x0000); + RFCU_POWER->RF_ENABLE_CONFIG42_REG = 0x0210; + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, 0x03E0, 0x0060); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_BLE_REG, 0x001F, 0x0015); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG46_FTDF_REG, 0x001F, 0x0015); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_BLE_REG, 0x001F, 0x0016); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG47_FTDF_REG, 0x001F, 0x0016); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_BLE_REG, 0x001F, 0x0017); + REG_SET_MASKED(RFCU_POWER, RF_ENABLE_CONFIG48_FTDF_REG, 0x001F, 0x0017); + REG_SET_MASKED(DEM, RF_FTDF_CTRL1_REG, 0xC000, 0x47C0); + REG_SET_MASKED(DEM, RF_FTDF_SIGDET_CTRL_REG, 0x1FFF, 0x0B6A); + REG_SET_MASKED(PLLDIG, RF_KMOD_ALPHA_BLE_REG, 0x0FC0, 0x030C); + PLLDIG->RF_KMOD_ALPHA_FTDF_REG = 0x000D; + RFCU->RF_LF_RES_CTRL_BLE_REG = 0x3434; + REG_SET_MASKED(RFCU, RF_LF_CTRL_REG, 0x0040, 0x0080); + REG_SET_MASKED(RFCU, RF_LF_RES_CTRL_FTDF_REG, 0x0F0F, 0x7474); + RFCU->RF_LO_IQ_TRIM_REG = 0x0001; + PLLDIG->RF_MGAIN_CTRL3_REG = 0x0050; + REG_SET_MASKED(PLLDIG, RF_MGAIN_CTRL_FTDF_REG, 0xFF00, 0x5000); + REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_BLE_REG, 0x000F, 0x0031); + REG_SET_MASKED(RFCU, RF_MIXER_CTRL1_FTDF_REG, 0x000F, 0x0031); + REG_SET_MASKED(RFCU, RF_OVERRULE_REG, 0x3C00, 0x5800); + REG_SET_MASKED(DEM, RF_RSSI_COMP_CTRL_REG, 0xF000, 0x9777); + REG_SET_MASKED(RFCU, RF_SPARE1_BLE_REG, 0x0038, 0x0018); + REG_SET_MASKED(RFCU, RF_SPARE1_FTDF_REG, 0x0008, 0x0008); + REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, 0x20C0, 0x304B); + REG_SET_MASKED(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, 0x0040, 0x004B); + RFCU->RF_TX_PWR_LUT_5_REG = 0x09FF; + REG_SET_MASKED(RFCU, RF_TXDAC_CTRL_REG, 0x0040, 0x0000); +#endif } +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A /** * \brief Modulation gain calibration * @@ -370,6 +390,7 @@ void hw_rf_set_recommended_settings(void) */ static void hw_rf_modulation_gain_calibration_start(bool mode_ble) { + uint32_t calcap_mid; // MP-12-02-2016 // Store all the registers that will be changed in this function @@ -421,7 +442,6 @@ static void hw_rf_modulation_gain_calibration_start(bool mode_ble) // Set length dependent on mode , JH-09-11-2015 REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 12); // Need to set ModIndex value to 0x3F. - // XXX This is needed for DA14680AA and DA14680AC for bug_133 workaround. REG_SETF(PLLDIG, RF_SYNTH_CTRL2_FTDF_REG, FTDF_MODINDEX, 0x3F); } else @@ -434,11 +454,6 @@ static void hw_rf_modulation_gain_calibration_start(bool mode_ble) REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x2); // Start with a VCO coarse cal to find the calcap for mid channel - // XXX workaround for - // XXX bug680a0m2_101: MGC does not start with the middle channel after the first calibration. - // XXX Channel intentionally set to 18 (and not 19 or 20) due to issue with wrapping around for mgc channel>31 - // XXX The lower the channel, the more the margin - // XXX MP-12-02-2016 REG_SETF(PLLDIG, RF_BMCW_REG, CN_SEL, 1); REG_SETF(PLLDIG, RF_BMCW_REG, CN_WR, 18); @@ -469,7 +484,211 @@ static void hw_rf_modulation_gain_calibration_start(bool mode_ble) REG_SETF(PLLDIG, RF_VCOCAL_CTRL_REG, VCO_FREQTRIM_SEL, 2); // manual calcap - // XXX --- end of workaround for bug680a0m2_101 and mgc channel wrap around, MP-12-02-2016 + } + + // Disable all calibrations except the modulation gain cal. + RFCU->RF_CAL_CTRL_REG = 0x0038; + + // Clear eo-cal interrupt, such that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; + + // Wait until next calibration can be started + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} + + NVIC_ClearPendingIRQ(RFCAL_IRQn); + + // Start the modulation gain calibration + REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); + + // Wait until the modulation gain calibration has started + while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} +} +#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ +static void hw_rf_modulation_gain_calibration_generic_start(mgc_mode_ctrl_e mode_ctrl, + int16_t average, int16_t mgain_mode, int16_t force, int16_t length) +{ + + // Store all the registers that will be changed in this function + rf_cntrl_timer14_reg_set_offset = REG_GETF(RFCU_POWER, RF_CNTRL_TIMER_14_REG, + SET_OFFSET); + rf_cntrl_timer_7_reg_value = RFCU_POWER->RF_CNTRL_TIMER_7_REG; + rf_enable_config14_reg_value = RFCU_POWER->RF_ENABLE_CONFIG14_REG; + rf_enable_config15_reg_value = RFCU_POWER->RF_ENABLE_CONFIG15_REG; + rf_cal_ctrl_reg_value = RFCU->RF_CAL_CTRL_REG; + rf_mgain_ctrl_reg_value = PLLDIG->RF_MGAIN_CTRL_BLE_REG; + rf_mgain_ctrl2_reg_value = PLLDIG->RF_MGAIN_CTRL2_REG; + rf_synth_ctrl2_ble_reg_value = PLLDIG->RF_SYNTH_CTRL2_BLE_REG; + rf_synth_ctrl2_ftdf_reg_value = PLLDIG->RF_SYNTH_CTRL2_FTDF_REG; + rf_overrule_reg_value = RFCU->RF_OVERRULE_REG; + rf_enable_config23_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG23_BLE_REG; + rf_enable_config23_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG23_FTDF_REG; + rf_enable_config45_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG45_BLE_REG; + rf_enable_config45_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG45_FTDF_REG; + + // move PLLCLOSED_EN to after PLL is in lock + REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_7_REG, SET_OFFSET, + rf_cntrl_timer14_reg_set_offset + 150); + + // Disable PA and PA ramp. + RFCU_POWER->RF_ENABLE_CONFIG14_REG = 0x0000; + RFCU_POWER->RF_ENABLE_CONFIG15_REG = 0x0000; + + // Disable end-of-packet detection (not needed for the MGC) + REG_SET_BIT(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, EO_PACKET_DIS); + + // Set Gain in Analog comparator to 1 + REG_SET_BIT(RFCU, RF_MGC_CTRL_REG, MGC_GAIN_SET); + + + /* Set mode specific settings for BLE mode with GaussDAC */ + if (mode_ctrl == MGC_MODE_CTRL_BLE_GAUSSDAC) + { + /* Set radio in BLE mode */ + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); + /* Inversion of analog comparator signal */ + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); + + if (force != -1) + { + /* Disable Gauss Gain override */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); + } + + if (average != -1) + { + /* Set number of averaging */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); + } + + /* Setting number of zeros and ones */ + if (length == -1) + { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); + } + else + { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, + length & 0x7f); + } + + /* Set modindex to 266kHz */ + REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x2); + /* Select the GaussDac in BLE mode */ + REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, BLE_DAC_SEL, 0x0); + + if (mgain_mode != -1) + { + /* Use the new algorithm */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); + } + + /* Disable TXDAC in BLE mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, txdac_en_ble_dcf_tx, 0x0); + /* Enable GaussDAC in BLE mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, gauss_en_ble_dcf_tx, 0x3); + /* Disable TX-DAC output selection */ + REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x0); + /* Enable GaussDAC output selection switch */ + REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x0); + } + + /* Set mode specific settings for BLE mode with TXDAC */ + if (mode_ctrl == MGC_MODE_CTRL_BLE_TXDAC) + { + /* Set radio in BLE mode */ + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); + /* Inversion of analog comparator signal */ + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); + + if (force != -1) + { + /* Disable Gauss Gain override */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); + } + + if (average != -1) + { + /* Set number of averaging */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); + } + + /* Setting number of zeros and ones */ + if (length == -1) + { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 8); + } + else + { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, + length & 0x7f); + } + + /* Set modindex to 250kHz */ + REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, MODINDEX, 0x0); + /* Select the TXDAC in BLE mode */ + REG_SETF(PLLDIG, RF_SYNTH_CTRL2_BLE_REG, BLE_DAC_SEL, 0x1); + + if (mgain_mode != -1) + { + /* Use the new algorithm */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); + } + + /* Enable TXDAC in BLE mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_BLE_REG, txdac_en_ble_dcf_tx, 0x3); + /* Disable GaussDAC in BLE mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_BLE_REG, gauss_en_ble_dcf_tx, 0x0); + /* Select TX-DAC output selection */ + REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x2); + /* Unselect GaussDAC output selection switch */ + REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x1); + } + + /* Set mode specific settings for FTDF mode */ + if (mode_ctrl == MGC_MODE_CTRL_FTDF) + { + /* Set radio in FTDF mode */ + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x2); + /* Inversion of analog comparator signal */ + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_CMP_INV); + + if (force != -1) + { + /* Disable Gauss Gain override */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL, force & 0x1); + } + + if (average != -1) + { + /* Set number of averaging */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, MGAIN_AVER, average & 0x3); + } + + /* Setting number of zeros and ones */ + if (length == -1) + { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, 16); + } + else + { + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_TRANSMIT_LENGTH, + length & 0x7f); + } + + if (mgain_mode != -1) + { + /* Use the new algorithm */ + REG_SETF(PLLDIG, RF_MGAIN_CTRL2_REG, MGAIN_MODE_SEL, mgain_mode & 0x1); + } + + /* Enable TXDAC in FTDF mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG45_FTDF_REG, txdac_en_ftdf_dcf_tx, 0x3); + /* Disable GaussDAC in FTDF mode */ + REG_SETF(RFCU_POWER, RF_ENABLE_CONFIG23_FTDF_REG, gauss_en_ftdf_dcf_tx, 0x0); + /* Select TX-DAC output selection */ + REG_SETF(RFCU, RF_OVERRULE_REG, TXDAC_SEL, 0x0); + /* Unselect GaussDAC output selection switch */ + REG_SETF(RFCU, RF_OVERRULE_REG, GAUSS_DAC_SEL, 0x0); } // Disable all calibrations except the modulation gain cal. @@ -490,43 +709,113 @@ static void hw_rf_modulation_gain_calibration_start(bool mode_ble) while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} } -static void hw_rf_modulation_gain_calibration_end(void) +static inline void hw_rf_modulation_gain_calibration_start(bool mode_ble) { - uint32_t ch_cal, gg_cal, gg_ch_prod, kmoda_max; // MP-12-02-2016 - uint32_t kmoda_base; - - if ((BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, C)) || - (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, D))) + if (mode_ble) { - kmoda_base = KMODE_ALPHA_ACAD_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE); - } - else if (BLACK_ORCA_TARGET_IC == BLACK_ORCA_IC_VERSION(A, A)) - { - kmoda_base = KMODE_ALPHA_AA_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE); + hw_rf_modulation_gain_calibration_generic_start(MGC_MODE_CTRL_BLE_TXDAC, 2, 1, 0, 8); } else { - /* Currently, only AA, AC and AD supported */ - ASSERT_WARNING(0); + hw_rf_modulation_gain_calibration_generic_start(MGC_MODE_CTRL_FTDF, 2, 1, 0, 8); } +} +#endif +static void hw_rf_modulation_gain_calibration_end(void) +{ +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A + uint32_t ch_cal, gg_cal, gg_ch_prod, kmoda_max, gg0, gg_th1, gg_th2; // MP-12-02-2016 + uint32_t kmoda_base; + uint32_t Y; + uint32_t tmp; + uint32_t dgain_kill_second_jump; + uint32_t dgain; + + if ((dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + || ((dg_configUSE_AUTO_CHIP_DETECTION == 1) + && (CHIP_IS_AE))) + { + kmoda_base = KMODE_ALPHA_ACAD_PREF & REG_MSK(PLLDIG, RF_KMOD_ALPHA_REG, + KMOD_ALPHA_BLE); + } // Clear eo_cal interrupt, so that new calibration can be started RFCU->RF_IRQ_CTRL_REG = 0x0000; - // XXX --- Workaround for bug680a0m2_156: Gauss gain can wrap around after the KmodA compensation, MP-12-02-2016 ch_cal = REG_GETF(PLLDIG, RF_SYNTH_RESULT2_BLE_REG, CN_CAL_RD); gg_cal = REG_GETF(PLLDIG, RF_SYNTH_RESULT_BLE_REG, GAUSS_GAIN_CAL_RD); - gg_ch_prod = (uint32)(gg_cal * ch_cal); - if (gg_ch_prod == 0) // Avoid HardFault due to division by 0 (not likely) + gg0 = gg_cal + ((gg_cal * kmoda_base * ch_cal + 1024) >> 11); + gg_th1 = (gg_cal & 0xE0) + DF1_DAC_CHECK_VALUE; // gg_th1 = (gg_cal&0xE0)+32; + gg_th2 = (gg_th1 + DF1_DAC_CHECK_VALUE); // gg_th2 = (gg_th1+32); + + if (gg0 >= gg_th2) //so 2 jumps are on the left of the cal. channel + { + /* + Formula (MP): + Y = 1 + ((kmoda_base*ch_cal)/2048); + dgain_kill_second_jump = gg_cal - (gg_th2-1)/Y; + + Improve the resolution, + Y = 2048* + (kmoda_base*ch_cal); + dgain_kill_second_jump = gg_cal - (gg_th2-1)*2048/Y; + */ + + Y = 2048 + (kmoda_base * ch_cal); + tmp = (((gg_th2 - 1) << 11) / Y); + + if (gg_cal > tmp) //check to prevent negative value for dgain_kill_second_jump + { + dgain_kill_second_jump = gg_cal - tmp; + + if (dgain_kill_second_jump <= DF1_DGAIN_THR1) + { + dgain = DF1_DGAIN_THR1; + } + else if (dgain_kill_second_jump >= DF1_DGAIN_THR2) + { + dgain = DF1_DGAIN_THR2; // Should never end up here � but better to be safe than sorry. dgain_thr2 is default 16 + } + else + { + dgain = dgain_kill_second_jump; + } + } + else + { + dgain = 0; // End up here because something went wrong with the calculation of tmp! + } + + } + else if (gg0 >= gg_th1) + { + dgain = DF1_DGAIN_THR1; + } + else + { + dgain = DF1_DGAIN_THR0; + } + + if (gg_cal > dgain) + { + gg_cal_modified = gg_cal - dgain; + } + else + { + gg_cal_modified = gg_cal; + } + + gg_ch_prod = (uint32_t)(gg_cal_modified * ch_cal); + + if (gg_ch_prod == 0) // Avoid HardFault due to division by 0 (not likely) { kmoda_cal = kmoda_base; } else { - kmoda_max = (255 * 2048 - 2048 * gg_cal) / gg_ch_prod ; + kmoda_max = (255 * 2048 - 2048 * gg_cal_modified) / gg_ch_prod ; if (kmoda_max >= kmoda_base) { @@ -536,12 +825,10 @@ static void hw_rf_modulation_gain_calibration_end(void) { kmoda_cal = kmoda_max; } - } // This should be done both here (to take effect after calib) AND after preferred settings REG_SETF(PLLDIG, RF_KMOD_ALPHA_REG, KMOD_ALPHA_BLE, kmoda_cal); - // XXX --- end of workaround for bug680a0m2_156, MP-12-02-2016 //Restore the values of the registers that were changed in the function //REG_SET_BIT(PLLDIG, RF_MSKMOD_CTRL1_REG, INV_SDM_POL); // Inverted SDM polarity @@ -561,13 +848,40 @@ static void hw_rf_modulation_gain_calibration_end(void) PLLDIG->RF_BMCW_REG = rf_bmcw_reg_value; // MP-12-02-2016 PLLDIG->RF_VCOCAL_CTRL_REG = rf_vcocal_ctrl_reg_value; // MP-12-02-2016 + REG_SETF(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_WR, gg_cal_modified); + REG_SET_BIT(PLLDIG, RF_MGAIN_CTRL_BLE_REG, GAUSS_GAIN_SEL); + // Disable overrule mode RFCU->RF_OVERRULE_REG &= ~REG_MSK(RFCU, RF_OVERRULE_REG, RF_MODE_OVR); +#else + // Clear eo_cal interrupt, so that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; + + //Restore the values of the registers that were changed in the function + RFCU_POWER->RF_CNTRL_TIMER_7_REG = rf_cntrl_timer_7_reg_value; + RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG14_REG = rf_enable_config14_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG15_REG = rf_enable_config15_reg_value; + PLLDIG->RF_MGAIN_CTRL_BLE_REG = rf_mgain_ctrl_reg_value; + PLLDIG->RF_MGAIN_CTRL2_REG = rf_mgain_ctrl2_reg_value; + PLLDIG->RF_SYNTH_CTRL2_BLE_REG = rf_synth_ctrl2_ble_reg_value; + PLLDIG->RF_SYNTH_CTRL2_FTDF_REG = rf_synth_ctrl2_ftdf_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG23_BLE_REG = rf_enable_config23_ble_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG23_FTDF_REG = rf_enable_config23_ftdf_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG45_BLE_REG = rf_enable_config45_ble_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG45_FTDF_REG = rf_enable_config45_ftdf_reg_value; + + // Disable overrule mode + RFCU->RF_OVERRULE_REG = rf_overrule_reg_value; + +#endif } /** - * \brief Modulation gain calibration - Wrapper function for - * standalone (not coex) mode + * \brief Modulation gain calibration - Wrapper function + * + * Used on boot, and generally whenever the interrupt-based approach is not + * needed * * \param[in] bool, true for FTDF, false for BLE * @@ -586,6 +900,7 @@ void hw_rf_modulation_gain_calibration(bool mode_ble) void hw_rf_dc_offset_calibration(void) { +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A // Save the values of registers that will be changed in the function uint32_t RF_ENABLE_CONFIG0_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG; uint32_t RF_ENABLE_CONFIG1_BLE_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG; @@ -594,7 +909,7 @@ void hw_rf_dc_offset_calibration(void) uint32_t RF_DC_OFFSET_CTRL2_REG_value = DEM->RF_DC_OFFSET_CTRL2_REG; uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; - uint32_t rf_overrule_reg_value = RFCU->RF_OVERRULE_REG; + uint32_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; // Required setting for the DC-offset calibration RFCU_POWER->RF_ENABLE_CONFIG0_BLE_REG = 0x0000; // Disable LNA_LDO @@ -635,13 +950,64 @@ void hw_rf_dc_offset_calibration(void) DEM->RF_DC_OFFSET_CTRL2_REG = RF_DC_OFFSET_CTRL2_REG_value; RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; - RFCU->RF_OVERRULE_REG = rf_overrule_reg_value; + RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; +#else /* REV_B */ + // Save the values of registers that will be changed in the function + uint32_t RF_ENABLE_CONFIG0_REG_value = RFCU_POWER->RF_ENABLE_CONFIG0_REG; + uint32_t RF_ENABLE_CONFIG1_REG_value = RFCU_POWER->RF_ENABLE_CONFIG1_REG; + uint32_t RF_ENABLE_CONFIG2_REG_value = RFCU_POWER->RF_ENABLE_CONFIG2_REG; + + uint32_t RF_DC_OFFSET_CTRL2_REG_value = DEM->RF_DC_OFFSET_CTRL2_REG; + uint32_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; + uint32_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; + + // Required setting for the DC-offset calibration + RFCU_POWER->RF_ENABLE_CONFIG0_REG = 0x0000; // Disable LNA_LDO + RFCU_POWER->RF_ENABLE_CONFIG1_REG = 0x0000; // Disable LNA_CORE + RFCU_POWER->RF_ENABLE_CONFIG2_REG = 0x0000; // Disable LNA_CGM + + // DCNGAIN = 3, DCNSTEP = 5, DCPARCAL_EN = 0, DCOFFSET_SEL = 0 + DEM->RF_DC_OFFSET_CTRL2_REG = 0x01D0; + // Disable all calibrations except the DC-offset cal. + RFCU->RF_CAL_CTRL_REG = 0x002C; + + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0x1); // Overrule RF_MODE <- BLE_MODE + + // Clear eo-cal interrupt, so that new calibration can be stared + RFCU->RF_IRQ_CTRL_REG = 0x0000; + + // Wait until the DC-offset calibration can be started + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) {} + + // Start the modulation gain calibration + REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); + + // Wait until the modulation gain calibration has started + while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) {} + + // Wait until the modulation gain calibration is completed + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) {} + + // Clear eo-cal interrupt, so that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; + + // Restore the values of registers that were changed in the function + RFCU_POWER->RF_ENABLE_CONFIG0_REG = RF_ENABLE_CONFIG0_REG_value; + RFCU_POWER->RF_ENABLE_CONFIG1_REG = RF_ENABLE_CONFIG1_REG_value; + RFCU_POWER->RF_ENABLE_CONFIG2_REG = RF_ENABLE_CONFIG2_REG_value; + + DEM->RF_DC_OFFSET_CTRL2_REG = RF_DC_OFFSET_CTRL2_REG_value; + RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; + RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; +#endif } + + +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A bool hw_rf_iff_calibration(void) { - - uint32_t start_time; + uint64_t start_time; uint16_t calcap_result; @@ -755,17 +1121,189 @@ bool hw_rf_iff_calibration(void) RFCU_POWER->RF_ENABLE_CONFIG1_BLE_REG = RF_ENABLE_CONFIG1_BLE_REG_value; RFCU_POWER->RF_ENABLE_CONFIG2_BLE_REG = RF_ENABLE_CONFIG2_BLE_REG_value; RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = RF_ENABLE_CONFIG46_BLE_REG_value; + return true; +} +#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */ +static bool iff_calib_internal(iff_mode_ovr_e rf_mode_ovr, iff_mode_ctrl_e mode_ctrl) +{ + uint16_t calcap_result; + uint64_t start_time; + + // Set mode + REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, rf_mode_ovr); + + // Disable all calibrations except the Iff cal. + RFCU->RF_CAL_CTRL_REG = 0x0034; + + // Select the IF calcap to use the FSM value + REG_SET_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); + + // Clear eo-cal interrupt, so that new calibration can be stared + RFCU->RF_IRQ_CTRL_REG = 0x0000; + + start_time = hw_rf_get_start_iff_time(); + + // Wait until the IFF calibration can be started + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, EO_CAL)) + { + if (hw_rf_check_iff_timeout(start_time)) + { + /* IFF lockup detected. Abort */ + return false; + } + } + + // Start the IFF calibration + REG_SET_BIT(RFCU, RF_CAL_CTRL_REG, SO_CAL); + + // Wait until the IFF calibration has started + while (!(RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL))) + { + if (hw_rf_check_iff_timeout(start_time)) + { + /* IFF lockup detected. Abort */ + return false; + } + } + + // Wait until the IFF calibration is completed + while (RFCU->RF_CAL_CTRL_REG & REG_MSK(RFCU, RF_CAL_CTRL_REG, SO_CAL)) + { + if (hw_rf_check_iff_timeout(start_time)) + { + /* IFF lockup detected. Abort */ + return false; + } + } + + // Clear eo-cal interrupt, so that new calibration can be started + RFCU->RF_IRQ_CTRL_REG = 0x0000; + + // Store the result to all IFF CC BLE registers + calcap_result = RFCU->RF_IFF_CAL_CAP_STAT_REG; + + if (mode_ctrl != IFF_MODE_CTRL_COMBO || rf_mode_ovr == IFF_MODE_OVR_BLE) + { + RFCU->RF_IFF_CC_BLE_SET1_REG = calcap_result; + RFCU->RF_IFF_CC_BLE_SET2_REG = calcap_result; + } + + switch (mode_ctrl) + { + case IFF_MODE_CTRL_BLE: // BLE + RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result - 2; + RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result - 2; + break; + + case IFF_MODE_CTRL_FTDF: // FTDF + RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result + 2; + RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result + 2; + break; + + case IFF_MODE_CTRL_COMBO: // COMBO + if (rf_mode_ovr == IFF_MODE_OVR_FTDF) + { + RFCU->RF_IFF_CC_FTDF_SET1_REG = calcap_result; + RFCU->RF_IFF_CC_FTDF_SET2_REG = calcap_result; + } + + break; + } return true; } +static bool hw_rf_iff_calibration(iff_mode_ctrl_e mode_ctrl) +{ + bool ret; + + ////////////////////////////////////////////////////////////// + /// Capacitance calibration for different modes + /// mode_ctrl=0 : Calibration in BLE mode, use offsetted values in FTDF + /// mode_ctrl=1 : Calibration in FTDF mode, use offsetted values in BLE + /// mode_ctrl=2 : Calibration done in BLE mode and FTDF mode + ////////////////////////////////////////////////////////////// + + + // Save the values of registers that will be changed in the function + uint16_t rf_cal_ctrl_reg_value_local = RFCU->RF_CAL_CTRL_REG; + uint16_t rf_overrule_reg_value_local = RFCU->RF_OVERRULE_REG; + uint16_t rf_enable_config0_reg_value = RFCU_POWER->RF_ENABLE_CONFIG0_REG; + uint16_t rf_enable_config1_reg_value = RFCU_POWER->RF_ENABLE_CONFIG1_REG; + uint16_t rf_enable_config2_reg_value = RFCU_POWER->RF_ENABLE_CONFIG2_REG; + uint16_t rf_enable_config46_ble_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG; + uint16_t rf_enable_config46_ftdf_reg_value = RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG; + uint16_t rf_dc_offset_ctrl2_reg_value = DEM->RF_DC_OFFSET_CTRL2_REG; + + // Required setting for the DC-offset calibration + RFCU_POWER->RF_ENABLE_CONFIG0_REG = 0x0000; // Disable LNA_LDO + RFCU_POWER->RF_ENABLE_CONFIG1_REG = 0x0000; // Disable LNA_CORE + RFCU_POWER->RF_ENABLE_CONFIG2_REG = 0x0000; // Disable LNA_CGM + RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = 0x0000; // Disable the DCF triggered Partial DCOC + RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = 0x0000; // Disable the DCF triggered Partial DCOC + REG_SETF(DEM, RF_DC_OFFSET_CTRL2_REG, DCPARCAL_EN, 0x0); + + + switch (mode_ctrl) + { + case IFF_MODE_CTRL_BLE: // BLE + ret = iff_calib_internal(IFF_MODE_OVR_BLE, IFF_MODE_CTRL_BLE); + break; + + case IFF_MODE_CTRL_FTDF: // FTDF + ret = iff_calib_internal(IFF_MODE_OVR_FTDF, IFF_MODE_CTRL_FTDF); + break; + + case IFF_MODE_CTRL_COMBO: // COMBO + ret = iff_calib_internal(IFF_MODE_OVR_BLE, IFF_MODE_CTRL_COMBO); + + if (!ret) + { + ret = iff_calib_internal(IFF_MODE_OVR_FTDF, IFF_MODE_CTRL_COMBO); + } + + break; + } + + if (!ret) + { + return false; + } + + // Restore the values of registers that were changed in the function + RFCU->RF_CAL_CTRL_REG = rf_cal_ctrl_reg_value_local; + RFCU->RF_OVERRULE_REG = rf_overrule_reg_value_local; + RFCU_POWER->RF_ENABLE_CONFIG0_REG = rf_enable_config0_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG1_REG = rf_enable_config1_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG2_REG = rf_enable_config2_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG46_BLE_REG = rf_enable_config46_ble_reg_value; + RFCU_POWER->RF_ENABLE_CONFIG46_FTDF_REG = rf_enable_config46_ftdf_reg_value; + DEM->RF_DC_OFFSET_CTRL2_REG = rf_dc_offset_ctrl2_reg_value; + + // De-select the IF calcap to use the FSM value + REG_CLR_BIT(RFCU, RF_IFF_CTRL1_REG, IF_SELECT_FSM); + + return true; +} +#endif + bool hw_rf_calibration(void) { bool iff_result; GLOBAL_INT_DISABLE(); hw_rf_dc_offset_calibration(); +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A iff_result = hw_rf_iff_calibration(); +#else +#if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) + iff_result = hw_rf_iff_calibration(0x2); +#elif defined(CONFIG_USE_BLE) + iff_result = hw_rf_iff_calibration(0x0); +#elif defined(CONFIG_USE_FTDF) + iff_result = hw_rf_iff_calibration(0x1); +#endif +#endif if (iff_result) { @@ -791,8 +1329,8 @@ void hw_rf_request_on(bool mode_ble) { hw_rf_poweron(); rf_state = RF_ST_ON; -#if dg_configUSE_HW_COEX == 1 - hw_coex_enable(); +#if dg_configCOEX_ENABLE_CONFIG == 1 + hw_coex_apply_config(); #endif } } @@ -839,6 +1377,8 @@ void hw_rf_request_off(bool mode_ble) bool hw_rf_start_calibration() { + bool iff_result; + if (rf_state == RF_ST_CONFIG) { /* Call pre-calibration user cb */ @@ -857,7 +1397,19 @@ bool hw_rf_start_calibration() hw_rf_dc_offset_calibration(); /* Perform IFF calibration */ - if (!hw_rf_iff_calibration()) +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A + iff_result = hw_rf_iff_calibration(); +#else /* BLACK_ORCA_IC_REV_B */ +#if defined(CONFIG_USE_FTDF) && defined(CONFIG_USE_BLE) + iff_result = hw_rf_iff_calibration(0x2); +#elif defined(CONFIG_USE_BLE) + iff_result = hw_rf_iff_calibration(0x0); +#elif defined(CONFIG_USE_FTDF) + iff_result = hw_rf_iff_calibration(0x1); +#endif +#endif + + if (iff_result == false) { return false; } @@ -970,6 +1522,19 @@ void hw_rf_request_recommended_settings(void) { hw_rf_apply_tcs_cb(); hw_rf_set_recommended_settings(); + + /* Initialize TX Power LUTs */ +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A + hw_rf_set_tx_power(rf_tx_power_luts.tx_power_ble); +#else +#ifdef CONFIG_USE_BLE + hw_rf_set_tx_power_ble(rf_tx_power_luts.tx_power_ble); +#endif +#ifdef CONFIG_USE_FTDF + hw_rf_set_tx_power_ftdf(rf_tx_power_luts.tx_power_ftdf); +#endif +#endif + rf_state = RF_ST_CONFIG; hw_rf_postconf_cb(); } @@ -1001,6 +1566,32 @@ void hw_rf_stop_continuous_wave(void) REG_SETF(RFCU, RF_OVERRULE_REG, TX_EN_OVR, 0); // NORMAL TX REG_SETF(RFCU, RF_OVERRULE_REG, RF_MODE_OVR, 0); // NORMAL RF mode, so disable BLE mode } + +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A +void hw_rf_set_tx_power(HW_RF_PWR_LUT_SETTING lut) +{ + RFCU->RF_TX_PWR_REG = lut; + rf_tx_power_luts.tx_power_ble = lut; +} +#else + +#ifdef CONFIG_USE_BLE +void hw_rf_set_tx_power_ble(HW_RF_PWR_LUT_SETTING lut) +{ + RFCU->RF_TX_PWR_BLE_REG = lut; + rf_tx_power_luts.tx_power_ble = lut; +} +#endif + +#ifdef CONFIG_USE_FTDF +void hw_rf_set_tx_power_ftdf(HW_RF_PWR_LUT_SETTING lut) +{ + RFCU->RF_TX_PWR_FTDF_REG = lut; + rf_tx_power_luts.tx_power_ftdf = lut; +} +#endif + +#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A */ #endif /* dg_configUSE_HW_RF */ /** * \} diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c index 1af9e6432..17cff4b7c 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c @@ -38,6 +38,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -45,7 +46,7 @@ #include -#include +#include #include #if (dg_configSYSTEMVIEW) diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c index 868422921..253deca7a 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c @@ -29,6 +29,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -44,31 +45,26 @@ #endif #define HW_TRNG_FIFO_DEPTH (32) -#define HW_TRNG_RAM (0x40040000) static hw_trng_cb trng_cb; -static void hw_disable_trng(void) -{ - REG_CLR_BIT(TRNG, TRNG_CTRL_REG, TRNG_ENABLE); -} - -static void hw_disable_trng_clk(void) +void hw_trng_disable_clk(void) { + GLOBAL_INT_DISABLE(); REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE); + GLOBAL_INT_RESTORE(); } -static void hw_trng_clear_pending(void) +void hw_trng_clear_pending(void) { - // read TRNG_FIFOLVL_REG to clear level-sensitive source. - TRNG->TRNG_FIFOLVL_REG; + uint32_t dummy __attribute__((unused)); + /* read TRNG_FIFOLVL_REG to clear level-sensitive source. */ + dummy = TRNG->TRNG_FIFOLVL_REG; NVIC_ClearPendingIRQ(TRNG_IRQn); } void hw_trng_enable(hw_trng_cb callback) { - hw_trng_disable(); - if (callback != NULL) { trng_cb = callback; @@ -76,7 +72,9 @@ void hw_trng_enable(hw_trng_cb callback) NVIC_EnableIRQ(TRNG_IRQn); } + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE); + GLOBAL_INT_RESTORE(); REG_SET_BIT(TRNG, TRNG_CTRL_REG, TRNG_ENABLE); } @@ -89,26 +87,34 @@ void hw_trng_get_numbers(uint32_t *buffer, uint8_t size) for (int i = 0; i < size ; i++) { - buffer[i] = *((volatile uint32_t *)HW_TRNG_RAM); + buffer[i] = hw_trng_get_number(); } } -uint8_t hw_trng_get_fifo_level(void) +__RETAINED_CODE uint8_t hw_trng_get_fifo_level(void) { return (TRNG->TRNG_FIFOLVL_REG) & (REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOLVL) | REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOFULL)); } +void hw_trng_disable_interrupt(void) +{ + NVIC_DisableIRQ(TRNG_IRQn); + trng_cb = NULL; +} + void hw_trng_disable(void) { - hw_disable_trng(); - NVIC_DisableIRQ(TRNG_IRQn); + hw_trng_stop(); + hw_trng_disable_interrupt(); hw_trng_clear_pending(); - hw_disable_trng_clk(); + hw_trng_disable_clk(); } void TRNG_Handler(void) { + uint32_t dummy __attribute__((unused)); + SEGGER_SYSTEMVIEW_ISR_ENTER(); if (trng_cb != NULL) @@ -116,7 +122,8 @@ void TRNG_Handler(void) trng_cb(); } - hw_trng_clear_pending(); + /* read TRNG_FIFOLVL_REG to clear level-sensitive source. */ + dummy = TRNG->TRNG_FIFOLVL_REG; SEGGER_SYSTEMVIEW_ISR_EXIT(); } diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c index 734526e2f..5462b5b46 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c @@ -38,6 +38,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -45,7 +46,7 @@ #include -#include +#include #include #include @@ -56,6 +57,56 @@ # define SEGGER_SYSTEMVIEW_ISR_EXIT() #endif +#if (dg_configUART1_SOFTWARE_FIFO_SIZE && dg_configUART_SOFTWARE_FIFO) +#if dg_configUART_RX_CIRCULAR_DMA && (dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE > 0) +#error UART1 can not be configured to use software FIFO and circular DMA FIFO at the same time +#endif +__RETAINED static uint8_t uart1_sw_fifo[dg_configUART1_SOFTWARE_FIFO_SIZE]; +#else +#define uart1_sw_fifo (NULL) +#endif + +#if (dg_configUART2_SOFTWARE_FIFO_SIZE && dg_configUART_SOFTWARE_FIFO) +#if dg_configUART_RX_CIRCULAR_DMA && (dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE > 0) +#error UART2 can not be configured to use software FIFO and circular DMA FIFO at the same time +#endif +__RETAINED static uint8_t uart2_sw_fifo[dg_configUART2_SOFTWARE_FIFO_SIZE]; +#else +#define uart2_sw_fifo (NULL) +#endif + +#if dg_configUART1_SOFTWARE_FIFO_SIZE > 255 || dg_configUART2_SOFTWARE_FIFO_SIZE > 255 +typedef uint16_t fifo_size_t; +#else +typedef uint8_t fifo_size_t; +#endif + +#if dg_configUART1_SOFTWARE_FIFO_SIZE > 256 || dg_configUART2_SOFTWARE_FIFO_SIZE > 256 +typedef uint16_t fifo_ptr_t; +#else +typedef uint8_t fifo_ptr_t; +#endif + +#if dg_configUART_RX_CIRCULAR_DMA + +#if !HW_UART_USE_DMA_SUPPORT +# error "dg_configUART_RX_CIRCULAR_DMA requires HW_UART_USE_DMA_SUPPORT to be enabled!" +#endif + +#if dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE > 0 +__RETAINED static uint8_t uart1_rx_dma_buf[dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE]; +#else +#define uart1_rx_dma_buf (NULL) +#endif + +#if dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE > 0 +__RETAINED static uint8_t uart2_rx_dma_buf[dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE]; +#else +#define uart2_rx_dma_buf (NULL) +#endif + +#endif /* dg_configUART_RX_CIRCULAR_DMA */ + typedef struct { #ifdef HW_UART_ENABLE_USER_ISR @@ -79,18 +130,24 @@ typedef struct uint8_t rx_fifo_level: 2; #if dg_configUART_SOFTWARE_FIFO uint8_t *rx_soft_fifo; - uint8_t rx_soft_fifo_size; - uint8_t rx_soft_fifo_rd_ptr; - uint8_t rx_soft_fifo_wr_ptr; + fifo_size_t rx_soft_fifo_size; + fifo_ptr_t rx_soft_fifo_rd_ptr; + fifo_ptr_t rx_soft_fifo_wr_ptr; #endif #if HW_UART_USE_DMA_SUPPORT uint8_t use_dma: 1; DMA_setup tx_dma; DMA_setup rx_dma; -#endif +#if dg_configUART_RX_CIRCULAR_DMA + bool rx_dma_active; + uint8_t *rx_dma_buf; + uint16_t rx_dma_buf_size; + uint16_t rx_dma_head; +#endif /* dg_configUART_RX_CIRCULAR_DMA */ +#endif /* HW_UART_USE_DMA_SUPPORT */ } UART_Data; -static UART_Data uart_data[2]; +__RETAINED_RW static UART_Data uart_data[2]; #define UART_INT(id) ((id) == HW_UART1 ? (UART_IRQn) : (UART2_IRQn)) #define UARTIX(id) ((id) == HW_UART1 ? 0 : 1) @@ -189,44 +246,124 @@ static inline void hw_uart_enable_rx_int(HW_UART_ID uart, bool enable) #define SOFTWARE_FIFO_PRESENT(ud) ((ud)->rx_soft_fifo != NULL) +/* + * Copy bytes from software FIFO to user provided buffer. + * This function allows software FIFO interrupts to read more data while copy takes place. + * + * Function returns true if all requested data is already in user buffer. + */ +static bool hw_uart_drain_rx(HW_UART_ID uart, UART_Data *ud, int len) +{ + /* + * This function is called with RX interrupt disabled. + * + * Get current software FIFO pointers before enabling interrupt again. + * ud->rx_len is still set to 0, so interrupt will not try to copy data to + * application buffer till all data from software FIFO is drained to user buffer. + */ + fifo_ptr_t rd_ptr = ud->rx_soft_fifo_rd_ptr; + fifo_ptr_t wr_ptr = ud->rx_soft_fifo_wr_ptr; + int idx = 0; + + /* + * ud->rx_ix is 0, set ud->rx_len to 0 to prevent interrupt from using it + * before all data from software FIFO is moved to application buffer. + */ + ud->rx_len = 0; + + hw_uart_enable_rx_int(uart, true); + + while (idx < len) + { + + if (wr_ptr == rd_ptr) + { + /* + * No more data in software FIFO, at least from state before + * interrupt was enabled. + * Disable interrupt and update read pointer to reflect position + * of already copied data. + */ + hw_uart_enable_rx_int(uart, false); + ud->rx_soft_fifo_rd_ptr = rd_ptr; + + /* + * Check if write pointer moved, if so interrupt put some more data + * in buffer. Remember current write position and try again with + * interrupts enabled. + */ + if (ud->rx_soft_fifo_wr_ptr != wr_ptr) + { + wr_ptr = ud->rx_soft_fifo_wr_ptr; + hw_uart_enable_rx_int(uart, true); + continue; + } + + /* + * All was copied from software FIFO. + * Setup user transaction ix and len so when interrupts are enabled + * again (not in this function) interrupt or DMA can continue. + */ + ud->rx_ix = idx; + ud->rx_len = len; + + return false; + } + + /* Copy from software FIFO to user provided buffer */ + ud->rx_buffer[idx++] = ud->rx_soft_fifo[rd_ptr++]; + + if (rd_ptr >= ud->rx_soft_fifo_size) + { + rd_ptr = 0; + } + } + + /* + * User buffer is filled, block interrupt so end of transmission callback will not be + * called from interrupt. + */ + hw_uart_enable_rx_int(uart, false); + ud->rx_soft_fifo_rd_ptr = rd_ptr; + ud->rx_len = len; + ud->rx_ix = len; + + return true; +} + void hw_uart_read_buffer(HW_UART_ID uart, void *data, uint16_t len) { UART_Data *ud = UARTDATA(uart); uint8_t *p = data; + /* + * Disable RX interrupt before draining software FIFO. + */ hw_uart_enable_rx_int(uart, false); + if (SOFTWARE_FIFO_PRESENT(ud)) + { + /* + * Drain uses ud fields so setup them accordingly. + */ + ud->rx_buffer = data; + + hw_uart_drain_rx(uart, ud, len); + len -= ud->rx_ix; + p += ud->rx_ix; + } + + /* + * Read all remaining bytes with RX interrupt still disabled. + */ while (len > 0) { - uint8_t rd_ptr = ud->rx_soft_fifo_rd_ptr; - - /* - * rd_ptr != rx_soft_fifo_wr_ptr --> data is in software FIFO - * rd_ptr == rx_soft_fifo_wr_ptr --> nothing in software FIFO, or software FIFO - * is not in use - */ - if (rd_ptr != ud->rx_soft_fifo_wr_ptr) - { - *p++ = ud->rx_soft_fifo[rd_ptr++]; - - if (rd_ptr >= ud->rx_soft_fifo_size) - { - ud->rx_soft_fifo_rd_ptr = 0; - } - else - { - ud->rx_soft_fifo_rd_ptr = rd_ptr; - } - } - else - { - /* Software FIFO drained or no software FIFO, just read from hardware */ - *p++ = hw_uart_read(uart); - } - + *p++ = hw_uart_read(uart); len--; } + ud->rx_ix = 0; + ud->rx_len = 0; hw_uart_enable_rx_int(uart, SOFTWARE_FIFO_PRESENT(ud)); } @@ -244,32 +381,6 @@ void hw_uart_set_soft_fifo(HW_UART_ID uart, uint8_t *buf, uint8_t size) hw_uart_enable_rx_int(uart, buf != NULL); } -static bool hw_uart_drain_rx(UART_Data *ud) -{ - while (ud->rx_ix < ud->rx_len) - { - uint8_t rd_ptr = ud->rx_soft_fifo_rd_ptr; - - if (rd_ptr == ud->rx_soft_fifo_wr_ptr) - { - return false; - } - - ud->rx_buffer[ud->rx_ix++] = ud->rx_soft_fifo[rd_ptr++]; - - if (rd_ptr >= ud->rx_soft_fifo_size) - { - ud->rx_soft_fifo_rd_ptr = 0; - } - else - { - ud->rx_soft_fifo_rd_ptr = rd_ptr; - } - } - - return true; -} - #else #define SOFTWARE_FIFO_PRESENT(ud) false @@ -295,7 +406,7 @@ static void hw_uart_fire_callback(UART_Data *ud) if (cb) { - cb(ud->rx_user_data, ud->rx_ix); + cb(ud->rx_user_data, ud->rx_len); } } @@ -320,7 +431,7 @@ void hw_uart_receive(HW_UART_ID uart, void *data, uint16_t len, hw_uart_rx_callb ud->rx_cb = cb; #if dg_configUART_SOFTWARE_FIFO - if (hw_uart_drain_rx(ud)) + if (hw_uart_drain_rx(uart, ud, len)) { hw_uart_fire_callback(ud); return; @@ -328,6 +439,61 @@ void hw_uart_receive(HW_UART_ID uart, void *data, uint16_t len, hw_uart_rx_callb #endif +#if dg_configUART_RX_CIRCULAR_DMA + + if (ud->rx_dma_buf_size > 0) + { + ASSERT_ERROR(len < ud->rx_dma_buf_size); + + uint16_t new_int, cur_idx; + bool data_ready = false; + + ASSERT_ERROR(ud->rx_dma_active == false); + + /* Calculate index of end of requested data (do not wrap it!) */ + new_int = ud->rx_dma_head + ud->rx_len - 1; + + /* Freeze DMA so it does not move pointers while we try to update them */ + hw_dma_freeze(); + + cur_idx = hw_dma_transfered_bytes(ud->rx_dma.channel_number); + + /* cur_idx is lower than rx_head only if it wrapped-around - fix it */ + if (cur_idx < ud->rx_dma_head) + { + cur_idx += ud->rx_dma_buf_size; + } + + /* + * If DMA has not read past the calculated index, we can set it and just wait for an + * interrupt. In other case, data are ready immediately in buffer. + */ + if (cur_idx <= new_int) + { + new_int %= ud->rx_dma_buf_size; + hw_dma_channel_update_int_ix(ud->rx_dma.channel_number, new_int); + ud->rx_dma_active = true; + } + else + { + hw_dma_channel_update_int_ix(ud->rx_dma.channel_number, cur_idx - 1); + data_ready = true; + } + + /* Unfreeze DMA now, it can start reading */ + hw_dma_unfreeze(); + + /* Fire callback immediately if data already available in buffer */ + if (data_ready) + { + hw_uart_fire_callback(ud); + } + + return; + } + +#endif + #if HW_UART_USE_DMA_SUPPORT if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID && (ud->rx_len - ud->rx_ix > 1)) @@ -354,10 +520,67 @@ static void hw_uart_irq_stop_receive(HW_UART_ID uart) // Disable RX interrupt hw_uart_enable_rx_int(uart, false); + ud->rx_len = ud->rx_ix; + hw_uart_fire_callback(ud); } -void hw_uart_abort_receive(HW_UART_ID uart) +#if dg_configUART_RX_CIRCULAR_DMA +static void hw_uart_copy_dma_rx_to_user_buffer(HW_UART_ID uart) +{ + UART_Data *ud = &uart_data[UARTIX(uart)]; + + uint16_t cur_idx; + uint16_t to_copy; + hw_uart_rx_callback cb; + + ud->rx_dma_active = false; + cb = ud->rx_cb; + + if (cb) + { + ud->rx_cb = NULL; + /* + * User callback was not fired, since rx_dma_active is false it will not + * fire even if requested number of bytes was received when abort was initiated. + */ + cur_idx = hw_dma_transfered_bytes(ud->rx_dma.channel_number); + + if (ud->rx_ix < ud->rx_len) + { + if (cur_idx < ud->rx_dma_head) + { + cur_idx += ud->rx_dma_buf_size; + } + + to_copy = cur_idx - ud->rx_dma_head; + + if (to_copy >= ud->rx_len - ud->rx_ix) + { + to_copy = ud->rx_len - ud->rx_ix; + } + } + } + else + { + /* + * Callback already fired, circular buffer holds enough data. + */ + to_copy = ud->rx_len - ud->rx_ix; + } + + hw_uart_copy_rx_circular_dma_buffer(uart, ud->rx_buffer + ud->rx_ix, to_copy); + ud->rx_ix += to_copy; + ud->rx_len = ud->rx_ix; + + if (cb) + { + cb(ud->rx_user_data, ud->rx_len); + } +} +#endif + +uint16_t hw_uart_abort_receive(HW_UART_ID uart) { UART_Data *ud = &uart_data[UARTIX(uart)]; @@ -365,11 +588,24 @@ void hw_uart_abort_receive(HW_UART_ID uart) if (ud->rx_dma.channel_number != HW_DMA_CHANNEL_INVALID) { +#if dg_configUART_RX_CIRCULAR_DMA + + if (ud->rx_dma_buf_size > 0) + { + hw_uart_copy_dma_rx_to_user_buffer(uart); + return ud->rx_ix; + } + +#else + /* No DMA circular buffer, stop DMA */ hw_dma_channel_stop(ud->rx_dma.channel_number); +#endif } else #endif hw_uart_irq_stop_receive(uart); + + return ud->rx_ix; } uint16_t hw_uart_peek_received(HW_UART_ID uart) @@ -428,35 +664,17 @@ static inline void hw_uart_tx_isr(HW_UART_ID uart) } } - -void (*hw_uart_simple_rx_callback)(void) = NULL; - -void hw_uart_register_simple_rx_callback(void (*callback)(void), HW_UART_ID uart) -{ - - hw_uart_simple_rx_callback = callback; - hw_uart_enable_rx_int(uart, 1); -} - - static inline void hw_uart_rx_isr(HW_UART_ID uart) { UART_Data *ud = UARTDATA(uart); - if (hw_uart_simple_rx_callback != NULL) - { - //Simple callback defined - hw_uart_simple_rx_callback(); - return; - } - if (SOFTWARE_FIFO_PRESENT(ud)) { #if dg_configUART_SOFTWARE_FIFO for (;;) { - uint8_t wr_ptr = ud->rx_soft_fifo_wr_ptr + 1; + fifo_ptr_t wr_ptr = ud->rx_soft_fifo_wr_ptr + 1; if (wr_ptr >= ud->rx_soft_fifo_size) { @@ -476,9 +694,23 @@ static inline void hw_uart_rx_isr(HW_UART_ID uart) } ud->rx_soft_fifo[ud->rx_soft_fifo_wr_ptr] = hw_uart_rxdata_getf(uart); - ud->rx_soft_fifo_wr_ptr = wr_ptr; - hw_uart_drain_rx(ud); + /* + * Application read is in progress. Copy data from software FIFO to + * user provided buffer. + */ + if (ud->rx_ix < ud->rx_len) + { + ud->rx_buffer[ud->rx_ix++] = ud->rx_soft_fifo[ud->rx_soft_fifo_wr_ptr]; + /* + * When application read is in progress, rx_ix < rx_len + * This interrupt is enabled only if all data was already copied from + * FIFO to user buffer. It is safe to modify rx_soft_fifo_rd_ptr. + */ + ud->rx_soft_fifo_rd_ptr = wr_ptr; + } + + ud->rx_soft_fifo_wr_ptr = wr_ptr; } #endif @@ -499,11 +731,12 @@ static inline void hw_uart_rx_isr(HW_UART_ID uart) } // Everything read? - if (ud->rx_ix >= ud->rx_len) + if (ud->rx_len > 0 && ud->rx_ix >= ud->rx_len) { // Disable RX interrupts, fire callback if present hw_uart_irq_stop_receive(uart); } + } static inline void hw_uart_rx_timeout_isr(HW_UART_ID uart) @@ -677,6 +910,7 @@ uint8_t hw_uart_fifo_en_getf(HW_UART_ID uart) default: ASSERT_ERROR(0); + return 255; // To satisfy the compiler } } @@ -703,6 +937,7 @@ static void hw_uart_rx_dma_callback(void *user_data, uint16_t len) if (cb) { + ud->rx_len = ud->rx_ix; hw_uart_enable_rx_int(UARTID(ud), SOFTWARE_FIFO_PRESENT(ud)); cb(ud->rx_user_data, ud->rx_ix); } @@ -861,7 +1096,78 @@ void hw_uart_set_dma_channels_ex(HW_UART_ID uart, int8_t tx_channel, int8_t rx_c ud->tx_dma.user_data = ud; } } -#endif + +#if dg_configUART_RX_CIRCULAR_DMA + +static void hw_uart_rx_circular_dma_callback(void *user_data, uint16_t len) +{ + UART_Data *ud = user_data; + hw_uart_rx_callback cb = ud->rx_cb; + + if (!ud->rx_dma_active) + { + return; + } + + ud->rx_cb = NULL; + ud->rx_dma_active = false; + + if (cb) + { + cb(ud->rx_user_data, ud->rx_len); + } +} + +void hw_uart_enable_rx_circular_dma(HW_UART_ID uart) +{ + UART_Data *ud = UARTDATA(uart); + + ASSERT_ERROR(ud->rx_dma_buf_size > 0); + + hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_DISABLED); + + /* Need to reconfigure few things for circular operation... */ + ud->rx_dma.circular = HW_DMA_MODE_CIRCULAR; + ud->rx_dma.dest_address = (uint32_t) ud->rx_dma_buf; + ud->rx_dma.length = ud->rx_dma_buf_size; + ud->rx_dma.callback = hw_uart_rx_circular_dma_callback; + ud->rx_dma.user_data = ud; + + /* Reset DMA buffer read pointer */ + ud->rx_dma_head = 0; + + /* Start DMA now since it should be always-running */ + hw_uart_clear_dma_request(uart); + hw_dma_channel_initialization(&ud->rx_dma); + hw_dma_channel_enable(ud->rx_dma.channel_number, HW_DMA_STATE_ENABLED); +} + +void hw_uart_copy_rx_circular_dma_buffer(HW_UART_ID uart, uint8_t *buf, uint16_t len) +{ + UART_Data *ud = UARTDATA(uart); + + ASSERT_ERROR(len < ud->rx_dma_buf_size); + + if (ud->rx_dma_head + len <= ud->rx_dma_buf_size) + { + memcpy(buf, &ud->rx_dma_buf[ud->rx_dma_head], len); + } + else + { + uint16_t chunk_len = ud->rx_dma_buf_size - ud->rx_dma_head; + memcpy(buf, &ud->rx_dma_buf[ud->rx_dma_head], chunk_len); + memcpy(buf + chunk_len, &ud->rx_dma_buf[0], len - chunk_len); + } + + /* This should be protected so ISR does not try to read rx_dma_head while we update it */ + GLOBAL_INT_DISABLE(); + ud->rx_dma_head = (ud->rx_dma_head + len) % ud->rx_dma_buf_size; + GLOBAL_INT_RESTORE(); +} + +#endif /* dg_configUART_RX_CIRCULAR_DMA */ + +#endif /* HW_UART_USE_DMA_SUPPORT */ //=========================== Line control functions ============================ void hw_uart_init_ex(HW_UART_ID uart, const uart_config_ex *uart_init) @@ -901,7 +1207,9 @@ void hw_uart_init_ex(HW_UART_ID uart, const uart_config_ex *uart_init) } } + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); + GLOBAL_INT_RESTORE(); // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); @@ -943,7 +1251,9 @@ void hw_uart_reinit_ex(HW_UART_ID uart, const uart_config_ex *uart_init) { UART_Data *ud = UARTDATA(uart); + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); + GLOBAL_INT_RESTORE(); /* * Read UART_USR_REG to clear any pending busy interrupt. @@ -1032,7 +1342,9 @@ void hw_uart_init(HW_UART_ID uart, const uart_config *uart_init) } } + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); + GLOBAL_INT_RESTORE(); // Set Divisor Latch Access Bit in LCR register to access DLL & DLH registers HW_UART_REG_SETF(uart, LCR, UART_DLAB, 1); @@ -1074,7 +1386,9 @@ void hw_uart_reinit(HW_UART_ID uart, const uart_config *uart_init) { UART_Data *ud = UARTDATA(uart); + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_PER, CLK_PER_REG, UART_ENABLE); + GLOBAL_INT_RESTORE(); /* * Read UART_USR_REG to clear any pending busy interrupt. diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c index 48fb0e157..5c764b3b6 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c @@ -38,6 +38,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ #include @@ -131,7 +132,7 @@ __RETAINED_CODE void hw_watchdog_handle_int(unsigned long *exception_args) if (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE)) { - __asm("BKPT #0\n"); + __BKPT(0); } else { diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_wkup.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_wkup.c old mode 100755 new mode 100644 index ef38939de..e009d6f46 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_wkup.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_wkup.c @@ -37,11 +37,12 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * **************************************************************************************** */ -#if dg_configUSE_HW_USB_WKUP +#if dg_configUSE_HW_WKUP #include @@ -50,22 +51,84 @@ static hw_wkup_interrupt_cb intr_cb __RETAINED /* = NULL*/; +#if ((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A)) +#define PX_DATA_REG_ADDR(_port) ((uint16_t *)(GPIO_BASE + offsetof(GPIO_Type, P0_DATA_REG)) + _port) +#define PX_DATA_REG(_port) *PX_DATA_REG_ADDR(_port) +#define BF_GET(_var, _pos) ((_var>>_pos) & 1) + +__RETAINED volatile wkup_pin_config_t wkup_pin_config; +volatile uint8_t wkup_status[HW_GPIO_NUM_PORTS]; + +static bool hw_wkup_update_status(void) +{ + uint8_t i, j, enable_loop_cnt = 0; + uint8_t pol_rx_reg; + bool wkup_status_updated = false; + uint8_t cur_port_data[HW_GPIO_NUM_PORTS]; + + for (i = 0; i < HW_GPIO_NUM_PORTS; i++) { + wkup_status[i] = 0; + if (wkup_pin_config.pin_state[i]) { + //read port status + cur_port_data[i] = PX_DATA_REG(i); + //read trigger polarity + pol_rx_reg = *((volatile uint16_t *)WAKEUP_BASE + 10 + i); + for (j = 0; j < 8; j++) { + if ((wkup_pin_config.pin_state[i] & (1 << j)) && + (BF_GET(pol_rx_reg, j) + == BF_GET(~cur_port_data[i], j))) { + //invert trigger polarity + pol_rx_reg ^= (1 << j); + if (BF_GET(wkup_pin_config.pin_trigger[i], j) + == BF_GET(~cur_port_data[i], j)) { + wkup_status[i] |= (1 << j); + wkup_status_updated = true; + } + } + } + //update trigger polarity + *((volatile uint16_t *)WAKEUP_BASE + 10 + i) = pol_rx_reg; + } + } + + return wkup_status_updated; +} +#endif /* dg_configLATCH_WKUP_SOURCE */ + void hw_wkup_init(const wkup_config *cfg) { unsigned int i; + GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, CLK_TMR_REG, WAKEUPCT_ENABLE); + GLOBAL_INT_RESTORE(); /* reset configuration */ WAKEUP->WKUP_CTRL_REG = 0; + +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A WAKEUP->WKUP_COMPARE_REG = 0; +#endif /* disable all pins */ - for (i = 0; i < 5; i++) { - *((volatile uint16_t *)WAKEUP_BASE + 5 + i) = 0; - *((volatile uint16_t *)WAKEUP_BASE + 10 + i) = 0; + for (i = 0; i < HW_GPIO_NUM_PORTS; i++) { + *((volatile uint16_t *)(&WAKEUP->WKUP_POL_P0_REG) + i) = 0; + *((volatile uint16_t *)(&WAKEUP->WKUP_SELECT_P0_REG) + i) = 0; +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A + *((volatile uint16_t *)(&WAKEUP-> WKUP_SEL_GPIO_P0_REG) + i) = 0; +#endif +#if dg_configLATCH_WKUP_SOURCE +#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A) + wkup_pin_config.pin_state[i] = 0; + wkup_pin_config.pin_trigger[i] = 0; + wkup_status[i] = 0; + hw_wkup_clear_status(i, 0xFF); +#endif +#endif //dg_configLATCH_WKUP_SOURCE } - +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A + WAKEUP->WKUP_CLEAR_0_REG = WAKEUP->WKUP_CLEAR_1_REG = WAKEUP->WKUP_CLEAR_2_REG = 0xFFFF; +#endif NVIC_DisableIRQ(WKUP_GPIO_IRQn); hw_wkup_configure(cfg); @@ -79,9 +142,12 @@ void hw_wkup_configure(const wkup_config *cfg) return; } +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A hw_wkup_set_counter_threshold(cfg->threshold); +#endif +#if !((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) hw_wkup_set_debounce_time(cfg->debounce); - +#endif for (i = 0; i < HW_GPIO_NUM_PORTS; i++) { hw_wkup_configure_port(i, cfg->pin_state[i], cfg->pin_trigger[i]); } @@ -90,9 +156,9 @@ void hw_wkup_configure(const wkup_config *cfg) void hw_wkup_register_interrupt(hw_wkup_interrupt_cb cb, uint32_t prio) { intr_cb = cb; - +#if !((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) HW_WKUP_REG_SETF(CTRL, WKUP_ENABLE_IRQ, 1); - +#endif NVIC_ClearPendingIRQ(WKUP_GPIO_IRQn); NVIC_SetPriority(WKUP_GPIO_IRQn, prio); NVIC_EnableIRQ(WKUP_GPIO_IRQn); @@ -101,18 +167,30 @@ void hw_wkup_register_interrupt(hw_wkup_interrupt_cb cb, uint32_t prio) void hw_wkup_unregister_interrupt(void) { intr_cb = NULL; - +#if !((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A)) HW_WKUP_REG_SETF(CTRL, WKUP_ENABLE_IRQ, 0); - +#endif NVIC_DisableIRQ(WKUP_GPIO_IRQn); } void hw_wkup_handler(void) { +#if ((dg_configLATCH_WKUP_SOURCE) && (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A)) + if (intr_cb && hw_wkup_update_status()) { +#else if (intr_cb) { +#endif intr_cb(); - } else { + } + else { hw_wkup_reset_interrupt(); +#if dg_configLATCH_WKUP_SOURCE + hw_wkup_clear_status(HW_GPIO_PORT_0, 0xFF); + hw_wkup_clear_status(HW_GPIO_PORT_1, 0xFF); + hw_wkup_clear_status(HW_GPIO_PORT_2, 0xFF); + hw_wkup_clear_status(HW_GPIO_PORT_3, 0xFF); + hw_wkup_clear_status(HW_GPIO_PORT_4, 0xFF); +#endif } } @@ -123,7 +201,7 @@ void WKUP_GPIO_Handler(void) } #endif -#endif /* dg_configUSE_HW_USB_WKUP */ +#endif /* dg_configUSE_HW_WKUP */ /** * \} * \} diff --git a/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c b/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c index 891c4f0cb..5b2de0bfb 100644 --- a/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c +++ b/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c @@ -9,11 +9,11 @@ /** **************************************************************************************** -* -* @file sys_tcs.c -* -* @brief TCS HAndler -* + * + * @file sys_tcs.c + * + * @brief TCS HAndler + * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -38,11 +38,15 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ #include +#include "hw_cpm.h" #include "sys_tcs.h" +#include "hw_gpadc.h" +#include "hw_gpio.h" #define APPEND_TCS_LENGTH (0) @@ -51,6 +55,9 @@ #define IS_IN_AREA(addr, base, size) ((addr >= base) && (addr <= (base + size))) +#define ADC_SE_GAIN_ERROR(value) ((value) & 0x0000FFFF) +#define ADC_DIFF_GAIN_ERROR(value) (((value) & 0xFFFF0000) >> 16) + /* * Global and / or retained variables */ @@ -60,10 +67,12 @@ uint8_t tcs_length __RETAINED_UNINIT; uint8_t area_offset[tcs_system + 1] __RETAINED; uint8_t area_size_global[tcs_system + 1] __RETAINED; +uint16_t sys_tcs_xtal16m_settling_time __RETAINED; + const uint32_t *tcs_ptr __RETAINED; -bool is_calibrated_chip __RETAINED_UNINIT; // Initial value: false +bool sys_tcs_is_calibrated_chip __RETAINED_UNINIT; // Initial value: false /* * Local variables @@ -251,13 +260,13 @@ static void swap_entries(uint32_t first_pos, uint32_t second_pos) */ static int sys_tcs_sort_area(uint32_t area_base, uint32_t area_size, uint32_t array_ptr, uint8_t *ptr, uint8_t *size) { - int i = array_ptr; - int sort_start; - int sort_end; + uint32_t i = array_ptr; + uint32_t sort_start; + uint32_t sort_end; if (array_ptr == tcs_length) { - return array_ptr; // Nothing else is left in the array + return array_ptr; // Nothing else is left in the array or tcs_length is zero } sort_start = array_ptr; @@ -266,7 +275,7 @@ static int sys_tcs_sort_area(uint32_t area_base, uint32_t area_size, uint32_t ar /* Make sure that the values in TCS don't overflow the allocated array */ ASSERT_WARNING(tcs_length <= sizeof(tcs_data) / sizeof(tcs_data[0])); - while (i < tcs_length) + while (i < (tcs_length - 1)) { if (IS_IN_AREA(tcs_data[i], area_base, area_size)) { @@ -302,7 +311,8 @@ static int sys_tcs_sort_area(uint32_t area_base, uint32_t area_size, uint32_t ar void sys_tcs_init(void) { tcs_length = 0; - is_calibrated_chip = false; + sys_tcs_is_calibrated_chip = false; + hw_cpm_bod_enabled_in_tcs = 0; } bool sys_tcs_store_pair(uint32_t address, uint32_t value) @@ -321,12 +331,35 @@ bool sys_tcs_store_pair(uint32_t address, uint32_t value) { if (address == (uint32_t)&CRG_TOP->BANDGAP_REG) { - is_calibrated_chip = true; + sys_tcs_is_calibrated_chip = true; } - - if (address == (uint32_t)&CRG_TOP->CLK_16M_REG) + else if (address == (uint32_t)&CRG_TOP->CLK_16M_REG) { - value |= 1; // Make sure that RC16 is enabled! + value |= CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk; // Make sure that RC16 is enabled! + } + else if (address == (uint32_t)&CRG_TOP->XTALRDY_CTRL_REG) + { + sys_tcs_xtal16m_settling_time = value; + } + else if (address == (uint32_t)&CRG_TOP->BOD_CTRL2_REG) + { + hw_cpm_bod_enabled_in_tcs = value; + /* + * Read the ADC Gain Error. Given that the Chip Configuration Section + * (CCS) of OTP is out of space, the values are stored in the TCS section + * using as address the read-only register SYS_STAT_REG. + * The 16 LSB of the 32bit data-value is the single ended gain error. + * The 16 MSB of the 32bit data-value is the differential gain error. + * Both gain error values should be interpreted as signed 16bit integers. + */ + } + else if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) + { + if (address == (uint32_t)&CRG_TOP->SYS_STAT_REG) + { + hw_gpadc_store_se_gain_error(ADC_SE_GAIN_ERROR(value)); + hw_gpadc_store_diff_gain_error(ADC_DIFF_GAIN_ERROR(value)); + } } apply_pair(address, value); @@ -336,7 +369,7 @@ bool sys_tcs_store_pair(uint32_t address, uint32_t value) store_in_array(address, value); } - return is_calibrated_chip; + return sys_tcs_is_calibrated_chip; } void sys_tcs_sort_array(void) @@ -354,7 +387,7 @@ void sys_tcs_sort_array(void) CRG_TOP->CLK_FREQ_TRIM_REG = 0x0460; } - if (is_calibrated_chip) + if (sys_tcs_is_calibrated_chip) { #ifdef CONFIG_USE_BLE entry_ptr = sys_tcs_sort_area(BLE_BASE, sizeof(BLE_Type), entry_ptr, diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h old mode 100755 new mode 100644 index 87dec2505..777c87cb0 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h @@ -1,8 +1,6 @@ /** \addtogroup INTERFACES \{ - \addtogroup RADIO - \{ \addtogroup FTDF \{ */ @@ -37,6 +35,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h old mode 100755 new mode 100644 index 30b90a500..d096c6956 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h @@ -1,8 +1,6 @@ /** \addtogroup INTERFACES \{ - \addtogroup RADIO - \{ \addtogroup FTDF \{ */ @@ -36,7 +34,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * **************************************************************************************** */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h old mode 100755 new mode 100644 index 64b485053..8398c6ace --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h @@ -1,10 +1,9 @@ /** \addtogroup INTERFACES \{ - \addtogroup RADIO - \{ \addtogroup FTDF \{ + \brief IEEE 802.15.4 Wireless */ /** **************************************************************************************** @@ -36,7 +35,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * **************************************************************************************** */ @@ -164,7 +164,9 @@ typedef uint8_t FTDF_MsgId; #if FTDF_DBG_BUS_ENABLE #define FTDF_DBG_MODE_SET_REQUEST 54 #endif /* FTDF_DBG_BUS_ENABLE */ - +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +#define FTDF_FPPR_MODE_SET_REQUEST 55 +#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ /** * \brief Request status * \remark Valid statuses: @@ -369,6 +371,8 @@ typedef uint64_t FTDF_PSec; typedef uint32_t FTDF_NrLowPowerClockCycles; +typedef uint8_t FTDF_NrBackoffPeriods; + /** * \brief Period of time * \remark Range 0..65535 @@ -651,8 +655,23 @@ typedef uint8_t FTDF_PIBAttribute; #define FTDF_PIB_TSCH_CAPABLE 103 #define FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD 104 +/* Proprietary PIB. */ +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +#define FTDF_PIB_BO_IRQ_THRESHOLD 105 +#define FTDF_PIB_PTI_CONFIG 106 +#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ + // Total number of PIB attributes -#define FTDF_NR_OF_PIB_ATTRIBUTES 104 +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +#define FTDF_NR_OF_PIB_ATTRIBUTES 106 +#else /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ +#define FTDF_NR_OF_PIB_ATTRIBUTES 104 +#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ + +/* Default values */ +#ifndef FTDF_BO_IRQ_THRESHOLD +#define FTDF_BO_IRQ_THRESHOLD 0xff +#endif #if FTDF_DBG_BUS_ENABLE /** @@ -1247,6 +1266,27 @@ typedef uint8_t FTDF_ChannelNumber; */ typedef uint8_t FTDF_PTI; +enum +{ + /* PTI index for explicit Rx. */ + FTDF_PTI_CONFIG_RX, + /* PTI index for Tx. */ + FTDF_PTI_CONFIG_TX, + FTDF_PTI_CONFIG_RESERVED0, + FTDF_PTI_CONFIG_RESERVED1, + FTDF_PTI_CONFIG_RESERVED2, + FTDF_PTI_CONFIG_RESERVED3, + FTDF_PTI_CONFIG_RESERVED4, + FTDF_PTI_CONFIG_RESERVED5, + /* Enumeration end. */ + FTDF_PTIS, +}; + +typedef struct +{ + FTDF_PTI ptis[FTDF_PTIS]; +} FTDF_PtiConfig; + /** * \brief Channel page * \remark Supported values: 0 @@ -1440,6 +1480,8 @@ typedef struct FTDF_Count duplicateFrameCount; FTDF_Count RXSuccessCount; FTDF_Count NACKCount; + FTDF_Count RxExpiredCount; + FTDF_Count BOIrqCount; } FTDF_PerformanceMetrics; typedef struct @@ -2703,6 +2745,19 @@ typedef struct } FTDF_DbgModeSetRequest; #endif /* FTDF_DBG_BUS_ENABLE */ +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +typedef struct +{ + /** \brief Message ID = FTDF_FPPR_MODE_SET_REQUEST */ + FTDF_MsgId msgId; + /** \brief fp bit value to set when src address matches*/ + FTDF_Bitmap8 matchFp; + /** \brief When set, fp_force_value will be applied to fp bit for all src addresses*/ + FTDF_Bitmap8 fpOverride; + /** \brief The value will be set to fp bit for all src addresses when fp_override is set*/ + FTDF_Bitmap8 fpForce; +} FTDF_FpprModeSetRequest; +#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ /** * \brief FTDF_getReleaseInfo - gets the LMAC (FPGA) and UMAC (FTDF SW driver) release info * \param[out] lmacRelName: LMAC release name @@ -3062,7 +3117,13 @@ void FTDF_reset(int setDefaultPIB); FTDF_PTI FTDF_getRxPti( void ); +#if FTDF_USE_PTI void FTDF_setRxPti( FTDF_PTI rx_pti ); +#if FTDF_USE_AUTO_PTI +void FTDF_restoreRxPti(void); +#endif +#endif + #ifdef FTDF_PHY_API FTDF_Status FTDF_sendFrameSimple( FTDF_DataLength frameLength, FTDF_Octet* frame, @@ -3092,6 +3153,274 @@ void FTDF_setDbgMode(FTDF_DbgMode dbgMode); void FTDF_DBG_BUS_GPIO_CONFIG(void); #endif /* FTDF_DBG_BUS_ENABLE */ +#if dg_configUSE_FTDF_DDPHY == 1 +void FTDF_ddphySet(uint16_t ccaReg); +#endif /* dg_configUSE_FTDF_DDPHY == 1 */ + +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A + +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO +#ifndef FTDF_LITE +/** + * \brief Controls when the FPPR address invalidation will be performed. + * + * If set to 0 (recommended), address invalidation in FPPR occurs right after the frame is passed to + * LMAC for direct transmission. If set to 1, address invalidation occurs after the associated + * confirm message is received. + */ +#define FTDF_FPPR_DEFER_INVALIDATION 0 + +/** + * \brief Adds a new short address to FPPR, initializing the corresponding FSM. + * + * A short address FP FSM accepts the following notifications (events): + * + * - New address (initialize) by calling @ref FTDF_fpFsmShortAddressNew() + * - Last frame pending (passed to direct sending) by calling @ref + * FTDF_fpFsmShortAddressLastFramePending() + * - Last pending frame sent by calling @ref FTDF_fpFsmClearPending() + * + * A new address may be rejected if there is no adequate space left in FPPR. + * + * \param [in] panId Destination PAN ID. + * \param [in] shortAddress Destination short address. + * + * \return \ref FTDF_TRUE on success. + */ +FTDF_Boolean FTDF_fpFsmShortAddressNew(FTDF_PANId panId, FTDF_ShortAddress shortAddress); + +/** + * \brief Adds a new extended address to FPPR, initializing the corresponding FSM. + * + * An extended address FP FSM accepts the following notifications (events): + * + * - New address (initialize) by calling @ref FTDF_fpFsmExtAddressNew() + * - Last frame pending (passed to direct sending) by calling @ref + * FTDF_fpFsmExtAddressLastFramePending() + * - Last pending frame sent by calling @ref FTDF_fpFsmClearPending() + * + * A new address may be rejected if there is no adequate space left in FPPR. + * + * \param [in] panId Destination PAN ID. + * \param [in] extAddress Destination extended address. + * + * \return \ref FTDF_TRUE on success. + */ +FTDF_Boolean FTDF_fpFsmExtAddressNew(FTDF_PANId panId, FTDF_ExtAddress extAddress); + +/** + * \brief Notifies FP FSM that the last packet for the associated destination has been passed for + * direct transmission. + * + * \param [in] panId Destination PAN ID. + * \param [in] shortAddress Destination short address. + */ +void FTDF_fpFsmShortAddressLastFramePending(FTDF_PANId panId, FTDF_ShortAddress shortAddress); + +/** + * \brief Notifies FP FSM that the last packet for the associated destination has been passed for + * direct transmission. + * + * \param [in] panId Destination PAN ID. + * \param [in] shortAddress Destination extended address. + */ +void FTDF_fpFsmExtAddressLastFramePending(FTDF_PANId panId, FTDF_ExtAddress extAddress); + +/** + * \brief Notifies FP FSM that the last pending packet has been transmitted (UMAC state machine + * closed). + */ +void FTDF_fpFsmClearPending(void); + +#endif /* #ifndef FTDF_LITE */ + +/** + * \brief Number of FPPR table entries. + */ +#define FTDF_FPPR_TABLE_ENTRIES 24 + +/** + * \brief Number of extended address table entries. + */ +#define FTDF_FPPR_TABLE_EXT_ADDRESS_ENTRIES FTDF_FPPR_TABLE_ENTRIES + +/** + * \brief Number of short address table entries. + */ +#define FTDF_FPPR_TABLE_SHORT_ADDRESS_ENTRIES (FTDF_FPPR_TABLE_ENTRIES * 4) + +/** + * \brief Resets FPPR table, invalidating all addresses. + */ +void FTDF_fpprReset(void); + +/** + * \brief Gets the short address programmed at the specified FPPR table position. + * + * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). + * \param [in] shortAddrIdx Short address position within the entry (0 to 3). + * + * \return Requested short address + */ +FTDF_ShortAddress FTDF_fpprGetShortAddress(uint8_t entry, uint8_t shortAddrIdx); + +/** + * \brief Programs a short address programmed at the specified FPPR table position. + * + * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). + * \param [in] shortAddrIdx Short address position within the entry (0 to 3). + * \param [in] Associated short address. + */ +void FTDF_fpprSetShortAddress(uint8_t entry, uint8_t shortAddrIdx, + FTDF_ShortAddress shortAddress); + +/** + * \brief Determines validity of a short address programmed at the specified FPPR table position. + * + * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). + * \param [in] shortAddrIdx Short address position within the entry (0 to 3). + * + * \return FTDF_TRUE if the address is valid. + */ +FTDF_Boolean FTDF_fpprGetShortAddressValid(uint8_t entry, uint8_t shortAddrIdx); + +/** + * \brief Sets validity of a short address programmed at the specified FPPR table position. + * + * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). + * \param [in] shortAddrIdx Short address position within the entry (0 to 3). + * \param [in] valid Associated validity. + */ +void FTDF_fpprSetShortAddressValid(uint8_t entry, uint8_t shortAddrIdx, + FTDF_Boolean valid); + +/** + * \brief Gets the extended address programmed at the specified FPPR table position. + * + * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). + * + * \return Requested extended address + */ +FTDF_ExtAddress FTDF_fpprGetExtAddress(uint8_t entry); + +/** + * \brief Programs an extended address programmed at the specified FPPR table position. + * + * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). + * \param [in] Associated extended address. + */ +void FTDF_fpprSetExtAddress(uint8_t entry, FTDF_ExtAddress extAddress); + +/** + * \brief Determines validity of an extended address programmed at the specified FPPR table + * position. + * + * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). + * + * \return \ref FTDF_TRUE if the address is valid. + */ +FTDF_Boolean FTDF_fpprGetExtAddressValid(uint8_t entry); + +/** + * \brief Sets validity of an extended address programmed at the specified FPPR table position. + * + * \param [in] entry FPPR table entry (0 to \ref FTDF_FPPR_TABLE_ENTRIES - 1). + * \param [in] valid Associated validity. + */ +void FTDF_fpprSetExtAddressValid(uint8_t entry, FTDF_Boolean valid); + +/** + * \brief Gets a free (invalid) short address position in the FPPR table. + * + * \param [out] entry Reference to the FPPR table entry. + * \param [out] shortAddrIdx Reference to the short address position within the entry. + * + * \return \ref FTDF_TRUE if a free position was found. + */ +FTDF_Boolean FTDF_fpprGetFreeShortAddress(uint8_t * entry, + uint8_t * shortAddrIdx); + +/** + * \brief Gets a free (invalid) extended address position in the FPPR table. + * + * \param [out] entry Reference to the FPPR table entry. + * + * \return \ref FTDF_TRUE if a free position was found. + */ +FTDF_Boolean FTDF_fpprGetFreeExtAddress(uint8_t * entry); + +/** + * \brief Looks up a short address within the FPPR table. + * + * \param [in] shortAddr Associated short address. + * \param [out] entry Reference to the FPPR table entry. + * \param [out] shortAddrIdx Reference to the short address position within the entry. + * + * * \return \ref FTDF_TRUE if the address was found. + */ +FTDF_Boolean FTDF_fpprLookupShortAddress(FTDF_ShortAddress shortAddr, uint8_t * entry, + uint8_t * shortAddrIdx); + +/** + * \brief Looks up an extended address within the FPPR table. + * + * \param [in] extAddr Associated extended address. + * \param [out] entry Reference to the FPPR table entry. + * + * * \return \ref FTDF_TRUE if the address was found. + */ +FTDF_Boolean FTDF_fpprLookupExtAddress(FTDF_ExtAddress extAddr, uint8_t * entry); + +#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ + +/** + * \brief Sets FPPR mode. + * + * \param [in] matchFp Specifies the value of the FP bit when acknowledging a received frame with a + * source address that matches a valid a address in the FPPR table. The opposite value is set if the + * source address does not match. Ignored if \a fpOverride is \ref FTDF_TRUE. + * + * \param [in] fpOverride If \ref FTDF_TRUE, the value of \a fpForce is used for setting the FP bit, + * regardless of the address table matching result. + * + * \param [in] fpForce FP bit value when fpOverride is \ref FTDF_TRUE. Ignored otherwise. + */ +void FTDF_fpprSetMode(FTDF_Boolean matchFp, FTDF_Boolean fpOverride, FTDF_Boolean fpForce); + +#if FTDF_FP_BIT_TEST_MODE +/** + * \brief Gets FPPR mode. + * + * \param [out] matchFp Reference to the returned value. \see FTDF_fpprRamSetMode + * + * \param [out] fpOverride Reference to the returned value. \see FTDF_fpprRamSetMode + * + * \param [out] fpForce FP Reference to the returned value. \see FTDF_fpprRamSetMode + */ +void FTDF_fpprGetMode(FTDF_Boolean * matchFp, FTDF_Boolean * fpOverride, FTDF_Boolean * fpForce); +#endif //FTDF_FP_BIT_TEST_MODE + +#if FTDF_USE_LPDP == 1 + +/** + * \brief Enable or disable LPDP. + * + * \param [in] enable if FTDF_TRUE, LPDP functionality is enabled. + */ +void FTDF_lpdpEnable(FTDF_Boolean enable); + +#if FTDF_FP_BIT_TEST_MODE +/** + * \brief Checks whether LPDP is enabled. + * + * \return FTDF_TRUE, if LPDP functionality is enabled. + */ +FTDF_Boolean FTDF_lpdpIsEnabled(void); +#endif + +#endif /* #if FTDF_USE_LPDP == 1 */ +#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ + #endif /* FTDF_H_ */ /** diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h old mode 100755 new mode 100644 index c5e6a261c..04e68c09c --- a/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h @@ -28,25 +28,24 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * **************************************************************************************** */ #ifndef FTDF_CONFIG_PHY_API_H_ #define FTDF_CONFIG_PHY_API_H_ -//#include "osal.h" // OS_FREERTOS macro is checked within the header file. - /** * \remark phy configuration values in microseconds */ #define FTDF_PHYTXSTARTUP 0x4c #define FTDF_PHYTXLATENCY 0x01 #define FTDF_PHYTXFINISH 0x00 -#define FTDF_PHYTRXWAIT 0x0f +#define FTDF_PHYTRXWAIT 0x20 #define FTDF_PHYRXSTARTUP 0 #define FTDF_PHYRXLATENCY 0 -#define FTDF_PHYENABLE 0 +#define FTDF_PHYENABLE 0x21 #ifndef FTDF_LITE #define FTDF_LITE @@ -146,5 +145,18 @@ void vPortExitCritical( void ); #define FTDF_DBG_BUS_GPIO_CONFIG ad_ftdf_dbgBusGpioConfig #endif /* FTDF_DBG_BUS_ENABLE */ +#ifndef FTDF_USE_FP_PROCESSING_RAM +/** + * \brief Whether to use HW acceleration for indirect sending. + * + * Feature is supported as of IC revision 14683-00. + */ +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +#define FTDF_USE_FP_PROCESSING_RAM 1 +#else +#define FTDF_USE_FP_PROCESSING_RAM 0 +#endif +#endif /* FTDF_USE_FP_PROCESSING_RAM */ + #endif /* FTDF_CONFIG_PHY_API_H_ */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c index a48b3f87f..cc829d982 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c @@ -29,8 +29,10 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ +#ifdef CONFIG_USE_FTDF #include #include @@ -45,15 +47,22 @@ #include "sys_tcs.h" -#include "black_orca.h" +#include "sdk_defs.h" #include "ad_ftdf.h" -#include "ad_rf.h" #include "internal.h" #include "regmap.h" #if FTDF_DBG_BUS_ENABLE #include "hw_gpio.h" #endif /* FTDF_DBG_BUS_ENABLE */ +#if FTDF_DBG_BLOCK_SLEEP_ENABLE +#include "hw_gpio.h" +#endif + +#if dg_configUSE_FTDF_DDPHY == 1 +#include "radio.h" +#endif + #define WUP_LATENCY (AD_FTDF_LP_CLOCK_CYCLE * AD_FTDF_WUP_LATENCY) #ifdef FTDF_PHY_API @@ -61,7 +70,7 @@ #define PRIVILEGED_DATA __attribute__((section("privileged_data_zi"))) #endif #ifndef INITIALIZED_PRIVILEGED_DATA -#define INITIALIZED_PRIVILEGED_DATA __attribute__((section("privileged_data_rw"))) +#define INITIALIZED_PRIVILEGED_DATA __attribute__((section("privileged_data_init"))) #endif #endif @@ -70,7 +79,6 @@ PRIVILEGED_DATA eSleepStatus sleep_status; PRIVILEGED_DATA FTDF_ExtAddress uExtAddress; - static void ad_ftdf_sleep(void) { @@ -82,6 +90,10 @@ static void ad_ftdf_sleep(void) while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_DOWN) == 0x0) // don't go-go before I sleep { } + +#if FTDF_DBG_BLOCK_SLEEP_ENABLE + hw_gpio_set_inactive(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN); +#endif } void ad_ftdf_wake_up_internal(bool sync) @@ -101,25 +113,18 @@ void ad_ftdf_wake_up_internal(bool sync) { } - /* Power on and configure RF */ -#if dg_configRF_ADAPTER - ad_rf_request_on(false); -#else - vPortEnterCritical(); - hw_rf_request_on(false); - vPortExitCritical(); +#if FTDF_DBG_BLOCK_SLEEP_ENABLE + hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true); #endif + /* Power on and configure RF */ + ad_rf_request_on(false); + /* Apply trim values */ - sys_tcs_apply(tcs_ftdf); +// sys_tcs_apply(tcs_ftdf); -#if dg_configRF_ADAPTER ad_rf_request_recommended_settings(); -#else - vPortEnterCritical(); - hw_rf_request_recommended_settings(); - vPortExitCritical(); -#endif if (sync) { @@ -207,21 +212,27 @@ void sleep_when_possible(uint8_t explicit_request, uint32_t sleepTime) // FTDF ready to sleep, disable clocks sleep_status = BLOCK_SLEEPING; explicit_sleep = explicit_request; +#if FTDF_USE_SLEEP_DURING_BACKOFF + FTDF_sdbFsmSleep(); +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ +#if dg_configUSE_FTDF_DDPHY == 1 + FTDF_ddphySave(); +#endif /* dg_configUSE_FTDF_DDPHY */ ad_ftdf_sleep(); } + else + { +#if FTDF_USE_SLEEP_DURING_BACKOFF + FTDF_sdbFsmAbortSleep(); +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ + } } FTDF_exitCritical(); if (blockSleep) { -#if dg_configRF_ADAPTER ad_rf_request_off(false); -#else - vPortEnterCritical(); - hw_rf_request_off(false); - vPortExitCritical(); -#endif } } @@ -237,6 +248,10 @@ void ad_ftdf_init(void) { } +#if FTDF_DBG_BLOCK_SLEEP_ENABLE + hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN, + HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true); +#endif REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_ENABLE); // on REG_SETF(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_DIV, 0); // divide by 1 @@ -276,13 +291,26 @@ void ad_ftdf_dbgBusGpioConfig(void) HW_GPIO_FUNC_FTDF_DIAG); hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_FTDF_DIAG); +#if FTDF_DBG_BUS_USE_SWDIO_PIN + /* + * Note that this pin has a conflict with SWD. Disable the debugger in order to use this + * pin. + */ hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_FTDF_DIAG); +#endif hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_FTDF_DIAG); +#if FTDF_DBG_BUS_USE_GPIO_P1_3_P2_2 + /* + * Note that these pins have a conflict with the pins used for UART by default. Configure + * UART on different pins if you would like to use the pins below for diagnostics. + */ hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_FTDF_DIAG); hw_gpio_set_pin_function(HW_GPIO_PORT_2, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_FTDF_DIAG); +#endif } #endif /* FTDF_DBG_BUS_ENABLE */ +#endif diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h old mode 100755 new mode 100644 index b82caf6ce..74da2d3d1 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h @@ -1,8 +1,6 @@ /** \addtogroup INTERFACES \{ - \addtogroup RADIO - \{ \addtogroup FTDF \{ */ @@ -36,7 +34,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * + * + * **************************************************************************************** */ diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c index 3d990789f..529f285a2 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c @@ -28,19 +28,27 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * **************************************************************************************** */ +#ifdef CONFIG_USE_FTDF + +#ifdef FTDF_PHY_API #include #include -#include "black_orca.h" +#include "sdk_defs.h" #include "ad_ftdf.h" #include "ad_ftdf_phy_api.h" #include "internal.h" +#if FTDF_DBG_BUS_ENABLE +#include "hw_gpio.h" +#endif /* FTDF_DBG_BUS_ENABLE */ #ifndef OS_FREERTOS -static unsigned long uxCriticalNesting = 0x0 ;//0xaaaaaaaa; +static unsigned long uxCriticalNesting = 0xaaaaaaaa; void vPortEnterCritical(void) { @@ -116,6 +124,9 @@ FTDF_Status ad_ftdf_send_frame_simple(FTDF_DataLength frameLength, { /* Wake-up the block */ ad_ftdf_wake_up_async(); +#if FTDF_DBG_BUS_ENABLE + FTDF_checkDbgMode(); +#endif /* FTDF_DBG_BUS_ENABLE */ sleep_status = BLOCK_ACTIVE; } @@ -134,6 +145,9 @@ void ad_ftdf_wake_up(void) { /* Wake-up the block */ ad_ftdf_wake_up_async(); +#if FTDF_DBG_BUS_ENABLE + FTDF_checkDbgMode(); +#endif /* FTDF_DBG_BUS_ENABLE */ sleep_status = BLOCK_ACTIVE; } @@ -151,5 +165,7 @@ void ad_ftdf_init_phy_api(void) uxCriticalNesting = 0; #endif - FTDF_reset(0); + FTDF_reset(1); } +#endif /* FTDF_PHY_API */ +#endif diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c index 3ebbc1ec2..caa379bff 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c @@ -29,6 +29,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -38,7 +39,7 @@ #include #include "internal.h" #include "regmap.h" -#include "black_orca.h" +#include "sdk_defs.h" #if dg_configCOEX_ENABLE_CONFIG #include "hw_coex.h" @@ -58,6 +59,17 @@ typedef struct struct FTDF_Pib FTDF_pib __attribute__((section(".retention"))); +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO +#if FTDF_FPPR_DEFER_INVALIDATION +static struct +{ + FTDF_AddressMode addrMode; + FTDF_PANId PANId; + FTDF_Address addr; +} FTDF_fpprPending __attribute__((section(".retention"))); +#endif /* FTDF_FPPR_DEFER_INVALIDATION */ +#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ + #ifndef FTDF_LITE const FTDF_ChannelNumber page0Channels[ FTDF_NR_OF_CHANNELS ] = { 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; @@ -444,7 +456,7 @@ const PIBAttributeTable pibAttributeTable = .attributeDefs[ FTDF_PIB_CCA_MODE ].addr = &FTDF_pib.CCAMode, .attributeDefs[ FTDF_PIB_CCA_MODE ].size = sizeof(FTDF_pib.CCAMode), .attributeDefs[ FTDF_PIB_CCA_MODE ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_CCA_MODE ].setFunc = NULL, + .attributeDefs[ FTDF_PIB_CCA_MODE ].setFunc = FTDF_setTXPower, #ifndef FTDF_LITE .attributeDefs[ FTDF_PIB_CURRENT_PAGE ].addr = &FTDF_pib.currentPage, .attributeDefs[ FTDF_PIB_CURRENT_PAGE ].size = 0, @@ -515,8 +527,18 @@ const PIBAttributeTable pibAttributeTable = .attributeDefs[ FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD ].addr = &FTDF_pib.tsSyncCorrectThreshold, .attributeDefs[ FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD ].size = sizeof(FTDF_pib.tsSyncCorrectThreshold), .attributeDefs[ FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD ].getFunc = NULL, - .attributeDefs[ FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD ].setFunc = NULL + .attributeDefs[ FTDF_PIB_TS_SYNC_CORRECT_THRESHOLD ].setFunc = NULL, #endif /* !FTDF_LITE */ +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A + .attributeDefs[ FTDF_PIB_BO_IRQ_THRESHOLD ].addr = &FTDF_pib.boIrqThreshold, + .attributeDefs[ FTDF_PIB_BO_IRQ_THRESHOLD ].size = sizeof(FTDF_pib.boIrqThreshold), + .attributeDefs[ FTDF_PIB_BO_IRQ_THRESHOLD ].getFunc = FTDF_getBoIrqThreshold, + .attributeDefs[ FTDF_PIB_BO_IRQ_THRESHOLD ].setFunc = FTDF_setBoIrqThreshold, + .attributeDefs[ FTDF_PIB_PTI_CONFIG ].addr = &FTDF_pib.ptiConfig, + .attributeDefs[ FTDF_PIB_PTI_CONFIG ].size = sizeof(FTDF_pib.ptiConfig), + .attributeDefs[ FTDF_PIB_PTI_CONFIG ].getFunc = NULL, + .attributeDefs[ FTDF_PIB_PTI_CONFIG ].setFunc = FTDF_setPtiConfig, +#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ }; FTDF_Boolean FTDF_transparentMode __attribute__((section(".retention"))); @@ -524,6 +546,9 @@ FTDF_Bitmap32 FTDF_transparentModeOptions __attribut #if FTDF_DBG_BUS_ENABLE FTDF_DbgMode FTDF_dbgMode __attribute__((section(".retention"))); #endif +#if dg_configUSE_FTDF_DDPHY == 1 +uint16_t FTDF_ddphyCcaReg __attribute__((section(".retention"))); +#endif #ifndef FTDF_LITE FTDF_Buffer FTDF_reqBuffers[ FTDF_NR_OF_REQ_BUFFERS ] __attribute__((section(".retention"))); FTDF_Queue FTDF_reqQueue __attribute__((section(".retention"))); @@ -538,6 +563,9 @@ FTDF_Time FTDF_txPendingTimerTime __attribut FTDF_MsgBuffer *FTDF_reqCurrent __attribute__((section(".retention"))); #endif FTDF_Size FTDF_nrOfRetries __attribute__((section(".retention"))); +#if FTDF_USE_SLEEP_DURING_BACKOFF +static FTDF_Sdb FTDF_sdb __attribute__((section(".retention"))); +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ #ifndef FTDF_LITE FTDF_Boolean FTDF_isPANCoordinator __attribute__((section(".retention"))); FTDF_Time FTDF_startCslSampleTime __attribute__((section(".retention"))); @@ -560,7 +588,7 @@ FTDF_SecurityHeader FTDF_sh; FTDF_AssocAdmin FTDF_aa; #endif /* !FTDF_LITE */ -#if dg_configCOEX_ENABLE_CONFIG +#if FTDF_USE_PTI /* Packet traffic information used when FTDF is in RX enable. */ static FTDF_PTI FTDF_RxPti __attribute__((section(".retention"))); #endif @@ -635,6 +663,15 @@ void FTDF_reset(int setDefaultPIB) FTDF_pib.timeslotTemplate.tsTimeslotLength = 10000; FTDF_pib.tsSyncCorrectThreshold = 220; FTDF_pib.hoppingSequenceLength = 16; +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A + int i; + + for (i = 0; i < FTDF_PTIS; i++) + { + FTDF_pib.ptiConfig.ptis[i] = 0; + } + +#endif #ifdef FTDF_NO_CSL FTDF_pib.LECapable = FTDF_FALSE; #else @@ -666,6 +703,9 @@ void FTDF_reset(int setDefaultPIB) #ifndef FTDF_LITE memset(FTDF_pib.defaultKeySource, 0xff, 8); #endif /* !FTDF_LITE */ +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A + FTDF_pib.boIrqThreshold = FTDF_BO_IRQ_THRESHOLD; +#endif /* #if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ } FTDF_initQueues(); @@ -683,13 +723,23 @@ void FTDF_reset(int setDefaultPIB) volatile uint32_t *wakeupTimerEnableStatus = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS); +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE, 0); +#else + FTDF_SET_FIELD(ON_OFF_REGMAP_WAKEUPTIMERENABLE_CLEAR, 1); +#endif + while (*wakeupTimerEnableStatus & MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS) { } +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE, 1); +#else + FTDF_SET_FIELD(ON_OFF_REGMAP_WAKEUPTIMERENABLE_SET, 1); +#endif + while ((*wakeupTimerEnableStatus & MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS) == 0) { } @@ -735,13 +785,17 @@ void FTDF_reset(int setDefaultPIB) #endif /* FTDF_NO_TSCH */ #endif /* !FTDF_LITE */ +#if FTDF_USE_SLEEP_DURING_BACKOFF + FTDF_sdbFsmReset(); +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ FTDF_initLmac(); #ifndef FTDF_NO_CSL FTDF_rzTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); #endif /* FTDF_NO_CSL */ -#if dg_configCOEX_ENABLE_CONFIG - FTDF_RxPti = 0; + +#if dg_configUSE_FTDF_DDPHY == 1 + FTDF_ddphySet(0); #endif } @@ -821,6 +875,27 @@ void FTDF_initLmac(void) *txFlagClearM |= MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M; txFlagClearM = FTDF_GET_FIELD_ADDR_INDEXED(ON_OFF_REGMAP_TX_FLAG_CLEAR_M, FTDF_TX_WAKEUP_BUFFER); *txFlagClearM |= MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M; +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO + FTDF_fpprReset(); + FTDF_fpprSetMode(FTDF_TRUE, FTDF_FALSE, FTDF_FALSE); +#else + FTDF_fpprSetMode(FTDF_FALSE, FTDF_TRUE, FTDF_TRUE); +#endif /* #if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ +#if FTDF_USE_SLEEP_DURING_BACKOFF + /* Unmask long BO interrupt. */ + FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_THR_M, 1); +#else /* FTDF_USE_SLEEP_DURING_BACKOFF */ + /* Set BO threshold. */ + FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD, FTDF_BO_IRQ_THRESHOLD); + + /* Mask long BO interrupt. */ + FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_THR_M, 0); +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ +#if FTDF_USE_LPDP == 1 + FTDF_lpdpEnable(FTDF_TRUE); +#endif /* #if FTDF_USE_LPDP == 1 */ +#endif /* #if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ } #ifdef FTDF_PHY_API @@ -1001,7 +1076,10 @@ void FTDF_sendCommStatusIndication(FTDF_MsgBuffer *request, FTDF_REL_MSG_BUFFER(request); FTDF_RCV_MSG((FTDF_MsgBuffer *) commStatus); - + /* Check for orphan response. */ +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO + FTDF_fpFsmClearPending(); +#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ FTDF_processNextRequest(); return; } @@ -1059,22 +1137,22 @@ FTDF_Octet *FTDF_addFrameHeader(FTDF_Octet *txPtr, // if ( panIdPresent || iesIncluded || seqNrSuppressed || ( options & FTDF_OPT_ENHANCED ) || FTDF_pib.tschEnabled ) if (panIdPresent || iesIncluded || seqNrSuppressed || (options & FTDF_OPT_ENHANCED)) { - frameVersion = 0x02; // 0b10; + frameVersion = 0b10; } else { if (secure || msduLength > FTDF_MAX_MAC_SAFE_PAYLOAD_SIZE) { - frameVersion = 0x01; // 0b01; + frameVersion = 0b01; } else { - frameVersion = 0x00; // 0b00; + frameVersion = 0b00; } } - if (frameVersion < 0x02) //0b10 ) + if (frameVersion < 0b10) { if (dstAddrMode != FTDF_NO_ADDRESS && srcAddrMode != FTDF_NO_ADDRESS && @@ -1121,7 +1199,7 @@ FTDF_Octet *FTDF_addFrameHeader(FTDF_Octet *txPtr, } else { - if (frameVersion < 0x02) //0b10 ) + if (frameVersion < 0b10) { if (dstAddrMode != FTDF_NO_ADDRESS) { @@ -1176,7 +1254,7 @@ FTDF_Octet *FTDF_addFrameHeader(FTDF_Octet *txPtr, if (frameType != FTDF_MULTIPURPOSE_FRAME) { - if (frameVersion < 0x02) // 0b10 ) + if (frameVersion < 0b10) { if (srcAddrMode != FTDF_NO_ADDRESS && !panIdCompression) { @@ -1229,7 +1307,7 @@ FTDF_Octet *FTDF_addFrameHeader(FTDF_Octet *txPtr, FTDF_PTI FTDF_getRxPti(void) { -#if dg_configCOEX_ENABLE_CONFIG +#if FTDF_USE_PTI FTDF_PTI rx_pti; FTDF_criticalVar(); FTDF_enterCritical(); @@ -1241,16 +1319,6 @@ FTDF_PTI FTDF_getRxPti(void) #endif } -void FTDF_setRxPti(FTDF_PTI rx_pti) -{ -#if dg_configCOEX_ENABLE_CONFIG - FTDF_criticalVar(); - FTDF_enterCritical(); - FTDF_RxPti = rx_pti; - FTDF_exitCritical(); -#endif -} - #ifdef FTDF_PHY_API void FTDF_rxEnable(FTDF_Time rxOnDuration) { @@ -1286,7 +1354,7 @@ FTDF_Octet *FTDF_getFrameHeader(FTDF_Octet *rxBuffer, FTDF_FrameHeader *frameHeader) { FTDF_FrameType frameType = *rxBuffer & 0x07; - uint8_t frameVersion = 0; // 0b00; + uint8_t frameVersion = 0; FTDF_Bitmap8 options = 0; FTDF_AddressMode dstAddrMode; FTDF_AddressMode srcAddrMode; @@ -1330,7 +1398,7 @@ FTDF_Octet *FTDF_getFrameHeader(FTDF_Octet *rxBuffer, options |= FTDF_OPT_IES_PRESENT; } - frameVersion = 0x00; //0b00; + frameVersion = 0; frameHeader->frameVersion = FTDF_FRAME_VERSION_E; @@ -1364,7 +1432,7 @@ FTDF_Octet *FTDF_getFrameHeader(FTDF_Octet *rxBuffer, frameVersion = (*rxBuffer & 0x30) >> 4; - if (frameVersion == 0x02) //0b10 ) + if (frameVersion == 0x02) { if (*rxBuffer & 0x01) { @@ -1378,11 +1446,11 @@ FTDF_Octet *FTDF_getFrameHeader(FTDF_Octet *rxBuffer, frameHeader->frameVersion = FTDF_FRAME_VERSION_E; } - else if (frameVersion == 0x01) // 0b01 ) + else if (frameVersion == 0x01) { frameHeader->frameVersion = FTDF_FRAME_VERSION_2011; } - else if (frameVersion == 0x00) //0b00 ) + else if (frameVersion == 0x00) { frameHeader->frameVersion = FTDF_FRAME_VERSION_2003; } @@ -1411,7 +1479,7 @@ FTDF_Octet *FTDF_getFrameHeader(FTDF_Octet *rxBuffer, } else { - if (frameVersion < 0x02) //0b10 ) + if (frameVersion < 0x02) { if (dstAddrMode != FTDF_NO_ADDRESS) { @@ -1461,7 +1529,7 @@ FTDF_Octet *FTDF_getFrameHeader(FTDF_Octet *rxBuffer, FTDF_Boolean hasSrcPANId = FTDF_FALSE; - if (frameVersion < 0x02 && frameType != FTDF_MULTIPURPOSE_FRAME) //0b10 + if (frameVersion < 0x02 && frameType != FTDF_MULTIPURPOSE_FRAME) { if (srcAddrMode != FTDF_NO_ADDRESS && !panIdCompression) { @@ -1586,6 +1654,8 @@ static void processRxFrame(int readBuf) status |= rxMeta1 & MSK_F_FTDF_RETENTION_RAM_DPANID_ERROR ? FTDF_TRANSPARENT_RCV_UNEXP_DST_PAN_ID : 0; status |= rxMeta1 & MSK_F_FTDF_RETENTION_RAM_DADDR_ERROR ? FTDF_TRANSPARENT_RCV_UNEXP_DST_ADDR : 0; + FTDF_RCV_FRAME_TRANSPARENT(frameLen, rxPtr, status, lqi); + #if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK if ((FTDF_transparentModeOptions & FTDF_TRANSPARENT_WAIT_FOR_ACK)) @@ -1645,14 +1715,62 @@ static void processRxFrame(int readBuf) } #endif /* FTDF_TRANSPARENT_USE_WAIT_FOR_ACK */ - FTDF_RCV_FRAME_TRANSPARENT(frameLen, rxPtr, status, lqi); - return; } #ifndef FTDF_LITE rxPtr = FTDF_getFrameHeader(rxPtr, frameHeader); +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_MANUAL + + if (frameHeader->options & FTDF_OPT_ACK_REQUESTED) + { + int n; + FTDF_Boolean addressFound = FTDF_FALSE; + + for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) + { + if (FTDF_txPendingList[ n ].addrMode == frameHeader->srcAddrMode && + FTDF_txPendingList[ n ].PANId == frameHeader->srcPANId) + { + if (frameHeader->srcAddrMode == FTDF_SHORT_ADDRESS) + { + if (FTDF_txPendingList[ n ].addr.shortAddress == + frameHeader->srcAddr.shortAddress) + { + addressFound = FTDF_TRUE; + break; + } + } + else if (frameHeader->srcAddrMode == FTDF_EXTENDED_ADDRESS) + { + if (FTDF_txPendingList[ n ].addr.extAddress == + frameHeader->srcAddr.extAddress) + { + addressFound = FTDF_TRUE; + break; + } + } + else + { + // Invalid srcAddrMode + return; + } + } + } + + if (addressFound) + { + FTDF_fpprSetMode(FTDF_FALSE, FTDF_TRUE, FTDF_TRUE); + } + else + { + FTDF_fpprSetMode(FTDF_FALSE, FTDF_TRUE, FTDF_FALSE); + } + } + +#endif + if (frameHeader->frameVersion == FTDF_FRAME_VERSION_NOT_SUPPORTED) { return; @@ -2522,6 +2640,23 @@ static void processRxFrame(int readBuf) } } +#if FTDF_USE_LPDP +#if FTDF_FP_BIT_TEST_MODE + + if (FTDF_lpdpIsEnabled() && !FTDF_reqCurrent && frameType == FTDF_DATA_FRAME) + { + FTDF_processTxPending(frameHeader, securityHeader); + } + +#else /* FTDF_FP_BIT_TEST_MODE */ + + if (!FTDF_reqCurrent && frameType == FTDF_DATA_FRAME) + { + FTDF_processTxPending(frameHeader, securityHeader); + } + +#endif /* FTDF_FP_BIT_TEST_MODE */ +#endif /* FTDF_USE_LPDP */ #ifndef FTDF_NO_TSCH if (FTDF_pib.tschEnabled == FTDF_TRUE) @@ -2616,6 +2751,11 @@ void FTDF_processRxEvent(void) *lmacEvent = MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E; #endif + if (FTDF_pib.metricsEnabled) + { + FTDF_pib.performanceMetrics.RxExpiredCount++; + } + #ifndef FTDF_LITE #ifndef FTDF_NO_TSCH @@ -2647,6 +2787,28 @@ void FTDF_processRxEvent(void) #endif /* !FTDF_LITE */ } + +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A + + if (*lmacEvent & MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E) + { +#ifdef SIMULATOR + *lmacEvent &= ~MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E; +#else + *lmacEvent = MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E; +#endif +#if FTDF_USE_SLEEP_DURING_BACKOFF + + if (FTDF_pib.metricsEnabled) + { + FTDF_pib.performanceMetrics.BOIrqCount++; + } + + FTDF_sdbFsmBackoffIRQ(); +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ + } + +#endif } static void sendConfirm(FTDF_Status status, @@ -2829,7 +2991,9 @@ void FTDF_processTxEvent(void) volatile uint32_t *txFlagStatE; FTDF_Status status = FTDF_SUCCESS; -#if dg_configCOEX_ENABLE_CONFIG +#if FTDF_USE_PTI && !FTDF_USE_AUTO_PTI + /* Restore Rx PTI in case the Tx transaction that just ended interrupted an Rx-always-on + * transaction. */ hw_coex_pti_t tx_pti; hw_coex_update_ftdf_pti(FTDF_getRxPti(), &tx_pti, true); #endif @@ -2893,7 +3057,9 @@ void FTDF_processTxEvent(void) FTDF_exitCritical(); #endif - +#if FTDF_USE_SLEEP_DURING_BACKOFF + FTDF_sdbFsmTxIRQ(); +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ FTDF_Boolean ackTX = FTDF_GET_FIELD_INDEXED(RETENTION_RAM_ACKREQUEST, FTDF_TX_DATA_BUFFER); if (status == FTDF_SUCCESS) @@ -2985,7 +3151,7 @@ void FTDF_processTxEvent(void) #endif /* FTDF_NO_CSL */ #endif /* !FTDF_LITE */ { -#if dg_configCOEX_ENABLE_CONFIG +#if FTDF_USE_PTI && !FTDF_USE_AUTO_PTI hw_coex_update_ftdf_pti(tx_pti, NULL, true); #endif volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); @@ -3236,7 +3402,7 @@ FTDF_Status FTDF_sendFrame(FTDF_ChannelNumber channel, volatile uint32_t *metaData1 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_1, FTDF_TX_DATA_BUFFER); uint16_t phyAttr = (FTDF_pib.CCAMode & 0x3) | 0x08 | ((channel - 11) & 0x0F) << 4 | - (FTDF_pib.TXPower & 0x03) << 8; + (FTDF_pib.TXPower & 0x07) << 12; metaData0 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_0, FTDF_TX_DATA_BUFFER); metaData1 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_1, FTDF_TX_DATA_BUFFER); @@ -3252,7 +3418,8 @@ FTDF_Status FTDF_sendFrame(FTDF_ChannelNumber channel, *metaData1 = ((frameHeader->SN << OFF_F_FTDF_RETENTION_RAM_MACSN) & MSK_F_FTDF_RETENTION_RAM_MACSN); - uint32_t phyCsmaCaAttr = (FTDF_pib.CCAMode & 0x3) | ((channel - 11) & 0xf) << 4; + uint32_t phyCsmaCaAttr = (FTDF_pib.CCAMode & 0x3) | ((channel - 11) & 0xf) << 4 | + (FTDF_pib.TXPower & 0x07) << 12; FTDF_SET_FIELD(ON_OFF_REGMAP_PHYCSMACAATTR, phyCsmaCaAttr); #ifndef FTDF_NO_CSL @@ -3295,8 +3462,11 @@ FTDF_Status FTDF_sendFrame(FTDF_ChannelNumber channel, *metaData1 = ((frameHeader->SN << OFF_F_FTDF_RETENTION_RAM_MACSN) & MSK_F_FTDF_RETENTION_RAM_MACSN); - +#if FTDF_USE_PTI && FTDF_USE_AUTO_PTI + *txPriority |= MSK_F_FTDF_ON_OFF_REGMAP_ISWAKEUP; +#else *txPriority = MSK_F_FTDF_ON_OFF_REGMAP_ISWAKEUP; +#endif } #endif /* FTDF_NO_CSL */ @@ -3379,7 +3549,7 @@ FTDF_Status FTDF_sendAckFrame(FTDF_FrameHeader *frameHeader, uint16_t phyAttr = (FTDF_pib.CCAMode & 0x3) | 0x08 | (FTDF_GET_FIELD(ON_OFF_REGMAP_PHYRXATTR) & 0x00f0) | - (FTDF_pib.TXPower & 0x03) << 8; + (FTDF_pib.TXPower & 0x07) << 12; *metaData0 = ((phyPayloadSize << OFF_F_FTDF_RETENTION_RAM_FRAME_LENGTH) & MSK_F_FTDF_RETENTION_RAM_FRAME_LENGTH) | @@ -3390,7 +3560,11 @@ FTDF_Status FTDF_sendAckFrame(FTDF_FrameHeader *frameHeader, *metaData1 = ((frameHeader->SN << OFF_F_FTDF_RETENTION_RAM_MACSN) & MSK_F_FTDF_RETENTION_RAM_MACSN); +#if FTDF_USE_PTI && FTDF_USE_AUTO_PTI + *txPriority |= 1; +#else *txPriority = 1; +#endif volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); @@ -3431,6 +3605,7 @@ void FTDF_sendTransparentFrame(FTDF_DataLength frameLength, { volatile uint32_t *metaData0 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_0, FTDF_TX_DATA_BUFFER); volatile uint32_t *metaData1 = FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_1, FTDF_TX_DATA_BUFFER); + volatile uint32_t *txPriority = FTDF_GET_REG_ADDR_INDEXED(ON_OFF_REGMAP_TX_PRIORITY, FTDF_TX_DATA_BUFFER); #if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK FTDF_Boolean useAck = FTDF_FALSE; @@ -3439,7 +3614,7 @@ void FTDF_sendTransparentFrame(FTDF_DataLength frameLength, FTDF_SN SN; #endif uint16_t phyAttr = (FTDF_pib.CCAMode & 0x3) | 0x08 | ((channel - 11) & 0x0F) << 4 | - (FTDF_pib.TXPower & 0x03) << 8; + (FTDF_pib.TXPower & 0x07) << 12; #if FTDF_TRANSPARENT_USE_WAIT_FOR_ACK if (FTDF_transparentModeOptions & FTDF_TRANSPARENT_WAIT_FOR_ACK) @@ -3456,6 +3631,10 @@ void FTDF_sendTransparentFrame(FTDF_DataLength frameLength, #endif +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A + *txPriority = ((pti << OFF_F_FTDF_ON_OFF_REGMAP_PTI_TX) & + MSK_F_FTDF_ON_OFF_REGMAP_PTI_TX) | 1; +#endif *metaData0 = ((frameLength << OFF_F_FTDF_RETENTION_RAM_FRAME_LENGTH) & MSK_F_FTDF_RETENTION_RAM_FRAME_LENGTH) | ((phyAttr << OFF_F_FTDF_RETENTION_RAM_PHYATTR) & MSK_F_FTDF_RETENTION_RAM_PHYATTR) | @@ -3483,10 +3662,13 @@ void FTDF_sendTransparentFrame(FTDF_DataLength frameLength, ((0 << OFF_F_FTDF_RETENTION_RAM_MACSN) & MSK_F_FTDF_RETENTION_RAM_MACSN); #endif - uint32_t phyCsmaCaAttr = (FTDF_pib.CCAMode & 0x3) | ((channel - 11) & 0xf) << 4; + uint32_t phyCsmaCaAttr = (FTDF_pib.CCAMode & 0x3) | ((channel - 11) & 0xf) << 4 | + (FTDF_pib.TXPower & 0x07) << 12; FTDF_SET_FIELD(ON_OFF_REGMAP_PHYCSMACAATTR, phyCsmaCaAttr); -#if dg_configCOEX_ENABLE_CONFIG +#if FTDF_USE_PTI && !FTDF_USE_AUTO_PTI hw_coex_update_ftdf_pti((hw_coex_pti_t) pti, NULL, true); +#else + // FTDF_SET_FIELD(ON_OFF_REGMAP_PTI_TX, pti); #endif volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); *txFlagSet |= (1 << FTDF_TX_DATA_BUFFER); @@ -3911,6 +4093,31 @@ void FTDF_sendTransactionExpired(FTDF_PendingTL *ptr) else #endif /* FTDF_NO_TSCH */ { +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO + + if (FTDF_txPendingList[ ptr->pendListNr ].addrMode == FTDF_SHORT_ADDRESS) + { + uint8_t entry, shortAddrIdx; + FTDF_Boolean found = FTDF_fpprLookupShortAddress( + FTDF_txPendingList[ ptr->pendListNr ].addr.shortAddress, &entry, + &shortAddrIdx); + ASSERT_WARNING(found); + FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_FALSE); + } + else if (FTDF_txPendingList[ ptr->pendListNr ].addrMode == FTDF_EXTENDED_ADDRESS) + { + uint8_t entry; + FTDF_Boolean found = FTDF_fpprLookupExtAddress( + FTDF_txPendingList[ ptr->pendListNr ].addr.extAddress, &entry); + ASSERT_WARNING(found); + FTDF_fpprSetExtAddressValid(entry, FTDF_FALSE); + } + else + { + ASSERT_WARNING(0); + } + +#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ FTDF_txPendingList[ ptr->pendListNr ].addrMode = FTDF_NO_ADDRESS; } } @@ -4329,12 +4536,12 @@ void FTDF_getRxOnWhenIdle(void) void FTDF_setRxOnWhenIdle(void) { -#if dg_configCOEX_ENABLE_CONFIG +#if FTDF_USE_PTI && !FTDF_USE_AUTO_PTI /* We do not force decision here. It will be automatically made when FTDF begins * transaction. */ hw_coex_update_ftdf_pti((hw_coex_pti_t) FTDF_getRxPti(), NULL, false); -#endif +#endif /* FTDF_USE_PTI && !FTDF_USE_AUTO_PTI */ FTDF_SET_FIELD(ON_OFF_REGMAP_RXENABLE, 0); FTDF_SET_FIELD(ON_OFF_REGMAP_RXALWAYSON, FTDF_pib.rxOnWhenIdle); FTDF_SET_FIELD(ON_OFF_REGMAP_RXENABLE, 1); @@ -4358,12 +4565,20 @@ void FTDF_getCurrentChannel(void) void FTDF_setCurrentChannel(void) { - uint32_t phyAckAttr = 0x08 | ((FTDF_pib.currentChannel - 11) & 0xf) << 4 | (FTDF_pib.TXPower & 0x3) << 8; + uint32_t phyAckAttr = 0x08 | ((FTDF_pib.currentChannel - 11) & 0xf) << 4 | (FTDF_pib.TXPower & 0x7) << 12; FTDF_SET_FIELD(ON_OFF_REGMAP_PHYRXATTR, (((FTDF_pib.currentChannel - 11) & 0xf) << 4)); FTDF_SET_FIELD(ON_OFF_REGMAP_PHYACKATTR, phyAckAttr); } +void FTDF_setTXPower(void) +{ + /* Just like setCurrentChannel, this sets pyAckAttr */ + uint32_t phyAckAttr = 0x08 | ((FTDF_pib.currentChannel - 11) & 0xf) << 4 | (FTDF_pib.TXPower & 0x7) << 12; + + FTDF_SET_FIELD(ON_OFF_REGMAP_PHYACKATTR, phyAckAttr); +} + void FTDF_getMaxFrameTotalWaitTime(void) { FTDF_pib.maxFrameTotalWaitTime = FTDF_GET_FIELD(ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME); @@ -4474,6 +4689,27 @@ void FTDF_setKeepPhyEnabled(void) FTDF_SET_FIELD(ON_OFF_REGMAP_KEEP_PHY_EN, FTDF_pib.keepPhyEnabled); } +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +void FTDF_setBoIrqThreshold(void) +{ + FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD, FTDF_pib.boIrqThreshold); +} +void FTDF_getBoIrqThreshold(void) +{ + FTDF_pib.boIrqThreshold = FTDF_GET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD); +} +void FTDF_setPtiConfig(void) +{ + FTDF_SET_FIELD_INDEXED(ON_OFF_REGMAP_PTI_TX, FTDF_pib.ptiConfig.ptis[FTDF_PTI_CONFIG_TX], + FTDF_TX_DATA_BUFFER); + FTDF_SET_FIELD_INDEXED(ON_OFF_REGMAP_PTI_TX, FTDF_pib.ptiConfig.ptis[FTDF_PTI_CONFIG_TX], + FTDF_TX_WAKEUP_BUFFER); + FTDF_SET_FIELD_INDEXED(ON_OFF_REGMAP_PTI_TX, FTDF_pib.ptiConfig.ptis[FTDF_PTI_CONFIG_RX], + FTDF_TX_ACK_BUFFER); + FTDF_SET_FIELD(ON_OFF_REGMAP_PTI_RX, FTDF_pib.ptiConfig.ptis[FTDF_PTI_CONFIG_RX]); +} +#endif /* #if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ + #ifndef FTDF_LITE #ifndef FTDF_NO_TSCH void FTDF_setTimeslotTemplate(void) @@ -4487,3 +4723,877 @@ void FTDF_setTimeslotTemplate(void) } #endif /* FTDF_NO_TSCH */ #endif /* !FTDF_LITE */ + +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO +/************************************ FPPR common functions ***************************************/ +#ifndef FTDF_LITE + +FTDF_Boolean FTDF_fpFsmShortAddressNew(FTDF_PANId panId, FTDF_ShortAddress shortAddress) +{ + uint8_t entry; + uint8_t shortAddrIdx; + + if (FTDF_fpprGetFreeShortAddress(&entry, &shortAddrIdx) == FTDF_FALSE) + { + return FTDF_FALSE; + } + + FTDF_fpprSetShortAddress(entry, shortAddrIdx, shortAddress); + FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_TRUE); + + return FTDF_TRUE; +} + +FTDF_Boolean FTDF_fpFsmExtAddressNew(FTDF_PANId panId, FTDF_ExtAddress extAddress) +{ + uint8_t entry; + + if (FTDF_fpprGetFreeExtAddress(&entry) == FTDF_FALSE) + { + return FTDF_FALSE; + } + + FTDF_fpprSetExtAddress(entry, extAddress); + FTDF_fpprSetExtAddressValid(entry, FTDF_TRUE); + + return FTDF_TRUE; +} + +void FTDF_fpFsmShortAddressLastFramePending(FTDF_PANId PANId, FTDF_ShortAddress shortAddress) +{ +#if FTDF_FPPR_DEFER_INVALIDATION + FTDF_fpprPending.addrMode = FTDF_SHORT_ADDRESS; + FTDF_fpprPending.PANId = PANId; + FTDF_fpprPending.addr.shortAddress = shortAddress; +#else /* FTDF_FPPR_DEFER_INVALIDATION */ + uint8_t entry; + uint8_t shortAddrIdx; + FTDF_Boolean found = FTDF_fpprLookupShortAddress(shortAddress, &entry, &shortAddrIdx); + ASSERT_WARNING(found); + FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_FALSE); +#endif /* FTDF_FPPR_DEFER_INVALIDATION */ +} + +void FTDF_fpFsmExtAddressLastFramePending(FTDF_PANId PANId, FTDF_ExtAddress extAddress) +{ +#if FTDF_FPPR_DEFER_INVALIDATION + FTDF_fpprPending.addrMode = FTDF_EXTENDED_ADDRESS; + FTDF_fpprPending.PANId = PANId; + FTDF_fpprPending.addr.extAddress = extAddress; +#else /* FTDF_FPPR_DEFER_INVALIDATION */ + uint8_t entry; + FTDF_Boolean found = FTDF_fpprLookupExtAddress(extAddress, &entry); + ASSERT_WARNING(found); + FTDF_fpprSetExtAddressValid(entry, FTDF_FALSE); +#endif /* FTDF_FPPR_DEFER_INVALIDATION */ +} + +void FTDF_fpFsmClearPending(void) +{ +#if FTDF_FPPR_DEFER_INVALIDATION + int n; + + if (FTDF_fpprPending.addrMode == FTDF_NO_ADDRESS) + { + return; + } + + if (FTDF_fpprPending.addrMode == FTDF_SHORT_ADDRESS) + { + for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) + { + if (FTDF_txPendingList[ n ].addrMode == FTDF_SHORT_ADDRESS) + { + if ((FTDF_txPendingList[ n ].PANId == FTDF_fpprPending.PANId) && + (FTDF_txPendingList[ n ].addr.shortAddress == + FTDF_fpprPending.addr.shortAddress)) + { + return; + } + } + } + + // Address not found. + uint8_t entry; + uint8_t shortAddrIdx; + FTDF_Boolean found = FTDF_fpprLookupShortAddress( + FTDF_fpprPending.addr.shortAddress, &entry, &shortAddrIdx); + ASSERT_WARNING(found); + FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_FALSE); + } + else if (FTDF_fpprPending.addrMode == FTDF_EXTENDED_ADDRESS) + { + for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) + { + if (FTDF_txPendingList[ n ].addrMode == FTDF_EXTENDED_ADDRESS) + { + if (FTDF_txPendingList[ n ].addr.extAddress == + FTDF_fpprPending.addr.extAddress) + { + return; + } + } + } + + // Address not found. + uint8_t entry; + FTDF_Boolean found = FTDF_fpprLookupExtAddress(FTDF_fpprPending.addr.extAddress, + &entry); + ASSERT_WARNING(found); + FTDF_fpprSetExtAddressValid(entry, FTDF_FALSE); + } + else + { + + } + + FTDF_fpprPending.addrMode = FTDF_NO_ADDRESS; +#endif /* FTDF_FPPR_DEFER_INVALIDATION */ +} + +#endif /* #ifndef FTDF_LITE */ +/*********************************** FPPR low-level access ****************************************/ +void FTDF_fpprReset(void) +{ + unsigned int i; + + for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) + { + *FTDF_GET_REG_ADDR_INDEXED(FP_PROCESSING_RAM_SIZE_AND_VAL, i) = 0; + } +} + +FTDF_ShortAddress FTDF_fpprGetShortAddress(uint8_t entry, uint8_t shortAddrIdx) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + + switch (shortAddrIdx) + { + case 0: + return (FTDF_ShortAddress) + * FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry) & + 0x0000ffff; + + case 1: + return (FTDF_ShortAddress) + (*FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry) >> 16) & + 0x0000ffff; + + case 2: + return (FTDF_ShortAddress) + * FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry) & + 0x0000ffff; + + case 3: + return (FTDF_ShortAddress) + (*FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry) >> 16) & + 0x0000ffff; + + default: + ASSERT_WARNING(0); + } +} + +void FTDF_fpprSetShortAddress(uint8_t entry, uint8_t shortAddrIdx, + FTDF_ShortAddress shortAddress) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + uint32_t val32; + + switch (shortAddrIdx) + { + case 0: + val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry); + val32 &= 0xffff0000; + val32 |= (shortAddress & 0x0000ffff); + *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry) = val32; + break; + + case 1: + val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry); + val32 &= 0x0000ffff; + val32 |= (shortAddress & 0x0000ffff) << 16; + *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry) = val32; + break; + + case 2: + val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry); + val32 &= 0xffff0000; + val32 |= (shortAddress & 0x0000ffff); + *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry) = val32; + break; + + case 3: + val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry); + val32 &= 0x0000ffff; + val32 |= (shortAddress & 0x0000ffff) << 16; + *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry) = val32; + break; + + default: + ASSERT_WARNING(0); + } +} + +FTDF_Boolean FTDF_fpprGetShortAddressValid(uint8_t entry, uint8_t shortAddrIdx) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + ASSERT_WARNING(shortAddrIdx < 4); + uint32_t val32; + val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry); + return ((val32 & (MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT | (1 << shortAddrIdx))) == + (MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT | (1 << shortAddrIdx))) ? + FTDF_TRUE : FTDF_FALSE; +} + +void FTDF_fpprSetShortAddressValid(uint8_t entry, uint8_t shortAddrIdx, + FTDF_Boolean valid) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + ASSERT_WARNING(shortAddrIdx < 4); + uint32_t val32; + val32 = *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry); + + if (valid) + { + val32 |= MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT | (1 << shortAddrIdx); /* Also indicate short address. */ + } + else + { + val32 &= ~(1 << shortAddrIdx); + } + + *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry) = val32; +} + +FTDF_ExtAddress FTDF_fpprGetExtAddress(uint8_t entry) +{ + FTDF_ExtAddress extAddress; + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + extAddress = (FTDF_ExtAddress) * FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, + entry) << 32; + extAddress |= (FTDF_ExtAddress) * FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, + entry); + return extAddress; +} + +void FTDF_fpprSetExtAddress(uint8_t entry, FTDF_ExtAddress extAddress) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, entry) = + (uint32_t)(extAddress); + *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, entry) = + (uint32_t)((extAddress >> 32)); +} + +FTDF_Boolean FTDF_fpprGetExtAddressValid(uint8_t entry) +{ + return (*FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry) == 0x1) ? + FTDF_TRUE : FTDF_FALSE; +} + +void FTDF_fpprSetExtAddressValid(uint8_t entry, FTDF_Boolean valid) +{ + ASSERT_WARNING(entry < FTDF_FPPR_TABLE_ENTRIES); + + if (valid) + { + /* Also indicate ext address. */ + *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry) = 0x1; + } + else + { + *FTDF_GET_FIELD_ADDR_INDEXED(FP_PROCESSING_RAM_VALID_SA, entry) = 0x0; + } +} + +FTDF_Boolean FTDF_fpprGetFreeShortAddress(uint8_t *entry, uint8_t *shortAddrIdx) +{ + int i, j; + uint32_t sizeAndVal; + int emptyEntry; + bool emptyFound = false, nonEmptyFound = false; + + for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) + { + sizeAndVal = *FTDF_GET_REG_ADDR_INDEXED(FP_PROCESSING_RAM_SIZE_AND_VAL, i); + + if (sizeAndVal == 0x1) + { + /* Check if there is a valid extended address. */ + continue; + } + else if ((sizeAndVal & MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT) == 0) + { + /* There is an invalid extended address, ignore SA valid bits */ + sizeAndVal = 0; + } + else + { + /* There is a SA. We are interested in bits V0 - V3. */ + sizeAndVal &= 0xf; + } + + /* Check if entire entry is free. */ + if (sizeAndVal == 0) + { + /* We prefer to use partially full entries. Make note of this and + * continue. */ + if (!emptyFound) + { + emptyEntry = i; + emptyFound = true; + } + + continue; + } + + /* Check for free short address entries. */ + sizeAndVal = (~sizeAndVal) & 0xf; + j = 0; + + while (sizeAndVal) + { + if (sizeAndVal & 0x1) + { + nonEmptyFound = true; + break; + } + + sizeAndVal >>= 1; + j++; + } + + if (nonEmptyFound) + { + break; + } + } + + if (nonEmptyFound) + { + *entry = i; + *shortAddrIdx = j; + } + else if (emptyFound) + { + *entry = emptyEntry; + *shortAddrIdx = 0; + } + else + { + return FTDF_FALSE; + } + + return FTDF_TRUE; +} + +FTDF_Boolean FTDF_fpprGetFreeExtAddress(uint8_t *entry) +{ + int i; + uint32_t sizeAndVal; + bool found = false; + + for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) + { + sizeAndVal = *FTDF_GET_REG_ADDR_INDEXED(FP_PROCESSING_RAM_SIZE_AND_VAL, i); + + /* Check if there is no valid extended or short address. */ + if (!sizeAndVal || (sizeAndVal == MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT)) + { + found = true; + break; + } + } + + if (found) + { + *entry = i; + } + else + { + return FTDF_FALSE; + } + + return FTDF_TRUE; +} + +FTDF_Boolean FTDF_fpprLookupShortAddress(FTDF_ShortAddress shortAddr, uint8_t *entry, + uint8_t *shortAddrIdx) +{ + uint8_t i; + uint32_t sizeAndVal; + uint32_t saPart; + + for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) + { + sizeAndVal = *FTDF_GET_REG_ADDR_INDEXED(FP_PROCESSING_RAM_SIZE_AND_VAL, i); + + /* Check if there is a valid short address. */ + if (!(sizeAndVal & MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT) || + !(sizeAndVal & MSK_F_FTDF_FP_PROCESSING_RAM_VALID_SA)) + { + continue; + } + + saPart = FTDF_GET_FIELD_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, i); + + if (sizeAndVal & 0x1) + { + if (shortAddr == (FTDF_ShortAddress)(saPart & 0x0000ffff)) + { + *entry = i; + *shortAddrIdx = 0; + return FTDF_TRUE; + } + } + + if (sizeAndVal & 0x2) + { + if (shortAddr == (FTDF_ShortAddress)((saPart >> 16) & 0x0000ffff)) + { + *entry = i; + *shortAddrIdx = 1; + return FTDF_TRUE; + } + } + + saPart = FTDF_GET_FIELD_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, i); + + if (sizeAndVal & 0x4) + { + if (shortAddr == (FTDF_ShortAddress)(saPart & 0x0000ffff)) + { + *entry = i; + *shortAddrIdx = 2; + return FTDF_TRUE; + } + } + + if (sizeAndVal & 0x8) + { + if (shortAddr == ((FTDF_ShortAddress)(saPart >> 16) & 0x0000ffff)) + { + *entry = i; + *shortAddrIdx = 3; + return FTDF_TRUE; + } + } + } + + return FTDF_FALSE; +} + +FTDF_Boolean FTDF_fpprLookupExtAddress(FTDF_ExtAddress extAddr, uint8_t *entry) +{ + uint8_t i; + uint32_t sizeAndVal; + uint32_t extAddrHi, extAddrLo; + extAddrHi = (uint32_t)((extAddr >> 32) & 0xffffffff); + extAddrLo = (uint32_t)(extAddr & 0xffffffff); + + for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++) + { + sizeAndVal = *FTDF_GET_REG_ADDR_INDEXED(FP_PROCESSING_RAM_SIZE_AND_VAL, i); + + /* Check if there is a valid extended address. */ + if (sizeAndVal != 0x1) + { + continue; + } + + if ((extAddrLo == FTDF_GET_FIELD_INDEXED(FP_PROCESSING_RAM_EXP_SA_L, i)) && + (extAddrHi == FTDF_GET_FIELD_INDEXED(FP_PROCESSING_RAM_EXP_SA_H, i))) + { + *entry = i; + return FTDF_TRUE; + } + } + + return FTDF_FALSE; +} + +#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ + +void FTDF_fpprSetMode(FTDF_Boolean matchFp, FTDF_Boolean fpOverride, FTDF_Boolean fpForce) +{ + FTDF_SET_FIELD(ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE, matchFp ? 1 : 0); + FTDF_SET_FIELD(ON_OFF_REGMAP_FP_OVERRIDE, fpOverride ? 1 : 0); + FTDF_SET_FIELD(ON_OFF_REGMAP_FP_FORCE_VALUE, fpForce ? 1 : 0); +} + +#if FTDF_FP_BIT_TEST_MODE +void FTDF_fpprGetMode(FTDF_Boolean *matchFp, FTDF_Boolean *fpOverride, FTDF_Boolean *fpForce) +{ + *matchFp = FTDF_GET_FIELD(ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE) ? FTDF_TRUE : FTDF_FALSE; + *fpOverride = FTDF_GET_FIELD(ON_OFF_REGMAP_FP_OVERRIDE) ? FTDF_TRUE : FTDF_FALSE; + *fpForce = FTDF_GET_FIELD(ON_OFF_REGMAP_FP_FORCE_VALUE) ? FTDF_TRUE : FTDF_FALSE; +} +#endif // FTDF_FP_BIT_TEST_MODE + +void FTDF_lpdpEnable(FTDF_Boolean enable) +{ + FTDF_SET_FIELD(ON_OFF_REGMAP_FTDF_LPDP_ENABLE, enable ? 1 : 0); +} + +#if FTDF_FP_BIT_TEST_MODE +FTDF_Boolean FTDF_lpdpIsEnabled(void) +{ + return FTDF_GET_FIELD(ON_OFF_REGMAP_FTDF_LPDP_ENABLE) ? FTDF_TRUE : FTDF_FALSE; +} +#endif + +#if FTDF_USE_SLEEP_DURING_BACKOFF + +static inline void FTDF_sdbSaveState(void) +{ + volatile uint32_t *txFifoPtr = FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO); + uint32_t *dstPtr = (uint32_t *) FTDF_sdb.buffer; + uint8_t word_length_rem; + + FTDF_sdb.nrOfBackoffs = FTDF_GET_FIELD(ON_OFF_REGMAP_CSMA_CA_NB_STAT); + + /* Read first 4 bytes. */ + *dstPtr++ = *txFifoPtr++; + + ASSERT_WARNING((FTDF_sdb.buffer[0] >= 3) && (FTDF_sdb.buffer[0] < FTDF_BUFFER_LENGTH)); + /* The length is the buffer length excluding the length byte itself */ + word_length_rem = (FTDF_sdb.buffer[0] + 4) / 4 - 1; /* 1 word we already read */ + + while (word_length_rem--) + { + *dstPtr++ = *txFifoPtr++; + } + + FTDF_sdb.metadata0 = *FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_0, + FTDF_TX_DATA_BUFFER); + FTDF_sdb.metadata1 = *FTDF_GET_REG_ADDR_INDEXED(RETENTION_RAM_TX_META_DATA_1, + FTDF_TX_DATA_BUFFER); + FTDF_sdb.phyCsmaCaAttr = FTDF_GET_FIELD(ON_OFF_REGMAP_PHYCSMACAATTR); +} + +static inline void FTDF_sdbResume(void) +{ + volatile uint32_t *txFifoPtr = FTDF_GET_REG_ADDR(RETENTION_RAM_TX_FIFO); + volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET); + uint32_t *srcPtr = (uint32_t *) FTDF_sdb.buffer; + + uint8_t word_length_rem; + + FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_NB_VAL, FTDF_sdb.nrOfBackoffs); + + FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_RESUME_SET, 1); + + ASSERT_WARNING((FTDF_sdb.buffer[0] >= 3) && (FTDF_sdb.buffer[0] < FTDF_BUFFER_LENGTH)); + + /* The length is the buffer length excluding the length byte itself */ + word_length_rem = (FTDF_sdb.buffer[0] + 4) / 4; + + while (word_length_rem--) + { + *txFifoPtr++ = *srcPtr++; + } + + FTDF_SET_FIELD(ON_OFF_REGMAP_PHYCSMACAATTR, FTDF_sdb.phyCsmaCaAttr); + + *FTDF_GET_REG_ADDR(RETENTION_RAM_TX_META_DATA_0) = FTDF_sdb.metadata0; + + *FTDF_GET_REG_ADDR(RETENTION_RAM_TX_META_DATA_1) = FTDF_sdb.metadata1; + + *txFlagSet |= (1 << FTDF_TX_DATA_BUFFER); +} + +static inline void FTDF_sdbReset(void) +{ + FTDF_SET_FIELD(ON_OFF_REGMAP_CSMA_CA_RESUME_CLEAR, 1); +} + +static inline void FTDF_sdbSetCCARetryTime(void) +{ + FTDF_Time timestamp = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); + FTDF_Time boStat = FTDF_GET_FIELD(ON_OFF_REGMAP_CSMA_CA_BO_STAT) * + FTDF_UNIT_BACKOFF_PERIOD; + FTDF_sdb.ccaRetryTime = timestamp + boStat; +} + +void FTDF_sdbFsmReset(void) +{ + FTDF_sdbReset(); + FTDF_sdb.state = FTDF_SDB_STATE_INIT; +} + +void FTDF_sdbFsmBackoffIRQ(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + + if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) + { + return; + } + +#endif + + switch (FTDF_sdb.state) + { + case FTDF_SDB_STATE_RESUMING: + FTDF_sdbReset(); + + case FTDF_SDB_STATE_INIT: + case FTDF_SDB_STATE_BACKING_OFF: + FTDF_sdbSetCCARetryTime(); + FTDF_sdb.state = FTDF_SDB_STATE_BACKING_OFF; + break; + + default: + ASSERT_WARNING(0); + } +} + +void FTDF_sdbFsmSleep(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + + if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) + { + return; + } + +#endif + + switch (FTDF_sdb.state) + { + case FTDF_SDB_STATE_BACKING_OFF: + FTDF_sdbSaveState(); + FTDF_sdb.state = FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ; + break; + + case FTDF_SDB_STATE_INIT: + break; + + default: + ASSERT_WARNING(0); + } +} + +void FTDF_sdbFsmAbortSleep(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + + if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) + { + return; + } + +#endif + + switch (FTDF_sdb.state) + { + case FTDF_SDB_STATE_BACKING_OFF: + FTDF_sdb.state = FTDF_SDB_STATE_INIT; + break; + + case FTDF_SDB_STATE_INIT: + case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: + case FTDF_SDB_STATE_RESUMING: + break; + + default: + ASSERT_WARNING(0); + } +} + +void FTDF_sdbFsmWakeUpIRQ(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + + if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) + { + return; + } + +#endif + + switch (FTDF_sdb.state) + { + case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: + FTDF_sdb.state = FTDF_SDB_STATE_RESUMING; + break; + + case FTDF_SDB_STATE_INIT: + break; + + default: + ASSERT_WARNING(0); + } +} + +void FTDF_sdbFsmWakeUp(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + + if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) + { + return; + } + +#endif + + switch (FTDF_sdb.state) + { + case FTDF_SDB_STATE_RESUMING: + FTDF_sdbResume(); + break; + + case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: + break; + + case FTDF_SDB_STATE_INIT: + break; + + default: + ASSERT_WARNING(0); + } +} + +void FTDF_sdbFsmTxIRQ(void) +{ +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + + if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) + { + return; + } + +#endif + + switch (FTDF_sdb.state) + { + case FTDF_SDB_STATE_RESUMING: + FTDF_sdbReset(); + FTDF_sdb.state = FTDF_SDB_STATE_INIT; + break; + + case FTDF_SDB_STATE_BACKING_OFF: + FTDF_sdb.state = FTDF_SDB_STATE_INIT; + break; + + case FTDF_SDB_STATE_INIT: + break; + + default: + ASSERT_WARNING(0); + } +} + +FTDF_USec FTDF_sdbGetSleepTime(void) +{ + FTDF_USec sleepTime = ~((FTDF_USec) 0); +#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH) + + if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) + { + return sleepTime; + } + +#endif + + switch (FTDF_sdb.state) + { + case FTDF_SDB_STATE_INIT: + { + if ((FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0) || FTDF_reqCurrent) + { + sleepTime = 0; + } + else + { + sleepTime = ~((FTDF_USec) 0); + } + + break; + } + + case FTDF_SDB_STATE_BACKING_OFF: + { + FTDF_Time currentTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); + + if (currentTime <= FTDF_sdb.ccaRetryTime) + { + sleepTime = (FTDF_sdb.ccaRetryTime - currentTime) * 16; + } + else + { + sleepTime = (1 << SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL - 1) - + (currentTime + FTDF_sdb.ccaRetryTime) * 16; + } + + if (sleepTime > 256 * FTDF_UNIT_BACKOFF_PERIOD * 16) + { + /* We have exceeded the CCA retry time. Abort sleep and wait for Tx IRQ. */ + sleepTime = 0; + } + + break; + } + + case FTDF_SDB_STATE_RESUMING: + sleepTime = 0; + break; + + case FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ: + sleepTime = ~((FTDF_USec) 0); + break; + + default: + ASSERT_WARNING(0); + } + + return sleepTime; +} + +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ + +#endif /* #if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ + +#if dg_configUSE_FTDF_DDPHY == 1 +void FTDF_ddphySet(uint16_t ccaReg) +{ + FTDF_criticalVar(); + FTDF_enterCritical(); + /* We use the critical section here as protection for the global variable and the HW sleep + * state. */ + FTDF_ddphyCcaReg = ccaReg; + + /* Apply immediately if block is up. */ + if (REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0) + { + FTDF_DPHY->DDPHY_CCA_REG = FTDF_ddphyCcaReg; + } + + FTDF_exitCritical(); +} + +void FTDF_ddphyRestore(void) +{ + if (FTDF_ddphyCcaReg) + { + /* Apply immediately if block is up. */ + FTDF_criticalVar(); + FTDF_enterCritical(); + ASSERT_WARNING(REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0); + FTDF_DPHY->DDPHY_CCA_REG = FTDF_ddphyCcaReg; + FTDF_exitCritical(); + } +} + +void FTDF_ddphySave(void) +{ + /* Apply immediately if block is up. */ + FTDF_criticalVar(); + FTDF_enterCritical(); + ASSERT_WARNING(REG_GETF(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP) == 0x0); + FTDF_ddphyCcaReg = FTDF_DPHY->DDPHY_CCA_REG; + FTDF_exitCritical(); +} +#endif diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c index 9d8a76e1f..3c638dad3 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c @@ -29,6 +29,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -128,7 +129,7 @@ void FTDF_processDataRequest(FTDF_DataRequest *dataRequest) if (status != FTDF_SUCCESS) { - // Queueing of indirect transfer was successful + // Queueing of indirect transfer was not successful FTDF_sendDataConfirm(dataRequest, status, 0, @@ -139,6 +140,30 @@ void FTDF_processDataRequest(FTDF_DataRequest *dataRequest) return; } +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO + uint8_t entry, shortAddrIdx; + + if (dstAddrMode == FTDF_SHORT_ADDRESS) + { + if (FTDF_fpprGetFreeShortAddress(&entry, &shortAddrIdx) == FTDF_FALSE) + { + goto transaction_overflow; + } + } + else if (dstAddrMode == FTDF_EXTENDED_ADDRESS) + { + if (FTDF_fpprGetFreeExtAddress(&entry) == FTDF_FALSE) + { + goto transaction_overflow; + } + } + else + { + status = FTDF_INVALID_PARAMETER; + } + +#endif + // Search for an empty indirect queue for (queue = 0; queue < FTDF_NR_OF_REQ_BUFFERS; queue++) { @@ -153,6 +178,24 @@ void FTDF_processDataRequest(FTDF_DataRequest *dataRequest) if (status == FTDF_SUCCESS) { +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO + + if (dstAddrMode == FTDF_SHORT_ADDRESS) + { + FTDF_fpprSetShortAddress(entry, shortAddrIdx, dstAddr.shortAddress); + FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_TRUE); + } + else if (dstAddrMode == FTDF_EXTENDED_ADDRESS) + { + FTDF_fpprSetExtAddress(entry, dstAddr.shortAddress); + FTDF_fpprSetExtAddressValid(entry, FTDF_TRUE); + } + else + { + ASSERT_WARNING(0); + } + +#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ FTDF_addTxPendingTimer((FTDF_MsgBuffer *) dataRequest, queue, FTDF_pib.transactionPersistenceTime * FTDF_BASE_SUPERFRAME_DURATION, @@ -167,6 +210,9 @@ void FTDF_processDataRequest(FTDF_DataRequest *dataRequest) } // Did not find an existing or an empty queue +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO +transaction_overflow: +#endif FTDF_sendDataConfirm(dataRequest, FTDF_TRANSACTION_OVERFLOW, 0, 0, @@ -331,7 +377,9 @@ void FTDF_sendDataConfirm(FTDF_DataRequest *dataRequest, FTDF_REL_MSG_BUFFER((FTDF_MsgBuffer *) dataRequest); FTDF_RCV_MSG((FTDF_MsgBuffer *) dataConfirm); - +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO + FTDF_fpFsmClearPending(); +#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ FTDF_processNextRequest(); } @@ -506,6 +554,31 @@ void FTDF_processPurgeRequest(FTDF_PurgeRequest *purgeRequest) if (dataRequest->indirectTX == FTDF_TRUE) { FTDF_removeTxPendingTimer(request); +#if FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO + + if (FTDF_txPendingList[ n ].addrMode == FTDF_SHORT_ADDRESS) + { + uint8_t entry, shortAddrIdx; + FTDF_Boolean found = FTDF_fpprLookupShortAddress( + FTDF_txPendingList[ n ].addr.shortAddress, &entry, + &shortAddrIdx); + ASSERT_WARNING(found); + FTDF_fpprSetShortAddressValid(entry, shortAddrIdx, FTDF_FALSE); + } + else if (FTDF_txPendingList[ n ].addrMode == FTDF_EXTENDED_ADDRESS) + { + uint8_t entry; + FTDF_Boolean found = FTDF_fpprLookupExtAddress( + FTDF_txPendingList[ n ].addr.extAddress, &entry); + ASSERT_WARNING(found); + FTDF_fpprSetExtAddressValid(entry, FTDF_FALSE); + } + else + { + ASSERT_WARNING(0); + } + +#endif /* FTDF_FP_BIT_MODE == FTDF_FP_BIT_MODE_AUTO */ if (FTDF_isQueueEmpty(&FTDF_txPendingList[ n ].queue)) { diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h b/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h old mode 100755 new mode 100644 index 794c242c5..a9e5d5276 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h @@ -29,6 +29,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -36,7 +37,9 @@ #define FTDF_FCS_LENGTH 2 #define FTDF_BUFFER_LENGTH 128 -#define FTDF_NR_OF_REQ_BUFFERS 16 +#ifndef FTDF_NR_OF_REQ_BUFFERS +#define FTDF_NR_OF_REQ_BUFFERS 96 +#endif #define FTDF_NR_OF_RX_BUFFERS 8 #define FTDF_NR_OF_CHANNELS 16 #define FTDF_NR_OF_SCAN_RESULTS 16 @@ -94,6 +97,14 @@ } \ while ( 0 ) + +#define FTDF_SET_FIELD_INDEXED( fieldName, value, index ) do { \ + uint32_t tmp = *FTDF_GET_FIELD_ADDR_INDEXED( fieldName, index ) & ~MSK_F_FTDF_ ## fieldName; \ + *FTDF_GET_FIELD_ADDR_INDEXED( fieldName, index ) = tmp | \ + ( ( ( value ) << OFF_F_FTDF_ ## fieldName ) & MSK_F_FTDF_ ## fieldName ); \ +} \ + while ( 0 ) + #define FTDF_processRequest FTDF_sndMsg struct FTDF_Pib @@ -219,6 +230,10 @@ struct FTDF_Pib FTDF_Boolean tschCapable; FTDF_Period tsSyncCorrectThreshold; #endif /* !FTDF_LITE */ +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A + FTDF_NrBackoffPeriods boIrqThreshold; + FTDF_PtiConfig ptiConfig; +#endif }; typedef uint8_t FTDF_FrameVersion; @@ -600,6 +615,7 @@ void FTDF_getPANId( void ); void FTDF_setPANId( void ); void FTDF_getCurrentChannel( void ); void FTDF_setCurrentChannel( void ); +void FTDF_setTXPower( void ); void FTDF_getMaxFrameTotalWaitTime( void ); void FTDF_setMaxFrameTotalWaitTime( void ); #ifndef FTDF_NO_CSL @@ -614,6 +630,12 @@ void FTDF_setMaxBE( void ); void FTDF_setMinBE( void ); void FTDF_getKeepPhyEnabled( void ); void FTDF_setKeepPhyEnabled( void ); +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +void FTDF_setBoIrqThreshold( void ); +void FTDF_getBoIrqThreshold( void ); +void FTDF_setPtiConfig( void ); +#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ + #ifndef FTDF_NO_TSCH void FTDF_setTimeslotTemplate( void ); #endif /* FTDF_NO_TSCH */ @@ -639,6 +661,9 @@ void FTDF_processKeepAliveTimerExp( FTDF_PendingTL* ptr ); void FTDF_resetKeepAliveTimer( FTDF_ShortAddress dstAddr ); #endif /* FTDF_NO_TSCH */ +void FTDF_processTxPending(FTDF_FrameHeader* frameHeader, + FTDF_SecurityHeader* securityHeader ); + void FTDF_processCommandFrame( FTDF_Octet* rxBuffer, FTDF_FrameHeader* frameHeader, FTDF_SecurityHeader* securityHeader, @@ -671,3 +696,49 @@ FTDF_SN FTDF_processTschSN( FTDF_MsgBuffer* msg, FTDF_SN sn, uint8_t* FTDF_Time64 FTDF_getCurTime64( void ); void FTDF_initCurTime64( void ); + +#if FTDF_USE_SLEEP_DURING_BACKOFF +typedef enum +{ + FTDF_SDB_STATE_INIT = 0, + FTDF_SDB_STATE_BACKING_OFF, + FTDF_SDB_STATE_WAITING_WAKE_UP_IRQ, + FTDF_SDB_STATE_RESUMING, +} FTDF_SdbState; + +typedef struct +{ + FTDF_SdbState state; + FTDF_Size nrOfBackoffs; + FTDF_Time ccaRetryTime; + FTDF_Octet buffer[FTDF_BUFFER_LENGTH]; + uint32_t metadata0; + uint32_t metadata1; + uint32_t phyCsmaCaAttr; +} FTDF_Sdb; + +void FTDF_sdbFsmReset(void); + +void FTDF_sdbFsmBackoffIRQ(void); + +void FTDF_sdbFsmSleep(void); + +void FTDF_sdbFsmAbortSleep(void); + +void FTDF_sdbFsmWakeUpIRQ(void); + +void FTDF_sdbFsmWakeUp(void); + +void FTDF_sdbFsmTxIRQ(void); + +FTDF_USec FTDF_sdbGetSleepTime(void); + +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ + +#if dg_configUSE_FTDF_DDPHY == 1 + +void FTDF_ddphyRestore(void); + +void FTDF_ddphySave(void); + +#endif diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c index 5a7e5fb8d..f869f9183 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c @@ -29,6 +29,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * + * **************************************************************************************** */ @@ -282,6 +283,15 @@ void FTDF_sndMsg(FTDF_MsgBuffer *msgBuf) FTDF_REL_MSG_BUFFER(msgBuf); break; #endif /* FTDF_DBG_BUS_ENABLE */ +#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A + + case FTDF_FPPR_MODE_SET_REQUEST: + FTDF_fpprSetMode(((FTDF_FpprModeSetRequest *) msgBuf)->matchFp, + ((FTDF_FpprModeSetRequest *) msgBuf)->fpOverride, + ((FTDF_FpprModeSetRequest *) msgBuf)->fpForce); + FTDF_REL_MSG_BUFFER(msgBuf); + break; +#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */ default: // Silenty release the message buffer diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c b/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c index bce829a39..f93cf972c 100644 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c @@ -79,16 +79,24 @@ FTDF_USec FTDF_canSleep(void) } #else +#if FTDF_USE_SLEEP_DURING_BACKOFF + if (FTDF_pib.keepPhyEnabled) +#else if (FTDF_reqCurrent || FTDF_pib.keepPhyEnabled) +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ { return 0; } #endif +#if FTDF_USE_SLEEP_DURING_BACKOFF + if (FTDF_GET_FIELD(ON_OFF_REGMAP_SECBUSY) == 1) +#else /* FTDF_USE_SLEEP_DURING_BACKOFF */ if (FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0 || FTDF_GET_FIELD(ON_OFF_REGMAP_SECBUSY) == 1) +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ { return 0; } @@ -97,6 +105,16 @@ FTDF_USec FTDF_canSleep(void) if (FTDF_pib.leEnabled) { +#if FTDF_USE_SLEEP_DURING_BACKOFF + + /* Abort sleep when LMAC is busy. */ + if (FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0) + { + return 0; + } + +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ + if (FTDF_txInProgress == FTDF_FALSE) { FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL); @@ -123,6 +141,15 @@ FTDF_USec FTDF_canSleep(void) if (FTDF_pib.tschEnabled) { +#if FTDF_USE_SLEEP_DURING_BACKOFF + + /* Abort sleep when LMAC is busy. */ + if (FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0) + { + return 0; + } + +#endif FTDF_Time64 curTime64 = FTDF_getCurTime64(); FTDF_Time64 delta = curTime64 - FTDF_tschSlotTime; @@ -179,7 +206,12 @@ FTDF_USec FTDF_canSleep(void) } #endif /* !FTDF_LITE */ +#if FTDF_USE_SLEEP_DURING_BACKOFF + return FTDF_sdbGetSleepTime(); +#else /* FTDF_USE_SLEEP_DURING_BACKOFF */ return 0xffffffff; +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ + } FTDF_Boolean FTDF_prepareForSleep(FTDF_USec sleepTime) @@ -235,6 +267,10 @@ FTDF_Boolean FTDF_prepareForSleep(FTDF_USec sleepTime) *getGeneratorValE = MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E; #endif uint64_t nextWakeUpThr; +#if FTDF_USE_SLEEP_DURING_BACKOFF + uint64_t picoSleepTime = (uint64_t)sleepTime * 1000000; + nextWakeUpThr = (picoSleepTime - FTDF_wakeUpLatency) / FTDF_lowPowerClockCycle; +#else /* FTDF_USE_SLEEP_DURING_BACKOFF */ if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled) { @@ -246,9 +282,11 @@ FTDF_Boolean FTDF_prepareForSleep(FTDF_USec sleepTime) nextWakeUpThr = FTDF_csmacaWakeupThr; } +#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */ + // Set wake up threshold uint32_t wakeUpIntThr = FTDF_eventCurrVal + nextWakeUpThr; - + // Note that for IC revs other than A the size of WAKEUPINTTHR is 25 bits. FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPINTTHR, wakeUpIntThr); FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPENABLE, 1); #endif @@ -285,7 +323,21 @@ void FTDF_wakeUp(void) #endif // Backward calculate the time slept - FTDF_PSec sleepTime = ((uint64_t)(eventNewCurrVal - FTDF_eventCurrVal) * FTDF_lowPowerClockCycle) + FTDF_wakeUpLatency; + //FTDF_PSec sleepTime = ( (uint64_t)( eventNewCurrVal - FTDF_eventCurrVal ) * FTDF_lowPowerClockCycle ) + FTDF_wakeUpLatency; + + FTDF_PSec sleepTime; + + if (eventNewCurrVal >= FTDF_eventCurrVal) /* Check for wraps. */ + { + sleepTime = (eventNewCurrVal - FTDF_eventCurrVal) * FTDF_lowPowerClockCycle + + FTDF_wakeUpLatency; + } + else + { + sleepTime = (eventNewCurrVal + + (MSK_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL - FTDF_eventCurrVal)) * + FTDF_lowPowerClockCycle + FTDF_wakeUpLatency; + } // Calculate sync values uint64_t newSyncVals = ((uint64_t)FTDF_timeStampCurrVal << 8) | (FTDF_timeStampCurrPhaseVal & 0xff); diff --git a/third_party/dialog/DialogSDK/interfaces/ftdf/src/regmap.h b/third_party/dialog/DialogSDK/interfaces/ftdf/src/regmap.h old mode 100755 new mode 100644 index 7ddc8344b..5e4503f81 --- a/third_party/dialog/DialogSDK/interfaces/ftdf/src/regmap.h +++ b/third_party/dialog/DialogSDK/interfaces/ftdf/src/regmap.h @@ -6,9 +6,15 @@ #ifndef _ftdf #define _ftdf +#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A /* * * REGISTER: ftdf_retention_ram_tx_fifo + * + * Initialization value: none. + * Access mode: C-RW (control - read/write) + ************************************************************************************ + * * Copyright (c) 2016, Dialog Semiconductor * All rights reserved. * Redistribution and use in source and binary forms, with or without modification, @@ -32,9 +38,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Initialization value: none. - * Access mode: C-RW (control - read/write) + * + **************************************************************************************** */ #define IND_R_FTDF_RETENTION_RAM_TX_FIFO 0x40080000 #define SIZE_R_FTDF_RETENTION_RAM_TX_FIFO 0x4 @@ -4100,4 +4105,4505 @@ #define MSK_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE 0x1 #define OFF_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE 0 #define SIZE_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPTIMERENABLE 1 +#else // dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A +/* + * + * REGISTER: ftdf_retention_ram_tx_fifo + * + * Initialization value: none. + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_RETENTION_RAM_TX_FIFO 0x40080000 +#define SIZE_R_FTDF_RETENTION_RAM_TX_FIFO 0x4 +#define MSK_R_FTDF_RETENTION_RAM_TX_FIFO 0xffffffff +#define FTDF_RETENTION_RAM_TX_FIFO_NUM_1D 0x4 +#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_1D 0x80 +#define FTDF_RETENTION_RAM_TX_FIFO_NUM_2D 0x20 +#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_2D 0x4 +#define FTDF_RETENTION_RAM_TX_FIFO_NUM_1D 0x4 +#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_1D 0x80 +#define FTDF_RETENTION_RAM_TX_FIFO_NUM_2D 0x20 +#define FTDF_RETENTION_RAM_TX_FIFO_INTVL_2D 0x4 + +/* + * + * Field: ftdf_retention_ram_tx_fifo + * + * Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. + * Note that, despite the name, this fifo is NOT retained when the LMAC is put into deep-sleep! + */ +#define IND_F_FTDF_RETENTION_RAM_TX_FIFO IND_R_FTDF_RETENTION_RAM_TX_FIFO +#define MSK_F_FTDF_RETENTION_RAM_TX_FIFO 0xffffffff +#define OFF_F_FTDF_RETENTION_RAM_TX_FIFO 0 +#define SIZE_F_FTDF_RETENTION_RAM_TX_FIFO 32 + +/* + * + * REGISTER: ftdf_retention_ram_tx_meta_data_0 + * + * Initialization value: none. + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 0x40080200 +#define SIZE_R_FTDF_RETENTION_RAM_TX_META_DATA_0 0x4 +#define MSK_R_FTDF_RETENTION_RAM_TX_META_DATA_0 0x57ffffff +#define FTDF_RETENTION_RAM_TX_META_DATA_0_NUM 0x4 +#define FTDF_RETENTION_RAM_TX_META_DATA_0_INTVL 0x10 +#define FTDF_RETENTION_RAM_FRAME_LENGTH_NUM 0x4 +#define FTDF_RETENTION_RAM_FRAME_LENGTH_INTVL 0x10 +#define FTDF_RETENTION_RAM_PHYATTR_NUM 0x4 +#define FTDF_RETENTION_RAM_PHYATTR_INTVL 0x10 +#define FTDF_RETENTION_RAM_FRAMETYPE_NUM 0x4 +#define FTDF_RETENTION_RAM_FRAMETYPE_INTVL 0x10 +#define FTDF_RETENTION_RAM_CSMACA_ENA_NUM 0x4 +#define FTDF_RETENTION_RAM_CSMACA_ENA_INTVL 0x10 +#define FTDF_RETENTION_RAM_ACKREQUEST_NUM 0x4 +#define FTDF_RETENTION_RAM_ACKREQUEST_INTVL 0x10 +#define FTDF_RETENTION_RAM_CRC16_ENA_NUM 0x4 +#define FTDF_RETENTION_RAM_CRC16_ENA_INTVL 0x10 + +/* + * + * Field: ftdf_retention_ram_frame_length + * + * Tx meta data per entry: Frame length (in bytes) + */ +#define IND_F_FTDF_RETENTION_RAM_FRAME_LENGTH IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 +#define MSK_F_FTDF_RETENTION_RAM_FRAME_LENGTH 0x7f +#define OFF_F_FTDF_RETENTION_RAM_FRAME_LENGTH 0 +#define SIZE_F_FTDF_RETENTION_RAM_FRAME_LENGTH 7 +/* + * + * Field: ftdf_retention_ram_phyAttr + * + * Tx meta data per entry: during the Tx-on phase, the control register phyRxAttr[16] sources the PHYATTR output signal to the DPHY. + */ +#define IND_F_FTDF_RETENTION_RAM_PHYATTR IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 +#define MSK_F_FTDF_RETENTION_RAM_PHYATTR 0x7fff80 +#define OFF_F_FTDF_RETENTION_RAM_PHYATTR 7 +#define SIZE_F_FTDF_RETENTION_RAM_PHYATTR 16 +/* + * + * Field: ftdf_retention_ram_frametype + * + * Tx meta data per entry: the frame type of the data to be transmitted (Data/Cmd/Ack/wakeup frame/etc.). + */ +#define IND_F_FTDF_RETENTION_RAM_FRAMETYPE IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 +#define MSK_F_FTDF_RETENTION_RAM_FRAMETYPE 0x3800000 +#define OFF_F_FTDF_RETENTION_RAM_FRAMETYPE 23 +#define SIZE_F_FTDF_RETENTION_RAM_FRAMETYPE 3 +/* + * + * Bit: ftdf_retention_ram_CsmaCa_ena + * + * Tx meta data per entry: '1' indicates that a CSMA-CA is required for the transmission of this packet. + */ +#define IND_F_FTDF_RETENTION_RAM_CSMACA_ENA IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 +#define MSK_F_FTDF_RETENTION_RAM_CSMACA_ENA 0x4000000 +#define OFF_F_FTDF_RETENTION_RAM_CSMACA_ENA 26 +#define SIZE_F_FTDF_RETENTION_RAM_CSMACA_ENA 1 +/* + * + * Bit: ftdf_retention_ram_AckRequest + * + * Tx meta data per entry: '1' indicates that an acknowledge is expected from the recipient of this packet. + */ +#define IND_F_FTDF_RETENTION_RAM_ACKREQUEST IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 +#define MSK_F_FTDF_RETENTION_RAM_ACKREQUEST 0x10000000 +#define OFF_F_FTDF_RETENTION_RAM_ACKREQUEST 28 +#define SIZE_F_FTDF_RETENTION_RAM_ACKREQUEST 1 +/* + * + * Bit: ftdf_retention_ram_CRC16_ena + * + * Tx meta data per entry: Indicates whether CRC16 insertion must be enabled or not. + * 0 : No hardware inserted CRC16 + * 1 : Hardware inserts CRC16 + */ +#define IND_F_FTDF_RETENTION_RAM_CRC16_ENA IND_R_FTDF_RETENTION_RAM_TX_META_DATA_0 +#define MSK_F_FTDF_RETENTION_RAM_CRC16_ENA 0x40000000 +#define OFF_F_FTDF_RETENTION_RAM_CRC16_ENA 30 +#define SIZE_F_FTDF_RETENTION_RAM_CRC16_ENA 1 + +/* + * + * REGISTER: ftdf_retention_ram_tx_meta_data_1 + * + * Initialization value: none. + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_RETENTION_RAM_TX_META_DATA_1 0x40080204 +#define SIZE_R_FTDF_RETENTION_RAM_TX_META_DATA_1 0x4 +#define MSK_R_FTDF_RETENTION_RAM_TX_META_DATA_1 0xff +#define FTDF_RETENTION_RAM_TX_META_DATA_1_NUM 0x4 +#define FTDF_RETENTION_RAM_TX_META_DATA_1_INTVL 0x10 +#define FTDF_RETENTION_RAM_MACSN_NUM 0x4 +#define FTDF_RETENTION_RAM_MACSN_INTVL 0x10 + +/* + * + * Field: ftdf_retention_ram_macSN + * + * Tx meta data per entry: Sequence Number of this packet. + */ +#define IND_F_FTDF_RETENTION_RAM_MACSN IND_R_FTDF_RETENTION_RAM_TX_META_DATA_1 +#define MSK_F_FTDF_RETENTION_RAM_MACSN 0xff +#define OFF_F_FTDF_RETENTION_RAM_MACSN 0 +#define SIZE_F_FTDF_RETENTION_RAM_MACSN 8 + +/* + * + * REGISTER: ftdf_retention_ram_tx_return_status_0 + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 0x40080240 +#define SIZE_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 0x4 +#define MSK_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 0xffffffff +#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_0_NUM 0x4 +#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_0_INTVL 0x10 +#define FTDF_RETENTION_RAM_TXTIMESTAMP_NUM 0x4 +#define FTDF_RETENTION_RAM_TXTIMESTAMP_INTVL 0x10 + +/* + * + * Field: ftdf_retention_ram_TxTimestamp + * + * Tx return status per entry: Transmit Timestamp + * The Timestamp of the transmitted packet. + */ +#define IND_F_FTDF_RETENTION_RAM_TXTIMESTAMP IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_0 +#define MSK_F_FTDF_RETENTION_RAM_TXTIMESTAMP 0xffffffff +#define OFF_F_FTDF_RETENTION_RAM_TXTIMESTAMP 0 +#define SIZE_F_FTDF_RETENTION_RAM_TXTIMESTAMP 32 + +/* + * + * REGISTER: ftdf_retention_ram_tx_return_status_1 + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 0x40080244 +#define SIZE_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 0x4 +#define MSK_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 0x1f +#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_1_NUM 0x4 +#define FTDF_RETENTION_RAM_TX_RETURN_STATUS_1_INTVL 0x10 +#define FTDF_RETENTION_RAM_ACKFAIL_NUM 0x4 +#define FTDF_RETENTION_RAM_ACKFAIL_INTVL 0x10 +#define FTDF_RETENTION_RAM_CSMACAFAIL_NUM 0x4 +#define FTDF_RETENTION_RAM_CSMACAFAIL_INTVL 0x10 +#define FTDF_RETENTION_RAM_CSMACANRRETRIES_NUM 0x4 +#define FTDF_RETENTION_RAM_CSMACANRRETRIES_INTVL 0x10 + +/* + * + * Bit: ftdf_retention_ram_AckFail + * + * Tx return status per entry: Acknowledgement status + * 0 : SUCCESS + * 1 : FAIL + */ +#define IND_F_FTDF_RETENTION_RAM_ACKFAIL IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 +#define MSK_F_FTDF_RETENTION_RAM_ACKFAIL 0x1 +#define OFF_F_FTDF_RETENTION_RAM_ACKFAIL 0 +#define SIZE_F_FTDF_RETENTION_RAM_ACKFAIL 1 +/* + * + * Bit: ftdf_retention_ram_CsmaCaFail + * + * Tx return status per entry: CSMA-CA status + * 0 : SUCCESS + * 1 : FAIL + */ +#define IND_F_FTDF_RETENTION_RAM_CSMACAFAIL IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 +#define MSK_F_FTDF_RETENTION_RAM_CSMACAFAIL 0x2 +#define OFF_F_FTDF_RETENTION_RAM_CSMACAFAIL 1 +#define SIZE_F_FTDF_RETENTION_RAM_CSMACAFAIL 1 +/* + * + * Field: ftdf_retention_ram_CsmaCaNrRetries + * + * Tx return status per entry: Number of CSMA-CA retries before this frame has been transmitted + */ +#define IND_F_FTDF_RETENTION_RAM_CSMACANRRETRIES IND_R_FTDF_RETENTION_RAM_TX_RETURN_STATUS_1 +#define MSK_F_FTDF_RETENTION_RAM_CSMACANRRETRIES 0x1c +#define OFF_F_FTDF_RETENTION_RAM_CSMACANRRETRIES 2 +#define SIZE_F_FTDF_RETENTION_RAM_CSMACANRRETRIES 3 + +/* + * + * REGISTER: ftdf_retention_ram_rx_meta_0 + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_RETENTION_RAM_RX_META_0 0x40080280 +#define SIZE_R_FTDF_RETENTION_RAM_RX_META_0 0x4 +#define MSK_R_FTDF_RETENTION_RAM_RX_META_0 0xffffffff +#define FTDF_RETENTION_RAM_RX_META_0_NUM 0x8 +#define FTDF_RETENTION_RAM_RX_META_0_INTVL 0x10 +#define FTDF_RETENTION_RAM_RX_TIMESTAMP_NUM 0x8 +#define FTDF_RETENTION_RAM_RX_TIMESTAMP_INTVL 0x10 + +/* + * + * Field: ftdf_retention_ram_rx_timestamp + * + * Rx meta data per entry: Timestamp taken when frame was received + */ +#define IND_F_FTDF_RETENTION_RAM_RX_TIMESTAMP IND_R_FTDF_RETENTION_RAM_RX_META_0 +#define MSK_F_FTDF_RETENTION_RAM_RX_TIMESTAMP 0xffffffff +#define OFF_F_FTDF_RETENTION_RAM_RX_TIMESTAMP 0 +#define SIZE_F_FTDF_RETENTION_RAM_RX_TIMESTAMP 32 + +/* + * + * REGISTER: ftdf_retention_ram_rx_meta_1 + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_RETENTION_RAM_RX_META_1 0x40080284 +#define SIZE_R_FTDF_RETENTION_RAM_RX_META_1 0x4 +#define MSK_R_FTDF_RETENTION_RAM_RX_META_1 0xfffd +#define FTDF_RETENTION_RAM_RX_META_1_NUM 0x8 +#define FTDF_RETENTION_RAM_RX_META_1_INTVL 0x10 +#define FTDF_RETENTION_RAM_CRC16_ERROR_NUM 0x8 +#define FTDF_RETENTION_RAM_CRC16_ERROR_INTVL 0x10 +#define FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR_NUM 0x8 +#define FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR_INTVL 0x10 +#define FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR_NUM 0x8 +#define FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR_INTVL 0x10 +#define FTDF_RETENTION_RAM_DPANID_ERROR_NUM 0x8 +#define FTDF_RETENTION_RAM_DPANID_ERROR_INTVL 0x10 +#define FTDF_RETENTION_RAM_DADDR_ERROR_NUM 0x8 +#define FTDF_RETENTION_RAM_DADDR_ERROR_INTVL 0x10 +#define FTDF_RETENTION_RAM_SPANID_ERROR_NUM 0x8 +#define FTDF_RETENTION_RAM_SPANID_ERROR_INTVL 0x10 +#define FTDF_RETENTION_RAM_ISPANID_COORD_ERROR_NUM 0x8 +#define FTDF_RETENTION_RAM_ISPANID_COORD_ERROR_INTVL 0x10 +#define FTDF_RETENTION_RAM_QUALITY_INDICATOR_NUM 0x8 +#define FTDF_RETENTION_RAM_QUALITY_INDICATOR_INTVL 0x10 + +/* + * + * Bit: ftdf_retention_ram_crc16_error + * + * Rx meta data per entry: if set, a CRC error has occurred in this frame, applicable for transparent mode only + */ +#define IND_F_FTDF_RETENTION_RAM_CRC16_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 +#define MSK_F_FTDF_RETENTION_RAM_CRC16_ERROR 0x1 +#define OFF_F_FTDF_RETENTION_RAM_CRC16_ERROR 0 +#define SIZE_F_FTDF_RETENTION_RAM_CRC16_ERROR 1 +/* + * + * Bit: ftdf_retention_ram_res_frm_type_error + * + * Rx meta data per entry: if set to '1' this frame is a not supported frame type, applicable when frame is not discarded + */ +#define IND_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 +#define MSK_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR 0x4 +#define OFF_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR 2 +#define SIZE_F_FTDF_RETENTION_RAM_RES_FRM_TYPE_ERROR 1 +/* + * + * Bit: ftdf_retention_ram_res_frm_version_error + * + * Rx meta data per entry: if set to '1' this frame is a not supported frame version, applicable when frame is not discarded. + */ +#define IND_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 +#define MSK_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR 0x8 +#define OFF_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR 3 +#define SIZE_F_FTDF_RETENTION_RAM_RES_FRM_VERSION_ERROR 1 +/* + * + * Bit: ftdf_retention_ram_dpanid_error + * + * Rx meta data per entry: if set to '1', a destination PAN ID error has occurred, applicable when frame is not discarded + */ +#define IND_F_FTDF_RETENTION_RAM_DPANID_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 +#define MSK_F_FTDF_RETENTION_RAM_DPANID_ERROR 0x10 +#define OFF_F_FTDF_RETENTION_RAM_DPANID_ERROR 4 +#define SIZE_F_FTDF_RETENTION_RAM_DPANID_ERROR 1 +/* + * + * Bit: ftdf_retention_ram_daddr_error + * + * Rx meta data per entry: if set to '1', a destination Address error has occurred, applicable when frame is not discarded + */ +#define IND_F_FTDF_RETENTION_RAM_DADDR_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 +#define MSK_F_FTDF_RETENTION_RAM_DADDR_ERROR 0x20 +#define OFF_F_FTDF_RETENTION_RAM_DADDR_ERROR 5 +#define SIZE_F_FTDF_RETENTION_RAM_DADDR_ERROR 1 +/* + * + * Bit: ftdf_retention_ram_spanid_error + * + * Rx meta data per entry: if set to '1', a PAN ID error has occurred, applicable when frame is not discarded + */ +#define IND_F_FTDF_RETENTION_RAM_SPANID_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 +#define MSK_F_FTDF_RETENTION_RAM_SPANID_ERROR 0x40 +#define OFF_F_FTDF_RETENTION_RAM_SPANID_ERROR 6 +#define SIZE_F_FTDF_RETENTION_RAM_SPANID_ERROR 1 +/* + * + * Bit: ftdf_retention_ram_ispanid_coord_error + * + * Rx meta data per entry: if set to '1', the received frame is not for PAN coordinator, applicable when frame is not discarded + */ +#define IND_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR IND_R_FTDF_RETENTION_RAM_RX_META_1 +#define MSK_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR 0x80 +#define OFF_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR 7 +#define SIZE_F_FTDF_RETENTION_RAM_ISPANID_COORD_ERROR 1 +/* + * + * Field: ftdf_retention_ram_quality_indicator + * + * Rx meta data per entry: the Link Quality Indication value during reception of this frame. + * + * # $software_scratch@retention_ram + * # TX ram not used by hardware, can be used by software as scratch ram with retention. + */ +#define IND_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR IND_R_FTDF_RETENTION_RAM_RX_META_1 +#define MSK_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR 0xff00 +#define OFF_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR 8 +#define SIZE_F_FTDF_RETENTION_RAM_QUALITY_INDICATOR 8 + +/* + * + * REGISTER: ftdf_rx_ram_rx_fifo + * + * Initialization value: none. + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_RX_RAM_RX_FIFO 0x40088000 +#define SIZE_R_FTDF_RX_RAM_RX_FIFO 0x4 +#define MSK_R_FTDF_RX_RAM_RX_FIFO 0xffffffff +#define FTDF_RX_RAM_RX_FIFO_NUM_1D 0x8 +#define FTDF_RX_RAM_RX_FIFO_INTVL_1D 0x80 +#define FTDF_RX_RAM_RX_FIFO_NUM_2D 0x20 +#define FTDF_RX_RAM_RX_FIFO_INTVL_2D 0x4 +#define FTDF_RX_RAM_RX_FIFO_NUM_1D 0x8 +#define FTDF_RX_RAM_RX_FIFO_INTVL_1D 0x80 +#define FTDF_RX_RAM_RX_FIFO_NUM_2D 0x20 +#define FTDF_RX_RAM_RX_FIFO_INTVL_2D 0x4 + +/* + * + * Field: ftdf_rx_ram_rx_fifo + * + * Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. + */ +#define IND_F_FTDF_RX_RAM_RX_FIFO IND_R_FTDF_RX_RAM_RX_FIFO +#define MSK_F_FTDF_RX_RAM_RX_FIFO 0xffffffff +#define OFF_F_FTDF_RX_RAM_RX_FIFO 0 +#define SIZE_F_FTDF_RX_RAM_RX_FIFO 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_Rel_Name + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_REL_NAME 0x40090000 +#define SIZE_R_FTDF_ON_OFF_REGMAP_REL_NAME 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_REL_NAME 0xffffffff +#define FTDF_ON_OFF_REGMAP_REL_NAME_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_REL_NAME_INTVL 0x4 +#define FTDF_ON_OFF_REGMAP_REL_NAME_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_REL_NAME_INTVL 0x4 + +/* + * + * Field: ftdf_on_off_regmap_Rel_Name + * + * A 4 words wide register, showing in ASCII the name of the release, eg. "ftdf_107". + */ +#define IND_F_FTDF_ON_OFF_REGMAP_REL_NAME IND_R_FTDF_ON_OFF_REGMAP_REL_NAME +#define MSK_F_FTDF_ON_OFF_REGMAP_REL_NAME 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_REL_NAME 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_REL_NAME 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_BuildTime + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_BUILDTIME 0x40090010 +#define SIZE_R_FTDF_ON_OFF_REGMAP_BUILDTIME 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_BUILDTIME 0xffffffff +#define FTDF_ON_OFF_REGMAP_BUILDTIME_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_BUILDTIME_INTVL 0x4 +#define FTDF_ON_OFF_REGMAP_BUILDTIME_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_BUILDTIME_INTVL 0x4 + +/* + * + * Field: ftdf_on_off_regmap_BuildTime + * + * A 4 words wide register, showing in ASCII the build date (dd mmm yy) and time (hh:mm) of device, eg. "01 Dec 14 14:10 ". + */ +#define IND_F_FTDF_ON_OFF_REGMAP_BUILDTIME IND_R_FTDF_ON_OFF_REGMAP_BUILDTIME +#define MSK_F_FTDF_ON_OFF_REGMAP_BUILDTIME 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_BUILDTIME 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_BUILDTIME 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_glob_control_0 + * + * Initialization value: 0xff00 Initialization mask: 0x6ff0e + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 0x40090020 +#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 0x6ff0e + +/* + * + * Bit: ftdf_on_off_regmap_IsPANCoordinator + * + * Enable/disable receiver check on address fields (0=enabled, 1=disabled) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_ISPANCOORDINATOR 1 +/* + * + * Bit: ftdf_on_off_regmap_rx_dma_req + * + * Source of the RX_DMA_REQ output pin of this block. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_DMA_REQ 1 +/* + * + * Bit: ftdf_on_off_regmap_tx_dma_req + * + * Source of the TX_DMA_REQ output pin of this block. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ 0x8 +#define OFF_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_DMA_REQ 1 +/* + * + * Field: ftdf_on_off_regmap_macSimpleAddress + * + * Simple address of the PAN coordinator + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS 0xff00 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACSIMPLEADDRESS 8 +/* + * + * Bit: ftdf_on_off_regmap_macLEenabled + * + * If set to '1', the Low Energy mode (also called CSL) is enabled + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACLEENABLED IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACLEENABLED 0x20000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACLEENABLED 17 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACLEENABLED 1 +/* + * + * Bit: ftdf_on_off_regmap_macTSCHenabled + * + * If set to '1', the TSCH mode is enabled + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED 0x40000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED 18 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSCHENABLED 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_glob_control_1 + * + * Initialization value: 0xffffffff Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 0x40090024 +#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macPANId + * + * The PAN ID of this device. + * The value 0xFFFF indicates that the device is not associated to a PAN. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACPANID IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACPANID 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACPANID 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACPANID 16 +/* + * + * Field: ftdf_on_off_regmap_macShortAddress + * + * The short address of the device. The values 0xFFFF and 0xFFFE indicate that no IEEE Short Address is available. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS 0xffff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACSHORTADDRESS 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_glob_control_2 + * + * Initialization value: 0xffffffff Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 0x40090028 +#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_aExtendedAddress_l + * + * Unique device address, 48 bits wide, lowest 32 bit + */ +#define IND_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_L 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_glob_control_3 + * + * Initialization value: 0xffffffff Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 0x4009002c +#define SIZE_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_aExtendedAddress_h + * + * Unique device address, 48 bits wide, highest 16 bit + */ +#define IND_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H IND_R_FTDF_ON_OFF_REGMAP_GLOB_CONTROL_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_AEXTENDEDADDRESS_H 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_0 + * + * Initialization value: 0x0 Initialization mask: 0xfbfffffe + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 0x40090030 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 0xfbfffffe + +/* + * + * Field: ftdf_on_off_regmap_RxonDuration + * + * The time (in symbol periods) the Rx must be on after setting RxEnable to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXONDURATION IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXONDURATION 0x1fffffe +#define OFF_F_FTDF_ON_OFF_REGMAP_RXONDURATION 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXONDURATION 24 +/* + * + * Bit: ftdf_on_off_regmap_RxAlwaysOn + * + * If set to '1', the receiver shall be always on if RxEnable is set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXALWAYSON IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXALWAYSON 0x2000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXALWAYSON 25 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXALWAYSON 1 +/* + * + * Field: ftdf_on_off_regmap_pti_rx + * + * This value will be used during receiving frames, during the auto ACK (when the AR bit is set in the received frame, see [FR0655] and further), a single CCA and ED scan. + * In TSCH mode this register will be used during the time slot in which frames can be received and consequently an Enhanced ACK can be transmitted. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PTI_RX IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_PTI_RX 0x78000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_PTI_RX 27 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PTI_RX 4 +/* + * + * Bit: ftdf_on_off_regmap_keep_phy_en + * + * When the transmit or receive action is ready (LmacReady4Sleep is set), the PHY_EN signal is cleared unless the control register keep_phy_en is set to '1'. + * When the control register keep_phy_en is set to '1', the signal PHY_EN shall remain being set until the keep_phy_en is cleared. + * This will help control the behavior of the arbiter between the LMAC and the DPHY. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN 0x80000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN 31 +#define SIZE_F_FTDF_ON_OFF_REGMAP_KEEP_PHY_EN 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_TxPipePropDelay + * + * Initialization value: 0x0 Initialization mask: 0xff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0x40090034 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0xff + +/* + * + * Field: ftdf_on_off_regmap_TxPipePropDelay + * + * Propagation delay (in us) of the tx pipe, between start of transmission (indicated by setting tx_flag_status) to the DPHY. + * The reset value is 0 us, which is also the closest value to the real implementation figure. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY IND_R_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY +#define MSK_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXPIPEPROPDELAY 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_MacAckWaitDuration + * + * Initialization value: 0x36 Initialization mask: 0xff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0x40090038 +#define SIZE_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0xff + +/* + * + * Field: ftdf_on_off_regmap_MacAckWaitDuration + * + * Maximum time (in symbol periods) to wait for an ACK response after transmitting a frame with the AR bit set to '1'. + * This value is used in the normal mode for the wait of an ACK response, irrespective if the ACK is a normal ACK or an Enhanced ACK. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION IND_R_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION +#define MSK_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACACKWAITDURATION 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_MacEnhAckWaitDuration + * + * Initialization value: 0x360 Initialization mask: 0xffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0x4009003c +#define SIZE_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0xffff + +/* + * + * Field: ftdf_on_off_regmap_MacEnhAckWaitDuration + * + * Maximum time (in us) to wait for an Enhanced ACK response after transmitting a frame with the AR bit set to '1'. + * This value is used in the LE/CSL mode for the wait of an ACK response (which is always an Enhanced ACK). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION IND_R_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION +#define MSK_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACENHACKWAITDURATION 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_1 + * + * Initialization value: 0x0 Initialization mask: 0xffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 0x40090040 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 0xffff + +/* + * + * Field: ftdf_on_off_regmap_phyRxAttr + * + * Value of the PHYATTR bus to DPHY during Rx operation. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYRXATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYRXATTR 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYRXATTR 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYRXATTR 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_2 + * + * Initialization value: 0x0 Initialization mask: 0xffffff01 + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 0x40090044 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 0xffffff01 + +/* + * + * Bit: ftdf_on_off_regmap_EdScanEnable + * + * If set to '1', the Energy Detect scan will be performed when RxEnable is set to '1' rather than starting a receive action. + * The length of this scan is defined by EdScanDuration. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANENABLE 1 +/* + * + * Field: ftdf_on_off_regmap_EdScanDuration + * + * The length of ED scan in symbol periods. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION 0xffffff00 +#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANDURATION 24 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_3 + * + * Initialization value: 0x70004c4 Initialization mask: 0xfffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 0x40090048 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 0xfffffff + +/* + * + * Field: ftdf_on_off_regmap_macMaxFrameTotalWaitTime + * + * Max time to wait (in symbol periods) for a requested Data Frame or an announced broadcast frame, triggered by the FP bit in the received frame was set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMAXFRAMETOTALWAITTIME 16 +/* + * + * Field: ftdf_on_off_regmap_CcaIdleWait + * + * Time to wait (in us) after CCA returned "medium idle" before starting TX-ON. + * Notes: + * 1) extra wait times are involved before a packet is really transmitted, see the relevant timing figures. + * 2) not applicable in TSCH mode since there macTSRxTx shall be used. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT 0xff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CCAIDLEWAIT 8 +/* + * + * Bit: ftdf_on_off_regmap_Addr_tab_match_FP_value + * + * In case the received source address matches with one of the Exp_SA registers, the value of the control register Addr_tap_match_FP_value will be inserted on the position of the FP bit. + * In case there is no match found, the inverse value of Addr_tap_match_FP_value will be inserted. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE 0x1000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE 24 +#define SIZE_F_FTDF_ON_OFF_REGMAP_ADDR_TAB_MATCH_FP_VALUE 1 +/* + * + * Bit: ftdf_on_off_regmap_FP_override + * + * In case the control register FP_override is set, the value of the control register FP_force_value will always be the value of the FP bit in the automatic ACK response frame. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_FP_OVERRIDE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_FP_OVERRIDE 0x2000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_FP_OVERRIDE 25 +#define SIZE_F_FTDF_ON_OFF_REGMAP_FP_OVERRIDE 1 +/* + * + * Bit: ftdf_on_off_regmap_FP_force_value + * + * In case the control register FP_override is set, the value of the control register FP_force_value will always be the value of the FP bit in the automatic ACK response frame. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_FP_FORCE_VALUE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_FP_FORCE_VALUE 0x4000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_FP_FORCE_VALUE 26 +#define SIZE_F_FTDF_ON_OFF_REGMAP_FP_FORCE_VALUE 1 +/* + * + * Bit: ftdf_on_off_regmap_FTDF_LPDP_Enable + * + * If set, not only is FP_override and SA matching done on data_request frames but to all command and data frame types (in normal mode) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_FTDF_LPDP_ENABLE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_FTDF_LPDP_ENABLE 0x8000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_FTDF_LPDP_ENABLE 27 +#define SIZE_F_FTDF_ON_OFF_REGMAP_FTDF_LPDP_ENABLE 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_os + * + * Initialization value: 0x0 Initialization mask: 0x1f + * Access mode: OS-W (one-shot - write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS 0x40090050 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS 0x1f + +/* + * + * Bit: ftdf_on_off_regmap_getGeneratorVal + * + * If set to '1', the current values of the Wake-up (event) counter/generator (EventCurrVal) and Timestamp (symbol) counter/generator (TimeStampCurrVal and TimeStampCurrPhaseVal) will be captured. + * Note that this capture actually has been done when getGeneratorVal_e is set (assuming it was cleared in advance). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL 1 +/* + * + * Bit: ftdf_on_off_regmap_RxEnable + * + * If set, receiving data may be done + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXENABLE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_RXENABLE 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXENABLE 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXENABLE 1 +/* + * + * Bit: ftdf_on_off_regmap_SingleCCA + * + * If set to '1', a single CCA will be performed. + * This can be used when e.g. the TSCH timing is not performed by the LMAC but completely by software. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SINGLECCA IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_SINGLECCA 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_SINGLECCA 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SINGLECCA 1 +/* + * + * Bit: ftdf_on_off_regmap_Csma_Ca_resume_set + * + * If set, Csma_Ca_resume_stat is set + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_SET IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_SET 0x8 +#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_SET 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_SET 1 +/* + * + * Bit: ftdf_on_off_regmap_Csma_Ca_resume_clear + * + * If set, Csma_Ca_resume_stat is cleared + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_CLEAR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_CLEAR 0x10 +#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_CLEAR 4 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_CLEAR 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_status + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS 0x40090054 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS 0xff0fff46 + +/* + * + * Bit: ftdf_on_off_regmap_LmacReady4sleep + * + * If set to '1' this register indicates that the LMAC is ready to go to sleep. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP 1 +/* + * + * Bit: ftdf_on_off_regmap_CCAStat + * + * The value of a single CCA, valid when CCAstat_e is set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CCASTAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTAT 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTAT 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTAT 1 +/* + * + * Bit: ftdf_on_off_regmap_WakeupTimerEnableStatus + * + * Status of WakeupTimerEnable after being clocked by LP_CLK (showing it's effective value). + * WakeupTimerEnableStatus can be set by setting the one-shot register WakeupTimerEnable_set and cleared by setting the one-shot register WakeupTimerEnable_clear. + * When WakeupTimerEnableStatus is set (after being cleared), the event counter will be reset to 0x0. + * + * This status can be used by software since WakeupTimerEnable is used in the slow LP_CLK area. + * Rather than waiting for a certain number of LP_CLK periods, simply scanning this status (or enable the interrupt created by WakeupTimerEnableStatus_e) will allow software to determine if this signal has been effected. + * Note that the rising edge of WakeupTimerEnable will reset the Wake-up (event) counter. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS 0x40 +#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS 6 +#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS 1 +/* + * + * Field: ftdf_on_off_regmap_EdScanValue + * + * The result of an ED scan. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE 0xff00 +#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANVALUE 8 +/* + * + * Field: ftdf_on_off_regmap_Csma_Ca_NB_stat + * + * Current status of the Number of Backoffs. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_STAT 0x70000 +#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_STAT 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_STAT 3 +/* + * + * Bit: ftdf_on_off_regmap_Csma_Ca_resume_stat + * + * In case Csma_Ca_resume_stat is set the LMAC will + * - use the value of Csma_Ca_NB_val in the CSMA-CA process rather than the initial value 0d. + * - immediately perform CCA after the sleep, not waiting for the backoff time. + * - reset Csma_Ca_resume_stat when it resumes CSMA-CA after the sleep. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_STAT 0x80000 +#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_STAT 19 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_RESUME_STAT 1 +/* + * + * Field: ftdf_on_off_regmap_Csma_Ca_BO_stat + * + * The value of the currently calculated BackOff value. To be used for the sleep time calculation in case of sleep during the BackOff time. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_STAT 0xff000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_STAT 24 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_STAT 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_EventCurrVal + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0x40090058 +#define SIZE_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0x1ffffff + +/* + * + * Field: ftdf_on_off_regmap_EventCurrVal + * + * The value of the captured Event generator (Wake-up counter) (initiated by getGeneratorVal, valid when getGeneratorVal_e is set). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL IND_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL +#define MSK_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0x1ffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_EVENTCURRVAL 25 + +/* + * + * REGISTER: ftdf_on_off_regmap_TimeStampCurrVal + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0x4009005c +#define SIZE_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_TimeStampCurrVal + * + * The value of captured timestamp generator (symbol counter) (initiated by getGeneratorVal, valid when getGeneratorVal_e is set) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL +#define MSK_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRVAL 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_TimeStampCurrPhaseVal + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0x40090074 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0xff + +/* + * + * Field: ftdf_on_off_regmap_TimeStampCurrPhaseVal + * + * Value of captured timestamp generator phase within a symbol (initiated by getGeneratorVal, valid when getGeneratorVal_e is set) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL IND_R_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL +#define MSK_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_macTSTxAckDelayVal + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0x40090078 +#define SIZE_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0xffff + +/* + * + * Field: ftdf_on_off_regmap_macTSTxAckDelayVal + * + * The time (in us) left until the ack frame is sent by the lmac. + * This can be used by software to determine if there is enough time left to send the, by software created, Enhanced ACK frame. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL IND_R_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL +#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAYVAL 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_4 + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 0x40090060 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_phySleepWait + * + * The minume time (in us) required between the clear to '0' and set to '1' of PHY_EN. + * When the signal PHY_EN is deasserted, it will not be asserted within the time phySleepWait. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYSLEEPWAIT 8 +/* + * + * Field: ftdf_on_off_regmap_RxPipePropDelay + * + * The control register RxPipePropDelay indicates the propagation delay in ~s of the Rx pipeline between the last symbol being captured at the DPHY interface and the "data valid" indication to the LMAC controller. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY 0xff00 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXPIPEPROPDELAY 8 +/* + * + * Field: ftdf_on_off_regmap_phyAckAttr + * + * During transmission of an ACK frame, phyAckAttr is used as PHYATTR on the DPHY interface. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYACKATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_4 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYACKATTR 0xffff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYACKATTR 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYACKATTR 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_5 + * + * Initialization value: 0x8c0 Initialization mask: 0xffff0fff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 0x40090064 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 0xffff0fff + +/* + * + * Field: ftdf_on_off_regmap_Ack_Response_Delay + * + * In order to have some flexibility the control register Ack_Response_Delay indicates the Acknowledge response time in ~s. + * The default value shall is 192 ~s (12 symbols). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 +#define MSK_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_ACK_RESPONSE_DELAY 8 +/* + * + * Field: ftdf_on_off_regmap_CcaStatWait + * + * The output CCASTAT is valid after 8 symbols + phyRxStartup. + * The 8 symbols are programmable by control registerCcaStatWait (in symbol periods). + * Default value is 8d. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 +#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT 0xf00 +#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTATWAIT 4 +/* + * + * Field: ftdf_on_off_regmap_phyCsmaCaAttr + * + * During CSMA-CA or CCA, the control register phyCsmaCaAttr is used to source PHYATT on the DPHY interface. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_5 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR 0xffff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYCSMACAATTR 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_6 + * + * Initialization value: 0xc0c28 Initialization mask: 0xffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 0x40090068 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 0xffffff + +/* + * + * Field: ftdf_on_off_regmap_LifsPeriod + * + * The Long IFS period is programmable by LifsPeriod (in symbols). + * The default is 40 symbols (640 us), + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 +#define MSK_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LIFSPERIOD 8 +/* + * + * Field: ftdf_on_off_regmap_SifsPeriod + * + * The Short IFS period is programmable by SifsPeriod (in symbols). + * The default is 12 symbols (192 is). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 +#define MSK_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD 0xff00 +#define OFF_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SIFSPERIOD 8 +/* + * + * Field: ftdf_on_off_regmap_WUifsPeriod + * + * The WakeUp IFS period is programmable by WUifsPeriod (in symbols). + * The default is 12 symbols (192 us). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_6 +#define MSK_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD 0xff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_WUIFSPERIOD 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_11 + * + * Initialization value: 0xff000000 Initialization mask: 0xff0fffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 0x4009006c +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 0xff0fffff + +/* + * + * Field: ftdf_on_off_regmap_macRxTotalCycleTime + * + * In CSL mode it can be decided to disable the PHY Rx (Rx-off) after reception of a Wake-up frame and enable the PHY Rx (Rx-on) when the data frame is to be expected, based on the received RZ time. + * In order to make it easier to calculate if it is efficient to switch to Rx-off and Rx-on again, a control register indicates the time needed to disable and enable the PHY Rx: macRxTotalCycleTime (resolution is 10 symbol periods) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXTOTALCYCLETIME 16 +/* + * + * Bit: ftdf_on_off_regmap_macDisCaRxOfftoRZ + * + * The switching off and on of the PHY Rx (see macRxTotalCycleTime) can be disabled whith the control register macDisCaRxOfftoRZ. + * 0 : Disabled + * 1 : Enabled + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ 0x10000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACDISCARXOFFTORZ 1 +/* + * + * Field: ftdf_on_off_regmap_Csma_Ca_NB_val + * + * Number of backoffs value in case of a CSMA-CA resume action. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_VAL IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 +#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_VAL 0xe0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_VAL 17 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_NB_VAL 3 +/* + * + * Field: ftdf_on_off_regmap_Csma_Ca_BO_threshold + * + * If the backoff time calculated in the CSMA-CA procedure as described in [FR3280] is equal to or higher than the control register Csma_Ca_BO_threshold[8] (resolution 320us, see [FR3290]) the event register Csma_Ca_BO_thr_e will be set and an interrupt. + * In case Csma_Ca_BO_threshold equals 0xFF no check will be performed and consequently Csma_Ca_BO_thr_e will not be set and no interrupt will be generated. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_11 +#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD 0xff000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD 24 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THRESHOLD 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_delta + * + * Initialization value: 0x0 Initialization mask: 0x7e + * Access mode: D-RCW (delta read/clear on write 1) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA 0x40090070 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA 0x7e + +/* + * + * Bit: ftdf_on_off_regmap_LmacReady4sleep_d + * + * Delta bit for register "LmacReady4sleep". + * This delta bit is set to '1' on each change of this status, contributes to ftdf_ce[3]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D 1 +/* + * + * Bit: ftdf_on_off_regmap_SyncTimeStamp_e + * + * The SyncTimeStamp_e event is set to '1' when the TimeStampgenerator is loaded with SyncTimeStampVal. + * This occurs at the rising edge of lp_clk when SyncTimeStampEna is set and the value of the Event generator is equal to the value SyncTimestampThr. + * This event bit contributes to ftdf_ce[3]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA +#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_E 1 +/* + * + * Bit: ftdf_on_off_regmap_SymbolTimeThr_e + * + * Event, set to '1' when the symboltime counter matched SymbolTimeThr + * This event bit contributes to ftdf_ce[3]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA +#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E 0x8 +#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_E 1 +/* + * + * Bit: ftdf_on_off_regmap_SymbolTime2Thr_e + * + * Event, set to '1' when the symboltime counter matched SymbolTime2Thr + * This event bit contributes to ftdf_ce[3]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA +#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E 0x10 +#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E 4 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_E 1 +/* + * + * Bit: ftdf_on_off_regmap_getGeneratorVal_e + * + * Event, set to '1' to indicate that the the getGeneratorVal request is completed. + * This event bit contributes to ftdf_ce[3]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA +#define MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E 0x20 +#define OFF_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E 5 +#define SIZE_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E 1 +/* + * + * Bit: ftdf_on_off_regmap_WakeupTimerEnableStatus_d + * + * Delta which indicates that WakeupTimerEnableStatus has changed + * This delta bit is set to '1' on each change of this status, contributes to ftdf_ce[3]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_DELTA +#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D 0x40 +#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D 6 +#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_D 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_mask + * + * Initialization value: 0x0 Initialization mask: 0x7e + * Access mode: DM-RW (delta mask) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK 0x40090080 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK 0x7e + +/* + * + * Bit: ftdf_on_off_regmap_LmacReady4sleep_m + * + * Mask bit for delta bit "LmacReady4sleep_d". + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M 1 +/* + * + * Bit: ftdf_on_off_regmap_SyncTimeStamp_m + * + * Mask bit for event register SyncTimeStamp_e. + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMP_M 1 +/* + * + * Bit: ftdf_on_off_regmap_SymbolTimeThr_m + * + * Mask for SymbolTimeThr_e + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M 0x8 +#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR_M 1 +/* + * + * Bit: ftdf_on_off_regmap_SymbolTime2Thr_m + * + * Mask for SymbolTime2Thr_e + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M 0x10 +#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M 4 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR_M 1 +/* + * + * Bit: ftdf_on_off_regmap_getGeneratorVal_m + * + * Mask for getGeneratorVal_e + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M 0x20 +#define OFF_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M 5 +#define SIZE_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_M 1 +/* + * + * Bit: ftdf_on_off_regmap_WakeupTimerEnableStatus_m + * + * Mask for WakeupTimerEnableStatus_d + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M 0x40 +#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M 6 +#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLESTATUS_M 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_event + * + * Initialization value: 0x0 Initialization mask: 0xf + * Access mode: E-RCW (event read/clear on write 1) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT 0x40090090 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT 0xf + +/* + * + * Bit: ftdf_on_off_regmap_EdScanReady_e + * + * The event EdScanReady_e is set to '1' to notify that the ED scan is ready. + * This event bit contributes to ftdf_ce[1]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT +#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_E 1 +/* + * + * Bit: ftdf_on_off_regmap_CCAstat_e + * + * If set to '1', the single CCA is ready + * This event bit contributes to ftdf_ce[1]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CCASTAT_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT +#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTAT_E 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTAT_E 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTAT_E 1 +/* + * + * Bit: ftdf_on_off_regmap_RxTimerExpired_e + * + * Set to '1' if one of the timers enabling the Rx-on mode expires without having received any valid frame. + * This event bit contributes to ftdf_ce[1]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT +#define MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_E 1 +/* + * + * Bit: ftdf_on_off_regmap_Csma_Ca_BO_thr_e + * + * If set, the calculated backoff time is more than Csma_Ca_BO_threshold. + * This event bit contributes to ftdf_ce[1]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E IND_R_FTDF_ON_OFF_REGMAP_LMAC_EVENT +#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E 0x8 +#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_E 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_mask + * + * Initialization value: 0x0 Initialization mask: 0xf + * Access mode: EM-RW (event mask) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK 0x40090094 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MASK 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MASK 0xf + +/* + * + * Bit: ftdf_on_off_regmap_EdScanReady_m + * + * Mask bit for event "EdScanReady_e" + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_EDSCANREADY_M 1 +/* + * + * Bit: ftdf_on_off_regmap_CCAstat_m + * + * Mask bit for event "CCAstat_e" + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CCASTAT_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_CCASTAT_M 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_CCASTAT_M 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CCASTAT_M 1 +/* + * + * Bit: ftdf_on_off_regmap_RxTimerExpired_m + * + * Mask bit for event "RxTimerExpired_e" + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXTIMEREXPIRED_M 1 +/* + * + * Bit: ftdf_on_off_regmap_Csma_Ca_BO_thr_m + * + * Mask bit for event "Csma_Ca_BO_thr_e" + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_M IND_R_FTDF_ON_OFF_REGMAP_LMAC_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_M 0x8 +#define OFF_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_M 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_CSMA_CA_BO_THR_M 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_manual_1 + * + * Initialization value: 0x0 Initialization mask: 0xffff0fff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 0x400900a0 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 0xffff0fff + +/* + * + * Bit: ftdf_on_off_regmap_lmac_manual_mode + * + * If the control register lmac_manual_mode is set to '1', the LMAC controller control signals should be controlled by the lmac_manual_control registers + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_MODE 1 +/* + * + * Bit: ftdf_on_off_regmap_lmac_manual_phy_en + * + * lmac_manual_phy_en controls the PHY_EN interface signal when lmac_manual_mode is set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_EN 1 +/* + * + * Bit: ftdf_on_off_regmap_lmac_manual_tx_en + * + * lmac_manual_tx_en controls the TX_EN interface signal when lmac_manual_mode is set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_EN 1 +/* + * + * Bit: ftdf_on_off_regmap_lmac_manual_rx_en + * + * lmac_manual_rx_en controls the RX_EN interface signal when lmac_manual_mode is set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN 0x8 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_EN 1 +/* + * + * Bit: ftdf_on_off_regmap_lmac_manual_rx_pipe_en + * + * lmac_manual_rx_pipe_en controls the rx_enable signal towards the rx pipeline when lmac_manual_mode is set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN 0x10 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN 4 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_RX_PIPE_EN 1 +/* + * + * Bit: ftdf_on_off_regmap_lmac_manual_ed_request + * + * lmac_manual_ed_request controls the ED_REQUEST interface signal when lmac_manual_mode is set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST 0x20 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST 5 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_REQUEST 1 +/* + * + * Field: ftdf_on_off_regmap_lmac_manual_tx_frm_nr + * + * lmac_manual_tx_frm_nr controls the entry in the tx buffer to be transmitted when lmac_manual_mode is set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR 0xc0 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR 6 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_FRM_NR 2 +/* + * + * Field: ftdf_on_off_regmap_lmac_manual_pti + * + * lmac_manual_pti controls the PTI interface signal when lmac_manual_mode is set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI 0xf00 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PTI 4 +/* + * + * Field: ftdf_on_off_regmap_lmac_manual_phy_attr + * + * lmac_manual_phy_attr controls the PHY_ATTR interface signal when lmac_manual_mode is set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR 0xffff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_PHY_ATTR 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_manual_os + * + * Initialization value: 0x0 Initialization mask: 0x1 + * Access mode: OS-W (one-shot - write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS 0x400900a4 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS 0x1 + +/* + * + * Bit: ftdf_on_off_regmap_lmac_manual_tx_start + * + * One shot register which triggers the transmission of a frame from the tx buffer in lmac_manual_mode to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_TX_START 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_manual_status + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS 0x400900a8 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS 0xff01 + +/* + * + * Bit: ftdf_on_off_regmap_lmac_manual_cca_stat + * + * lmac_manual_cca_stat shows the status of the CCA_STAT DPHY interface signal. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_CCA_STAT 1 +/* + * + * Field: ftdf_on_off_regmap_lmac_manual_ed_stat + * + * lmac_manual_ed_stat shows the status of the ED_STAT DPHY interface signal. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT IND_R_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT 0xff00 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMAC_MANUAL_ED_STAT 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_7 + * + * Initialization value: 0x420000 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 0x40090100 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macWUPeriod + * + * In CSL mode, the Wake-up duration in symbol periods. During this period, Wake-up frames will be transmitted. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACWUPERIOD 16 +/* + * + * Field: ftdf_on_off_regmap_macCSLsamplePeriod + * + * In CSL mode, when performing a idle listening, the receiver is enabled for at least macCSLsamplePeriod (in symbol oeriods). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_7 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD 0xffff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLSAMPLEPERIOD 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_8 + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 0x40090104 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macCSLstartSampleTime + * + * In CSL mode, the control register macCSLstartSampleTime indicates the TimeStamp generator time (in symbol periods) when to start listening (called "idle listening") or transmitting (when tx_flag_status is set). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_8 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_9 + * + * Initialization value: 0x42 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 0x40090108 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macCSLdataPeriod + * + * In CSL mode, after the wake-up sequence a data frame is expected. The receiver will be enabled for at least a period of macCSLdataPeriod (in symbol periods). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLDATAPERIOD 16 +/* + * + * Field: ftdf_on_off_regmap_macCSLFramePendingWaitT + * + * In CSL mode, if a non Wake-up frame with Frame Pending bit = '1' is received, the receiver is enabled for at least an extra period of macCSLFramePendingWaitT (in symbol periods) after the end of the received frame. + * The time the Enhanced ACK transmission lasts (if applicable) is included in this time. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_9 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT 0xffff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLFRAMEPENDINGWAITT 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_lmac_control_10 + * + * Initialization value: 0x20000000 Initialization mask: 0xf00f00ff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 0x4009010c +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 0xf00f00ff + +/* + * + * Field: ftdf_on_off_regmap_macRZzeroVal + * + * In CSL mode, if the current RZtime is less or Equal to macRZzeroVal an RZtime with value zero is inserted in the wakeup frame. So this is by default the last Wake-up frame of a Wake-up sequence. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL 0xf0000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL 28 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRZZEROVAL 4 +/* + * + * Field: ftdf_on_off_regmap_macCSLmarginRZ + * + * In CSL mode, the software can set the margin for the expected frame by control register macCSLmarginRZ (in 10 symbol periods). + * The LMAC will make sure that the receiver is ready to receive data this amount of time earlier than to be expected by the received RZ time. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ 0xf0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACCSLMARGINRZ 4 +/* + * + * Field: ftdf_on_off_regmap_macWURZCorrection + * + * In CSL mode, this register shall be used if the Wake-up frame to be transmitted is larger than 15 octets. + * It shall indicate the amount of extra data in a Wake-up frame after the RZ position in the frame (in 10 symbol periods). + * This correction is needed to make sure that the correct RZ time is filled in by the LMAC. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION IND_R_FTDF_ON_OFF_REGMAP_LMAC_CONTROL_10 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACWURZCORRECTION 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_security_0 + * + * Initialization value: 0x0 Initialization mask: 0xff7f0f02 + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 0x40090110 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_0 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_0 0xff7f0f02 + +/* + * + * Bit: ftdf_on_off_regmap_secTxRxn + * + * Encryption/decryption mode: see register "secEntry". + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECTXRXN IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECTXRXN 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECTXRXN 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECTXRXN 1 +/* + * + * Field: ftdf_on_off_regmap_secEntry + * + * Encryption/decryption mode: the software indicates by the control registers secEntry and secTxRxn which entry to use and if it's from the Tx or Rx buffer ('1' resp. '0'). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECENTRY IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECENTRY 0xf00 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECENTRY 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECENTRY 4 +/* + * + * Field: ftdf_on_off_regmap_secAlength + * + * Encryption/decryption mode: the length of the a_data is indicated by control register secAlength (in bytes). + * The end of the a_data is the start point of the m_data. So secAlength must also be set if security level==4. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECALENGTH IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECALENGTH 0x7f0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECALENGTH 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECALENGTH 7 +/* + * + * Field: ftdf_on_off_regmap_secMlength + * + * Encryption/decryption mode: the length of the m_data is indicated by control register secMlength (in bytes). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECMLENGTH IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECMLENGTH 0x7f000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECMLENGTH 24 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECMLENGTH 7 +/* + * + * Bit: ftdf_on_off_regmap_secEncDecn + * + * Encryption/decryption mode: the control register secEncDecn indicates whether to encrypt ('1') or decrypt ('0') the data. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECENCDECN IND_R_FTDF_ON_OFF_REGMAP_SECURITY_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECENCDECN 0x80000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECENCDECN 31 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECENCDECN 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_security_1 + * + * Initialization value: 0x0 Initialization mask: 0xffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_1 0x40090114 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_1 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_1 0xffff + +/* + * + * Field: ftdf_on_off_regmap_secAuthFlags + * + * Encryption/decryption mode: register secAuthFlags contains the authentication flags fields. + * bit[7] is '0' + * bit[6] is "A_data present" + * bit[5:3]: 3-bit security level of m_data + * bit[2:0]: 3-bit security level of a_data. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS IND_R_FTDF_ON_OFF_REGMAP_SECURITY_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECAUTHFLAGS 8 +/* + * + * Field: ftdf_on_off_regmap_secEncrFlags + * + * Encryption/decryption mode: register secEncrFlags contains the encryption flags field. + * Bits [2:0] are the 3-bit encoding flags of a_data, the other bits msut be set to '0'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS IND_R_FTDF_ON_OFF_REGMAP_SECURITY_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS 0xff00 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECENCRFLAGS 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_secKey_0 + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_0 0x40090118 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_0 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_0 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_secKey_0 + * + * Encryption/decryption mode: Registers secKey[0..3] contain the key to be used. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_0 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_0 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_0 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_0 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_secKey_1 + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_1 0x4009011c +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_1 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_1 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_secKey_1 + * + * Encryption/decryption mode: see register "secKey_0" + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_1 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_1 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_1 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_1 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_secKey_2 + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_2 0x40090120 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_2 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_2 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_secKey_2 + * + * Encryption/decryption mode: see register "secKey_0" + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_2 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_2 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_2 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_2 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_secKey_3 + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECKEY_3 0x40090124 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECKEY_3 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECKEY_3 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_secKey_3 + * + * Encryption/decryption mode: see register "secKey_0" + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECKEY_3 IND_R_FTDF_ON_OFF_REGMAP_SECKEY_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECKEY_3 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SECKEY_3 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECKEY_3 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_secNonce_0 + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 0x40090128 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_secNonce_0 + * + * Encryption/decryption mode: register secNonce[0..3] contains the Nonce to be used for encryption/decryption. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_0 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_secNonce_1 + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 0x4009012c +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_secNonce_1 + * + * Encryption/decryption mode: see register "Nonce_0" + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_1 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_secNonce_2 + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 0x40090130 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_secNonce_2 + * + * Encryption/decryption mode: see register "Nonce_0" + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_2 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_secNonce_3 + * + * Initialization value: 0x0 Initialization mask: 0xff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 0x40090134 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 0xff + +/* + * + * Field: ftdf_on_off_regmap_secNonce_3 + * + * Encryption/decryption mode: see register "Nonce_0" + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 IND_R_FTDF_ON_OFF_REGMAP_SECNONCE_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECNONCE_3 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_security_os + * + * Initialization value: 0x0 Initialization mask: 0x3 + * Access mode: OS-W (one-shot - write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_OS 0x40090138 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_OS 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_OS 0x3 + +/* + * + * Bit: ftdf_on_off_regmap_secAbort + * + * Encryption/decryption mode: see register "Nonce_0" + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECABORT IND_R_FTDF_ON_OFF_REGMAP_SECURITY_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_SECABORT 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECABORT 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECABORT 1 +/* + * + * Bit: ftdf_on_off_regmap_secStart + * + * Encryption/decryption mode: one_shot register to start the encryption, decryption and authentication support task. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECSTART IND_R_FTDF_ON_OFF_REGMAP_SECURITY_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_SECSTART 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECSTART 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECSTART 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_security_status + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS 0x40090140 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS 0x3 + +/* + * + * Bit: ftdf_on_off_regmap_secBusy + * + * Encryption/decryption mode: register "secBusy" indicates if the encryption/decryption process is still running. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECBUSY IND_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_SECBUSY 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECBUSY 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECBUSY 1 +/* + * + * Bit: ftdf_on_off_regmap_secAuthFail + * + * Encryption/decryption mode: in case of decryption, the status bit secAuthFail will be set when the authentication has failed. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL IND_R_FTDF_ON_OFF_REGMAP_SECURITY_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECAUTHFAIL 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_security_event + * + * Initialization value: 0x0 Initialization mask: 0x1 + * Access mode: E-RCW (event read/clear on write 1) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT 0x40090150 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT 0x1 + +/* + * + * Bit: ftdf_on_off_regmap_secReady_e + * + * Encryption/decryption mode: the Event bit secReady_e is set to '1' when the authentication process is ready (i.e. secBusy is cleared). + * This event bit contributes to ftdf_ce[3]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECREADY_E IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENT +#define MSK_F_FTDF_ON_OFF_REGMAP_SECREADY_E 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECREADY_E 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECREADY_E 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_security_eventmask + * + * Initialization value: 0x0 Initialization mask: 0x1 + * Access mode: EM-RW (event mask) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK 0x40090154 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK 0x1 + +/* + * + * Bit: ftdf_on_off_regmap_secReady_m + * + * Mask bit for event "secReady_e". + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SECREADY_M IND_R_FTDF_ON_OFF_REGMAP_SECURITY_EVENTMASK +#define MSK_F_FTDF_ON_OFF_REGMAP_SECREADY_M 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_SECREADY_M 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SECREADY_M 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_tsch_control_0 + * + * Initialization value: 0x89803e8 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 0x40090160 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macTSTxAckDelay + * + * TSCH mode: the time between the end of a Rx frame and the start of an Enhanced Acknowlegde frame. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSTXACKDELAY 16 +/* + * + * Field: ftdf_on_off_regmap_macTSRxWait + * + * TSCH mode: The times to wait for start of frame + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT 0xffff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSRXWAIT 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_tsch_control_1 + * + * Initialization value: 0xc0 Initialization mask: 0xffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 0x40090164 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 0xffff + +/* + * + * Field: ftdf_on_off_regmap_macTSRxTx + * + * TSCH mode: The time between the CCA and the TX of a frame + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACTSRXTX IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSRXTX 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSRXTX 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSRXTX 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_tsch_control_2 + * + * Initialization value: 0x1900320 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 0x40090168 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macTSRxAckDelay + * + * TSCH mode: End of frame to when the transmitter shall listen for Acknowledgement + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY 0xffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSRXACKDELAY 16 +/* + * + * Field: ftdf_on_off_regmap_macTSAckWait + * + * TSCH mode: The minimum time to wait for start of an Acknowledgement + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT IND_R_FTDF_ON_OFF_REGMAP_TSCH_CONTROL_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT 0xffff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTSACKWAIT 16 + +/* + * + * REGISTER: ftdf_on_off_regmap_phy_parameters_0 + * + * Initialization value: 0x76543210 Initialization mask: 0x77777777 + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 0x40090180 +#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 0x77777777 + +/* + * + * Field: ftdf_on_off_regmap_rxBitPos_0 + * + * DPHY interface: control rxBitPos(8)(3) controls the position that a bit should have at the DPHY interface. + * So the default values are rxBitPos_0 = 0, rxBitPos_1 = 1, rxBitPos_2 = 2, etc. + * + * Note1 that this is a conversion from rx DPHY interface to the internal data byte + * So + * for(n=7;n>=0;n--) + * rx_data(n) = dphy_bit(tx_BitPos(n)) + * endfor + * + * Note2 that rxBitPos and txBitPos must have inverse functions. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 0x7 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_0 3 +/* + * + * Field: ftdf_on_off_regmap_rxBitPos_1 + * + * DPHY interface: see rxBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 0x70 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 4 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_1 3 +/* + * + * Field: ftdf_on_off_regmap_rxBitPos_2 + * + * DPHY interface: see rxBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 0x700 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_2 3 +/* + * + * Field: ftdf_on_off_regmap_rxBitPos_3 + * + * DPHY interface: see rxBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 0x7000 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 12 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_3 3 +/* + * + * Field: ftdf_on_off_regmap_rxBitPos_4 + * + * DPHY interface: see rxBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 0x70000 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_4 3 +/* + * + * Field: ftdf_on_off_regmap_rxBitPos_5 + * + * DPHY interface: see rxBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 0x700000 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 20 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_5 3 +/* + * + * Field: ftdf_on_off_regmap_rxBitPos_6 + * + * DPHY interface: see rxBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 0x7000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 24 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_6 3 +/* + * + * Field: ftdf_on_off_regmap_rxBitPos_7 + * + * DPHY interface: see rxBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 0x70000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 28 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBITPOS_7 3 + +/* + * + * REGISTER: ftdf_on_off_regmap_phy_parameters_1 + * + * Initialization value: 0x76543210 Initialization mask: 0x77777777 + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 0x40090184 +#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 0x77777777 + +/* + * + * Field: ftdf_on_off_regmap_txBitPos_0 + * + * DPHY interface: control txBitPos(8)(3) controls the position that a bit should have at the DPHY interface. + * So the default values are txBitPos_0 = 0, txBitPos_1 = 1, txBitPos_2 = 2, etc. + * + * Note1 that this is a conversion from internal data byte to the DPHY interface. + * So + * for(n=7;n>=0;n--) + * tx_dphy_bit(n) = tx_data(tx_BitPos(n)) + * endfor + * + * Note2 that txBitPos and rxBitPos must have inverse functions. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 0x7 +#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_0 3 +/* + * + * Field: ftdf_on_off_regmap_txBitPos_1 + * + * DPHY interface: see txBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 0x70 +#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 4 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_1 3 +/* + * + * Field: ftdf_on_off_regmap_txBitPos_2 + * + * DPHY interface: see txBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 0x700 +#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_2 3 +/* + * + * Field: ftdf_on_off_regmap_txBitPos_3 + * + * DPHY interface: see txBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 0x7000 +#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 12 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_3 3 +/* + * + * Field: ftdf_on_off_regmap_txBitPos_4 + * + * DPHY interface: see txBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 0x70000 +#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_4 3 +/* + * + * Field: ftdf_on_off_regmap_txBitPos_5 + * + * DPHY interface: see txBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 0x700000 +#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 20 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_5 3 +/* + * + * Field: ftdf_on_off_regmap_txBitPos_6 + * + * DPHY interface: see txBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 0x7000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 24 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_6 3 +/* + * + * Field: ftdf_on_off_regmap_txBitPos_7 + * + * DPHY interface: see txBitPos_0 + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 0x70000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 28 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBITPOS_7 3 + +/* + * + * REGISTER: ftdf_on_off_regmap_phy_parameters_2 + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 0x40090188 +#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_phyTxStartup + * + * DPHY interface: the phy wait time (in us) before transmission of a frame may start. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTXSTARTUP 8 +/* + * + * Field: ftdf_on_off_regmap_phyTxLatency + * + * DPHY interface: phy delay (in us) between DPHY interface and air interface. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY 0xff00 +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTXLATENCY 8 +/* + * + * Field: ftdf_on_off_regmap_phyTxFinish + * + * DPHY interface: Phy wait time (in us) before deasserting TX_EN after deasserting TX_VALID. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH 0xff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTXFINISH 8 +/* + * + * Field: ftdf_on_off_regmap_phyTRxWait + * + * DPHY interface: Phy wait time (in us) between deassertion of TX_EN and assertion of RX_EN or vice versa. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_2 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT 0xff000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT 24 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYTRXWAIT 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_phy_parameters_3 + * + * Initialization value: 0x1000000 Initialization mask: 0x1ffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 0x4009018c +#define SIZE_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 0x1ffffff + +/* + * + * Field: ftdf_on_off_regmap_phyRxStartup + * + * DPHY interface: Phy wait time (in us) before receiving of a frame may start. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYRXSTARTUP 8 +/* + * + * Field: ftdf_on_off_regmap_phyRxLatency + * + * DPHY interface: Phy delay (in us) between air and DPHY interface. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY 0xff00 +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYRXLATENCY 8 +/* + * + * Field: ftdf_on_off_regmap_phyEnable + * + * DPHY interface: Asserting the DPHY interface signals TX_EN or RX_EN does not take place within the time phyEnable after asserting the signal PHY_EN. + * (in us). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PHYENABLE IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_PHYENABLE 0xff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_PHYENABLE 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PHYENABLE 8 +/* + * + * Bit: ftdf_on_off_regmap_use_legacy_phy_en + * + * If the control register use_legacy_phy_en is set (default), the output signal PHY_TRANSACTION will be sourced by PHY_EN rather than PHY_TRANSACTION. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_USE_LEGACY_PHY_EN IND_R_FTDF_ON_OFF_REGMAP_PHY_PARAMETERS_3 +#define MSK_F_FTDF_ON_OFF_REGMAP_USE_LEGACY_PHY_EN 0x1000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_USE_LEGACY_PHY_EN 24 +#define SIZE_F_FTDF_ON_OFF_REGMAP_USE_LEGACY_PHY_EN 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_rx_control_0 + * + * Initialization value: 0x0 Initialization mask: 0xfffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 0x40090200 +#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 0xfffffff + +/* + * + * Bit: ftdf_on_off_regmap_DbgRxTransparentMode + * + * If set yo '1', Rx pipe is fully set in transparent mode (for debug purpose). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_DBGRXTRANSPARENTMODE 1 +/* + * + * Bit: ftdf_on_off_regmap_RxBeaconOnly + * + * If set to '1', only Beacons frames are accepted + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBEACONONLY 1 +/* + * + * Bit: ftdf_on_off_regmap_RxCoordRealignOnly + * + * If set to '1', only Coordinator Realignment frames are accepted + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXCOORDREALIGNONLY 1 +/* + * + * Field: ftdf_on_off_regmap_rx_read_buf_ptr + * + * Indication where new data will be read + * All four bits shall be used when using these pointer values (0d - 15d). + * However, the Receive Packet buffer has a size of 8 entries. + * So reading the Receive Packet buffer entries shall use the mod8 of the pointer values. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR 0x78 +#define OFF_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_READ_BUF_PTR 4 +/* + * + * Bit: ftdf_on_off_regmap_DisRxFrmPendingca + * + * Whan the control register DisRxFrmPendingCa is set to '1', the notification of the received FP bit to the LMAC Controller is disabled and thus no consequent actions will take place. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA 0x80 +#define OFF_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA 7 +#define SIZE_F_FTDF_ON_OFF_REGMAP_DISRXFRMPENDINGCA 1 +/* + * + * Bit: ftdf_on_off_regmap_DisRxAckRequestca + * + * When the control register DisRxAckRequestca is set to '1' all consequent actions for a received Acknowledge Request bit are disabled. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA 0x100 +#define OFF_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_DISRXACKREQUESTCA 1 +/* + * + * Bit: ftdf_on_off_regmap_macAlwaysPassCrcerror + * + * If set to '1', a FCS error will not drop the frame. However, an FCS error will be reported in the Rx meta data (crc16_error is set to '1'). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR 0x200 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR 9 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSCRCERROR 1 +/* + * + * Bit: ftdf_on_off_regmap_DisDataRequestca + * + * When the control register DisDataRequestCa is set, the notification of the received Data Request is disabled. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA 0x400 +#define OFF_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA 10 +#define SIZE_F_FTDF_ON_OFF_REGMAP_DISDATAREQUESTCA 1 +/* + * + * Bit: ftdf_on_off_regmap_macAlwaysPassResFrameVersion + * + * If set to '1', a packet with a reserved FrameVersion shall not be dropped + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION 0x800 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION 11 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSRESFRAMEVERSION 1 +/* + * + * Bit: ftdf_on_off_regmap_macAlwaysPassWrongDPANId + * + * If register macAlwaysPassWrongDPANId is set to '1', packet with a wrong Destiantion PanID will not be dropped. + * However, in case of an FCS error, the packet is dropped. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID 0x1000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID 12 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDPANID 1 +/* + * + * Bit: ftdf_on_off_regmap_macAlwaysPassWrongDAddr + * + * If set to '1', a packet with a wrong DAddr is not dropped + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR 0x2000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR 13 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWRONGDADDR 1 +/* + * + * Bit: ftdf_on_off_regmap_macAlwaysPassBeaconWrongPANId + * + * If the control register macAlwaysPassBeaconWrongPANId is set, the frame is not dropped in case of a mismatch in PAN-ID, irrespective of the setting of RxBeaconOnly. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID 0x4000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID 14 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSBEACONWRONGPANID 1 +/* + * + * Bit: ftdf_on_off_regmap_macAlwaysPassToPanCoordinator + * + * When the control register macAlwaysPassToPanCoordinator is set to '1', the frame is not dropped due to a span_coord_error. + * However, in case of an FCS error, the packet is dropped. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR 0x8000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR 15 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSTOPANCOORDINATOR 1 +/* + * + * Field: ftdf_on_off_regmap_macAlwaysPassFrmType + * + * The control registers macAlwaysPassFrmType[7:0], shall control if this Frame Type shall be dropped. + * If a bit is set to '1', the Frame Type corresponding with the bit position is not dropped, even in case of a CRC error. + * Example: + * if bit 3 is set to '1', Frame Type 3 shall not be dropped. + * If there is a FCS error, the error shall be reported in the Rx meta data (crc16_error is set to '1'). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE 0xff0000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSFRMTYPE 8 +/* + * + * Bit: ftdf_on_off_regmap_macAlwaysPassWakeUp + * + * In CSL mode, if the control register macAlwaysPassWakeUp is set to '1', received Wake- up frames for this device are put into the Rx packet buffer without notifying the LMAC Controller (part of transparent mode control). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP 0x1000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP 24 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACALWAYSPASSWAKEUP 1 +/* + * + * Bit: ftdf_on_off_regmap_macPassWakeUp + * + * In CSL mode, if set to '1', WakeUp frames will be put into the Rx buffer. + * This can be useful for software to parse the WakeUp frame. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP 0x2000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP 25 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACPASSWAKEUP 1 +/* + * + * Bit: ftdf_on_off_regmap_macImplicitBroadcast + * + * If set to '1', Frame Version 2 frames without Daddr or DPANId shall be accepted. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST 0x4000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST 26 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACIMPLICITBROADCAST 1 +/* + * + * Bit: ftdf_on_off_regmap_DisRxAckReceivedca + * + * If set to '1', the LMAC controller shall ignore all consequent actions upon a set AR bit in the transmitted frame (e.g. enabling Rx-on mode after the transmission and wait for an ACK). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA IND_R_FTDF_ON_OFF_REGMAP_RX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA 0x8000000 +#define OFF_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA 27 +#define SIZE_F_FTDF_ON_OFF_REGMAP_DISRXACKRECEIVEDCA 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_rx_event + * + * Initialization value: 0x0 Initialization mask: 0xf + * Access mode: E-RCW2 (event read/clear on write 1) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT 0x40090204 +#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_EVENT 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_RX_EVENT 0xf + +/* + * + * Bit: ftdf_on_off_regmap_RxSof_e + * + * Set to '1' when RX_SOF has been detected. + * This event bit contributes to ftdf_ce[1]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXSOF_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT +#define MSK_F_FTDF_ON_OFF_REGMAP_RXSOF_E 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXSOF_E 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXSOF_E 1 +/* + * + * Bit: ftdf_on_off_regmap_rx_overflow_e + * + * If set to '1' it indicates that the Rx packet buffer has an overflow. + * This event bit contributes to ftdf_ce[1]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT +#define MSK_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_E 1 +/* + * + * Bit: ftdf_on_off_regmap_rx_buf_avail_e + * + * If set to '1' it indicates that a new valid packet completely has been received + * This event bit contributes to ftdf_ce[1]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT +#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_E 1 +/* + * + * Bit: ftdf_on_off_regmap_rxbyte_e + * + * If set to '1' it indicates that the first byte of a new packet has been received + * This event bit contributes to ftdf_ce[1]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBYTE_E IND_R_FTDF_ON_OFF_REGMAP_RX_EVENT +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBYTE_E 0x8 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBYTE_E 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBYTE_E 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_rx_mask + * + * Initialization value: 0x0 Initialization mask: 0xf + * Access mode: EM-RW (event mask) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_RX_MASK 0x40090208 +#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_MASK 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_RX_MASK 0xf + +/* + * + * Bit: ftdf_on_off_regmap_RxSof_m + * + * Mask bit for event "RxSof_e". + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXSOF_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_RXSOF_M 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXSOF_M 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXSOF_M 1 +/* + * + * Bit: ftdf_on_off_regmap_rx_overflow_m + * + * Mask bit for event " rx_overflow_e". + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_OVERFLOW_M 1 +/* + * + * Bit: ftdf_on_off_regmap_rx_buf_avail_m + * + * Mask bit for event "rx_buf_avail_e". + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUF_AVAIL_M 1 +/* + * + * Bit: ftdf_on_off_regmap_rxbyte_m + * + * Mask bit for event "rxbyte_e". + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RXBYTE_M IND_R_FTDF_ON_OFF_REGMAP_RX_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_RXBYTE_M 0x8 +#define OFF_F_FTDF_ON_OFF_REGMAP_RXBYTE_M 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RXBYTE_M 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_rx_status + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS 0x4009020c +#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_STATUS 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_RX_STATUS 0x1f + +/* + * + * Bit: ftdf_on_off_regmap_rx_buff_is_full + * + * If set to '1', it indicates that the Rx packet buffer is full + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL 1 +/* + * + * Field: ftdf_on_off_regmap_rx_write_buf_ptr + * + * Indication where new data will be written. + * All four bits shall be used when using these pointer values (0d - 15d). + * However, the Receive Packet buffer has a size of 8 entries. + * So reading the Receive Packet buffer entries shall use the mod8 of the pointer values. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS +#define MSK_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR 0x1e +#define OFF_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_WRITE_BUF_PTR 4 + +/* + * + * REGISTER: ftdf_on_off_regmap_SymbolTimeSnapshotVal + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0x40090210 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_SymbolTimeSnapshotVal + * + * The Status register SymbolTimeSnapshotVal indicates the actual value of the TimeStamp generator. + * This can be useful for software to use e.g. in CSL mode at creating an Enhanced ACK to calculate the CSL phase and period. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL +#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_rx_status_delta + * + * Initialization value: 0x0 Initialization mask: 0x1 + * Access mode: D-RCW (delta read/clear on write 1) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA 0x40090220 +#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA 0x1 + +/* + * + * Bit: ftdf_on_off_regmap_rx_buff_is_full_d + * + * Delta bit of status "rx_buff_is_full". + * This delta bit is set to '1' on each change of this status, contributes to ftdf_ce[1]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_DELTA +#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_D 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_rx_status_mask + * + * Initialization value: 0x0 Initialization mask: 0x1 + * Access mode: DM-RW (delta mask) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK 0x40090224 +#define SIZE_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK 0x1 + +/* + * + * Bit: ftdf_on_off_regmap_rx_buff_is_full_m + * + * Mask bit for delta bit "rx_buff_is_full_d". + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M IND_R_FTDF_ON_OFF_REGMAP_RX_STATUS_MASK +#define MSK_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_RX_BUFF_IS_FULL_M 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_tx_control_0 + * + * Initialization value: 0x4350 Initialization mask: 0x7ff1 + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 0x40090240 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 0x7ff1 + +/* + * + * Bit: ftdf_on_off_regmap_DbgTxTransparentMode + * + * If set to '1', the MPDU octets pass transparently through the MAC in the transmit direction (for debug purpose). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_DBGTXTRANSPARENTMODE 1 +/* + * + * Field: ftdf_on_off_regmap_macMaxBE + * + * CSMA-CA: Maximum Backoff Exponent (range 3-8) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACMAXBE IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACMAXBE 0xf0 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACMAXBE 4 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMAXBE 4 +/* + * + * Field: ftdf_on_off_regmap_macMinBE + * + * CSMA-CA: Minimum Backoff Exponent (range 0-macMaxBE) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACMINBE IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACMINBE 0xf00 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACMINBE 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMINBE 4 +/* + * + * Field: ftdf_on_off_regmap_macMaxCSMABackoffs + * + * CSMA-CA: Maximum number of CSMA-CA backoffs (range 0-5) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS IND_R_FTDF_ON_OFF_REGMAP_TX_CONTROL_0 +#define MSK_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS 0x7000 +#define OFF_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS 12 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACMAXCSMABACKOFFS 3 + +/* + * + * REGISTER: ftdf_on_off_regmap_ftdf_ce + * + * Initialization value: none. + * Access mode: EC-R (composite event) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_FTDF_CE 0x40090250 +#define SIZE_R_FTDF_ON_OFF_REGMAP_FTDF_CE 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_FTDF_CE 0x3f + +/* + * + * Field: ftdf_on_off_regmap_ftdf_ce + * + * Composite service request from ftdf macro (see FR0400 in v40.100.2.41.pdf), set to '1' if the branch currently contributes to the interrupt. + * Bit 0 = unused + * Bit 1 = rx interrupts + * Bit 2 = unused + * Bit 3 = miscelaneous interrupts + * Bit 4 = tx interrupts + * Bit 5 = Reserved + * Upon an interrupt, using the ftdf_ce bits it can be checked which interrupt branch creates this interrupt. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_FTDF_CE IND_R_FTDF_ON_OFF_REGMAP_FTDF_CE +#define MSK_F_FTDF_ON_OFF_REGMAP_FTDF_CE 0x3f +#define OFF_F_FTDF_ON_OFF_REGMAP_FTDF_CE 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_FTDF_CE 6 + +/* + * + * REGISTER: ftdf_on_off_regmap_ftdf_cm + * + * Initialization value: 0x0 Initialization mask: 0x3f + * Access mode: ECM-RW (composite event mask) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_FTDF_CM 0x40090254 +#define SIZE_R_FTDF_ON_OFF_REGMAP_FTDF_CM 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_FTDF_CM 0x3f + +/* + * + * Field: ftdf_on_off_regmap_ftdf_cm + * + * mask bits for ftf_ce. + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_FTDF_CM IND_R_FTDF_ON_OFF_REGMAP_FTDF_CM +#define MSK_F_FTDF_ON_OFF_REGMAP_FTDF_CM 0x3f +#define OFF_F_FTDF_ON_OFF_REGMAP_FTDF_CM 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_FTDF_CM 6 + +/* + * + * REGISTER: ftdf_on_off_regmap_SyncTimeStampThr + * + * Initialization value: 0x0 Initialization mask: 0x1ffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0x40090304 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0x1ffffff + +/* + * + * Field: ftdf_on_off_regmap_SyncTimeStampThr + * + * Threshold for synchronize the timestamp counter: at this value of the event counter the synchronization of the timestamp (symbol) counter is done (if SyncTimeStampEna is set to '1'). + * If SyncTimeStamp_e is set to '1' the synchronization has taken place. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR +#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0x1ffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPTHR 25 + +/* + * + * REGISTER: ftdf_on_off_regmap_SyncTimeStampVal + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0x40090308 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_SyncTimeStampVal + * + * Value to synchronize the timestamp counter with at the moment indicated by SyncTimeStampThr. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL +#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPVAL 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_SyncTimeStampPhaseVal + * + * Initialization value: 0x0 Initialization mask: 0xff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0x40090320 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0xff + +/* + * + * Field: ftdf_on_off_regmap_SyncTimeStampPhaseVal + * + * Value to synchronize the timestamp counter phase with at the moment indicated by SyncTimeStampThr. + * Please note the +1 correction needed for most accurate result (+0.5 is than the average error, resulting is a just too fast clock). + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL IND_R_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL +#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_timer_control_1 + * + * Initialization value: 0x0 Initialization mask: 0x2 + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 0x4009030c +#define SIZE_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 0x2 + +/* + * + * Bit: ftdf_on_off_regmap_SyncTimeStampEna + * + * If set to '1', the synchronization of the timestamp counter after a deep-sleep cycle will be performed when SyncTimeStampThr matches the value of the event (wake-up) counter. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA IND_R_FTDF_ON_OFF_REGMAP_TIMER_CONTROL_1 +#define MSK_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYNCTIMESTAMPENA 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_macTxStdAckFrmCnt + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0x40090310 +#define SIZE_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macTxStdAckFrmCnt + * + * Traffic counter: the number of standard Acknowledgment frames transmitted after the last deep-sleep cycle. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT IND_R_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT +#define MSK_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACTXSTDACKFRMCNT 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_macRxStdAckFrmOkCnt + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0x40090314 +#define SIZE_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macRxStdAckFrmOkCnt + * + * Traffic counter: the number of Standard Acknowledgment frames received after the last deep-sleep cycle. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT IND_R_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT +#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_macRxAddrFailFrmCnt + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0x40090318 +#define SIZE_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macRxAddrFailFrmCnt + * + * Traffic counter: the number of frames discarded due to incorrect address or PAN Id after the last deep-sleep cycle. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT IND_R_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT +#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXADDRFAILFRMCNT 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_macRxUnsupFrmCnt + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0x4009031c +#define SIZE_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macRxUnsupFrmCnt + * + * Traffic counter: the number of frames which do pass the checks but are not supported after the last deep-sleep cycle. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT IND_R_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT +#define MSK_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACRXUNSUPFRMCNT 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_macFCSErrorCount + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0x40090340 +#define SIZE_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_macFCSErrorCount + * + * metrics counter: the number of received frames that were discarded due to an incorrect FCS after the last deep-sleep cycle. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT IND_R_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT +#define MSK_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_MACFCSERRORCOUNT 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_LmacReset + * + * Initialization value: 0x0 Initialization mask: 0x106df + * Access mode: OS-W (one-shot - write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_LMACRESET 0x40090360 +#define SIZE_R_FTDF_ON_OFF_REGMAP_LMACRESET 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_LMACRESET 0x106df + +/* + * + * Bit: ftdf_on_off_regmap_LmacReset_control + * + * LmacReset_control: A '1' resets LMAC Controller (for debug and MLME-reset) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL IND_R_FTDF_ON_OFF_REGMAP_LMACRESET +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_CONTROL 1 +/* + * + * Bit: ftdf_on_off_regmap_LmacReset_rx + * + * LmacReset_rx: A '1' resets LMAC rx pipeline (for debug and MLME-reset) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX IND_R_FTDF_ON_OFF_REGMAP_LMACRESET +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_RX 1 +/* + * + * Bit: ftdf_on_off_regmap_LmacReset_tx + * + * LmacReset_tx: A '1' resets LMAC tx pipeline (for debug and MLME-reset) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX IND_R_FTDF_ON_OFF_REGMAP_LMACRESET +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX 0x4 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX 2 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_TX 1 +/* + * + * Bit: ftdf_on_off_regmap_LmacReset_ahb + * + * LmacReset_ahb: A '1' resets LMAC ahb interface (for debug and MLME-reset) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB IND_R_FTDF_ON_OFF_REGMAP_LMACRESET +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB 0x8 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB 3 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_AHB 1 +/* + * + * Bit: ftdf_on_off_regmap_LmacReset_oreg + * + * LmacReset_oreg: A '1' resets LMAC on_off regmap (for debug and MLME-reset) + * + * #$LmacReset_areg@on_off_regmap + * #LmacReset_areg: A '1' Resets LMAC always_on regmap (for debug and MLME-reset) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG IND_R_FTDF_ON_OFF_REGMAP_LMACRESET +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG 0x10 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG 4 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_OREG 1 +/* + * + * Bit: ftdf_on_off_regmap_LmacReset_tstim + * + * LmacReset_tstim: A '1' resets LMAC timestamp timer (for debug and MLME-reset) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM IND_R_FTDF_ON_OFF_REGMAP_LMACRESET +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM 0x40 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM 6 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_TSTIM 1 +/* + * + * Bit: ftdf_on_off_regmap_LmacReset_sec + * + * LmacReset_sec: A '1' resets LMAC security (for debug and MLME-reset) + * + * #$LmacReset_wutim@on_off_regmap + * #LmacReset_wutim: A '1' Resets LMAC wake-up timer (for debug and MLME-reset) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC IND_R_FTDF_ON_OFF_REGMAP_LMACRESET +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC 0x80 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC 7 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_SEC 1 +/* + * + * Bit: ftdf_on_off_regmap_LmacReset_count + * + * LmacReset_count: A '1' resets LMAC mac counters (for debug and MLME-reset) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT IND_R_FTDF_ON_OFF_REGMAP_LMACRESET +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT 0x200 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT 9 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_COUNT 1 +/* + * + * Bit: ftdf_on_off_regmap_LmacReset_timctrl + * + * LmacReset_count: A '1' resets LMAC timing control block (for debug and MLME-reset) + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL IND_R_FTDF_ON_OFF_REGMAP_LMACRESET +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL 0x400 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL 10 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACRESET_TIMCTRL 1 +/* + * + * Bit: ftdf_on_off_regmap_LmacGlobReset_count + * + * If set, the LMAC performance and traffic counters will be reset. + * Use this register for functionally reset these counters. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT IND_R_FTDF_ON_OFF_REGMAP_LMACRESET +#define MSK_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT 0x10000 +#define OFF_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT 16 +#define SIZE_F_FTDF_ON_OFF_REGMAP_LMACGLOBRESET_COUNT 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_wakeup_control_os + * + * Initialization value: 0x0 Initialization mask: 0x3 + * Access mode: OS-W (one-shot - write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_WAKEUP_CONTROL_OS 0x40090364 +#define SIZE_R_FTDF_ON_OFF_REGMAP_WAKEUP_CONTROL_OS 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_WAKEUP_CONTROL_OS 0x3 + +/* + * + * Bit: ftdf_on_off_regmap_WakeupTimerEnable_set + * + * If set, WakeupTimerEnableStatus will be set. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_SET IND_R_FTDF_ON_OFF_REGMAP_WAKEUP_CONTROL_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_SET 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_SET 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_SET 1 +/* + * + * Bit: ftdf_on_off_regmap_WakeupTimerEnable_clear + * + * If set, WakeupTimerEnableStatus will be cleared. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_CLEAR IND_R_FTDF_ON_OFF_REGMAP_WAKEUP_CONTROL_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_CLEAR 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_CLEAR 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_WAKEUPTIMERENABLE_CLEAR 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_SymbolTimeThr + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0x40090380 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_SymbolTimeThr + * + * Symboltime Threshold to generate a general interrupt when this value matches the symbol counter value. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR +#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIMETHR 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_SymbolTime2Thr + * + * Initialization value: 0x0 Initialization mask: 0xffffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0x40090384 +#define SIZE_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0xffffffff + +/* + * + * Field: ftdf_on_off_regmap_SymbolTime2Thr + * + * Symboltime 2 Threshold to generate a general interrupt when this value matches the symbol counter value. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR IND_R_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR +#define MSK_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0xffffffff +#define OFF_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_SYMBOLTIME2THR 32 + +/* + * + * REGISTER: ftdf_on_off_regmap_DebugControl + * + * Initialization value: 0x0 Initialization mask: 0x1ff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL 0x40090390 +#define SIZE_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL 0x1ff + +/* + * + * Bit: ftdf_on_off_regmap_dbg_rx_input + * + * If set to '1', the Rx debug interface will be selected as input for the Rx pipeline rather than the DPHY interface signals. + * Note that in this mode, DBG_RX_DATA[3:0] and DBG_RX_SOF are sourced by another source (outside the scope of the LMAC) while the other Rx inputs (CCA_STAT, LQI[7:0] and ED_STAT[7:0]) are forced to 0x00. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT IND_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL +#define MSK_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT 0x100 +#define OFF_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_DBG_RX_INPUT 1 +/* + * + * Field: ftdf_on_off_regmap_dbg_control + * + * Control of the debug interface: + * + * dbg_control 0x00 Not used + * diagnose bus bit 7 - 0 = all '0' + * + * dbg_control 0x01 Legacy debug mode + * diagnose bus bit 7 = ed_request + * diagnose bus bit 6 = gen_irq + * diagnose bus bit 5 = tx_en + * diagnose bus bit 4 = rx_en + * diagnose bus bit 3 = phy_en + * diagnose bus bit 2 = tx_valid + * diagnose bus bit 1 = rx_sof + * diagnose bus bit 0 = rx_eof + * + * dbg_control 0x02 Clocks and reset + * diagnose bus bit 7-3 = "00000" + * diagnose bus bit 2 = lp_clk divide by 2 + * diagnose bus bit 1 = mac_clk divide by 2 + * diagnose bus bit 0 = hclk divided by 2 + * + * dbg_control in range 0x02 - 0x0f Not used + * diagnose bus bit 7 - 0 = all '0' + * + * dbg_control in range 0x10 - 0x1f Debug rx pipeline + * + * 0x10 Rx phy signals + * diagnose_bus bit 7 = rx_enable towards the rx_pipeline + * diagnose bus bit 6 = rx_sof from phy + * diagnose bus bit 5-2 = rx_data from phy + * diagnose bus bit 1 = rx_eof to phy + * diagnose bus bit 0 = rx_sof event from rx_mac_timing block + * + * 0x11 Rx sof and length + * diagnose_bus bit 7 = rx_sof + * diagnose bus bit 6-0 = rx_mac_length from rx_mac_timing block + * + * 0x12 Rx mac timing output + * diagnose_bus bit 7 = Enable from rx_mac_timing block + * diagnose bus bit 6 = Sop from rx_mac_timing block + * diagnose bus bit 5 = Eop from rx_mac_timing block + * diagnose bus bit 4 = Crc from rx_mac_timing block + * diagnose bus bit 3 = Err from rx_mac_timing block + * diagnose bus bit 2 = Drop from rx_mac_timing block + * diagnose bus bit 1 = Forward from rx_mac_timing block + * diagnose bus bit 0 = rx_sof + * + * 0x13 Rx mac frame parser output + * diagnose_bus bit 7 = Enable from mac_frame_parser block + * diagnose bus bit 6 = Sop from mac_frame_parser block + * diagnose bus bit 5 = Eop from mac_frame_parser block + * diagnose bus bit 4 = Crc from mac_frame_parser block + * diagnose bus bit 3 = Err from mac_frame_parser block + * diagnose bus bit 2 = Drop from mac_frame_parser block + * diagnose bus bit 1 = Forward from mac_frame_parser block + * diagnose bus bit 0 = rx_sof + * + * 0x14 Rx status to Umac + * diagnose_bus bit 7 = rx_frame_stat_umac.crc16_error + * diagnose bus bit 6 = rx_frame_stat_umac.res_frm_type_error + * diagnose bus bit 5 = rx_frame_stat_umac.res_frm_version_error + * diagnose bus bit 4 = rx_frame_stat_umac.dpanid_error + * diagnose bus bit 3 = rx_frame_stat_umac.daddr_error + * diagnose bus bit 2 = rx_frame_stat_umac.spanid_error + * diagnose bus bit 1 = rx_frame_stat_umac.ispan_coord_error + * diagnose bus bit 0 = rx_sof + * + * 0x15 Rx status to lmac + * diagnose_bus bit 7 = rx_frame_stat.packet_valid + * diagnose bus bit 6 = rx_frame_stat.rx_sof_e + * diagnose bus bit 5 = rx_frame_stat.rx_eof_e + * diagnose bus bit 4 = rx_frame_stat.wakeup_frame + * diagnose bus bit 3-1 = rx_frame_stat.frame_type + * diagnose bus bit 0 = rx_frame_stat.rx_sqnr_valid + * + * 0x16 Rx buffer control + * diagnose_bus bit 7-4 = prov_from_swio.rx_read_buf_ptr + * diagnose bus bit 3-0 = stat_to_swio.rx_write_buf_ptr + * + * 0x17 Rx interrupts + * diagnose_bus bit 7 = stat_to_swio.rx_buf_avail_e + * diagnose bus bit 6 = stat_to_swio.rx_buf_full + * diagnose bus bit 5 = stat_to_swio.rx_buf_overflow_e + * diagnose bus bit 4 = stat_to_swio.rx_sof_e + * diagnose bus bit 3 = stat_to_swio.rxbyte_e + * diagnose bus bit 2 = rx_frame_ctrl.rx_enable + * diagnose bus bit 1 = rx_eof + * diagnose bus bit 0 = rx_sof + * + * 0x18 diagnose_bus bit 7-3 = + * Prt statements mac frame parser + * 0 Reset + * 1 Multipurpose frame with no dpanid and macImplicitBroadcast is false and not pan cooordinator dropped + * 2 Multipurpose frame with no dest address and macImplicitBroadcast is false and not pan cooordinator dropped + * 3 RX unsupported frame type detected + * 4 RX non Beacon frame detected and dropped in RxBeaconOnly mode + * 5 RX frame passed due to macAlwaysPassFrmType set + * 6 RX unsupported da_mode = 01 for frame_version 0x0- detected + * 7 RX unsupported sa_mode = 01 for frame_version 0x0- detected + * 8 Data or command frame with no dpanid and macImplicitBroadcast is false and not pan cooordinator dropped + * 9 Data or command frame with no dest address and macImplicitBroadcast is false and not pan cooordinator dropped + * 10 RX unsupported frame_version detected + * 11 Multipurpose frame with no dpanid and macImplicitBroadcast is false and not pan cooordinator dropped + * 12 Multipurpose frame with no dest address and macImplicitBroadcast is false and not pan cooordinator dropped + * 13 RX unsupported frame_version detected + * 14 RX Destination PAN Id check failed + * 15 RX Destination address (1 byte) check failed + * 16 RX Destination address (2 byte) check failed + * 17 RX Destination address (8 byte) check failed + * 18 RX Source PAN Id check for Beacon frames failed + * 19 RX Source PAN Id check failed + * 20 Auxiliary Security Header security control word received + * 21 Auxiliary Security Header unsupported_legacy received frame_version 00 + * 22 Auxiliary Security Header unsupported_legacy security frame_version 11 + * 23 Auxiliary Security Header frame counter field received + * 24 Auxiliary Security Header Key identifier field received + * 25 Errored Destination Wakeup frame found send to Umac, not indicated towards lmac controller + * 26 MacAlwaysPassWakeUpFrames = 1, Wakeup frame found send to Umac, not indicated towards lmac controller + * 27 Wakeup frame found send to lmac controller and Umac + * 28 Wakeup frame found send to lmac controller, dropped towards Umac + * 29 Command frame with data_request command received + * 30 Coordinator realignment frame received + * 31 Not Used + * diagnose bus bit 2-0 = frame_type + * + * 0x19 diagnose_bus bit 7-4 = + * Framestates mac frame parser + * 0 idle_state + * 1 fr_ctrl_state + * 2 fr_ctrl_long_state + * 3 seq_nr_state + * 4 dest_pan_id_state + * 5 dest_addr_state + * 6 src_pan_id_state + * 7 src_addr_state + * 8 aux_sec_hdr_state + * 9 hdr_ie_state + * 10 pyld_ie_state + * 11 ignore_state + * 12-16 Not used + * diagnose bus bit 3 = rx_mac_sof_e + * diagnose bus bit 2-0 = frame_type + * + * 0x1a diagnose_bus bit 7 = execute_sa_match + * diagnose_bus bit 6 = sa_match_found (1 clk delayed) + * diagnose_bus bit 5 = prov_from_swio.FP_override + * diagnose_bus bit 4 = fp_mac_drdy + * diagnose_bus bit 3 = fp_mac_ld_strb + * diagnose_bus bit 2-1 = rx_frame_stat_lmac.rx_sa_mode + * diagnose_bus bit 0 = rx_mac_sof_e + * + * 0x1b diagnose_bus bit 7 = execute_sa_match + * diagnose_bus bit 6-2 = fp_mac_addr_cnt + * diagnose_bus bit 1 = fp_bit_decided + * diagnose_bus bit 0 = prov_from_swio.Addr_tab_match_FP_value + * + * 0x1c diagnose_bus bit 7 = execute_sa_match + * diagnose_bus bit 6 = sa_match_found (1 clk delayed) + * diagnose_bus bit 5 = fp_mac_rdata(68): Short_LongNot + * diagnose_bus bit 4-1 = fp_mac_rdata(67 DOWNTO 64): SA valid bits + * diagnose_bus bit 0 = fp_mac_rdata(0): least significant bit from FPPR + * + * 0x1d diagnose_bus bit 7 = execute_sa_match + * diagnose_bus bit 6 = sa_match_found (1 clk delayed) + * diagnose_bus bit 5-0 = fp_mac_rdata(5 DOWNTO 0): 6 least significant bits from FPPR + * + * 0x1e-0x1f Not Used + * diagnose bus bit 7-0 = all '0' + * + * dbg_control in range 0x20 - 0x2f Debug tx pipeline + * 0x20 Top and bottom interfaces tx datapath + * diagnose_bus bit 7 = tx_mac_ld_strb + * diagnose bus bit 6 = tx_mac_drdy + * diagnose bus bit 5 = tx_valid + * diagnose bus bit 4-1 = tx_data + * diagnose bus bit 0 = symbol_ena + * + * 0x21 Control signals for tx datapath + * diagnose_bus bit 7 = TxTransparentMode + * diagnose bus bit 6 = ctrl_lmac_to_tx.CRC16_ena + * diagnose bus bit 5 = ctrl_lmac_to_tx.tx_start + * diagnose bus bit 4 = ctrl_lmac_to_tx.gen_ack + * diagnose bus bit 3 = ctrl_lmac_to_tx.gen_wu + * diagnose bus bit 2-1 = ctrl_lmac_to_tx.tx_frame_nmbr + * diagnose bus bit 0 = tx_valid + * + * 0x22 Control signals for wakeup frames + * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start + * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_wu + * diagnose bus bit 5-1 = ctrl_lmac_to_tx.gen_wu_RZ(4 DOWNTO 0) + * diagnose bus bit 0 = ctrl_tx_to_lmac.tx_rz_zero + * + * 0x23 Data signals for wakeup frame + * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start + * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_wu + * diagnose bus bit 5 = tx_valid + * diagnose bus bit 4-1 = tx_data + * diagnose bus bit 0 = ctrl_tx_to_lmac.tx_rz_zero + * + * 0x24 Data and control ack frame + * diagnose_bus bit 7 = ctrl_lmac_to_tx.tx_start + * diagnose bus bit 6 = ctrl_lmac_to_tx.gen_ack + * diagnose bus bit 5 = tx_valid + * diagnose bus bit 4-1 = tx_data + * diagnose bus bit 0 = symbol_ena + * + * 0x25 FP bit decision + * diagnose_bus bit 7 = fp_bit_decided + * diagnose bus bit 6 = execute_sa_match + * diagnose bus bit 5 = ctrl_lmac_to_tx.rx_fp_decided + * diagnose bus bit 4-3 = ctrl_lmac_to_tx.rx_sa_mode + * diagnose bus bit 2 = swio_to_lmac_tx.FP_override + * diagnose bus bit 1 = swio_to_lmac_tx.FP_force_value + * diagnose bus bit 0 = tx_valid + * + * 0x2a Event counter, 8 least significant bits, synchronized to mac_clk + * + * 0x2b symbol counter, 8 fore most least significant bits (15 downto 8) + * + * 0x2c symbol counter, 8 least significant bits (7 downto 0) + * + * + * dbg_control in range 0x2e - 0x3f Debug lmac_controller + * 0x2d Not Used + * diagnose bus bit 7-0 = all '0' + * + * 0x23 Phy_transaction last minute changes due to corner cases + * diagnose_bus bit 7 = phy_transaction + * diagnose_bus bit 6 = symbol_timer_preset + * diagnose_bus bit 5 = symbol_timer_almost_ready + * diagnose_bus bit 4 = csl_idle_rx + * diagnose_bus bit 3 = csl_data_rx + * diagnose_bus bit 2 = rx_enable_os_capt + * diagnose_bus bit 1 = rx_enable_os_capt_done + * diagnose_bus bit 0 = phy_en_ready + * + * 0x2f Phy control in combination with arbiter state machine + * diagnose_bus bit 7 = phy_transaction + * diagnose_bus bit 6 = arb_phy_trans_res_store + * diagnose_bus bit 5-0 = arb_debug_info + * + * 0x30 Phy signals + * diagnose_bus bit 7 = phy_en + * diagnose bus bit 6 = tx_en + * diagnose bus bit 5 = rx_en + * diagnose bus bit 4-1 = phyattr(3 downto 0) + * diagnose bus bit 0 = ed_request + * + * 0x31 Phy enable and detailed statemachine info + * diagnose_bus bit 7 = phy_en + * diagnose bus bit 6-0 = prt statements detailed statemachine info + * 0 Reset + * 1 MAIN_STATE_IDLE TX_ACKnowledgement frame skip CSMA_CA + * 2 MAIN_STATE_IDLE : Wake-Up frame resides in buffer no + * 3 MAIN_STATE_IDLE : TX frame in TSCH mode + * 4 MAIN_STATE_IDLE : TX frame + * 5 MAIN_STATE_IDLE : goto SINGLE_CCA + * 6 MAIN_STATE_IDLE : goto Energy Detection + * 7 MAIN_STATE_IDLE : goto RX + * 8 MAIN_STATE_IDLE de-assert phy_en wait for + * 9 MAIN_STATE_IDLE Start phy_en and assert phy_en wait for : + * 10 MAIN_STATE_CSMA_CA_WAIT_FOR_METADATA framenr : + * 11 MAIN_STATE_CSMA_CA framenr : + * 12 MAIN_STATE_CSMA_CA start CSMA_CA + * 14 MAIN_STATE_CSMA_CA skip CSMA_CA + * 15 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Failed for CSL mode + * 16 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Failed + * 17 MAIN_STATE_WAIT_FOR_CSMA_CA csma_ca Success + * 18 MAIN_STATE_SINGLE_CCA cca failed + * 19 MAIN_STATE_SINGLE_CCA cca ok + * 20 MAIN_STATE_WAIT_ACK_DELAY wait time elapsed + * 21 MAIN_STATE_WAIT ACK_DELAY : Send Ack in TSCH mode + * 22 MAIN_STATE_WAIT ACK_DELAY : Ack not scheduled in time in TSCH mode + * 23 MAIN_STATE_TSCH_TX_FRAME macTSRxTx time elapsed + * 24 MAIN_STATE_TX_FRAME it is CSL mode, start the WU seq for macWUPeriod + * 25 MAIN_STATE_TX_FRAME1 + * 26 MAIN_STATE_TX_FRAME_W1 exit, waited for : + * 27 MAIN_STATE_TX_FRAME_W2 exit, waited for : + * 28 MAIN_STATE_TX_WAIT_LAST_SYMBOL exit + * 29 MAIN_STATE_TX_RAMPDOWN_W exit, waited for : + * 30 MAIN_STATE_TX_PHYTRXWAIT exit, waited for : + * 31 MAIN_STATE_GEN_IFS , Ack with frame pending received + * 32 MAIN_STATE_GEN_IFS , Ack requested but DisRXackReceivedca is set + * 33 MAIN_STATE_GEN_IFS , instead of generating an IFS, switch the rx-on for an ACK + * 34 MAIN_STATE_GEN_IFS , generating an SIFS (Short Inter Frame Space) + * 35 MAIN_STATE_GEN_IFS , generating an LIFS (Long Inter Frame Space) + * 36 MAIN_STATE_GEN_IFS_FINISH in CSL mode, 'cslperiod_timer_ready' is ready sent the data frame + * 37 MAIN_STATE_GEN_IFS_FINISH in CSL mode, 'Rendezvous zero time not yet transmitted sent another WU frame + * 38 MAIN_STATE_GEN_IFS_FINISH exit, corrected for : + * 39 MAIN_STATE_GEN_IFS_FINISH in CSL mode, rx_resume_after_tx is set + * 40 MAIN_STATE_SENT_STATUS CSLMode wu_sequence_done_flag : + * 41 MAIN_STATE_ADD_DELAY exit, goto RX for frame pending time + * 42 MAIN_STATE_ADD_DELAY exit, goto IDLE + * 43 MAIN_STATE_RX switch the RX from off to on + * 44 MAIN_STATE_RX_WAIT_PHYRXSTART waited for + * 45 MAIN_STATE_RX_WAIT_PHYRXLATENCY start the MacAckDuration timer + * 46 MAIN_STATE_RX_WAIT_PHYRXLATENCY start the ack wait timer + * 47 MAIN_STATE_RX_WAIT_PHYRXLATENCY NORMAL mode : start rx_duration + * 48 MAIN_STATE_RX_WAIT_PHYRXLATENCY TSCH mode : start macTSRxWait (macTSRxWait) timer + * 49 MAIN_STATE_RX_WAIT_PHYRXLATENCY CSL mode : start the csl_rx_duration (macCSLsamplePeriod) timer + * 50 MAIN_STATE_RX_WAIT_PHYRXLATENCY CSL mode : start the csl_rx_duration (macCSLdataPeriod) timer + * 51 MAIN_STATE_RX_CHK_EXPIRED 1 ackwait_timer_ready or ack_received_ind + * 52 MAIN_STATE_RX_CHK_EXPIRED 2 normal_mode. ACK with FP bit set, start frame pending timer + * 54 MAIN_STATE_RX_CHK_EXPIRED 4 RxAlwaysOn is set to 0 + * 55 MAIN_STATE_RX_CHK_EXPIRED 5 TSCH mode valid frame rxed + * 56 MAIN_STATE_RX_CHK_EXPIRED 6 TSCH mode macTSRxwait expired + * 57 MAIN_STATE_RX_CHK_EXPIRED 7 macCSLsamplePeriod timer ready + * 58 MAIN_STATE_RX_CHK_EXPIRED 8 csl_mode. Data frame recieved with FP bit set, increment RX duration time + * 59 MAIN_STATE_RX_CHK_EXPIRED 9 CSL mode : Received wu frame in data listening period restart macCSLdataPeriod timer + * 60 MAIN_STATE_RX_CHK_EXPIRED 10 csl_rx_duration_ready or csl data frame received: + * 61 MAIN_STATE_RX_CHK_EXPIRED 11 normal_mode. FP bit is set, start frame pending timer + * 62 MAIN_STATE_RX_CHK_EXPIRED 12 normal mode rx_duration_timer_ready and frame_pending_timer_ready + * 63 MAIN_STATE_RX_CHK_EXPIRED 13 acknowledge frame requested + * 64 MAIN_STATE_RX_CHK_EXPIRED 14 Interrupt to sent a frame. found_tx_packet + * 65 MAIN_STATE_CSL_RX_IDLE_END RZ time is far away, switch receiver Off and wait for csl_rx_rz_time before switching on + * 66 MAIN_STATE_CSL_RX_IDLE_END RZ time is not so far away, keep receiver On and wait for + * 67 MAIN_STATE_RX_START_PHYRXSTOP ack with fp received keep rx on + * 68 MAIN_STATE_RX_START_PHYRXSTOP switch the RX from on to off + * 69 MAIN_STATE_RX_WAIT_PHYRXSTOP acknowledge done : switch back to finish TX + * 70 MAIN_STATE_RX_WAIT_PHYRXSTOP switch the RX off + * 71 MAIN_STATE_ED switch the RX from off to on + * 72 MAIN_STATE_ED_WAIT_PHYRXSTART waited for phyRxStartup + * 73 MAIN_STATE_ED_WAIT_EDSCANDURATION waited for EdScanDuration + * 74 MAIN_STATE_ED_WAIT_PHYRXSTOP end of Energy Detection, got IDLE + * 75 MAIN_STATE_IDLE, use_legacy_phy_en = '0', rx_enable_os_capt detected and not yet 1 us 101 of PHY_EN done. + * 76 - 127 Not used + * + * 0x32 RX enable and detailed statemachine info + * diagnose_bus bit 7 = rx_en + * diagnose bus bit 6-0 = detailed statemachine info see dbg_control = 0x31 + * + * 0x33 TX enable and detailed statemachine info + * diagnose_bus bit 7 = tx_en + * diagnose bus bit 6-0 = detailed statemachine info see dbg_control = 0x31 + * + * 0x34 Phy enable, TX enable and Rx enable and state machine states + * diagnose_bus bit 7 = phy_en + * diagnose_bus bit 6 = tx_en + * diagnose_bus bit 5 = rx_en + * diagnose bus bit 4-0 = State machine states + * 1 MAIN_STATE_IDLE + * 2 MAIN_STATE_CSMA_CA_WAIT_FOR_METADATA + * 3 MAIN_STATE_CSMA_CA + * 4 MAIN_STATE_WAIT_FOR_CSMA_CA_0 + * 5 MAIN_STATE_WAIT_FOR_CSMA_CA + * 6 MAIN_STATE_SINGLE_CCA + * 7 MAIN_STATE_WAIT_ACK_DELAY + * 8 MAIN_STATE_TSCH_TX_FRAME + * 9 MAIN_STATE_TX_FRAME + * 10 MAIN_STATE_TX_FRAME1 + * 11 MAIN_STATE_TX_FRAME_W1 + * 12 MAIN_STATE_TX_FRAME_W2 + * 13 MAIN_STATE_TX_WAIT_LAST_SYMBOL + * 14 MAIN_STATE_TX_RAMPDOWN + * 15 MAIN_STATE_TX_RAMPDOWN_W + * 16 MAIN_STATE_TX_PHYTRXWAIT + * 17 MAIN_STATE_GEN_IFS + * 18 MAIN_STATE_GEN_IFS_FINISH + * 19 MAIN_STATE_SENT_STATUS + * 20 MAIN_STATE_ADD_DELAY + * 21 MAIN_STATE_TSCH_RX_ACKDELAY + * 22 MAIN_STATE_RX + * 23 MAIN_STATE_RX_WAIT_PHYRXSTART + * 24 MAIN_STATE_RX_WAIT_PHYRXLATENCY + * 25 MAIN_STATE_RX_CHK_EXPIRED + * 26 MAIN_STATE_CSL_RX_IDLE_END + * 27 MAIN_STATE_RX_START_PHYRXSTOP + * 28 MAIN_STATE_RX_WAIT_PHYRXSTOP + * 29 MAIN_STATE_ED + * 30 MAIN_STATE_ED_WAIT_PHYRXSTART + * 31 MAIN_STATE_ED_WAIT_EDSCANDURATION + * + * 0x35 lmac controller to tx interface with wakeup + * diagnose_bus bit 7 = tx_en + * diagnose_bus bit 6 = rx_en + * diagnose_bus bit 5 = ctrl_lmac_to_tx.gen_wu + * diagnose_bus bit 4 = ctrl_lmac_to_tx.gen_ack + * diagnose_bus bit 3-2 = ctrl_lmac_to_tx.tx_frame_nmbr + * diagnose_bus bit 1 = ctrl_lmac_to_tx.tx_start + * diagnose_bus bit 0 = ctrl_tx_to_lmac.tx_last_symbol + * + * 0x36 lmac controller to tx interface with frame pending + * diagnose_bus bit 7 = tx_en + * diagnose_bus bit 6 = rx_en + * diagnose_bus bit 5 = ctrl_lmac_to_tx.gen.fp_bit + * diagnose_bus bit 4 = ctrl_lmac_to_tx.gen_ack + * diagnose_bus bit 3-2 = ctrl_lmac_to_tx.tx_frame_nmbr + * diagnose_bus bit 1 = ctrl_lmac_to_tx.tx_start + * diagnose_bus bit 0 = ctrl_tx_to_lmac.tx_last_symbol + * + * 0x37 rx pipepline to lmac controller interface + * diagnose_bus bit 7 = tx_en + * diagnose_bus bit 6 = rx_en + * diagnose_bus bit 5 = ctrl_rx_to_lmac.rx_sof_e + * diagnose_bus bit 4 = ctrl_rx_to_lmac.rx_eof_e + * diagnose_bus bit 3 = ctrl_rx_to_lmac.packet_valid + * diagnose_bus bit 2 = ack_received_ind + * diagnose_bus bit 1 = ack_request_ind + * diagnose_bus bit 0 = ctrl_rx_to_lmac.data_request_frame + * + * 0x38 csl start + * diagnose_bus bit 7 = tx_en + * diagnose_bus bit 6 = rx_en + * diagnose_bus bit 5 = csl_start + * diagnose_bus bit 4-1 = swio_always_on_to_lmac_ctrl.tx_flag_stat + * diagnose_bus bit 0 = found_wu_packet; + * + * 0x39 Tsch TX ack timing + * diagnose_bus bit 7-4 = swio_always_on_to_lmac_ctrl.tx_flag_stat + * diagnose_bus bit 3 = tx_en + * diagnose_bus bit 2 = rx_en + * diagnose_bus bit 1 = ctrl_rx_to_lmac.packet_valid + * diagnose_bus bit 0 = one_us_timer_ready + * + * 0x3a Phy control and Phy status + * diagnose_bus bit 7 = phy_transaction + * diagnose_bus bit 6 = phy_en + * diagnose_bus bit 5 = rx_en + * diagnose_bus bit 4 = tx_en + * diagnose_bus bit 3 = cca_stat + * diagnose bus bit 2 = ed_request + * diagnose bus bit 1 = rx_enable_os_capt + * diagnose bus bit 0 = found_tx_packet + * + * 0x3b Phy control, incl old PHY_EN (to show the improvement using v2) + * diagnose_bus bit 7 = phy_transaction + * diagnose_bus bit 6 = phy_en + * diagnose_bus bit 5 = rx_en + * diagnose_bus bit 4 = tx_en + * diagnose_bus bit 3-0 = pti + * + * 0x3c Control signals for arbiter control state machine + * diagnose_bus bit 7 = phy_transaction + * diagnose_bus bit 6 = arb_phy_trans_set_store + * diagnose_bus bit 5 = arb_phy_trans_clr_store + * diagnose_bus bit 4 = arb_phy_trans_res_store + * diagnose_bus bit 3 = found_tx_packet + * diagnose bus bit 2 = found_tx_packet_next + * diagnose bus bit 1 = found_wu_packet + * diagnose bus bit 0 = req_for_ack_flag + * + * 0x3d Output of check which packet to send + * diagnose_bus bit 7 = phy_transaction + * diagnose_bus bit 6 = LmacReady4sleep + * diagnose_bus bit 5-4 = found_tx_number + * diagnose_bus bit 3-2 = found_tx_number_next + * diagnose bus bit 1-0 = found_wu_number + * + * 0x3e CSMA_CA and timer control + * diagnose_bus bit 7 = phy_transaction + * diagnose_bus bit 6 = Csma_ca_resume_stat + * diagnose_bus bit 5 = SingleCCA_os_capt + * diagnose_bus bit 4 = backoff_timer_preset + * diagnose_bus bit 3 = backoff_timer_almost_ready + * diagnose bus bit 2 = backoff_timer_ready + * diagnose bus bit 1 = arb_timer_preset + * diagnose bus bit 0 = arb_timer_ready + * + * 0x3f arbiter control state machine + * diagnose_bus bit 7 = phy_transaction + * diagnose_bus bit 6 = rx_en + * diagnose_bus bit 5 = arb_phy_trans_set_store + * diagnose_bus bit 4 = arb_phy_trans_clr_store + * diagnose_bus bit 3 = arb_phy_trans_res_store + * diagnose bus bit 2-0 = arb_state_info + * + * + * dbg_control in range 0x40 - 0x4f Debug security + * 0x40 Security control + * diagnose_bus bit 7 = swio_to_security.secStart + * diagnose_bus bit 6 = swio_to_security.secTxRxn + * diagnose_bus bit 5 = swio_to_security.secAbort + * diagnose_bus bit 4 = swio_to_security.secEncDecn + * diagnose_bus bit 3 = swio_from_security.secBusy + * diagnose_bus bit 2 = swio_from_security.secAuthFail + * diagnose_bus bit 1 = swio_from_security.secReady_e + * diagnose_bus bit 0 = '0' + * + * 0x41 Security ctlid access rx and tx + * diagnose_bus bit 7 = tx_sec_ci.ld_strb + * diagnose_bus bit 6 = tx_sec_ci.ctlid_rw + * diagnose_bus bit 5 = tx_sec_ci.selectp + * diagnose_bus bit 4 = tx_sec_co.d_rdy + * diagnose_bus bit 3 = rx_sec_ci.ld_strb + * diagnose_bus bit 2 = rx_sec_ci.ctlid_rw + * diagnose_bus bit 1 = rx_sec_ci.selectp + * diagnose_bus bit 0 = rx_sec_co.d_rdy + * + * 0x42 Security ctlid access tx with sec_wr_data_valid + * diagnose_bus bit 7 = tx_sec_ci.ld_strb + * diagnose_bus bit 6 = tx_sec_ci.ctlid_rw + * diagnose_bus bit 5 = tx_sec_ci.selectp + * diagnose_bus bit 4 = tx_sec_co.d_rdy + * diagnose_bus bit 3-0 = sec_wr_data_valid + * + * 0x43 Security ctlid access rx with sec_wr_data_valid + * diagnose_bus bit 7 = rx_sec_ci.ld_strb + * diagnose_bus bit 6 = rx_sec_ci.ctlid_rw + * diagnose_bus bit 5 = rx_sec_ci.selectp + * diagnose_bus bit 4 = rx_sec_co.d_rdy + * diagnose_bus bit 3-0 = sec_wr_data_valid + * + * 0x44-0x4f Not used + * diagnose bus bit 7 - 0 = all '0' + * + * dbg_control in range 0x50 - 0x5f AHB bus + * 0x50 ahb bus without hsize + * diagnose_bus bit 7 = hsel + * diagnose_bus bit 6-5 = htrans + * diagnose_bus bit 4 = hwrite + * diagnose_bus bit 3 = hready_in + * diagnose_bus bit 2 = hready_out + * diagnose_bus bit 1-0 = hresp + * + * 0x51 ahb bus without hwready_in and hresp(1) + * diagnose_bus bit 7 = hsel + * diagnose_bus bit 6-5 = htrans + * diagnose_bus bit 4 = hwrite + * diagnose_bus bit 3-2 = hhsize(1 downto 0) + * diagnose_bus bit 1 = hready_out + * diagnose_bus bit 0 = hresp(0) + * + * 0x52 Amba tx signals + * diagnose_bus bit 7 = ai_tx.penable + * diagnose_bus bit 6 = ai_tx.psel + * diagnose_bus bit 5 = ai_tx.pwrite + * diagnose_bus bit 4 = ao_tx.pready + * diagnose_bus bit 3 = ao_tx.pslverr + * diagnose_bus bit 2-1 = psize_tx + * diagnose_bus bit 0 = hready_out + * + * 0x53 Amba rx signals + * diagnose_bus bit 7 = ai_rx.penable + * diagnose_bus bit 6 = ai_rx.psel + * diagnose_bus bit 5 = ai_rx.pwrite + * diagnose_bus bit 4 = ao_rx.pready + * diagnose_bus bit 3 = ao_rx.pslverr + * diagnose_bus bit 2-1 = psize_rx + * diagnose_bus bit 0 = hready_out + * + * 0x54 Amba register map signals + * diagnose_bus bit 7 = ai_reg.penable + * diagnose_bus bit 6 = ai_reg.psel + * diagnose_bus bit 5 = ai_reg.pwrite + * diagnose_bus bit 4 = ao_reg.pready + * diagnose_bus bit 3 = ao_reg.pslverr + * diagnose_bus bit 2-1 = "00" + * diagnose_bus bit 0 = hready_out + * + * 0x55-0x5f Not used + * diagnose bus bit 7 - 0 = all '0' + */ +#define IND_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL IND_R_FTDF_ON_OFF_REGMAP_DEBUGCONTROL +#define MSK_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL 0xff +#define OFF_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_DBG_CONTROL 8 + +/* + * + * REGISTER: ftdf_on_off_regmap_txbyte_e + * + * Initialization value: 0x0 Initialization mask: 0x3 + * Access mode: E-RCW (event read/clear on write 1) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x40090394 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x3 + +/* + * + * Bit: ftdf_on_off_regmap_txbyte_e + * + * If set to '1', it indicates the first byte of a frame is transmitted + * This event bit contributes to ftdf_ce[4]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXBYTE_E IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_E +#define MSK_F_FTDF_ON_OFF_REGMAP_TXBYTE_E 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_TXBYTE_E 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBYTE_E 1 +/* + * + * Bit: ftdf_on_off_regmap_tx_last_symbol_e + * + * If set to '1', it indicates the last symbol of a frame is transmitted + * This event bit contributes to ftdf_ce[4]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_E +#define MSK_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_E 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_txbyte_m + * + * Initialization value: 0x0 Initialization mask: 0x3 + * Access mode: EM-RW (event mask) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x40090398 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x3 + +/* + * + * Bit: ftdf_on_off_regmap_txbyte_m + * + * Mask bit for event "txbyte_e". + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TXBYTE_M IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_M +#define MSK_F_FTDF_ON_OFF_REGMAP_TXBYTE_M 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_TXBYTE_M 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TXBYTE_M 1 +/* + * + * Bit: ftdf_on_off_regmap_tx_last_symbol_m + * + * Mask bit for event "tx_last_symbol_e". + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M IND_R_FTDF_ON_OFF_REGMAP_TXBYTE_M +#define MSK_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M 0x2 +#define OFF_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M 1 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_LAST_SYMBOL_M 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_tx_flag_s + * + * Initialization value: none. + * Access mode: S-R (state - read) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S 0x40090400 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S 0x1 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_S_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_S_INTVL 0x20 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_STAT_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_STAT_INTVL 0x20 + +/* + * + * Bit: ftdf_on_off_regmap_tx_flag_stat + * + * Tx meta data per entry: if set to '1', the packet is ready for transmission + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_S +#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_STAT 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_tx_flag_clear_e + * + * Initialization value: 0x0 Initialization mask: 0x1 + * Access mode: E-RCW (event read/clear on write 1) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x40090404 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x1 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_INTVL 0x20 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E_INTVL 0x20 + +/* + * + * Bit: ftdf_on_off_regmap_tx_flag_clear_e + * + * Tx meta data per entry: if set to '1' the LMAC hardware has cleared the tx_flag_stat status. + * This event bit contributes to ftdf_ce[4]. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E +#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_E 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_tx_flag_clear_m + * + * Initialization value: 0x0 Initialization mask: 0x1 + * Access mode: EM-RW (event mask) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x40090408 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x1 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_INTVL 0x20 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M_INTVL 0x20 + +/* + * + * Bit: ftdf_on_off_regmap_tx_flag_clear_m + * + * Tx meta data per entry: Mask bit for event "tx_flag_clear_e". + * The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M IND_R_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M +#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0x1 +#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR_M 1 + +/* + * + * REGISTER: ftdf_on_off_regmap_tx_priority + * + * Initialization value: 0x0 Initialization mask: 0xf1f + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0x40090410 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0xf1f +#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_INTVL 0x20 +#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_TX_PRIORITY_INTVL 0x20 +#define FTDF_ON_OFF_REGMAP_ISWAKEUP_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_ISWAKEUP_INTVL 0x20 +#define FTDF_ON_OFF_REGMAP_PTI_TX_NUM 0x4 +#define FTDF_ON_OFF_REGMAP_PTI_TX_INTVL 0x20 + +/* + * + * Field: ftdf_on_off_regmap_tx_priority + * + * Tx meta data per entry: Priority of packet + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY +#define MSK_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0xf +#define OFF_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_PRIORITY 4 +/* + * + * Bit: ftdf_on_off_regmap_IsWakeUp + * + * Tx meta data per entry: A basic wake-up frame can be generated by the UMAC in the Tx buffer. + * The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_ISWAKEUP IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY +#define MSK_F_FTDF_ON_OFF_REGMAP_ISWAKEUP 0x10 +#define OFF_F_FTDF_ON_OFF_REGMAP_ISWAKEUP 4 +#define SIZE_F_FTDF_ON_OFF_REGMAP_ISWAKEUP 1 +/* + * + * Field: ftdf_on_off_regmap_pti_tx + * + * This register has 4 entries, belonging to the entry of the Tx frame to send, to be used during transmitting frames and the CMSA-CA phase before (when requested). + * In TSCH mode this register shall be used during the time slot in which frames can be transmitted and consequently an Enhanced ACK can be received. + * Since pti_tx belongs to a certain frame to be transmitted, pti_tx can be considered as extra Tx meta data. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_PTI_TX IND_R_FTDF_ON_OFF_REGMAP_TX_PRIORITY +#define MSK_F_FTDF_ON_OFF_REGMAP_PTI_TX 0xf00 +#define OFF_F_FTDF_ON_OFF_REGMAP_PTI_TX 8 +#define SIZE_F_FTDF_ON_OFF_REGMAP_PTI_TX 4 + +/* + * + * REGISTER: ftdf_on_off_regmap_tx_set_os + * + * Initialization value: 0x0 Initialization mask: 0xf + * Access mode: OS-W (one-shot - write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TX_SET_OS 0x40090480 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_SET_OS 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TX_SET_OS 0xf + +/* + * + * Field: ftdf_on_off_regmap_tx_flag_set + * + * Tx meta data per entry: if set to '1', the tx_flag_stat will be set to '1'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET IND_R_FTDF_ON_OFF_REGMAP_TX_SET_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET 0xf +#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_SET 4 + +/* + * + * REGISTER: ftdf_on_off_regmap_tx_clear_os + * + * Initialization value: 0x0 Initialization mask: 0xf + * Access mode: OS-W (one-shot - write) + */ +#define IND_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS 0x40090484 +#define SIZE_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS 0x4 +#define MSK_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS 0xf + +/* + * + * Field: ftdf_on_off_regmap_tx_flag_clear + * + * Tx meta data per entry: if set to '1', the tx_flag_stat will be cleared to '0'. + */ +#define IND_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR IND_R_FTDF_ON_OFF_REGMAP_TX_CLEAR_OS +#define MSK_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR 0xf +#define OFF_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR 0 +#define SIZE_F_FTDF_ON_OFF_REGMAP_TX_FLAG_CLEAR 4 + +/* + * + * REGISTER: ftdf_always_on_regmap_wakeup_control + * + * Initialization value: 0x40000000 Initialization mask: 0xe1ffffff + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL 0x40091000 +#define SIZE_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL 0x4 +#define MSK_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL 0xe1ffffff + +/* + * + * Field: ftdf_always_on_regmap_WakeUpIntThr + * + * Threshold for wake-up interrupt. When WakeUpEnable is set to '1' and the Wake-up (event) counter matches this value, the interrupt WAKEUP_IRQ is set to '1' for the duration of one LP_CLK period. + */ +#define IND_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL +#define MSK_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 0x1ffffff +#define OFF_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 0 +#define SIZE_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPINTTHR 25 +/* + * + * Bit: ftdf_always_on_regmap_WakeUpEnable + * + * If set to '1', the WakeUpIntThr is enabled to generate an WAKEUP_IRQ interrupt. + */ +#define IND_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL +#define MSK_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE 0x20000000 +#define OFF_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE 29 +#define SIZE_F_FTDF_ALWAYS_ON_REGMAP_WAKEUPENABLE 1 +/* + * + * Field: ftdf_always_on_regmap_WakeUp_mode + * + * The Control register WakeUp_mode controls the behavior of the Event counter: + * 0d = off, 1d = free running (default), 2d = one shot with auto clear, 3d = configurable period (timer + * mode). + */ +#define IND_F_FTDF_ALWAYS_ON_REGMAP_WAKEUP_MODE IND_R_FTDF_ALWAYS_ON_REGMAP_WAKEUP_CONTROL +#define MSK_F_FTDF_ALWAYS_ON_REGMAP_WAKEUP_MODE 0xc0000000 +#define OFF_F_FTDF_ALWAYS_ON_REGMAP_WAKEUP_MODE 30 +#define SIZE_F_FTDF_ALWAYS_ON_REGMAP_WAKEUP_MODE 2 + +/* + * + * REGISTER: ftdf_fp_processing_ram_long_addr_0 + * + * Initialization value: none. + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_0 0x40092000 +#define SIZE_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_0 0x4 +#define MSK_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_0 0xffffffff +#define FTDF_FP_PROCESSING_RAM_LONG_ADDR_0_NUM 0x18 +#define FTDF_FP_PROCESSING_RAM_LONG_ADDR_0_INTVL 0x10 +#define FTDF_FP_PROCESSING_RAM_EXP_SA_L_NUM 0x18 +#define FTDF_FP_PROCESSING_RAM_EXP_SA_L_INTVL 0x10 + +/* + * + * Field: ftdf_fp_processing_ram_Exp_SA_l + * + * Lowest part of the 64 bits long source address or SA entry 1 resp. SA entry 0 in case of short source address. + */ +#define IND_F_FTDF_FP_PROCESSING_RAM_EXP_SA_L IND_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_0 +#define MSK_F_FTDF_FP_PROCESSING_RAM_EXP_SA_L 0xffffffff +#define OFF_F_FTDF_FP_PROCESSING_RAM_EXP_SA_L 0 +#define SIZE_F_FTDF_FP_PROCESSING_RAM_EXP_SA_L 32 + +/* + * + * REGISTER: ftdf_fp_processing_ram_long_addr_1 + * + * Initialization value: none. + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_1 0x40092004 +#define SIZE_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_1 0x4 +#define MSK_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_1 0xffffffff +#define FTDF_FP_PROCESSING_RAM_LONG_ADDR_1_NUM 0x18 +#define FTDF_FP_PROCESSING_RAM_LONG_ADDR_1_INTVL 0x10 +#define FTDF_FP_PROCESSING_RAM_EXP_SA_H_NUM 0x18 +#define FTDF_FP_PROCESSING_RAM_EXP_SA_H_INTVL 0x10 + +/* + * + * Field: ftdf_fp_processing_ram_Exp_SA_h + * + * Highest part of the 64 bits long source address or SA entry 3 resp. SA entry 2 in case of short source address. + */ +#define IND_F_FTDF_FP_PROCESSING_RAM_EXP_SA_H IND_R_FTDF_FP_PROCESSING_RAM_LONG_ADDR_1 +#define MSK_F_FTDF_FP_PROCESSING_RAM_EXP_SA_H 0xffffffff +#define OFF_F_FTDF_FP_PROCESSING_RAM_EXP_SA_H 0 +#define SIZE_F_FTDF_FP_PROCESSING_RAM_EXP_SA_H 32 + +/* + * + * REGISTER: ftdf_fp_processing_ram_size_and_val + * + * Initialization value: none. + * Access mode: C-RW (control - read/write) + */ +#define IND_R_FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL 0x40092008 +#define SIZE_R_FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL 0x4 +#define MSK_R_FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL 0x1f +#define FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL_NUM 0x18 +#define FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL_INTVL 0x10 +#define FTDF_FP_PROCESSING_RAM_VALID_SA_NUM 0x18 +#define FTDF_FP_PROCESSING_RAM_VALID_SA_INTVL 0x10 +#define FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT_NUM 0x18 +#define FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT_INTVL 0x10 + +/* + * + * Field: ftdf_fp_processing_ram_Valid_SA + * + * Indication which SA entry is valid (if set). In case of 4 short SA Valid bit 3 belongs to SA entry 3 etc. + * In case of a long SA Valid bit 0 is the valid indication. + */ +#define IND_F_FTDF_FP_PROCESSING_RAM_VALID_SA IND_R_FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL +#define MSK_F_FTDF_FP_PROCESSING_RAM_VALID_SA 0xf +#define OFF_F_FTDF_FP_PROCESSING_RAM_VALID_SA 0 +#define SIZE_F_FTDF_FP_PROCESSING_RAM_VALID_SA 4 +/* + * + * Bit: ftdf_fp_processing_ram_Short_LongNot + * + * A '1' indicates that Exp_SA contains four short SA's, a '0' indicates one long SA. + */ +#define IND_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT IND_R_FTDF_FP_PROCESSING_RAM_SIZE_AND_VAL +#define MSK_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT 0x10 +#define OFF_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT 4 +#define SIZE_F_FTDF_FP_PROCESSING_RAM_SHORT_LONGNOT 1 +#endif // dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A #endif // _ftdf diff --git a/third_party/dialog/DialogTools/bin2image b/third_party/dialog/DialogTools/bin2image deleted file mode 100755 index edc2d0367..000000000 Binary files a/third_party/dialog/DialogTools/bin2image and /dev/null differ diff --git a/third_party/dialog/DialogTools/cli_programmer b/third_party/dialog/DialogTools/cli_programmer index ead088cf1..379551d07 100755 Binary files a/third_party/dialog/DialogTools/cli_programmer and b/third_party/dialog/DialogTools/cli_programmer differ diff --git a/third_party/dialog/DialogTools/imgprep.sh b/third_party/dialog/DialogTools/imgprep.sh index 4de6c7621..4312e4d6d 100755 --- a/third_party/dialog/DialogTools/imgprep.sh +++ b/third_party/dialog/DialogTools/imgprep.sh @@ -1,4 +1,4 @@ arm-none-eabi-objcopy -O binary ../../../output/bin/arm-none-eabi-ot-cli-ftd ../../../output/bin/arm-none-eabi-ot-cli-ftd.bin -./bin2image qspi_cached ../../../output/bin/arm-none-eabi-ot-cli-ftd.bin ../../../output/bin/arm-none-eabi-ot-cli-ftd.img AD enable_uart + diff --git a/third_party/dialog/DialogTools/uartboot.bin b/third_party/dialog/DialogTools/uartboot.bin deleted file mode 100755 index e9d835ba0..000000000 Binary files a/third_party/dialog/DialogTools/uartboot.bin and /dev/null differ