mirror of
https://github.com/espressif/openthread.git
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e7a6bde56d
Use EDBG DGI SPI interface to put log. Signed-off-by: Oleksandr Grytsov <al1img@gmail.com>
202 lines
5.6 KiB
C
202 lines
5.6 KiB
C
/*
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* Copyright (c) 2017, The OpenThread Authors.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* @brief
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* This file includes the platform-specific initializers.
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*/
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#include "asf.h"
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#include <openthread-core-config.h>
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#include <openthread/platform/radio.h>
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#include "openthread-system.h"
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#include "platform-samr21.h"
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#include "utils/code_utils.h"
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#ifdef CONF_USER_ROW_EXIST
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#include "user_row.h"
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samr21UserRow *sUserRow = (samr21UserRow *)SAMR21_USER_ROW;
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#endif
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#ifdef CONF_KIT_DATA_EXIST
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#define EDBG_ADDRESS 0x28
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#define EDBG_KIT_DATA_TOKEN 0xD2;
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#define KIT_DATA_MAX_RETRY 1000
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static uint8_t sIeeeEui64[OT_EXT_ADDRESS_SIZE];
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struct i2c_master_module sI2cMasterInstance;
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static void configureI2cMaster()
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{
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/* Create and initialize config structure */
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struct i2c_master_config configI2c;
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i2c_master_get_config_defaults(&configI2c);
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/* Change pins */
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configI2c.pinmux_pad0 = EDBG_I2C_SERCOM_PINMUX_PAD0;
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configI2c.pinmux_pad1 = EDBG_I2C_SERCOM_PINMUX_PAD1;
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/* Initialize and enable device with config */
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i2c_master_init(&sI2cMasterInstance, EDBG_I2C_MODULE, &configI2c);
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i2c_master_enable(&sI2cMasterInstance);
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}
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static void getKitData()
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{
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uint8_t requestToken = EDBG_KIT_DATA_TOKEN;
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uint32_t timeout;
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struct i2c_master_packet masterPacket;
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/** Send the request token */
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masterPacket.address = EDBG_ADDRESS;
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masterPacket.data_length = 1;
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masterPacket.data = &requestToken;
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masterPacket.ten_bit_address = false;
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masterPacket.high_speed = false;
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masterPacket.hs_master_code = 0x0;
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timeout = 0;
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while (i2c_master_write_packet_wait_no_stop(&sI2cMasterInstance, &masterPacket) != STATUS_OK)
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{
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/* Increment timeout counter and check if timed out. */
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otEXPECT(timeout++ < KIT_DATA_MAX_RETRY);
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}
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/** Get the extension boards info */
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masterPacket.data_length = OT_EXT_ADDRESS_SIZE;
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masterPacket.data = sIeeeEui64;
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timeout = 0;
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while (i2c_master_read_packet_wait(&sI2cMasterInstance, &masterPacket) != STATUS_OK)
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{
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/* Increment timeout counter and check if timed out. */
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otEXPECT(timeout++ < KIT_DATA_MAX_RETRY);
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}
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exit:
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return;
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}
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#endif
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otInstance *sInstance;
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void boardInit(void)
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{
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struct port_config pin_conf;
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port_get_config_defaults(&pin_conf);
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pin_conf.direction = PORT_PIN_DIR_OUTPUT;
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port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
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port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
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port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
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port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
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port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
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port_pin_set_output_level(AT86RFX_SPI_SCK, true);
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port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
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port_pin_set_output_level(AT86RFX_SPI_CS, true);
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port_pin_set_output_level(AT86RFX_RST_PIN, true);
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port_pin_set_output_level(AT86RFX_SLP_PIN, true);
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pin_conf.direction = PORT_PIN_DIR_INPUT;
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port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
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}
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void samr21GetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64)
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{
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#if defined(CONF_KIT_DATA_EXIST)
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memcpy(aIeeeEui64, sIeeeEui64, OT_EXT_ADDRESS_SIZE);
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#elif defined(CONF_USER_ROW_EXIST)
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for (uint8_t i = 0; i < OT_EXT_ADDRESS_SIZE; i++)
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{
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aIeeeEui64[i] = sUserRow->mMacAddress[OT_EXT_ADDRESS_SIZE - i - 1];
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}
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#else
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#error Platform IEEE EUI-64 shall be provided
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#endif
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}
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void otSysInit(int argc, char *argv[])
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{
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system_clock_init();
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boardInit();
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#ifdef CONF_KIT_DATA_EXIST
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configureI2cMaster();
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getKitData();
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#endif
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#if (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED) || \
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(OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_NCP_SPINEL)
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samr21LogInit();
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#endif
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samr21AlarmInit();
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samr21RadioInit();
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}
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bool otSysPseudoResetWasRequested(void)
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{
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return false;
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}
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void otSysDeinit(void)
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{
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}
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void otSysProcessDrivers(otInstance *aInstance)
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{
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sInstance = aInstance;
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samr21UartProcess();
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samr21AlarmProcess(aInstance);
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samr21RadioProcess(aInstance);
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}
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