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revert tlg kernels for ease of merge

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Signed-off-by: Xiwen Yu <13230610+VALLIS-NERIA@users.noreply.github.com>
This commit is contained in:
Xiwen Yu 2025-08-19 11:44:36 +08:00
parent c1014e85cc
commit 4a95d88ce2
1948 changed files with 23857 additions and 8585 deletions
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54
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.cpp
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@ -65,6 +65,8 @@ std::vector<int64_t> prioritizePredefinedConfigs(int m, int n, int k, std::vecto
//
// Dummy
//
// Qwen3_235B_TP8_EP1_MoE_FC2 m=4096 k=192
if (n /* out_dim */ == 0 && k /* in_dim */ == 0)
{
auto pred = [](BatchedGemmConfig const& config)
@ -100,13 +102,27 @@ TrtllmGenBatchedGemmRunner::TrtllmGenBatchedGemmRunner(TrtllmGenBatchedGemmRunne
auto const options = configs[i].mOptions;
auto const tileSize = mOptions.transposeMmaOutput ? options.mTileN : options.mTileM;
// When we include low-latency kernels we can set transposeMmaOutput via constructor
if (options.mDtypeA == mOptions.eltType && options.mDtypeC == mOptions.outputType
&& options.mUseDeepSeekFp8 == mOptions.deepSeekFp8
if (options.mDtypeA == mOptions.dtypeA && options.mDtypeB == mOptions.dtypeB
&& options.mDtypeC == mOptions.dtypeC && options.mUseDeepSeekFp8 == mOptions.deepSeekFp8
&& options.mTransposeMmaOutput == mOptions.transposeMmaOutput
&& (!doesRouteImplUseNoRoute(options.mRouteImpl)) == mOptions.routeAct
&& options.mFusedAct == mOptions.fusedAct && options.mIsStaticBatch == mOptions.staticBatch
&& tileSize == mOptions.tileSize)
{
// FIXME: Disable split-k for now.
if (options.mClusterDimZ != 1)
{
continue;
}
if (options.mFusedAct)
{
if (options.mActType != static_cast<batchedGemm::gemmGatedAct::ActType>(mOptions.actType))
{
continue;
}
}
if (mOptions.transposeMmaOutput && options.mEpilogueTileM == mOptions.epilogueTileM)
{
mPassingConfigIndices.push_back(i);
@ -146,9 +162,10 @@ size_t TrtllmGenBatchedGemmRunner::getWorkspaceSizeInBytes(int32_t m, int32_t n,
void TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens,
int32_t numTokens, int32_t numBatches, int32_t maxNumCtasInBatchDim, void const* a, void const* sfA, void const* b,
void const* sfB, void const* perTokensSfA, void const* perTokensSfB, float const* scaleC, float const* scaleGateC,
void* c, void* outSfC, int32_t const* routeMap, int32_t const* totalNumPaddedTokens,
int32_t const* ctaIdxXyToBatchIdx, int32_t const* ctaIdxXyToMnLimit, int32_t const* numNonExitingCtas,
void* workspace, CUstream stream, int device, int32_t configIndex)
float const* ptrBias, float const* ptrAlpha, float const* ptrBeta, float const* ptrClampLimit, void* c,
void* outSfC, int32_t const* routeMap, int32_t const* totalNumPaddedTokens, int32_t const* ctaIdxXyToBatchIdx,
int32_t const* ctaIdxXyToMnLimit, int32_t const* numNonExitingCtas, void* workspace, CUstream stream, int device,
int32_t configIndex)
{
auto bmm = BatchedGemmInterface();
@ -200,6 +217,10 @@ void TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k, std::vecto
gemmData.mInputBuffers.mPtrScaleGate = scaleGateC;
gemmData.mInputBuffers.mPtrPerTokenSfA = mOptions.transposeMmaOutput ? perTokensSfB : perTokensSfA;
gemmData.mInputBuffers.mPtrPerTokenSfB = mOptions.transposeMmaOutput ? perTokensSfA : perTokensSfB;
gemmData.mInputBuffers.mPtrBias = ptrBias;
gemmData.mInputBuffers.mPtrSwiGluAlpha = ptrAlpha;
gemmData.mInputBuffers.mPtrSwiGluBeta = ptrBeta;
gemmData.mInputBuffers.mPtrClampLimit = ptrClampLimit;
gemmData.mInputBuffers.mPtrRouteMap = routeMap;
@ -242,7 +263,22 @@ void TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k, std::vecto
// Dispatch with block scaling factors and with static batching.
run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0, a, sfA, b, sfB,
/* perTokensSfA */ nullptr, /* perTokensSfB */ nullptr,
/* scaleC */ nullptr, /* scaleGateC */ nullptr, c, outSfC,
/* scaleC */ nullptr, /* scaleGateC */ nullptr, /* ptrBias */ nullptr, /* ptrAlpha */ nullptr,
/* ptrBeta */ nullptr, /* ptrClampLimit */ nullptr, c, outSfC,
/* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,
/* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,
/* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex);
}
void TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens,
void const* a, void const* sfA, void const* b, void const* sfB, float const* ptrBias, float const* ptrAlpha,
float const* ptrBeta, float const* ptrClampLimit, void* c, void* outSfC, void* workspace, CUstream stream,
int device, int32_t configIndex)
{
// Dispatch with block scaling factors and with static batching.
run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0, a, sfA, b, sfB,
/* perTokensSfA */ nullptr, /* perTokensSfB */ nullptr,
/* scaleC */ nullptr, /* scaleGateC */ nullptr, ptrBias, ptrAlpha, ptrBeta, ptrClampLimit, c, outSfC,
/* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,
/* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,
/* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex);
@ -255,7 +291,9 @@ void TrtllmGenBatchedGemmRunner::run(int32_t m, int32_t n, int32_t k, std::vecto
// Dispatch with block scaling factors and with static batching.
run(m, n, k, batchedTokens, /* numTokens */ 0, batchedTokens.size(), /* maxNumCtasInBatchDim */ 0, a,
/* sfA */ nullptr, b, /* sfB */ nullptr, /* perTokensSfA */ nullptr, /* perTokensSfB */ nullptr, scaleC,
scaleGateC, c, /* outSfC */ nullptr,
scaleGateC, /* ptrBias */ nullptr, /* ptrAlpha */ nullptr, /* ptrBeta */ nullptr, /* ptrClampLimit */ nullptr,
c,
/* outSfC */ nullptr,
/* routeMap */ nullptr, /* totalNumPaddedTokens */ nullptr,
/* ctaIdxXyToBatchIdx */ nullptr, /* ctaIdxXyToMnLimit */ nullptr,
/* numNonExitingCtas */ nullptr, workspace, stream, device, configIndex);
@ -281,7 +319,6 @@ std::vector<int64_t> TrtllmGenBatchedGemmRunner::getValidConfigIndices(int32_t m
gemmData.mProblemDimensions.mRank = 0;
gemmData.mProblemDimensions.mWorldSize = 1;
gemmData.mProblemDimensions.mMaxNumCtasInTokenDim = maxNumCtasInBatchDim;
// Tier 0: K < tileK, prefer higher efficiency.
auto cmpTier0 = [&configs, &gemmData](int64_t idx0, int64_t idx1)
{
@ -343,7 +380,6 @@ std::vector<int64_t> TrtllmGenBatchedGemmRunner::getValidConfigIndices(int32_t m
}
return false;
};
// Sort configs by options.
std::vector<int64_t> sortedIndices = mPassingConfigIndices;
std::sort(sortedIndices.begin(), sortedIndices.end(), cmpTier0);

30
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/KernelRunner.h
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@ -27,10 +27,28 @@ namespace tensorrt_llm
namespace kernels
{
// Keep this in sync with the ActType in
// cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/GemmGatedActOptions.h
enum class ActType
{
// For ActType == SwiGlu, ideally we would like to have something like
// gatedAct = scaleC * (x0 * scaleAb + beta) * ((x1 * scaleGate) * sigmoid(alpha * x1 *
// scaleGate)).
// But for now, we use the simplified version
// gatedAct = scaleC' * (x0 + beta') * ((x1 * scaleGate) * sigmoid(alpha * x1 * scaleGate)),
// where x0 and x1 are the raw numbers from Gemm, while scaleC and scaleGate are input scales,
// beta' = beta / scaleAb, scaleC' = scaleC * scaleAb.
//
// GatedSilu is a special case of SwiGlu where the alpha is 1.0 and the beta is 0.0.
SwiGlu
};
struct TrtllmGenBatchedGemmRunnerOptions
{
batchedGemm::trtllm::gen::Dtype eltType;
batchedGemm::trtllm::gen::Dtype outputType;
batchedGemm::trtllm::gen::Dtype dtypeA;
batchedGemm::trtllm::gen::Dtype dtypeB;
batchedGemm::trtllm::gen::Dtype dtypeC;
ActType actType{ActType::SwiGlu};
bool deepSeekFp8{false};
bool fusedAct{false};
bool routeAct{false};
@ -53,7 +71,8 @@ public:
void run(int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,
int32_t numBatches, int32_t maxNumCtasInBatchDim, void const* a, void const* sfA, void const* b,
void const* sfB, void const* perTokensSfA, void const* perTokensSfB, float const* scaleC,
float const* scaleGateC, void* c, void* outSfC, int32_t const* routeMap, int32_t const* totalNumPaddedTokens,
float const* scaleGateC, float const* bias, float const* swiGluAlpha, float const* swiGluBeta,
float const* clampLimit, void* c, void* outSfC, int32_t const* routeMap, int32_t const* totalNumPaddedTokens,
int32_t const* ctaIdxXyToBatchIdx, int32_t const* ctaIdxXyToMnLimit, int32_t const* numNonExitingCtas,
void* workspace, CUstream stream, int device, int32_t configIndex);
@ -62,6 +81,11 @@ public:
void const* b, void const* sfB, void* c, void* outSfC, void* workspace, CUstream stream, int device,
int32_t configIndex);
void run(int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, void const* a, void const* sfA,
void const* b, void const* sfB, float const* bias, float const* swiGluAlpha, float const* swiGluBeta,
float const* clampLimit, void* c, void* outSfC, void* workspace, CUstream stream, int device,
int32_t configIndex);
// FP8 per-tensor scaling GEMM
void run(int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, void const* a, void const* b,
float const* scaleC, float const* scaleGateC, void* c, void* workspace, CUstream stream, int device,

25
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmInterface.h
View File

@ -247,35 +247,10 @@ struct BatchedGemmData
// The clamp limit for the accumulator before applying the activation.
// Shape is [B].
// Clamp is INF if nullptr.
// When the input is FP8 or NVFP4, the clamp has to be scaled by limit' = limit / dequantAb.
// If applied on SwiGlu, it will be:
//
// x_glu = x_glu.clamp(min=None, max=limit)
// x_linear = x_linear.clamp(min=-limit, max=limit)
//
// The given clamp limit applies to the dequantized values, so the order of operations would
// look something like this:
//
// x0 = x0 * dqAb
// x0 = clamp(x0, none, limit)
// x0 = x0 * sigmoid(alpha * x0)
// x1 = dqAb * x1
// x1 = clamp(x1, -limit, limit)
// out = qC * (x1 + beta) * x0
//
// Given that the dqAb and qC are combined into scaleC, we can bring the dqAb into the clamp
// limit and apply the clamping prior to dequantization:
//
// x0 = clamp(x0, none, limit / dqAb)
// x0 = x0 * dqAb
// x0 = x0 * sigmoid(alpha * x0)
// x1 = clamp(x1, -limit / dqAb, limit / dqAb)
// scaleC = dqAb * qC
// beta' = beta / dqAb
// out = scaleC * (x1 + beta') * x0
//
// Note this assumes that scaleAb == scaleGate which is true in TRT-LLM MoE use-case
//
float const* mPtrClampLimit{nullptr};
// The alpha and beta for SwiGlu.

56
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/BatchedGemmOptions.h
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@ -99,7 +99,7 @@ struct BatchedGemmOptions : public gemmGatedAct::GemmGatedActOptions
int32_t sfReshapeFactor, gemm::TileScheduler tileScheduler, gemmGatedAct::ActType actType, bool clampBeforeAct,
std::vector<int> batchedM, std::vector<int> batchedN, BatchMode batchMode, int numBatches, bool isStaticBatch,
int numTokens, RouteImpl routeImpl, bool gridWaitForPrimaryRouting, bool fusedAct,
int numRegsPerThreadNonEpilogueWarp, int numRegsPerThreadEpilogueWarp, int numRegsCastAWarps, bool useTmaOobOpt)
int numRegsPerThreadNonEpilogueWarp, int numRegsPerThreadEpilogueWarp, int numRegsCastAWarps)
: gemmGatedAct::GemmGatedActOptions(
gemm::GemmOptions(allReduceAlgo, biasType, blockK, clusterDimX, clusterDimY, clusterDimZ, dtypeAcc, dtypeA,
dtypeB, dtypeC, dtypeMmaA, dtypeMmaB, enablesEarlyExit, enablesDelayedEarlyExit, enablesGlobalPtxKnobs,
@ -116,16 +116,15 @@ struct BatchedGemmOptions : public gemmGatedAct::GemmGatedActOptions
, mBatchedM(batchedM)
, mBatchedN(batchedN)
, mBatchMode(BatchMode(batchMode))
, mFusedAct(fusedAct)
, mGridWaitForPrimaryRouting(gridWaitForPrimaryRouting)
, mIsStaticBatch(isStaticBatch)
, mNumBatches(numBatches)
, mIsStaticBatch(isStaticBatch)
, mNumTokens(numTokens)
, mRouteImpl(routeImpl)
, mGridWaitForPrimaryRouting(gridWaitForPrimaryRouting)
, mFusedAct(fusedAct)
, mNumRegsPerThreadNonEpilogueWarp(numRegsPerThreadNonEpilogueWarp)
, mNumRegsPerThreadEpilogueWarp(numRegsPerThreadEpilogueWarp)
, mNumRegsCastAWarps(numRegsCastAWarps)
, mNumTokens(numTokens)
, mRouteImpl(routeImpl)
, mUseTmaOobOpt(useTmaOobOpt)
{
}
@ -135,28 +134,28 @@ struct BatchedGemmOptions : public gemmGatedAct::GemmGatedActOptions
std::vector<int> mBatchedN;
// Whether batching M or N.
BatchMode mBatchMode{BatchMode::BatchM};
// Whether to perform a fused gated activation.
bool mFusedAct{false};
// Number of Gemm batches.
int mNumBatches;
// Whether the batch size is static (i.e. known at kernel launch time).
bool mIsStaticBatch{true};
// Total number of tokens.
int mNumTokens{32};
// Whether load the input tokens and do routing.
RouteImpl mRouteImpl{RouteImpl::NoRoute};
// Whether the loads that load from ptrRouteMap, ptrTotalNumPaddedTokens,
// ptrCtaIdxXyToBatchIdx, etc.. should wait on a grid dependency.
bool mGridWaitForPrimaryRouting{true};
// Whether the batch size is static (i.e. known at kernel launch time).
bool mIsStaticBatch{true};
// Number of Gemm batches.
int mNumBatches;
// Whether to perform a fused gated activation.
bool mFusedAct{false};
// Number of registers per thread for non-epilogue warps
int mNumRegsPerThreadNonEpilogueWarp{0};
// Number of registers per thread for epilogue warps
int mNumRegsPerThreadEpilogueWarp{0};
// Number of registers for the cast A warps.
int mNumRegsCastAWarps{0};
// Total number of tokens.
int mNumTokens{32};
// Whether load the input tokens and do routing.
RouteImpl mRouteImpl{RouteImpl::NoRoute};
// Whether to use TMA out-of-bounds optimization to reduce wasted traffic. See details in
// BatchedGemm/KernelParamsDecl.h.
bool mUseTmaOobOpt{false};
};
////////////////////////////////////////////////////////////////////////////////////////////////////
@ -166,20 +165,6 @@ bool checkAndUpdateBatchedGemmOptions(BatchedGemmOptions& options, bool isBlackw
{
bool isValid = true;
if (options.mUseTmaOobOpt && !options.mUseTwoTmaLoadWarps)
{
if (updateOptions)
{
// Since any routing (mRouteAct != NoRoute) requires mUseTwoTmaLoadWarps == true.
// Single TMA load warp is not the target use case for OOB optimization.
options.mUseTmaOobOpt = false;
}
else
{
TLLM_CHECK_ERROR(false, "TMA OOB optimization requires two TMA load warps.");
return false;
}
}
if (options.mFusedAct)
{
// ensure that we check the fused options as well
@ -382,8 +367,7 @@ inline std::string dumpOptions(BatchedGemmOptions const& options)
ss << "mFusedAct=" << options.mFusedAct << "," << std::endl;
ss << "mNumRegsPerThreadNonEpilogueWarp=" << options.mNumRegsPerThreadNonEpilogueWarp << "," << std::endl;
ss << "mNumRegsPerThreadEpilogueWarp=" << options.mNumRegsPerThreadEpilogueWarp << "," << std::endl;
ss << "mNumRegsCastAWarps=" << options.mNumRegsCastAWarps << "," << std::endl;
ss << "mUseTmaOobOpt=" << options.mUseTmaOobOpt << std::endl;
ss << "mNumRegsCastAWarps=" << options.mNumRegsCastAWarps << std::endl;
return ss.str();
}

2
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/GemmGatedActOptions.h
View File

@ -179,7 +179,7 @@ inline std::string dumpOptions(GemmGatedActOptions const& options)
ss << gemm::dumpOptions(options) << ", ";
ss << "mActType="
<< "gemmGatedAct::ActType(" << static_cast<int32_t>(options.mActType) << ")," << std::endl;
ss << "mClampBeforeAct=" << options.mClampBeforeAct << "" << std::endl;
ss << "mClampLimit=" << options.mClampBeforeAct << "," << std::endl;
return ss.str();
}

4
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/GemmOptions.h
View File

@ -527,7 +527,6 @@ inline int32_t getShuffleBlockSize(int epilogueTileM)
inline bool checkAndUpdateGemmOptions(
GemmOptions& options, bool isBlackwell, int /* tpGrpSize */, bool updateOptions = true)
{
if (options.mDtypeB == tg::Dtype::Void)
{
if (updateOptions)
@ -568,8 +567,7 @@ inline bool checkAndUpdateGemmOptions(
// Currently, we only support {MxFp4, NvFp4} -> Bf16.
TLLM_CHECK_ERROR((options.mDtypeA == options.mDtypeMmaA)
|| ((options.mDtypeA == tg::Dtype::MxE2m1 || options.mDtypeA == tg::Dtype::E2m1)
&& options.mDtypeMmaA == tg::Dtype::Bfloat16)
|| (options.mDtypeA == tg::Dtype::E2m1 && options.mDtypeMmaA == tg::Dtype::E4m3),
&& options.mDtypeMmaA == tg::Dtype::Bfloat16),
"Unsupported cast for A: ", tg::dtypeToString(options.mDtypeA), " -> ", tg::dtypeToString(options.mDtypeMmaA));
// Check that the B cast is supported.

16634
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/KernelMetaInfo.h
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File diff suppressed because it is too large Load Diff

114
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/KernelParams.h
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@ -18,7 +18,6 @@
#include "trtllm/gen/CommonUtils.h"
#include "trtllm/gen/SfLayoutDecl.h"
#include <stdexcept>
#include "BatchedGemmEnums.h"
#include "Enums.h"
@ -52,7 +51,11 @@ namespace tg = trtllm::gen;
namespace KernelParamsSetup
{
#ifdef TLLM_ENABLE_CUDA
//////////////////////////////////////////////////////////////////////////////////////////////////
//
// Member functions.
//
//////////////////////////////////////////////////////////////////////////////////////////////////
enum class MatrixType
{
MatrixA = 0,
@ -60,38 +63,6 @@ enum class MatrixType
MatrixC
};
//////////////////////////////////////////////////////////////////////////////////////////////////
//
// Utility functions.
//
//////////////////////////////////////////////////////////////////////////////////////////////////
template <typename BatchedGemmOptions>
bool useTmaOobOptA(BatchedGemmOptions const& options)
{
return options.mBatchMode == BatchedGemmOptions::BatchMode::BatchM && doesRouteImplUseNoRoute(options.mRouteImpl)
&& options.mUseTmaOobOpt;
}
//////////////////////////////////////////////////////////////////////////////////////////////////
template <typename BatchedGemmOptions>
bool useTmaOobOptB(BatchedGemmOptions const& options)
{
return options.mBatchMode == BatchedGemmOptions::BatchMode::BatchN && doesRouteImplUseNoRoute(options.mRouteImpl)
&& options.mUseTmaOobOpt;
}
//////////////////////////////////////////////////////////////////////////////////////////////////
template <typename BatchedGemmOptions>
bool useTmaOobOptC(BatchedGemmOptions const& options)
{
return options.mUseTmaStore && options.mUseTmaOobOpt;
}
//////////////////////////////////////////////////////////////////////////////////////////////////
// Create the TMA shape/stride for A/B/C.
template <class GemmOptions>
static auto makeTmaShapeStrideAbc(
@ -102,83 +73,60 @@ static auto makeTmaShapeStrideAbc(
bool const isWeights = (matrixType == MatrixType::MatrixA && options.mTransposeMmaOutput)
|| (matrixType == MatrixType::MatrixB && !options.mTransposeMmaOutput);
// Whether to use TMA OOB trick to block out padded dummy tokens and saving BW whenever no routing
// is involved. It applies to batchM and matrixA, or batchN and matrixB, or any case for matrixC.
bool const useTmaOobOpt = matrixType == MatrixType::MatrixA ? useTmaOobOptA(options)
: matrixType == MatrixType::MatrixB ? useTmaOobOptB(options)
: matrixType == MatrixType::MatrixC ? useTmaOobOptC(options)
: false;
// The outer dimension.
auto numTokens = (matrixType == MatrixType::MatrixA || matrixType == MatrixType::MatrixC) ? mM : mN;
// The outer dimension tile size.
auto ctaTileNumTokens = (matrixType == MatrixType::MatrixA || matrixType == MatrixType::MatrixC) ? tileM : tileN;
// The outer dimension of TMA box shape.
auto tileNumTokens = (matrixType == MatrixType::MatrixC) ? options.mEpilogueTileM : ctaTileNumTokens;
auto tileNumTokens = (matrixType == MatrixType::MatrixC) ? options.mEpilogueTileM
: (matrixType == MatrixType::MatrixA) ? tileM
: tileN;
// The inner dimension.
auto hiddenSize = (matrixType == MatrixType::MatrixC) ? mN : mK;
// The inner dimension tile size.
auto ctaTileHiddenSize = (matrixType == MatrixType::MatrixC) ? tileN : tileK;
// The inner dimension of TMA box shape.
auto tileHiddenSize = (matrixType == MatrixType::MatrixC) ? options.mEpilogueTileN : ctaTileHiddenSize;
auto tileHiddenSize = (matrixType == MatrixType::MatrixC) ? options.mEpilogueTileN : tileK;
// Swap matrix C sizes if output is transposed.
// Swap matrix C sizes if output is transpose
if (matrixType == MatrixType::MatrixC && options.mTransposeMmaOutput)
{
std::swap(numTokens, hiddenSize);
std::swap(ctaTileNumTokens, ctaTileHiddenSize);
std::swap(tileNumTokens, tileHiddenSize);
numTokens = mN;
hiddenSize = mM;
tileNumTokens = options.mEpilogueTileN;
tileHiddenSize = options.mEpilogueTileM;
}
// For a fused activation kernel, the hidden size of output is halved. TODO: That's true for
// gated activations but not regular activations.
if (options.mFusedAct && matrixType == MatrixType::MatrixC)
if (options.mFusedAct)
{
hiddenSize /= 2;
tileHiddenSize /= 2;
ctaTileHiddenSize /= 2;
if (matrixType == MatrixType::MatrixC)
{
hiddenSize /= 2;
tileHiddenSize /= 2;
}
}
// The cute tensor shape for A/B: (numTokens, hiddenSize).
// Note that TMA descriptor expects the first dimension's stride to be
// 1, so swap the first two dimension so that the hiddenSize dimension comes first.
// Activations matrix is 2D (sum(divUpMul(M[bi], tileM) for bi in B), K).
std::vector<uint64_t> shape = {static_cast<uint64_t>(hiddenSize), static_cast<uint64_t>(numTokens)};
if (useTmaOobOpt /* also implies input/output activation */)
auto shape = std::vector<uint64_t>{static_cast<uint64_t>(hiddenSize), static_cast<uint64_t>(numTokens)};
// If the matrix is a weights matrix, we use 3D logical shape for it (B, M, K) or (B, N, K).
// Ativations matrix is 2D (sum(divUpMul(M[bi], tileM) for bi in B), K).
if (isWeights)
{
// If TMA OOB optimization is used, we use 3D logical shape (M, tileM, K) or (N, tileN, K).
// The outer dimension is extended to make room for the possible counterbalance positive
// offset from the middle "bound" dimension. The counterbalance should be no more than
// ctaTileNumTokens.
shape = {static_cast<uint64_t>(hiddenSize), static_cast<uint64_t>(ctaTileNumTokens),
static_cast<uint64_t>(numTokens + ctaTileNumTokens)};
}
else if (isWeights)
{
// If the matrix is a weights matrix, we use 3D logical shape (B, M, K) or (B, N, K).
shape = {static_cast<uint64_t>(hiddenSize), static_cast<uint64_t>(numTokens),
static_cast<uint64_t>(options.mNumBatches)};
shape.push_back(static_cast<uint64_t>(options.mNumBatches));
}
// Assemble the stride (strideTokens, 1).
// Swap the first two dimension as mentioned before.
std::vector<uint64_t> stride = {1, static_cast<uint64_t>(hiddenSize)};
if (useTmaOobOpt)
auto stride = std::vector<uint64_t>{1, static_cast<uint64_t>(hiddenSize)};
if (isWeights)
{
stride = {1, static_cast<uint64_t>(hiddenSize), static_cast<uint64_t>(hiddenSize)};
}
else if (isWeights)
{
stride = {
1, static_cast<uint64_t>(hiddenSize), static_cast<uint64_t>(hiddenSize) * static_cast<uint64_t>(numTokens)};
stride.push_back(static_cast<uint64_t>(hiddenSize * numTokens));
}
// Assemble the box shape
std::vector<int32_t> tileShape = {tileHiddenSize, tileNumTokens};
// Alternate layouts (MajorMn and BlockMajorK) do not apply to matrixC
// Alternate layouts do not apply to matrixC
if (matrixType != MatrixType::MatrixC)
{
gemm::MatrixLayout layout = (matrixType == MatrixType::MatrixA) ? options.mLayoutA : options.mLayoutB;
@ -348,8 +296,8 @@ static KernelParams setKernelParams(GemmOptions_ const& options, bool const batc
for (int b = 0; b < options.mNumBatches; b++)
{
int mM = batchM ? options.mBatchedM[b] : options.mM;
int mN = batchM ? options.mN : options.mBatchedN[b];
int mM = batchM ? options.mBatchedM[b] : options.mN;
int mN = batchM ? options.mM : options.mBatchedN[b];
// Skip Tma descriptor creation if expert isn't used
if (mM == 0 || mN == 0)

51
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/KernelParamsDecl.h
View File

@ -1,3 +1,4 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0
@ -18,7 +19,6 @@
namespace batchedGemm
{
// This is device code
struct KernelParams
@ -32,55 +32,6 @@ struct KernelParams
// Maximum number of CTAs
static constexpr int MaxNumCtas = 2048;
// NOTE: TMA out-of-bounds optimization for MoE padded tokens:
//
// Originally the padded tokens is a 2D tensor [hiddenDim, ctaGridDimY * tileN] with stride [1,
// hiddenDim] and box size [tileM, tileN] at pointer p. We waste bandwidth bytes since we only
// want to load [0, batchEnd) out of the [0, tileN) box size: batchEnd is a runtime variable while
// box size needs to be fixed at compile time.
//
// To deal with this, we reshape the tensor to 3D: [hiddenDim, tileN, ctaGridDimY * tileN] with
// stride [1, hiddenDim, hiddenDim] and box size [tileM, tileN, 1]. For the original 2D
// tensor,
//
// Offset Coords [ : , ctaIdxY * tileN ],
// Box Sizes [ : , tileN ],
// Coords Range [ : , ctaIdxY * tileN : ctaIdxY * tileN + tileN],
//
// while we only want load the range [ctaIdxY * tileN, ctaIdxY * tileN + batchEnd), 1 <= batchEnd
// <= tileN
//
// For the reshaped 3D tensor,
//
// Offset Coords [ : , tileN - batchEnd ,
// ctaIdxY * tileN + batchEnd ],
// Box Sizes [ : , tileN ,
// 1 ],
// Coords Range [ : , tileN - batchEnd : min(tileN, 2 * tileN - batchEnd),
// ctaIdxY * tileN + batchEnd : ctaIdx * tileN + batchEnd + 1],
//
// while min(tileN, 2 * tileN - batchEnd) always evaluates to tileN. The unwanted tokens are
// essentially filtered out by utilizing the OOB feature of TMA. Since the 2nd and 3rd dimension
// has the same stride, we end up loading the following (adding the left and right end of the 2nd
// and 3rd dimension ranges):
//
// Effective 2D Coords Range
// [ : , tileN + ctaIdxY * tileN : tileN + ctaIdxY * tileN + batchEnd],
//
// This is exactly the same as the original range except for the offset tileN, thus we also need
// to offset the pointer in the opposite direction:
//
// Ptr (p) -> Ptr (p - tileN * hiddenDim)
//
// Due to the restrictions of TMA unit, the above operations requires the TMA descriptor and the
// underlying buffer be constructed differently:
// - Requires valid buffer at (p - tileN * hidden) - needs prepending `tileN` tokens.
// - TMA outermost dimension must be extended by `tileN` or loads will OOB in the rightmost side.
// The latter is because when batchEnd == tileN, the offset coords in the 3rd dimension becomes
// ctaIdxY * tileN + tileN. When ctaIdxY = ctaGridDimY - 1, it becomes ((ctaGridDimY - 1) * tileN
// + tileN = ctaGridDimY * tileN which is equal to the 3rd dimension size and will be filtered
// out. That's why we need to extend the tensor size by tileN.
//
// TMA descriptor for A.
// Must be setup using gemm::buildNdTmaDescriptor with shapes and strides from
// makeTmaShapeStrideAbc.

74
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/KernelTraits.h
View File

@ -20,7 +20,6 @@
#include "trtllm/gen/CommonUtils.h"
#include "trtllm/gen/DtypeDecl.h"
#include <cassert>
#include <stdexcept>
namespace batchedGemm
{
@ -78,38 +77,6 @@ public:
}
// Returns the offset of the ith chunk
int32_t getChunkOffsetByName(std::string const& name) const
{
for (size_t ii = 0; ii < mSmemChunkNames.size(); ++ii)
{
if (mSmemChunkNames[ii] == name)
{
return getChunkOffset(ii);
}
}
throw std::runtime_error("Name not found: " + name);
}
// Returns the first chunk reuse flag given chunk name.
int getFirstChunkReuseFlagByName(std::string const& name) const
{
for (size_t ii = 0; ii < mSmemChunkNames.size(); ++ii)
{
if (mSmemChunkNames[ii] == name)
{
return getFirstChunkReuseFlag(ii);
}
}
throw std::runtime_error("Name not found: " + name);
}
// Function to calculate the total size of the SMEM array
int32_t getTotalSize() const
{
return getOffsetBeforeChunk(static_cast<int32_t>(mNumBytesAndAlignmentPerSmemChunk.size()));
}
private:
int32_t getChunkOffset(int32_t ii) const
{
if (mFirstChunkReuse[ii])
@ -124,6 +91,12 @@ private:
return getSizePaddedToAlignment(offset, mNumBytesAndAlignmentPerSmemChunk[ii].second);
}
// Function to calculate the total size of the SMEM array
int32_t getTotalSize() const
{
return getOffsetBeforeChunk(static_cast<int32_t>(mNumBytesAndAlignmentPerSmemChunk.size()));
}
// Returns the first chunk reuse flag for the ith chunk.
int getFirstChunkReuseFlag(int32_t ii) const
{
@ -166,7 +139,9 @@ int getNumSmemBitsPerElt(tg::Dtype dtype, tg::MmaKind mmaKind)
{
if (mmaKind == tg::MmaKind::Auto)
{
throw std::runtime_error("mmaKind != tg::MmaKind::Auto");
std::cout << "mmaKind != tg::MmaKind::Auto" << std::endl;
assert(false);
return -1;
}
if (mmaKind == tg::MmaKind::MxFp8Fp6Fp4)
{
@ -566,14 +541,14 @@ inline int32_t getTmemBufferSize(KernelTraits traits)
inline int32_t getSmemOffsetLoadA(KernelTraits traits)
{
return traits.mSmemAllocatorHelper.getChunkOffsetByName("smemLoadA");
return traits.mSmemAllocatorHelper.getChunkOffset(0);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getSmemOffsetLoadB(KernelTraits traits)
{
return traits.mSmemAllocatorHelper.getChunkOffsetByName("smemLoadB");
return traits.mSmemAllocatorHelper.getChunkOffset(1);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
@ -587,63 +562,64 @@ inline int32_t getSmemOffsetLoadAb(KernelTraits traits)
inline int32_t getSmemOffsetLoadShuffleB(KernelTraits traits)
{
return traits.mSmemAllocatorHelper.getChunkOffsetByName("smemBShuffle");
return traits.mSmemAllocatorHelper.getChunkOffset(2);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getSmemOffsetGmemC(KernelTraits traits, int resIdx = 0)
{
return traits.mSmemAllocatorHelper.getChunkOffsetByName("smemGmemC" + std::to_string(resIdx));
return traits.mSmemAllocatorHelper.getChunkOffset(3 + resIdx);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getSmemOffsetRowMax(KernelTraits traits)
{
return traits.mSmemAllocatorHelper.getChunkOffsetByName("smemRowMax");
return traits.mSmemAllocatorHelper.getChunkOffset(5);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getSmemOffsetSliceK(KernelTraits traits)
{
return traits.mSmemAllocatorHelper.getChunkOffsetByName("smemSliceK");
return traits.mSmemAllocatorHelper.getChunkOffset(6);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getSmemOffsetPerTokenSf(KernelTraits traits)
{
return traits.mSmemAllocatorHelper.getChunkOffsetByName("smemPerTokenSf");
return traits.mSmemAllocatorHelper.getChunkOffset(7);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getSmemOffsetBias(KernelTraits traits)
{
return traits.mSmemAllocatorHelper.getChunkOffsetByName("smemBias");
return traits.mSmemAllocatorHelper.getChunkOffset(8);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getSmemOffsetBlockAmax(KernelTraits traits)
{
return traits.mSmemAllocatorHelper.getChunkOffsetByName("smemBlockAmax");
return traits.mSmemAllocatorHelper.getChunkOffset(9);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getSmemOffsetConstSfBuf(KernelTraits traits)
{
return traits.mSmemAllocatorHelper.getChunkOffsetByName("smemConstSfBuf");
return traits.mSmemAllocatorHelper.getChunkOffset(10);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t isSmemAbRepurposedToGmemC(KernelTraits traits, int resIdx = 0)
{
return traits.mSmemAllocatorHelper.getFirstChunkReuseFlagByName("smemGmemC" + std::to_string(resIdx));
// Be conscious that the index (3 + resIdx) should match the index in getSmemOffsetGmemC().
return traits.mSmemAllocatorHelper.getFirstChunkReuseFlag(3 + resIdx);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
@ -654,28 +630,28 @@ inline int32_t isSmemAbRepurposedToGmemC(KernelTraits traits, int resIdx = 0)
inline int32_t getTmemOffsetD(KernelTraits traits)
{
return traits.mTmemAllocatorHelper.getChunkOffsetByName("tmemD");
return traits.mTmemAllocatorHelper.getChunkOffset(0);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getTmemOffsetA(KernelTraits traits)
{
return traits.mTmemAllocatorHelper.getChunkOffsetByName("tmemA");
return traits.mTmemAllocatorHelper.getChunkOffset(1);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getTmemOffsetSfA(KernelTraits traits)
{
return traits.mTmemAllocatorHelper.getChunkOffsetByName("tmemSfA");
return traits.mTmemAllocatorHelper.getChunkOffset(2);
}
////////////////////////////////////////////////////////////////////////////////////////////////////
inline int32_t getTmemOffsetSfB(KernelTraits traits)
{
return traits.mTmemAllocatorHelper.getChunkOffsetByName("tmemSfB");
return traits.mTmemAllocatorHelper.getChunkOffset(3);
}
////////////////////////////////////////////////////////////////////////////////////////////////////

6
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/TmaDescriptor.h
View File

@ -181,8 +181,6 @@ inline CUtensorMap buildNdTmaDescriptor(tg::Dtype dtype, tg::MmaKind mmaKind, st
if (result != CUDA_SUCCESS)
{
char const* errorString;
cuGetErrorString(result, &errorString);
std::stringstream ss;
ss << "Error: Failed to initialize the TMA descriptor " << result << std::endl;
@ -285,10 +283,8 @@ inline CUtensorMap buildSfTmaDescriptor(tg::Dtype dtype, std::vector<uint64_t> c
if (result != CUDA_SUCCESS)
{
char const* errorString;
cuGetErrorString(result, &errorString);
std::stringstream ss;
ss << "Error: Failed to initialize the TMA descriptor for SF " << errorString << std::endl;
ss << "Error: Failed to initialize the TMA descriptor for SF " << result << std::endl;
ss << "tmaFormat: " << static_cast<int>(tmaDataFormat) << " dim: " << dim << " gmem: " << gmemAddr << std::endl;

271
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/config.json
View File

@ -12,6 +12,7 @@
"epilogueTileM": 128,
"epilogueTileN": 8,
"numStages": 4,
"numStagesMma": 1,
"numSlicesForSplitK": 1,
"useTwoTmaLoadWarps": true,
"clusterDimX": 1,
@ -30,7 +31,8 @@
"sfLayoutC": "8x4",
"batch": "N",
"numExperts": 128,
"useCudaGraph": true
"useCudaGraph": true,
"clampLimit": 2
},
"BatchedGemmPerTensorScalingFp8LowLatency": {
"dtypeA": "e4m3",
@ -44,6 +46,7 @@
"epilogueTileM": 128,
"epilogueTileN": 8,
"numStages": 3,
"numStagesMma": 1,
"numSlicesForSplitK": 1,
"useTwoTmaLoadWarps": true,
"clusterDimX": 1,
@ -60,7 +63,8 @@
"gridWaitForPrimaryB": true,
"batch": "N",
"numExperts": 128,
"useCudaGraph": true
"useCudaGraph": true,
"clampLimit": 2
},
"BatchedGemmDeepSeekFp8LowLatency": {
"dtypeA": "e4m3",
@ -94,7 +98,123 @@
"numStagesMma": 4,
"batch": "N",
"numExperts": 128,
"useCudaGraph": true
"useCudaGraph": true,
"clampLimit": 2
},
"BatchedGemmMxE2m1E4m3LowLatency": {
"dtypeA": "mxe2m1",
"dtypeB": "e4m3",
"dtypeC": "e4m3",
"dtypeMmaB": "mxe4m3",
"mmaM": 128,
"mmaN": 8,
"mmaK": 32,
"tileM": 128,
"tileN": 8,
"tileK": 512,
"epilogueTileM": 128,
"epilogueTileN": 8,
"numStages": 3,
"numStagesMma": 1,
"numSlicesForSplitK": 1,
"useTwoTmaLoadWarps": true,
"clusterDimX": 1,
"clusterDimY": 1,
"clusterDimZ": 1,
"sliceK": false,
"transposeMmaOutput": true,
"useShuffledMatrixA": true,
"useDeepSeekFp8": false,
"useTmaStore": true,
"useCustomMmaSchedule": true,
"gridTriggerSecondaryB": true,
"gridWaitForPrimaryA": false,
"gridWaitForPrimaryB": true,
"sfLayoutB": "8x4",
"sfLayoutC": "8x4",
"batch": "N",
"numExperts": 128,
"useCudaGraph": true,
"biasType": "m",
"act": "swiglu",
"clampLimit": 2
},
"BatchedGemmMxE2m1MxE4m3LowLatency": {
"dtypeA": "mxe2m1",
"dtypeB": "mxe4m3",
"dtypeC": "mxe4m3",
"mmaM": 128,
"mmaN": 8,
"mmaK": 32,
"tileM": 128,
"tileN": 8,
"tileK": 512,
"epilogueTileM": 128,
"epilogueTileN": 8,
"numStages": 3,
"numStagesMma": 1,
"numSlicesForSplitK": 1,
"useTwoTmaLoadWarps": true,
"clusterDimX": 1,
"clusterDimY": 1,
"clusterDimZ": 1,
"sliceK": false,
"transposeMmaOutput": true,
"useShuffledMatrixA": true,
"useDeepSeekFp8": false,
"useTmaStore": true,
"useCustomMmaSchedule": true,
"gridTriggerSecondaryB": true,
"gridWaitForPrimaryA": false,
"gridWaitForPrimaryB": true,
"sfLayoutB": "8x4",
"sfLayoutC": "8x4",
"batch": "N",
"numExperts": 128,
"useCudaGraph": true,
"biasType": "m",
"act": "swiglu",
"clampLimit": 2
},
"BatchedGemmMxE2m1Bf16LowLatency": {
"dtypeA": "mxe2m1",
"dtypeB": "bf16",
"dtypeC": "bf16",
"dtypeMmaA": "bf16",
"dtypeMmaB": "bf16",
"mmaM": 128,
"mmaN": 8,
"mmaK": 16,
"tileM": 128,
"tileN": 8,
"tileK": 256,
"epilogueTileM": 128,
"epilogueTileN": 8,
"numStages": 3,
"numStagesMma": 1,
"numSlicesForSplitK": 1,
"useTwoTmaLoadWarps": true,
"clusterDimX": 1,
"clusterDimY": 1,
"clusterDimZ": 1,
"sliceK": false,
"transposeMmaOutput": true,
"useShuffledMatrixA": true,
"useDeepSeekFp8": false,
"useTmaStore": true,
"useCustomMmaSchedule": true,
"gridTriggerSecondaryB": true,
"gridWaitForPrimaryA": false,
"gridWaitForPrimaryB": true,
"sfLayoutB": "8x4",
"sfLayoutC": "8x4",
"batch": "N",
"numExperts": 128,
"useCudaGraph": true,
"biasType": "m",
"act": "swiglu",
"patchF2fp": true,
"clampLimit": 2
}
},
"configs": [
@ -221,6 +341,7 @@
"_template": "BatchedGemmPerTensorScalingFp8LowLatency",
"routeAct": true,
"fusedAct": true,
"usePerTokenSfB": true,
"useUnrollLoop2xForMma": [true, false],
"dtypeC": "e4m3",
"numTokens": 2,
@ -243,6 +364,150 @@
["static", 1],
["persistent", 2]
]
},
{
"_comment": "MxFp4xFp8_FC1",
"_template": "BatchedGemmMxE2m1E4m3LowLatency",
"routeAct": "ldgsts",
"fusedAct": true,
"sfLayoutB": "linear",
"useUnrollLoop2xForMma": [true, false],
"numTokens": 2,
"numExperts": 2,
"mmaN,tileN,epilogueTileN,tileK,numStages": [
[8, 8, 8, 512, 3],
[8, 8, 8, 256, 5],
[16, 16, 16, 256, 5],
[32, 32, 32, 256, 5],
[64, 64, 64, 256, 4]
],
"tileScheduler,numStagesMma": [
["static", 1],
["persistent", 2]
]
},
{
"_comment": "MxFp4xFp8_FC2",
"_template": "BatchedGemmMxE2m1E4m3LowLatency",
"routeAct": false,
"fusedAct": false,
"useUnrollLoop2xForMma": [true, false],
"dtypeC": "bf16",
"numTokens": 2,
"numExperts": 2,
"mmaN,tileN,epilogueTileN,tileK,numStages": [
[8, 8, 8, 512, 3],
[8, 8, 8, 256, 5],
[16, 16, 16, 256, 5],
[32, 32, 32, 256, 5],
[64, 64, 64, 256, 4]
],
"tileScheduler,numStagesMma": [
["static", 1],
["persistent", 2]
]
},
{
"_comment": "MxFp4xMxFp8_FC1",
"_template": "BatchedGemmMxE2m1MxE4m3LowLatency",
"routeAct": "ldgsts",
"fusedAct": true,
"sfLayoutB": "linear",
"useUnrollLoop2xForMma": [true, false],
"numTokens": 2,
"numExperts": 2,
"mmaN,tileN,epilogueTileN,tileK,numSlicesForSplitK,clusterDimZ,numStages": [
[8, 8, 8, 512, 1, 1, 3],
[8, 8, 8, 512, 2, 2, 3],
[8, 8, 8, 256, 1, 1, 4],
[8, 8, 8, 256, 1, 1, 5],
[8, 8, 8, 256, 1, 1, 6],
[8, 8, 8, 256, 2, 2, 4],
[8, 8, 8, 256, 2, 2, 5],
[8, 8, 8, 256, 2, 2, 6],
[16, 16, 16, 256, 1, 1, 3],
[16, 16, 16, 256, 1, 1, 4],
[32, 32, 32, 256, 1, 1, 3],
[32, 32, 32, 256, 1, 1, 4],
[64, 64, 64, 256, 1, 1, 3],
[64, 64, 64, 256, 1, 1, 4]
],
"tileScheduler,numStagesMma": [
["static", 1],
["persistent", 2]
]
},
{
"_comment": "MxFp4xMxFp8_FC2",
"_template": "BatchedGemmMxE2m1MxE4m3LowLatency",
"routeAct": false,
"fusedAct": false,
"useUnrollLoop2xForMma": [true, false],
"dtypeC": "bf16",
"numTokens": 2,
"numExperts": 2,
"mmaN,tileN,epilogueTileN,tileK,numSlicesForSplitK,clusterDimZ,numStages": [
[8, 8, 8, 512, 1, 1, 3],
[8, 8, 8, 512, 2, 2, 3],
[8, 8, 8, 256, 1, 1, 4],
[8, 8, 8, 256, 1, 1, 5],
[8, 8, 8, 256, 1, 1, 6],
[8, 8, 8, 256, 2, 2, 4],
[8, 8, 8, 256, 2, 2, 5],
[8, 8, 8, 256, 2, 2, 6],
[16, 16, 16, 256, 1, 1, 3],
[16, 16, 16, 256, 1, 1, 4],
[32, 32, 32, 256, 1, 1, 3],
[32, 32, 32, 256, 1, 1, 4],
[64, 64, 64, 256, 1, 1, 3],
[64, 64, 64, 256, 1, 1, 4]
],
"tileScheduler,numStagesMma": [
["static", 1],
["persistent", 2]
]
},
{
"_comment": "MxFp4xBf16_FC1",
"_template": "BatchedGemmMxE2m1Bf16LowLatency",
"routeAct": "ldgsts",
"fusedAct": true,
"sfLayoutB": "linear",
"useUnrollLoop2xForMma": [true, false],
"dtypeC": "bf16",
"numTokens": 2,
"numExperts": 2,
"tileK": 256,
"mmaN,tileN,epilogueTileN,numStages": [
[8, 8, 8, 3],
[16, 16, 16, 3],
[32, 32, 32, 3],
[64, 64, 64, 3]
],
"tileScheduler,numStagesMma": [
["static", 1],
["persistent", 2]
]
},
{
"_comment": "MxFp4xBf16_FC2",
"_template": "BatchedGemmMxE2m1Bf16LowLatency",
"routeAct": false,
"fusedAct": false,
"useUnrollLoop2xForMma": [true, false],
"dtypeC": "bf16",
"numTokens": 2,
"numExperts": 2,
"mmaN,tileN,epilogueTileN,numStages": [
[8, 8, 8, 3],
[16, 16, 16, 3],
[32, 32, 32, 3],
[64, 64, 64, 3]
],
"tileScheduler,numStagesMma": [
["static", 1],
["persistent", 2]
]
}
]
}

3
cpp/tensorrt_llm/kernels/trtllmGenKernels/batchedGemm/trtllmGen_bmm_export/cubins/Bmm_Bfloat16_E2m1E2m1_Fp32_t128x16x256_et128x16_m128x16x64_cga1x1x1_16dp256b_s6_TN_transOut_schedP_bN_dynBatch_sm100a_cubin.cpp Normal file
View File

@ -0,0 +1,3 @@
version https://git-lfs.github.com/spec/v1
oid sha256:eba4edca5eaa1fc6b654c4b720339cd536a02723cc798fc17cb31314a1681633
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