brb-nv
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e10a027a03
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[TRTLLM-7731][feat] KV cache transmission in disagg with CP on gen side (#7624)
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
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2025-09-20 06:15:26 -07:00 |
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Iman Tabrizian
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6ce0624208
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[TRTLLM-8044][refactor] Rename data -> cache for cacheTransceiver (#7659)
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2025-09-16 08:43:56 -04:00 |
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Chuang Zhu
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77657a1c12
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[TRTLLM-7361][feat] KV cache transfer for uneven pp (#7117)
Signed-off-by: Chuang Zhu <111838961+chuangz0@users.noreply.github.com>
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2025-09-08 13:37:46 -04:00 |
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brb-nv
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43cb50f788
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[None][feat] Update TargetInfo to accommodate CP in disagg (#7224)
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
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2025-08-29 15:56:20 -04:00 |
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Robin Kobus
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31979aefac
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[None] [ci] Reorganize CMake and Python integration test infrastructure for C++ tests (#6754)
Signed-off-by: Robin Kobus <19427718+Funatiq@users.noreply.github.com>
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2025-08-24 20:53:17 +02:00 |
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