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a8310b01dc
* feat: trtllm-gen fp4 GEMM Signed-off-by: Dom Brown <3886319+DomBrown@users.noreply.github.com> * Clean up Signed-off-by: Dom Brown <3886319+DomBrown@users.noreply.github.com> * Remove incorrect header Signed-off-by: Dom Brown <3886319+DomBrown@users.noreply.github.com> * Reviewer comment Signed-off-by: Dom Brown <3886319+DomBrown@users.noreply.github.com> --------- Signed-off-by: Dom Brown <3886319+DomBrown@users.noreply.github.com>
49 lines
1.4 KiB
C++
49 lines
1.4 KiB
C++
/*
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* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <cuda.h>
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#include "trtllmGen_export/GemmOptions.h"
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#include "trtllmGen_export/trtllm/gen/DtypeDecl.h"
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namespace tensorrt_llm
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{
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namespace kernels
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{
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namespace tg = trtllm::gen;
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class TrtllmGenGemmRunner
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{
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public:
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explicit TrtllmGenGemmRunner(tg::Dtype eltType, tg::Dtype outputType);
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[[nodiscard]] size_t getWorkspaceSizeInBytes(
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int32_t m, int32_t n, int32_t k, tg::Dtype eltType, tg::Dtype outputType) const;
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void run(int32_t m, int32_t n, int32_t k, void const* a, float const* aScale, void const* b, float const* bScale,
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void* c, float* cScale, void* workspace, CUstream stream, int device);
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private:
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tg::Dtype mEltType;
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tg::Dtype mOutputType;
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gemm::GemmConfig const* mGemmConfig;
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};
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} // namespace kernels
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} // namespace tensorrt_llm
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