mirror of
https://github.com/NVIDIA/TensorRT-LLM.git
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88 lines
3.6 KiB
C++
88 lines
3.6 KiB
C++
/*
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* Copyright (c) 2023-2024, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include "tensorrt_llm/batch_manager/common.h"
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#include "tensorrt_llm/runtime/bufferManager.h"
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#include "tensorrt_llm/runtime/iTensor.h"
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#include "tensorrt_llm/runtime/modelConfig.h"
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#include "tensorrt_llm/runtime/worldConfig.h"
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#include <optional>
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#include <unordered_map>
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#include <vector>
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namespace tensorrt_llm::batch_manager::rnn_state_manager
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{
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class RnnStateManager
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{
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public:
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using TensorPtr = runtime::ITensor::SharedPtr;
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using SizeType32 = tensorrt_llm::runtime::SizeType32;
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using TensorMap = runtime::StringPtrMap<runtime::ITensor>;
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using RequestIdType = tensorrt_llm::batch_manager::RequestIdType;
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RnnStateManager(SizeType32 maxNumSequences, tensorrt_llm::runtime::ModelConfig const& modelConfig,
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runtime::WorldConfig const& worldConfig, tensorrt_llm::runtime::BufferManager const& bufferManager);
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RnnStateManager(SizeType32 dState, SizeType32 dConv, SizeType32 numHeads, SizeType32 nGroups, SizeType32 headDim,
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SizeType32 maxBatchSize, runtime::WorldConfig const& worldConfig, int64_t stream, nvinfer1::DataType dtype,
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nvinfer1::DataType ssmCacheDtype, std::vector<SizeType32> const& ppLayers);
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void getPtrBuffers(TensorMap& inputBuffers, runtime::ModelConfig const& modelConfig,
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runtime::WorldConfig const& worldConfig) const;
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void fillSlotMapping(
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runtime::ITensor& dstPointers, SizeType32 dstSlotOffset, SizeType32 seqSlotIdx, SizeType32 beamWidth) const;
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void allocateCacheBlocks(std::vector<RequestIdType> const& requestIds);
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void freeCacheBlock(RequestIdType requestId);
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[[nodiscard]] SizeType32 getCacheIndex(RequestIdType requestId) const;
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[[nodiscard]] std::vector<SizeType32> getStateIndices(
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std::vector<RequestIdType> const& requestIds, std::vector<bool> const& isPadding);
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[[nodiscard]] TensorPtr getConvStates(SizeType32 layerIdx) const;
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[[nodiscard]] TensorPtr getSsmStates(SizeType32 layerIdx) const;
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private:
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// If we need support beam search, we may need mMaxBeamWidth + 1 slots and use separate input / output states.
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TensorPtr pagedRnnStates; // [local_nb_layers, max_seq_num * max_beam_width, state_size, rnn_hidden_size] or
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// [local_nb_layers, max_seq_num * max_beam_width, num_heads, state_size, rnn_head_size]
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TensorPtr pagedConvStates; // [local_nb_layers, max_seq_num * max_beam_width, conv_kernel - 1, rnn_hidden_size]
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TensorPtr rnnStatePtrs; // [layer_count]
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TensorPtr convStatePtrs; // [layer_count]
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std::vector<TensorPtr> rnnStatePtr; // [1]
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std::vector<TensorPtr> convStatePtr; // [1]
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SizeType32 mMaxNumSequences = 0;
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SizeType32 mMaxBeamWidth = 0;
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SizeType32 mBeamSlotsPerSequence = 0;
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std::unordered_map<SizeType32, SizeType32> mLayerOffsets;
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std::vector<SizeType32> mFreeBlocks;
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std::unordered_map<RequestIdType, SizeType32> mCacheIndex;
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std::optional<runtime::BufferManager> mBufferManager;
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};
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} // namespace tensorrt_llm::batch_manager::rnn_state_manager
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