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https://github.com/NVIDIA/TensorRT-LLM.git
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16d2467ea8
* Update TensorRT-LLM --------- Co-authored-by: Denis Kayshev <topenkoff@gmail.com> Co-authored-by: akhoroshev <arthoroshev@gmail.com> Co-authored-by: Patrick Reiter Horn <patrick.horn@gmail.com> Update
94 lines
2.1 KiB
C++
94 lines
2.1 KiB
C++
/*
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* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include "tensorrt_llm/common/mpiUtils.h"
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#include "tensorrt_llm/runtime/worldConfig.h"
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#include <algorithm>
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#include <cuda.h>
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#include <cuda_runtime.h>
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#include <set>
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namespace tensorrt_llm::runtime
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{
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struct IpcNvlsHandle
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{
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size_t size = 0;
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uintptr_t uc_ptr = 0;
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uintptr_t mc_ptr = 0;
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CUdeviceptr uc_va;
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CUdeviceptr mc_va;
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CUmemGenericAllocationHandle uc_handle;
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CUmemGenericAllocationHandle mc_handle;
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};
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void MPI_group_barrier(std::set<int> ranks);
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bool ipcNvlsSupported();
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IpcNvlsHandle ipcNvlsAllocate(size_t size, std::set<int> ranks);
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void ipcNvlsFree(IpcNvlsHandle handle);
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template <typename T>
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class DeviceAllocationNvls
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{
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public:
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DeviceAllocationNvls() = default;
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~DeviceAllocationNvls()
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{
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this->free();
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}
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void reset(size_t size, std::set<int> ranks)
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{
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this->free();
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_handle = ipcNvlsAllocate(size * sizeof(T), ranks);
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_capacity = size;
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}
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T* getMulticastPointer() const
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{
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return reinterpret_cast<T*>(_handle.mc_ptr);
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}
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T* getUnicastPointer() const
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{
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return reinterpret_cast<T*>(_handle.uc_ptr);
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}
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size_t getCapacity() const
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{
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return _capacity;
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}
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void free()
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{
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if (_capacity > 0)
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{
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ipcNvlsFree(_handle);
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_capacity = 0;
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}
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}
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private:
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size_t _capacity = 0;
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IpcNvlsHandle _handle;
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};
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} // namespace tensorrt_llm::runtime
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