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https://github.com/NVIDIA/TensorRT-LLM.git
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16d2467ea8
* Update TensorRT-LLM --------- Co-authored-by: Denis Kayshev <topenkoff@gmail.com> Co-authored-by: akhoroshev <arthoroshev@gmail.com> Co-authored-by: Patrick Reiter Horn <patrick.horn@gmail.com> Update
128 lines
3.8 KiB
C++
128 lines
3.8 KiB
C++
/*
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* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <NvInferRuntime.h>
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#include <cuda_bf16.h>
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#include <cuda_fp16.h>
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#include "tensorrt_llm/common/assert.h"
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#include "tensorrt_llm/common/cudaUtils.h"
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namespace tensorrt_llm::kernels
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{
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constexpr size_t WARP_SIZE = 32;
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constexpr size_t MAX_ALL_REDUCE_BLOCKS = 24;
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constexpr size_t MAX_RANKS_PER_NODE = 8;
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constexpr size_t DEFAULT_BLOCK_SIZE = 512;
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namespace reduce_fusion::details
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{
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static constexpr int kBytesPerAccess = 16;
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static constexpr int kWarpSize = 32;
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static constexpr int kMaxCtaSize = 1024;
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static constexpr int kClusterMaxSize = 8;
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static constexpr int kLamportTokenNumThreshold = 16;
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static constexpr int kLamportHiddenSizeThreshold = 256;
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}; // namespace reduce_fusion::details
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// Warning: python definition is in tensorrt_llm/functional.py
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// they must be kept in sync
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enum class AllReduceStrategyType : int8_t
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{
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NCCL = 0,
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ONESHOT = 1,
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TWOSHOT = 2,
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UB = 3,
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AUTO = 4,
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};
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enum class AllReduceStrategyConfig : int8_t
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{
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USE_MEMCPY = 1 << 0,
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PUSH_MODE = 1 << 1,
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};
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enum class AllReduceFusionOp : int8_t
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{
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NONE = 0,
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RESIDUAL_RMS_NORM = 1,
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LAST_PROCESS_FOR_UB = 2,
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RESIDUAL_RMS_PREPOST_NORM = 3,
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RESIDUAL_RMS_NORM_QUANT_FP8 = 4,
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RESIDUAL_RMS_NORM_QUANT_NVFP4 = 5,
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};
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struct AllReduceFusionParams
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{
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AllReduceFusionParams()
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: bias_buffer(nullptr)
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, residual_buffer(nullptr)
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, weight_buffer(nullptr)
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, weight_buffer_pre_residual_norm(nullptr)
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, intermediate_buffer(nullptr)
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{
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}
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// gemm bias
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void const* bias_buffer;
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// residuial add
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void const* residual_buffer;
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// rms norm
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int hidden_size; // equal to normalized_shape
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void const* weight_buffer; // norm elem-wise affine gamma
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void const* weight_buffer_pre_residual_norm; // for gemma norm before residual
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float eps;
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// new residual
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void* intermediate_buffer;
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void* lamport_peer_comm_buffer_ptrs[MAX_RANKS_PER_NODE * 3];
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};
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struct AllReduceParams
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{
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size_t elts_total;
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size_t elts_per_rank;
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size_t elts_per_block;
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size_t rank_offset;
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size_t ranks_per_node;
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size_t local_rank;
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uint32_t barrier_flag;
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uint32_t* peer_barrier_ptrs_in[MAX_RANKS_PER_NODE];
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uint32_t* peer_barrier_ptrs_out[MAX_RANKS_PER_NODE];
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void* peer_comm_buffer_ptrs[MAX_RANKS_PER_NODE];
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void* local_output_buffer_ptr;
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void const* local_input_buffer_ptr;
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AllReduceFusionParams fusion_params;
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static AllReduceParams deserialize(int64_t* buffer, size_t tpSize, size_t tpRank, nvinfer1::DataType dataType,
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int token_num, int hidden_size, AllReduceFusionOp op);
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};
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bool configurationSupported(AllReduceStrategyType algo, size_t msg_size, size_t n_ranks, nvinfer1::DataType type);
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void customAllReduce(kernels::AllReduceParams& params, nvinfer1::DataType dataType, AllReduceStrategyType strat,
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AllReduceStrategyConfig config, AllReduceFusionOp fusionOp, cudaStream_t stream);
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void residualRmsNorm(
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kernels::AllReduceParams& params, nvinfer1::DataType dataType, cudaStream_t stream, AllReduceFusionOp fusionOp);
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void lamportInitialize(void* buffer, size_t size, nvinfer1::DataType dataType, cudaStream_t stream);
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} // namespace tensorrt_llm::kernels
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