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https://github.com/NVIDIA/TensorRT-LLM.git
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16d2467ea8
* Update TensorRT-LLM --------- Co-authored-by: Denis Kayshev <topenkoff@gmail.com> Co-authored-by: akhoroshev <arthoroshev@gmail.com> Co-authored-by: Patrick Reiter Horn <patrick.horn@gmail.com> Update
127 lines
6.7 KiB
C++
127 lines
6.7 KiB
C++
/*
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* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include "tensorrt_llm/common/cudaUtils.h"
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#include "tensorrt_llm/kernels/weightOnlyBatchedGemv/common.h"
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#include "tensorrt_llm/kernels/weightOnlyBatchedGemv/details.h"
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namespace tensorrt_llm
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{
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namespace kernels
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{
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namespace weight_only
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{
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template <bool isGroupwise, typename Details>
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void select_gs(Params& params, cudaStream_t s);
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inline void kernel_launcher(int arch, Params& params, cudaStream_t s)
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{
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#define EXEC(KType, A, B, Layout, ConverterInterleave) \
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if (params.type == KType) \
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{ \
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select_gs<kernel_type_traits<KType>::isGroupwise, KernelDetails<A, B, Layout, ConverterInterleave, 64>>( \
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params, s); \
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return; \
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}
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#define EXEC_W4A8(KType, A, B, Layout, ConverterInterleave) \
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if (params.type == KType && params.apply_alpha_in_advance) \
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{ \
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select_gs<kernel_type_traits<KType>::isGroupwise, KernelDetails<A, B, Layout, ConverterInterleave, 128>>( \
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params, s); \
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return; \
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}
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if (arch >= 75 && arch < 80)
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{
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EXEC(KernelType::FP16Int8Groupwise, FP16DetailsA, Int8DetailsW, ColumnMajorInterleaved, true);
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EXEC(KernelType::FP16Int4Groupwise, FP16DetailsA, Int4DetailsW, ColumnMajorInterleaved, true);
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EXEC(KernelType::FP16Int8PerChannel, FP16DetailsA, Int8DetailsW, ColumnMajorInterleaved, true);
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EXEC(KernelType::FP16Int4PerChannel, FP16DetailsA, Int4DetailsW, ColumnMajorInterleaved, true);
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}
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else if ((arch >= 80 && arch < 90) || arch >= 100)
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{
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if (arch == 89)
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{
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EXEC_W4A8(KernelType::FP16Int4Groupwise, FP16DetailsA, Int4DetailsW, ColumnMajorInterleaved, true);
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EXEC_W4A8(KernelType::BF16Int4Groupwise, BF16DetailsA, Int4DetailsW, ColumnMajorInterleaved, true);
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}
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EXEC(KernelType::FP16Int8Groupwise, FP16DetailsA, Int8DetailsW, ColumnMajorInterleaved, true);
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EXEC(KernelType::BF16Int8Groupwise, BF16DetailsA, Int8DetailsW, ColumnMajorInterleaved, true);
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EXEC(KernelType::FP16Int4Groupwise, FP16DetailsA, Int4DetailsW, ColumnMajorInterleaved, true);
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EXEC(KernelType::BF16Int4Groupwise, BF16DetailsA, Int4DetailsW, ColumnMajorInterleaved, true);
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EXEC(KernelType::FP16Int8PerChannel, FP16DetailsA, Int8DetailsW, ColumnMajorInterleaved, true);
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EXEC(KernelType::BF16Int8PerChannel, BF16DetailsA, Int8DetailsW, ColumnMajorInterleaved, true);
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EXEC(KernelType::FP16Int4PerChannel, FP16DetailsA, Int4DetailsW, ColumnMajorInterleaved, true);
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EXEC(KernelType::BF16Int4PerChannel, BF16DetailsA, Int4DetailsW, ColumnMajorInterleaved, true);
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}
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else if (arch >= 90)
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{
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// Dispatchers for W4A8 groupwise
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EXEC_W4A8(KernelType::FP16Int4Groupwise, FP16DetailsA, Int4DetailsW, ColumnMajorInterleavedForHopper, true);
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EXEC_W4A8(KernelType::BF16Int4Groupwise, BF16DetailsA, Int4DetailsW, ColumnMajorInterleavedForHopper, true);
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EXEC(KernelType::FP16Int8Groupwise, FP16DetailsA, Int8DetailsW, ColumnMajorInterleavedForHopper, true);
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EXEC(KernelType::BF16Int8Groupwise, BF16DetailsA, Int8DetailsW, ColumnMajorInterleavedForHopper, true);
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EXEC(KernelType::FP16Int4Groupwise, FP16DetailsA, Int4DetailsW, ColumnMajorInterleavedForHopper, true);
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EXEC(KernelType::BF16Int4Groupwise, BF16DetailsA, Int4DetailsW, ColumnMajorInterleavedForHopper, true);
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EXEC(KernelType::FP16Int8PerChannel, FP16DetailsA, Int8DetailsW, ColumnMajorInterleavedForHopper, true);
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EXEC(KernelType::BF16Int8PerChannel, BF16DetailsA, Int8DetailsW, ColumnMajorInterleavedForHopper, true);
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EXEC(KernelType::FP16Int4PerChannel, FP16DetailsA, Int4DetailsW, ColumnMajorInterleavedForHopper, true);
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EXEC(KernelType::BF16Int4PerChannel, BF16DetailsA, Int4DetailsW, ColumnMajorInterleavedForHopper, true);
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}
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#undef EXEC
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}
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inline bool is_supported(int arch, KernelType kernel_type)
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{
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#define SUPPORT(Type) \
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if (kernel_type == Type) \
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return true;
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if (arch >= 75 && arch < 80)
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{
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SUPPORT(KernelType::FP16Int4Groupwise);
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SUPPORT(KernelType::FP16Int8PerChannel);
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SUPPORT(KernelType::FP16Int4PerChannel);
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}
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else if (arch >= 80 && arch < 90)
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{
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SUPPORT(KernelType::FP16Int8Groupwise);
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SUPPORT(KernelType::BF16Int8Groupwise);
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SUPPORT(KernelType::FP16Int4Groupwise);
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SUPPORT(KernelType::BF16Int4Groupwise);
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SUPPORT(KernelType::FP16Int8PerChannel);
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SUPPORT(KernelType::BF16Int8PerChannel);
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SUPPORT(KernelType::FP16Int4PerChannel);
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SUPPORT(KernelType::BF16Int4PerChannel);
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}
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else if (arch >= 90 && arch != 120)
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{
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SUPPORT(KernelType::FP16Int8Groupwise);
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SUPPORT(KernelType::BF16Int8Groupwise);
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SUPPORT(KernelType::FP16Int4Groupwise);
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SUPPORT(KernelType::BF16Int4Groupwise);
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SUPPORT(KernelType::FP16Int8PerChannel);
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SUPPORT(KernelType::BF16Int8PerChannel);
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SUPPORT(KernelType::FP16Int4PerChannel);
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SUPPORT(KernelType::BF16Int4PerChannel);
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}
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return false;
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#undef SUPPORT
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}
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} // namespace weight_only
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} // namespace kernels
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} // namespace tensorrt_llm
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