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16d2467ea8
* Update TensorRT-LLM --------- Co-authored-by: Denis Kayshev <topenkoff@gmail.com> Co-authored-by: akhoroshev <arthoroshev@gmail.com> Co-authored-by: Patrick Reiter Horn <patrick.horn@gmail.com> Update
93 lines
4.1 KiB
Plaintext
93 lines
4.1 KiB
Plaintext
/*
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* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "tensorrt_llm/common/cudaBf16Wrapper.h"
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#include "tensorrt_llm/common/cudaUtils.h"
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// TODO(oargov): literally zero performance optimization work was put into these kernels and their launch parameters,
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// since they should hopefully be fused to some gemm eventually.
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namespace tensorrt_llm::kernels
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{
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template <typename T>
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__global__ void tokenPerChannelScaleKernel(size_t const numModules, size_t const numTokens,
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int64_t const* __restrict__ cumModuleSizes, T const* __restrict__ a, T const* const* __restrict__ scales,
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T* __restrict__ result)
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{
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/*
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* This kernel applies DoRA scaling to LoRA output.
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* Like LoRA, each token in the batch may target a different adapter.
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* Each adapter may also have multiple modules, for example: QKV projection will have a different scale for Q, K and
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* V, but they will be concatenated into a single input vector.
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* `scales` is a vector of pointers to DoRA magnitude vectors. Each token will have `numModules` pointers, and
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* pointers for the same module are next to each other. For example:
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* scales = [token0_module0_ptr, token1_module0_ptr, ..., token0_module1_ptr, token1_module1_ptr, ...]
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*/
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auto const threadId = blockIdx.x * blockDim.x + threadIdx.x;
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// number of columns in the input
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auto const numChannels = cumModuleSizes[numModules - 1];
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// current thread's column
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auto const channelId = threadId % numChannels;
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// current thread's token
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auto const tokenId = threadId / numChannels;
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// offset the input column to fit in the scaling vector's column in case of multiple modules
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int64_t scaleChannelOffset = 0;
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T const* scale = nullptr;
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// this loop searches for the module the current column is a part of, in case of multiple modules
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for (auto moduleId = 0; moduleId < numModules; moduleId++)
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{
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if (channelId < cumModuleSizes[moduleId])
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{
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// pick the proper scale for the token and module
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scale = scales[numTokens * moduleId + tokenId];
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break;
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}
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// adjust scale offset
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scaleChannelOffset = cumModuleSizes[moduleId];
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}
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if (threadId < numChannels * numTokens)
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{
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// apply scaling if scale is not null (it is null in case of a non-DoRA adapter)
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result[threadId] = scale == nullptr ? a[threadId] : a[threadId] * scale[channelId - scaleChannelOffset];
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}
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}
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template <typename T>
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void tokenPerChannelScale(int64_t const numel, size_t const numModules, size_t const numTokens,
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int64_t const* __restrict__ cumModuleSizes, T const* __restrict__ a, T const* const* __restrict__ scale_ptrs,
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T* __restrict__ result, cudaStream_t stream)
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{
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dim3 block(256);
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dim3 grid((numel + 255) / 256);
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tokenPerChannelScaleKernel<T>
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<<<grid, block, 0, stream>>>(numModules, numTokens, cumModuleSizes, a, scale_ptrs, result);
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}
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template void tokenPerChannelScale<half>(int64_t const numel, size_t const numModules, size_t const numTokens,
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int64_t const* __restrict__ cumModuleSizes, half const* __restrict__ a, half const* const* __restrict__ scale_ptrs,
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half* __restrict__ result, cudaStream_t stream);
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#ifdef ENABLE_BF16
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template void tokenPerChannelScale<nv_bfloat16>(int64_t const numel, size_t const numModules, size_t const numTokens,
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int64_t const* __restrict__ cumModuleSizes, nv_bfloat16 const* __restrict__ a,
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nv_bfloat16 const* const* __restrict__ scale_ptrs, nv_bfloat16* __restrict__ result, cudaStream_t stream);
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#endif
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} // namespace tensorrt_llm::kernels
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