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Signed-off-by: Chenfei Zhang <chenfeiz@nvidia.com> Signed-off-by: Yilin Fan <206948969+nv-yilinf@users.noreply.github.com> Co-authored-by: Chenfei Zhang <chenfeiz@nvidia.com>
31 lines
1.1 KiB
C++
31 lines
1.1 KiB
C++
/*
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* Copyright (c) 2025-2025, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <cuda.h>
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#include <cuda_bf16.h>
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#include <cuda_fp8.h>
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#include <cuda_runtime.h>
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namespace tensorrt_llm::kernels::llama4_min_latency::llama4_fp8_bf16_gemm
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{
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void llama4_fp8_bf16_gemm_op(void const* A, void const* B, void* C, void const* scaling_factor, void const* pos_ids,
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bool pos_ids_int64, int num_tokens, int hidden_in, int hidden_out, cudaStream_t stream);
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} // namespace tensorrt_llm::kernels::llama4_min_latency::llama4_fp8_bf16_gemm
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