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https://github.com/NVIDIA/TensorRT-LLM.git
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60 lines
1.8 KiB
C++
60 lines
1.8 KiB
C++
/*
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* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <cuda.h>
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#include <optional>
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#include "trtllmGen_gatedAct_export/trtllm/gen/DtypeDecl.h"
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namespace tensorrt_llm
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{
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namespace kernels
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{
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struct TrtllmGenGemmGatedActRunnerOptions
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{
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gemmGatedAct::trtllm::gen::Dtype eltType;
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gemmGatedAct::trtllm::gen::Dtype outputType;
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bool deepSeekFp8{false};
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bool transposeMmaOutput{false};
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};
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class TrtllmGenGemmGatedActRunner
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{
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public:
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explicit TrtllmGenGemmGatedActRunner(TrtllmGenGemmGatedActRunnerOptions const& options);
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[[nodiscard]] size_t getWorkspaceSizeInBytes(int32_t m, int32_t n, int32_t k);
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void run(int32_t m, int32_t n, int32_t k, void const* a, float const* aScale, void const* b, float const* bScale,
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void* c, float* cScale, float* cScaleGate, void* workspace, CUstream stream, int device);
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void run(int32_t m, int32_t n, int32_t k, void const* a, void const* b, void* c, float* cScale, float* cScaleGate,
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void* workspace, CUstream stream, int device);
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private:
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void selectGemmConfig(int32_t m, int32_t n, int32_t k);
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private:
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TrtllmGenGemmGatedActRunnerOptions mOptions;
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std::optional<int> mSelectedConfigIndex;
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std::vector<int32_t> mPassingConfigIndices;
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};
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} // namespace kernels
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} // namespace tensorrt_llm
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