Jiagan Cheng 4a3a66b124 [https://nvbugs/5677746][fix] Use first PP rank's schedule result in other PP ranks to fix PP hang (#9659) ... Signed-off-by: Jiagan Cheng <jiaganc@nvidia.com>		2025-12-08 18:43:52 -08:00
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cmake	[None][doc] Rename TensorRT-LLM to TensorRT LLM for homepage and the … (#7850)	2025-09-25 21:02:35 +08:00
include/tensorrt_llm	[TRTLLM-9372][feat] Enable CuteDSL MoE with Large EP (#9592)	2025-12-05 22:08:52 -08:00
kernels	[https://nvbugs/5567586][feat] Ampere xqa swa specdec for GPT-OSS Eagle3-one-model (#8383)	2025-12-08 11:16:05 -08:00
micro_benchmarks	[TRTLLM-9197][infra] Move thirdparty stuff to it's own listfile (#8986)	2025-11-20 16:44:23 -08:00
tensorrt_llm	[https://nvbugs/5677746][fix] Use first PP rank's schedule result in other PP ranks to fix PP hang (#9659)	2025-12-08 18:43:52 -08:00
tests	[None][feat] Enable NCCL_SYMMETRIC as default fallback for AllReduce (#9314)	2025-12-07 09:43:26 -08:00
CMakeLists.txt	[TRTLLM-9211][infra] Minor fixes to 3rdparty/CMakelists (#9365)	2025-11-23 22:57:02 -08:00
conandata.yml	infra: add conan (#3744)	2025-04-30 11:53:14 -07:00
conanfile.py	feat: large-scale EP(part 6: Online EP load balancer integration for GB200 nvfp4) (#4818)	2025-06-08 10:25:18 +08:00
libnuma_conan.py	fix cuda driver link issue with driver version less than 12.3 (#5025)	2025-06-10 15:27:39 +08:00