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https://github.com/NVIDIA/TensorRT-LLM.git
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5955b8afba
* Update TensorRT-LLM --------- Co-authored-by: Shixiaowei02 <39303645+Shixiaowei02@users.noreply.github.com>
125 lines
3.5 KiB
C++
125 lines
3.5 KiB
C++
/*
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* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include "tensorrt_llm/runtime/common.h"
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#include <NvInferRuntime.h>
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#include <optional>
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#include <vector>
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namespace tensorrt_llm::runtime
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{
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class WorldConfig
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{
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public:
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static SizeType constexpr kDefaultGpusPerNode = 8;
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explicit WorldConfig(SizeType tensorParallelism = 1, SizeType pipelineParallelism = 1, SizeType rank = 0,
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SizeType gpusPerNode = kDefaultGpusPerNode,
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std::optional<std::vector<SizeType>> const& deviceIds = std::nullopt);
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[[nodiscard]] SizeType constexpr getSize() const noexcept
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{
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return mTensorParallelism * mPipelineParallelism;
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}
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[[nodiscard]] SizeType constexpr getTensorParallelism() const noexcept
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{
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return mTensorParallelism;
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}
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[[nodiscard]] bool constexpr isTensorParallel() const noexcept
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{
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return mTensorParallelism > 1;
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}
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[[nodiscard]] SizeType constexpr getPipelineParallelism() const noexcept
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{
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return mPipelineParallelism;
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}
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[[nodiscard]] bool constexpr isPipelineParallel() const noexcept
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{
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return mPipelineParallelism > 1;
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}
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[[nodiscard]] SizeType constexpr getRank() const noexcept
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{
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return mRank;
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}
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[[nodiscard]] SizeType constexpr getGpusPerNode() const noexcept
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{
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return mGpusPerNode;
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}
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[[nodiscard]] SizeType getGpusPerGroup() const noexcept
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{
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return static_cast<SizeType>(mDeviceIds.size());
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}
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[[nodiscard]] SizeType getDevice() const noexcept
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{
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return mDeviceIds[mRank % getGpusPerGroup()];
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}
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[[nodiscard]] SizeType constexpr getPipelineParallelRank() const noexcept
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{
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return mRank / mTensorParallelism;
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}
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[[nodiscard]] SizeType constexpr getTensorParallelRank() const noexcept
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{
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return mRank % mTensorParallelism;
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}
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[[nodiscard]] bool constexpr isFirstPipelineParallelRank() const noexcept
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{
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return getPipelineParallelRank() == 0;
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}
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//! \brief Is my rank the last rank in its pipeline?
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[[nodiscard]] bool constexpr isLastPipelineParallelRank() const noexcept
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{
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return getPipelineParallelRank() == getPipelineParallelism() - 1;
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}
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[[nodiscard]] SizeType constexpr getLastRank() const noexcept
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{
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return getSize() - 1;
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}
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[[nodiscard]] std::vector<SizeType> getPipelineParallelGroup() const;
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static bool validConfig(SizeType tensorParallelism, SizeType pipelineParallelism);
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static WorldConfig mpi(SizeType gpusPerNode = kDefaultGpusPerNode,
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std::optional<SizeType> tensorParallelism = std::nullopt,
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std::optional<SizeType> pipelineParallelism = std::nullopt,
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std::optional<std::vector<SizeType>> const& deviceIds = std::nullopt);
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private:
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SizeType mTensorParallelism;
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SizeType mPipelineParallelism;
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SizeType mRank;
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SizeType mGpusPerNode;
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std::vector<SizeType> mDeviceIds;
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};
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} // namespace tensorrt_llm::runtime
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