mirror of
https://github.com/NVIDIA/TensorRT-LLM.git
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51 lines
2.1 KiB
C++
51 lines
2.1 KiB
C++
/*
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* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "tensorrt_llm/batch_manager/assignReqSeqSlots.h"
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#include "tensorrt_llm/common/logger.h"
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#include "tensorrt_llm/common/nvtxUtils.h"
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void tensorrt_llm::batch_manager::AssignReqSeqSlots::operator()(SequenceSlotManager& seqSlotManager,
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RequestVector const& contextRequests, RequestVector const& generationRequests) const
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{
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TLLM_LOG_TRACE("%s start", __PRETTY_FUNCTION__);
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NVTX3_SCOPED_RANGE(AssignReqSeqSlots);
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seqSlotManager.freeIdleSequenceSlots();
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for (auto const& requests : {contextRequests, generationRequests})
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{
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for (auto const& llmReq : requests)
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{
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if (llmReq->isDisaggGenerationInitState())
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{
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// Skip assigning sequence slot for DISAGG_GENERATION_INIT request
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continue;
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}
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auto const isReqNew = (llmReq->isContextInitState() && !llmReq->mSeqSlot)
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|| (llmReq->isDisaggGenerationTransmissionComplete());
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if (isReqNew && llmReq->getReturnPerfMetrics())
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{
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llmReq->setFirstScheduledTime();
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}
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auto const reqSeqSlot = seqSlotManager.getSequenceSlot(isReqNew, llmReq->mRequestId);
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TLLM_CHECK_WITH_INFO(reqSeqSlot, "Unable to get batch slot for request ID %lu", llmReq->mRequestId);
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llmReq->mSeqSlot = reqSeqSlot;
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}
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}
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TLLM_LOG_TRACE("%s stop", __PRETTY_FUNCTION__);
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}
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