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https://github.com/NVIDIA/TensorRT-LLM.git
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31624b079a
* Add TRT-LLM Gen MOE to Deepseek fix fused moe rebase bug. Fix atol in test_fp4_gemm_quantize.py fix fused moe rebase bug. Fix FusedMoe. Disable 2nd routing kernel preexit Bump routing reduction to fp32 Disable PDL for fc1 [DEBUG] Lift token limit to 16k [Bugfix] Token limit to 16k + fp32 routing + tanh Make fp8 tileN 8 Fix FP8 MoE + Remove redundent temp output for FP4 [FP8-only] Avoid wasting CTAs for activation kernel fix: unblock FP8 weightloading with trtllm-gen Remove max_token limit for trtllm-gen path perf: avoid type-conversion and fill_ from aten Minor fix Signed-off-by: Hao Lu <haolu@nvidia.com> * Fix rebase issues Signed-off-by: Hao Lu <haolu@nvidia.com> * Fix compile issue Signed-off-by: Zongfei Jing <20381269+zongfeijing@users.noreply.github.com> * CI clean Signed-off-by: Zongfei Jing <20381269+zongfeijing@users.noreply.github.com> --------- Signed-off-by: Hao Lu <haolu@nvidia.com> Signed-off-by: Zongfei Jing <20381269+zongfeijing@users.noreply.github.com> Co-authored-by: Zongfei Jing <20381269+zongfeijing@users.noreply.github.com>
82 lines
3.2 KiB
C++
82 lines
3.2 KiB
C++
/*
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* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include "tensorrt_llm/common/quantization.h"
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#include <cuda_fp16.h>
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#include <cuda_runtime.h>
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namespace tensorrt_llm
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{
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enum class FP4QuantizationSFLayout
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{
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// Block scale factors are stored in swizzled layout for cutlass FP4 kernel. Scale factor
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// blocks are organized in 512-byte blocks in global memory, with each block having 128x4 FP8 values.
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// The SF matrix dimensions are therefore padded - rows to the nearest multiple of 128 and columns to
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// the nearest multiple of 4.
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//
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// The scale factor block rows map to data block rows in an interleaved pattern:
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// For a scale factor row 'i', it maps to data block row: (i % 4) * 32 + (i / 4)
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// Column 'j' in the scale factor block corresponds to scaling the j-th block in the data tensor.
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//
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// Please refer to https://nvbugs/4165523 for more details about the swizzled layout.
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SWIZZLED,
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// Block scale factors are stored in linear layout (row-major). This is used in some trtllm-gen kernels standard.
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LINEAR
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};
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#define PadUpFn(X, Y) ((X + Y - 1) / (Y) * (Y))
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// totalCloumn should be in SFMatrix, not activation Matrix, so no sfVecSize needed.
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inline int computeFP4SwizzledLayoutSFSize(int totalRow, int totalColumn)
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{
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int paddedRow = PadUpFn(totalRow, 128);
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int paddedColumn = PadUpFn(totalColumn, 4);
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return paddedRow * paddedColumn;
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}
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inline int computeFP4LinearLayoutSFSize(int totalRow, int totalColumn)
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{
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return totalRow * totalColumn;
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}
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namespace kernels
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{
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template <typename T>
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void invokeQuantization(
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int8_t* dst, T const* src, int64_t const size, float const* scalePtr, cudaStream_t stream = 0, int maxGirdSize = 0);
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template <typename T, typename QuantT>
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void invokePerTokenQuantization(QuantT* dst, T const* src, int64_t const numRows, int64_t const numCols,
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float const* clampPtr, float* scalePtr, float* sumPtr, tensorrt_llm::common::QuantMode quantMode,
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cudaStream_t stream = 0);
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template <typename T>
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void invokeFP4Quantization(int m, int n, T const* input, float const* globalScale, int64_t* output, int32_t* SFOuput,
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bool useUE8M0, FP4QuantizationSFLayout layout, int multiProcessorCount, cudaStream_t stream = 0);
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template <typename T>
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void invokeBatchedFP4Quantization(int b, int m, int n, T const* input, float const* globalScale, int64_t* output,
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int32_t* SFOuput, bool useUE8M0, int multiProcessorCount, cudaStream_t stream = 0);
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void invokeNVFP4BlockScaleInterleave(
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int b, int m, int n, uint8_t const* SFIn, uint8_t* SFOutput, int multiProcessorCount, cudaStream_t stream = 0);
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} // namespace kernels
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} // namespace tensorrt_llm
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