mirror of
https://github.com/NVIDIA/TensorRT-LLM.git
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128 lines
3.1 KiB
Plaintext
128 lines
3.1 KiB
Plaintext
/*
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* Copyright (c) 2025-2025, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include "tensorrt_llm/common/config.h"
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#include <cuda_fp8.h>
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#include "tensorrt_llm/common/envUtils.h"
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TRTLLM_NAMESPACE_BEGIN
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namespace kernels::llama4_min_latency
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{
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namespace llama4_bf16_bf16_gemm
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{
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constexpr int GEMM_K = 5120;
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constexpr int BLOCK_SIZE = 256;
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constexpr int NUM_EXPERTS = 128;
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constexpr int VEC_SIZE = 4;
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} // namespace llama4_bf16_bf16_gemm
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namespace llama4_fp8_bf16_gemm
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{
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constexpr int HIDDEN_IN = 5120;
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constexpr int HIDDEN_OUT = 896;
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constexpr int Q_HIDDEN_OUT = 640;
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constexpr float FLOOR_SCALE = 8192.0;
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constexpr float ATTN_SCALE = 0.1;
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constexpr int BLOCK_SIZE = 128;
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constexpr int WARP_SIZE = 32;
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constexpr int WARP_PER_BLOCK = BLOCK_SIZE / WARP_SIZE;
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constexpr int VEC_SIZE = 8;
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constexpr bool ENABLE_ACQBULK = 1;
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constexpr bool ENABLE_PREFETCH = 1;
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constexpr bool ENABLE_PREEXIT = 0;
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} // namespace llama4_fp8_bf16_gemm
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namespace llama4_fp8_fp8_gemm_swiglu
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{
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constexpr int BLOCK_SIZE = 128;
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constexpr int WARP_SIZE = 32;
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constexpr int VEC_SIZE = 8;
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constexpr bool ENABLE_ACQBULK = 1;
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constexpr bool ENABLE_PREFETCH = 0;
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constexpr bool ENABLE_PREEXIT = 0;
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} // namespace llama4_fp8_fp8_gemm_swiglu
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inline void launch_kernel_pdl(
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dim3 grid_dim, dim3 block_dim, cudaStream_t stream, void* kernel_func, void* args[], int num_args)
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{
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cudaLaunchConfig_t config;
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config.gridDim = grid_dim;
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config.blockDim = block_dim;
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config.dynamicSmemBytes = 0;
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config.stream = stream;
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cudaLaunchAttribute attrs[1];
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config.attrs = attrs;
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config.numAttrs = 0;
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attrs[config.numAttrs].id = cudaLaunchAttributeProgrammaticStreamSerialization;
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attrs[config.numAttrs++].val.programmaticStreamSerializationAllowed
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= (tensorrt_llm::common::getEnvEnablePDL() ? 1 : 0);
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cudaLaunchKernelExC(&config, (void const*) kernel_func, args);
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}
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inline int div_up(int x, int y)
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{
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return (x + y - 1) / y;
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}
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__device__ __forceinline__ float2 ffma2(float2 x, float2 y, float2 acc)
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{
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#if (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ == 1000))
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return __ffma2_rn(x, y, acc);
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#else
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return make_float2(x.x * y.x + acc.x, x.y * y.y + acc.y);
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#endif
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}
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__device__ __forceinline__ float silu(float x)
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{
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return x / (1.0f + __expf(-x));
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}
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__device__ __forceinline__ float sigmoid(float x)
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{
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return 1.0f / (1.0f + __expf(-x));
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}
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struct __align__(8) aligned_fp8x8
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{
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__align__(8) __nv_fp8x4_e4m3 data[2];
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};
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struct __align__(8) aligned_bfloat16x4
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{
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__align__(8) __nv_bfloat16 data[4];
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};
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} // namespace kernels::llama4_min_latency
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TRTLLM_NAMESPACE_END
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