Bo Deng dd25595ae8 [TRTLLM-7964][infra] Set nixl to default cache transceiver backend (#7926) ... Signed-off-by: Bo Deng <deemod@nvidia.com>		2025-10-19 19:24:43 +08:00
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cmake	[None][doc] Rename TensorRT-LLM to TensorRT LLM for homepage and the … (#7850)	2025-09-25 21:02:35 +08:00
include/tensorrt_llm	[https://nvbugs/5404000][fix] Ensure consistency between firstTokenTime and lastTokenTime (#8294)	2025-10-14 08:15:08 -04:00
kernels	[None][feat] Add fmha_v2 kernel for head_dim=80 and sm=100 to support VLM (#8392)	2025-10-17 19:42:47 +08:00
micro_benchmarks	[TRTLLM-6286] [perf] Add NoSmem epilogue schedule and dynamic cluster shape for sm10x group gemm (#7757)	2025-09-21 11:38:17 +08:00
tensorrt_llm	[TRTLLM-7964][infra] Set nixl to default cache transceiver backend (#7926)	2025-10-19 19:24:43 +08:00
tests	[None][feat] Revise the calculation related to TileN in routing of MOE TRTLLM backend (#8148)	2025-10-16 09:15:46 +08:00
CMakeLists.txt	[None][doc] Rename TensorRT-LLM to TensorRT LLM for homepage and the … (#7850)	2025-09-25 21:02:35 +08:00
conandata.yml	infra: add conan (#3744)	2025-04-30 11:53:14 -07:00
conanfile.py	feat: large-scale EP(part 6: Online EP load balancer integration for GB200 nvfp4) (#4818)	2025-06-08 10:25:18 +08:00
libnuma_conan.py	fix cuda driver link issue with driver version less than 12.3 (#5025)	2025-06-10 15:27:39 +08:00