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<li class="toctree-l1"><a class="reference internal" href="../blogs/H100vsA100.html">H100 has 4.6x A100 Performance in TensorRT-LLM, achieving 10,000 tok/s at 100ms to first token</a></li>
<li class="toctree-l1"><a class="reference internal" href="../blogs/H200launch.html">H200 achieves nearly 12,000 tokens/sec on Llama2-13B with TensorRT-LLM</a></li>
<li class="toctree-l1"><a class="reference internal" href="../blogs/Falcon180B-H200.html">Falcon-180B on a single H200 GPU with INT4 AWQ, and 6.7x faster Llama-70B over A100</a></li>
<li class="toctree-l1"><a class="reference internal" href="../blogs/quantization-in-TRT-LLM.html">Speed up inference with SOTA quantization techniques in TRT-LLM</a></li>
<li class="toctree-l1"><a class="reference internal" href="../blogs/XQA-kernel.html">New XQA-kernel provides 2.4x more Llama-70B throughput within the same latency budget</a></li>
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<section id="support-matrix">
<span id="id1"></span><h1>Support Matrix<a class="headerlink" href="#support-matrix" title="Link to this heading"></a></h1>
<p>TensorRT-LLM optimizes the performance of a range of well-known models on NVIDIA GPUs. The following sections provide a list of supported GPU architectures as well as important features implemented in TensorRT-LLM.</p>
<section id="hardware">
<span id="support-matrix-hardware"></span><h2>Hardware<a class="headerlink" href="#hardware" title="Link to this heading"></a></h2>
<p>The following table shows the supported hardware for TensorRT-LLM.</p>
<p>If a GPU is not listed, it is important to note that TensorRT-LLM is expected to work on GPUs based on the Volta, Turing, Ampere, Hopper, and Ada Lovelace architectures. Certain limitations may, however, apply.</p>
<table class="docutils align-default">
<colgroup>
<col style="width: 20.0%" />
<col style="width: 80.0%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"></th>
<th class="head"><p>Hardware Compatibility</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>Operating System</p></td>
<td><p>TensorRT-LLM requires Linux x86_64 or Windows.</p></td>
</tr>
<tr class="row-odd"><td><p>GPU Model Architectures</p></td>
<td><ul class="simple">
<li><p><a class="reference external" href="https://www.nvidia.com/en-us/data-center/h100/">NVIDIA Hopper H100 GPU</a></p></li>
<li><p><a class="reference external" href="https://www.nvidia.com/en-us/data-center/l40s/">NVIDIA L40S GPU</a></p></li>
<li><p><a class="reference external" href="https://www.nvidia.com/en-us/technologies/ada-architecture/">NVIDIA Ada Lovelace GPU</a></p></li>
<li><p><a class="reference external" href="https://www.nvidia.com/en-us/data-center/a100/">NVIDIA Ampere A100 GPU</a></p></li>
<li><p><a class="reference external" href="https://www.nvidia.com/en-us/data-center/products/a30-gpu/">NVIDIA A30 GPU</a></p></li>
<li><p><a class="reference external" href="https://www.nvidia.com/en-us/data-center/tesla-t4/">NVIDIA Turing T4 GPU</a></p></li>
<li><p><a class="reference external" href="https://www.nvidia.com/en-us/data-center/v100/">NVIDIA Volta V100 GPU</a> (experimental)</p></li>
</ul>
</td>
</tr>
</tbody>
</table>
</section>
<section id="software">
<span id="support-matrix-software"></span><h2>Software<a class="headerlink" href="#software" title="Link to this heading"></a></h2>
<p>The following table shows the supported software for TensorRT-LLM.</p>
<table class="docutils align-default">
<colgroup>
<col style="width: 20.0%" />
<col style="width: 80.0%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"></th>
<th class="head"><p>Software Compatibility</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>Container</p></td>
<td><p>[24.05](<a class="reference external" href="https://docs.nvidia.com/deeplearning/frameworks/support-matrix/index.html">https://docs.nvidia.com/deeplearning/frameworks/support-matrix/index.html</a>)</p></td>
</tr>
<tr class="row-odd"><td><p>TensorRT</p></td>
<td><p>[10.1](<a class="reference external" href="https://docs.nvidia.com/deeplearning/tensorrt/release-notes/index.html">https://docs.nvidia.com/deeplearning/tensorrt/release-notes/index.html</a>)</p></td>
</tr>
<tr class="row-even"><td><p>Precision</p></td>
<td><ul class="simple">
<li><p>Hopper (SM90) - FP32, FP16, BF16, FP8, INT8, INT4</p></li>
<li><p>Ada Lovelace (SM89) - FP32, FP16, BF16, FP8, INT8, INT4</p></li>
<li><p>Ampere (SM80, SM86) - FP32, FP16, BF16, INT8, INT4(3)</p></li>
<li><p>Turing (SM75) - FP32, FP16, INT8(1), INT4</p></li>
<li><p>Volta (SM70) - FP32, FP16, INT8(1), INT4(2)</p></li>
</ul>
</td>
</tr>
<tr class="row-odd"><td><p>Models</p></td>
<td><ul class="simple">
<li><p>[Arctic](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/arctic">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/arctic</a>)</p></li>
<li><p>[Baichuan](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/baichuan">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/baichuan</a>)</p></li>
<li><p>[BART](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec</a>)</p></li>
<li><p>[BERT](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bert">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bert</a>)</p></li>
<li><p>[BLOOM](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bloom">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bloom</a>)</p></li>
<li><p>[ByT5](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec</a>)</p></li>
<li><p>[ChatGLM](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/chatglm">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/chatglm</a>)</p></li>
<li><p>[DBRX](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/dbrx">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/dbrx</a>)</p></li>
<li><p>[FairSeq NMT](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec</a>)</p></li>
<li><p>[Falcon](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/falcon">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/falcon</a>)</p></li>
<li><p>[Flan-T5](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec</a>) (4)</p></li>
<li><p>[Gemma](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gemma">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gemma</a>)</p></li>
<li><p>[GPT](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt</a>)</p></li>
<li><p>[GPT-J](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gptj">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gptj</a>)</p></li>
<li><p>[GPT-Nemo](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt</a>)</p></li>
<li><p>[GPT-NeoX](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gptneox">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gptneox</a>)</p></li>
<li><p>[InternLM](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/internlm">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/internlm</a>)</p></li>
<li><p>[InternLM2](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/internlm2">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/internlm2</a>)</p></li>
<li><p>[LLaMA](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/llama">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/llama</a>)</p></li>
<li><p>[LLaMA-v2](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/llama">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/llama</a>)</p></li>
<li><p>[Mamba](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mamba">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mamba</a>)</p></li>
<li><p>[mBART](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec</a>)</p></li>
<li><p>[Mistral](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mixtral">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mixtral</a>)</p></li>
<li><p>[MPT](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mpt">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mpt</a>)</p></li>
<li><p>[mT5](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec</a>)</p></li>
<li><p>[OPT](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/opt">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/opt</a>)</p></li>
<li><p>[Phi-1.5/Phi-2/Phi-3](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/phi">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/phi</a>)</p></li>
<li><p>[Qwen/Qwen1.5](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/qwen">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/qwen</a>)</p></li>
<li><p>[Qwen-VL](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/qwenvl">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/qwenvl</a>)</p></li>
<li><p>[RecurrentGemma](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/recurrentgemma">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/recurrentgemma</a>)</p></li>
<li><p>[Replit Code](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mpt">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mpt</a>)</p></li>
<li><p>[RoBERTa](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bert">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bert</a>)</p></li>
<li><p>[SantaCoder](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt</a>)</p></li>
<li><p>[Skywork](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/skywork">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/skywork</a>)</p></li>
<li><p>[Smaug](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/smaug">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/smaug</a>)</p></li>
<li><p>[StarCoder](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt</a>)</p></li>
<li><p>[T5](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec</a>)</p></li>
<li><p>[Whisper](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/whisper">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/whisper</a>)</p></li>
</ul>
</td>
</tr>
<tr class="row-even"><td><p>Multi-Modal Models (5)</p></td>
<td><ul class="simple">
<li><p>[BLIP2 w/ OPT](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
<li><p>[BLIP2 w/ T5](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
<li><p>[CogVLM](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)(6">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)(6</a>)</p></li>
<li><p>[Deplot](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
<li><p>[Fuyu](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
<li><p>[Kosmos](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
<li><p>[LLaVA-v1.5](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
<li><p>[NeVA](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
<li><p>[Nougat](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
<li><p>[Phi-3-vision](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
<li><p>[Video NeVA](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
<li><p>[VILA](<a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal">https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal</a>)</p></li>
</ul>
</td>
</tr>
</tbody>
</table>
<p>(1) INT8 SmoothQuant is not supported on SM70 and SM75.<br>
(2) INT4 AWQ and GPTQ are not supported on SM &lt; 75.<br>
(3) INT4 AWQ and GPTQ with FP8 activations require SM &gt;= 89.<br>
(4) <a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/main/examples/enc_dec">Encoder-Decoder</a> provides general encoder-decoder functionality that supports many encoder-decoder models such as T5 family, BART family, Whisper family, NMT family, and so on.
(5) Multi-modal provides general multi-modal functionality that supports many multi-modal architectures such as BLIP2 family, LLaVA family, and so on.
(6) Only supports bfloat16 precision.</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>Support for FP8 and quantized data types (INT8 or INT4) is not implemented for all the models. Refer to <a class="reference internal" href="precision.html#precision"><span class="std std-ref">Numerical Precision</span></a> and <a class="reference external" href="https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples">examples</a> folder for additional information.</p>
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