mirror of
https://github.com/NVIDIA/TensorRT-LLM.git
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61 lines
1.8 KiB
Plaintext
61 lines
1.8 KiB
Plaintext
/*
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* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <cuda_fp16.h>
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#include <cuda_runtime.h>
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#include <stdint.h>
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namespace tensorrt_llm
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{
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namespace kernels
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{
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static inline __device__ int8_t float_to_int8_rn(float x)
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{
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uint32_t dst;
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asm volatile("cvt.rni.sat.s8.f32 %0, %1;" : "=r"(dst) : "f"(x));
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return reinterpret_cast<const int8_t&>(dst);
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}
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static inline __device__ uint32_t float4_to_char4(float x, float y, float z, float w)
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{
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uint32_t dst;
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#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 720
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uint32_t a;
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asm volatile("cvt.rni.sat.s32.f32 %0, %1;\n" : "=r"(a) : "f"(x));
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uint32_t b;
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asm volatile("cvt.rni.sat.s32.f32 %0, %1;\n" : "=r"(b) : "f"(y));
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uint32_t c;
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asm volatile("cvt.rni.sat.s32.f32 %0, %1;\n" : "=r"(c) : "f"(z));
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uint32_t d;
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asm volatile("cvt.rni.sat.s32.f32 %0, %1;\n" : "=r"(d) : "f"(w));
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asm volatile("cvt.pack.sat.s8.s32.b32 %0, %1, %2, 0;\n" : "=r"(dst) : "r"(d), "r"(c));
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asm volatile("cvt.pack.sat.s8.s32.b32 %0, %1, %2, %0;\n" : "+r"(dst) : "r"(b), "r"(a));
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#else
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char4 tmp;
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tmp.x = x;
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tmp.y = y;
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tmp.z = z;
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tmp.w = w;
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dst = reinterpret_cast<const uint32_t&>(tmp);
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#endif
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return dst;
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}
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} // namespace kernels
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} // namespace tensorrt_llm
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