mirror of
https://github.com/NVIDIA/TensorRT-LLM.git
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16d2467ea8
* Update TensorRT-LLM --------- Co-authored-by: Denis Kayshev <topenkoff@gmail.com> Co-authored-by: akhoroshev <arthoroshev@gmail.com> Co-authored-by: Patrick Reiter Horn <patrick.horn@gmail.com> Update
112 lines
4.0 KiB
C++
112 lines
4.0 KiB
C++
/*
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* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "tensorrt_llm/common/cudaUtils.h"
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#include "tensorrt_llm/kernels/quantization.h"
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#include "tensorrt_llm/thop/thUtils.h"
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#include <ATen/cuda/EmptyTensor.h>
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#include <cuda_fp16.h>
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#include <cstdint>
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namespace torch_ext
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{
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// self: [M, K], fp16/bf16/fp8_quantized
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// globalScale: [1] float, = (448 * 6) / self.abs().max()
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// nvfp4: sfVecSize = 16, sfUseUE8M0 = false
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// mxfp4: sfVecSize = 32 (not supported yet), sfUseUE8M0 = true
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// alignment: sfVecSize
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// returns self_fp4, self_block_scale_factors
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// self_fp4: [M, K / 2], FLOAT4_E2M1X2
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// self_block_scale_factors: ceil(M / 128) * 128 * ceil(K / sfVecSize / 4) * 4, SF_DTYPE (UE4M3 or UE8M0)
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std::tuple<at::Tensor, at::Tensor> fp4_quantize(
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at::Tensor const& self, at::Tensor const& globalScale, int64_t sfVecSize, bool sfUseUE8M0)
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{
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CHECK_TH_CUDA(self);
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CHECK_CONTIGUOUS(self);
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CHECK_INPUT(globalScale, torch::kFloat32);
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TORCH_CHECK(sfVecSize == 16, "sfVecSize can only be 16");
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auto const& inputShape = self.sizes();
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auto const& rank = inputShape.size();
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TORCH_CHECK(rank >= 2, "Input should be >=2D tensor.");
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int64_t m = 1;
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for (auto i = 0; i < rank - 1; i++)
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{
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m *= inputShape[i];
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}
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auto const k = inputShape[rank - 1];
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TORCH_CHECK(k % sfVecSize == 0);
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std::vector<int64_t> outputShape(inputShape.begin(), inputShape.end());
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outputShape[rank - 1] = k / 2;
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at::Tensor valueE2M1 = at::detail::empty_cuda(outputShape, FLOAT4_E2M1X2, self.device(), /* stride */ std::nullopt);
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at::Tensor scaleFP8SF = at::detail::empty_cuda({tensorrt_llm::computeSFSize(m, k / sfVecSize)}, SF_DTYPE,
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self.device(), /* stride */ std::nullopt); // 1D tensor
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const thread_local int mMultiProcessorCount = tensorrt_llm::common::getMultiProcessorCount();
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#define LAUNCH_FP4_QUANTIZE_KERNEL(T) \
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tensorrt_llm::kernels::invokeFP4Quantization(m, k, reinterpret_cast<T*>(self.data_ptr()), \
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globalScale.data_ptr<float>(), reinterpret_cast<int64_t*>(valueE2M1.data_ptr()), \
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reinterpret_cast<int32_t*>(scaleFP8SF.data_ptr()), sfUseUE8M0, mMultiProcessorCount, \
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at::cuda::getCurrentCUDAStream(self.get_device()));
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if (self.scalar_type() == at::ScalarType::Half)
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{
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LAUNCH_FP4_QUANTIZE_KERNEL(half)
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}
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else if (self.scalar_type() == at::ScalarType::BFloat16)
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{
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#ifdef ENABLE_BF16
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LAUNCH_FP4_QUANTIZE_KERNEL(__nv_bfloat16)
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#else
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C10_THROW_ERROR(NotImplementedError, "BFloat16 must be enabled to quantize an bf16 tensor to fp4.");
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#endif
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}
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else if (self.scalar_type() == at::ScalarType::Float8_e4m3fn)
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{
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#ifdef ENABLE_FP8
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LAUNCH_FP4_QUANTIZE_KERNEL(__nv_fp8_e4m3)
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#else
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C10_THROW_ERROR(NotImplementedError, "FP8 must be enabled to quantize an fp8 tensor to fp4.");
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#endif
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}
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else
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{
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C10_THROW_ERROR(NotImplementedError, "fp4_quantize only supports input tensor with dtypes fp16/bf16/e4m3.");
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}
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#undef LAUNCH_FP4_QUANTIZE_KERNEL
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return {valueE2M1, scaleFP8SF};
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}
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} // namespace torch_ext
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TORCH_LIBRARY_FRAGMENT(trtllm, m)
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{
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m.def("fp4_quantize(Tensor input, Tensor globalScale, int sfVecSize, bool sfUseUE8M0=False) -> (Tensor, Tensor)");
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}
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TORCH_LIBRARY_IMPL(trtllm, CUDA, m)
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{
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m.impl("fp4_quantize", &torch_ext::fp4_quantize);
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}
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