mirror of
https://github.com/NVIDIA/TensorRT-LLM.git
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ed887940d4
Replace libtensorrt_llm_nvrtc_wrapper.so with its source code, which consists of two parts: 1. NVRTC glue code 2. XQA kernel code During TensorRT-LLM build, XQA kernel code is embedded as C++ arries via gen_cpp_header.py and passed to NVRTC for JIT compilation. Signed-off-by: Ming Wei <2345434+ming-wei@users.noreply.github.com>
64 lines
2.5 KiB
Plaintext
64 lines
2.5 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: NVIDIA TensorRT Source Code License Agreement
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*
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* NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
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* property and proprietary rights in and to this material, related
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* documentation and any modifications thereto. Any use, reproduction,
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* disclosure or distribution of this material and related documentation
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* without an express license agreement from NVIDIA CORPORATION or
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* its affiliates is strictly prohibited.
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*/
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#pragma once
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#include "cuda_hint.cuh"
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#include "mha_stdheaders.cuh"
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#ifndef __CUDACC__
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#include <cuda_runtime.h>
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#endif
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#include <cuda_fp16.h>
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#include <cuda_fp8.h>
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// for both a and b, outer-dim is gemm-K and inner-dim is gemm-M or gemm-N
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// acc is used as both input and output.
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template <typename InputElem>
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__device__ inline void mma(float (&acc)[2][2], uint32_t const (&a)[2][2], uint32_t const (&b)[2][1])
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{
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static_assert(mha::is_same_v<InputElem, half> || mha::is_same_v<InputElem, __nv_bfloat16>, "not implemented");
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if (mha::is_same_v<InputElem, half>)
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{
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asm("mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 \n"
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" {%0, %1, %2, %3}, \n"
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" {%4, %5, %6, %7}, \n"
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" {%8, %9}, \n"
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" {%0, %1, %2, %3}; \n"
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: "+f"(acc[0][0]), "+f"(acc[0][1]), "+f"(acc[1][0]), "+f"(acc[1][1])
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: "r"(a[0][0]), "r"(a[0][1]), "r"(a[1][0]), "r"(a[1][1]), "r"(b[0][0]), "r"(b[1][0]));
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}
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else if constexpr (mha::is_same_v<InputElem, __nv_bfloat16>)
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{
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asm("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 \n"
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" {%0, %1, %2, %3}, \n"
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" {%4, %5, %6, %7}, \n"
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" {%8, %9}, \n"
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" {%0, %1, %2, %3}; \n"
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: "+f"(acc[0][0]), "+f"(acc[0][1]), "+f"(acc[1][0]), "+f"(acc[1][1])
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: "r"(a[0][0]), "r"(a[0][1]), "r"(a[1][0]), "r"(a[1][1]), "r"(b[0][0]), "r"(b[1][0]));
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}
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else if constexpr (mha::is_same_v<InputElem, __nv_fp8_e4m3>)
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{
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asm("mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32 \n"
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" {%0, %1, %2, %3}, \n"
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" {%4, %5, %6, %7}, \n"
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" {%8, %9}, \n"
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" {%0, %1, %2, %3}; \n"
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: "+f"(acc[0][0]), "+f"(acc[0][1]), "+f"(acc[1][0]), "+f"(acc[1][1])
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: "r"(a[0][0]), "r"(a[0][1]), "r"(a[1][0]), "r"(a[1][1]), "r"(b[0][0]), "r"(b[1][0]));
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}
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else
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{
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trap();
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}
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}
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