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7f5716ef83
* feat: TRT-LLM Gen FP8 MoE Llama4 Signed-off-by: Nikita Korobov <nkorobov@nvidia.com> * feat: TRT-LLM Gen llama4 MoE Top1 routing Signed-off-by: Jiqun Tu <jtu@nvidia.com> * feat: add per tensor FP8 TRT-LLM Gen GEMMs Signed-off-by: Nikita Korobov <nkorobov@nvidia.com> * Update Signed-off-by: Chenfei Zhang <chenfeiz@nvidia.com> * Update Signed-off-by: Chenfei Zhang <chenfeiz@nvidia.com> * Add license for cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/gemmCubins Signed-off-by: Chenfei Zhang <chenfeiz@nvidia.com> * Add guard for routingIndicesClusterKernel Signed-off-by: Chenfei Zhang <chenfeiz@nvidia.com> * Guard sm90+ for routingkernels Signed-off-by: Chenfei Zhang <chenfeiz@nvidia.com> * Guard sm90+ for routingkernels Signed-off-by: Chenfei Zhang <chenfeiz@nvidia.com> --------- Signed-off-by: Nikita Korobov <nkorobov@nvidia.com> Signed-off-by: Jiqun Tu <jtu@nvidia.com> Signed-off-by: Chenfei Zhang <chenfeiz@nvidia.com> Co-authored-by: Nikita Korobov <nkorobov@nvidia.com> Co-authored-by: Jiqun Tu <jtu@nvidia.com>
60 lines
1.7 KiB
C++
60 lines
1.7 KiB
C++
/*
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* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <cuda.h>
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#include "tensorrt_llm/kernels/trtllmGenKernels/common/Dtype.h"
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#include <optional>
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namespace tensorrt_llm
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{
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namespace kernels
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{
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struct TrtllmGenGemmRunnerOptions
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{
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Dtype eltType;
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Dtype outputType;
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bool deepSeekFp8{false};
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bool transposeMmaOutput{false};
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};
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class TrtllmGenGemmRunner
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{
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public:
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explicit TrtllmGenGemmRunner(TrtllmGenGemmRunnerOptions const& options);
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[[nodiscard]] size_t getWorkspaceSizeInBytes(int32_t m, int32_t n, int32_t k);
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void run(int32_t m, int32_t n, int32_t k, void const* a, float const* aScale, void const* b, float const* bScale,
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void* c, float* cScale, void* workspace, CUstream stream, int device);
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void run(int32_t m, int32_t n, int32_t k, void const* a, void const* b, void* c, float* cScale, void* workspace,
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CUstream stream, int device);
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private:
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void selectGemmConfig(int32_t m, int32_t n, int32_t k);
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private:
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TrtllmGenGemmRunnerOptions mOptions;
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std::optional<int> mSelectedConfigIndex;
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std::vector<int32_t> mPassingConfigIndices;
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};
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} // namespace kernels
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} // namespace tensorrt_llm
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