mirror of
https://github.com/NVIDIA/TensorRT-LLM.git
synced 2026-01-22 11:42:41 +08:00
fa3879629e
- Adds BatchedGemm cubins and the respective call interface from TensorRT-LLM Generator. - Refactors TRT-LLM Gen MoE runner to call to BMM interface - The accuracy is verified for DeepSeek R1 FP4 Signed-off-by: Nikita Korobov <nkorobov@nvidia.com>
75 lines
2.9 KiB
C++
75 lines
2.9 KiB
C++
/*
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* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <cuda.h>
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#include <optional>
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#include "tensorrt_llm/kernels/trtllmGenKernels/common/Dtype.h"
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#include "trtllmGen_bmm_export/trtllm/gen/DtypeDecl.h"
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namespace tensorrt_llm
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{
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namespace kernels
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{
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struct TrtllmGenBatchedGemmRunnerOptions
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{
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trtllm::gen::Dtype eltType;
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trtllm::gen::Dtype outputType;
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bool deepSeekFp8{false};
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bool fusedAct{false};
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bool routeAct{false};
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bool staticBatch{false};
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bool transposeMmaOutput{false};
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int32_t tileSize{8};
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int32_t epilogueTileM{128};
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};
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class TrtllmGenBatchedGemmRunner
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{
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public:
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explicit TrtllmGenBatchedGemmRunner(TrtllmGenBatchedGemmRunnerOptions const& options);
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[[nodiscard]] size_t getWorkspaceSizeInBytes(int32_t m, int32_t n, int32_t k,
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std::vector<int32_t> const& batchedTokens, int32_t numTokens, int32_t numBatches, int32_t maxNumCtasInBatchDim);
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void run(int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,
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int32_t numBatches, int32_t maxNumCtasInBatchDim, void const* a, void const* sfA, void const* b,
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void const* sfB, void const* perTokensSfA, void const* perTokensSfB, float const* scaleC,
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float const* scaleGateC, void* c, void* outSfC, int32_t const* routeMap, int32_t const* totalNumPaddedTokens,
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int32_t const* ctaIdxXyToBatchIdx, int32_t const* ctaIdxXyToMnLimit, int32_t const* numNonExitingCtas,
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void* workspace, CUstream stream, int device);
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void run(int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, void const* a, void const* sfA,
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void const* b, void const* sfB, void* c, void* outSfC, void* workspace, CUstream stream, int device);
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void run(int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, void const* a, void const* b,
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float const* scaleC, float const* scaleGateC, void* c, void* workspace, CUstream stream, int device);
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private:
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void selectGemmConfig(int32_t m, int32_t n, int32_t k, std::vector<int32_t> const& batchedTokens, int32_t numTokens,
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int32_t numBatches, int32_t maxNumCtasInBatchDim);
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private:
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TrtllmGenBatchedGemmRunnerOptions mOptions;
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std::optional<int> mSelectedConfigIndex;
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std::vector<int32_t> mPassingConfigIndices;
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};
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} // namespace kernels
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} // namespace tensorrt_llm
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