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https://github.com/NVIDIA/TensorRT-LLM.git
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ed887940d4
Replace libtensorrt_llm_nvrtc_wrapper.so with its source code, which consists of two parts: 1. NVRTC glue code 2. XQA kernel code During TensorRT-LLM build, XQA kernel code is embedded as C++ arries via gen_cpp_header.py and passed to NVRTC for JIT compilation. Signed-off-by: Ming Wei <2345434+ming-wei@users.noreply.github.com>
57 lines
2.7 KiB
Plaintext
57 lines
2.7 KiB
Plaintext
#include <vector_types.h>
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extern "C"
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{
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/*
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* Rounding mode modifiers:
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* _rn : round to nearest even (default)
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* _rm : round towards negative infinity
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* _rp : round towards positive infinity
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* _rz : round towards zero
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*
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* _ftz : flush denormalized values to zero
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*/
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/*
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* FFMA2 - fused multiply-add
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*/
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__device__ float2 __nv_ptx_builtin_ocg_ffma2(float2 a, float2 b, float2 c);
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__device__ float2 __nv_ptx_builtin_ocg_ffma2_rn(float2 a, float2 b, float2 c);
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__device__ float2 __nv_ptx_builtin_ocg_ffma2_rm(float2 a, float2 b, float2 c);
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__device__ float2 __nv_ptx_builtin_ocg_ffma2_rp(float2 a, float2 b, float2 c);
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__device__ float2 __nv_ptx_builtin_ocg_ffma2_rz(float2 a, float2 b, float2 c);
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__device__ float2 __nv_ptx_builtin_ocg_ffma2_ftz(float2 a, float2 b, float2 c);
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__device__ float2 __nv_ptx_builtin_ocg_ffma2_ftz_rn(float2 a, float2 b, float2 c);
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__device__ float2 __nv_ptx_builtin_ocg_ffma2_ftz_rm(float2 a, float2 b, float2 c);
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__device__ float2 __nv_ptx_builtin_ocg_ffma2_ftz_rp(float2 a, float2 b, float2 c);
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__device__ float2 __nv_ptx_builtin_ocg_ffma2_ftz_rz(float2 a, float2 b, float2 c);
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/*
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* FADD2 - add
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*/
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__device__ float2 __nv_ptx_builtin_ocg_fadd2(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fadd2_rn(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fadd2_rm(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fadd2_rp(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fadd2_rz(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fadd2_ftz(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fadd2_ftz_rn(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fadd2_ftz_rm(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fadd2_ftz_rp(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fadd2_ftz_rz(float2 a, float2 b);
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/*
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* FMUL2 - multiply
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*/
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__device__ float2 __nv_ptx_builtin_ocg_fmul2(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fmul2_rn(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fmul2_rm(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fmul2_rp(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fmul2_rz(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fmul2_ftz(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fmul2_ftz_rn(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fmul2_ftz_rm(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fmul2_ftz_rp(float2 a, float2 b);
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__device__ float2 __nv_ptx_builtin_ocg_fmul2_ftz_rz(float2 a, float2 b);
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}
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