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https://github.com/NVIDIA/TensorRT-LLM.git
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101 lines
3.7 KiB
C++
101 lines
3.7 KiB
C++
/*
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* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "tensorrt_llm/common/opUtils.h"
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#include "tensorrt_llm/kernels/dsv3MinLatencyKernels/dsv3FusedAGemm.h"
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#include "tensorrt_llm/runtime/torchUtils.h"
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#include "tensorrt_llm/thop/cublasScaledMM.h"
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namespace th = torch;
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namespace tl = tensorrt_llm;
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namespace tk = tensorrt_llm::kernels;
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TRTLLM_NAMESPACE_BEGIN
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namespace torch_ext
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{
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th::Tensor dsv3_fused_a_gemm_op(th::Tensor const& mat_a, th::Tensor const& mat_b, std::optional<at::Tensor> const& bias,
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std::optional<c10::ScalarType> const& out_dtype)
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{
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int const num_tokens = mat_a.sizes()[0];
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int const hd_in = mat_a.sizes()[1];
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int const hd_out = mat_b.sizes()[1];
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// auto const out_dtype_ = out_dtype.value_or(mat_a.scalar_type());
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auto const out_dtype_ = out_dtype.value_or(mat_a.scalar_type());
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auto const data_type = mat_a.scalar_type();
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constexpr int kHdIn = 7168;
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constexpr int kHdOut = 2112;
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std::vector<int64_t> output_size = {num_tokens, hd_out};
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th::Tensor out = th::empty(output_size, mat_a.options().dtype(out_dtype_));
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TORCH_CHECK(mat_a.dim() == 2 && mat_b.dim() == 2);
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TORCH_CHECK(mat_a.strides()[1] == 1 && out.strides()[1] == 1); // Row-major
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TORCH_CHECK(mat_b.strides()[0] == 1); // Column-major
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TORCH_CHECK(!bias.has_value(), "bias is not support yet");
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auto const sm = tensorrt_llm::common::getSMVersion();
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if (sm >= 90)
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{
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bool use_custom_kernel = false;
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if (num_tokens >= 1 && num_tokens <= 16 && hd_in == kHdIn && hd_out == kHdOut && data_type == torch::kBFloat16
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&& out_dtype_ == torch::kBFloat16)
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{
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use_custom_kernel = true;
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}
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if (use_custom_kernel)
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{
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auto stream = at::cuda::getCurrentCUDAStream(mat_a.get_device());
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if (num_tokens <= 8)
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{
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tk::dsv3MinLatencyKernels::invokeFusedAGemm<__nv_bfloat16, kHdIn, kHdOut, 8>(
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reinterpret_cast<__nv_bfloat16*>(out.mutable_data_ptr()),
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reinterpret_cast<__nv_bfloat16 const*>(mat_a.data_ptr()),
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reinterpret_cast<__nv_bfloat16 const*>(mat_b.data_ptr()), num_tokens, stream);
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}
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else
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{
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tk::dsv3MinLatencyKernels::invokeFusedAGemm<__nv_bfloat16, kHdIn, kHdOut, 16>(
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reinterpret_cast<__nv_bfloat16*>(out.mutable_data_ptr()),
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reinterpret_cast<__nv_bfloat16 const*>(mat_a.data_ptr()),
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reinterpret_cast<__nv_bfloat16 const*>(mat_b.data_ptr()), num_tokens, stream);
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}
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}
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else
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{
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cublas_mm_out(mat_a, mat_b, bias, out);
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}
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}
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else
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{
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cublas_mm_out(mat_a, mat_b, bias, out);
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}
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return out;
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}
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} // namespace torch_ext
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TRTLLM_NAMESPACE_END
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TORCH_LIBRARY_FRAGMENT(trtllm, m)
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{
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m.def("dsv3_fused_a_gemm_op(Tensor mat_a, Tensor mat_b, Tensor? bias, ScalarType? out_dtype) -> (Tensor out)");
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}
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TORCH_LIBRARY_IMPL(trtllm, CUDA, m)
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{
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m.impl("dsv3_fused_a_gemm_op", &tensorrt_llm::torch_ext::dsv3_fused_a_gemm_op);
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}
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