mirror of
https://github.com/NVIDIA/TensorRT-LLM.git
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683 lines
26 KiB
Python
683 lines
26 KiB
Python
# SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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import ctypes
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import os
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import platform
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import sys
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from dataclasses import dataclass
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from typing import List, Optional, Union
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import pynvml
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import torch
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try:
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from cuda.bindings import driver as cuda
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except ImportError:
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from cuda import cuda
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from ._dlpack_utils import pack_strided_memory
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from ._utils import mpi_comm
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from .logger import logger
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from .mapping import Mapping
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def _check_cu_result(cu_func_ret):
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if isinstance(cu_func_ret, tuple):
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cu_result, *others = cu_func_ret
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if cu_result != cuda.CUresult.CUDA_SUCCESS:
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raise RuntimeError(cu_result)
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if len(others) == 1:
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return others[0]
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elif len(others) > 1:
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return tuple(others)
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else:
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return None
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else:
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if cu_func_ret != cuda.CUresult.CUDA_SUCCESS:
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raise RuntimeError(cu_func_ret)
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return None
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class MnnvlMemory:
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"""MNNVL memory management for tensor parallel (TP) operations."""
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# Shared across all subclasses (global/device state).
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initialized: bool = False
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allocation_granularity: int = 0
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fabric_page_size: int = 1 << 29 # 512 MB.
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dev_id: int = None
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# Per-class state attributes. These will be auto-initialized for each subclass
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# to avoid polluting the parent class's state. Use callable (e.g., dict) for mutable defaults.
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_per_class_attrs = {
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"current_mem_offset": 0,
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"current_rank_stride": 0, # stride for ranks and also address space size.
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"current_start_address": 0,
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"comm": None, # MPI communicator.
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"allocated_map": dict, # callable for fresh dict.
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"address_refcnt": dict, # callable for fresh dict.
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}
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# Initialize per-class state for the base class.
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current_mem_offset: int = 0
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current_rank_stride: int = 0
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current_start_address: int = 0
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comm = None
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allocated_map = {}
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address_refcnt = {}
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def __init_subclass__(cls, **kwargs):
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"""Auto-initialize per-class attributes for each subclass to avoid sharing state with parent."""
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super().__init_subclass__(**kwargs)
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for attr, default in cls._per_class_attrs.items():
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if callable(default):
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setattr(cls, attr, default()) # e.g., dict() creates a fresh dict.
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else:
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setattr(cls, attr, default)
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def __init__(self, mapping: Mapping, size: int):
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self.mapping = mapping
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self.segment_size = size
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self.ptr, self.rank_stride = type(self).open_mnnvl_memory(self.mapping, size)
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def __del__(self):
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if not sys.is_finalizing():
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if hasattr(self, "ptr"):
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type(self).close_mnnvl_memory(self.ptr)
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def as_torch_strided_tensor(self, dtype):
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num_segments = type(self).comm.Get_size()
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return pack_strided_memory(
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self.ptr, self.segment_size, self.rank_stride, num_segments, dtype, MnnvlMemory.dev_id
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)
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@staticmethod
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def initialize():
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if not MnnvlMemory.initialized:
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# use a dummy torch CUDA tensor to trigger CUDA context initialization
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_ = torch.empty(1, device="cuda")
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# ensure nvml is initialized.
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try:
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pynvml.nvmlDeviceGetCount()
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except pynvml.NVMLError_Uninitialized:
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pynvml.nvmlInit()
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MnnvlMemory.initialized = True
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@classmethod
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def get_comm(cls, mapping: Mapping):
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"""Get TP-based communicator (ranks grouped by PP+CP+MOE_TP, ordered by TP rank)."""
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if cls.comm is not None:
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return cls.comm
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comm = mpi_comm().Split(
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(mapping.pp_rank * mapping.cp_size + mapping.cp_rank) * mapping.moe_tp_size
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+ mapping.moe_tp_rank,
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mapping.tp_rank,
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)
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cls.comm = comm
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return comm
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@staticmethod
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def get_allocation_prop(dev_id: int):
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location = cuda.CUmemLocation()
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location.type = cuda.CUmemLocationType.CU_MEM_LOCATION_TYPE_DEVICE
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location.id = dev_id
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allocation_prop = cuda.CUmemAllocationProp()
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allocation_prop.type = cuda.CUmemAllocationType.CU_MEM_ALLOCATION_TYPE_PINNED
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# TODO: We differentiate FABRIC for GB200 (aarch64) and POSIX_FILE_DESCRIPTOR for BB200 (x86_64).
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# May need to find a better way to handle this.
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arch = platform.machine().lower()
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is_on_aarch64 = "aarch64" in arch
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if is_on_aarch64:
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allocation_prop.requestedHandleTypes = (
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cuda.CUmemAllocationHandleType.CU_MEM_HANDLE_TYPE_FABRIC
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)
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else:
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allocation_prop.requestedHandleTypes = (
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cuda.CUmemAllocationHandleType.CU_MEM_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR
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)
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allocation_prop.location = location
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return allocation_prop
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@staticmethod
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def get_allocation_granularity(dev_id: int):
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if MnnvlMemory.allocation_granularity != 0:
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return MnnvlMemory.allocation_granularity
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allocation_prop = MnnvlMemory.get_allocation_prop(dev_id)
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option = cuda.CUmemAllocationGranularity_flags(
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cuda.CUmemAllocationGranularity_flags.CU_MEM_ALLOC_GRANULARITY_RECOMMENDED
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)
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granularity = _check_cu_result(
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cuda.cuMemGetAllocationGranularity(prop=allocation_prop, option=option)
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)
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MnnvlMemory.allocation_granularity = granularity
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return MnnvlMemory.allocation_granularity
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@classmethod
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def new_mnnvl_memory_address(cls, mapping: Mapping, size: int):
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page_count = (size + MnnvlMemory.fabric_page_size - 1) // MnnvlMemory.fabric_page_size
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current_rank_stride = page_count * MnnvlMemory.fabric_page_size
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logger.info(f"[{cls.__name__}] creating address with stride={current_rank_stride}")
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comm = cls.get_comm(mapping)
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comm_size = comm.Get_size()
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address_size = current_rank_stride * comm_size
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ptr = _check_cu_result(
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cuda.cuMemAddressReserve(address_size, MnnvlMemory.fabric_page_size, 0, 0)
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)
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cls.current_start_address = int(ptr)
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cls.current_rank_stride = current_rank_stride
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cls.current_mem_offset = 0
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@classmethod
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def open_mnnvl_memory(cls, mapping: Mapping, size: int):
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# Ensure MnnvlMemory is initialized (for dev_id and allocation_granularity)
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MnnvlMemory.initialize()
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dev = _check_cu_result(cuda.cuCtxGetDevice())
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dev_id = int(dev)
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if MnnvlMemory.dev_id is None:
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MnnvlMemory.dev_id = dev_id
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assert dev_id == MnnvlMemory.dev_id, (
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f"Different dev_id found dev_id={dev_id} but MnnvlMemory.dev_id={MnnvlMemory.dev_id}"
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)
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comm = cls.get_comm(mapping)
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comm_rank = comm.Get_rank()
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comm_size = comm.Get_size()
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all_rank_allocate_sizes = comm.allgather(size)
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assert len(all_rank_allocate_sizes) == comm_size
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assert all(x == size for x in all_rank_allocate_sizes), "Not all rank allocating same size."
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granularity = MnnvlMemory.get_allocation_granularity(dev_id)
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aligned_size = (size + granularity - 1) // granularity * granularity
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if cls.current_mem_offset + aligned_size > cls.current_rank_stride:
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cls.new_mnnvl_memory_address(mapping, aligned_size)
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assert cls.current_mem_offset + aligned_size <= cls.current_rank_stride
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allocation_prop = MnnvlMemory.get_allocation_prop(dev_id)
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allocated_mem_handle = _check_cu_result(
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cuda.cuMemCreate(aligned_size, allocation_prop, flags=0)
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)
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exported_fabric_handle = _check_cu_result(
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cuda.cuMemExportToShareableHandle(
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allocated_mem_handle, allocation_prop.requestedHandleTypes, 0
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)
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)
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if (
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allocation_prop.requestedHandleTypes
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== cuda.CUmemAllocationHandleType.CU_MEM_HANDLE_TYPE_FABRIC
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):
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all_handles_data = comm.allgather(exported_fabric_handle.data)
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else:
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all_handles_data = comm.allgather(exported_fabric_handle)
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all_pids = comm.allgather(os.getpid())
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libc = ctypes.CDLL(None, use_errno=True)
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syscall = libc.syscall
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SYS_pidfd_open = 434
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SYS_pidfd_getfd = 438
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pidfds = []
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for i, pid in enumerate(all_pids):
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pidfd = syscall(SYS_pidfd_open, pid, 0)
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if pidfd < 0:
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err = ctypes.get_errno()
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raise RuntimeError(
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f"pidfd_open({pid}) failed with errno {err}: {os.strerror(err)}"
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)
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pidfds.append(pidfd)
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remote_fds = []
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for i, (pidfd, fd) in enumerate(zip(pidfds, all_handles_data)):
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remote_fd = syscall(SYS_pidfd_getfd, pidfd, fd, 0)
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if remote_fd < 0:
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err = ctypes.get_errno()
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error_msg = f"pidfd_getfd(pidfd={pidfd}, fd={fd}) failed with errno {err}: {os.strerror(err)}."
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if err == 1: # EPERM
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error_msg += (
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" Permission denied. If running in a container, try adding --cap-add=SYS_PTRACE "
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"to your docker run command."
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)
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else:
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error_msg += " This may be due to kernel version (requires Linux 5.6+)."
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raise RuntimeError(error_msg)
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remote_fds.append(remote_fd)
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all_handles_data = remote_fds
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# all_handles_data like b'\x00\x00\x00 \x00\x00\x00\x00\x8f\xec\x02\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\t\x00\x00\x00\x00\x00\x1d\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00' # noqa: E501
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# can use buf = memoryview(data) to import if using plain buffer for data.
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madesc = cuda.CUmemAccessDesc()
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madesc.location = allocation_prop.location
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madesc.flags = cuda.CUmemAccess_flags.CU_MEM_ACCESS_FLAGS_PROT_READWRITE
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mem_handles = [None] * comm_size
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for i, remote_handle_data in enumerate(all_handles_data):
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rank_ptr = (
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cls.current_start_address + cls.current_rank_stride * i + cls.current_mem_offset
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)
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if i == comm_rank:
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# Local memory mapping
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mem_handles[i] = allocated_mem_handle
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_check_cu_result(cuda.cuMemMap(rank_ptr, aligned_size, 0, allocated_mem_handle, 0))
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else:
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# Fabric memory mapping
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imported_mem_handle = _check_cu_result(
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cuda.cuMemImportFromShareableHandle(
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remote_handle_data, allocation_prop.requestedHandleTypes
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)
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)
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mem_handles[i] = imported_mem_handle
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_check_cu_result(cuda.cuMemMap(rank_ptr, aligned_size, 0, imported_mem_handle, 0))
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_check_cu_result(cuda.cuMemSetAccess(rank_ptr, aligned_size, [madesc], 1))
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ptr = cls.current_start_address + cls.current_mem_offset
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stride = cls.current_rank_stride
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cls.allocated_map[ptr] = (
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mapping,
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aligned_size,
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mem_handles,
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cls.current_start_address,
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cls.current_rank_stride,
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cls.current_mem_offset,
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)
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cls.address_refcnt[cls.current_start_address] = (
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cls.address_refcnt.get(cls.current_start_address, 0) + 1
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)
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cls.current_mem_offset += aligned_size
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return ptr, stride
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@classmethod
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def close_mnnvl_memory(cls, ptr: int):
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mapping, aligned_size, mem_handles, start_address, rank_stride, address_offset = (
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cls.allocated_map.pop(ptr)
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)
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comm = cls.get_comm(mapping)
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comm_size = comm.Get_size()
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for i in range(comm_size):
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rank_ptr = start_address + i * rank_stride + address_offset
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_check_cu_result(cuda.cuMemUnmap(rank_ptr, aligned_size))
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_check_cu_result(cuda.cuMemRelease(mem_handles[i]))
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cls.address_refcnt[start_address] -= 1
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if cls.address_refcnt[start_address] == 0:
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cls.address_refcnt.pop(start_address)
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device_ptr = cuda.CUdeviceptr(start_address)
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_check_cu_result(cuda.cuMemAddressFree(device_ptr, comm_size * rank_stride))
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if start_address == cls.current_start_address:
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cls.current_start_address = 0
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cls.current_rank_stride = 0
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cls.current_mem_offset = 0
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@staticmethod
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def support_nvlink(need_all_up: bool = True):
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dev_id = torch.cuda.current_device()
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handle = pynvml.nvmlDeviceGetHandleByIndex(dev_id)
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link_count = pynvml.NVML_NVLINK_MAX_LINKS
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active_links = 0
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available_links = 0
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for link_idx in range(link_count):
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try:
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if pynvml.nvmlDeviceGetNvLinkCapability(
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handle, link_idx, pynvml.NVML_NVLINK_CAP_P2P_SUPPORTED
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):
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available_links += 1
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is_active = pynvml.nvmlDeviceGetNvLinkState(handle, link_idx)
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if is_active:
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active_links += 1
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except pynvml.NVMLError_NotSupported:
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continue
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return (
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active_links == available_links and available_links > 0
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if need_all_up
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else available_links > 0
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)
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@staticmethod
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def supports_mnnvl() -> bool:
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# TODO:
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# We check if it has all NVLink up now.
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# But it is not equivalent to MNNVL support.
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# May need better support check.
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support_nvlink_and_all_up = MnnvlMemory.support_nvlink(True)
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return support_nvlink_and_all_up
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class HelixCpMnnvlMemory(MnnvlMemory):
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"""MNNVL memory management for Helix context parallel (CP) operations.
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Per-class state (current_mem_offset, comm, allocated_map, etc.) is automatically
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initialized via __init_subclass__ in the parent class, ensuring this class has
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its own isolated state separate from MnnvlMemory.
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"""
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@classmethod
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def get_comm(cls, mapping: Mapping):
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"""Get CP-based communicator (ranks grouped by PP+TP+MOE_TP, ordered by CP rank)."""
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if cls.comm is not None:
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return cls.comm
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comm = mpi_comm().Split(
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mapping.pp_rank * mapping.tp_size + mapping.tp_rank,
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mapping.cp_rank,
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)
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cls.comm = comm
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return comm
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def init_helix_cp_comm(mapping: Mapping) -> None:
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"""Pre-initialize the Helix CP communicator.
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This function MUST be called during model initialization when all ranks
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are synchronized (before any PP pipeline divergence). The MPI Split operation
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is collective and requires all ranks in the communicator to participate.
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In PP (pipeline parallel) mode, different PP stages execute different parts
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of the model at different times. If the communicator is initialized lazily
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during the first forward pass, ranks in different PP stages may not reach
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the Split operation at the same time, causing a deadlock.
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Args:
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mapping: The mapping object containing parallelism configuration.
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"""
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if mapping.has_cp_helix() and not mapping.cp_config.get("use_nccl_for_alltoall", True):
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HelixCpMnnvlMemory.get_comm(mapping)
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@dataclass
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class MoEAlltoallInfo:
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local_gather_indices: torch.Tensor
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send_rank_count_cumsum: torch.Tensor
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send_rank_local_indices: torch.Tensor
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recv_rank_count_cumsum: torch.Tensor
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recv_rank_local_indices: torch.Tensor
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backward_recv_rank_local_indices: torch.Tensor
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local_token_allocation_count: int
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class MnnvlMoe:
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moe_workspace: MnnvlMemory = None
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moe_prepare_workspace: MnnvlMemory = None
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moe_workspace_tensor: torch.Tensor = None
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moe_prepare_workspace_tensor: torch.Tensor = None
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moe_mapping: Mapping = None
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@staticmethod
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def get_moe_workspaces(mapping: Mapping):
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if MnnvlMoe.moe_workspace is not None:
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assert mapping == MnnvlMoe.moe_mapping, "only one moe mapping supported now"
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return MnnvlMoe.moe_workspace_tensor
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MnnvlMoe.moe_mapping = mapping
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workspace_size_per_rank = torch.ops.trtllm.get_moe_commworkspace_size_per_rank(
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mapping.moe_ep_size
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)
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MnnvlMoe.moe_workspace = MnnvlMemory(mapping, workspace_size_per_rank)
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MnnvlMoe.moe_workspace_tensor = MnnvlMoe.moe_workspace.as_torch_strided_tensor(torch.uint64)
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torch.ops.trtllm.moe_initialize_workspace(
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MnnvlMoe.moe_workspace_tensor, mapping.moe_ep_rank, mapping.moe_ep_size
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)
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torch.cuda.synchronize()
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MnnvlMoe.moe_workspace.comm.barrier()
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return MnnvlMoe.moe_workspace_tensor
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@staticmethod
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def get_moe_prepare_workspace(mapping: Mapping):
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if MnnvlMoe.moe_prepare_workspace_tensor is not None:
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assert mapping == MnnvlMoe.moe_mapping, "only one moe mapping supported now"
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return MnnvlMoe.moe_prepare_workspace_tensor
|
|
workspace_size_per_rank = torch.ops.trtllm.get_moe_prepare_workspace_size_per_rank(
|
|
mapping.moe_ep_size
|
|
)
|
|
MnnvlMoe.moe_prepare_workspace = MnnvlMemory(mapping, workspace_size_per_rank)
|
|
MnnvlMoe.moe_prepare_workspace_tensor = (
|
|
MnnvlMoe.moe_prepare_workspace.as_torch_strided_tensor(torch.uint64)
|
|
)
|
|
return MnnvlMoe.moe_prepare_workspace_tensor
|
|
|
|
@staticmethod
|
|
def compute_target_rank_id(
|
|
token_selected_experts: torch.Tensor, expert_count: int, ep_size: int
|
|
):
|
|
assert expert_count % ep_size == 0, "expert_count should be divisible by ep_size"
|
|
expert_per_rank = expert_count // ep_size
|
|
token_target_rank_ids = token_selected_experts // expert_per_rank
|
|
return token_target_rank_ids
|
|
|
|
@staticmethod
|
|
def mnnvl_moe_alltoallv_prepare_without_allgather(
|
|
expert_ids: torch.Tensor,
|
|
expert_statics: Optional[torch.Tensor],
|
|
workspace: torch.Tensor,
|
|
max_token_count_per_rank: int,
|
|
ep_rank: int,
|
|
ep_size: int,
|
|
expert_count: int,
|
|
slot_count: int,
|
|
top_k: int,
|
|
):
|
|
(
|
|
local_send_rank_count_cumsum,
|
|
local_send_rank_indices,
|
|
local_recv_rank_count_cumsum,
|
|
local_recv_rank_indices,
|
|
backward_local_recv_rank_indices,
|
|
gathered_expert_statics,
|
|
) = torch.ops.trtllm.mnnvl_moe_alltoallv_prepare_without_allgather(
|
|
expert_ids,
|
|
expert_statics,
|
|
workspace,
|
|
max_token_count_per_rank,
|
|
ep_rank,
|
|
ep_size,
|
|
expert_count,
|
|
slot_count,
|
|
top_k,
|
|
)
|
|
|
|
local_token_allocation_count = max_token_count_per_rank * ep_size
|
|
# Looks like we don't need this.
|
|
local_gather_indices = None
|
|
|
|
alltoall_info = MoEAlltoallInfo(
|
|
local_gather_indices,
|
|
local_send_rank_count_cumsum,
|
|
local_send_rank_indices,
|
|
local_recv_rank_count_cumsum,
|
|
local_recv_rank_indices,
|
|
backward_local_recv_rank_indices,
|
|
local_token_allocation_count,
|
|
)
|
|
|
|
return alltoall_info, gathered_expert_statics
|
|
|
|
@staticmethod
|
|
def mnnvl_moe_expert_static_allgather(
|
|
expert_ids: torch.Tensor,
|
|
workspace: torch.Tensor,
|
|
ep_rank: int,
|
|
ep_size: int,
|
|
expert_count: int,
|
|
):
|
|
gathered_expert_ids = torch.ops.trtllm.mnnvl_moe_expert_static_allgather(
|
|
expert_ids, workspace, ep_rank, ep_size, expert_count
|
|
)
|
|
return gathered_expert_ids
|
|
|
|
@staticmethod
|
|
def mnnvl_moe_alltoallv_prepare(
|
|
gathered_target_rank_ids: torch.Tensor,
|
|
real_rank_token_count_cumsum: Optional[torch.Tensor],
|
|
gathered_expert_ids: torch.Tensor,
|
|
gathered_scales: Optional[torch.Tensor],
|
|
max_token_count_per_rank: int,
|
|
expert_count: int,
|
|
top_k: int,
|
|
ep_rank: int,
|
|
ep_size: int,
|
|
):
|
|
(
|
|
local_gather_indices,
|
|
send_rank_count_cumsum,
|
|
send_rank_local_indices,
|
|
recv_rank_count_cumsum,
|
|
recv_rank_local_indices,
|
|
backward_recv_rank_local_indices,
|
|
) = torch.ops.trtllm.moe_comm_prepare_indices(
|
|
gathered_target_rank_ids,
|
|
real_rank_token_count_cumsum,
|
|
max_token_count_per_rank,
|
|
expert_count,
|
|
top_k,
|
|
ep_rank,
|
|
ep_size,
|
|
)
|
|
|
|
local_token_allocation_count = max_token_count_per_rank * ep_size
|
|
|
|
local_expert_ids = torch.empty(
|
|
local_token_allocation_count, top_k, dtype=torch.int32, device=torch.device("cuda")
|
|
)
|
|
if gathered_scales is None:
|
|
local_scales = None
|
|
else:
|
|
local_scales = torch.empty(
|
|
local_token_allocation_count,
|
|
top_k,
|
|
dtype=torch.float32,
|
|
device=torch.device("cuda"),
|
|
)
|
|
|
|
torch.ops.trtllm.moe_local_gather(
|
|
recv_rank_count_cumsum,
|
|
local_gather_indices,
|
|
gathered_expert_ids,
|
|
gathered_scales,
|
|
local_expert_ids,
|
|
local_scales,
|
|
max_token_count_per_rank,
|
|
expert_count,
|
|
top_k,
|
|
ep_rank,
|
|
ep_size,
|
|
)
|
|
|
|
alltoall_info = MoEAlltoallInfo(
|
|
local_gather_indices,
|
|
send_rank_count_cumsum,
|
|
send_rank_local_indices,
|
|
recv_rank_count_cumsum,
|
|
recv_rank_local_indices,
|
|
backward_recv_rank_local_indices,
|
|
local_token_allocation_count,
|
|
)
|
|
return alltoall_info, local_expert_ids, local_scales
|
|
|
|
@staticmethod
|
|
def mnnvl_moe_alltoallv(
|
|
x: Union[torch.Tensor, List[Optional[torch.Tensor]]],
|
|
alltoall_info: MoEAlltoallInfo,
|
|
workspace: torch.Tensor,
|
|
ep_rank: int,
|
|
ep_size: int,
|
|
) -> Union[torch.Tensor, List[Optional[torch.Tensor]]]:
|
|
# Convert single tensor to list for unified handling
|
|
is_single_tensor = not isinstance(x, list)
|
|
if is_single_tensor:
|
|
assert x.dim() == 2, "only 2D tensor supported, please reshape."
|
|
x = [x]
|
|
|
|
assert len(x) > 0, "Empty tensor list not supported"
|
|
|
|
# Filter out None values
|
|
valid_list = [tensor is not None for tensor in x]
|
|
valid_tensors = [tensor for tensor in x if tensor is not None]
|
|
|
|
if len(valid_tensors) == 0:
|
|
# All tensors are None, return list of None
|
|
result = [None] * len(x)
|
|
else:
|
|
first_dim = None
|
|
for tensor in valid_tensors:
|
|
# Validate dimensions of valid tensors
|
|
assert tensor.dim() == 2, "only 2D tensor supported, please reshape."
|
|
if first_dim is None:
|
|
first_dim = tensor.shape[0]
|
|
else:
|
|
assert tensor.shape[0] == first_dim, (
|
|
f"All tensors must have the same first dimension, got {tensor.shape[0]} vs {first_dim}"
|
|
)
|
|
|
|
# Process only valid tensors
|
|
output_tensors = torch.ops.trtllm.moe_comm(
|
|
valid_tensors,
|
|
alltoall_info.send_rank_count_cumsum,
|
|
alltoall_info.send_rank_local_indices,
|
|
alltoall_info.recv_rank_count_cumsum,
|
|
alltoall_info.recv_rank_local_indices,
|
|
workspace,
|
|
alltoall_info.local_token_allocation_count,
|
|
ep_rank,
|
|
ep_size,
|
|
)
|
|
|
|
# Restore None positions in output
|
|
idx = 0
|
|
result = []
|
|
for is_valid in valid_list:
|
|
if is_valid:
|
|
result.append(output_tensors[idx])
|
|
idx += 1
|
|
else:
|
|
result.append(None)
|
|
|
|
# If input was a single tensor, return a single tensor
|
|
if is_single_tensor:
|
|
result = result[0]
|
|
|
|
return result
|
|
|
|
@staticmethod
|
|
def mnnvl_moe_alltoallv_combine(
|
|
x: torch.Tensor,
|
|
alltoall_info: MoEAlltoallInfo,
|
|
workspace: torch.Tensor,
|
|
ep_rank: int,
|
|
ep_size: int,
|
|
top_k: int,
|
|
token_count: int,
|
|
use_low_precision_combine: bool = False,
|
|
do_reduce: bool = True,
|
|
):
|
|
assert x.dim() == 2, "2D tensor supported, please reshape."
|
|
output_tensors = torch.ops.trtllm.moe_comm(
|
|
[x],
|
|
alltoall_info.recv_rank_count_cumsum,
|
|
alltoall_info.recv_rank_local_indices,
|
|
alltoall_info.send_rank_count_cumsum,
|
|
alltoall_info.backward_recv_rank_local_indices,
|
|
workspace,
|
|
token_count * top_k,
|
|
ep_rank,
|
|
ep_size,
|
|
[True],
|
|
use_low_precision_combine,
|
|
)
|
|
output_tensor = output_tensors[0].reshape(token_count, top_k, x.shape[1])
|
|
if do_reduce:
|
|
return torch.sum(output_tensor, dim=1, keepdim=False)
|
|
else:
|
|
return output_tensor
|