mirror of
https://github.com/NVIDIA/TensorRT-LLM.git
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f8dd494536
Signed-off-by: Matthias Jouanneaux <mjoux@nvidia.com> Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com> Co-authored-by: Zheyu Fu <zheyuf@nvidia.com>
131 lines
4.2 KiB
C++
131 lines
4.2 KiB
C++
/*
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* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "tensorrt_llm/common/opUtils.h"
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#include "tensorrt_llm/runtime/torchUtils.h"
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#include "tensorrt_llm/runtime/utils/mpiUtils.h"
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#include <NvInferRuntime.h>
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#include <c10/cuda/CUDAStream.h>
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#include <cassert>
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#include <set>
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#include <string>
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#include <torch/extension.h>
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#include <vector>
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#if ENABLE_MULTI_DEVICE
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#include <nccl.h>
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#endif // ENABLE_MULTI_DEVICE
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namespace torch_ext
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{
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#if ENABLE_MULTI_DEVICE
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namespace
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{
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class AllToAllHelixOp
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{
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public:
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AllToAllHelixOp(std::set<int> group)
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: mGroup(std::move(group))
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{
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}
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~AllToAllHelixOp() = default;
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int initialize()
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{
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TLLM_LOG_TRACE("%s start for rank %d", __PRETTY_FUNCTION__, COMM_SESSION.getRank());
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mNcclComm = getComm(mGroup);
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TLLM_CHECK_WITH_INFO(mGroup.size() > 0, "group size should be greater than 0");
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TLLM_LOG_TRACE("%s stop for rank %d", __PRETTY_FUNCTION__, COMM_SESSION.getRank());
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return 0;
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}
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std::vector<torch::Tensor> run(torch::TensorList input_list, torch::optional<int64_t> num_lists)
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{
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TLLM_CHECK_WITH_INFO(mNcclComm.get() != nullptr, "mNcclComm should be initialized before used");
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auto num_lists_ = static_cast<int>(num_lists.value_or(1));
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auto num_ranks = static_cast<int>(mGroup.size());
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// note: ensures that input_list size > 0
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TLLM_CHECK_WITH_INFO(static_cast<int>(input_list.size()) == num_ranks * num_lists_,
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"input_list size should be equal to group size * num_lists");
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for (auto const& input : input_list)
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{
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TORCH_CHECK(input.is_contiguous(), "input must be contiguous");
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}
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std::vector<torch::Tensor> output_list(static_cast<size_t>(num_lists_));
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auto stream = at::cuda::getCurrentCUDAStream(input_list[0].get_device());
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ncclGroupStart();
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for (int il = 0; il < num_lists_; ++il)
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{
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auto off = il * num_ranks;
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auto output_shape = input_list[off].sizes().vec();
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output_shape.insert(output_shape.begin(), num_ranks);
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auto output = torch::empty(output_shape, input_list[off].options());
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output_list[il] = output;
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auto type = tensorrt_llm::runtime::TorchUtils::dataType(input_list[off].scalar_type());
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auto nccl_type = (*getDtypeMap())[type];
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for (int r = 0; r < num_ranks; ++r)
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{
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auto const& input = input_list[off + r];
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ncclSend(input.data_ptr(), input.numel(), nccl_type, r, *mNcclComm, stream);
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ncclRecv(output[r].mutable_data_ptr(), output[r].numel(), nccl_type, r, *mNcclComm, stream);
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}
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}
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NCCLCHECK_THROW(ncclGroupEnd());
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return output_list;
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}
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private:
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std::set<int> mGroup;
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std::shared_ptr<ncclComm_t> mNcclComm;
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};
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} // namespace
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#endif // ENABLE_MULTI_DEVICE
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std::vector<torch::Tensor> alltoall_helix(
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torch::TensorList input_list, torch::List<int64_t> group_, torch::optional<int64_t> num_lists)
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{
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#if ENABLE_MULTI_DEVICE
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std::set<int> group;
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for (int64_t rank : group_)
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{
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group.insert(static_cast<int>(rank));
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}
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AllToAllHelixOp op(group);
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op.initialize();
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return op.run(input_list, num_lists);
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#else
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return {};
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#endif // ENABLE_MULTI_DEVICE
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}
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} // namespace torch_ext
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TORCH_LIBRARY_FRAGMENT(trtllm, m)
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{
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m.def("alltoall_helix(Tensor[] input_list, int[] group, int? num_lists) -> Tensor[]");
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}
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TORCH_LIBRARY_IMPL(trtllm, CUDA, m)
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{
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m.impl("alltoall_helix", &torch_ext::alltoall_helix);
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}
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