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nimble/transport: Fix typo in UART transport

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X-Original-Commit: 29c5182089491d76a4ab373e2e800e8ed0f71056
This commit is contained in:
Szymon Janc
2018-01-15 17:32:53 +01:00
parent efaad20099
commit 5a9801bdf8
1 changed files with 1 additions and 1 deletions
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nimble/transport/uart/src/ble_hci_uart.c
+1 -1
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@@ -1040,7 +1040,7 @@ ble_hci_uart_init(void)
acl_block_size = acl_data_length + BLE_MBUF_MEMBLOCK_OVERHEAD +
BLE_HCI_DATA_HDR_SZ;
acl_block_size = OS_ALIGN(acl_block_size, OS_ALIGNMENT);
rc = mem_malloc_mempool_ext(&ble_hci_emspi_acl_pool,
rc = mem_malloc_mempool_ext(&ble_hci_uart_acl_pool,
MYNEWT_VAL(BLE_ACL_BUF_COUNT),
acl_block_size,
"ble_hci_uart_acl_pool",